Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbSerialInterfaceEngine_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbSerialInterfaceEngine_h.v	(revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine_h.v                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSerialInterfaceEngine_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+ // Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate
+`define OVER_SAMPLE_RATE 4
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 6
+`define RESUME_WAIT_TIME 10
+`define RESUME_WAIT_TIME_MINUS1 9
+`define RESUME_LEN 20
+`define CONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd20
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates 
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf	(revision 264)
@@ -0,0 +1,587 @@
+VERSION=1.19
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FREEOID=955
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/9/2004"
+HEADER_PARAM="TITLE,SIETransmitter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 16
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 216
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 213
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 359
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 455
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 465
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 474
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 483
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 609
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 617
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 626
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 718
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 720
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 717
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 911
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_SIETX\n/22/"
+W 545 458 0 530 540 BEZIER "Transitions" | 168710,66267 156425,60534 83183,49066 70898,43333
+C 557 555 0 TEXT "Conditions" | 72988,107460 1 0 0 "USBWireRdy == 1'b1"
+A 556 555 16 TEXT "Actions" | 112553,111735 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 555 458 0 543 534 BEZIER "Transitions" | 69825,102352 80940,102469 155253,103091 166368,103208
+A 554 534 4 TEXT "Actions" | 157773,116901 1 0 0 "USBWireWEn <= 1'b0;"
+C 553 549 0 TEXT "Conditions" | 134841,94437 1 0 0 "USBWireRdy == 1'b1"
+C 552 547 0 TEXT "Conditions" | 72597,69165 1 0 0 "USBWireRdy == 1'b1"
+A 550 549 16 TEXT "Actions" | 89913,93969 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 549 458 0 534 532 BEZIER "Transitions" | 166590,101641 155007,95674 81782,81027 70199,75060
+A 548 547 16 TEXT "Actions" | 109101,76185 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 547 458 0 532 530 BEZIER "Transitions" | 71250,71190 82482,70839 157007,69015 168239,68664
+L 544 543 0 TEXT "State Labels" | 63328,102539 1 0 0 "WAIT_WIRE\n/47/"
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "SIETx"
+F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: SIETransmitter"
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "STX_CHK_ST\n/23/"
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+I 12 6 0 Builtin Reset | 22016,204762
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+L 15 16 0 TEXT "State Labels" | 115356,124706 1 0 0 "RES_ST"
+I 816 0 2 Builtin OutPort | 64372,260578 "" ""
+L 817 818 0 TEXT "Labels" | 72692,255938 1 0 0 "processTxByteRdy"
+I 818 0 2 Builtin InPort | 66692,255938 "" ""
+L 819 820 0 TEXT "Labels" | 70372,251298 1 0 0 "TxByteOut[7:0]"
+I 820 0 2 Builtin OutPort | 64372,251298 "" ""
+L 821 822 0 TEXT "Labels" | 70372,246658 1 0 0 "TxByteOutCtrl[7:0]"
+I 822 0 2 Builtin OutPort | 64372,246658 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 824 0 2 Builtin OutPort | 15604,240596 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+A 835 9 4 TEXT "Actions" | 153876,205564 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 5'h0;"
+W 574 458 0 567 543 BEZIER "Transitions" | 44298,153135 48358,141709 56556,119871 60616,108445
+A 563 530 4 TEXT "Actions" | 161517,83673 1 0 0 "USBWireWEn <= 1'b0;"
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+I 572 458 0 Builtin Entry | 44780,253519
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/5/"
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/37/"
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+A 562 532 4 TEXT "Actions" | 37965,60741 1 0 0 "USBWireWEn <= 1'b0;"
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+A 836 63 4 TEXT "Actions" | 101212,188184 1 0 0 "SIEPortTxRdy <= 1'b1;"
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+I 838 0 2 Builtin Signal | 71732,224652 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 840 0 2 Builtin Signal | 71500,220244 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[4:0]"
+I 844 0 2 Builtin Signal | 71500,215836 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 846 0 2 Builtin InPort | 125108,216932 "" ""
+I 847 0 2 Builtin InPort | 125241,221252 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 312 0 2 Builtin OutPort | 123156,255220 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 314 0 2 Builtin InPort | 125655,250603 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+I 872 360 0 Builtin Exit | 188676,86316
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+                                      42326,129670 44202,125650 52711,124511 61220,123372\
+                                      92777,123293 108857,123025
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "STX_WAIT_BYTE\n/24/"
+S 63 6 0 ELLIPSE "States" | 112744,173179 6500 6500
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 324 0 2 Builtin InPort | 126267,236303 "" ""
+I 599 489 0 Builtin Entry | 81144,219546
+I 606 489 0 Builtin Exit | 138120,51311
+W 895 224 8194 891 897 BEZIER "Transitions" | 101794,119505 95833,118125 85494,117151 81290,118312\
+                                              77086,119473 72191,126878 71751,132901 71312,138925\
+                                              74451,155618 76866,160637 79282,165657 85808,169046\
+                                              89165,169297 92522,169548 98692,166980 102143,165788
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 5'h7"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/2/"
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 890 885 0 TEXT "State Labels" | 60832,129059 1 0 0 "CHK_FIN\n/1/"
+C 889 888 0 TEXT "Conditions" | 62558,122269 1 0 0 "i == 5'h7"
+W 888 217 8193 885 221 BEZIER "Transitions" | 60935,122562 61052,115893 61713,104679 61830,98010
+W 887 217 8194 885 883 BEZIER "Transitions" | 54752,126763 48791,125383 38452,124409 34248,125570\
+                                              30044,126731 25149,134136 24709,140159 24270,146183\
+                                              27409,162876 29824,167895 32240,172915 38766,176304\
+                                              42123,176555 45480,176806 51650,174238 55101,173046
+A 886 885 4 TEXT "Actions" | 76742,138579 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 885 217 0 ELLIPSE "States" | 60832,129059 6500 6500
+L 884 883 0 TEXT "State Labels" | 60901,170112 1 0 0 "STX_WAIT_RDY\n/26/"
+S 883 217 0 ELLIPSE "States" | 60901,170112 6500 6500
+C 882 880 0 TEXT "Conditions" | 61330,163577 1 0 0 "USBWireRdy == 1'b1"
+A 881 880 16 TEXT "Actions" | 49805,157344 1 0 0 "USBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 880 217 0 883 885 BEZIER "Transitions" | 60836,163644 60774,157457 60714,141730 60652,135543
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59299,174571 47927,176730
+C 66 65 0 TEXT "Conditions" | 67688,166172 1 0 0 "SIEPortWEn == 1'b1"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+A 78 65 16 TEXT "Actions" | 54348,179673 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+                                        161730,108850 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 135270,157360\
+                                        132480,162850 129690,168340 122852,170455 118982,171355
+L 608 609 0 TEXT "State Labels" | 111818,198264 1 0 0 "PID"
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111818,198264 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114123,147554 6500 6500
+I 909 224 0 Builtin Exit | 108872,88817
+I 908 224 0 Builtin Entry | 85162,237767
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/33/"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/43/"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+                                        43361,99065 46384,95576 54928,94878 63472,94181\
+                                        94207,96080 109784,96428
+I 363 360 0 Builtin Entry | 47792,257148
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 68542,191838 89078,185356 109614,178874
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 114123,147554 1 0 0 "BYTE1"
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112740,88546 6500 6500
+L 634 626 0 TEXT "State Labels" | 112740,88546 1 0 0 "CRC"
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 636 610 0 Builtin Entry | 71380,236621
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+W 927 360 0 933 929 BEZIER "Transitions" | 144010,222256 143885,215969 143879,198227 143754,191940
+C 924 922 0 TEXT "Conditions" | 97818,190135 1 0 0 "USBWireRdy == 1'b1"
+A 923 922 16 TEXT "Actions" | 93859,209922 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit;  \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 922 360 0 929 453 BEZIER "Transitions" | 138043,187612 109537,196045 81451,206574 52945,215007
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+A 920 888 16 TEXT "Actions" | 54464,112031 1 0 0 "USBWireReq <= 1'b0;"
+A 917 371 4 TEXT "Actions" | 71825,218040 1 0 0 "i <= 5'h0;"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 5'h0;"
+C 378 377 0 TEXT "Conditions" | 56860,208360 1 0 0 "USBWireGnt == 1'b1"
+W 377 217 0 371 883 BEZIER "Transitions" | 52975,210241 55849,199016 58723,187790 61597,176565
+A 374 373 16 TEXT "Actions" | 43761,237148 1 0 0 "USBWireReq <= 1'b1;"
+W 373 217 0 220 371 BEZIER "Transitions" | 41882,245025 44900,239618 46527,227520 49545,222113
+S 371 217 0 ELLIPSE "States" | 53178,216725 6500 6500
+L 370 371 0 TEXT "State Labels" | 53178,216725 1 0 0 "STX_WAIT_GNT\n/25/"
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/7/"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/40/"
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 645 610 0 Builtin Exit | 114540,97930
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+W 648 489 0 599 609 BEZIER "Transitions" | 84906,219546 91705,215743 99788,205923 106587,202120
+W 649 489 0 609 617 BEZIER "Transitions" | 111887,191768 112232,181972 113177,163821 113522,154025
+W 650 489 0 617 626 BEZIER "Transitions" | 113848,141065 113272,128964 113115,107129 112539,95028
+W 651 489 0 626 606 BEZIER "Transitions" | 115586,82704 120772,74867 130139,59148 135325,51311
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/29/"
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 913 912 0 Builtin Entry | 86360,167640
+I 914 912 0 Builtin Exit | 129540,111760
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+A 937 453 4 TEXT "Actions" | 60460,224205 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+L 934 933 0 TEXT "State Labels" | 144285,228746 1 0 0 "WAIT_GNT\n/49/"
+S 933 360 12288 ELLIPSE "States" | 144285,228746 6500 6500
+A 932 931 16 TEXT "Actions" | 105661,247407 1 0 0 "USBWireReq <= 1'b1;"
+W 931 360 0 363 933 BEZIER "Transitions" | 51554,257148 80200,248283 109429,239528 138075,230663
+L 930 929 0 TEXT "State Labels" | 144175,185833 1 0 0 "WAIT_RDY_WIRE\n/48/"
+S 929 360 8192 ELLIPSE "States" | 144175,185458 6500 6500
+C 928 927 0 TEXT "Conditions" | 145669,221771 1 0 0 "USBWireGnt == 1'b1"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/31/"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 663 624 0 Builtin Entry | 59190,254840
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+                                           104039,47385 110550,45085 113597,43935
+I 671 624 0 Builtin Exit | 116402,43935
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/50/"
+S 939 633 16384 ELLIPSE "States" | 39277,179580 6500 6500
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;	\ni <= i + 1'b1;"
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/0/"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/38/"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+A 414 413 16 TEXT "Actions" | 50880,235676 1 0 0 "USBWireReq <= 1'b1;\ni <= 5'h0;"
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/42/"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/27/"
+I 682 633 0 Builtin Exit | 119917,39891
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/51/"
+S 947 734 20480 ELLIPSE "States" | 160390,197270 6500 6500
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/52/"
+S 952 624 24576 ELLIPSE "States" | 35474,185224 6500 6500
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "S5\n/17/"
+S 430 17 0 ELLIPSE "States" | 61659,61312 6500 6500
+L 429 430 0 TEXT "State Labels" | 61659,61312 1 0 0 "S4\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "S3\n/15/"
+C 426 425 0 TEXT "Conditions" | 60723,121216 1 0 0 "i == `RESUME_LEN"
+W 425 17 0 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/34/"
+I 417 17 0 Builtin Entry | 44586,243455
+I 418 17 0 Builtin Exit | 145044,30588
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+W 422 17 8194 407 411 BEZIER "Transitions" | 53385,128518 47424,127138 37085,126164 32881,127325\
+                                             28677,128486 23782,135891 23342,141914 22903,147938\
+                                             26042,164631 28457,169650 30873,174670 37399,178059\
+                                             40756,178310 44113,178561 50283,175993 53734,174801
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "S1\n/14/"
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/30/"
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/6/"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/41/"
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 447 438 16 TEXT "Actions" | 92898,48208 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 106002,65992 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 445 436 16 TEXT "Actions" | 86814,83776 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 444 438 0 TEXT "Conditions" | 142974,49612 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 69498,58972 1 0 0 "USBWireRdy == 1'b1"
+C 442 436 0 TEXT "Conditions" | 131742,84244 1 0 0 "USBWireRdy == 1'b1"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+W 438 17 0 432 434 BEZIER "Transitions" | 165378,56758 153093,51025 79495,38601 67210,32868
+W 437 17 0 430 432 BEZIER "Transitions" | 68151,60997 79383,60646 153908,58822 165140,58471
+W 436 17 0 428 430 BEZIER "Transitions" | 163491,91448 151908,85481 78683,70834 67100,64867
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "S6\n/18/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/35/"
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/10/"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251308 41695,240089 71091,229875 69529,218656
+I 711 480 0 Builtin Entry | 43257,253243
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 713 480 0 Builtin Exit | 85376,122104
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 715 471 0 Builtin Exit | 140592,59380
+I 716 471 0 Builtin Entry | 83616,227615
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/46/"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 123646,30705 142249,30588
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34866,50548 1 0 0 "USBWireWEn <= 1'b0;"
+A 448 432 4 TEXT "Actions" | 158418,73480 1 0 0 "USBWireWEn <= 1'b0;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 731 727 0 Builtin Entry | 71380,236621
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/28/"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+I 738 727 0 Builtin Exit | 114540,97930
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/36/"
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+I 744 734 0 Builtin Exit | 116402,43935
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+I 750 734 0 Builtin Entry | 59190,254840
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/3/"
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 220 217 0 Builtin Entry | 38120,245025
+I 221 217 0 Builtin Exit | 61830,96075
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/32/"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+I 762 733 0 Builtin Exit | 119917,39891
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+                                           48829,42592 51359,37532 61605,36267 71852,35002\
+                                           109061,35775 128289,35775
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+                                           48196,74723 50474,70169 60657,69030 70840,67892\
+                                           108432,68626 127660,68626
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+                                           46931,109511 49715,104703 60024,103501 70334,102300\
+                                           108774,103037 128002,103037
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+                                           46299,139871 48829,136075 59202,135063 69575,134052\
+                                           106314,125693 125795,125567
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/8/"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/39/"
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/45/"
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+I 787 733 0 Builtin Entry | 62705,250796
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/4/"
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+                                              31250,150650 32250,89650 34750,72525 37250,55400\
+                                              46250,47900 56000,46150 65750,44400 95896,46012\
+                                              103573,44899 111250,43786 113107,43935 113607,43935
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+                                           128857,67252 162473,65260 171997,66691 181521,68123\
+                                           186003,75843 187123,97692 188244,119542 188244,199222\
+                                           184384,221196 180525,243170 165087,251388 155563,253628\
+                                           146039,255869 123379,256617 115100,254625 106821,252633\
+                                           98206,243956 92977,239599
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+S 530 458 0 ELLIPSE "States" | 174738,68697 6500 6500
+L 531 530 0 TEXT "State Labels" | 174738,68697 1 0 0 "SEND_IDLE3\n/21/"
+S 543 458 0 ELLIPSE "States" | 63328,102539 6500 6500
+I 540 458 0 Builtin Exit | 68103,43333
+L 535 534 0 TEXT "State Labels" | 172866,103329 1 0 0 "SEND_IDLE1\n/19/"
+S 534 458 0 ELLIPSE "States" | 172866,103329 6500 6500
+L 533 532 0 TEXT "State Labels" | 64758,71505 1 0 0 "SEND_IDLE2\n/20/"
+S 532 458 0 ELLIPSE "States" | 64758,71505 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/44/"
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 812 0 2 Builtin InPort | 18598,255166 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 814 0 2 Builtin InPort | 19062,250526 "" ""
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxBit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxBit.asf	(revision 264)
@@ -0,0 +1,296 @@
+VERSION=1.19
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FREEOID=256
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/9/2004"
+HEADER_PARAM="TITLE,processRxBit"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 16
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 24
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 33
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 42
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 97
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 113
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 115
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 213
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 219
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 227
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+L 7 6 0 TEXT "Labels" | 23239,210942 1 0 0 "prRxBit"
+F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,221539
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 94226,265828 1 0 0 "Module: processRxBit"
+L 8 9 0 TEXT "State Labels" | 42238,183458 1 0 0 "START\n/0/"
+S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
+I 12 6 0 Builtin Reset | 22728,190398
+W 13 6 0 12 9 BEZIER "Transitions" | 22728,190398 27224,190134 31822,186104 35786,184244
+L 15 16 0 TEXT "State Labels" | 116068,123104 1 0 0 "IDLE"
+S 16 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116068,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 18 17 8192 ELLIPSE "States" | 107950,139700 6500 6500
+L 19 18 0 TEXT "State Labels" | 107950,139700 1 0 0 "FIRST_BIT\n/1/"
+I 20 17 0 Builtin Entry | 56736,212076
+I 21 17 0 Builtin Exit | 128380,96970
+W 23 17 0 18 21 BEZIER "Transitions" | 111741,134422 116780,127404 120535,103988 125575,96970
+S 24 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116801,94499 6500 6500
+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
+W 35 41 0 40 37 BEZIER "Transitions" | 111741,134422 116780,127404 121695,118778 126735,111760
+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
+I 37 41 0 Builtin Exit | 129540,111760
+I 38 41 0 Builtin Entry | 86360,167640
+L 39 40 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK\n/9/"
+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 119820,36808 1 0 0 "RES_END"
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 51 6 0 213 16 BEZIER "Transitions" | 42388,154240 42522,148478 41966,137442 42502,133556\
+                                       43038,129670 44914,125650 53423,124511 61932,123372\
+                                       93489,123426 109569,123158
+W 52 6 0 213 24 BEZIER "Transitions" | 42699,154238 43235,140704 42636,114126 43641,106354\
+                                       44646,98582 47594,94562 55902,93624 64210,92686\
+                                       94494,92954 102132,93021 109770,93088 110325,93078\
+                                       110459,93078
+W 53 6 0 213 33 BEZIER "Transitions" | 42645,154234 43047,131722 42770,88800 43976,77142\
+                                       45182,65484 49202,63876 57711,63474 66220,63072\
+                                       96236,63072 103807,63072 111378,63072 111758,63165\
+                                       111892,63165
+W 54 6 0 213 42 BEZIER "Transitions" | 42671,154227 43609,125551 43842,70308 45115,54764\
+                                       46388,39220 49604,34396 58247,33391 66890,32386\
+                                       97657,35973 113335,36375
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+                                       188238,99472 188778,113512 186145,122422 183513,131332\
+                                       167904,143587 159264,149864 150624,156142 133542,158851\
+                                       125779,159931 118017,161011 123617,159646 119837,160051
+W 68 6 0 16 219 BEZIER "Transitions" | 121312,119265 131167,111435 152206,96104 162061,88274
+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 122746,145328 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h1;                          \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+W 76 17 4096 241 18 BEZIER "Transitions" | 130017,172236 121274,163054 112530,153872 103787,144690
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
+W 82 17 8194 75 21 BEZIER "Transitions" | 74719,170800 71529,161085 64380,142085 64960,133312\
+                                          65540,124540 74240,108880 82215,104385 90190,99890\
+                                          113975,98130 125575,96970
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 98161,161647 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+                                            151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+                                        176540,156388 181096,131196 181431,113977 181766,96758\
+                                        182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit)                           //if current bit is a JBit, then\n  RXBitStMachCurrState <= `IDLE_BIT_ST;       //next state is idle\nelse                                          //else\nbegin\n  RXBitStMachCurrState <= `WAIT_RESUME_ST;    //check for resume\n  resumeWaitCnt <= 0;                          \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte;       \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 2 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 2 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit)  //line must leave KBit state for the end of resume\nbegin\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\n  resumeDetected <= 1'b0;   //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit)  //can only be a resume if line remains in Kbit state\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n  resumeWaitCnt <= resumeWaitCnt + 1'b1; \n  //if we've waited long enough, then\n  if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)\n  begin	\n    RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n    resumeDetected <= 1'b1;  //report resume detected\n  end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+                                         107061,21822 137747,20482 148467,20415 159187,20348\
+                                         171381,21420 174463,22458 177545,23497 178090,26035\
+                                         178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+                                         145117,36964 157043,31068 161599,29627 166155,28187\
+                                         172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 134636,218473 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 4'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 2 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 2 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 2 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 2 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 2 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 2 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 2 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 2 Builtin Signal | 78080,259259 "" ""
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[3:0]"
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 2 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 35548,248222 1 0 0 "if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n  RXSameBitCount <= RXSameBitCount + 1'b1;  //inc 'RXSameBitCount'\n  if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error\n    bitStuffError <= 1'b1;                         //flag 'bitStuffError'\n  else                                          //else no bit stuffing error\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;                   //early indication of ready\n	end\n    RXByte <= { 1'b1, RXByte[7:1]};              //RZ bit = 1 (ie no change in 'RxBits')\n  end\nend\nelse                                            //else current 'RxBits' are different from old 'RxBits'\nbegin\n  if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;	               //early indication of ready\n	end\n    RXByte <= {1'b0, RXByte[7:1]};             //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n  end\n  RXSameBitCount <= 4'h1;                      //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 127967,178402 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 127967,178402 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 111780,177768 121508,177678
+C 243 242 0 TEXT "Conditions" | 86880,174058 1 0 0 "RxBits == KBit"
+C 244 76 0 TEXT "Conditions" | 125584,169201 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxByte.v	(revision 264)
@@ -0,0 +1,456 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processRxByte.v
+// Generated   : 09/13/04 06:05:00
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processRxByte.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC);
+input   [15:0] CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0] CRC5Result;
+input   CRC5UpdateRdy;
+input   [7:0] RxByteIn;
+input   [7:0] RxCtrlIn;
+input   clk;
+input   processRxDataInWEn;
+input   rst;
+output  CRC16En;
+output  CRC5En;
+output  CRC5_8Bit;
+output  [7:0] CRCData;
+output  [7:0] RxCtrlOut;
+output  RxDataOutWEn;
+output  [7:0] RxDataOut;
+output  processRxByteRdy;
+output  rstCRC;
+
+reg     CRC16En, next_CRC16En;
+wire    [15:0] CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5En, next_CRC5En;
+wire    [4:0] CRC5Result;
+wire    CRC5UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     [7:0] CRCData, next_CRCData;
+wire    [7:0] RxByteIn;
+wire    [7:0] RxCtrlIn;
+reg     [7:0] RxCtrlOut, next_RxCtrlOut;
+reg     RxDataOutWEn, next_RxDataOutWEn;
+reg     [7:0] RxDataOut, next_RxDataOut;
+wire    clk;
+reg     processRxByteRdy, next_processRxByteRdy;
+wire    processRxDataInWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg CRCError, next_CRCError;
+reg NAKRxed, next_NAKRxed;
+reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg  [7:0]RxByte, next_RxByte;
+reg  [7:0]RxCtrl, next_RxCtrl;
+reg RxOverflow, next_RxOverflow;
+reg  [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg bitStuffError, next_bitStuffError;
+reg dataSequence, next_dataSequence;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0] CurrState_prRxByte;
+reg [3:0] NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+  next_RxOverflow or next_NAKRxed or
+  next_stallRxed or next_ACKRxed or
+  next_dataSequence)
+begin
+    RxStatus <=
+    {1'b0, next_dataSequence,
+    next_ACKRxed,
+    next_stallRxed, next_NAKRxed,
+    next_RxOverflow,
+    next_bitStuffError, next_CRCError };
+end
+
+
+//--------------------------------------------------------------------
+// Machine: prRxByte
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin : prRxByte_NextState
+	NextState_prRxByte <= CurrState_prRxByte;
+	// Set default values for outputs and signals
+	next_RxByte <= RxByte;
+	next_RxCtrl <= RxCtrl;
+	next_RXByteStMachCurrState <= RXByteStMachCurrState;
+	next_CRCError <= CRCError;
+	next_bitStuffError <= bitStuffError;
+	next_RxOverflow <= RxOverflow;
+	next_RxTimeOut <= RxTimeOut;
+	next_NAKRxed <= NAKRxed;
+	next_stallRxed <= stallRxed;
+	next_ACKRxed <= ACKRxed;
+	next_dataSequence <= dataSequence;
+	next_RxDataOut <= RxDataOut;
+	next_RxCtrlOut <= RxCtrlOut;
+	next_RxDataOutWEn <= RxDataOutWEn;
+	next_rstCRC <= rstCRC;
+	next_CRCData <= CRCData;
+	next_CRC5En <= CRC5En;
+	next_CRC5_8Bit <= CRC5_8Bit;
+	next_CRC16En <= CRC16En;
+	next_RXDataByteCnt <= RXDataByteCnt;
+	next_processRxByteRdy <= processRxByteRdy;
+	case (CurrState_prRxByte) // synopsys parallel_case full_case
+		`CHK_ST:
+			if (RXByteStMachCurrState == `HS_BYTE_ST)	
+				NextState_prRxByte <= `HSHAKE_CHK;
+			else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)	
+				NextState_prRxByte <= `TOKEN_WAIT_CRC;
+			else if (RXByteStMachCurrState == `DATA_BYTE_ST)	
+				NextState_prRxByte <= `DATA_WAIT_CRC;
+			else if (RXByteStMachCurrState == `IDLE_BYTE_ST)	
+				NextState_prRxByte <= `IDLE_CHK_START;
+			else if (RXByteStMachCurrState == `CHECK_SYNC_ST)	
+				NextState_prRxByte <= `CHK_SYNC_DO;
+			else if (RXByteStMachCurrState == `CHECK_PID_ST)	
+				NextState_prRxByte <= `CHK_PID_DO_CHK;
+		`START_PRBY:
+		begin
+			next_RxByte <= 8'h00;
+			next_RxCtrl <= 8'h00;
+			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			next_CRCError <= 1'b0;
+			next_bitStuffError <= 1'b0;
+			next_RxOverflow <= 1'b0;
+			next_RxTimeOut <= 1'b0;
+			next_NAKRxed <= 1'b0;
+			next_stallRxed <= 1'b0;
+			next_ACKRxed <= 1'b0;
+			next_dataSequence <= 1'b0;
+			next_RxDataOut <= 8'h00;
+			next_RxCtrlOut <= 8'h00;
+			next_RxDataOutWEn <= 1'b0;
+			next_rstCRC <= 1'b0;
+			next_CRCData <= 8'h00;
+			next_CRC5En <= 1'b0;
+			next_CRC5_8Bit <= 1'b0;
+			next_CRC16En <= 1'b0;
+			next_RXDataByteCnt <= 10'h00;
+			next_processRxByteRdy <= 1'b1;
+			NextState_prRxByte <= `WAIT_BYTE;
+		end
+		`WAIT_BYTE:
+			if (processRxDataInWEn == 1'b1)	
+			begin
+				NextState_prRxByte <= `CHK_ST;
+				next_RxByte <= RxByteIn;
+				next_RxCtrl <= RxCtrlIn;
+				next_processRxByteRdy <= 1'b0;
+			end
+		`HSHAKE_FIN:
+		begin
+			next_RxDataOutWEn <= 1'b0;
+			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`HSHAKE_CHK:
+		begin
+			NextState_prRxByte <= `HSHAKE_FIN;
+			if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+			  next_RxOverflow <= 1'b1;
+			next_RxDataOut <= RxStatus;
+			next_RxCtrlOut <= `RX_PACKET_STOP;
+			next_RxDataOutWEn <= 1'b1;
+		end
+		`CHK_PID_DO_CHK:
+			if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)	
+			begin
+				NextState_prRxByte <= `WAIT_BYTE;
+				next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+				next_processRxByteRdy <= 1'b1;
+			end
+			else
+			begin
+				NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+				next_CRCError <= 1'b0;
+				next_bitStuffError <= 1'b0;
+				next_RxOverflow <= 1'b0;
+				next_NAKRxed <= 1'b0;
+				next_stallRxed <= 1'b0;
+				next_ACKRxed <= 1'b0;
+				next_dataSequence <= 1'b0;
+				next_RxTimeOut <= 1'b0;
+				next_RXDataByteCnt <= 0;
+				next_RxDataOut <= RxByte;
+				next_RxCtrlOut <= `RX_PACKET_START;
+				next_RxDataOutWEn <= 1'b1;
+				next_rstCRC <= 1'b1;
+			end
+		`CHK_PID_FIRST_BYTE_PROC:
+		begin
+			next_rstCRC <= 1'b0;
+			next_RxDataOutWEn <= 1'b0;
+			case (RxByte[1:0] )
+			    `SPECIAL:                              //Special PID.
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    `TOKEN:                                //Token PID
+			    begin
+			    next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+			    next_RXDataByteCnt <= 0;
+			    end
+			    `HANDSHAKE:                            //Handshake PID
+			    begin
+			        case (RxByte[3:2] )
+			            2'b00:
+			        next_ACKRxed <= 1'b1;
+			            2'b10:
+			        next_NAKRxed <= 1'b1;
+			            2'b11:
+			        next_stallRxed <= 1'b1;
+			            default:
+			            begin
+			                $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+			            end
+			        endcase
+			    next_RXByteStMachCurrState <= `HS_BYTE_ST;
+			    end
+			    `DATA:                                  //Data PID
+			    begin
+			        case (RxByte[3:2] )
+			            2'b00:
+			        next_dataSequence <= 1'b0;
+			            2'b10:
+			        next_dataSequence <= 1'b1;
+			            default:
+			                $display ("Invalid DATA PID detected in ProcessRXByte\n");
+			        endcase
+			    next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+			    next_RXDataByteCnt <= 0;
+			    end
+			endcase
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`DATA_FIN:
+		begin
+			next_CRC16En <= 1'b0;
+			next_RxDataOutWEn <= 1'b0;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`DATA_CHK_STRM:
+		begin
+			next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+			case (RxCtrl)
+			    `DATA_STOP:
+			    begin
+			        if (CRC16Result != 16'hb001)
+			      next_CRCError <= 1'b1;
+			    next_RxDataOut <= RxStatus;
+			    next_RxCtrlOut <= `RX_PACKET_STOP;
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    end
+			    `DATA_BIT_STUFF_ERROR:
+			    begin
+			    next_bitStuffError <= 1'b1;
+			    next_RxDataOut <= RxStatus;
+			    next_RxCtrlOut <= `RX_PACKET_STOP;
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    end
+			    `DATA_STREAM:
+			    begin
+			    next_RxDataOut <= RxByte;
+			    next_RxCtrlOut <= `RX_PACKET_STREAM;
+			    next_CRCData <= RxByte;
+			    next_CRC16En <= 1'b1;
+			    end
+			endcase
+			next_RxDataOutWEn <= 1'b1;
+			NextState_prRxByte <= `DATA_FIN;
+		end
+		`DATA_WAIT_CRC:
+			if (CRC16UpdateRdy == 1'b1)	
+				NextState_prRxByte <= `DATA_CHK_STRM;
+		`TOKEN_CHK_STRM:
+		begin
+			next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+			case (RxCtrl)
+			    `DATA_STOP:
+			    begin
+			        if (CRC5Result != 5'h6)
+			      next_CRCError <= 1'b1;
+			    next_RxDataOut <= RxStatus;
+			    next_RxCtrlOut <= `RX_PACKET_STOP;
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    end
+			    `DATA_BIT_STUFF_ERROR:
+			    begin
+			    next_bitStuffError <= 1'b1;
+			    next_RxDataOut <= RxStatus;
+			    next_RxCtrlOut <= `RX_PACKET_STOP;
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    end
+			    `DATA_STREAM:
+			    begin
+			        if (RXDataByteCnt > 10'h2)
+			        begin
+			      next_RxOverflow <= 1'b1;
+			      next_RxDataOut <= RxStatus;
+			      next_RxCtrlOut <= `RX_PACKET_STOP;
+			      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			        end
+			        else
+			        begin
+			      next_RxDataOut <= RxByte;
+			      next_RxCtrlOut <= `RX_PACKET_STREAM;
+			      next_CRCData <= RxByte;
+			      next_CRC5_8Bit <= 1'b1;
+			      next_CRC5En <= 1'b1;
+			        end
+			    end
+			endcase
+			next_RxDataOutWEn <= 1'b1;
+			NextState_prRxByte <= `TOKEN_FIN;
+		end
+		`TOKEN_FIN:
+		begin
+			next_CRC5En <= 1'b0;
+			next_RxDataOutWEn <= 1'b0;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`TOKEN_WAIT_CRC:
+			if (CRC5UpdateRdy == 1'b1)	
+				NextState_prRxByte <= `TOKEN_CHK_STRM;
+		`CHK_SYNC_DO:
+		begin
+			if (RxByte == `SYNC_BYTE)
+			  next_RXByteStMachCurrState = `CHECK_PID_ST;
+			else
+			  next_RXByteStMachCurrState = `IDLE_BYTE_ST;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`IDLE_CHK_START:
+		begin
+			if (RxCtrl == `DATA_START)
+			  next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prRxByte_CurrentState
+	if (rst)	
+		CurrState_prRxByte <= `START_PRBY;
+	else
+		CurrState_prRxByte <= NextState_prRxByte;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prRxByte_RegOutput
+	if (rst)	
+	begin
+		RxByte <= 8'h00;
+		RxCtrl <= 8'h00;
+		RXByteStMachCurrState <= `IDLE_BYTE_ST;
+		CRCError <= 1'b0;
+		bitStuffError <= 1'b0;
+		RxOverflow <= 1'b0;
+		RxTimeOut <= 1'b0;
+		NAKRxed <= 1'b0;
+		stallRxed <= 1'b0;
+		ACKRxed <= 1'b0;
+		dataSequence <= 1'b0;
+		RXDataByteCnt <= 10'h00;
+		RxDataOut <= 8'h00;
+		RxCtrlOut <= 8'h00;
+		RxDataOutWEn <= 1'b0;
+		rstCRC <= 1'b0;
+		CRCData <= 8'h00;
+		CRC5En <= 1'b0;
+		CRC5_8Bit <= 1'b0;
+		CRC16En <= 1'b0;
+		processRxByteRdy <= 1'b1;
+	end
+	else 
+	begin
+		RxByte <= next_RxByte;
+		RxCtrl <= next_RxCtrl;
+		RXByteStMachCurrState <= next_RXByteStMachCurrState;
+		CRCError <= next_CRCError;
+		bitStuffError <= next_bitStuffError;
+		RxOverflow <= next_RxOverflow;
+		RxTimeOut <= next_RxTimeOut;
+		NAKRxed <= next_NAKRxed;
+		stallRxed <= next_stallRxed;
+		ACKRxed <= next_ACKRxed;
+		dataSequence <= next_dataSequence;
+		RXDataByteCnt <= next_RXDataByteCnt;
+		RxDataOut <= next_RxDataOut;
+		RxCtrlOut <= next_RxCtrlOut;
+		RxDataOutWEn <= next_RxDataOutWEn;
+		rstCRC <= next_rstCRC;
+		CRCData <= next_CRCData;
+		CRC5En <= next_CRC5En;
+		CRC5_8Bit <= next_CRC5_8Bit;
+		CRC16En <= next_CRC16En;
+		processRxByteRdy <= next_processRxByteRdy;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sofcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sofcontroller.v	(revision 264)
@@ -0,0 +1,152 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sofcontroller.v
+// Generated   : 09/08/04 06:24:36
+// From        : c:\projects\USBHostSlave\RTL\hostController\sofcontroller.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, SOFEnable, SOFTimerClr, SOFTimer, clk, rst);
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   SOFEnable;
+input   SOFTimerClr;
+input   clk;
+input   rst;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [15:0] SOFTimer;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    SOFEnable;
+wire    SOFTimerClr;
+reg     [15:0] SOFTimer, next_SOFTimer;
+wire    clk;
+wire    rst;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0] CurrState_sofCntl;
+reg [2:0] NextState_sofCntl;
+
+
+//--------------------------------------------------------------------
+// Machine: sofCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl)
+begin : sofCntl_NextState
+	NextState_sofCntl <= CurrState_sofCntl;
+	// Set default values for outputs and signals
+	next_HCTxPortReq <= HCTxPortReq;
+	next_HCTxPortWEn <= HCTxPortWEn;
+	next_HCTxPortData <= HCTxPortData;
+	next_HCTxPortCntl <= HCTxPortCntl;
+	next_SOFTimer <= SOFTimer;
+	case (CurrState_sofCntl) // synopsys parallel_case full_case
+		`START_SC:
+			NextState_sofCntl <= `WAIT_SOF_EN;
+		`WAIT_SOF_EN:
+			if (SOFEnable == 1'b1)	
+			begin
+				NextState_sofCntl <= `SC_WAIT_GNT;
+				next_HCTxPortReq <= 1'b1;
+			end
+		`WAIT_SEND_RESUME:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sofCntl <= `CLR_WEN;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= 8'h00;
+				next_HCTxPortCntl <= `TX_RESUME_START;
+			end
+		`INC_TIMER:
+		begin
+			next_HCTxPortReq <= 1'b0;
+			if (SOFTimerClr == 1'b1)
+			  next_SOFTimer <= 16'h0000;
+			else
+			  next_SOFTimer <= SOFTimer + 1'b1;
+			if (SOFEnable == 1'b0)	
+			begin
+				NextState_sofCntl <= `WAIT_SOF_EN;
+				next_SOFTimer <= 16'h0000;
+			end
+		end
+		`SC_WAIT_GNT:
+			if (HCTxPortGnt == 1'b1)	
+				NextState_sofCntl <= `WAIT_SEND_RESUME;
+		`CLR_WEN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sofCntl <= `INC_TIMER;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sofCntl_CurrentState
+	if (rst)	
+		CurrState_sofCntl <= `START_SC;
+	else
+		CurrState_sofCntl <= NextState_sofCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sofCntl_RegOutput
+	if (rst)	
+	begin
+		SOFTimer <= 16'h0000;
+		HCTxPortCntl <= 8'h00;
+		HCTxPortData <= 8'h00;
+		HCTxPortWEn <= 1'b0;
+		HCTxPortReq <= 1'b0;
+	end
+	else 
+	begin
+		SOFTimer <= next_SOFTimer;
+		HCTxPortCntl <= next_HCTxPortCntl;
+		HCTxPortData <= next_HCTxPortData;
+		HCTxPortWEn <= next_HCTxPortWEn;
+		HCTxPortReq <= next_HCTxPortReq;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/softransmit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/softransmit.v	(revision 264)
@@ -0,0 +1,146 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\softransmit.v
+// Generated   : 09/14/04 21:51:27
+// From        : c:\projects\USBHostSlave\RTL\hostController\softransmit.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn);
+input   SOFEnable;		// After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input   SOFSyncEn;
+input   [15:0] SOFTimer;
+input   clk;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+output  SOFSent;		// single cycle pulse
+output  SOFTimerClr;		// Single cycle pulse
+output  sendPacketArbiterReq;
+output  sendPacketWEn;
+
+wire    SOFEnable;
+reg     SOFSent, next_SOFSent;
+wire    SOFSyncEn;
+reg     SOFTimerClr, next_SOFTimerClr;
+wire    [15:0] SOFTimer;
+wire    clk;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+
+reg [2:0] CurrState_SOFTx;
+reg [2:0] NextState_SOFTx;
+
+
+//--------------------------------------------------------------------
+// Machine: SOFTx
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
+begin : SOFTx_NextState
+	NextState_SOFTx <= CurrState_SOFTx;
+	// Set default values for outputs and signals
+	next_sendPacketArbiterReq <= sendPacketArbiterReq;
+	next_sendPacketWEn <= sendPacketWEn;
+	next_SOFTimerClr <= SOFTimerClr;
+	next_SOFSent <= SOFSent;
+	case (CurrState_SOFTx) // synopsys parallel_case full_case
+		`START_STX:
+			NextState_SOFTx <= `WAIT_SOF_NEAR;
+		`WAIT_SOF_NEAR:
+			if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+				(SOFSyncEn == 1'b1 &&
+				SOFEnable == 1'b1))	
+			begin
+				NextState_SOFTx <= `WAIT_SP_GNT;
+				next_sendPacketArbiterReq <= 1'b1;
+			end
+		`WAIT_SP_GNT:
+			if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)	
+				NextState_SOFTx <= `WAIT_SOF_NOW;
+		`WAIT_SOF_NOW:
+			if (SOFTimer >= `SOF_TX_TIME)	
+			begin
+				NextState_SOFTx <= `SOF_FIN;
+				next_sendPacketWEn <= 1'b1;
+				next_SOFTimerClr <= 1'b1;
+				next_SOFSent <= 1'b1;
+			end
+			else if (SOFEnable == 1'b0)	
+			begin
+				NextState_SOFTx <= `SOF_FIN;
+				next_SOFTimerClr <= 1'b1;
+			end
+		`SOF_FIN:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			next_SOFTimerClr <= 1'b0;
+			next_SOFSent <= 1'b0;
+			NextState_SOFTx <= `WAIT_SOF_NEAR;
+			next_sendPacketArbiterReq <= 1'b0;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SOFTx_CurrentState
+	if (rst)	
+		CurrState_SOFTx <= `START_STX;
+	else
+		CurrState_SOFTx <= NextState_SOFTx;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SOFTx_RegOutput
+	if (rst)	
+	begin
+		SOFSent <= 1'b0;
+		SOFTimerClr <= 1'b0;
+		sendPacketArbiterReq <= 1'b0;
+		sendPacketWEn <= 1'b0;
+	end
+	else 
+	begin
+		SOFSent <= next_SOFSent;
+		SOFTimerClr <= next_SOFTimerClr;
+		sendPacketArbiterReq <= next_sendPacketArbiterReq;
+		sendPacketWEn <= next_sendPacketWEn;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/usbHostControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/usbHostControl.v	(revision 264)
@@ -0,0 +1,403 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostControl.v,v 1.1.1.1 2004-10-11 04:00:56 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+module usbHostControl(
+	clk, rst,
+	//sendPacket
+	TxFifoRE, TxFifoData, TxFifoEmpty,
+	//getPacket
+	RxFifoWE, RxFifoData, RxFifoFull,
+	RxByteStatus, RxData, RxDataValid,
+	SIERxTimeOut,
+	//speedCtrlMux
+	fullSpeedRate, fullSpeedPol,
+	//HCTxPortArbiter
+	HCTxPortEn, HCTxPortRdy,
+	HCTxPortData, HCTxPortCtrl,
+	//rxStatusMonitor
+	connectStateIn, 
+	resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+	SOFSentIntOut, 
+  connEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  hostControlSelect
+ 	 );
+
+input clk, rst;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [3:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut; 
+output connEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+input hostControlSelect;
+
+wire clk;
+wire rst;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut; 
+wire connEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire sendPacketCPFSRate;
+wire sendPacketCPFSPol;
+wire sendPacketCPGrabLine;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;	  
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire directCtrlRate;
+wire directCtrlPol;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI 
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+	.SOFSentIntOut(SOFSentIntOut), 
+  .connEventIntOut(connEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .TxTransTypeReg(transType), 
+  .TxSOFEnableReg(SOFEnable),
+	.TxAddrReg(TxAddr), 
+  .TxEndPReg(TxEndP), 
+  .frameNumIn(frameNum), 
+  .RxPktStatusIn(RxPktStatus), 
+  .RxPIDIn(RxPID),
+  .connectStateIn(connectStateOut),
+	.SOFSentIn(SOFSent), 
+  .connEventIn(connectionEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .hostControlSelect(hostControlSelect),
+  .clrTransReq(clrTxReq),
+  .preambleEn(preAmbleEnable),
+  .SOFSync(SOFSyncEn),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(directCtrlPol), 
+  .fullSpeedRate(directCtrlRate),
+  .transReq(transReq)
+  
+  );
+
+
+hostcontroller u_hostController
+	(.RXStatus(RxPktStatus), 
+	.clearTXReq(clrTxReq),
+	.clk(clk),
+	.getPacketREn(getPacketREn),
+	.getPacketRdy(getPacketRdy),
+	.rst(rst),
+	.sendPacketArbiterGnt(HCTxGnt),
+	.sendPacketArbiterReq(HCTxReq),
+	.sendPacketPID(HC_PID),
+	.sendPacketRdy(sendPacketCPReadyOut),
+	.sendPacketWEn(HC_SP_WEn),
+	.transDone(transDone),
+	.transReq(transReq),
+	.transType(transType) );
+
+SOFController u_SOFController
+	(.HCTxPortCntl(SOFCntlCntl),
+	.HCTxPortData(SOFCntlData),
+	.HCTxPortGnt(SOFCntlGnt),
+	.HCTxPortRdy(HCTxPortRdy),
+	.HCTxPortReq(SOFCntlReq),
+	.HCTxPortWEn(SOFCntlWEn),
+	.SOFEnable(SOFEnable),
+	.SOFTimerClr(SOFTimerClr),
+	.SOFTimer(SOFTimer),
+	.clk(clk),
+	.rst(rst) ); 
+
+SOFTransmit u_SOFTransmit
+	(.SOFEnable(SOFEnable),
+	.SOFSent(SOFSent),
+	.SOFSyncEn(SOFSyncEn),
+	.SOFTimerClr(SOFTimerClr),
+	.SOFTimer(SOFTimer),
+	.clk(clk),
+	.rst(rst),
+	.sendPacketArbiterGnt(SOFTxGnt),
+	.sendPacketArbiterReq(SOFTxReq),
+	.sendPacketRdy(sendPacketCPReadyOut),
+	.sendPacketWEn(SOF_SP_WEn) );	
+
+
+sendPacketArbiter u_sendPacketArbiter
+	(.HCTxGnt(HCTxGnt),
+	.HCTxReq(HCTxReq),
+	.HC_PID(HC_PID),
+	.HC_SP_WEn(HC_SP_WEn),
+	.SOFTxGnt(SOFTxGnt),
+	.SOFTxReq(SOFTxReq),
+	.SOF_SP_WEn(SOF_SP_WEn),
+	.clk(clk),
+	.rst(rst),
+	.sendPacketPID(sendPacketCPPIDIn),
+	.sendPacketWEnable(sendPacketCPWEnIn) );	  
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+	(.sendPacketCPPID(sendPacketCPPIDIn),
+	.clk(clk),
+	.fullSpeedBitRate(sendPacketCPFSRate),
+	.fullSpeedPolarity(sendPacketCPFSPol),
+	.grabLineControl(sendPacketCPGrabLine),
+	.preAmbleEnable(preAmbleEnable),
+	.rst(rst),
+	.sendPacketCPReady(sendPacketCPReadyOut),
+	.sendPacketCPWEn(sendPacketCPWEnIn),
+	.sendPacketPID(sendPacketCPPIDOut),
+	.sendPacketRdy(sendPacketCPReadyIn),
+	.sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+	(.HCTxPortCntl(sendPacketCntl),
+	.HCTxPortData(sendPacketData),
+	.HCTxPortGnt(sendPacketGnt),
+	.HCTxPortRdy(HCTxPortRdy),
+	.HCTxPortReq(sendPacketReq),
+	.HCTxPortWEn(sendPacketWEn),
+	.PID(sendPacketCPPIDOut),
+	.TxAddr(TxAddr),
+	.TxEndP(TxEndP),
+	.clk(clk),
+	.fifoData(TxFifoData),
+	.fifoEmpty(TxFifoEmpty),
+	.fifoReadEn(TxFifoRE),
+	.frameNum(frameNum),
+	.rst(rst),
+	.sendPacketRdy(sendPacketCPReadyIn),
+	.sendPacketWEn(sendPacketCPWEnOut) );
+	
+directControl u_directControl
+	(.HCTxPortCntl(directCntlCntl),
+	.HCTxPortData(directCntlData),
+	.HCTxPortGnt(directCntlGnt),
+	.HCTxPortRdy(HCTxPortRdy),
+	.HCTxPortReq(directCntlReq),
+	.HCTxPortWEn(directCntlWEn),
+	.clk(clk),
+	.directControlEn(directLineCtrlEn),
+	.directControlLineState(directLineState),
+	.rst(rst) ); 
+
+HCTxPortArbiter u_HCTxPortArbiter
+	(.HCTxPortCntl(HCTxPortCtrl),
+	.HCTxPortData(HCTxPortData),
+	.HCTxPortWEnable(HCTxPortEn),
+	.SOFCntlCntl(SOFCntlCntl),
+	.SOFCntlData(SOFCntlData),
+	.SOFCntlGnt(SOFCntlGnt),
+	.SOFCntlReq(SOFCntlReq),
+	.SOFCntlWEn(SOFCntlWEn),
+	.clk(clk),
+	.directCntlCntl(directCntlCntl),
+	.directCntlData(directCntlData),
+	.directCntlGnt(directCntlGnt),
+	.directCntlReq(directCntlReq),
+	.directCntlWEn(directCntlWEn),
+	.rst(rst),
+	.sendPacketCntl(sendPacketCntl),
+	.sendPacketData(sendPacketData),
+	.sendPacketGnt(sendPacketGnt),
+	.sendPacketReq(sendPacketReq),
+	.sendPacketWEn(sendPacketWEn) );	  
+
+getPacket u_getPacket
+	(.RXDataIn(RxData),
+	.RXDataValid(RxDataValid),
+	.RXFifoData(RxFifoData),
+	.RXFifoFull(RxFifoFull),
+	.RXFifoWEn(RxFifoWE),
+	.RXPacketRdy(getPacketRdy),
+	.RXPktStatus(RxPktStatus),
+	.RXStreamStatusIn(RxByteStatus),
+	.RxPID(RxPID),
+	.SIERxTimeOut(SIERxTimeOut),
+	.clk(clk),
+	.getPacketEn(getPacketREn),
+	.rst(rst) ); 
+
+speedCtrlMux u_speedCtrlMux
+	(.directCtrlRate(directCtrlRate),
+	.directCtrlPol(directCtrlPol),
+	.sendPacketRate(sendPacketCPFSRate),
+	.sendPacketPol(sendPacketCPFSPol),
+	.sendPacketSel(sendPacketCPGrabLine),
+	.fullSpeedRate(fullSpeedRate),
+	.fullSpeedPol(fullSpeedPol) );
+
+rxStatusMonitor	u_rxStatusMonitor
+	(.connectStateIn(connectStateIn),
+	.connectStateOut(connectStateOut),
+	.resumeDetectedIn(resumeDetectedIn),
+	.connectionEventOut(connectionEventFromRxStatusMon),
+	.resumeIntOut(resumeIntFromRxStatusMon),
+	.clk(clk),
+	.rst(rst)  );
+
+endmodule
+
+	
+	
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v	(revision 264)
@@ -0,0 +1,92 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMuxBI.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostSlaveMuxBI.v,v 1.1.1.1 2004-10-11 04:00:56 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+ module hostSlaveMuxBI (dataIn, dataOut, writeEn, strobe_i, clk, rst,
+	hostMode, hostSlaveMuxSel);
+
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+
+//internal wire and regs
+
+//sync write demux
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+    hostMode <= 1'b0;
+  else begin
+	  if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1)
+			hostMode <= dataIn[0];
+  end
+end
+
+
+// async read mux
+always @(hostMode)
+begin
+	dataOut <= {7'h0, hostMode};
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbHostControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbHostControl_h.v	(revision 264)
@@ -0,0 +1,111 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl_h.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostControl_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+ 
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants 
+`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval
+`define SOF_TX_MARGIN 2
+       
+//Host RXStatusRegIndices 
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/wishBoneBus_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/wishBoneBus_h.v	(revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBus_h.v                                              ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: wishBoneBus_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+ 
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v	(revision 264)
@@ -0,0 +1,82 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// lineControlUpdate.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: lineControlUpdate.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+    if (fullSpeedPolarity == 1'b1)
+	begin
+      JBit = `ONE_ZERO;
+      KBit = `ZERO_ONE;
+    end
+    else
+	begin
+      JBit = `ZERO_ONE;
+      KBit = `ONE_ZERO;
+    end
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxByte.asf	(revision 264)
@@ -0,0 +1,292 @@
+VERSION=1.19
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FREEOID=384
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/9/2004"
+HEADER_PARAM="TITLE,processRxByte"
+END
+BUNDLES
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+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
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+END
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+L 299 300 0 TEXT "Labels" | 82848,255265 1 0 0 "RxCtrlOut[7:0]"
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+I 306 0 2 Builtin InPort | 78465,238172 "" ""
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+C 55 51 0 TEXT "Conditions" | 43455,121392 1 0 0 "RXByteStMachCurrState == `CHECK_PID_ST"
+C 56 52 0 TEXT "Conditions" | 45596,90880 1 0 0 "RXByteStMachCurrState == `HS_BYTE_ST"
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+I 221 217 0 Builtin Exit | 136710,89055
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+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n  RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n  RXByteStMachCurrState = `IDLE_BYTE_ST;"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n  RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n  `SPECIAL:                              //Special PID.\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  `TOKEN:                                //Token PID\n  begin\n    RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\n  `HANDSHAKE:                            //Handshake PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        ACKRxed <= 1'b1;\n      2'b10:\n        NAKRxed <= 1'b1;\n      2'b11:\n        stallRxed <= 1'b1;\n      default:\n      begin\n        $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n      end\n    endcase\n    RXByteStMachCurrState <= `HS_BYTE_ST;\n  end\n  `DATA:                                  //Data PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        dataSequence <= 1'b0;\n      2'b10:\n        dataSequence <= 1'b1;\n      default:\n        $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n    endcase\n    RXByteStMachCurrState <= `DATA_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\nendcase"
+I 252 248 0 Builtin Entry | 35384,229000
+I 253 248 0 Builtin Exit | 78564,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+                                          110499,87996 110355,80840 110355,80474
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n  RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+I 260 32 0 Builtin Exit | 110355,78302
+I 259 32 0 Builtin Entry | 66351,233704
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+                                        89364,102368 89220,95212 89220,94846
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/RxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/RxFifo.v	(revision 264)
@@ -0,0 +1,130 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo read access via bus interface, fifo write access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: RxFifo.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module RxFifo(
+  clk, 
+  rst, 
+  fifoWEn, 
+  fifoFull,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataIn  );
+  //FIFO_DEPTH = ADDR_WIDTH^2
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk; 
+wire rst; 
+wire fifoWEn; 
+wire fifoFull;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(fifoDataIn), 
+  .dataOut(dataFromFifoToBus), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+RxfifoBI u_RxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .fifoDataIn(dataFromFifoToBus),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoREn(fifoREn),
+  .fifoEmpty(fifoEmpty),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/RxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/RxFifoBI.v	(revision 264)
@@ -0,0 +1,131 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: RxFifoBI.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+  address, 
+  writeEn, 
+  strobe_i,
+  clk, 
+  rst, 
+  fifoSelect,
+  fifoDataIn,
+  busDataIn, 
+  busDataOut,
+  fifoREn,
+  fifoEmpty,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoREn;
+input fifoEmpty;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoREn;
+wire fifoEmpty;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+	if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)
+begin
+	case (address)
+      `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00; 
+	endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b0 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoREn <= 1'b1;
+  else
+    fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/TxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/TxFifo.v	(revision 264)
@@ -0,0 +1,128 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo write access via bus interface, fifo read access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: TxFifo.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module TxFifo(
+  clk, 
+  rst, 
+  fifoREn, 
+  fifoEmpty,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataOut ); 
+  //FIFO_DEPTH = ADDR_WIDTH^2
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoREn; 
+output fifoEmpty;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire clk; 
+wire rst; 
+wire fifoREn; 
+wire fifoEmpty;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(busDataIn), 
+  .dataOut(fifoDataOut), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+TxfifoBI u_TxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoWEn(fifoWEn),
+  .fifoFull(fifoFull),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/TxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/TxFifoBI.v	(revision 264)
@@ -0,0 +1,123 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: TxFifoBI.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+  address, writeEn, strobe_i,
+  clk, rst, fifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoWEn,
+  fifoFull,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoWEn;
+input fifoFull;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoWEn;
+wire fifoFull;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+	if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoFull or numElementsInFifo)
+begin
+	case (address)
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00;
+	endcase
+end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoWEn <= 1'b1;
+  else
+    fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/fifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/fifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/fifoMem.v	(revision 264)
@@ -0,0 +1,102 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMem.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoMem.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module fifoMem(	addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+	// Generic synchronous dual-port RAM interface
+	.rclk(clk), 
+  .rrst(1'b0), 
+  .rce(1'b1), 
+  .oe(readEn), 
+  .raddr(addrOut), 
+  .do(dataOut),
+	.wclk(clk), 
+  .wrst(1'b0), 
+  .wce(1'b1),
+  .we(writeEn), 
+  .waddr(addrIn), 
+  .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_simFifoMem (
+	.addrIn(addrIn),
+	.addrOut(addrOut),
+	.clk(clk),
+	.dataIn(dataIn),
+	.writeEn(writeEn),
+	.readEn(readEn),
+	.dataOut(dataOut));  
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/fifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/fifoRTL.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/fifoRTL.v	(revision 264)
@@ -0,0 +1,146 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoRTL.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+////  User must check full and empty flags before accessing fifo
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoRTL.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+  parameter FIFO_WIDTH = 8;
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input rst;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoWEn;
+input fifoREn;
+output fifoFull;
+output fifoEmpty;
+input forceEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire clk;
+wire rst;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg  [15:0]numElementsInFifo;
+
+
+// local registers
+reg  [ADDR_WIDTH-1:0]bufferInIndex;
+reg  [ADDR_WIDTH-1:0]bufferOutIndex;
+reg  [ADDR_WIDTH:0]bufferCnt;
+reg  fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || forceEmpty == 1'b1)
+  begin
+    bufferCnt <= 0;
+    fifoFull <= 1'b0;
+    fifoEmpty <= 1'b1;
+		bufferInIndex <= 0;
+		bufferOutIndex <= 0;
+    fifoREnDelayed <= 1'b0;
+	end
+    else
+    begin
+      if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        dataOut <= dataFromMem;
+      end
+      fifoREnDelayed <= fifoREn;
+      if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
+        bufferCnt <= bufferCnt + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end 
+      else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferCnt <= bufferCnt - 1;
+        bufferOutIndex <= bufferOutIndex + 1;
+      end
+      else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferOutIndex <= bufferOutIndex + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end
+      if (bufferCnt[ADDR_WIDTH] == 1'b1)
+        fifoFull <= 1'b1;
+      else
+        fifoFull <= 1'b0;
+      if (|bufferCnt == 1'b0) 
+        fifoEmpty <= 1'b1;
+      else
+        fifoEmpty <= 1'b0;
+    end
+end
+
+//pad bufferCnt with leading zeroes
+always @(bufferCnt) begin
+  numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
+end
+
+fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_fifoMem (
+	.addrIn(bufferInIndex),
+	.addrOut(bufferOutIndex),
+	.clk(clk),
+	.dataIn(dataIn),
+	.writeEn(fifoWEn),
+	.readEn(fifoREn),
+	.dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/simFifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/simFifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/simFifoMem.v	(revision 264)
@@ -0,0 +1,89 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// simFifoMem.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: simFifoMem.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module simFifoMem(	addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge clk) begin
+  dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge clk) begin
+  if (writeEn == 1'b1)
+    buffer[addrIn] <= dataIn;
+end                  
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/buffers/simFifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/busInterface/wishBoneBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/busInterface/wishBoneBI.v	(revision 264)
@@ -0,0 +1,251 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBI.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: wishBoneBI.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "wishBoneBus_h.v"
+
+ 
+module wishBoneBI (
+  address, dataIn, dataOut, writeEn, 
+  strobe_i,
+  ack_o,
+  clk, rst,
+	hostControlSel, 
+  hostRxFifoSel, hostTxFifoSel,
+  slaveControlSel,
+  slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, 
+  slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, 
+  hostSlaveMuxSel,
+  dataFromHostControl,
+  dataFromHostRxFifo,
+  dataFromHostTxFifo,
+  dataFromSlaveControl,
+  dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+  dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+  dataFromHostSlaveMux
+	 );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+  dataFromHostControl or
+  dataFromHostRxFifo or
+  dataFromHostTxFifo or
+  dataFromSlaveControl or
+  dataFromEP0RxFifo or 
+  dataFromEP1RxFifo or
+  dataFromEP2RxFifo or
+  dataFromEP3RxFifo or
+  dataFromHostSlaveMux or 
+  dataFromEP0TxFifo or
+  dataFromEP1TxFifo or
+  dataFromEP2TxFifo or
+  dataFromEP3TxFifo)
+begin
+  hostControlSel <= 1'b0;
+  hostRxFifoSel <= 1'b0;
+  hostTxFifoSel <= 1'b0;
+  slaveControlSel <= 1'b0;
+  slaveEP0RxFifoSel <= 1'b0;
+  slaveEP0TxFifoSel <= 1'b0;
+  slaveEP1RxFifoSel <= 1'b0;
+  slaveEP1TxFifoSel <= 1'b0;
+  slaveEP2RxFifoSel <= 1'b0;
+  slaveEP2TxFifoSel <= 1'b0;
+  slaveEP3RxFifoSel <= 1'b0;
+  slaveEP3TxFifoSel <= 1'b0;
+  hostSlaveMuxSel <= 1'b0;
+  case (address & `ADDRESS_DECODE_MASK)
+    `HCREG_BASE : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HCREG_BASE_PLUS_0X10 : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HOST_RX_FIFO_BASE : begin
+      hostRxFifoSel <= 1'b1;
+      dataOut <= dataFromHostRxFifo;
+    end
+    `HOST_TX_FIFO_BASE : begin
+      hostTxFifoSel <= 1'b1;
+      dataOut <= dataFromHostTxFifo;
+    end
+    `SCREG_BASE : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `SCREG_BASE_PLUS_0X10 : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `EP0_RX_FIFO_BASE : begin
+      slaveEP0RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0RxFifo;
+    end
+    `EP0_TX_FIFO_BASE : begin
+      slaveEP0TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0TxFifo;
+    end
+    `EP1_RX_FIFO_BASE : begin
+      slaveEP1RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1RxFifo;
+    end
+    `EP1_TX_FIFO_BASE : begin
+      slaveEP1TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1TxFifo;
+    end
+    `EP2_RX_FIFO_BASE : begin
+      slaveEP2RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2RxFifo;
+    end
+    `EP2_TX_FIFO_BASE : begin
+      slaveEP2TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2TxFifo;
+    end
+    `EP3_RX_FIFO_BASE : begin
+      slaveEP3RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3RxFifo;
+    end
+    `EP3_TX_FIFO_BASE : begin
+      slaveEP3TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3TxFifo;
+    end
+    `HOST_SLAVE_CONTROL_BASE : begin
+      hostSlaveMuxSel <= 1'b1; 
+      dataOut <= dataFromHostSlaveMux;
+    end
+    default: 
+      dataOut <= 8'h00;
+	endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+  ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+  ack_immediate <= strobe_i;
+end 
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+  if (writeEn == 1'b0 &&
+      (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+  begin
+    ack_o <= ack_delayed;
+  end
+  else
+  begin
+    ack_o <= ack_immediate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/USBHostControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/USBHostControlBI.v	(revision 264)
@@ -0,0 +1,264 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBHostControlBI.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: USBHostControlBI.v,v 1.1.1.1 2004-10-11 04:00:56 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbHostControl_h.v"
+ 
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+	SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+	TxTransTypeReg, TxSOFEnableReg,
+	TxAddrReg, TxEndPReg, frameNumIn, 
+	RxPktStatusIn, RxPIDIn,
+	connectStateIn,
+	SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+  hostControlSelect,
+  clrTransReq,
+  preambleEn,
+  SOFSync,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  transReq
+  );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output transReq;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg transReq;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//sync write demux
+always @(posedge clk)
+begin
+	clrSOFReq <= 1'b0;
+  clrConnEvtReq <= 1'b0;
+  clrResInReq <= 1'b0;
+  clrTransDoneReq <= 1'b0;
+  setTransReq <= 1'b0;
+	if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+	begin
+		case (address)
+			`TX_CONTROL_REG : begin
+        preambleEn <= dataIn[2];
+        SOFSync <= dataIn[1];
+        setTransReq <= dataIn[0];
+      end
+			`TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
+			`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+			`TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[0];
+			`TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
+			`TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
+			`INTERRUPT_STATUS_REG :	begin
+        clrSOFReq <= dataIn[3];
+        clrConnEvtReq <= dataIn[2];
+        clrResInReq <= dataIn[1];
+        clrTransDoneReq <= dataIn[0];
+      end
+			`INTERRUPT_MASK_REG	: interruptMaskReg <= dataIn[3:0];
+		endcase
+	end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+	if (SOFSentIn == 1'b1)
+		SOFSentInt <= 1'b1;
+	else if (clrSOFReq == 1'b1)
+		SOFSentInt <= 1'b0;
+		
+	if (connEventIn == 1'b1)
+		connEventInt <= 1'b1;
+	else if (clrConnEvtReq == 1'b1)
+		connEventInt <= 1'b0;
+		
+	if (resumeIntIn == 1'b1)
+		resumeInt <= 1'b1;
+	else if (clrResInReq == 1'b1)
+		resumeInt <= 1'b0;	
+
+	if (transDoneIn == 1'b1)
+		transDoneInt <= 1'b1;
+	else if (clrTransDoneReq == 1'b1)
+		transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end  
+  
+//transaction request set/clear
+always @(posedge clk)
+begin
+	if (setTransReq == 1'b1)
+		transReq <= 1'b1;
+	else if (clrTransReq == 1'b1)
+		transReq <= 1'b0;
+end  
+  
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+  TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+  fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+  
+// async read mux
+always @(address or
+	TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+	TxAddrReg or TxEndPReg or frameNumIn or 
+	SOFSentInt or connEventInt or resumeInt or transDoneInt or
+	interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+  preambleEn or SOFSync or transReq)
+begin
+	case (address)
+			`TX_CONTROL_REG : dataOut <= {5'b00000, preambleEn, SOFSync, transReq} ;
+			`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
+			`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+			`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
+			`TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
+			`TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
+			`FRAME_NUM_MSB_REG : dataOut <= frameNumIn[10:3];
+			`FRAME_NUM_LSB_REG : dataOut <= {5'b00000, frameNumIn[2:0]};
+			`INTERRUPT_STATUS_REG :	dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+			`INTERRUPT_MASK_REG	: dataOut <= {4'h0, interruptMaskReg};
+			`RX_STATUS_REG	: dataOut <= RxPktStatusIn;
+			`RX_PID_REG	: dataOut <= {4'b0000, RxPIDIn};
+			`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
+      default: dataOut <= 8'h00;
+	endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/directcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/directcontrol.asf	(revision 264)
@@ -0,0 +1,132 @@
+VERSION=1.19
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FREEOID=180
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/20/2004"
+HEADER_PARAM="TITLE,directControl"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
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+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 78
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 127
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: directControl"
+A 5 0 1 TEXT "Actions" | 17700,253700 1 0 0 "// diagram ACTION"
+F 6 0 671089152 16 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "drctCntl"
+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_DC\n/0/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+I 13 6 0 Builtin Reset | 48900,215400
+W 14 6 0 13 9 BEZIER "Transitions" | 48900,215400 60300,214600 83007,213291 94407,212491
+L 15 16 0 TEXT "Labels" | 187300,263800 1 0 0 "clk"
+I 16 0 3 Builtin InPort | 181300,263800 "" ""
+L 17 18 0 TEXT "Labels" | 187500,257400 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 181500,257400 "" ""
+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
+L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn"
+I 21 0 2 Builtin InPort | 57252,239123 "" ""
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+L 77 78 0 TEXT "State Labels" | 68590,129326 1 0 0 "DRCT_CNTL"
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+L 91 90 0 TEXT "State Labels" | 62621,146145 1 0 0 "WAIT_GNT\n/2/"
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+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;"
+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1"
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+A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/directcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/directcontrol.v	(revision 264)
@@ -0,0 +1,167 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\directcontrol.v
+// Generated   : 06/05/04 05:32:20
+// From        : c:\projects\USBHostSlave\RTL\hostController\directcontrol.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, clk, directControlEn, directControlLineState, rst);
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   clk;
+input   directControlEn;
+input   [1:0] directControlLineState;
+input   rst;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    clk;
+wire    directControlEn;
+wire    [1:0] directControlLineState;
+wire    rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0] CurrState_drctCntl;
+reg [2:0] NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+//--------------------------------------------------------------------
+// Machine: drctCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (directControlLineState or directControlEn or HCTxPortGnt or HCTxPortRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_drctCntl)
+begin : drctCntl_NextState
+	NextState_drctCntl <= CurrState_drctCntl;
+	// Set default values for outputs and signals
+	next_HCTxPortReq <= HCTxPortReq;
+	next_HCTxPortWEn <= HCTxPortWEn;
+	next_HCTxPortData <= HCTxPortData;
+	next_HCTxPortCntl <= HCTxPortCntl;
+	case (CurrState_drctCntl) // synopsys parallel_case full_case
+		`START_DC:
+			NextState_drctCntl <= `CHK_DRCT_CNTL;
+		`CHK_DRCT_CNTL:
+			if (directControlEn == 1'b1)	
+			begin
+				NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+				next_HCTxPortReq <= 1'b1;
+			end
+			else
+			begin
+				NextState_drctCntl <= `IDLE_WAIT_GNT;
+				next_HCTxPortReq <= 1'b1;
+			end
+		`DRCT_CNTL_WAIT_GNT:
+			if (HCTxPortGnt == 1'b1)	
+				NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+		`DRCT_CNTL_CHK_LOOP:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			if (directControlEn == 1'b0)	
+			begin
+				NextState_drctCntl <= `CHK_DRCT_CNTL;
+				next_HCTxPortReq <= 1'b0;
+			end
+			else
+				NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+		end
+		`DRCT_CNTL_WAIT_RDY:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= {6'b000000, directControlLineState};
+				next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+			end
+		`IDLE_FIN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			next_HCTxPortReq <= 1'b0;
+			NextState_drctCntl <= `CHK_DRCT_CNTL;
+		end
+		`IDLE_WAIT_GNT:
+			if (HCTxPortGnt == 1'b1)	
+				NextState_drctCntl <= `IDLE_WAIT_RDY;
+		`IDLE_WAIT_RDY:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_drctCntl <= `IDLE_FIN;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= 8'h00;
+				next_HCTxPortCntl <= `TX_IDLE;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : drctCntl_CurrentState
+	if (rst)	
+		CurrState_drctCntl <= `START_DC;
+	else
+		CurrState_drctCntl <= NextState_drctCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : drctCntl_RegOutput
+	if (rst)	
+	begin
+		HCTxPortCntl <= 8'h00;
+		HCTxPortData <= 8'h00;
+		HCTxPortWEn <= 1'b0;
+		HCTxPortReq <= 1'b0;
+	end
+	else 
+	begin
+		HCTxPortCntl <= next_HCTxPortCntl;
+		HCTxPortData <= next_HCTxPortData;
+		HCTxPortWEn <= next_HCTxPortWEn;
+		HCTxPortReq <= next_HCTxPortReq;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/getpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/getpacket.asf	(revision 264)
@@ -0,0 +1,280 @@
+VERSION=1.19
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FREEOID=259
+"LIBRARIES=`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/22/2004"
+HEADER_PARAM="TITLE,getPacket"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 33
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 58
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 112
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 245
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 251
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
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+F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "getPkt"
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+                                         190292,107515 191648,100057 191987,92429 192326,84802\
+                                         192326,61750 188540,53162 184755,44574 169613,33274\
+                                         159556,30336 149499,27398 125714,27614 113171,27388
+C 43 41 0 TEXT "Conditions" | 74897,110510 1 0 0 "SIERxTimeOut == 1'b1"
+A 42 41 16 TEXT "Actions" | 81060,99034 1 0 0 "RXTimeOut <= 1'b1;"
+W 41 6 0 11 40 BEZIER "Transitions" | 96829,146625 92570,132664 92057,131084 90299,121915\
+                                      88541,112746 87971,105860 87641,93102 87312,80344\
+                                      87761,70127 92565,59363 97370,48599 95270,45542\
+                                      101102,30966
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+L 32 33 0 TEXT "State Labels" | 141010,72814 1 0 0 "PROC_PKT"
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141010,72814 6500 6500
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141270,86456 141068,79285
+C 35 34 0 TEXT "Conditions" | 122408,97630 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 59 46 0 49 54 BEZIER "Transitions" | 52133,248640 63746,242665 85368,230107 96981,224132
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+I 49 46 0 Builtin Entry | 47660,248640
+I 50 46 0 Builtin Exit | 180308,72140
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+I 76 72 0 Builtin Exit | 187140,27160
+I 75 72 0 Builtin Entry | 33260,254940
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nNAKRxed <= RXDataIn[`NAK_RXED_BIT];\nstallRxed <= RXDataIn[`STALL_RXED_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+W 87 72 0 75 80 BEZIER "Transitions" | 37733,254940 43032,249077 61954,258197 67253,252334
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177616,25344 184028,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176799,72082 177196,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 2 Builtin InPort | 114408,221254 "" ""
+I 191 0 2 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 2 Builtin Signal | 19204,221408 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 207 0 0 Builtin OutPort | 77404,226912 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+I 216 0 2 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 2 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+I 238 0 2 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 2 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 2 Builtin OutPort | 77780,242452 "" ""
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n  RXPktStatus = { \n  dataSequence, ACKRxed, \n  stallRxed, NAKRxed,\n  RXTimeOut, RXOverflow, \n  bitStuffError, CRCError};\nend"
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+                                           57686,214631 75382,223396 84426,228258
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/getpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/getpacket.v	(revision 264)
@@ -0,0 +1,337 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\getpacket.v
+// Generated   : 09/22/04 06:01:21
+// From        : c:\projects\USBHostSlave\RTL\hostController\getpacket.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, clk, getPacketEn, rst);
+input   [7:0] RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0] RXStreamStatusIn;
+input   SIERxTimeOut;		// Single cycle pulse
+input   clk;
+input   getPacketEn;
+input   rst;
+output  [7:0] RXFifoData;
+output  RXFifoWEn;
+output  RXPacketRdy;
+output  [7:0] RXPktStatus;
+output  [3:0] RxPID;
+
+wire    [7:0] RXDataIn;
+wire    RXDataValid;
+reg     [7:0] RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [7:0] RXPktStatus;
+wire    [7:0] RXStreamStatusIn;
+reg     [3:0] RxPID, next_RxPID;
+wire    SIERxTimeOut;
+wire    clk;
+wire    getPacketEn;
+wire    rst;
+
+// diagram signals declarations
+reg  ACKRxed, next_ACKRxed;
+reg  CRCError, next_CRCError;
+reg  NAKRxed, next_NAKRxed;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXByte, next_RXByte;
+reg  RXOverflow, next_RXOverflow;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+reg  RXTimeOut, next_RXTimeOut;
+reg  bitStuffError, next_bitStuffError;
+reg  dataSequence, next_dataSequence;
+reg  stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0] CurrState_getPkt;
+reg [4:0] NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+  RXOverflow or RXTimeOut or
+  NAKRxed or stallRxed or
+  ACKRxed or dataSequence)
+begin
+    RXPktStatus = {
+    dataSequence, ACKRxed,
+    stallRxed, NAKRxed,
+    RXTimeOut, RXOverflow,
+    bitStuffError, CRCError};
+end
+
+
+//--------------------------------------------------------------------
+// Machine: getPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)
+begin : getPkt_NextState
+	NextState_getPkt <= CurrState_getPkt;
+	// Set default values for outputs and signals
+	next_CRCError <= CRCError;
+	next_bitStuffError <= bitStuffError;
+	next_RXOverflow <= RXOverflow;
+	next_RXTimeOut <= RXTimeOut;
+	next_NAKRxed <= NAKRxed;
+	next_stallRxed <= stallRxed;
+	next_ACKRxed <= ACKRxed;
+	next_dataSequence <= dataSequence;
+	next_RXByte <= RXByte;
+	next_RXStreamStatus <= RXStreamStatus;
+	next_RxPID <= RxPID;
+	next_RXPacketRdy <= RXPacketRdy;
+	next_RXByteOldest <= RXByteOldest;
+	next_RXByteOld <= RXByteOld;
+	next_RXFifoWEn <= RXFifoWEn;
+	next_RXFifoData <= RXFifoData;
+	case (CurrState_getPkt) // synopsys parallel_case full_case
+		`START_GP:
+			NextState_getPkt <= `WAIT_EN;
+		`WAIT_PKT:
+		begin
+			next_CRCError <= 1'b0;
+			next_bitStuffError <= 1'b0;
+			next_RXOverflow <= 1'b0;
+			next_RXTimeOut <= 1'b0;
+			next_NAKRxed <= 1'b0;
+			next_stallRxed <= 1'b0;
+			next_ACKRxed <= 1'b0;
+			next_dataSequence <= 1'b0;
+			if (SIERxTimeOut == 1'b1)	
+			begin
+				NextState_getPkt <= `PKT_RDY;
+				next_RXTimeOut <= 1'b1;
+			end
+			else if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `CHK_PKT_START;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		end
+		`CHK_PKT_START:
+			if (RXStreamStatus == `RX_PACKET_START)	
+			begin
+				NextState_getPkt <= `PROC_PKT_CHK_PID;
+				next_RxPID <= RXByte[3:0];
+			end
+			else
+			begin
+				NextState_getPkt <= `PKT_RDY;
+				next_RXTimeOut <= 1'b1;
+			end
+		`WAIT_EN:
+		begin
+			next_RXPacketRdy <= 1'b0;
+			if (getPacketEn == 1'b1)	
+				NextState_getPkt <= `WAIT_PKT;
+		end
+		`PKT_RDY:
+		begin
+			next_RXPacketRdy <= 1'b1;
+			NextState_getPkt <= `WAIT_EN;
+		end
+		`PROC_PKT_CHK_PID:
+			if (RXByte[1:0] == `HANDSHAKE)	
+				NextState_getPkt <= `PROC_PKT_HS;
+			else if (RXByte[1:0] == `DATA)	
+				NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+			else
+				NextState_getPkt <= `PKT_RDY;
+		`PROC_PKT_HS:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PKT_RDY;
+				next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+				next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+				next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+				next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+			end
+		`PROC_PKT_DATA_W_D1:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_CHK_D1:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+				next_RXByteOldest <= RXByte;
+			end
+			else
+				NextState_getPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_W_D2:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_FIN:
+		begin
+			next_CRCError <= RXByte[`CRC_ERROR_BIT];
+			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+			NextState_getPkt <= `PKT_RDY;
+		end
+		`PROC_PKT_DATA_CHK_D2:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+				next_RXByteOld <= RXByte;
+			end
+			else
+				NextState_getPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_W_D3:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_CHK_D3:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+				NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+			else
+				NextState_getPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_LOOP_CHK_FIFO:
+			if (RXFifoFull == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+				next_RXOverflow <= 1'b1;
+			end
+			else
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+				next_RXFifoWEn <= 1'b1;
+				next_RXFifoData <= RXByteOldest;
+				next_RXByteOldest <= RXByteOld;
+				next_RXByteOld <= RXByte;
+			end
+		`PROC_PKT_DATA_LOOP_FIFO_FULL:
+			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+		`PROC_PKT_DATA_LOOP_W_D:
+		begin
+			next_RXFifoWEn <= 1'b0;
+			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+			else if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_FIN;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		end
+		`PROC_PKT_DATA_LOOP_DELAY:
+			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : getPkt_CurrentState
+	if (rst)	
+		CurrState_getPkt <= `START_GP;
+	else
+		CurrState_getPkt <= NextState_getPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : getPkt_RegOutput
+	if (rst)	
+	begin
+		RXByteOld <= 8'h00;
+		RXByteOldest <= 8'h00;
+		CRCError <= 1'b0;
+		bitStuffError <= 1'b0;
+		RXOverflow <= 1'b0;
+		RXTimeOut <= 1'b0;
+		NAKRxed <= 1'b0;
+		stallRxed <= 1'b0;
+		ACKRxed <= 1'b0;
+		dataSequence <= 1'b0;
+		RXByte <= 8'h00;
+		RXStreamStatus <= 8'h00;
+		RXPacketRdy <= 1'b0;
+		RXFifoWEn <= 1'b0;
+		RXFifoData <= 8'h00;
+		RxPID <= 4'h0;
+	end
+	else 
+	begin
+		RXByteOld <= next_RXByteOld;
+		RXByteOldest <= next_RXByteOldest;
+		CRCError <= next_CRCError;
+		bitStuffError <= next_bitStuffError;
+		RXOverflow <= next_RXOverflow;
+		RXTimeOut <= next_RXTimeOut;
+		NAKRxed <= next_NAKRxed;
+		stallRxed <= next_stallRxed;
+		ACKRxed <= next_ACKRxed;
+		dataSequence <= next_dataSequence;
+		RXByte <= next_RXByte;
+		RXStreamStatus <= next_RXStreamStatus;
+		RXPacketRdy <= next_RXPacketRdy;
+		RXFifoWEn <= next_RXFifoWEn;
+		RXFifoData <= next_RXFifoData;
+		RxPID <= next_RxPID;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hctxportarbiter.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.19
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FREEOID=101
+"LIBRARIES=`timescale 1ns / 1ps\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/20/2004"
+HEADER_PARAM="TITLE,HCTxPortArbiter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 431800,558800
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SEND_PACKET\n/3/"
+S 14 6 12288 ELLIPSE "States" | 269063,296392 6500 6500
+L 13 12 0 TEXT "State Labels" | 191859,293613 1 0 0 "SEND_SOF\n/2/"
+S 12 6 8192 ELLIPSE "States" | 191859,293613 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "WAIT_REQ\n/1/"
+S 10 6 4096 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_HARB\n/0/"
+S 8 6 0 ELLIPSE "States" | 225591,395370 6500 6500
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "HCTxArb"
+F 6 0 671089152 41 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,543100 1 0 0 "Module: HCTxPortArbiter"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+W 28 6 0 12 10 BEZIER "Transitions" | 186560,297376 167155,311353 168429,333163 167686,340659\
+                                      166944,348155 168507,364217 173450,370590 178394,376963\
+                                      186275,384997 193806,383684 201338,382371 213515,373400\
+                                      220004,369229
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+                                      288786,359372 287077,371461 282417,376909 277757,382357\
+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+C 26 17 0 TEXT "Conditions" | 201742,391978 1 0 0 "rst"
+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
+A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxCntl <= `SEND_PACKET_MUX;"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+C 21 20 0 TEXT "Conditions" | 185611,358255 1 0 0 "SOFCntlReq == 1'b1"
+W 20 6 1 10 12 BEZIER "Transitions" | 219884,360995 214322,355742 203672,314353 193976,299756
+W 19 6 2 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210052,391894 219337,393602
+I 16 6 0 Builtin Reset | 178237,395710
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n  `SOF_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= SOFCntlWEn;\n    HCTxPortData <= SOFCntlData;\n    HCTxPortCntl <= SOFCntlCntl;\n  end\n  `DIRECT_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= directCntlWEn;\n    HCTxPortData <= directCntlData;\n    HCTxPortCntl <= directCntlCntl;\n  end\n  `SEND_PACKET_MUX :\n  begin  \n    HCTxPortWEnable <= sendPacketWEn;\n    HCTxPortData <= sendPacketData;\n    HCTxPortCntl <= sendPacketCntl;\n  end\n  default :\n  begin  \n    HCTxPortWEnable <= 1'b0;\n    HCTxPortData <= 8'h00;\n    HCTxPortCntl <= 8'h00;\n  end\nendcase	\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286404,388600 275724,388298\
+                                      265045,387996 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hctxportarbiter.v	(revision 264)
@@ -0,0 +1,210 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\hctxportarbiter.v
+// Generated   : 09/10/04 20:20:21
+// From        : c:\projects\USBHostSlave\RTL\hostController\hctxportarbiter.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (HCTxPortCntl, HCTxPortData, HCTxPortWEnable, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   [7:0] SOFCntlCntl;
+input   [7:0] SOFCntlData;
+input   SOFCntlReq;
+input   SOFCntlWEn;
+input   clk;
+input   [7:0] directCntlCntl;
+input   [7:0] directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0] sendPacketCntl;
+input   [7:0] sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortWEnable;
+output  SOFCntlGnt;
+output  directCntlGnt;
+output  sendPacketGnt;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+reg     HCTxPortWEnable, next_HCTxPortWEnable;
+wire    [7:0] SOFCntlCntl;
+wire    [7:0] SOFCntlData;
+reg     SOFCntlGnt, next_SOFCntlGnt;
+wire    SOFCntlReq;
+wire    SOFCntlWEn;
+wire    clk;
+wire    [7:0] directCntlCntl;
+wire    [7:0] directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+wire    [7:0] sendPacketCntl;
+wire    [7:0] sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg  [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0] CurrState_HCTxArb;
+reg [2:0] NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+		 		 directCntlWEn or directCntlData or directCntlCntl or
+                  directCntlWEn or directCntlData or directCntlCntl or
+ 		  		 sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+    `SOF_CTRL_MUX :
+    begin
+        HCTxPortWEnable <= SOFCntlWEn;
+        HCTxPortData <= SOFCntlData;
+        HCTxPortCntl <= SOFCntlCntl;
+    end
+    `DIRECT_CTRL_MUX :
+    begin
+        HCTxPortWEnable <= directCntlWEn;
+        HCTxPortData <= directCntlData;
+        HCTxPortCntl <= directCntlCntl;
+    end
+    `SEND_PACKET_MUX :
+    begin
+        HCTxPortWEnable <= sendPacketWEn;
+        HCTxPortData <= sendPacketData;
+        HCTxPortCntl <= sendPacketCntl;
+    end
+    default :
+    begin
+        HCTxPortWEnable <= 1'b0;
+        HCTxPortData <= 8'h00;
+        HCTxPortCntl <= 8'h00;
+    end
+endcase
+end
+
+
+//--------------------------------------------------------------------
+// Machine: HCTxArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or muxCntl or sendPacketGnt or directCntlGnt or CurrState_HCTxArb)
+begin : HCTxArb_NextState
+	NextState_HCTxArb <= CurrState_HCTxArb;
+	// Set default values for outputs and signals
+	next_SOFCntlGnt <= SOFCntlGnt;
+	next_muxCntl <= muxCntl;
+	next_sendPacketGnt <= sendPacketGnt;
+	next_directCntlGnt <= directCntlGnt;
+	case (CurrState_HCTxArb) // synopsys parallel_case full_case
+		`START_HARB:
+			NextState_HCTxArb <= `WAIT_REQ;
+		`WAIT_REQ:
+			if (SOFCntlReq == 1'b1)	
+			begin
+				NextState_HCTxArb <= `SEND_SOF;
+				next_SOFCntlGnt <= 1'b1;
+				next_muxCntl <= `SOF_CTRL_MUX;
+			end
+			else if (sendPacketReq == 1'b1)	
+			begin
+				NextState_HCTxArb <= `SEND_PACKET;
+				next_sendPacketGnt <= 1'b1;
+				next_muxCntl <= `SEND_PACKET_MUX;
+			end
+			else if (directCntlReq == 1'b1)	
+			begin
+				NextState_HCTxArb <= `DIRECT_CONTROL;
+				next_directCntlGnt <= 1'b1;
+				next_muxCntl <= `DIRECT_CTRL_MUX;
+			end
+		`SEND_SOF:
+			if (SOFCntlReq == 1'b0)	
+			begin
+				NextState_HCTxArb <= `WAIT_REQ;
+				next_SOFCntlGnt <= 1'b0;
+			end
+		`SEND_PACKET:
+			if (sendPacketReq == 1'b0)	
+			begin
+				NextState_HCTxArb <= `WAIT_REQ;
+				next_sendPacketGnt <= 1'b0;
+			end
+		`DIRECT_CONTROL:
+			if (directCntlReq == 1'b0)	
+			begin
+				NextState_HCTxArb <= `WAIT_REQ;
+				next_directCntlGnt <= 1'b0;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : HCTxArb_CurrentState
+	if (rst)	
+		CurrState_HCTxArb <= `START_HARB;
+	else
+		CurrState_HCTxArb <= NextState_HCTxArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : HCTxArb_RegOutput
+	if (rst)	
+	begin
+		muxCntl <= 2'b00;
+		SOFCntlGnt <= 1'b0;
+		sendPacketGnt <= 1'b0;
+		directCntlGnt <= 1'b0;
+	end
+	else 
+	begin
+		muxCntl <= next_muxCntl;
+		SOFCntlGnt <= next_SOFCntlGnt;
+		sendPacketGnt <= next_sendPacketGnt;
+		directCntlGnt <= next_directCntlGnt;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hostcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hostcontroller.asf	(revision 264)
@@ -0,0 +1,280 @@
+VERSION=1.19
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FREEOID=432
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,hostController"
+END
+BUNDLES
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+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
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+INSTHEADER 51
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+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+F 6 0 671089152 282 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
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+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+A 302 83 16 TEXT "Actions" | 136700,161820 1 0 0 "sendPacketArbiterReq <= 1'b1;"
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+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
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+A 334 332 16 TEXT "Actions" | 87236,105298 1 0 0 "getPacketREn <= 1'b1;"
+C 333 332 0 TEXT "Conditions" | 48120,123470 1 0 0 "sendPacketRdy == 1'b1"
+W 332 66 0 220 331 BEZIER "Transitions" | 82714,126587 85717,114267 91541,91328 94544,79008
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+I 55 52 0 Builtin Entry | 88756,239499
+I 56 52 0 Builtin Exit | 155694,46048
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+C 321 320 0 TEXT "Conditions" | 124852,185328 1 0 0 "sendPacketRdy == 1'b1"
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+                                          110726,37400 115182,37514 117348,37514
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+I 366 73 0 Builtin Entry | 66816,246531
+I 365 73 0 Builtin Exit | 138662,35952
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+                                          129080,35838 133536,35952 135702,35952
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 95 6 0 294 41 BEZIER "Transitions" | 117484,22592 114800,20099 105581,15162 96803,16522\
+                                       88026,17883 53248,36150 43780,48625 34312,61101\
+                                       33772,117285 37441,132224 41110,147164 52980,154980\
+                                       61012,157537 69044,160095 94076,164012 106263,166770
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+A 368 362 4 TEXT "Actions" | 121320,126002 1 0 0 "sendPacketWEn <= 1'b0;"
+I 96 6 0 Builtin Reset | 67359,192312
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+W 371 59 2 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+                                          40160,89849 37728,77233 37462,69633 37196,62033\
+                                          38564,44249 44378,36953 50192,29657 72080,18257\
+                                          79528,15331 86976,12405 94012,13028 97964,12876
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+I 411 59 0 Builtin Exit | 100924,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+                                          134254,207065 123583,209376 117848,210301
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+W 167 59 1 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+I 216 66 0 Builtin Exit | 120308,37514
+I 215 66 0 Builtin Entry | 50996,240683
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+A 231 220 4 TEXT "Actions" | 102966,127564 1 0 0 "sendPacketWEn <= 1'b0;"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hostcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hostcontroller.v	(revision 264)
@@ -0,0 +1,348 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\hostcontroller.v
+// Generated   : 09/14/04 22:52:06
+// From        : c:\projects\USBHostSlave\RTL\hostController\hostcontroller.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input   [7:0] RXStatus;
+input   clk;
+input   getPacketRdy;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   transReq;
+input   [1:0] transType;
+output  clearTXReq;
+output  getPacketREn;
+output  sendPacketArbiterReq;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+output  transDone;
+
+wire    [7:0] RXStatus;
+reg     clearTXReq, next_clearTXReq;
+wire    clk;
+reg     getPacketREn, next_getPacketREn;
+wire    getPacketRdy;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     transDone, next_transDone;
+wire    transReq;
+wire    [1:0] transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 5'b00000
+`define TX_REQ 5'b00001
+`define CHK_TYPE 5'b00010
+`define FLAG 5'b00011
+`define IN_WAIT_DATA_RXED 5'b00100
+`define IN_CHK_FOR_ERROR 5'b00101
+`define IN_CLR_SP_WEN2 5'b00110
+`define SETUP_CLR_SP_WEN1 5'b00111
+`define SETUP_CLR_SP_WEN2 5'b01000
+`define FIN 5'b01001
+`define WAIT_GNT 5'b01010
+`define SETUP_WAIT_PKT_RXED 5'b01011
+`define IN_WAIT_IN_SENT 5'b01100
+`define OUT0_WAIT_RX_DATA 5'b01101
+`define OUT0_WAIT_DATA0_SENT 5'b01110
+`define OUT0_WAIT_OUT_SENT 5'b01111
+`define SETUP_HC_WAIT_RDY 5'b10000
+`define IN_WAIT_SP_RDY1 5'b10001
+`define IN_WAIT_SP_RDY2 5'b10010
+`define OUT0_WAIT_SP_RDY1 5'b10011
+`define SETUP_WAIT_SETUP_SENT 5'b10100
+`define SETUP_WAIT_DATA_SENT 5'b10101
+`define IN_CLR_SP_WEN1 5'b10110
+`define IN_WAIT_ACK_SENT 5'b10111
+`define OUT0_CLR_WEN1 5'b11000
+`define OUT0_CLR_WEN2 5'b11001
+`define OUT1_WAIT_RX_DATA 5'b11010
+`define OUT1_WAIT_OUT_SENT 5'b11011
+`define OUT1_WAIT_DATA1_SENT 5'b11100
+`define OUT1_WAIT_SP_RDY1 5'b11101
+`define OUT1_CLR_WEN1 5'b11110
+`define OUT1_CLR_WEN2 5'b11111
+
+reg [4:0] CurrState_hstCntrl;
+reg [4:0] NextState_hstCntrl;
+
+
+//--------------------------------------------------------------------
+// Machine: hstCntrl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
+begin : hstCntrl_NextState
+	NextState_hstCntrl <= CurrState_hstCntrl;
+	// Set default values for outputs and signals
+	next_sendPacketArbiterReq <= sendPacketArbiterReq;
+	next_transDone <= transDone;
+	next_clearTXReq <= clearTXReq;
+	next_sendPacketWEn <= sendPacketWEn;
+	next_getPacketREn <= getPacketREn;
+	next_sendPacketPID <= sendPacketPID;
+	case (CurrState_hstCntrl) // synopsys parallel_case full_case
+		`START_HC:
+			NextState_hstCntrl <= `TX_REQ;
+		`TX_REQ:
+			if (transReq == 1'b1)	
+			begin
+				NextState_hstCntrl <= `WAIT_GNT;
+				next_sendPacketArbiterReq <= 1'b1;
+			end
+		`CHK_TYPE:
+			if (transType == `IN_TRANS)	
+				NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+			else if (transType == `OUTDATA0_TRANS)	
+				NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+			else if (transType == `OUTDATA1_TRANS)	
+				NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+			else if (transType == `SETUP_TRANS)	
+				NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+		`FLAG:
+		begin
+			next_transDone <= 1'b1;
+			next_clearTXReq <= 1'b1;
+			next_sendPacketArbiterReq <= 1'b0;
+			NextState_hstCntrl <= `FIN;
+		end
+		`FIN:
+		begin
+			next_transDone <= 1'b0;
+			next_clearTXReq <= 1'b0;
+			NextState_hstCntrl <= `TX_REQ;
+		end
+		`WAIT_GNT:
+			if (sendPacketArbiterGnt == 1'b1)	
+				NextState_hstCntrl <= `CHK_TYPE;
+		`SETUP_CLR_SP_WEN1:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+		end
+		`SETUP_CLR_SP_WEN2:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+		end
+		`SETUP_WAIT_PKT_RXED:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `FLAG;
+		end
+		`SETUP_HC_WAIT_RDY:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `SETUP;
+			end
+		`SETUP_WAIT_SETUP_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA0;
+			end
+		`SETUP_WAIT_DATA_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+				next_getPacketREn <= 1'b1;
+			end
+		`IN_WAIT_DATA_RXED:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+		end
+		`IN_CHK_FOR_ERROR:
+			if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+				RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+				RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+				RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+				RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+				RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)	
+				NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+			else
+				NextState_hstCntrl <= `FLAG;
+		`IN_CLR_SP_WEN2:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+		end
+		`IN_WAIT_IN_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+				next_getPacketREn <= 1'b1;
+			end
+		`IN_WAIT_SP_RDY1:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `IN;
+			end
+		`IN_WAIT_SP_RDY2:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `ACK;
+			end
+		`IN_CLR_SP_WEN1:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+		end
+		`IN_WAIT_ACK_SENT:
+			if (sendPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `FLAG;
+		`OUT0_WAIT_RX_DATA:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `FLAG;
+		end
+		`OUT0_WAIT_DATA0_SENT:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+				next_getPacketREn <= 1'b1;
+			end
+		end
+		`OUT0_WAIT_OUT_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT0_CLR_WEN2;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA0;
+			end
+		`OUT0_WAIT_SP_RDY1:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT0_CLR_WEN1;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `OUT;
+			end
+		`OUT0_CLR_WEN1:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+		end
+		`OUT0_CLR_WEN2:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+		end
+		`OUT1_WAIT_RX_DATA:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `FLAG;
+		end
+		`OUT1_WAIT_OUT_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT1_CLR_WEN2;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA1;
+			end
+		`OUT1_WAIT_DATA1_SENT:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+				next_getPacketREn <= 1'b1;
+			end
+		end
+		`OUT1_WAIT_SP_RDY1:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT1_CLR_WEN1;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `OUT;
+			end
+		`OUT1_CLR_WEN1:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+		end
+		`OUT1_CLR_WEN2:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : hstCntrl_CurrentState
+	if (rst)	
+		CurrState_hstCntrl <= `START_HC;
+	else
+		CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : hstCntrl_RegOutput
+	if (rst)	
+	begin
+		transDone <= 1'b0;
+		clearTXReq <= 1'b0;
+		getPacketREn <= 1'b0;
+		sendPacketArbiterReq <= 1'b0;
+		sendPacketWEn <= 1'b0;
+		sendPacketPID <= 4'b0;
+	end
+	else 
+	begin
+		transDone <= next_transDone;
+		clearTXReq <= next_clearTXReq;
+		getPacketREn <= next_getPacketREn;
+		sendPacketArbiterReq <= next_sendPacketArbiterReq;
+		sendPacketWEn <= next_sendPacketWEn;
+		sendPacketPID <= next_sendPacketPID;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/rxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/rxStatusMonitor.v	(revision 264)
@@ -0,0 +1,99 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// rxStatusMonitor.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: rxStatusMonitor.v,v 1.1.1.1 2004-10-11 04:00:53 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+	connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+	if (rst == 1'b1)
+	begin
+		oldConnectState <= connectStateIn;
+		oldResumeDetected <= resumeDetectedIn;
+	end
+	else
+	begin
+		oldConnectState <= connectStateIn;
+		oldResumeDetected <= resumeDetectedIn;
+		if (oldConnectState != connectStateIn)
+			connectionEventOut <= 1'b1;
+		else
+			connectionEventOut <= 1'b0;
+		if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+			resumeIntOut <= 1'b1;
+		else 
+			resumeIntOut <= 1'b0;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacket.asf	(revision 264)
@@ -0,0 +1,238 @@
+VERSION=1.19
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FREEOID=225
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,sendPacket"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
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+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 21
+PAGE 0,0 215900,279400
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+MARGINS 25400,0 0,25400
+END
+INSTHEADER 45
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
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+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "WAIT_ENABLE\n/1/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP\n/0/"
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "sndPkt"
+F 6 0 671089152 188 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: sendPacket"
+I 12 6 0 Builtin Reset | 74872,202290
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+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
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+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
+L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
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+A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;"
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+S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500
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+S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500
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+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
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+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
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+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
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+I 127 65 0 Builtin Exit | 176933,37229
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+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1;	 \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 173 0 2 Builtin InPort | 35299,213676 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 2 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170179,37688 173765,37229
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+I 185 0 2 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 183 0 2 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+                                          48213,88528 42471,75064 41184,67490 39897,59917\
+                                          40491,43087 47668,36800 54846,30514 82962,22198\
+                                          91674,19921 100386,17644 105983,17263 109349,16867
+I 203 0 2 Builtin OutPort | 102204,236768 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 201 0 2 Builtin InPort | 101760,245904 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 199 0 2 Builtin OutPort | 101972,241240 "" ""
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 0 Builtin Signal | 35000,231468 "" ""
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+                                          200128,135446 205472,144130 205681,151728 205890,159327\
+                                          201380,181037 194241,189595 187102,198154 163054,210680\
+                                          152909,214312 142764,217944 127179,220153 118913,221155
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacket.v	(revision 264)
@@ -0,0 +1,297 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacket.v
+// Generated   : 09/25/04 06:36:27
+// From        : c:\projects\USBHostSlave\RTL\hostController\sendpacket.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, rst, sendPacketRdy, sendPacketWEn);
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   [3:0] PID;
+input   [6:0] TxAddr;
+input   clk;
+input   [7:0] fifoData;
+input   fifoEmpty;
+input   rst;
+input   sendPacketWEn;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [3:0] TxEndP;
+output  fifoReadEn;
+output  [10:0] frameNum;
+output  sendPacketRdy;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    [3:0] PID;
+wire    [6:0] TxAddr;
+reg     [3:0] TxEndP, next_TxEndP;
+wire    clk;
+wire    [7:0] fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+reg     [10:0] frameNum, next_frameNum;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+
+reg [4:0] CurrState_sndPkt;
+reg [4:0] NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+    PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+//--------------------------------------------------------------------
+// Machine: sndPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PID or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt)
+begin : sndPkt_NextState
+	NextState_sndPkt <= CurrState_sndPkt;
+	// Set default values for outputs and signals
+	next_sendPacketRdy <= sendPacketRdy;
+	next_HCTxPortReq <= HCTxPortReq;
+	next_HCTxPortWEn <= HCTxPortWEn;
+	next_HCTxPortData <= HCTxPortData;
+	next_HCTxPortCntl <= HCTxPortCntl;
+	next_frameNum <= frameNum;
+	next_fifoReadEn <= fifoReadEn;
+	case (CurrState_sndPkt) // synopsys parallel_case full_case
+		`START_SP:
+			NextState_sndPkt <= `WAIT_ENABLE;
+		`WAIT_ENABLE:
+			if (sendPacketWEn == 1'b1)	
+			begin
+				NextState_sndPkt <= `SP_WAIT_GNT;
+				next_sendPacketRdy <= 1'b0;
+				next_HCTxPortReq <= 1'b1;
+			end
+		`SP_WAIT_GNT:
+			if (HCTxPortGnt == 1'b1)	
+				NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+		`FIN_SP:
+		begin
+			NextState_sndPkt <= `WAIT_ENABLE;
+			next_sendPacketRdy <= 1'b1;
+			next_HCTxPortReq <= 1'b0;
+		end
+		`SEND_PID_WAIT_RDY:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `SEND_PID_FIN;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= PIDNotPID;
+				next_HCTxPortCntl <= `TX_PACKET_START;
+			end
+		`SEND_PID_FIN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			if (PID == `DATA0 || PID == `DATA1)	
+				NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+			else if (PID == `SOF)	
+				NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+			else if (PID == `OUT || 
+				PID == `IN || 
+				PID == `SETUP)	
+				NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+			else
+				NextState_sndPkt <= `FIN_SP;
+		end
+		`OUT_IN_SETUP_WAIT_RDY1:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+				next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			end
+		`OUT_IN_SETUP_WAIT_RDY2:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+				next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			end
+		`OUT_IN_SETUP_FIN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `FIN_SP;
+		end
+		`OUT_IN_SETUP_CLR_WEN1:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+		end
+		`SEND_SOF_FIN1:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			next_frameNum <= frameNum + 1'b1;
+			NextState_sndPkt <= `FIN_SP;
+		end
+		`SEND_SOF_WAIT_RDY3:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= frameNum[7:0];
+				next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			end
+		`SEND_SOF_WAIT_RDY4:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `SEND_SOF_FIN1;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+				next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			end
+		`SEND_SOF_CLR_WEN1:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+		end
+		`DATA0_DATA1_READ_FIFO:
+		begin
+			next_HCTxPortWEn <= 1'b1;
+			next_HCTxPortData <= fifoData;
+			next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+		end
+		`DATA0_DATA1_WAIT_READ_FIFO:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+				next_fifoReadEn <= 1'b1;
+			end
+		`DATA0_DATA1_FIFO_EMPTY:
+			if (fifoEmpty == 1'b0)	
+				NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+			else
+				NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+		`DATA0_DATA1_FIN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `FIN_SP;
+		end
+		`DATA0_DATA1_TERM_BYTE:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `DATA0_DATA1_FIN;
+				//Last byte is not valid data,
+				//but the 'TX_PACKET_STOP' flag is required
+				//by the SIE state machine to detect end of data packet
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= 8'h00;
+				next_HCTxPortCntl <= `TX_PACKET_STOP;
+			end
+		`DATA0_DATA1_CLR_WEN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+		end
+		`DATA0_DATA1_CLR_REN:
+		begin
+			next_fifoReadEn <= 1'b0;
+			NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sndPkt_CurrentState
+	if (rst)	
+		CurrState_sndPkt <= `START_SP;
+	else
+		CurrState_sndPkt <= NextState_sndPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sndPkt_RegOutput
+	if (rst)	
+	begin
+		sendPacketRdy <= 1'b1;
+		HCTxPortReq <= 1'b0;
+		HCTxPortWEn <= 1'b0;
+		HCTxPortData <= 8'h00;
+		HCTxPortCntl <= 8'h00;
+		frameNum <= 11'h000;
+		fifoReadEn <= 1'b0;
+	end
+	else 
+	begin
+		sendPacketRdy <= next_sendPacketRdy;
+		HCTxPortReq <= next_HCTxPortReq;
+		HCTxPortWEn <= next_HCTxPortWEn;
+		HCTxPortData <= next_HCTxPortData;
+		HCTxPortCntl <= next_HCTxPortCntl;
+		frameNum <= next_frameNum;
+		fifoReadEn <= next_fifoReadEn;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketarbiter.asf	(revision 264)
@@ -0,0 +1,96 @@
+VERSION=1.19
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FREEOID=98
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,sendPacketArbiter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: sendPacketArbiter"
+F 6 0 671089152 59 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "sendPktArb"
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_SARB\n/3/"
+S 9 6 12288 ELLIPSE "States" | 128958,117844 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "SARB_WAIT_REQ\n/2/"
+S 11 6 8192 ELLIPSE "States" | 128339,87513 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "SOF_ACT\n/1/"
+S 13 6 4096 ELLIPSE "States" | 95226,16087 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "HC_ACT\n/0/"
+S 15 6 0 ELLIPSE "States" | 172430,18866 6500 6500
+I 20 6 0 Builtin Reset | 86247,136033
+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 114611,125692 123896,121919
+W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
+W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
+W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
+C 29 24 0 TEXT "Conditions" | 88369,77278 1 0 0 "SOFTxReq == 1'b1"
+C 30 23 0 TEXT "Conditions" | 141765,76523 1 0 0 "HCTxReq == 1'b1"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "HCTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b0;"
+I 47 0 2 Builtin OutPort | 89651,157673 "" ""
+L 46 47 0 TEXT "Labels" | 95651,157673 1 0 0 "SOFTxGnt"
+I 45 0 130 Builtin OutPort | 162661,153684 "" ""
+L 44 45 0 TEXT "Labels" | 168661,153684 1 0 0 "sendPacketPID[3:0]"
+I 43 0 2 Builtin OutPort | 162738,158202 "" ""
+L 42 43 0 TEXT "Labels" | 168738,158202 1 0 0 "sendPacketWEnable"
+I 41 0 2 Builtin OutPort | 36274,157869 "" ""
+L 40 41 0 TEXT "Labels" | 42274,157869 1 0 0 "HCTxGnt"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "SOFTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b1;"
+A 39 9 2 TEXT "Actions" | 134973,143961 1 0 0 "SOFTxGnt <= 1'b0;\nHCTxGnt <= 1'b0; \nmuxSOFNotHC <= 1'b0;"
+C 62 21 0 TEXT "Conditions" | 108713,128484 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 53 0 130 Builtin InPort | 38410,162874 "" ""
+L 52 53 0 TEXT "Labels" | 44410,162874 1 0 0 "HC_PID[3:0]"
+I 51 0 2 Builtin InPort | 38527,153081 "" ""
+L 50 51 0 TEXT "Labels" | 44527,153081 1 0 0 "HCTxReq"
+I 49 0 2 Builtin InPort | 92038,153080 "" ""
+L 48 49 0 TEXT "Labels" | 98038,153080 1 0 0 "SOFTxReq"
+C 71 65 0 TEXT "Conditions" | 184576,32757 1 0 0 "HCTxReq == 1'b0"
+W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
+                                      200193,83454 202194,93721 199799,97969 197405,102218\
+                                      189371,107780 182843,108050 176316,108321 158239,103840\
+                                      151634,101445 145030,99051 137656,94031 133485,91482
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+I 89 0 2 Builtin InPort | 92234,162554 "" ""
+L 86 85 0 TEXT "Labels" | 44222,167883 1 0 0 "HC_SP_WEn"
+I 85 0 2 Builtin InPort | 38222,167883 "" ""
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "HCTxGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+                                      70311,70629 71874,86691 76817,93064 81761,99437\
+                                      89642,107471 97173,106158 104705,104845 116882,95874\
+                                      123371,91703
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "SOFTxGnt <= 1'b0;"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)  \nbegin\n  if (muxSOFNotHC  == 1'b1)  \n  begin\n    sendPacketWEnable <= SOF_SP_WEn;\n    sendPacketPID <= `SOF;\n  end\n  else\n  begin\n    sendPacketWEnable <= HC_SP_WEn;\n    sendPacketPID <= HC_PID;\n  end\nend"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketarbiter.v	(revision 264)
@@ -0,0 +1,153 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacketarbiter.v
+// Generated   : 09/10/04 20:20:24
+// From        : c:\projects\USBHostSlave\RTL\hostController\sendpacketarbiter.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (HCTxGnt, HCTxReq, HC_PID, HC_SP_WEn, SOFTxGnt, SOFTxReq, SOF_SP_WEn, clk, rst, sendPacketPID, sendPacketWEnable);
+input   HCTxReq;
+input   [3:0] HC_PID;
+input   HC_SP_WEn;
+input   SOFTxReq;
+input   SOF_SP_WEn;
+input   clk;
+input   rst;
+output  HCTxGnt;
+output  SOFTxGnt;
+output  [3:0] sendPacketPID;
+output  sendPacketWEnable;
+
+reg     HCTxGnt, next_HCTxGnt;
+wire    HCTxReq;
+wire    [3:0] HC_PID;
+wire    HC_SP_WEn;
+reg     SOFTxGnt, next_SOFTxGnt;
+wire    SOFTxReq;
+wire    SOF_SP_WEn;
+wire    clk;
+wire    rst;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+reg     sendPacketWEnable, next_sendPacketWEnable;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0] CurrState_sendPktArb;
+reg [1:0] NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+    if (muxSOFNotHC  == 1'b1)
+    begin
+        sendPacketWEnable <= SOF_SP_WEn;
+        sendPacketPID <= `SOF;
+    end
+    else
+    begin
+        sendPacketWEnable <= HC_SP_WEn;
+        sendPacketPID <= HC_PID;
+    end
+end
+
+
+//--------------------------------------------------------------------
+// Machine: sendPktArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin : sendPktArb_NextState
+	NextState_sendPktArb <= CurrState_sendPktArb;
+	// Set default values for outputs and signals
+	next_HCTxGnt <= HCTxGnt;
+	next_SOFTxGnt <= SOFTxGnt;
+	next_muxSOFNotHC <= muxSOFNotHC;
+	case (CurrState_sendPktArb) // synopsys parallel_case full_case
+		`HC_ACT:
+			if (HCTxReq == 1'b0)	
+			begin
+				NextState_sendPktArb <= `SARB_WAIT_REQ;
+				next_HCTxGnt <= 1'b0;
+			end
+		`SOF_ACT:
+			if (SOFTxReq == 1'b0)	
+			begin
+				NextState_sendPktArb <= `SARB_WAIT_REQ;
+				next_SOFTxGnt <= 1'b0;
+			end
+		`SARB_WAIT_REQ:
+			if (SOFTxReq == 1'b1)	
+			begin
+				NextState_sendPktArb <= `SOF_ACT;
+				next_SOFTxGnt <= 1'b1;
+				next_muxSOFNotHC <= 1'b1;
+			end
+			else if (HCTxReq == 1'b1)	
+			begin
+				NextState_sendPktArb <= `HC_ACT;
+				next_HCTxGnt <= 1'b1;
+				next_muxSOFNotHC <= 1'b0;
+			end
+		`START_SARB:
+			NextState_sendPktArb <= `SARB_WAIT_REQ;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktArb_CurrentState
+	if (rst)	
+		CurrState_sendPktArb <= `START_SARB;
+	else
+		CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktArb_RegOutput
+	if (rst)	
+	begin
+		muxSOFNotHC <= 1'b0;
+		SOFTxGnt <= 1'b0;
+		HCTxGnt <= 1'b0;
+	end
+	else 
+	begin
+		muxSOFNotHC <= next_muxSOFNotHC;
+		SOFTxGnt <= next_SOFTxGnt;
+		HCTxGnt <= next_HCTxGnt;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketcheckpreamble.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketcheckpreamble.asf	(revision 264)
@@ -0,0 +1,149 @@
+VERSION=1.19
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FREEOID=153
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,sendPacketCheckPreamble"
+END
+BUNDLES
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+END
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+PAGE 0,0 215900,279400
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+END
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+END
+INSTHEADER 95
+PAGE 0,0 215900,279400
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+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
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+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
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+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
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+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
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+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
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+A 59 56 16 TEXT "Actions" | 87075,172050 1 0 0 "sendPacketWEn <= 1'b0;"
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
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+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+A 66 65 16 TEXT "Actions" | 90202,77286 1 0 0 "sendPacketWEn <= 1'b0;"
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+I 75 0 2 Builtin OutPort | 29624,223586 "" ""
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+I 77 0 2 Builtin OutPort | 29360,218796 "" ""
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+I 79 0 2 Builtin OutPort | 29397,214093 "" ""
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
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+I 106 98 0 Builtin Exit | 199200,49878
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+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
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+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
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+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+                                        94907,51569 61918,50756 52575,52503 43232,54250\
+                                        38843,62050 37706,72734 36569,83418 36406,118357\
+                                        40062,129609 43718,140862 58507,150938 67687,153172\
+                                        76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 95904,234688 "" ""
+L 150 151 0 TEXT "Labels" | 101904,234688 1 0 0 "preAmbleEnable"
+K 149 75 0 TEXT "Comments" | 60868,223364 1 0 0 "mux select"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nfullSpeedBitRate <= 1'b0;\nfullSpeedPolarity <= 1'b0;\ngrabLineControl <= 1'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketcheckpreamble.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketcheckpreamble.v	(revision 264)
@@ -0,0 +1,192 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacketcheckpreamble.v
+// Generated   : 09/10/04 20:20:24
+// From        : c:\projects\USBHostSlave\RTL\hostController\sendpacketcheckpreamble.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   preAmbleEnable;
+input   rst;
+input   [3:0] sendPacketCPPID;
+input   sendPacketCPWEn;
+input   sendPacketRdy;
+output  fullSpeedBitRate;
+output  fullSpeedPolarity;
+output  grabLineControl;		// mux select
+output  sendPacketCPReady;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+
+wire    clk;
+reg     fullSpeedBitRate, next_fullSpeedBitRate;
+reg     fullSpeedPolarity, next_fullSpeedPolarity;
+reg     grabLineControl, next_grabLineControl;
+wire    preAmbleEnable;
+wire    rst;
+wire    [3:0] sendPacketCPPID;
+reg     sendPacketCPReady, next_sendPacketCPReady;
+wire    sendPacketCPWEn;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_WAIT_RDY2 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_WAIT_RDY3 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+
+reg [3:0] CurrState_sendPktCP;
+reg [3:0] NextState_sendPktCP;
+
+
+//--------------------------------------------------------------------
+// Machine: sendPktCP
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
+begin : sendPktCP_NextState
+	NextState_sendPktCP <= CurrState_sendPktCP;
+	// Set default values for outputs and signals
+	next_sendPacketCPReady <= sendPacketCPReady;
+	next_sendPacketWEn <= sendPacketWEn;
+	next_sendPacketPID <= sendPacketPID;
+	next_fullSpeedBitRate <= fullSpeedBitRate;
+	next_fullSpeedPolarity <= fullSpeedPolarity;
+	next_grabLineControl <= grabLineControl;
+	case (CurrState_sendPktCP) // synopsys parallel_case full_case
+		`SPC_WAIT_EN:
+			if (sendPacketCPWEn == 1'b1)	
+			begin
+				NextState_sendPktCP <= `CHK_PREAM;
+				next_sendPacketCPReady <= 1'b0;
+			end
+		`START_SPC:
+			NextState_sendPktCP <= `SPC_WAIT_EN;
+		`CHK_PREAM:
+			if (preAmbleEnable == 1'b1)	
+				NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+			else
+				NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+		`READY:
+		begin
+			next_sendPacketCPReady <= 1'b1;
+			NextState_sendPktCP <= `SPC_WAIT_EN;
+		end
+		`PREAM_PKT_SND_PREAM:
+		begin
+			next_sendPacketWEn <= 1'b1;
+			next_sendPacketPID <= `PREAMBLE;
+			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+			next_sendPacketWEn <= 1'b0;
+		end
+		`PREAM_PKT_WAIT_RDY1:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+				next_fullSpeedBitRate <= 1'b1;
+				next_fullSpeedPolarity <= 1'b1;
+				next_grabLineControl <= 1'b1;
+			end
+		`PREAM_PKT_WAIT_RDY2:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+				next_fullSpeedBitRate <= 1'b1;
+			end
+		`PREAM_PKT_SND_PID:
+		begin
+			next_sendPacketWEn <= 1'b1;
+			next_sendPacketPID <= sendPacketCPPID;
+			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+			next_sendPacketWEn <= 1'b0;
+		end
+		`PREAM_PKT_WAIT_RDY3:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_sendPktCP <= `READY;
+				next_grabLineControl <= 1'b0;
+			end
+		`REG_PKT_SEND_PID:
+		begin
+			next_sendPacketWEn <= 1'b1;
+			next_sendPacketPID <= sendPacketCPPID;
+			NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+		end
+		`REG_PKT_WAIT_RDY1:
+			if (sendPacketRdy == 1'b1)	
+				NextState_sendPktCP <= `REG_PKT_SEND_PID;
+		`REG_PKT_WAIT_RDY:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_sendPktCP <= `READY;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktCP_CurrentState
+	if (rst)	
+		CurrState_sendPktCP <= `START_SPC;
+	else
+		CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktCP_RegOutput
+	if (rst)	
+	begin
+		sendPacketWEn <= 1'b0;
+		sendPacketPID <= 4'b0;
+		fullSpeedBitRate <= 1'b0;
+		fullSpeedPolarity <= 1'b0;
+		grabLineControl <= 1'b0;
+		sendPacketCPReady <= 1'b1;
+	end
+	else 
+	begin
+		sendPacketWEn <= next_sendPacketWEn;
+		sendPacketPID <= next_sendPacketPID;
+		fullSpeedBitRate <= next_fullSpeedBitRate;
+		fullSpeedPolarity <= next_fullSpeedPolarity;
+		grabLineControl <= next_grabLineControl;
+		sendPacketCPReady <= next_sendPacketCPReady;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sofcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sofcontroller.asf	(revision 264)
@@ -0,0 +1,96 @@
+VERSION=1.19
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FREEOID=65
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/19/2004"
+HEADER_PARAM="TITLE,SOFController"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: SOFController"
+F 6 0 671089152 16 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "sofCntl"
+L 8 9 0 TEXT "State Labels" | 101706,207040 1 0 0 "START_SC\n/0/"
+S 9 6 0 ELLIPSE "States" | 101706,207040 6500 6500
+L 10 11 0 TEXT "State Labels" | 102510,174880 1 0 0 "WAIT_SOF_EN\n/1/"
+S 11 6 4096 ELLIPSE "States" | 102510,174880 6500 6500
+W 12 6 0 9 11 BEZIER "Transitions" | 101472,200547 101472,195422 101786,186460 101786,181335
+I 13 6 0 Builtin Reset | 56682,217090
+W 14 6 0 13 9 BEZIER "Transitions" | 56682,217090 66531,215181 85597,210696 95446,208787
+L 15 16 0 TEXT "Labels" | 186096,262516 1 0 0 "clk"
+I 16 0 3 Builtin InPort | 180096,262516 "" ""
+L 17 18 0 TEXT "Labels" | 185694,255682 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 179694,255682 "" ""
+C 19 14 0 TEXT "Conditions" | 80380,211899 1 0 0 "rst"
+L 20 21 0 TEXT "State Labels" | 104118,144730 1 0 0 "WAIT_SEND_RESUME\n/2/"
+S 21 6 8192 ELLIPSE "States" | 104118,144730 6500 6500
+W 22 6 0 11 50 BEZIER "Transitions" | 102807,168391 103209,163969 153274,157911 158500,157308
+L 23 24 0 TEXT "State Labels" | 107147,54820 1 0 0 "INC_TIMER\n/3/"
+S 24 6 12288 ELLIPSE "States" | 107147,54820 6500 6500
+W 25 6 0 21 62 BEZIER "Transitions" | 104501,138249 108970,126031 113441,113813 117910,101595
+C 26 22 0 TEXT "Conditions" | 109587,169712 1 0 0 "SOFEnable == 1'b1"
+C 27 25 0 TEXT "Conditions" | 106980,134689 1 0 0 "HCTxPortRdy == 1'b1"
+A 29 25 16 TEXT "Actions" | 99582,127475 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_RESUME_START;"
+A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n  SOFTimer <= 16'h0000;\nelse\n  SOFTimer <= SOFTimer + 1'b1;"
+W 33 6 0 24 11 BEZIER "Transitions" | 101788,58497 95658,55482 71624,73399 68189,77671\
+                                      64755,81944 65727,99405 63767,113072 61807,126740\
+                                      62411,169554 65777,180659 69144,191764 82008,193372\
+                                      86530,192015 91053,190659 96125,183689 98738,180172
+C 35 33 0 TEXT "Conditions" | 56071,65104 1 0 0 "SOFEnable == 1'b0"
+L 36 37 0 TEXT "Labels" | 26502,239200 1 0 0 "SOFTimer[15:0]"
+I 37 0 2 Builtin OutPort | 20502,239200 "" ""
+L 38 39 0 TEXT "Labels" | 28914,244024 1 0 0 "SOFEnable"
+I 39 0 2 Builtin InPort | 22914,244024 "" ""
+L 40 41 0 TEXT "Labels" | 90018,239200 1 0 0 "HCTxPortRdy"
+I 41 0 2 Builtin InPort | 84018,239200 "" ""
+I 42 0 2 Builtin OutPort | 81638,244416 "" ""
+L 43 42 0 TEXT "Labels" | 87638,244416 1 0 0 "HCTxPortWEn"
+I 44 0 2 Builtin OutPort | 81915,250446 "" ""
+L 45 44 0 TEXT "Labels" | 87915,250446 1 0 0 "HCTxPortData[7:0]"
+I 46 0 2 Builtin OutPort | 81312,256878 "" ""
+L 47 46 0 TEXT "Labels" | 87312,256878 1 0 0 "HCTxPortCntl[7:0]"
+I 60 0 2 Builtin InPort | 23316,251905 "" ""
+L 59 60 0 TEXT "Labels" | 29316,251905 1 0 0 "SOFTimerClr"
+A 48 9 2 TEXT "Actions" | 114168,219502 1 0 0 "SOFTimer <= 16'h0000;\nHCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+L 49 50 0 TEXT "State Labels" | 162077,151882 1 0 0 "SC_WAIT_GNT\n/4/"
+S 50 6 16384 ELLIPSE "States" | 162077,151882 6500 6500
+W 51 6 0 50 21 BEZIER "Transitions" | 155785,150253 143926,148645 122475,143375 110616,144581
+C 52 51 0 TEXT "Conditions" | 129444,145489 1 0 0 "HCTxPortGnt == 1'b1"
+A 53 22 16 TEXT "Actions" | 118898,162608 1 0 0 "HCTxPortReq <= 1'b1;"
+A 54 33 16 TEXT "Actions" | 41502,87168 1 0 0 "SOFTimer <= 16'h0000;"
+L 55 56 0 TEXT "Labels" | 139062,239200 1 0 0 "HCTxPortReq"
+I 56 0 2 Builtin OutPort | 133062,239200 "" ""
+L 57 58 0 TEXT "Labels" | 141474,244024 1 0 0 "HCTxPortGnt"
+I 58 0 2 Builtin InPort | 135474,244024 "" ""
+L 61 62 0 TEXT "State Labels" | 118352,95112 1 0 0 "CLR_WEN\n/5/"
+S 62 6 20480 ELLIPSE "States" | 118352,95112 6500 6500
+A 63 62 4 TEXT "Actions" | 137072,99272 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 64 6 0 62 24 BEZIER "Transitions" | 116496,88885 114624,81865 110713,68112 108841,61092
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/softransmit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/softransmit.asf	(revision 264)
@@ -0,0 +1,101 @@
+VERSION=1.19
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FREEOID=73
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,SOFTransmit"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+F 6 0 671089152 54 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+                                     119442,151760 119430,151725 119430,151571
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+I 16 6 0 Builtin Reset | 76112,190530
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;"
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+W 51 6 0 26 11 BEZIER "Transitions" | 117404,14128 103585,14128 76675,12449 68441,16586\
+                                      60208,20724 54912,37274 53629,49148 52346,61023\
+                                      52495,91978 54333,104221 56172,116465 66907,131666\
+                                      73940,137333 80974,143001 92272,144264 98160,144352\
+                                      104049,144440 109926,143957 113732,143626
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+A 67 51 16 TEXT "Actions" | 33349,35565 1 0 0 "sendPacketArbiterReq <= 1'b0;"
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+                                         105450,47318 105450,38252 107207,34228 108965,30205\
+                                         115846,23167 119361,19652
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/speedCtrlMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/speedCtrlMux.v	(revision 264)
@@ -0,0 +1,82 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// speedCtrlMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: speedCtrlMux.v,v 1.1.1.1 2004-10-11 04:00:55 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input   directCtrlRate;
+input   directCtrlPol;
+input   sendPacketRate;
+input   sendPacketPol;
+input   sendPacketSel;
+output  fullSpeedRate;
+output  fullSpeedPol;
+
+wire   directCtrlRate;
+wire   directCtrlPol;
+wire   sendPacketRate;
+wire   sendPacketPol;
+wire   sendPacketSel;
+reg   fullSpeedRate;
+reg   fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+  if (sendPacketSel == 1'b1) 
+  begin
+	fullSpeedRate <= sendPacketRate;
+	fullSpeedPol <= sendPacketPol;
+  end
+  else
+  begin
+	fullSpeedRate <= directCtrlRate;
+	fullSpeedPol <= directCtrlPol;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostSlaveMux/hostSlaveMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostSlaveMux/hostSlaveMux.v	(revision 264)
@@ -0,0 +1,168 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostSlaveMux.v,v 1.1.1.1 2004-10-11 04:00:56 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module hostSlaveMux (
+	SIEPortCtrlInToSIE,
+	SIEPortCtrlInFromHost,
+	SIEPortCtrlInFromSlave,
+	SIEPortDataInToSIE, 
+	SIEPortDataInFromHost, 
+	SIEPortDataInFromSlave, 
+	SIEPortWEnToSIE, 
+	SIEPortWEnFromHost, 
+	SIEPortWEnFromSlave, 
+	fullSpeedPolarityToSIE,
+	fullSpeedPolarityFromHost,
+	fullSpeedPolarityFromSlave,
+	fullSpeedBitRateToSIE,
+	fullSpeedBitRateFromHost,
+	fullSpeedBitRateFromSlave,
+  dataIn, 
+  dataOut, 
+  writeEn,
+  strobe_i,
+  clk, 
+  rst,
+  hostSlaveMuxSel  );
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE; 
+input [7:0] SIEPortDataInFromHost; 
+input [7:0] SIEPortDataInFromSlave; 
+output SIEPortWEnToSIE; 
+input SIEPortWEnFromHost; 
+input SIEPortWEnFromSlave; 
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE; 
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+reg SIEPortWEnToSIE; 
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+	SIEPortCtrlInFromHost or
+	SIEPortCtrlInFromSlave or
+	SIEPortDataInFromHost or 
+	SIEPortDataInFromSlave or 
+	SIEPortWEnFromHost or 
+	SIEPortWEnFromSlave or 
+	fullSpeedPolarityFromHost or
+	fullSpeedPolarityFromSlave or
+	fullSpeedBitRateFromHost or
+	fullSpeedBitRateFromSlave)
+begin
+  if (hostMode == 1'b1) 
+  begin
+	  SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+	  SIEPortDataInToSIE <=	SIEPortDataInFromHost;
+	  SIEPortWEnToSIE <= SIEPortWEnFromHost;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+  end
+  else
+  begin
+	  SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+	  SIEPortDataInToSIE <=	SIEPortDataInFromSlave;
+	  SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+  end
+end      
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(dataIn), 
+  .dataOut(dataOut), 
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+	.hostMode(hostMode), 
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbConstants_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbConstants_h.v	(revision 264)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbConstants_h.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  USB global constants as defined by USB spec 1.1
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbConstants_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc 
+	   
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+       
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbSlaveControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbSlaveControl_h.v	(revision 264)
@@ -0,0 +1,122 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSlaveControl_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+//endPointConstants 
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices 
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices 
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices 
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+//SCMasterControlegIndices 
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices 
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes 
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts 
+`define SC_RX_PACKET_TOUT 18
+       

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/SIETransmitter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/SIETransmitter.v	(revision 264)
@@ -0,0 +1,674 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\SIETransmitter.v
+// Generated   : 09/27/04 21:05:15
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\SIETransmitter.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOut, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst, rstCRC);
+input   [15:0] CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0] CRC5Result;
+input   CRC5UpdateRdy;
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [7:0] SIEPortCtrlIn;
+input   [7:0] SIEPortDataIn;
+input   SIEPortWEn;
+input   USBWireGnt;
+input   USBWireRdy;
+input   clk;
+input   processTxByteRdy;
+input   rst;
+output  CRC16En;
+output  CRC5En;
+output  CRC5_8Bit;
+output  [7:0] CRCData;
+output  SIEPortTxRdy;
+output  [7:0] TxByteOutCtrl;
+output  [7:0] TxByteOut;
+output  USBWireCtrl;
+output  [1:0] USBWireData;
+output  USBWireReq;
+output  USBWireWEn;
+output  processTxByteWEn;
+output  rstCRC;
+
+reg     CRC16En, next_CRC16En;
+wire    [15:0] CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5En, next_CRC5En;
+wire    [4:0] CRC5Result;
+wire    CRC5UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     [7:0] CRCData, next_CRCData;
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [7:0] SIEPortCtrlIn;
+wire    [7:0] SIEPortDataIn;
+reg     SIEPortTxRdy, next_SIEPortTxRdy;
+wire    SIEPortWEn;
+reg     [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
+reg     [7:0] TxByteOut, next_TxByteOut;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0] USBWireData, next_USBWireData;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+wire    processTxByteRdy;
+reg     processTxByteWEn, next_processTxByteWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+
+// diagram signals declarations
+reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg  [7:0]SIEPortData, next_SIEPortData;
+reg  [4:0]i, next_i;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define RES_ST_CHK_FIN 6'b000000
+`define IDLE_CHK_FIN 6'b000001
+`define DIR_CTL_CHK_FIN 6'b000010
+`define PKT_ST_CHK_PID 6'b000011
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
+`define PKT_ST_SPCL_PKT_SENT 6'b000101
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
+`define PKT_ST_TKN_PID_PKT_SENT 6'b000111
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b001000
+`define PKT_ST_DATA_PID_PKT_SENT 6'b001001
+`define PKT_ST_HS_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_S1 6'b001110
+`define RES_ST_S3 6'b001111
+`define RES_ST_S4 6'b010000
+`define RES_ST_S5 6'b010001
+`define RES_ST_S6 6'b010010
+`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
+`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
+`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
+`define START_SIETX 6'b010110
+`define STX_CHK_ST 6'b010111
+`define STX_WAIT_BYTE 6'b011000
+`define IDLE_STX_WAIT_GNT 6'b011001
+`define IDLE_STX_WAIT_RDY 6'b011010
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b011100
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011101
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
+`define DIR_CTL_WAIT_GNT 6'b100001
+`define RES_ST_WAIT_GNT 6'b100010
+`define PKT_ST_HS_WAIT_RDY 6'b100011
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100100
+`define PKT_ST_SPCL_WAIT_RDY 6'b100101
+`define RES_ST_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100111
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b101001
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b101010
+`define DIR_CTL_WAIT_RDY 6'b101011
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
+`define PKT_ST_WAIT_RDY_PKT 6'b101110
+`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
+`define PKT_ST_WAIT_RDY_WIRE 6'b110000
+`define PKT_ST_WAIT_GNT 6'b110001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b110010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b110011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110100
+
+reg [5:0] CurrState_SIETx;
+reg [5:0] NextState_SIETx;
+
+
+//--------------------------------------------------------------------
+// Machine: SIETx
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SIEPortDataIn or SIEPortCtrlIn or i or SIEPortData or JBit or CRC16Result or CRC5Result or KBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
+begin : SIETx_NextState
+	NextState_SIETx <= CurrState_SIETx;
+	// Set default values for outputs and signals
+	next_processTxByteWEn <= processTxByteWEn;
+	next_TxByteOut <= TxByteOut;
+	next_TxByteOutCtrl <= TxByteOutCtrl;
+	next_USBWireData <= USBWireData;
+	next_USBWireCtrl <= USBWireCtrl;
+	next_USBWireReq <= USBWireReq;
+	next_USBWireWEn <= USBWireWEn;
+	next_rstCRC <= rstCRC;
+	next_CRCData <= CRCData;
+	next_CRC5En <= CRC5En;
+	next_CRC5_8Bit <= CRC5_8Bit;
+	next_CRC16En <= CRC16En;
+	next_SIEPortTxRdy <= SIEPortTxRdy;
+	next_SIEPortData <= SIEPortData;
+	next_SIEPortCtrl <= SIEPortCtrl;
+	next_i <= i;
+	case (CurrState_SIETx) // synopsys parallel_case full_case
+		`START_SIETX:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			next_TxByteOut <= 8'h00;
+			next_TxByteOutCtrl <= 8'h00;
+			next_USBWireData <= 2'b00;
+			next_USBWireCtrl <= `TRI_STATE;
+			next_USBWireReq <= 1'b0;
+			next_USBWireWEn <= 1'b0;
+			next_rstCRC <= 1'b0;
+			next_CRCData <= 8'h00;
+			next_CRC5En <= 1'b0;
+			next_CRC5_8Bit <= 1'b0;
+			next_CRC16En <= 1'b0;
+			next_SIEPortTxRdy <= 1'b0;
+			next_SIEPortData <= 8'h00;
+			next_SIEPortCtrl <= 8'h00;
+			next_i <= 5'h0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`STX_CHK_ST:
+			if (SIEPortCtrl == `TX_PACKET_START)	
+			begin
+				NextState_SIETx <= `PKT_ST_WAIT_GNT;
+				next_USBWireReq <= 1'b1;
+			end
+			else if (SIEPortCtrl == `TX_IDLE)	
+			begin
+				NextState_SIETx <= `IDLE_STX_WAIT_GNT;
+				next_USBWireReq <= 1'b1;
+			end
+			else if (SIEPortCtrl == `TX_DIRECT_CONTROL)	
+			begin
+				NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+				next_USBWireReq <= 1'b1;
+			end
+			else if (SIEPortCtrl == `TX_RESUME_START)	
+			begin
+				NextState_SIETx <= `RES_ST_WAIT_GNT;
+				next_USBWireReq <= 1'b1;
+				next_i <= 5'h0;
+			end
+		`STX_WAIT_BYTE:
+		begin
+			next_SIEPortTxRdy <= 1'b1;
+			if (SIEPortWEn == 1'b1)	
+			begin
+				NextState_SIETx <= `STX_CHK_ST;
+				next_SIEPortData <= SIEPortDataIn;
+				next_SIEPortCtrl <= SIEPortCtrlIn;
+				next_SIEPortTxRdy <= 1'b0;
+			end
+		end
+		`DIR_CTL_CHK_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_i <= i + 1'b1;
+			if (i == 5'h7)	
+			begin
+				NextState_SIETx <= `STX_WAIT_BYTE;
+				next_USBWireReq <= 1'b0;
+			end
+			else
+				NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+		end
+		`DIR_CTL_WAIT_GNT:
+		begin
+			next_i <= 5'h0;
+			if (USBWireGnt == 1'b1)	
+				NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+		end
+		`DIR_CTL_WAIT_RDY:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `DIR_CTL_CHK_FIN;
+				next_USBWireData <= SIEPortData[1:0];
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`IDLE_CHK_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_i <= i + 1'b1;
+			if (i == 5'h7)	
+			begin
+				NextState_SIETx <= `STX_WAIT_BYTE;
+				next_USBWireReq <= 1'b0;
+			end
+			else
+				NextState_SIETx <= `IDLE_STX_WAIT_RDY;
+		end
+		`IDLE_STX_WAIT_GNT:
+		begin
+			next_i <= 5'h0;
+			if (USBWireGnt == 1'b1)	
+				NextState_SIETx <= `IDLE_STX_WAIT_RDY;
+		end
+		`IDLE_STX_WAIT_RDY:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `IDLE_CHK_FIN;
+				next_USBWireData <= 2'b00;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`PKT_ST_CHK_PID:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			if (SIEPortData[1:0] == `HANDSHAKE)	
+				NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+			else if (SIEPortData[1:0] == `TOKEN)	
+				NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+			else if (SIEPortData[1:0] == `SPECIAL)	
+				NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+			else if (SIEPortData[1:0] == `DATA)	
+				NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+		end
+		`PKT_ST_WAIT_RDY_PKT:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_USBWireReq <= 1'b0;
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_CHK_PID;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= `SYNC_BYTE;
+				next_TxByteOutCtrl <= `DATA_START;
+			end
+		end
+		`PKT_ST_WAIT_RDY_WIRE:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+				//actively drive the first J bit
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`PKT_ST_WAIT_GNT:
+			if (USBWireGnt == 1'b1)	
+				NextState_SIETx <= `PKT_ST_WAIT_RDY_WIRE;
+		`PKT_ST_DATA_CRC_PKT_SENT1:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+		end
+		`PKT_ST_DATA_CRC_PKT_SENT2:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`PKT_ST_DATA_CRC_WAIT_RDY1:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= ~CRC16Result[7:0];
+				next_TxByteOutCtrl <= `DATA_STREAM;
+			end
+		`PKT_ST_DATA_CRC_WAIT_RDY2:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= ~CRC16Result[15:8];
+				next_TxByteOutCtrl <= `DATA_STOP;
+			end
+		`PKT_ST_DATA_DATA_CHK_STOP:
+			if (SIEPortCtrl == `TX_PACKET_STOP)	
+				NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+			else
+				NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+		`PKT_ST_DATA_DATA_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+		end
+		`PKT_ST_DATA_DATA_UPD_CRC:
+		begin
+			next_CRCData <= SIEPortData;
+			next_CRC16En <= 1'b1;
+			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+		end
+		`PKT_ST_DATA_DATA_WAIT_BYTE:
+		begin
+			next_SIEPortTxRdy <= 1'b1;
+			if (SIEPortWEn == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+				next_SIEPortData <= SIEPortDataIn;
+				next_SIEPortCtrl <= SIEPortCtrlIn;
+				next_SIEPortTxRdy <= 1'b0;
+			end
+		end
+		`PKT_ST_DATA_DATA_WAIT_RDY:
+		begin
+			next_CRC16En <= 1'b0;
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STREAM;
+			end
+		end
+		`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+			if (CRC16UpdateRdy == 1'b1)	
+				NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+		`PKT_ST_DATA_PID_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			next_rstCRC <= 1'b0;
+			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+		end
+		`PKT_ST_DATA_PID_WAIT_RDY:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STREAM;
+				next_rstCRC <= 1'b1;
+			end
+		`PKT_ST_HS_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`PKT_ST_HS_WAIT_RDY:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STOP;
+			end
+		`PKT_ST_SPCL_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
+		end
+		`PKT_ST_SPCL_SEND_IDLE1:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`PKT_ST_SPCL_SEND_IDLE2:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`PKT_ST_SPCL_SEND_IDLE3:
+		begin
+			next_USBWireWEn <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`PKT_ST_SPCL_WAIT_RDY:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STOP;
+			end
+		`PKT_ST_SPCL_WAIT_WIRE:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`PKT_ST_TKN_BYTE1_PKT_SENT1:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+		end
+		`PKT_ST_TKN_BYTE1_UPD_CRC:
+		begin
+			next_CRCData <= SIEPortData;
+			next_CRC5_8Bit <= 1'b1;
+			next_CRC5En <= 1'b1;
+			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+		end
+		`PKT_ST_TKN_BYTE1_WAIT_BYTE:
+		begin
+			next_SIEPortTxRdy <= 1'b1;
+			if (SIEPortWEn == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+				next_SIEPortData <= SIEPortDataIn;
+				next_SIEPortCtrl <= SIEPortCtrlIn;
+				next_SIEPortTxRdy <= 1'b0;
+			end
+		end
+		`PKT_ST_TKN_BYTE1_WAIT_RDY:
+		begin
+			next_CRC5En <= 1'b0;
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STREAM;
+			end
+		end
+		`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+			if (CRC5UpdateRdy == 1'b1)	
+				NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+		`PKT_ST_TKN_CRC_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`PKT_ST_TKN_CRC_UPD_CRC:
+		begin
+			next_CRCData <= SIEPortData;
+			next_CRC5_8Bit <= 1'b0;
+			next_CRC5En <= 1'b1;
+			NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+		end
+		`PKT_ST_TKN_CRC_WAIT_BYTE:
+		begin
+			next_SIEPortTxRdy <= 1'b1;
+			if (SIEPortWEn == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+				next_SIEPortData <= SIEPortDataIn;
+				next_SIEPortCtrl <= SIEPortCtrlIn;
+				next_SIEPortTxRdy <= 1'b0;
+			end
+		end
+		`PKT_ST_TKN_CRC_WAIT_RDY:
+		begin
+			next_CRC5En <= 1'b0;
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+				next_TxByteOutCtrl <= `DATA_STOP;
+			end
+		end
+		`PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+			if (CRC5UpdateRdy == 1'b1)	
+				NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+		`PKT_ST_TKN_PID_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			next_rstCRC <= 1'b0;
+			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+		end
+		`PKT_ST_TKN_PID_WAIT_RDY:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STREAM;
+				next_rstCRC <= 1'b1;
+			end
+		`RES_ST_CHK_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (i == `RESUME_LEN)	
+				NextState_SIETx <= `RES_ST_S1;
+			else
+				NextState_SIETx <= `RES_ST_WAIT_RDY;
+		end
+		`RES_ST_S1:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_S3;
+				next_USBWireData <= `SE0;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`RES_ST_S3:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_S4;
+				next_USBWireData <= `SE0;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`RES_ST_S4:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_S5;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`RES_ST_S5:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_S6;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`RES_ST_S6:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_USBWireReq <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`RES_ST_WAIT_GNT:
+			if (USBWireGnt == 1'b1)	
+				NextState_SIETx <= `RES_ST_WAIT_RDY;
+		`RES_ST_WAIT_RDY:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_CHK_FIN;
+				next_USBWireData <= KBit;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+				next_i <= i + 1'b1;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SIETx_CurrentState
+	if (rst)	
+		CurrState_SIETx <= `START_SIETX;
+	else
+		CurrState_SIETx <= NextState_SIETx;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SIETx_RegOutput
+	if (rst)	
+	begin
+		SIEPortData <= 8'h00;
+		SIEPortCtrl <= 8'h00;
+		i <= 5'h0;
+		processTxByteWEn <= 1'b0;
+		TxByteOut <= 8'h00;
+		TxByteOutCtrl <= 8'h00;
+		USBWireData <= 2'b00;
+		USBWireCtrl <= `TRI_STATE;
+		USBWireReq <= 1'b0;
+		USBWireWEn <= 1'b0;
+		rstCRC <= 1'b0;
+		CRCData <= 8'h00;
+		CRC5En <= 1'b0;
+		CRC5_8Bit <= 1'b0;
+		CRC16En <= 1'b0;
+		SIEPortTxRdy <= 1'b0;
+	end
+	else 
+	begin
+		SIEPortData <= next_SIEPortData;
+		SIEPortCtrl <= next_SIEPortCtrl;
+		i <= next_i;
+		processTxByteWEn <= next_processTxByteWEn;
+		TxByteOut <= next_TxByteOut;
+		TxByteOutCtrl <= next_TxByteOutCtrl;
+		USBWireData <= next_USBWireData;
+		USBWireCtrl <= next_USBWireCtrl;
+		USBWireReq <= next_USBWireReq;
+		USBWireWEn <= next_USBWireWEn;
+		rstCRC <= next_rstCRC;
+		CRCData <= next_CRCData;
+		CRC5En <= next_CRC5En;
+		CRC5_8Bit <= next_CRC5_8Bit;
+		CRC16En <= next_CRC16En;
+		SIEPortTxRdy <= next_SIEPortTxRdy;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxBit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxBit.v	(revision 264)
@@ -0,0 +1,372 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processRxBit.v
+// Generated   : 09/12/04 22:54:47
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processRxBit.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [1:0] RxBitsIn;
+input   clk;
+input   processRxBitsWEn;
+input   processRxByteRdy;
+input   rst;
+output  [7:0] RxCtrlOut;
+output  [7:0] RxDataOut;
+output  processRxBitRdy;
+output  processRxByteWEn;
+output  resumeDetected;
+
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [1:0] RxBitsIn;
+reg     [7:0] RxCtrlOut, next_RxCtrlOut;
+reg     [7:0] RxDataOut, next_RxDataOut;
+wire    clk;
+reg     processRxBitRdy, next_processRxBitRdy;
+wire    processRxBitsWEn;
+wire    processRxByteRdy;
+reg     processRxByteWEn, next_processRxByteWEn;
+reg     resumeDetected, next_resumeDetected;
+wire    rst;
+
+// diagram signals declarations
+reg  [3:0]RXBitCount, next_RXBitCount;
+reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg  [7:0]RXByte, next_RXByte;
+reg  [3:0]RXSameBitCount, next_RXSameBitCount;
+reg  [1:0]RxBits, next_RxBits;
+reg bitStuffError, next_bitStuffError;
+reg  [1:0]oldRXBits, next_oldRXBits;
+reg  [3:0]resumeWaitCnt, next_resumeWaitCnt;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0] CurrState_prRxBit;
+reg [3:0] NextState_prRxBit;
+
+
+//--------------------------------------------------------------------
+// Machine: prRxBit
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
+begin : prRxBit_NextState
+	NextState_prRxBit <= CurrState_prRxBit;
+	// Set default values for outputs and signals
+	next_processRxByteWEn <= processRxByteWEn;
+	next_RxCtrlOut <= RxCtrlOut;
+	next_RxDataOut <= RxDataOut;
+	next_resumeDetected <= resumeDetected;
+	next_RXBitStMachCurrState <= RXBitStMachCurrState;
+	next_RxBits <= RxBits;
+	next_RXSameBitCount <= RXSameBitCount;
+	next_RXBitCount <= RXBitCount;
+	next_oldRXBits <= oldRXBits;
+	next_RXByte <= RXByte;
+	next_bitStuffError <= bitStuffError;
+	next_resumeWaitCnt <= resumeWaitCnt;
+	next_processRxBitRdy <= processRxBitRdy;
+	case (CurrState_prRxBit) // synopsys parallel_case full_case
+		`START:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			next_RxCtrlOut <= 8'h00;
+			next_RxDataOut <= 8'h00;
+			next_resumeDetected <= 1'b0;
+			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			next_RxBits <= 2'b00;
+			next_RXSameBitCount <= 4'h0;
+			next_RXBitCount <= 4'h0;
+			next_oldRXBits <= 2'b00;
+			next_RXByte <= 8'h00;
+			next_bitStuffError <= 1'b0;
+			next_resumeWaitCnt <= 4'h0;
+			next_processRxBitRdy <= 1'b1;
+			NextState_prRxBit <= `WAIT_BITS;
+		end
+		`WAIT_BITS:
+			if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))	
+			begin
+				NextState_prRxBit <= `DATA_RX_CHK_SE0;
+				next_RxBits <= RxBitsIn;
+				next_processRxBitRdy <= 1'b0;
+			end
+			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))	
+			begin
+				NextState_prRxBit <= `RES_RX_CHK;
+				next_RxBits <= RxBitsIn;
+				next_processRxBitRdy <= 1'b0;
+			end
+			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))	
+			begin
+				NextState_prRxBit <= `RES_END_CHK1;
+				next_RxBits <= RxBitsIn;
+				next_processRxBitRdy <= 1'b0;
+			end
+			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))	
+			begin
+				NextState_prRxBit <= `IDLE_CHK_KBIT;
+				next_RxBits <= RxBitsIn;
+				next_processRxBitRdy <= 1'b0;
+			end
+		`IDLE_FIRST_BIT:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+			next_RXSameBitCount <= 4'h1;
+			next_RXBitCount <= 4'h1;
+			next_oldRXBits <= RxBits;
+			//zero is always the first RZ data bit of a new packet
+			next_RXByte <= 8'h00;
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`IDLE_CHK_KBIT:
+			if (RxBits == KBit)	
+				NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+			else
+			begin
+				NextState_prRxBit <= `WAIT_BITS;
+				next_processRxBitRdy <= 1'b1;
+			end
+		`IDLE_WAIT_PRB_RDY:
+			if (processRxByteRdy == 1'b1)	
+			begin
+				NextState_prRxBit <= `IDLE_FIRST_BIT;
+				next_RxDataOut <= 8'h00;
+				//redundant data
+				next_RxCtrlOut <= `DATA_START;
+				//start of packet
+				next_processRxByteWEn <= 1'b1;
+			end
+		`DATA_RX_LAST_BIT:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`DATA_RX_CHK_SE0:
+		begin
+			next_bitStuffError <= 1'b0;
+			if (RxBits == `SE0)	
+				NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+			else
+			begin
+				NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+				if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
+				begin
+				  next_RXSameBitCount <= RXSameBitCount + 1'b1;
+				    //inc 'RXSameBitCount'
+				    if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error
+				    next_bitStuffError <= 1'b1;
+				        //flag 'bitStuffError'
+				    else                                          //else no bit stuffing error
+				    begin
+				    next_RXBitCount <= RXBitCount + 1'b1;
+				        if (RXBitCount != 4'h7) begin
+				      next_processRxBitRdy <= 1'b1;
+				            //early indication of ready
+						end
+				    next_RXByte <= { 1'b1, RXByte[7:1]};
+				        //RZ bit = 1 (ie no change in 'RxBits')
+				    end
+				end
+				else                                            //else current 'RxBits' are different from old 'RxBits'
+				begin
+				    if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+				    begin
+				    next_RXBitCount <= RXBitCount + 1'b1;
+				        if (RXBitCount != 4'h7) begin
+				      next_processRxBitRdy <= 1'b1;
+				            //early indication of ready
+						end
+				    next_RXByte <= {1'b0, RXByte[7:1]};
+				        //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
+				    end
+				  next_RXSameBitCount <= 4'h1;
+				    //reset 'RXSameBitCount'
+				end
+				next_oldRXBits <= RxBits;
+			end
+		end
+		`DATA_RX_WAIT_PRB_RDY:
+			if (processRxByteRdy == 1'b1)	
+			begin
+				NextState_prRxBit <= `DATA_RX_LAST_BIT;
+				next_RxDataOut <= 8'h00;
+				//redundant data
+				next_RxCtrlOut <= `DATA_STOP;
+				//end of packet
+				next_processRxByteWEn <= 1'b1;
+			end
+		`DATA_RX_DATA_DESTUFF:
+			if (RXBitCount == 4'h8 & bitStuffError == 1'b0)	
+				NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+			else if (bitStuffError == 1'b1)	
+				NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+			else
+			begin
+				NextState_prRxBit <= `WAIT_BITS;
+				next_processRxBitRdy <= 1'b1;
+			end
+		`DATA_RX_BYTE_SEND2:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`DATA_RX_BYTE_WAIT_RDY:
+			if (processRxByteRdy == 1'b1)	
+			begin
+				NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+				next_RXBitCount <= 4'h0;
+				next_RxDataOut <= RXByte;
+				next_RxCtrlOut <= `DATA_STREAM;
+				next_processRxByteWEn <= 1'b1;
+			end
+		`DATA_RX_ERROR_CHK_RES:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			if (RxBits == JBit)                           //if current bit is a JBit, then
+			  next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			    //next state is idle
+			else                                          //else
+			begin
+			  next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+			    //check for resume
+			  next_resumeWaitCnt <= 0;
+			end
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`DATA_RX_ERROR_WAIT_RDY:
+			if (processRxByteRdy == 1'b1)	
+			begin
+				NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+				next_RxDataOut <= 8'h00;
+				//redundant data
+				next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+				next_processRxByteWEn <= 1'b1;
+			end
+		`RES_RX_CHK:
+		begin
+			if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
+			  next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			else
+			begin
+			  next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+			    //if we've waited long enough, then
+			    if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
+			    begin
+			    next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+			    next_resumeDetected <= 1'b1;
+			        //report resume detected
+			    end
+			end
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`RES_END_CHK1:
+		begin
+			if (RxBits != KBit)  //line must leave KBit state for the end of resume
+			begin
+			  next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			  next_resumeDetected <= 1'b0;
+			    //clear resume detected flag
+			end
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prRxBit_CurrentState
+	if (rst)	
+		CurrState_prRxBit <= `START;
+	else
+		CurrState_prRxBit <= NextState_prRxBit;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prRxBit_RegOutput
+	if (rst)	
+	begin
+		RXBitStMachCurrState <= `IDLE_BIT_ST;
+		RxBits <= 2'b00;
+		RXSameBitCount <= 4'h0;
+		RXBitCount <= 4'h0;
+		oldRXBits <= 2'b00;
+		RXByte <= 8'h00;
+		bitStuffError <= 1'b0;
+		resumeWaitCnt <= 4'h0;
+		processRxByteWEn <= 1'b0;
+		RxCtrlOut <= 8'h00;
+		RxDataOut <= 8'h00;
+		resumeDetected <= 1'b0;
+		processRxBitRdy <= 1'b1;
+	end
+	else 
+	begin
+		RXBitStMachCurrState <= next_RXBitStMachCurrState;
+		RxBits <= next_RxBits;
+		RXSameBitCount <= next_RXSameBitCount;
+		RXBitCount <= next_RXBitCount;
+		oldRXBits <= next_oldRXBits;
+		RXByte <= next_RXByte;
+		bitStuffError <= next_bitStuffError;
+		resumeWaitCnt <= next_resumeWaitCnt;
+		processRxByteWEn <= next_processRxByteWEn;
+		RxCtrlOut <= next_RxCtrlOut;
+		RxDataOut <= next_RxDataOut;
+		resumeDetected <= next_resumeDetected;
+		processRxBitRdy <= next_processRxBitRdy;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processTxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processTxByte.asf	(revision 264)
@@ -0,0 +1,215 @@
+VERSION=1.19
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FREEOID=1000
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/9/2004"
+HEADER_PARAM="TITLE,processTxByte"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 874
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 887
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 994
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 2 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 2 Builtin InPort | 20959,250108 "" ""
+L 821 822 0 TEXT "Labels" | 26959,250108 1 0 0 "TxByteCtrlIn[7:0]"
+I 820 0 2 Builtin InPort | 20959,254515 "" ""
+L 819 820 0 TEXT "Labels" | 26959,254515 1 0 0 "TxByteIn[7:0]"
+I 818 0 2 Builtin OutPort | 18852,259388 "" ""
+L 817 818 0 TEXT "Labels" | 24852,259388 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin InPort | 20959,264028 "" ""
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+I 847 0 2 Builtin InPort | 125241,221252 "" ""
+I 846 0 2 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 2 Builtin Signal | 69660,223196 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+C 870 869 0 TEXT "Conditions" | 44743,165433 1 0 0 "processTxByteWEn == 1'b1"
+A 871 869 16 TEXT "Actions" | 40695,156023 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+L 873 874 0 TEXT "State Labels" | 48483,85161 1 0 0 "SEND_BYTE"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48483,85161 6500 6500
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 883 880 0 Builtin Entry | 38120,248040
+I 884 880 0 Builtin Exit | 178131,23271
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47391,100834 47973,91631
+W 897 6 0 874 887 BEZIER "Transitions" | 48237,78679 48703,71573 48867,58679 49333,51573
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+                                         25630,50244 23766,53274 22950,67894 22135,82515\
+                                         20737,137969 21261,153813 21785,169657 25281,177579\
+                                         27028,179792 28775,182006 32271,182938 33727,182355\
+                                         35183,181773 37321,179186 38486,177555
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+A 902 901 4 TEXT "Actions" | 75251,207304 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1)                      //If this bit is 1, then\n  TXOneCount <= TXOneCount + 1'b1;          //increment 'TXOneCount'\nelse                                        //else this is a zero bit\nbegin\n  TXOneCount <= 4'h1;                            //reset 'TXOneCount'\n  if (TXLineState == JBit) TXLineState <= KBit; //toggle the line state\n  else TXLineState <= JBit;\nend"
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == 4'h6"
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h1;                                //reset 'TXOneCount'\nif (TXLineState == JBit) TXLineState <= KBit;   //toggle the line state\nelse TXLineState <= JBit;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+                                              113354,23912 154429,23527 174909,23271
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+                                              40522,42856 31562,47464 29098,65320 26634,83176\
+                                              25738,149992 26858,168968 27978,187944 33354,197032\
+                                              36938,198888 40522,200744 49226,198568 51498,198152\
+                                              53770,197736 54409,198230 54473,198230
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 1;       \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+W 940 6 0 936 874 BEZIER "Transitions" | 142661,111545 128565,105371 68178,94636 54082,88462
+C 941 940 0 TEXT "Conditions" | 111729,100310 1 0 0 "USBWireGnt == 1'b1"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+W 944 895 0 948 942 BEZIER "Transitions" | 72730,212275 73358,204982 73632,189078 74260,181785
+C 945 944 0 TEXT "Conditions" | 73971,211371 1 0 0 "USBWireRdy == 1'b1"
+A 946 942 4 TEXT "Actions" | 93534,178039 1 0 0 "USBWireWEn <= 1'b0;"
+A 947 944 16 TEXT "Actions" | 69416,202253 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+W 958 895 0 942 956 BEZIER "Transitions" | 75377,168841 76005,161548 76957,146611 77585,139318
+A 959 958 16 TEXT "Actions" | 72304,159240 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 960 956 4 TEXT "Actions" | 96752,135563 1 0 0 "USBWireWEn <= 1'b0;"
+C 961 958 0 TEXT "Conditions" | 76516,167828 1 0 0 "USBWireRdy == 1'b1"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+W 964 895 0 956 962 BEZIER "Transitions" | 78681,126377 79309,119084 79833,97641 80461,90348
+A 965 964 16 TEXT "Actions" | 75410,113723 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+A 966 962 4 TEXT "Actions" | 99640,86596 1 0 0 "USBWireWEn <= 1'b0;"
+C 967 964 0 TEXT "Conditions" | 79852,125749 1 0 0 "USBWireRdy == 1'b1"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+W 970 895 0 962 968 BEZIER "Transitions" | 81334,77407 81962,70114 82544,57872 83172,50579
+A 971 970 16 TEXT "Actions" | 77621,69378 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+C 973 970 0 TEXT "Conditions" | 81643,77033 1 0 0 "USBWireRdy == 1'b1"
+I 974 895 0 Builtin Exit | 97904,23272
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+                                           90132,26172 93257,24084 94765,23272
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+                                              104561,139388 153745,139620 168013,138576 182281,137532\
+                                              190169,133124 192141,121582 194113,110040 194113,68280\
+                                              192025,55114 189937,41948 185529,28723 181353,23271
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+                                              41124,121640 36948,124424 36020,132602 35092,140780\
+                                              35556,170708 38166,179350 40776,187992 50140,192687\
+                                              55128,195007
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+                                              30972,218732 29812,212468 29638,189094 29464,165720\
+                                              29928,78488 31900,55230 33872,31972 41296,26172\
+                                              49358,24664 57420,23156 82353,23388 94765,23272
+I 977 895 0 Builtin Entry | 34452,259216
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+A 979 9 4 TEXT "Actions" | 108416,207754 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;"
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+I 981 0 2 Builtin Signal | 69434,227674 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 983 0 2 Builtin Signal | 69201,232334 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 985 0 2 Builtin Signal | 69201,236994 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 987 0 2 Builtin Signal | 69201,241421 "" ""
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 997 995 0 Builtin Exit | 129540,111760
+I 996 995 0 Builtin Entry | 86360,167640
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+L 815 816 0 TEXT "Labels" | 26959,264028 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/readUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/readUSBWireData.v	(revision 264)
@@ -0,0 +1,198 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// readUSBWireData.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: readUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:01 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
+input   [1:0] RxBitsIn;
+output  RxDataInTick;
+input   SIERxRdyIn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+input   disableWireRead;
+output  [1:0] RxBitsOut;
+output  SIERxWEn;
+
+wire   [1:0] RxBitsIn;
+reg    RxDataInTick;
+wire   SIERxRdyIn;
+wire   clk;
+wire   fullSpeedRate;
+wire   rst;
+reg    [1:0] RxBitsOut;
+reg    SIERxWEn;
+
+// local registers
+reg  [1:0]buffer0;
+reg  [1:0]buffer1;
+reg  [1:0]buffer2;
+reg  [1:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg  [1:0]oldRxBitsIn;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+	end
+  else begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+ 		incBufferCnt <= 1'b0;
+		bufferInIndex <= 2'b00;
+		buffer0 <= 2'b00;
+		buffer1 <= 2'b00;
+		buffer2 <= 2'b00;
+		buffer3 <= 2'b00;
+    RxDataInTick <= 1'b0;
+	end
+  else begin
+	  incBufferCnt <= 1'b0;         //default value
+	  oldRxBitsIn <= RxBitsIn;
+	  if (oldRxBitsIn != RxBitsIn)  //if edge detected then
+		  i <= 5'b00000;              //reset the counter
+	  else
+		  i <= i + 1'b1;
+    if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+	  begin
+      RxDataInTick <= !RxDataInTick;
+      if (disableWireRead != 1'b1)  //do not read wire data when transmitter is active
+      begin
+        incBufferCnt <= 1'b1;
+		    bufferInIndex <= bufferInIndex + 1'b1;
+		    case (bufferInIndex)
+			    2'b00 : buffer0 <= RxBitsIn;
+			    2'b01 : buffer1 <= RxBitsIn;
+			    2'b10 : buffer2 <= RxBitsIn;
+			    2'b11 : buffer3 <= RxBitsIn;
+		    endcase
+      end
+	  end
+  end
+end
+
+				
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+		decBufferCnt <= 1'b0;
+		bufferOutIndex <= 2'b00;
+		RxBitsOut <= 2'b00;
+		SIERxWEn <= 1'b0;
+		bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+	end
+  else begin
+	  case (bufferOutStMachCurrState)
+		  `WAIT_BUFFER_NOT_EMPTY:
+		  begin
+			  if (bufferCnt != 3'b000)
+				  bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+		  end
+		  `WAIT_SIE_RX_READY:
+		  begin
+			  if (SIERxRdyIn == 1'b1)
+			  begin 
+				  SIERxWEn <= 1'b1;
+				  bufferOutStMachCurrState <= `SIE_RX_WRITE;
+				  decBufferCnt <= 1'b1;
+				  bufferOutIndex <= bufferOutIndex + 1'b1;
+				  case (bufferOutIndex)
+  			    2'b00 :	RxBitsOut <= buffer0;
+					  2'b01 : RxBitsOut <= buffer1;
+					  2'b10 : RxBitsOut <= buffer2;
+					  2'b11 : RxBitsOut <= buffer3;
+				  endcase
+			  end
+		  end
+		  `SIE_RX_WRITE:
+		  begin
+			  SIERxWEn <= 1'b0;
+			  decBufferCnt <= 1'b0;
+			  bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+		  end
+	  endcase
+  end
+end
+
+			
+
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/updateCRC16.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/updateCRC16.v	(revision 264)
@@ -0,0 +1,110 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC16.v                                                ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: updateCRC16.v,v 1.1.1.1 2004-10-11 04:01:04 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [15:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [15:0] CRCResult;
+reg    ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 16'hffff;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0)
+    begin
+      if (CRCEn == 1'b1) begin
+	      doUpdateCRC = 1'b1;
+	      data <= dataIn;
+        ready <= 1'b0;
+	  end
+    end
+    else begin
+	    i <= i + 1'b1;
+	    if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+	      CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+	    end
+	    else begin
+	      CRCResult <= {1'b0, CRCResult[15:1]};
+	    end
+	    data <= {1'b0, data[7:1]};
+	    if (i == 4'h7)
+	    begin
+	      doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+	    end
+    end
+  end
+end
+		
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(revision 264)
@@ -0,0 +1,108 @@
+VERSION=1.19
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBWireTxArbiter"
+FREEOID=128
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,USBWireTxArbiter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
+F 6 0 671089152 59 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: USBWireTxArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
+W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
+W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
+W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 144675,143037 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0; \nUSBWireWEn <= 1'b0;\nTxBits <= 2'b00;\nTxCtl <= `TRI_STATE;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+C 62 21 0 TEXT "Conditions" | 105671,125880 1 0 0 "rst"
+W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
+                                      200193,83454 202194,93721 199799,97969 197405,102218\
+                                      189371,107780 182843,108050 176316,108321 158239,103840\
+                                      151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n  USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)  \nbegin\n  if (muxSIENotPTXB  == 1'b1)  \n  begin\n    USBWireWEn <= SIETxWEn;\n    TxBits <= SIETxData;\n    TxCtl <= SIETxCtrl;\n  end\n  else\n  begin\n    USBWireWEn <= prcTxByteWEn;\n    TxBits <= prcTxByteData;\n    TxCtl <= prcTxByteCtrl;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+                                      70311,70629 71874,86691 76817,93064 81761,99437\
+                                      89642,107471 97173,106158 104705,104845 116882,95874\
+                                      123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 153906,181456 "" ""
+L 110 111 0 TEXT "Labels" | 159906,181456 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 156447,157894 "" ""
+L 108 109 0 TEXT "Labels" | 162447,157894 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 156216,186076 "" ""
+L 106 107 0 TEXT "Labels" | 162216,186076 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 154368,153274 "" ""
+L 104 105 0 TEXT "Labels" | 160368,153274 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 2 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 155985,199705 "" ""
+L 122 123 0 TEXT "Labels" | 161985,199705 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 155985,195316 "" ""
+L 120 121 0 TEXT "Labels" | 161985,195316 1 0 0 "prcTxByteCtrl"
+I 119 0 2 Builtin InPort | 155985,190696 "" ""
+L 118 119 0 TEXT "Labels" | 161985,190696 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 156447,171985 "" ""
+L 116 117 0 TEXT "Labels" | 162447,171985 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 156447,167596 "" ""
+L 114 115 0 TEXT "Labels" | 162447,167596 1 0 0 "SIETxCtrl"
+I 113 0 2 Builtin InPort | 156447,162745 "" ""
+L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/siereceiver.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/siereceiver.asf	(revision 264)
@@ -0,0 +1,265 @@
+VERSION=1.19
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FREEOID=262
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/6/2004"
+HEADER_PARAM="TITLE,SIEReceiver"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 23
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 46
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 55
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 64
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 73
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 82
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 91
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 235
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 241
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+W 15 6 0 11 241 BEZIER "Transitions" | 54697,186192 54895,182331 55070,163352 55268,159491
+W 14 6 0 9 11 BEZIER "Transitions" | 53793,212320 54090,208657 54044,202830 54341,199167
+S 11 6 16384 ELLIPSE "States" | 54795,192690 6500 6500
+L 10 11 0 TEXT "State Labels" | 54795,192690 1 0 0 "WAIT_BIT\n/4/"
+S 9 6 20480 ELLIPSE "States" | 54004,218793 6500 6500
+L 8 9 0 TEXT "State Labels" | 54004,218793 1 0 0 "START_SRX\n/5/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: SIEReceiver"
+F 6 0 671089152 228 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14253,12655 205887,234211
+L 7 6 0 TEXT "Labels" | 17253,231211 1 0 0 "rcvr"
+S 23 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 143681,32406 6500 6500
+L 22 23 0 TEXT "State Labels" | 143681,32406 1 0 0 "DISCNCT"
+A 21 15 16 TEXT "Actions" | 50061,176470 1 0 0 "RxBits <= RxWireDataIn;\nSIERxRdyOut <= 1'b0;"
+C 19 15 0 TEXT "Conditions" | 55867,186045 1 0 0 "RxWireDataWEn == 1'b1"
+W 17 6 0 16 9 BEZIER "Transitions" | 25106,221421 30781,219421 43306,224917 48981,222917
+I 16 6 0 Builtin Reset | 25106,221421
+H 39 23 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 40 39 12288 ELLIPSE "States" | 64508,213851 6500 6500
+L 41 40 0 TEXT "State Labels" | 64508,213851 1 0 0 "CHK_RXBITS\n/3/"
+I 42 39 0 Builtin Entry | 42918,241791
+I 43 39 0 Builtin Exit | 147281,109121
+W 44 39 0 42 40 BEZIER "Transitions" | 47426,241791 52025,234967 56275,226064 60875,219240
+S 46 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 142838,49983 6500 6500
+L 47 46 0 TEXT "State Labels" | 142838,49983 1 0 0 "WAIT_FS_CONN"
+H 54 46 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 48 54 4096 53 50 BEZIER "Transitions" | 111761,134435 116730,128048 137142,101490 142112,94624
+W 49 54 0 51 53 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 50 54 0 Builtin Exit | 145248,94624
+I 51 54 0 Builtin Entry | 86360,167640
+L 52 53 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/0/"
+S 53 54 0 ELLIPSE "States" | 107950,139700 6500 6500
+H 63 55 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 55 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141452,68793 6500 6500
+L 56 55 0 TEXT "State Labels" | 141452,68793 1 0 0 "WAIT_LS_CONN"
+W 57 63 0 62 59 BEZIER "Transitions" | 111761,134435 116730,127570 121442,118626 126412,111760
+W 58 63 0 60 62 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 59 63 0 Builtin Exit | 129540,111760
+I 60 63 0 Builtin Entry | 86360,167640
+L 61 62 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/1/"
+S 62 63 4096 ELLIPSE "States" | 107950,139700 6500 6500
+H 72 64 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 64 6 36868 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 140066,86613 6500 6500
+L 65 64 0 TEXT "State Labels" | 140066,86613 1 0 0 "LS_CONN"
+W 67 72 0 69 71 BEZIER "Transitions" | 69044,194920 73643,188096 77893,179193 82493,172369
+I 68 72 0 Builtin Exit | 131860,37310
+I 69 72 0 Builtin Entry | 64536,194920
+L 70 71 0 TEXT "State Labels" | 86126,166980 1 0 0 "CHK_RX_BITS\n/2/"
+S 71 72 8192 ELLIPSE "States" | 86126,166980 6500 6500
+S 73 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 139274,106215 6500 6500
+L 74 73 0 TEXT "State Labels" | 139274,106215 1 0 0 "FS_CONN"
+H 81 73 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 90 82 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 82 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 137888,126411 6500 6500
+L 83 82 0 TEXT "State Labels" | 137888,126411 1 0 0 "WAIT_LS_DIS"
+S 91 6 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 136700,148244 6500 6500
+L 92 91 0 TEXT "State Labels" | 136700,148244 1 0 0 "WAIT_FS_DIS"
+H 99 91 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 129 39 8194 40 43 BEZIER "Transitions" | 67288,207977 90867,158271 120574,158827 144153,109121
+W 130 39 8193 40 43 BEZIER "Transitions" | 69252,218293 110985,257468 165540,129446 150409,109121
+C 131 129 0 TEXT "Conditions" | 55856,199298 1 0 0 "RxBits == `ONE_ZERO"
+C 132 130 0 TEXT "Conditions" | 98621,230429 1 0 0 "RxBits == `ZERO_ONE"
+A 133 130 16 TEXT "Actions" | 102033,204788 1 0 0 "RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+A 134 129 16 TEXT "Actions" | 41551,160050 1 0 0 "RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+W 138 6 0 241 91 BEZIER "Transitions" | 55726,152526 55825,150740 55689,148412 56830,147271\
+                                        57971,146130 62339,145137 65812,144988 69286,144839\
+                                        125497,147159 130261,147357
+W 139 6 0 241 82 BEZIER "Transitions" | 54775,152569 53765,144812 51800,131524 53198,127807\
+                                        54597,124090 58369,121813 62636,121465 66904,121118\
+                                        125138,124972 131490,125269
+W 140 6 0 241 73 BEZIER "Transitions" | 54816,152562 53725,141843 49733,121615 49138,115313\
+                                        48543,109011 48344,105238 49038,103700 49733,102162\
+                                        52773,100254 56507,99743 60241,99232 74292,101683\
+                                        79033,101771 83774,101859 131499,104027 132998,104525
+W 141 6 0 241 64 BEZIER "Transitions" | 54966,152543 53478,134579 47748,100673 48939,91443\
+                                        50130,82213 57873,81220 62984,81170 68095,81121\
+                                        127305,85134 133657,85531
+W 142 6 0 241 55 BEZIER "Transitions" | 55084,152531 53397,129108 47947,83900 50081,72287\
+                                        52215,60675 60863,63077 65955,63276 71048,63475\
+                                        83004,63522 85042,64000 87080,64479 134402,67217\
+                                        135100,67416
+W 143 6 0 241 46 BEZIER "Transitions" | 54918,152546 51842,126940 43778,76555 43182,62859\
+                                        42587,49163 46360,45589 52513,44944 58666,44299\
+                                        125961,48736 136382,49232
+W 159 6 0 23 235 BEZIER "Transitions" | 148132,37141 151647,41428 158891,48733 161548,55421\
+                                        164206,62109 167707,83613 169507,92702
+W 158 6 0 46 235 BEZIER "Transitions" | 146210,55537 151355,64540 163238,84117 168383,93120
+W 157 6 0 55 235 BEZIER "Transitions" | 145872,73557 150759,78444 162584,89003 167471,93890
+W 155 6 0 64 235 BEZIER "Transitions" | 146100,89028 150732,91430 162771,94113 166713,95483
+W 154 6 0 73 235 BEZIER "Transitions" | 145399,104041 150201,102669 162025,98607 166827,97235
+W 153 6 0 82 235 BEZIER "Transitions" | 142566,121900 148139,116412 162016,104012 167589,98524
+W 152 6 0 91 235 BEZIER "Transitions" | 140515,142982 147718,132349 161212,109811 168415,99178
+C 151 138 0 TEXT "Conditions" | 53061,140339 1 0 0 "RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST"
+C 150 139 0 TEXT "Conditions" | 52495,119006 1 0 0 "RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST"
+C 149 140 0 TEXT "Conditions" | 50344,99146 1 0 0 "RXStMachCurrState == `CONNECT_FULL_SPEED_ST"
+C 148 141 0 TEXT "Conditions" | 51096,80093 1 0 0 "RXStMachCurrState == `CONNECT_LOW_SPEED_ST"
+C 147 142 0 TEXT "Conditions" | 46355,62337 1 0 0 "RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST"
+C 146 143 0 TEXT "Conditions" | 46100,43512 1 0 0 "RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST"
+W 144 6 0 241 23 BEZIER "Transitions" | 54917,152544 50947,121578 41893,61271 41744,45441\
+                                        41595,29611 48940,28220 55540,28071 62140,27923\
+                                        127685,31371 137213,31768
+C 145 144 0 TEXT "Conditions" | 62881,26704 1 0 0 "RXStMachCurrState == `DISCONNECT_ST"
+W 161 39 8195 40 43 BEZIER "Transitions" | 58578,211192 49548,206204 31147,197012 26632,187509\
+                                           22117,178006 22117,149970 33211,139263 44305,128556\
+                                           88681,113764 103817,110238 118953,106712 136069,108777\
+                                           144153,109121
+W 160 6 0 235 11 BEZIER "Transitions" | 171556,99342 175414,111175 187017,133454 187960,147988\
+                                        188903,162522 181196,168609 172535,178212 163875,187816\
+                                        140506,197413 125270,198727 110035,200042 80303,196085\
+                                        61192,193841
+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `LOW_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+A 166 53 4 TEXT "Actions" | 101814,215348 1 0 0 "if (RxBits == `ONE_ZERO)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `FULL_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+L 167 168 0 TEXT "State Labels" | 102779,73959 1 0 0 "PROC_RX_BITS\n/6/"
+S 168 72 53248 ELLIPSE "States" | 102779,73959 6500 6500
+W 169 72 0 71 168 BEZIER "Transitions" | 86126,160480 86807,152989 100534,87755 101215,80264
+W 170 72 0 168 68 BEZIER "Transitions" | 106629,68724 112767,60967 122594,45067 128732,37310
+A 173 168 4 TEXT "Actions" | 121345,75637 1 0 0 "processRxBitsWEn <= 1'b0;"
+S 174 81 57344 ELLIPSE "States" | 85374,175380 6500 6500
+L 175 174 0 TEXT "State Labels" | 85374,175380 1 0 0 "CHK_RX_BITS1\n/7/"
+I 176 81 0 Builtin Entry | 63784,203320
+I 177 81 0 Builtin Exit | 137732,35774
+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+S 179 81 81920 ELLIPSE "States" | 108651,72423 6500 6500
+A 180 179 4 TEXT "Actions" | 127217,74101 1 0 0 "processRxBitsWEn <= 1'b0;"
+W 182 81 0 179 177 BEZIER "Transitions" | 112501,67188 118639,59431 128706,43531 134844,35774
+W 183 81 0 174 179 BEZIER "Transitions" | 85374,168880 86055,161389 106112,86141 106793,78650
+L 184 179 0 TEXT "State Labels" | 108651,72423 1 0 0 "PROC_RX_BITS1\n/12/"
+S 185 90 61440 ELLIPSE "States" | 81562,170615 6500 6500
+L 186 185 0 TEXT "State Labels" | 81562,170615 1 0 0 "CHK_RX_BITS\n/8/"
+I 187 90 0 Builtin Entry | 59972,198555
+I 188 90 0 Builtin Exit | 126468,30181
+W 189 90 0 187 185 BEZIER "Transitions" | 63495,198555 68094,191731 73329,182828 77929,176004
+S 190 90 65536 ELLIPSE "States" | 97387,66830 6500 6500
+A 191 190 4 TEXT "Actions" | 115953,68508 1 0 0 "processRxBitsWEn <= 1'b0;"
+W 193 90 0 190 188 BEZIER "Transitions" | 101237,61595 107375,53838 117590,37938 123728,30181
+W 194 90 0 185 190 BEZIER "Transitions" | 81562,164115 82243,156624 95324,80670 96005,73179
+L 195 190 0 TEXT "State Labels" | 97387,66830 1 0 0 "PROC_RX_BITS\n/9/"
+S 196 99 69632 ELLIPSE "States" | 91399,59215 6500 6500
+A 197 196 4 TEXT "Actions" | 109965,60893 1 0 0 "processRxBitsWEn <= 1'b0;"
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+I 199 99 0 Builtin Exit | 120480,22566
+I 200 99 0 Builtin Entry | 53777,190526
+S 201 99 73728 ELLIPSE "States" | 75367,162586 6500 6500
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/11/"
+L 203 196 0 TEXT "State Labels" | 91399,59215 1 0 0 "PROC_RX_BITS2\n/10/"
+W 204 99 0 201 196 BEZIER "Transitions" | 75367,156086 76048,148595 89316,73050 89997,65559
+W 205 99 0 196 199 BEZIER "Transitions" | 95249,53980 101387,46223 111486,30323 117624,22566
+I 221 0 2 Builtin OutPort | 129743,241655 "" ""
+L 220 221 0 TEXT "Labels" | 135743,241655 1 0 0 "processRxBitsWEn"
+I 219 0 2 Builtin Signal | 20132,253454 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 215 0 2 Builtin Signal | 20439,258880 "" ""
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+I 209 0 2 Builtin InPort | 77032,244882 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+I 233 0 2 Builtin Signal | 19714,243194 "" ""
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;\nRxBitsOut <= 2'b00;\nprocessRxBitsWEn <= 1'b0;\nSIERxRdyOut <= 1'b1;"
+I 225 0 2 Builtin OutPort | 129743,246614 "" ""
+L 224 225 0 TEXT "Labels" | 135743,246614 1 0 0 "RxBitsOut[1:0]"
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+S 235 6 77844 ELLIPSE "Junction" | 170150,96140 3500 3500
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 237 236 0 Builtin Entry | 86360,167640
+I 238 236 0 Builtin Exit | 129540,111760
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+A 255 194 16 TEXT "Actions" | 61406,142366 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend\nprocessRxBitsWEn <= 1'b1;"
+C 254 194 0 TEXT "Conditions" | 81005,160052 1 0 0 "processRxBitRdyIn == 1'b1"
+C 253 204 0 TEXT "Conditions" | 76690,153596 1 0 0 "processRxBitRdyIn == 1'b1"
+A 252 204 16 TEXT "Actions" | 57026,138798 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend\nprocessRxBitsWEn <= 1'b1;"
+A 250 160 16 TEXT "Actions" | 151210,187452 1 0 0 "SIERxRdyOut <= 1'b1;"
+I 249 0 2 Builtin OutPort | 74763,249425 "" ""
+L 248 249 0 TEXT "Labels" | 80763,249425 1 0 0 "SIERxRdyOut"
+I 247 0 2 Builtin InPort | 132223,251370 "" ""
+L 246 247 0 TEXT "Labels" | 138223,251370 1 0 0 "processRxBitRdyIn"
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+S 241 6 81940 ELLIPSE "Junction" | 55410,156008 3500 3500
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 243 242 0 Builtin Entry | 86360,167640
+I 244 242 0 Builtin Exit | 129540,111760
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+A 259 169 16 TEXT "Actions" | 64097,138640 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend\nprocessRxBitsWEn <= 1'b1;\nRxBitsOut <= RxBits;"
+A 258 183 16 TEXT "Actions" | 78587,143608 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend\nprocessRxBitsWEn <= 1'b1;\nRxBitsOut <= RxBits;\nSIERxRdyOut <= 1'b1; //early indication of ready"
+C 257 169 0 TEXT "Conditions" | 57276,154345 1 0 0 "processRxBitRdyIn == 1'b1"
+C 256 183 0 TEXT "Conditions" | 63784,161795 1 0 0 "processRxBitRdyIn == 1'b1"
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+I 261 0 2 Builtin OutPort | 74654,253805 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/updateCRC5.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/updateCRC5.v	(revision 264)
@@ -0,0 +1,117 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC5.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: updateCRC5.v,v 1.1.1.1 2004-10-11 04:01:04 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   CRC5_8BitIn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [4:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   CRC5_8BitIn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+	  i <= 4'h0;
+	  CRCResult <= 5'h1f;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0) begin
+      if (CRCEn == 1'b1) begin
+        ready <= 1'b0;
+	      doUpdateCRC <= 1'b1;
+	      data <= dataIn;
+	      if (CRC5_8BitIn == 1'b1) begin
+	        loopEnd <= 4'h7; 
+        end
+	      else begin
+		      loopEnd <= 4'h2;
+        end
+	    end
+    end
+    else begin
+	    i <= i + 1'b1;
+	    if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+		    CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+	    end
+      else begin
+        CRCResult <= {1'b0, CRCResult[4:1]};
+      end
+	    data <= {1'b0, data[7:1]};
+	    if (i == loopEnd) begin
+	      doUpdateCRC <= 1'b0; 
+		    i <= 4'h0;
+        ready <= 1'b1;
+	    end
+    end
+  end
+end
+		
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(revision 264)
@@ -0,0 +1,172 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\usbTxWireArbiter.v
+// Generated   : 06/05/04 05:53:14
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\usbTxWireArbiter.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module USBWireTxArbiter (SIETxCtrl, SIETxData, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, USBWireRdyIn, USBWireRdyOut, USBWireWEn, clk, prcTxByteCtrl, prcTxByteData, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst);
+input   SIETxCtrl;
+input   [1:0] SIETxData;
+input   SIETxReq;
+input   SIETxWEn;
+input   USBWireRdyIn;
+input   clk;
+input   prcTxByteCtrl;
+input   [1:0] prcTxByteData;
+input   prcTxByteReq;
+input   prcTxByteWEn;
+input   rst;
+output  SIETxGnt;
+output  [1:0] TxBits;
+output  TxCtl;
+output  USBWireRdyOut;
+output  USBWireWEn;
+output  prcTxByteGnt;
+
+wire    SIETxCtrl;
+wire    [1:0] SIETxData;
+reg     SIETxGnt, next_SIETxGnt;
+wire    SIETxReq;
+wire    SIETxWEn;
+reg     [1:0] TxBits, next_TxBits;
+reg     TxCtl, next_TxCtl;
+wire    USBWireRdyIn;
+reg     USBWireRdyOut, next_USBWireRdyOut;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+wire    prcTxByteCtrl;
+wire    [1:0] prcTxByteData;
+reg     prcTxByteGnt, next_prcTxByteGnt;
+wire    prcTxByteReq;
+wire    prcTxByteWEn;
+wire    rst;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0] CurrState_txWireArb;
+reg [1:0] NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+    USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)
+begin
+    if (muxSIENotPTXB  == 1'b1)
+    begin
+        USBWireWEn <= SIETxWEn;
+        TxBits <= SIETxData;
+        TxCtl <= SIETxCtrl;
+    end
+    else
+    begin
+        USBWireWEn <= prcTxByteWEn;
+        TxBits <= prcTxByteData;
+        TxCtl <= prcTxByteCtrl;
+    end
+end
+
+
+//--------------------------------------------------------------------
+// Machine: txWireArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb)
+begin : txWireArb_NextState
+	NextState_txWireArb <= CurrState_txWireArb;
+	// Set default values for outputs and signals
+	next_prcTxByteGnt <= prcTxByteGnt;
+	next_muxSIENotPTXB <= muxSIENotPTXB;
+	next_SIETxGnt <= SIETxGnt;
+	case (CurrState_txWireArb) // synopsys parallel_case full_case
+		`START_TARB:
+			NextState_txWireArb <= `TARB_WAIT_REQ;
+		`TARB_WAIT_REQ:
+			if (prcTxByteReq == 1'b1)	
+			begin
+				NextState_txWireArb <= `PTXB_ACT;
+				next_prcTxByteGnt <= 1'b1;
+				next_muxSIENotPTXB <= 1'b0;
+			end
+			else if (SIETxReq == 1'b1)	
+			begin
+				NextState_txWireArb <= `SIE_TX_ACT;
+				next_SIETxGnt <= 1'b1;
+				next_muxSIENotPTXB <= 1'b1;
+			end
+		`PTXB_ACT:
+			if (prcTxByteReq == 1'b0)	
+			begin
+				NextState_txWireArb <= `TARB_WAIT_REQ;
+				next_prcTxByteGnt <= 1'b0;
+			end
+		`SIE_TX_ACT:
+			if (SIETxReq == 1'b0)	
+			begin
+				NextState_txWireArb <= `TARB_WAIT_REQ;
+				next_SIETxGnt <= 1'b0;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : txWireArb_CurrentState
+	if (rst)	
+		CurrState_txWireArb <= `START_TARB;
+	else
+		CurrState_txWireArb <= NextState_txWireArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : txWireArb_RegOutput
+	if (rst)	
+	begin
+		muxSIENotPTXB <= 1'b0;
+		prcTxByteGnt <= 1'b0;
+		SIETxGnt <= 1'b0;
+	end
+	else 
+	begin
+		muxSIENotPTXB <= next_muxSIENotPTXB;
+		prcTxByteGnt <= next_prcTxByteGnt;
+		SIETxGnt <= next_SIETxGnt;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/endpMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/endpMux.v	(revision 264)
@@ -0,0 +1,265 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// endpMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: endpMux.v,v 1.1.1.1 2004-10-11 04:01:05 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbSlaveControl_h.v" 
+
+module endpMux (
+  clk, 
+  rst,
+  currEndP,
+  NAKSent,
+  stallSent,
+  CRCError,
+  bitStuffError,
+  RxOverflow,
+  RxTimeOut,
+  dataSequence,
+  ACKRxed,
+  transType,
+  transTypeNAK,
+  endPControlReg,
+  clrEPRdy,
+  endPMuxErrorsWEn,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  endP0StatusReg,
+  endP1StatusReg,
+  endP2StatusReg,
+  endP3StatusReg,
+  endP0TransTypeReg,
+  endP1TransTypeReg,
+  endP2TransTypeReg,
+  endP3TransTypeReg,
+  endP0NAKTransTypeReg,
+  endP1NAKTransTypeReg,
+  endP2NAKTransTypeReg,
+  endP3NAKTransTypeReg,
+  clrEP0Rdy,
+  clrEP1Rdy,
+  clrEP2Rdy,
+  clrEP3Rdy);
+
+
+input clk; 
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [3:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [3:0] endP0ControlReg;
+input [3:0] endP1ControlReg;
+input [3:0] endP2ControlReg;
+input [3:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk; 
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [3:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      endPControlReg <= endP0ControlReg;
+      clrEP0Rdy <= clrEPRdy;
+    end
+    2'b01: begin
+      endPControlReg <= endP1ControlReg;
+      clrEP1Rdy <= clrEPRdy;
+    end
+    2'b10: begin
+      endPControlReg <= endP2ControlReg;
+      clrEP2Rdy <= clrEPRdy;
+    end
+    2'b11: begin
+      endPControlReg <= endP3ControlReg;
+      clrEP3Rdy <= clrEPRdy;
+    end
+  endcase  
+end      
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+  if (rst) begin
+    endP0NAKTransTypeReg <= 2'b00;
+    endP1NAKTransTypeReg <= 2'b00;
+    endP2NAKTransTypeReg <= 2'b00;
+    endP3NAKTransTypeReg <= 2'b00;
+    endP0TransTypeReg <= 2'b00;
+    endP1TransTypeReg <= 2'b00;
+    endP2TransTypeReg <= 2'b00;
+    endP3TransTypeReg <= 2'b00;
+    endP0StatusReg <= 4'h0;
+    endP1StatusReg <= 4'h0;
+    endP2StatusReg <= 4'h0;
+    endP3StatusReg <= 4'h0;
+  end
+  else begin
+    if (endPMuxErrorsWEn == 1'b1) begin
+      if (NAKSent == 1'b1) begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0NAKTransTypeReg <= transTypeNAK;
+            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; 
+          end
+          2'b01: begin
+            endP1NAKTransTypeReg <= transTypeNAK;
+            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; 
+          end
+          2'b10: begin
+            endP2NAKTransTypeReg <= transTypeNAK;
+            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; 
+          end
+          2'b11: begin
+            endP3NAKTransTypeReg <= transTypeNAK;
+            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; 
+          end
+        endcase
+      end
+      else begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0TransTypeReg <= transType;
+            endP0StatusReg <= endPStatusCombine; 
+          end
+          2'b01: begin
+            endP1TransTypeReg <= transType;
+            endP1StatusReg <= endPStatusCombine; 
+          end
+          2'b10: begin
+            endP2TransTypeReg <= transType;
+            endP2StatusReg <= endPStatusCombine; 
+          end
+          2'b11: begin
+            endP3TransTypeReg <= transType;
+            endP3StatusReg <= endPStatusCombine; 
+          end
+        endcase
+      end
+    end
+  end
+end
+        
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/sctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/sctxportarbiter.v	(revision 264)
@@ -0,0 +1,173 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sctxportarbiter.v
+// Generated   : 06/10/04 22:29:55
+// From        : c:\projects\USBHostSlave\RTL\slaveController\sctxportarbiter.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   SCTxPortRdyIn;
+input   clk;
+input   [7:0] directCntlCntl;
+input   [7:0] directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0] sendPacketCntl;
+input   [7:0] sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortRdyOut;
+output  SCTxPortWEnable;
+output  directCntlGnt;
+output  sendPacketGnt;
+
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortRdyIn;
+reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg     SCTxPortWEnable, next_SCTxPortWEnable;
+wire    clk;
+wire    [7:0] directCntlCntl;
+wire    [7:0] directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+wire    [7:0] sendPacketCntl;
+wire    [7:0] sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0] CurrState_SCTxArb;
+reg [1:0] NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+    SCTxPortRdyOut = SCTxPortRdyIn;
+end
+always @(muxDCEn or
+		 		 directCntlWEn or directCntlData or directCntlCntl or
+                  directCntlWEn or directCntlData or directCntlCntl or
+ 		  		 sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+    begin
+        SCTxPortWEnable <= directCntlWEn;
+        SCTxPortData <= directCntlData;
+        SCTxPortCntl <= directCntlCntl;
+    end
+else
+    begin
+        SCTxPortWEnable <= sendPacketWEn;
+        SCTxPortData <= sendPacketData;
+        SCTxPortCntl <= sendPacketCntl;
+    end
+end
+
+
+//--------------------------------------------------------------------
+// Machine: SCTxArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin : SCTxArb_NextState
+	NextState_SCTxArb <= CurrState_SCTxArb;
+	// Set default values for outputs and signals
+	next_sendPacketGnt <= sendPacketGnt;
+	next_muxDCEn <= muxDCEn;
+	next_directCntlGnt <= directCntlGnt;
+	case (CurrState_SCTxArb) // synopsys parallel_case full_case
+		`SARB1_WAIT_REQ:
+			if (sendPacketReq == 1'b1)	
+			begin
+				NextState_SCTxArb <= `SARB_SEND_PACKET;
+				next_sendPacketGnt <= 1'b1;
+				next_muxDCEn <= 1'b0;
+			end
+			else if (directCntlReq == 1'b1)	
+			begin
+				NextState_SCTxArb <= `SARB_DC;
+				next_directCntlGnt <= 1'b1;
+				next_muxDCEn <= 1'b1;
+			end
+		`SARB_SEND_PACKET:
+			if (sendPacketReq == 1'b0)	
+			begin
+				NextState_SCTxArb <= `SARB1_WAIT_REQ;
+				next_sendPacketGnt <= 1'b0;
+			end
+		`SARB_DC:
+			if (directCntlReq == 1'b0)	
+			begin
+				NextState_SCTxArb <= `SARB1_WAIT_REQ;
+				next_directCntlGnt <= 1'b0;
+			end
+		`START_SARB:
+			NextState_SCTxArb <= `SARB1_WAIT_REQ;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_CurrentState
+	if (rst)	
+		CurrState_SCTxArb <= `START_SARB;
+	else
+		CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_RegOutput
+	if (rst)	
+	begin
+		muxDCEn <= 1'b0;
+		sendPacketGnt <= 1'b0;
+		directCntlGnt <= 1'b0;
+	end
+	else 
+	begin
+		muxDCEn <= next_muxDCEn;
+		sendPacketGnt <= next_sendPacketGnt;
+		directCntlGnt <= next_directCntlGnt;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveGetpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveGetpacket.asf	(revision 264)
@@ -0,0 +1,268 @@
+VERSION=1.19
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FREEOID=280
+"LIBRARIES=`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/22/2004"
+HEADER_PARAM="TITLE,slaveGetPacket"
+END
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+END
+INSTHEADER 1
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+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+I 76 72 0 Builtin Exit | 187140,27160
+I 75 72 0 Builtin Entry | 33260,254940
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177624,25344 184036,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176807,72082 177204,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 2 Builtin InPort | 114408,221254 "" ""
+I 191 0 2 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 2 Builtin Signal | 19204,221408 "" ""
+I 216 0 2 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 2 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+I 238 0 2 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 2 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 2 Builtin OutPort | 77780,242452 "" ""
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveSendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveSendpacket.asf	(revision 264)
@@ -0,0 +1,170 @@
+VERSION=1.19
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FREEOID=215
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,slaveSendPacket"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 21
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 45
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "SP_WAIT_ENABLE\n/1/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP1\n/0/"
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
+F 6 0 671089152 188 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: slaveSendPacket"
+I 12 6 0 Builtin Reset | 74872,202290
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP1_WAIT_GNT\n/2/"
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nSCTxPortReq <= 1'b1;"
+L 20 21 0 TEXT "State Labels" | 113767,93734 1 0 0 "SP_SEND_PID"
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113767,93734 6500 6500
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 112951,104607 113260,100204
+C 23 22 0 TEXT "Conditions" | 114630,116691 1 0 0 "SCTxPortGnt == 1'b1"
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 29624,2084 214124,250084
+S 26 25 16384 ELLIPSE "States" | 72734,192072 6500 6500
+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
+I 28 25 0 Builtin Entry | 49237,230379
+I 29 25 0 Builtin Exit | 146004,95604
+W 30 25 0 28 26 BEZIER "Transitions" | 53779,230379 60054,220138 63123,209223 69341,197615
+L 32 33 0 TEXT "State Labels" | 75021,153035 1 0 0 "FIN\n/4/"
+S 33 25 20480 ELLIPSE "States" | 75021,153035 6500 6500
+W 34 25 0 26 33 BEZIER "Transitions" | 72953,185597 73302,178879 73960,166205 74309,159487
+C 36 34 0 TEXT "Conditions" | 75236,185214 1 0 0 "SCTxPortRdy == 1'b1"
+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
+A 38 33 4 TEXT "Actions" | 93627,154331 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 39 25 0 33 29 BEZIER "Transitions" | 79375,148210 95944,135371 126275,108443 142844,95604
+L 44 45 0 TEXT "State Labels" | 182202,45960 1 0 0 "SP_D0_D1"
+S 45 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,45960 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
+S 47 6 28672 ELLIPSE "States" | 115848,16910 6500 6500
+W 48 6 8194 21 205 BEZIER "Transitions" | 108645,89734 97773,80901 77133,63853 66261,55020
+W 50 6 8193 21 45 BEZIER "Transitions" | 119169,90120 134042,80003 162156,60011 177029,49894
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+W 73 6 0 45 47 BEZIER "Transitions" | 176581,42697 162161,37714 135904,25306 121888,19311
+W 74 6 0 205 47 BEZIER "Transitions" | 67096,47093 78647,41129 99521,27639 110324,20335
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 127 65 0 Builtin Exit | 176933,37229
+I 126 65 0 Builtin Entry | 68162,237252
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1;	 \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
+S 136 65 32768 ELLIPSE "States" | 97326,133352 6500 6500
+W 128 65 0 126 145 BEZIER "Transitions" | 72704,237252 77515,245311 99394,235265 108723,227500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 173 0 2 Builtin InPort | 35299,213676 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 2 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170187,37688 173773,37229
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+I 185 0 2 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 183 0 2 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "SCTxPortWEn"
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 0 Builtin Signal | 35000,231468 "" ""
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
+W 210 65 0 207 145 BEZIER "Transitions" | 169895,125680 176804,126013 188953,127552 193864,130465\
+                                          198775,133379 204604,144369 205686,152818 206768,161268\
+                                          205269,184079 201481,192903 197694,201727 184040,214216\
+                                          173218,217462 162396,220708 133810,221642 118992,221891
+W 209 65 0 136 207 BEZIER "Transitions" | 103712,132145 117531,130730 143304,126529 157123,125114
+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 76973,151815 1 0 0 "CLR_REN\n/13/"
+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slavecontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slavecontroller.v	(revision 264)
@@ -0,0 +1,406 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slavecontroller.v
+// Generated   : 09/22/04 06:01:23
+// From        : c:\projects\USBHostSlave\RTL\slaveController\slavecontroller.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (CRCError, NAKSent, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, SOFRxed, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBEndP, USBTgtAddress, bitStuffError, clk, clrEPRdy, endPMuxErrorsWEn, frameNum, getPacketREn, getPacketRdy, rst, sendPacketPID, sendPacketRdy, sendPacketWEn, stallSent, transDone);
+input   CRCError;
+input   [7:0] RxByte;
+input   RxDataWEn;
+input   RxOverflow;
+input   [7:0] RxStatus;
+input   RxTimeOut;
+input   SCGlobalEn;
+input   [3:0] USBEndPControlReg;
+input   [6:0] USBTgtAddress;
+input   bitStuffError;
+input   clk;
+input   getPacketRdy;
+input   rst;
+input   sendPacketRdy;
+output  NAKSent;
+output  SOFRxed;
+output  [1:0] USBEndPNakTransTypeReg;
+output  [1:0] USBEndPTransTypeReg;
+output  [3:0] USBEndP;
+output  clrEPRdy;
+output  endPMuxErrorsWEn;
+output  [10:0] frameNum;
+output  getPacketREn;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+output  stallSent;
+output  transDone;
+
+wire    CRCError;
+reg     NAKSent, next_NAKSent;
+wire    [7:0] RxByte;
+wire    RxDataWEn;
+wire    RxOverflow;
+wire    [7:0] RxStatus;
+wire    RxTimeOut;
+wire    SCGlobalEn;
+reg     SOFRxed, next_SOFRxed;
+wire    [3:0] USBEndPControlReg;
+reg     [1:0] USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg     [1:0] USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+reg     [3:0] USBEndP, next_USBEndP;
+wire    [6:0] USBTgtAddress;
+wire    bitStuffError;
+wire    clk;
+reg     clrEPRdy, next_clrEPRdy;
+reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg     [10:0] frameNum, next_frameNum;
+reg     getPacketREn, next_getPacketREn;
+wire    getPacketRdy;
+wire    rst;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     stallSent, next_stallSent;
+reg     transDone, next_transDone;
+
+// diagram signals declarations
+reg  [7:0]PIDByte, next_PIDByte;
+reg  [6:0]USBAddress, next_USBAddress;
+reg  [7:0]addrEndPTemp, next_addrEndPTemp;
+reg  [7:0]endpCRCTemp, next_endpCRCTemp;
+reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define IN_DATA 5'b01011
+`define IN_GET_RESP 5'b01100
+`define SETUP_OUT_CHK 5'b01101
+`define SETUP_OUT_SEND 5'b01110
+`define SETUP_OUT_GET_PKT 5'b01111
+`define START_S1 5'b10000
+`define GET_TOKEN_DELAY 5'b10001
+`define GET_TOKEN_CHK_ADDR 5'b10010
+
+reg [4:0] CurrState_slvCntrl;
+reg [4:0] NextState_slvCntrl;
+
+
+//--------------------------------------------------------------------
+// Machine: slvCntrl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxByte or tempUSBEndPTransTypeReg or endpCRCTemp or addrEndPTemp or RxDataWEn or RxStatus or PIDByte or USBEndPControlReg or NAKSent or sendPacketRdy or getPacketRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or getPacketREn or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or frameNum or CurrState_slvCntrl)
+begin : slvCntrl_NextState
+	NextState_slvCntrl <= CurrState_slvCntrl;
+	// Set default values for outputs and signals
+	next_stallSent <= stallSent;
+	next_NAKSent <= NAKSent;
+	next_SOFRxed <= SOFRxed;
+	next_PIDByte <= PIDByte;
+	next_transDone <= transDone;
+	next_clrEPRdy <= clrEPRdy;
+	next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+	next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+	next_getPacketREn <= getPacketREn;
+	next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+	next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+	next_sendPacketWEn <= sendPacketWEn;
+	next_sendPacketPID <= sendPacketPID;
+	next_endpCRCTemp <= endpCRCTemp;
+	next_addrEndPTemp <= addrEndPTemp;
+	next_frameNum <= frameNum;
+	next_USBAddress <= USBAddress;
+	next_USBEndP <= USBEndP;
+	case (CurrState_slvCntrl) // synopsys parallel_case full_case
+		`WAIT_RX1:
+		begin
+			next_stallSent <= 1'b0;
+			next_NAKSent <= 1'b0;
+			next_SOFRxed <= 1'b0;
+			if (RxDataWEn == 1'b1 && 
+				RxStatus == `RX_PACKET_START && 
+				RxByte[1:0] == `TOKEN)	
+			begin
+				NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+				next_PIDByte <= RxByte;
+			end
+		end
+		`FIN_SC:
+		begin
+			next_transDone <= 1'b0;
+			next_clrEPRdy <= 1'b0;
+			next_endPMuxErrorsWEn <= 1'b0;
+			NextState_slvCntrl <= `WAIT_RX1;
+		end
+		`CHK_PID:
+			if (PIDByte[3:0] == `SETUP)	
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+				next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+				next_getPacketREn <= 1'b1;
+			end
+			else if (PIDByte[3:0] == `OUT)	
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+				next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+				next_getPacketREn <= 1'b1;
+			end
+			else if (PIDByte[3:0] == `IN)	
+			begin
+				NextState_slvCntrl <= `IN_CHK_RDY;
+				next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+			end
+			else
+				NextState_slvCntrl <= `PID_ERROR;
+		`PID_ERROR:
+			NextState_slvCntrl <= `WAIT_RX1;
+		`CHK_RDY:
+			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)	
+			begin
+				NextState_slvCntrl <= `FIN_SC;
+				next_transDone <= 1'b1;
+				next_clrEPRdy <= 1'b1;
+				next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+				next_endPMuxErrorsWEn <= 1'b1;
+			end
+			else if (NAKSent == 1'b1)	
+			begin
+				NextState_slvCntrl <= `FIN_SC;
+				next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+				next_endPMuxErrorsWEn <= 1'b1;
+			end
+			else
+				NextState_slvCntrl <= `FIN_SC;
+		`SETUP_OUT_CHK:
+			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)	
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_SEND;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `NAK;
+				next_NAKSent <= 1'b1;
+			end
+			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)	
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_SEND;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `STALL;
+				next_stallSent <= 1'b1;
+			end
+			else
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_SEND;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `ACK;
+			end
+		`SETUP_OUT_SEND:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+				NextState_slvCntrl <= `CHK_RDY;
+		end
+		`SETUP_OUT_GET_PKT:
+		begin
+			next_getPacketREn <= 1'b0;
+			if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+				bitStuffError == 1'b0 &&
+				RxOverflow == 1'b0 &&
+				RxTimeOut == 1'b0))	
+				NextState_slvCntrl <= `SETUP_OUT_CHK;
+			else if (getPacketRdy == 1'b1)	
+				NextState_slvCntrl <= `CHK_RDY;
+		end
+		`IN_NAK_STALL:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+				NextState_slvCntrl <= `CHK_RDY;
+		end
+		`IN_CHK_RDY:
+			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)	
+			begin
+				NextState_slvCntrl <= `IN_NAK_STALL;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `NAK;
+				next_NAKSent <= 1'b1;
+			end
+			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)	
+			begin
+				NextState_slvCntrl <= `IN_NAK_STALL;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `STALL;
+				next_stallSent <= 1'b1;
+			end
+			else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)	
+			begin
+				NextState_slvCntrl <= `IN_DATA;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA0;
+			end
+			else
+			begin
+				NextState_slvCntrl <= `IN_DATA;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA1;
+			end
+		`IN_DATA:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_slvCntrl <= `IN_GET_RESP;
+				next_getPacketREn <= 1'b1;
+			end
+		end
+		`IN_GET_RESP:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_slvCntrl <= `CHK_RDY;
+		end
+		`START_S1:
+			NextState_slvCntrl <= `WAIT_RX1;
+		`GET_TOKEN_WAIT_CRC:
+			if (RxDataWEn == 1'b1 && 
+				RxStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+				next_endpCRCTemp <= RxByte;
+			end
+			else if (RxDataWEn == 1'b1 && 
+				RxStatus != `RX_PACKET_STREAM)	
+				NextState_slvCntrl <= `WAIT_RX1;
+		`GET_TOKEN_WAIT_ADDR:
+			if (RxDataWEn == 1'b1 && 
+				RxStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+				next_addrEndPTemp <= RxByte;
+			end
+			else if (RxDataWEn == 1'b1 && 
+				RxStatus != `RX_PACKET_STREAM)	
+				NextState_slvCntrl <= `WAIT_RX1;
+		`GET_TOKEN_WAIT_STOP:
+			if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+				RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+				RxByte [`RX_OVERFLOW_BIT] == 1'b0))	
+				NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+			else if (RxDataWEn == 1'b1)	
+				NextState_slvCntrl <= `WAIT_RX1;
+		`GET_TOKEN_CHK_SOF:
+			if (PIDByte[3:0] == `SOF)	
+			begin
+				NextState_slvCntrl <= `WAIT_RX1;
+				next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+				next_SOFRxed <= 1'b1;
+			end
+			else
+			begin
+				NextState_slvCntrl <= `GET_TOKEN_DELAY;
+				next_USBAddress <= addrEndPTemp[6:0];
+				next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+			end
+		`GET_TOKEN_DELAY:		// Insert delay to allow USBEndPControlReg to update
+			NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+		`GET_TOKEN_CHK_ADDR:
+			if (USBEndP < `NUM_OF_ENDPOINTS  &&
+				USBAddress == USBTgtAddress &&
+				SCGlobalEn == 1'b1 &&
+				USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)	
+				NextState_slvCntrl <= `CHK_PID;
+			else
+				NextState_slvCntrl <= `WAIT_RX1;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_CurrentState
+	if (rst)	
+		CurrState_slvCntrl <= `START_S1;
+	else
+		CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_RegOutput
+	if (rst)	
+	begin
+		tempUSBEndPTransTypeReg <= 2'b00;
+		addrEndPTemp <= 8'h00;
+		endpCRCTemp <= 8'h00;
+		USBAddress <= 7'b0000000;
+		PIDByte <= 8'h00;
+		transDone <= 1'b0;
+		getPacketREn <= 1'b0;
+		sendPacketPID <= 4'b0;
+		sendPacketWEn <= 1'b0;
+		clrEPRdy <= 1'b0;
+		USBEndPTransTypeReg <= 2'b00;
+		USBEndPNakTransTypeReg <= 2'b00;
+		NAKSent <= 1'b0;
+		stallSent <= 1'b0;
+		SOFRxed <= 1'b0;
+		endPMuxErrorsWEn <= 1'b0;
+		frameNum <= 11'b00000000000;
+		USBEndP <= 4'h0;
+	end
+	else 
+	begin
+		tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+		addrEndPTemp <= next_addrEndPTemp;
+		endpCRCTemp <= next_endpCRCTemp;
+		USBAddress <= next_USBAddress;
+		PIDByte <= next_PIDByte;
+		transDone <= next_transDone;
+		getPacketREn <= next_getPacketREn;
+		sendPacketPID <= next_sendPacketPID;
+		sendPacketWEn <= next_sendPacketWEn;
+		clrEPRdy <= next_clrEPRdy;
+		USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+		USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+		NAKSent <= next_NAKSent;
+		stallSent <= next_stallSent;
+		SOFRxed <= next_SOFRxed;
+		endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+		frameNum <= next_frameNum;
+		USBEndP <= next_USBEndP;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processTxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processTxByte.v	(revision 264)
@@ -0,0 +1,308 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processTxByte.v
+// Generated   : 08/29/04 21:36:09
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processTxByte.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [7:0] TxByteCtrlIn;
+input   [7:0] TxByteIn;
+input   USBWireGnt;
+input   USBWireRdy;
+input   clk;
+input   processTxByteWEn;
+input   rst;
+output  USBWireCtrl;
+output  [1:0] USBWireData;
+output  USBWireReq;
+output  USBWireWEn;
+output  processTxByteRdy;
+
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [7:0] TxByteCtrlIn;
+wire    [7:0] TxByteIn;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0] USBWireData, next_USBWireData;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+reg     processTxByteRdy, next_processTxByteRdy;
+wire    processTxByteWEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [1:0]TXLineState, next_TXLineState;
+reg  [3:0]TXOneCount, next_TXOneCount;
+reg  [7:0]TxByteCtrl, next_TxByteCtrl;
+reg  [7:0]TxByte, next_TxByte;
+reg  [3:0]i, next_i;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 4'b0000
+`define PTBY_WAIT_EN 4'b0001
+`define SEND_BYTE_UPDATE_BYTE 4'b0010
+`define SEND_BYTE_WAIT_RDY 4'b0011
+`define SEND_BYTE_CHK 4'b0100
+`define SEND_BYTE_BIT_STUFF 4'b0101
+`define SEND_BYTE_WAIT_RDY2 4'b0110
+`define SEND_BYTE_CHK_FIN 4'b0111
+`define PTBY_WAIT_GNT 4'b1000
+`define STOP_SND_SE0_2 4'b1001
+`define STOP_SND_SE0_1 4'b1010
+`define STOP_CHK 4'b1011
+`define STOP_SND_J 4'b1100
+`define STOP_SND_IDLE 4'b1101
+`define STOP_FIN 4'b1110
+
+reg [3:0] CurrState_prcTxB;
+reg [3:0] NextState_prcTxB;
+
+
+//--------------------------------------------------------------------
+// Machine: prcTxB
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (TxByteIn or TxByteCtrlIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
+begin : prcTxB_NextState
+	NextState_prcTxB <= CurrState_prcTxB;
+	// Set default values for outputs and signals
+	next_processTxByteRdy <= processTxByteRdy;
+	next_USBWireData <= USBWireData;
+	next_USBWireCtrl <= USBWireCtrl;
+	next_USBWireReq <= USBWireReq;
+	next_USBWireWEn <= USBWireWEn;
+	next_i <= i;
+	next_TxByte <= TxByte;
+	next_TxByteCtrl <= TxByteCtrl;
+	next_TXLineState <= TXLineState;
+	next_TXOneCount <= TXOneCount;
+	case (CurrState_prcTxB) // synopsys parallel_case full_case
+		`START_PTBY:
+		begin
+			next_processTxByteRdy <= 1'b0;
+			next_USBWireData <= 2'b00;
+			next_USBWireCtrl <= `TRI_STATE;
+			next_USBWireReq <= 1'b0;
+			next_USBWireWEn <= 1'b0;
+			next_i <= 4'h0;
+			next_TxByte <= 8'h00;
+			next_TxByteCtrl <= 8'h00;
+			next_TXLineState <= 2'b0;
+			next_TXOneCount <= 4'h0;
+			NextState_prcTxB <= `PTBY_WAIT_EN;
+		end
+		`PTBY_WAIT_EN:
+		begin
+			next_processTxByteRdy <= 1'b1;
+			if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))	
+			begin
+				NextState_prcTxB <= `PTBY_WAIT_GNT;
+				next_processTxByteRdy <= 1'b0;
+				next_TxByte <= TxByteIn;
+				next_TxByteCtrl <= TxByteCtrlIn;
+				next_TXOneCount <= 1;
+				next_TXLineState <= JBit;
+				next_USBWireReq <= 1'b1;
+			end
+			else if (processTxByteWEn == 1'b1)	
+			begin
+				NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+				next_processTxByteRdy <= 1'b0;
+				next_TxByte <= TxByteIn;
+				next_TxByteCtrl <= TxByteCtrlIn;
+				next_i <= 4'h0;
+			end
+		end
+		`PTBY_WAIT_GNT:
+			if (USBWireGnt == 1'b1)	
+			begin
+				NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+				next_i <= 4'h0;
+			end
+		`SEND_BYTE_UPDATE_BYTE:
+		begin
+			next_i <= i + 1'b1;
+			next_TxByte <= {1'b0, TxByte[7:1] };
+			if (TxByte[0] == 1'b1)                      //If this bit is 1, then
+			  next_TXOneCount <= TXOneCount + 1'b1;
+			    //increment 'TXOneCount'
+			else                                        //else this is a zero bit
+			begin
+			  next_TXOneCount <= 4'h1;
+			    //reset 'TXOneCount'
+			  if (TXLineState == JBit) next_TXLineState <= KBit;
+			    //toggle the line state
+			  else next_TXLineState <= JBit;
+			end
+			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+		end
+		`SEND_BYTE_WAIT_RDY:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `SEND_BYTE_CHK;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= TXLineState;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		`SEND_BYTE_CHK:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (TXOneCount == 4'h6)	
+				NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+			else if (i != 4'h8)	
+				NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+			else
+				NextState_prcTxB <= `STOP_CHK;
+		end
+		`SEND_BYTE_BIT_STUFF:
+		begin
+			next_TXOneCount <= 4'h1;
+			//reset 'TXOneCount'
+			if (TXLineState == JBit) next_TXLineState <= KBit;
+			//toggle the line state
+			else next_TXLineState <= JBit;
+			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+		end
+		`SEND_BYTE_WAIT_RDY2:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= TXLineState;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		`SEND_BYTE_CHK_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (i == 4'h8)	
+				NextState_prcTxB <= `STOP_CHK;
+			else
+				NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+		end
+		`STOP_SND_SE0_2:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `STOP_SND_J;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= `SE0;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		end
+		`STOP_SND_SE0_1:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `STOP_SND_SE0_2;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= `SE0;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		`STOP_CHK:
+			if (TxByteCtrl == `DATA_STOP)	
+				NextState_prcTxB <= `STOP_SND_SE0_1;
+			else
+				NextState_prcTxB <= `PTBY_WAIT_EN;
+		`STOP_SND_J:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `STOP_SND_IDLE;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		end
+		`STOP_SND_IDLE:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `STOP_FIN;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+			end
+		end
+		`STOP_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_USBWireReq <= 1'b0;
+			//release the wire
+			NextState_prcTxB <= `PTBY_WAIT_EN;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prcTxB_CurrentState
+	if (rst)	
+		CurrState_prcTxB <= `START_PTBY;
+	else
+		CurrState_prcTxB <= NextState_prcTxB;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prcTxB_RegOutput
+	if (rst)	
+	begin
+		i <= 4'h0;
+		TxByte <= 8'h00;
+		TxByteCtrl <= 8'h00;
+		TXLineState <= 2'b0;
+		TXOneCount <= 4'h0;
+		processTxByteRdy <= 1'b0;
+		USBWireData <= 2'b00;
+		USBWireCtrl <= `TRI_STATE;
+		USBWireReq <= 1'b0;
+		USBWireWEn <= 1'b0;
+	end
+	else 
+	begin
+		i <= next_i;
+		TxByte <= next_TxByte;
+		TxByteCtrl <= next_TxByteCtrl;
+		TXLineState <= next_TXLineState;
+		TXOneCount <= next_TXOneCount;
+		processTxByteRdy <= next_processTxByteRdy;
+		USBWireData <= next_USBWireData;
+		USBWireCtrl <= next_USBWireCtrl;
+		USBWireReq <= next_USBWireReq;
+		USBWireWEn <= next_USBWireWEn;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/siereceiver.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/siereceiver.v	(revision 264)
@@ -0,0 +1,328 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\siereceiver.v
+// Generated   : 09/06/04 06:18:21
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\siereceiver.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (RxBitsOut, RxWireDataIn, RxWireDataWEn, SIERxRdyOut, clk, connectState, processRxBitRdyIn, processRxBitsWEn, rst);
+input   [1:0] RxWireDataIn;
+input   RxWireDataWEn;
+input   clk;
+input   processRxBitRdyIn;
+input   rst;
+output  [1:0] RxBitsOut;
+output  SIERxRdyOut;
+output  [1:0] connectState;
+output  processRxBitsWEn;
+
+reg     [1:0] RxBitsOut, next_RxBitsOut;
+wire    [1:0] RxWireDataIn;
+wire    RxWireDataWEn;
+reg     SIERxRdyOut, next_SIERxRdyOut;
+wire    clk;
+reg     [1:0] connectState, next_connectState;
+wire    processRxBitRdyIn;
+reg     processRxBitsWEn, next_processRxBitsWEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg  [7:0]RXWaitCount, next_RXWaitCount;
+reg  [1:0]RxBits, next_RxBits;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define LS_CONN_PROC_RX_BITS 4'b0110
+`define FS_CONN_CHK_RX_BITS1 4'b0111
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b1000
+`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
+`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
+`define FS_CONN_PROC_RX_BITS1 4'b1100
+
+reg [3:0] CurrState_rcvr;
+reg [3:0] NextState_rcvr;
+
+
+//--------------------------------------------------------------------
+// Machine: rcvr
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or processRxBitRdyIn or SIERxRdyOut or connectState or RxBitsOut or processRxBitsWEn or CurrState_rcvr)
+begin : rcvr_NextState
+	NextState_rcvr <= CurrState_rcvr;
+	// Set default values for outputs and signals
+	next_RxBits <= RxBits;
+	next_SIERxRdyOut <= SIERxRdyOut;
+	next_RXStMachCurrState <= RXStMachCurrState;
+	next_RXWaitCount <= RXWaitCount;
+	next_connectState <= connectState;
+	next_RxBitsOut <= RxBitsOut;
+	next_processRxBitsWEn <= processRxBitsWEn;
+	case (CurrState_rcvr) // synopsys parallel_case full_case
+		`WAIT_BIT:
+			if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))	
+			begin
+				NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))	
+			begin
+				NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))	
+			begin
+				NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))	
+			begin
+				NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))	
+			begin
+				NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))	
+			begin
+				NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))	
+			begin
+				NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+		`START_SRX:
+		begin
+			next_RXStMachCurrState <= `DISCONNECT_ST;
+			next_RXWaitCount <= 8'h00;
+			next_connectState <= `DISCONNECT;
+			next_RxBits <= 2'b00;
+			next_RxBitsOut <= 2'b00;
+			next_processRxBitsWEn <= 1'b0;
+			next_SIERxRdyOut <= 1'b1;
+			NextState_rcvr <= `WAIT_BIT;
+		end
+		`DISCNCT_CHK_RXBITS:
+			if (RxBits == `ZERO_ONE)	
+			begin
+				NextState_rcvr <= `WAIT_BIT;
+				next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+				next_RXWaitCount <= 8'h00;
+				next_SIERxRdyOut <= 1'b1;
+			end
+			else if (RxBits == `ONE_ZERO)	
+			begin
+				NextState_rcvr <= `WAIT_BIT;
+				next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+				next_RXWaitCount <= 8'h00;
+				next_SIERxRdyOut <= 1'b1;
+			end
+			else
+			begin
+				NextState_rcvr <= `WAIT_BIT;
+				next_SIERxRdyOut <= 1'b1;
+			end
+		`WAIT_FS_CONN_CHK_RX_BITS:
+		begin
+			if (RxBits == `ONE_ZERO)
+			begin
+			  next_RXWaitCount <= RXWaitCount + 1'b1;
+			    if (RXWaitCount == `CONNECT_WAIT_TIME)
+			    begin
+			    next_connectState <= `FULL_SPEED_CONNECT;
+			    next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+			    end
+			end
+			else
+			begin
+			  next_RXStMachCurrState = `DISCONNECT_ST;
+			end
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`WAIT_LS_CONN_CHK_RX_BITS:
+		begin
+			if (RxBits == `ZERO_ONE)
+			begin
+			  next_RXWaitCount <= RXWaitCount + 1'b1;
+			    if (RXWaitCount == `CONNECT_WAIT_TIME)
+			    begin
+			    next_connectState <= `LOW_SPEED_CONNECT;
+			    next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+			    end
+			end
+			else
+			begin
+			  next_RXStMachCurrState = `DISCONNECT_ST;
+			end
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`LS_CONN_CHK_RX_BITS:
+			if (processRxBitRdyIn == 1'b1)	
+			begin
+				NextState_rcvr <= `LS_CONN_PROC_RX_BITS;
+				if (RxBits == `SE0)
+				begin
+				  next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+				  next_RXWaitCount <= 0;
+				end
+				next_processRxBitsWEn <= 1'b1;
+				next_RxBitsOut <= RxBits;
+			end
+		`LS_CONN_PROC_RX_BITS:
+		begin
+			next_processRxBitsWEn <= 1'b0;
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`FS_CONN_CHK_RX_BITS1:
+			if (processRxBitRdyIn == 1'b1)	
+			begin
+				NextState_rcvr <= `FS_CONN_PROC_RX_BITS1;
+				if (RxBits == `SE0)
+				begin
+				  next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+				  next_RXWaitCount <= 0;
+				end
+				next_processRxBitsWEn <= 1'b1;
+				next_RxBitsOut <= RxBits;
+				next_SIERxRdyOut <= 1'b1;
+				//early indication of ready
+			end
+		`FS_CONN_PROC_RX_BITS1:
+		begin
+			next_processRxBitsWEn <= 1'b0;
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`WAIT_LS_DIS_CHK_RX_BITS:
+			if (processRxBitRdyIn == 1'b1)	
+			begin
+				NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS;
+				if (RxBits == `SE0)
+				begin
+				  next_RXWaitCount <= RXWaitCount + 1'b1;
+				    if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+				    begin
+				    next_RXStMachCurrState <= `DISCONNECT_ST;
+				    next_connectState = `DISCONNECT;
+				    end
+				end
+				else
+				begin
+				  next_RXStMachCurrState = `CONNECT_LOW_SPEED_ST;
+				end
+				next_processRxBitsWEn <= 1'b1;
+			end
+		`WAIT_LS_DIS_PROC_RX_BITS:
+		begin
+			next_processRxBitsWEn <= 1'b0;
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`WAIT_FS_DIS_PROC_RX_BITS2:
+		begin
+			next_processRxBitsWEn <= 1'b0;
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`WAIT_FS_DIS_CHK_RX_BITS2:
+			if (processRxBitRdyIn == 1'b1)	
+			begin
+				NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2;
+				if (RxBits == `SE0)
+				begin
+				  next_RXWaitCount <= RXWaitCount + 1'b1;
+				    if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+				    begin
+				    next_RXStMachCurrState <= `DISCONNECT_ST;
+				    next_connectState = `DISCONNECT;
+				    end
+				end
+				else
+				begin
+				  next_RXStMachCurrState = `CONNECT_FULL_SPEED_ST;
+				end
+				next_processRxBitsWEn <= 1'b1;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : rcvr_CurrentState
+	if (rst)	
+		CurrState_rcvr <= `START_SRX;
+	else
+		CurrState_rcvr <= NextState_rcvr;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : rcvr_RegOutput
+	if (rst)	
+	begin
+		RXStMachCurrState <= `DISCONNECT_ST;
+		RXWaitCount <= 8'h00;
+		RxBits <= 2'b00;
+		connectState <= `DISCONNECT;
+		RxBitsOut <= 2'b00;
+		processRxBitsWEn <= 1'b0;
+		SIERxRdyOut <= 1'b1;
+	end
+	else 
+	begin
+		RXStMachCurrState <= next_RXStMachCurrState;
+		RXWaitCount <= next_RXWaitCount;
+		RxBits <= next_RxBits;
+		connectState <= next_connectState;
+		RxBitsOut <= next_RxBitsOut;
+		processRxBitsWEn <= next_processRxBitsWEn;
+		SIERxRdyOut <= next_SIERxRdyOut;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(revision 264)
@@ -0,0 +1,375 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine.v                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSerialInterfaceEngine.v,v 1.1.1.1 2004-10-11 04:01:04 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module usbSerialInterfaceEngine(
+	clk, rst,
+	//readUSBWireData
+	USBWireDataIn,
+	USBWireDataInTick,
+	//writeUSBWireData
+	USBWireDataOut,
+	USBWireCtrlOut,
+	USBWireDataOutTick,
+	//SIEReceiver
+	connectState,
+	//processRxBit
+	resumeDetected,
+	//processRxByte
+	RxCtrlOut, 
+	RxDataOutWEn, 
+	RxDataOut, 
+    //SIETransmitter
+	SIEPortCtrlIn,
+	SIEPortDataIn, 
+	SIEPortTxRdy, 
+	SIEPortWEn, 
+    //lineControlUpdate
+	fullSpeedPolarity,
+	fullSpeedBitRate,
+  noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut; 
+output RxDataOutWEn; 
+output [7:0] RxDataOut; 
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy; 
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut; 
+wire RxDataOutWEn; 
+wire [7:0] RxDataOut; 
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy; 
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire [1:0] RxBitsFromSIERxToPrRxBit;
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRxToSIERx;
+wire RxWireDataWEn;
+wire SIERxRdyOut;
+wire disableWireRead;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En; 
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En; 
+wire [4:0] RxCRC5Result; 
+wire RxCRC5_8Bit; 
+wire [7:0] RxCRCData; 
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En; 
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En; 
+wire [4:0] TxCRC5Result; 
+wire TxCRC5_8Bit; 
+wire [7:0] TxCRCData; 
+wire TxRstCRC; 
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy; 
+wire processTxByteWEn; 
+
+lineControlUpdate u_lineControlUpdate
+	(.fullSpeedPolarity(fullSpeedPolarity),
+	.fullSpeedBitRate(fullSpeedBitRate),
+	.JBit(JBit),
+	.KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+	(.RxBitsOut(RxBitsFromSIERxToPrRxBit),
+	.RxWireDataIn(RxWireDataFromWireRxToSIERx), 
+	.RxWireDataWEn(RxWireDataWEn), 
+	.SIERxRdyOut(SIERxRdyOut), 
+	.clk(clk),
+	.connectState(connectState),
+	.processRxBitRdyIn(processRxBitRdy), 
+	.processRxBitsWEn(processRxBitsWEn), 
+	.rst(rst) );
+	
+processRxBit u_processRxBit
+	(.JBit(JBit), 
+	.KBit(KBit), 
+	.RxBitsIn(RxBitsFromSIERxToPrRxBit), 
+	.RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), 
+	.RxDataOut(RxDataFromPrcRxBitToPrcRxByte), 
+	.clk(clk), 
+	.processRxBitRdy(processRxBitRdy), 
+	.processRxBitsWEn(processRxBitsWEn), 
+	.processRxByteWEn(processRxByteWEn), 
+	.resumeDetected(resumeDetected), 
+	.rst(rst),
+  .processRxByteRdy(processRxByteRdy) );
+	
+processRxByte u_processRxByte
+	(.CRC16En(RxCRC16En), 
+	.CRC16Result(RxCRC16Result), 
+  .CRC16UpdateRdy(RxCRC16UpdateRdy),
+	.CRC5En(RxCRC5En), 
+	.CRC5Result(RxCRC5Result), 
+	.CRC5_8Bit(RxCRC5_8Bit),
+  .CRC5UpdateRdy(RxCRC5UpdateRdy),
+	.CRCData(RxCRCData), 
+	.RxByteIn(RxDataFromPrcRxBitToPrcRxByte), 
+	.RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), 
+	.RxCtrlOut(RxCtrlOut), 
+	.RxDataOutWEn(RxDataOutWEn), 
+	.RxDataOut(RxDataOut), 
+	.clk(clk), 
+	.processRxDataInWEn(processRxByteWEn), 
+	.rst(rst), 
+	.rstCRC(RxRstCRC),
+  .processRxByteRdy(processRxByteRdy) ); 
+	
+	
+updateCRC5 RxUpdateCRC5
+	(.rstCRC(RxRstCRC), 
+	.CRCResult(RxCRC5Result), 
+	.CRCEn(RxCRC5En), 
+	.CRC5_8BitIn(RxCRC5_8Bit), 
+	.dataIn(RxCRCData), 
+  .ready(RxCRC5UpdateRdy),
+	.clk(clk), 
+	.rst(rst) );  
+	
+updateCRC16 RxUpdateCRC16
+	(.rstCRC(RxRstCRC), 
+	.CRCResult(RxCRC16Result), 
+	.CRCEn(RxCRC16En), 
+	.dataIn(RxCRCData), 
+  .ready(RxCRC16UpdateRdy),
+	.clk(clk), 
+	.rst(rst) );	
+	
+SIETransmitter u_SIETransmitter
+	(.CRC16En(TxCRC16En), 
+	.CRC16Result(TxCRC16Result), 
+	.CRC5En(TxCRC5En), 
+	.CRC5Result(TxCRC5Result), 
+	.CRC5_8Bit(TxCRC5_8Bit), 
+	.CRCData(TxCRCData),
+  .CRC5UpdateRdy(TxCRC5UpdateRdy),
+  .CRC16UpdateRdy(TxCRC16UpdateRdy),
+	.JBit(JBit), 
+	.KBit(KBit), 
+	.SIEPortCtrlIn(SIEPortCtrlIn),
+	.SIEPortDataIn(SIEPortDataIn), 
+	.SIEPortTxRdy(SIEPortTxRdy), 
+	.SIEPortWEn(SIEPortWEn), 
+	.TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), 
+	.TxByteOut(TxByteFromSIEToPrcTxByte), 
+	.USBWireCtrl(SIETxCtrl), 
+	.USBWireData(SIETxData), 
+	.USBWireGnt(SIETxGnt), 
+	.USBWireRdy(USBWireReadyFromTxArb), 
+	.USBWireReq(SIETxReq), 
+	.USBWireWEn(SIETxWEn), 
+	.clk(clk), 
+	.processTxByteRdy(processTxByteRdy), 
+	.processTxByteWEn(processTxByteWEn), 
+	.rst(rst), 
+	.rstCRC(TxRstCRC) );	  
+
+updateCRC5 TxUpdateCRC5
+	(.rstCRC(TxRstCRC), 
+	.CRCResult(TxCRC5Result), 
+	.CRCEn(TxCRC5En), 
+	.CRC5_8BitIn(TxCRC5_8Bit), 
+	.dataIn(TxCRCData),
+  .ready(TxCRC5UpdateRdy),
+	.clk(clk), 
+	.rst(rst) );  
+	
+updateCRC16 TxUpdateCRC16
+	(.rstCRC(TxRstCRC), 
+	.CRCResult(TxCRC16Result), 
+	.CRCEn(TxCRC16En), 
+	.dataIn(TxCRCData), 
+  .ready(TxCRC16UpdateRdy),
+	.clk(clk), 
+	.rst(rst) );	
+
+processTxByte u_processTxByte
+	(.JBit(JBit), 
+	.KBit(KBit), 
+	.TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), 
+	.TxByteIn(TxByteFromSIEToPrcTxByte), 
+	.USBWireCtrl(prcTxByteCtrl), 
+	.USBWireData(prcTxByteData), 
+	.USBWireGnt(prcTxByteGnt), 
+	.USBWireRdy(USBWireReadyFromTxArb), 
+	.USBWireReq(prcTxByteReq), 
+	.USBWireWEn(prcTxByteWEn), 
+	.clk(clk), 
+	.processTxByteRdy(processTxByteRdy), 
+	.processTxByteWEn(processTxByteWEn), 
+	.rst(rst) ); 
+	
+USBWireTxArbiter u_USBWireTxArbiter
+	(.SIETxCtrl(SIETxCtrl), 
+	.SIETxData(SIETxData), 
+	.SIETxGnt(SIETxGnt), 
+	.SIETxReq(SIETxReq), 
+	.SIETxWEn(SIETxWEn), 
+	.TxBits(TxBitsFromArbToWire), 
+	.TxCtl(TxCtrlFromArbToWire), 
+	.USBWireRdyIn(USBWireRdy), 
+	.USBWireRdyOut(USBWireReadyFromTxArb), 
+	.USBWireWEn(USBWireWEn),
+	.clk(clk), 
+	.prcTxByteCtrl(prcTxByteCtrl), 
+	.prcTxByteData(prcTxByteData), 
+	.prcTxByteGnt(prcTxByteGnt), 
+	.prcTxByteReq(prcTxByteReq), 
+	.prcTxByteWEn(prcTxByteWEn), 
+	.rst(rst) ); 
+	
+writeUSBWireData u_writeUSBWireData
+	(.TxBitsIn(TxBitsFromArbToWire), 
+	.TxBitsOut(USBWireDataOut), 
+	.TxDataOutTick(USBWireDataOutTick),
+	.TxCtrlIn(TxCtrlFromArbToWire), 
+	.TxCtrlOut(USBWireCtrlOut), 
+	.USBWireRdy(USBWireRdy), 
+	.USBWireWEn(USBWireWEn),
+	.disableWireReadOut(disableWireRead),
+	.fullSpeedRate(fullSpeedBitRate), 
+	.clk(clk),
+	.rst(rst),
+  .noActivityTimeOut(noActivityTimeOut) );  
+	
+readUSBWireData u_readUSBWireData
+	(.RxBitsIn(USBWireDataIn), 
+	.RxDataInTick(USBWireDataInTick),
+	.RxBitsOut(RxWireDataFromWireRxToSIERx), 
+	.SIERxRdyIn(SIERxRdyOut), 
+	.SIERxWEn(RxWireDataWEn), 
+	.fullSpeedRate(fullSpeedBitRate), 
+	.disableWireRead(disableWireRead),
+	.clk(clk),
+	.rst(rst) );
+
+
+endmodule
+
+	
+	
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v	(revision 264)
@@ -0,0 +1,308 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// writeUSBWireData.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: writeUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:05 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL  3'b100
+
+module writeUSBWireData (
+  TxBitsIn, 
+  TxBitsOut,
+ 	TxDataOutTick,
+  TxCtrlIn, 
+  TxCtrlOut, 
+  USBWireRdy,
+  USBWireWEn, 
+  disableWireReadOut, 
+  fullSpeedRate, 
+  clk, 
+  rst,
+  noActivityTimeOut );
+  
+input   [1:0] TxBitsIn;
+input   TxCtrlIn;
+input   USBWireWEn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+output  [1:0] TxBitsOut;
+output TxDataOutTick;
+output  TxCtrlOut;
+output  USBWireRdy;
+output  disableWireReadOut;
+output noActivityTimeOut;
+
+wire    [1:0] TxBitsIn;
+reg     [1:0] TxBitsOut;
+reg     TxDataOutTick;
+wire    TxCtrlIn;
+reg     TxCtrlOut;
+reg     USBWireRdy;
+wire    USBWireWEn;
+wire    clk;
+wire    fullSpeedRate;
+wire    rst;
+reg  disableWireReadOut;
+reg noActivityTimeOut;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+reg [15:0] timeOutCnt;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+	end
+  else
+  begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+//buffer input state machine 
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+ 		incBufferCnt <= 1'b0;
+		bufferInIndex <= 2'b00;
+		buffer0 <= 3'b000;
+		buffer1 <= 3'b000;
+		buffer2 <= 3'b000;
+		buffer3 <= 3'b000;
+		USBWireRdy <= 1'b0;
+		bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+	end
+  else begin
+	  case (bufferInStMachCurrState)
+	  	`WAIT_BUFFER_NOT_FULL:
+	  	begin
+			  if (bufferCnt != `BUFFER_FULL)	
+			  begin
+				  bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+				  USBWireRdy <= 1'b1;
+			  end
+		  end
+		  `WAIT_WRITE_REQ:
+		  begin
+			  if (USBWireWEn == 1'b1)
+			  begin
+				  incBufferCnt <= 1'b1;
+				  USBWireRdy <= 1'b0;
+				  bufferInIndex <= bufferInIndex + 1'b1;
+				  case (bufferInIndex)
+					  2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+					  2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+					  2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+					  2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+				  endcase
+				  bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+			  end
+		  end
+		  `CLR_INC_BUFFER_CNT:
+		  begin
+			  incBufferCnt <= 1'b0;
+			  if (bufferCnt != (`BUFFER_FULL - 1'b1) )	
+			  begin
+				  bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+				  USBWireRdy <= 1'b1;
+			  end
+        else begin
+		      bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+        end
+		  end
+	  endcase
+  end
+end
+				
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    fullSpeedTick <= 1'b0;
+    lowSpeedTick <= 1'b0;
+  end
+  else
+  begin
+    i <= i + 1'b1;
+    if (i[1:0] == 2'b00)
+      fullSpeedTick <= 1'b1;
+    else
+      fullSpeedTick <= 1'b0; 
+    if (i == 5'b00000)
+      lowSpeedTick <= 1'b1;
+    else
+      lowSpeedTick <= 1'b0;
+  end
+end
+
+//buffer output state machine
+//After reset, waits for the output buffer to become full.
+//Once the buffer is full then it is constantly emptied at either
+//the full or low speed rate with no under run protection
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+		bufferOutIndex <= 2'b00;
+		decBufferCnt <= 1'b0;
+		TxBitsOut <= 2'b00;
+		TxCtrlOut <= `TRI_STATE;
+    TxDataOutTick <= 1'b0;
+		bufferOutStMachCurrState <= `WAIT_BUFFER_FULL;
+	end
+  else
+  begin
+	  case (bufferOutStMachCurrState)
+		  `WAIT_BUFFER_FULL:
+		  begin
+			  if (bufferCnt == `BUFFER_FULL)
+				  bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+		  end
+		  `WAIT_LINE_WRITE:
+		  begin
+			  if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+			  begin
+          TxDataOutTick <= !TxDataOutTick;
+				  bufferOutStMachCurrState <= `LINE_WRITE;
+				  decBufferCnt <= 1'b1;
+				  bufferOutIndex <= bufferOutIndex + 1'b1;
+				  case (bufferOutIndex)
+  				  2'b00 :
+				  begin 
+					  TxBitsOut <= buffer0[2:1];
+					  TxCtrlOut <= buffer0[0];
+				  end
+				  2'b01 : 
+				  begin
+					  TxBitsOut <= buffer1[2:1];
+					  TxCtrlOut <= buffer1[0];
+				  end
+				  2'b10 : 
+				  begin 
+					  TxBitsOut <= buffer2[2:1];
+					  TxCtrlOut <= buffer2[0];
+				  end
+				  2'b11 : 
+				  begin
+					  TxBitsOut <= buffer3[2:1];
+					  TxCtrlOut <= buffer3[0];
+				  end
+				  endcase
+			  end
+		  end
+		  `LINE_WRITE:
+		  begin
+			  decBufferCnt <= 1'b0;
+			  bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+		  end
+	  endcase
+  end
+end
+
+// control 'disableWireReadOut' 
+always @(TxCtrlOut)
+begin	
+	if (TxCtrlOut == `DRIVE)
+		disableWireReadOut <= 1'b1;
+	else
+		disableWireReadOut <= 1'b0;
+end
+
+//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks
+always @(posedge clk) begin
+  if (rst) begin
+    timeOutCnt <= 16'h0000;
+    noActivityTimeOut <= 1'b0;
+  end
+  else begin
+    if (TxCtrlOut == `DRIVE)
+      timeOutCnt <= 16'h0000;
+    else 
+      timeOutCnt <= timeOutCnt + 1'b1;
+    //if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
+    if (timeOutCnt == 16'h200)  //temporary fix
+      noActivityTimeOut <= 1'b1;
+    else
+      noActivityTimeOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/fifoMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/fifoMux.v	(revision 264)
@@ -0,0 +1,217 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoMux.v,v 1.1.1.1 2004-10-11 04:01:05 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module fifoMux (
+  currEndP,
+  //TxFifo
+  TxFifoREn,
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoData,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEmpty,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  //RxFifo
+  RxFifoWEn,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoFull,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+  //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+  //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+  TxFifoREn or
+  RxFifoWEn or
+  TxFifoEP0Data or
+  TxFifoEP1Data or
+  TxFifoEP2Data or
+  TxFifoEP3Data or
+  TxFifoEP0Empty or
+  TxFifoEP1Empty or
+  TxFifoEP2Empty or
+  TxFifoEP3Empty or
+  RxFifoEP0Full or
+  RxFifoEP1Full or
+  RxFifoEP2Full or
+  RxFifoEP3Full)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      TxFifoEP0REn <= TxFifoREn;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP0Data;
+      TxFifoEmpty <= TxFifoEP0Empty;
+      RxFifoEP0WEn <= RxFifoWEn;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP0Full;
+    end
+    2'b01: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= TxFifoREn;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP1Data;
+      TxFifoEmpty <= TxFifoEP1Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= RxFifoWEn;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP1Full;
+    end
+    2'b10: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= TxFifoREn;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP2Data;
+      TxFifoEmpty <= TxFifoEP2Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= RxFifoWEn;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP2Full;
+    end
+    2'b11: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= TxFifoREn;
+      TxFifoData <= TxFifoEP3Data;
+      TxFifoEmpty <= TxFifoEP3Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= RxFifoWEn;
+      RxFifoFull <= RxFifoEP3Full;
+    end
+  endcase  
+end      
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveDirectcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveDirectcontrol.asf	(revision 264)
@@ -0,0 +1,132 @@
+VERSION=1.19
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FREEOID=180
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/20/2004"
+HEADER_PARAM="TITLE,slaveDirectControl"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 78
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 127
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: slaveDirectControl"
+A 5 0 1 TEXT "Actions" | 17700,253700 1 0 0 "// diagram ACTION"
+F 6 0 671089152 16 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "slvDrctCntl"
+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_SDC\n/0/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+I 13 6 0 Builtin Reset | 48900,215400
+W 14 6 0 13 9 BEZIER "Transitions" | 48900,215400 60300,214600 83007,213291 94407,212491
+L 15 16 0 TEXT "Labels" | 187300,263800 1 0 0 "clk"
+I 16 0 3 Builtin InPort | 181300,263800 "" ""
+L 17 18 0 TEXT "Labels" | 187500,257400 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 181500,257400 "" ""
+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
+L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn"
+I 21 0 2 Builtin InPort | 57252,239123 "" ""
+W 26 6 0 9 11 BEZIER "Transitions" | 100525,205718 101125,199618 101292,188766 101892,182666
+W 27 6 8193 11 78 BEZIER "Transitions" | 99393,170493 94693,161093 75357,144887 70657,135487
+C 28 27 0 TEXT "Conditions" | 80136,160617 1 0 0 "directControlEn == 1'b1"
+W 51 6 8194 11 127 BEZIER "Transitions" | 108159,173005 122851,164817 139855,136277 144754,128309
+L 77 78 0 TEXT "State Labels" | 68590,129326 1 0 0 "DRCT_CNTL"
+S 78 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 68590,129326 6500 6500
+H 79 78 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 88 79 4096 124 90 BEZIER "Transitions" | 105569,175900 100869,166500 70569,161175 65869,151775
+S 90 79 12288 ELLIPSE "States" | 62621,146145 6500 6500
+L 91 90 0 TEXT "State Labels" | 62621,146145 1 0 0 "WAIT_GNT\n/2/"
+W 92 79 8194 93 102 BEZIER "Transitions" | 62907,72842 59107,76242 50421,81945 48421,85645\
+                                           46421,89345 46021,97345 47471,100295 48921,103245\
+                                           55748,105011 58848,106911
+S 93 79 16384 ELLIPSE "States" | 68621,69745 6500 6500
+A 94 93 4 TEXT "Actions" | 87021,72145 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 95 79 0 102 93 BEZIER "Transitions" | 65496,102474 65896,97574 67230,81067 67630,76167
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= {6'b000000, directControlLineState}; \nSCTxPortCntl <= `TX_DIRECT_CONTROL;"
+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "SCTxPortRdy == 1'b1"
+L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/"
+W 99 79 0 90 102 BEZIER "Transitions" | 62834,139649 63234,133449 64005,121613 64405,115413
+C 100 99 0 TEXT "Conditions" | 62221,136545 1 0 0 "SCTxPortGnt == 1'b1"
+S 102 79 20480 ELLIPSE "States" | 65021,108945 6500 6500
+L 103 102 0 TEXT "State Labels" | 65021,108945 1 0 0 "WAIT_RDY\n/4/"
+I 122 79 0 Builtin Exit | 138103,36586
+I 124 79 0 Builtin Entry | 109800,175900
+W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\
+                                       47285,153175 50048,167625 56316,171290 62585,174956\
+                                       84856,175714 96012,175820
+L 126 127 0 TEXT "State Labels" | 147819,122579 1 0 0 "IDLE"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
+H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
+C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "SCTxPortGnt == 1'b1"
+S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "SCTxPortRdy == 1'b1"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= 8'h00; \nSCTxPortCntl <= `TX_IDLE;"
+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "SCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "SCTxPortReq <= 1'b1;"
+I 150 128 0 Builtin Entry | 67068,204814
+I 151 128 0 Builtin Exit | 67380,61048
+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+                                        171826,160150 159742,169266 150997,171704 142252,174142\
+                                        120424,175336 108976,175654
+I 154 0 2 Builtin OutPort | 108837,257571 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "SCTxPortCntl[7:0]"
+I 156 0 2 Builtin OutPort | 109440,251139 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "SCTxPortData[7:0]"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "SCTxPortWEn"
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "SCTxPortRdy"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "SCTxPortGnt"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "SCTxPortReq"
+A 166 9 2 TEXT "Actions" | 121708,221292 1 0 0 "SCTxPortCntl <= 8'h00;\nSCTxPortData <= 8'h00;\nSCTxPortWEn <= 1'b0;   \nSCTxPortReq <= 1'b0;"
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "SCTxPortReq <= 1'b1;"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+I 179 0 2 Builtin InPort | 57352,247790 "" ""
+L 178 179 0 TEXT "Labels" | 63352,247790 1 0 0 "directControlLineState[1:0]"
+A 177 174 16 TEXT "Actions" | 102262,47300 1 0 0 "SCTxPortReq <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveGetpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveGetpacket.v	(revision 264)
@@ -0,0 +1,308 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveGetpacket.v
+// Generated   : 09/22/04 06:01:23
+// From        : c:\projects\USBHostSlave\RTL\slaveController\slaveGetpacket.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, bitStuffError, clk, dataSequence, getPacketEn, rst);
+input   [7:0] RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0] RXStreamStatusIn;
+input   SIERxTimeOut;		// Single cycle pulse
+input   clk;
+input   getPacketEn;
+input   rst;
+output  ACKRxed;
+output  CRCError;
+output  [7:0] RXFifoData;
+output  RXFifoWEn;
+output  RXOverflow;
+output  RXPacketRdy;
+output  RXTimeOut;
+output  [3:0] RxPID;
+output  bitStuffError;
+output  dataSequence;
+
+reg     ACKRxed, next_ACKRxed;
+reg     CRCError, next_CRCError;
+wire    [7:0] RXDataIn;
+wire    RXDataValid;
+reg     [7:0] RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXOverflow, next_RXOverflow;
+reg     RXPacketRdy, next_RXPacketRdy;
+wire    [7:0] RXStreamStatusIn;
+reg     RXTimeOut, next_RXTimeOut;
+reg     [3:0] RxPID, next_RxPID;
+wire    SIERxTimeOut;
+reg     bitStuffError, next_bitStuffError;
+wire    clk;
+reg     dataSequence, next_dataSequence;
+wire    getPacketEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0] CurrState_slvGetPkt;
+reg [4:0] NextState_slvGetPkt;
+
+
+//--------------------------------------------------------------------
+// Machine: slvGetPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
+begin : slvGetPkt_NextState
+	NextState_slvGetPkt <= CurrState_slvGetPkt;
+	// Set default values for outputs and signals
+	next_CRCError <= CRCError;
+	next_bitStuffError <= bitStuffError;
+	next_RXOverflow <= RXOverflow;
+	next_RXTimeOut <= RXTimeOut;
+	next_ACKRxed <= ACKRxed;
+	next_dataSequence <= dataSequence;
+	next_RXByte <= RXByte;
+	next_RXStreamStatus <= RXStreamStatus;
+	next_RxPID <= RxPID;
+	next_RXPacketRdy <= RXPacketRdy;
+	next_RXByteOldest <= RXByteOldest;
+	next_RXByteOld <= RXByteOld;
+	next_RXFifoWEn <= RXFifoWEn;
+	next_RXFifoData <= RXFifoData;
+	case (CurrState_slvGetPkt) // synopsys parallel_case full_case
+		`START_GP:
+			NextState_slvGetPkt <= `WAIT_EN;
+		`WAIT_PKT:
+		begin
+			next_CRCError <= 1'b0;
+			next_bitStuffError <= 1'b0;
+			next_RXOverflow <= 1'b0;
+			next_RXTimeOut <= 1'b0;
+			next_ACKRxed <= 1'b0;
+			next_dataSequence <= 1'b0;
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `CHK_PKT_START;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		end
+		`CHK_PKT_START:
+			if (RXStreamStatus == `RX_PACKET_START)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+				next_RxPID <= RXByte[3:0];
+			end
+			else
+			begin
+				NextState_slvGetPkt <= `PKT_RDY;
+				next_RXTimeOut <= 1'b1;
+			end
+		`WAIT_EN:
+		begin
+			next_RXPacketRdy <= 1'b0;
+			if (getPacketEn == 1'b1)	
+				NextState_slvGetPkt <= `WAIT_PKT;
+		end
+		`PKT_RDY:
+		begin
+			next_RXPacketRdy <= 1'b1;
+			NextState_slvGetPkt <= `WAIT_EN;
+		end
+		`PROC_PKT_CHK_PID:
+			if (RXByte[1:0] == `HANDSHAKE)	
+				NextState_slvGetPkt <= `PROC_PKT_HS;
+			else if (RXByte[1:0] == `DATA)	
+				NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+			else
+				NextState_slvGetPkt <= `PKT_RDY;
+		`PROC_PKT_HS:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PKT_RDY;
+				next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+				next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+			end
+		`PROC_PKT_DATA_W_D1:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_CHK_D1:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+				next_RXByteOldest <= RXByte;
+			end
+			else
+				NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_W_D2:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_FIN:
+		begin
+			next_CRCError <= RXByte[`CRC_ERROR_BIT];
+			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+			NextState_slvGetPkt <= `PKT_RDY;
+		end
+		`PROC_PKT_DATA_CHK_D2:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+				next_RXByteOld <= RXByte;
+			end
+			else
+				NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_W_D3:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_CHK_D3:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+				NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+			else
+				NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_LOOP_CHK_FIFO:
+			if (RXFifoFull == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+				next_RXOverflow <= 1'b1;
+			end
+			else
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+				next_RXFifoWEn <= 1'b1;
+				next_RXFifoData <= RXByteOldest;
+				next_RXByteOldest <= RXByteOld;
+				next_RXByteOld <= RXByte;
+			end
+		`PROC_PKT_DATA_LOOP_FIFO_FULL:
+			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+		`PROC_PKT_DATA_LOOP_W_D:
+		begin
+			next_RXFifoWEn <= 1'b0;
+			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+				next_RXByte <= RXDataIn;
+			end
+			else if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+				next_RXByte <= RXDataIn;
+			end
+		end
+		`PROC_PKT_DATA_LOOP_DELAY:
+			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_CurrentState
+	if (rst)	
+		CurrState_slvGetPkt <= `START_GP;
+	else
+		CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_RegOutput
+	if (rst)	
+	begin
+		RXByteOld <= 8'h00;
+		RXByteOldest <= 8'h00;
+		RXByte <= 8'h00;
+		RXStreamStatus <= 8'h00;
+		RXPacketRdy <= 1'b0;
+		RXFifoWEn <= 1'b0;
+		RXFifoData <= 8'h00;
+		CRCError <= 1'b0;
+		bitStuffError <= 1'b0;
+		RXOverflow <= 1'b0;
+		RXTimeOut <= 1'b0;
+		ACKRxed <= 1'b0;
+		dataSequence <= 1'b0;
+		RxPID <= 4'h0;
+	end
+	else 
+	begin
+		RXByteOld <= next_RXByteOld;
+		RXByteOldest <= next_RXByteOldest;
+		RXByte <= next_RXByte;
+		RXStreamStatus <= next_RXStreamStatus;
+		RXPacketRdy <= next_RXPacketRdy;
+		RXFifoWEn <= next_RXFifoWEn;
+		RXFifoData <= next_RXFifoData;
+		CRCError <= next_CRCError;
+		bitStuffError <= next_bitStuffError;
+		RXOverflow <= next_RXOverflow;
+		RXTimeOut <= next_RXTimeOut;
+		ACKRxed <= next_ACKRxed;
+		dataSequence <= next_dataSequence;
+		RxPID <= next_RxPID;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveSendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveSendpacket.v	(revision 264)
@@ -0,0 +1,222 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveSendpacket.v
+// Generated   : 09/25/04 06:34:38
+// From        : c:\projects\USBHostSlave\RTL\slaveController\slaveSendpacket.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn);
+input   [3:0] PID;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   clk;
+input   [7:0] fifoData;
+input   fifoEmpty;
+input   rst;
+input   sendPacketWEn;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+output  fifoReadEn;
+output  sendPacketRdy;
+
+wire    [3:0] PID;
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+wire    clk;
+wire    [7:0] fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0] CurrState_slvSndPkt;
+reg [3:0] NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+    PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+//--------------------------------------------------------------------
+// Machine: slvSndPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt)
+begin : slvSndPkt_NextState
+	NextState_slvSndPkt <= CurrState_slvSndPkt;
+	// Set default values for outputs and signals
+	next_sendPacketRdy <= sendPacketRdy;
+	next_SCTxPortReq <= SCTxPortReq;
+	next_SCTxPortWEn <= SCTxPortWEn;
+	next_SCTxPortData <= SCTxPortData;
+	next_SCTxPortCntl <= SCTxPortCntl;
+	next_fifoReadEn <= fifoReadEn;
+	case (CurrState_slvSndPkt) // synopsys parallel_case full_case
+		`START_SP1:
+			NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+		`SP_WAIT_ENABLE:
+			if (sendPacketWEn == 1'b1)	
+			begin
+				NextState_slvSndPkt <= `SP1_WAIT_GNT;
+				next_sendPacketRdy <= 1'b0;
+				next_SCTxPortReq <= 1'b1;
+			end
+		`SP1_WAIT_GNT:
+			if (SCTxPortGnt == 1'b1)	
+				NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+		`FIN_SP1:
+		begin
+			NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+			next_sendPacketRdy <= 1'b1;
+			next_SCTxPortReq <= 1'b0;
+		end
+		`SP_NOT_DATA:
+			NextState_slvSndPkt <= `FIN_SP1;
+		`SP_SEND_PID_WAIT_RDY:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+				next_SCTxPortWEn <= 1'b1;
+				next_SCTxPortData <= PIDNotPID;
+				next_SCTxPortCntl <= `TX_PACKET_START;
+			end
+		`SP_SEND_PID_FIN:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			if (PID == `DATA0 || PID == `DATA1)	
+				NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+			else
+				NextState_slvSndPkt <= `SP_NOT_DATA;
+		end
+		`SP_D0_D1_READ_FIFO:
+		begin
+			next_SCTxPortWEn <= 1'b1;
+			next_SCTxPortData <= fifoData;
+			next_SCTxPortCntl <= `TX_PACKET_STREAM;
+			NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+		end
+		`SP_D0_D1_WAIT_READ_FIFO:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+				next_fifoReadEn <= 1'b1;
+			end
+		`SP_D0_D1_FIFO_EMPTY:
+			if (fifoEmpty == 1'b0)	
+				NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+			else
+				NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+		`SP_D0_D1_FIN:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			NextState_slvSndPkt <= `FIN_SP1;
+		end
+		`SP_D0_D1_TERM_BYTE:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvSndPkt <= `SP_D0_D1_FIN;
+				//Last byte is not valid data,
+				//but the 'TX_PACKET_STOP' flag is required
+				//by the SIE state machine to detect end of data packet
+				next_SCTxPortWEn <= 1'b1;
+				next_SCTxPortData <= 8'h00;
+				next_SCTxPortCntl <= `TX_PACKET_STOP;
+			end
+		`SP_D0_D1_CLR_WEN:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+		end
+		`SP_D0_D1_CLR_REN:
+		begin
+			next_fifoReadEn <= 1'b0;
+			NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvSndPkt_CurrentState
+	if (rst)	
+		CurrState_slvSndPkt <= `START_SP1;
+	else
+		CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvSndPkt_RegOutput
+	if (rst)	
+	begin
+		sendPacketRdy <= 1'b1;
+		SCTxPortReq <= 1'b0;
+		SCTxPortWEn <= 1'b0;
+		SCTxPortData <= 8'h00;
+		SCTxPortCntl <= 8'h00;
+		fifoReadEn <= 1'b0;
+	end
+	else 
+	begin
+		sendPacketRdy <= next_sendPacketRdy;
+		SCTxPortReq <= next_SCTxPortReq;
+		SCTxPortWEn <= next_SCTxPortWEn;
+		SCTxPortData <= next_SCTxPortData;
+		SCTxPortCntl <= next_SCTxPortCntl;
+		fifoReadEn <= next_fifoReadEn;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/usbSlaveControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/usbSlaveControl.v	(revision 264)
@@ -0,0 +1,498 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSlaveControl.v,v 1.1.1.1 2004-10-11 04:01:10 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module usbSlaveControl(
+	clk, rst,
+	//getPacket
+	RxByteStatus, RxData, RxDataValid,
+	SIERxTimeOut, RxFifoData,
+	//speedCtrlMux
+	fullSpeedRate, fullSpeedPol,
+	//SCTxPortArbiter
+	SCTxPortEn, SCTxPortRdy,
+	SCTxPortData, SCTxPortCtrl,
+	//rxStatusMonitor
+	connectStateIn, 
+	resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+	SOFRxedIntOut, 
+  resetEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  NAKSentIntOut,
+  slaveControlSelect,
+  //fifoMux
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+ 	 );
+
+input clk, rst;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [4:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut; 
+output resetEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire clk;
+wire rst;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut; 
+wire resetEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;	  
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed; 
+wire CRCError; 
+wire RXOverflow; 
+wire RXTimeOut; 
+wire bitStuffError; 
+wire dataSequence; 
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [3:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+
+USBSlaveControlBI u_USBSlaveControlBI
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+	.SOFRxedIntOut(SOFRxedIntOut), 
+  .resetEventIntOut(resetEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+	.NAKSentIntOut(NAKSentIntOut),
+  .endP0TransTypeReg(endP0TransTypeReg), 
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg), 
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg), 
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg), 
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .EP0StatusReg(endP0StatusReg),
+  .EP1StatusReg(endP1StatusReg),
+  .EP2StatusReg(endP2StatusReg),
+  .EP3StatusReg(endP3StatusReg),
+  .SCAddrReg(USBTgtAddress), 
+  .frameNum(frameNum),
+  .connectStateIn(connectStateOut),
+	.SOFRxedIn(SOFRxed), 
+  .resetEventIn(resetEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .NAKSentIn(NAKSent),
+  .slaveControlSelect(slaveControlSelect),
+  .clrEP0Ready(clrEP0Rdy), 
+  .clrEP1Ready(clrEP1Rdy), 
+  .clrEP2Ready(clrEP2Rdy), 
+  .clrEP3Ready(clrEP3Rdy),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .SCGlobalEn(SCGlobalEn)
+  );
+
+slavecontroller u_slavecontroller
+  (.CRCError(CRCError), 
+  .NAKSent(NAKSent), 
+  .RxByte(RxData), 
+  .RxDataWEn(RxDataValid), 
+  .RxOverflow(RXOverflow), 
+  .RxStatus(RxByteStatus), 
+  .RxTimeOut(RXTimeOut), 
+  .SCGlobalEn(SCGlobalEn), 
+  .SOFRxed(SOFRxed), 
+  .USBEndPControlReg(endPControlReg), 
+  .USBEndPNakTransTypeReg(transTypeNAK), 
+  .USBEndPTransTypeReg(transType), 
+  .USBEndP(currEndP), 
+  .USBTgtAddress(USBTgtAddress),
+  .bitStuffError(bitStuffError), 
+  .clk(clk), 
+  .clrEPRdy(clrEPRdy), 
+  .endPMuxErrorsWEn(endPMuxErrorsWEn), 
+  .frameNum(frameNum), 
+  .getPacketREn(getPacketREn), 
+  .getPacketRdy(getPacketRdy), 
+  .rst(rst), 
+  .sendPacketPID(slaveControllerPIDOut), 
+  .sendPacketRdy(slaveControllerReadyIn), 
+  .sendPacketWEn(slaveControllerWEnOut), 
+  .stallSent(stallSent), 
+  .transDone(transDone) 
+    );
+
+
+endpMux u_endpMux (
+  .clk(clk), 
+  .rst(rst),
+  .currEndP(currEndP),
+  .NAKSent(NAKSent),
+  .stallSent(stallSent),
+  .CRCError(CRCError),
+  .bitStuffError(bitStuffError),
+  .RxOverflow(RXOverflow),
+  .RxTimeOut(RXTimeOut),
+  .dataSequence(dataSequence),
+  .ACKRxed(ACKRxed),
+  .transType(transType),
+  .transTypeNAK(transTypeNAK),
+  .endPControlReg(endPControlReg),
+  .clrEPRdy(clrEPRdy),
+  .endPMuxErrorsWEn(endPMuxErrorsWEn),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .endP0StatusReg(endP0StatusReg),
+  .endP1StatusReg(endP1StatusReg),
+  .endP2StatusReg(endP2StatusReg),
+  .endP3StatusReg(endP3StatusReg),
+  .endP0TransTypeReg(endP0TransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg),
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .clrEP0Rdy(clrEP0Rdy),
+  .clrEP1Rdy(clrEP1Rdy),
+  .clrEP2Rdy(clrEP2Rdy),
+  .clrEP3Rdy(clrEP3Rdy)
+    );
+
+slaveSendPacket u_slaveSendPacket
+  (.PID(slaveControllerPIDOut), 
+	.SCTxPortCntl(sendPacketCntl),
+	.SCTxPortData(sendPacketData),
+	.SCTxPortGnt(sendPacketGnt),
+	.SCTxPortRdy(SCTxPortArbRdyOut),
+	.SCTxPortReq(sendPacketReq),
+	.SCTxPortWEn(sendPacketWEn),
+	.clk(clk),
+	.fifoData(TxFifoData),
+	.fifoEmpty(TxFifoEmpty),
+	.fifoReadEn(TxFifoRE),
+	.rst(rst),
+	.sendPacketRdy(slaveControllerReadyIn),
+	.sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+	(.SCTxPortCntl(directCntlCntl),
+	.SCTxPortData(directCntlData),
+	.SCTxPortGnt(directCntlGnt),
+	.SCTxPortRdy(SCTxPortArbRdyOut),
+	.SCTxPortReq(directCntlReq),
+	.SCTxPortWEn(directCntlWEn),
+	.clk(clk),
+	.directControlEn(directLineCtrlEn),
+	.directControlLineState(directLineState),
+	.rst(rst) ); 
+
+SCTxPortArbiter u_SCTxPortArbiter
+	(.SCTxPortCntl(SCTxPortCtrl),
+	.SCTxPortData(SCTxPortData),
+	.SCTxPortRdyIn(SCTxPortRdy),
+	.SCTxPortRdyOut(SCTxPortArbRdyOut),
+	.SCTxPortWEnable(SCTxPortEn),
+	.clk(clk),
+	.directCntlCntl(directCntlCntl),
+	.directCntlData(directCntlData),
+	.directCntlGnt(directCntlGnt),
+	.directCntlReq(directCntlReq),
+	.directCntlWEn(directCntlWEn),
+	.rst(rst),
+	.sendPacketCntl(sendPacketCntl),
+	.sendPacketData(sendPacketData),
+	.sendPacketGnt(sendPacketGnt),
+	.sendPacketReq(sendPacketReq),
+	.sendPacketWEn(sendPacketWEn) );	  
+
+
+slaveGetPacket u_slaveGetPacket
+  (.ACKRxed(ACKRxed), 
+  .CRCError(CRCError), 
+	.RXDataIn(RxData),
+	.RXDataValid(RxDataValid),
+	.RXFifoData(RxFifoData),
+	.RXFifoFull(RxFifoFull),
+	.RXFifoWEn(RxFifoWE),
+	.RXPacketRdy(getPacketRdy),
+	.RXStreamStatusIn(RxByteStatus),
+	.RxPID(RxPID),
+	.SIERxTimeOut(SIERxTimeOut),
+	.clk(clk),
+  .RXOverflow(RXOverflow), 
+  .RXTimeOut(RXTimeOut), 
+  .bitStuffError(bitStuffError), 
+  .dataSequence(dataSequence), 
+	.getPacketEn(getPacketREn),
+	.rst(rst) ); 
+
+slaveRxStatusMonitor	u_slaveRxStatusMonitor
+	(.connectStateIn(connectStateIn),
+	.connectStateOut(connectStateOut),
+	.resumeDetectedIn(resumeDetectedIn),
+	.resetEventOut(resetEventFromRxStatusMon),
+	.resumeIntOut(resumeIntFromRxStatusMon),
+	.clk(clk),
+	.rst(rst)  );    
+  
+fifoMux u_fifoMux (
+  .currEndP(currEndP),
+  //TxFifo
+  .TxFifoREn(TxFifoRE),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoData(TxFifoData),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEmpty(TxFifoEmpty),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  //RxFifo
+  .RxFifoWEn(RxFifoWE),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoFull(RxFifoFull),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+    );
+
+endmodule
+
+	
+	
+
+
+
+

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+body   { color: #000000; background-color: #FFFFFF }
+pre    { font-family: Courier New, monospace; font-size: 10pt; }
+#t_com { color: #008000; font-style: italic; }
+#t_kwd { color: #0000FF; }
+#t_cns { color: #848484; }
+#t_idt { }
+#t_msb { }
+#t_dir { color: #6B6D9C; }
+#t_sdt { font-weight: bold; }
+#t_sdv { }
+#t_sdf { }
+#t_sys { color: #6B6D9C; }
+

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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/USBSlaveControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/USBSlaveControlBI.v	(revision 264)
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+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBSlaveControlBI.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: USBSlaveControlBI.v,v 1.1.1.1 2004-10-11 04:01:10 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbSlaveControl_h.v"
+ 
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+	SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+  endP0TransTypeReg, endP0NAKTransTypeReg,
+  endP1TransTypeReg, endP1NAKTransTypeReg,
+  endP2TransTypeReg, endP2NAKTransTypeReg,
+  endP3TransTypeReg, endP3NAKTransTypeReg,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  EP0StatusReg,
+  EP1StatusReg,
+  EP2StatusReg,
+  EP3StatusReg,
+  SCAddrReg, frameNum,
+	connectStateIn,
+	SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+  slaveControlSelect,
+  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  SCGlobalEn
+  );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg; 
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg; 
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg; 
+input [1:0] endP3NAKTransTypeReg;
+output [3:0] endP0ControlReg;
+output [3:0] endP1ControlReg;
+output [3:0] endP2ControlReg;
+output [3:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg; 
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg; 
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg; 
+wire [1:0] endP3NAKTransTypeReg;
+reg [3:0] endP0ControlReg;
+reg [3:0] endP1ControlReg;
+reg [3:0] endP2ControlReg;
+reg [3:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+
+//sync write demux
+always @(posedge clk)
+begin
+	clrNAKReq <= 1'b0;
+  clrSOFReq <= 1'b0;
+  clrResetReq <= 1'b0;
+  clrResInReq <= 1'b0;
+  clrTransDoneReq <= 1'b0;
+  EP0SetReady <= 1'b0;
+  EP1SetReady <= 1'b0;
+  EP2SetReady <= 1'b0;
+  EP3SetReady <= 1'b0;
+	if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+	begin
+		case (address)
+      `EP0_CTRL_REG : begin
+        EP0SendStall <= dataIn[3];
+        EP0DataSequence <= dataIn[2];
+        EP0SetReady <= dataIn[1];
+        EP0Enable <= dataIn[0];
+      end
+      `EP1_CTRL_REG : begin
+        EP1SendStall <= dataIn[3];
+        EP1DataSequence <= dataIn[2];
+        EP1SetReady <= dataIn[1];
+        EP1Enable <= dataIn[0];
+      end
+      `EP2_CTRL_REG : begin
+        EP2SendStall <= dataIn[3];
+        EP2DataSequence <= dataIn[2];
+        EP2SetReady <= dataIn[1];
+        EP2Enable <= dataIn[0];
+      end
+      `EP3_CTRL_REG : begin
+        EP3SendStall <= dataIn[3];
+        EP3DataSequence <= dataIn[2];
+        EP3SetReady <= dataIn[1];
+        EP3Enable <= dataIn[0];
+      end
+			`SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+			`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+			`SC_INTERRUPT_STATUS_REG : begin
+        clrNAKReq <= dataIn[4];
+        clrSOFReq <= dataIn[3];
+        clrResetReq <= dataIn[2];
+        clrResInReq <= dataIn[1];
+        clrTransDoneReq <= dataIn[0];
+      end
+			`SC_INTERRUPT_MASK_REG	: interruptMaskReg <= dataIn[4:0];
+		endcase
+	end
+end
+
+//interrupt control 
+always @(posedge clk)
+begin
+	if (NAKSentIn == 1'b1)
+		NAKSentInt <= 1'b1;
+	else if (clrNAKReq == 1'b1)
+		NAKSentInt <= 1'b0; 
+    
+	if (SOFRxedIn == 1'b1)
+		SOFRxedInt <= 1'b1;
+	else if (clrSOFReq == 1'b1)
+		SOFRxedInt <= 1'b0;
+		
+	if (resetEventIn == 1'b1)
+		resetEventInt <= 1'b1;
+	else if (clrResetReq == 1'b1)
+		resetEventInt <= 1'b0;
+		
+	if (resumeIntIn == 1'b1)
+		resumeInt <= 1'b1;
+	else if (clrResInReq == 1'b1)
+		resumeInt <= 1'b0;	
+
+	if (transDoneIn == 1'b1)
+		transDoneInt <= 1'b1;
+	else if (clrTransDoneReq == 1'b1)
+		transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end  
+
+//end point ready, set/clear
+always @(posedge clk)
+begin
+	if (EP0SetReady == 1'b1)
+		EP0Ready <= 1'b1;
+	else if (clrEP0Ready == 1'b1)
+		EP0Ready <= 1'b0;
+    
+	if (EP1SetReady == 1'b1)
+		EP1Ready <= 1'b1;
+	else if (clrEP1Ready == 1'b1)
+		EP1Ready <= 1'b0;
+    
+	if (EP2SetReady == 1'b1)
+		EP2Ready <= 1'b1;
+	else if (clrEP2Ready == 1'b1)
+		EP2Ready <= 1'b0;
+    
+	if (EP3SetReady == 1'b1)
+		EP3Ready <= 1'b1;
+	else if (clrEP3Ready == 1'b1)
+		EP3Ready <= 1'b0;
+end  
+  
+//break out control signals
+always @(SCControlReg) begin
+  SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+  TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+  fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals 
+always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable) 
+begin
+  endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+  endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+  endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+  endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+      
+      
+      // async read mux
+always @(address or
+  EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+  EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
+  endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
+  endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or 
+  endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
+  SCControlReg or connectStateIn or
+  NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or SCAddrReg or frameNum)
+begin
+	case (address)
+      `EP0_CTRL_REG : dataOut <= endP0ControlReg;
+      `EP0_STS_REG : dataOut <= EP0StatusReg;
+      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
+      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
+      `EP1_CTRL_REG : dataOut <= endP1ControlReg;
+      `EP1_STS_REG :  dataOut <= EP1StatusReg;
+      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
+      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
+      `EP2_CTRL_REG : dataOut <= endP2ControlReg;
+      `EP2_STS_REG :  dataOut <= EP2StatusReg;
+      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
+      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
+      `EP3_CTRL_REG : dataOut <= endP3ControlReg;
+      `EP3_STS_REG :  dataOut <= EP3StatusReg;
+      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
+      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
+  		`SC_CONTROL_REG : dataOut <= SCControlReg;
+			`SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn}; 
+			`SC_INTERRUPT_STATUS_REG :	dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+			`SC_INTERRUPT_MASK_REG	: dataOut <= {3'b000, interruptMaskReg};
+			`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+			`SC_FRAME_NUM_MSP : dataOut <= frameNum[10:3];
+			`SC_FRAME_NUM_LSP : dataOut <= {5'b00000, frameNum[2:0]};
+      default: dataOut <= 8'h00;
+	endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/sctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/sctxportarbiter.asf	(revision 264)
@@ -0,0 +1,110 @@
+VERSION=1.19
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FREEOID=101
+"LIBRARIES=`timescale 1ns / 1ps\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/20/2004"
+HEADER_PARAM="TITLE,SCTxPortArbiter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 431800,558800
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SARB_SEND_PACKET\n/1/"
+S 14 6 4096 ELLIPSE "States" | 269063,296392 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 10 6 0 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_SARB\n/3/"
+S 8 6 12288 ELLIPSE "States" | 225591,395370 6500 6500
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "SCTxArb"
+F 6 0 671089152 41 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,543100 1 0 0 "Module: SCTxPortArbiter"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+                                      288786,359372 287077,371461 282417,376909 277757,382357\
+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+C 26 17 0 TEXT "Conditions" | 202073,391408 1 0 0 "rst"
+A 25 8 2 TEXT "Actions" | 234434,411387 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+W 19 6 4097 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210185,391478 219470,393186
+I 16 6 0 Builtin Reset | 178237,395710
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 43 42 0 TEXT "Labels" | 172566,462781 1 0 0 "SCTxPortRdyIn"
+I 42 0 2 Builtin InPort | 166566,462781 "" ""
+I 41 0 3 Builtin InPort | 190061,536582 "" ""
+L 40 39 0 TEXT "Labels" | 195447,542126 1 0 0 "rst"
+I 39 0 2 Builtin InPort | 189447,542126 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "SCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 61 41 0 TEXT "Labels" | 196061,536582 1 0 0 "clk"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "SCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n  SCTxPortRdyOut = SCTxPortRdyIn;\nend\n	  \nalways @(muxDCEn or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n  begin  \n    SCTxPortWEnable <= directCntlWEn;\n    SCTxPortData <= directCntlData;\n    SCTxPortCntl <= directCntlCntl;\n  end\nelse\n  begin  \n    SCTxPortWEnable <= sendPacketWEn;\n    SCTxPortData <= sendPacketData;\n    SCTxPortCntl <= sendPacketCntl;\n  end\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "SCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+L 65 64 0 TEXT "Labels" | 170048,467134 1 0 0 "SCTxPortRdyOut"
+I 64 0 2 Builtin OutPort | 164048,467134 "" ""
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+W 92 6 4098 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+S 91 6 8192 ELLIPSE "States" | 230314,289948 6500 6500
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "SARB_DC\n/2/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxDCEn"
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286142,395412 275462,395110\
+                                      264783,394808 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveDirectcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveDirectcontrol.v	(revision 264)
@@ -0,0 +1,167 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveDirectcontrol.v
+// Generated   : 06/05/04 05:59:19
+// From        : c:\projects\USBHostSlave\RTL\slaveController\slaveDirectcontrol.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   clk;
+input   directControlEn;
+input   [1:0] directControlLineState;
+input   rst;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+wire    clk;
+wire    directControlEn;
+wire    [1:0] directControlLineState;
+wire    rst;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0] CurrState_slvDrctCntl;
+reg [2:0] NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+//--------------------------------------------------------------------
+// Machine: slvDrctCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)
+begin : slvDrctCntl_NextState
+	NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+	// Set default values for outputs and signals
+	next_SCTxPortReq <= SCTxPortReq;
+	next_SCTxPortWEn <= SCTxPortWEn;
+	next_SCTxPortData <= SCTxPortData;
+	next_SCTxPortCntl <= SCTxPortCntl;
+	case (CurrState_slvDrctCntl) // synopsys parallel_case full_case
+		`START_SDC:
+			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+		`CHK_DRCT_CNTL:
+			if (directControlEn == 1'b1)	
+			begin
+				NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+				next_SCTxPortReq <= 1'b1;
+			end
+			else
+			begin
+				NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+				next_SCTxPortReq <= 1'b1;
+			end
+		`DRCT_CNTL_WAIT_GNT:
+			if (SCTxPortGnt == 1'b1)	
+				NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+		`DRCT_CNTL_CHK_LOOP:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			if (directControlEn == 1'b0)	
+			begin
+				NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+				next_SCTxPortReq <= 1'b0;
+			end
+			else
+				NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+		end
+		`DRCT_CNTL_WAIT_RDY:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+				next_SCTxPortWEn <= 1'b1;
+				next_SCTxPortData <= {6'b000000, directControlLineState};
+				next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+			end
+		`IDLE_FIN:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			next_SCTxPortReq <= 1'b0;
+			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+		end
+		`IDLE_WAIT_GNT:
+			if (SCTxPortGnt == 1'b1)	
+				NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+		`IDLE_WAIT_RDY:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvDrctCntl <= `IDLE_FIN;
+				next_SCTxPortWEn <= 1'b1;
+				next_SCTxPortData <= 8'h00;
+				next_SCTxPortCntl <= `TX_IDLE;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_CurrentState
+	if (rst)	
+		CurrState_slvDrctCntl <= `START_SDC;
+	else
+		CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_RegOutput
+	if (rst)	
+	begin
+		SCTxPortCntl <= 8'h00;
+		SCTxPortData <= 8'h00;
+		SCTxPortWEn <= 1'b0;
+		SCTxPortReq <= 1'b0;
+	end
+	else 
+	begin
+		SCTxPortCntl <= next_SCTxPortCntl;
+		SCTxPortData <= next_SCTxPortData;
+		SCTxPortWEn <= next_SCTxPortWEn;
+		SCTxPortReq <= next_SCTxPortReq;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveRxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveRxStatusMonitor.v	(revision 264)
@@ -0,0 +1,100 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveRxStatusMonitor.v                                       ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveRxStatusMonitor.v,v 1.1.1.1 2004-10-11 04:01:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+	connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+	if (rst == 1'b1)
+	begin
+		oldConnectState <= connectStateIn;
+		oldResumeDetected <= resumeDetectedIn;
+	end
+	else
+	begin
+		oldConnectState <= connectStateIn;
+		oldResumeDetected <= resumeDetectedIn;
+		if (oldConnectState != connectStateIn)
+			resetEventOut <= 1'b1;
+		else
+			resetEventOut <= 1'b0;
+		if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+			resumeIntOut <= 1'b1;
+		else 
+			resumeIntOut <= 1'b0;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slavecontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slavecontroller.asf	(revision 264)
@@ -0,0 +1,347 @@
+VERSION=1.19
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FREEOID=789
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,slaveController"
+END
+BUNDLES
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+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
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+END
+INSTHEADER 1
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+END
+OBJECTS
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+                                       96612,168665 117496,167729
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+                                           69710,37919
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+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
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+I 399 377 0 Builtin Link | 54419,17564
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+                                              60053,165183 57484,160822 55722,148570 53960,136319\
+                                              36935,95064 38880,77714 40826,60365 38327,20823\
+                                              54419,15564
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+                                              46511,172964 33727,90292 34975,71611 36223,52930\
+                                              35724,34993 37785,28932 39847,22872 46307,16188\
+                                              54419,15564
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+I 701 699 0 Builtin Exit | 144780,101600
+I 700 699 0 Builtin Entry | 96520,152400
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 698 559 81940 ELLIPSE "Junction" | 117000,209824 3500 3500
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+W 696 559 8194 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+                                              200304,203038 205920,186346 207441,167119 208962,147892\
+                                              209430,87676 208962,71608 208494,55540 206154,51484\
+                                              204438,50041 202722,48598 199528,45916 197266,45058
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+                                              39220,148925 36609,140943 36571,133460 36533,125977\
+                                              38989,104026 47738,97617 56488,91209 87662,87731\
+                                              103933,85889
+C 693 692 0 TEXT "Conditions" | 108065,184348 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 &&\nRxOverflow == 1'b0 &&\nRxTimeOut == 1'b0"
+W 692 559 8193 698 654 BEZIER "Transitions" | 115978,206479 112866,179807 96893,185826 93781,159154
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+S 690 559 77824 ELLIPSE "States" | 98991,238090 6500 6500
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/15/"
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+                                              69948,104476 47394,95074 43302,84878 39210,74682\
+                                              42917,24960 54419,15564
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+I 423 421 0 Builtin Exit | 144780,101600
+I 422 421 0 Builtin Entry | 96520,152400
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+                                           108160,233400 112640,227800 113920,224400 115200,221000\
+                                           116013,213096 116333,209096
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+I 727 722 0 Builtin Exit | 144780,101600
+I 726 722 0 Builtin Entry | 96520,152400
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;"
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/16/"
+S 723 722 90112 ELLIPSE "States" | 120650,127000 6500 6500
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/18/"
+S 462 377 102400 ELLIPSE "States" | 94684,51331 6500 6500
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 749 0 2 Builtin InPort | 122043,237048 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[3:0]"
+I 747 0 2 Builtin InPort | 29748,247328 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 743 0 2 Builtin OutPort | 119778,227003 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+C 468 457 0 TEXT "Conditions" | 76387,38022 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS  &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+A 763 41 68 TEXT "Actions" | 141963,174883 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 757 0 2 Builtin OutPort | 119853,246737 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 755 0 2 Builtin OutPort | 119826,241925 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+I 765 0 2 Builtin Signal | 120578,208940 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+                                              46860,73975 46530,57145 47396,48771 48262,40398\
+                                              52522,23896 54419,15564
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+I 769 0 2 Builtin InPort | 77236,247440 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 771 0 2 Builtin InPort | 76928,242820 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 773 0 2 Builtin Signal | 120664,213560 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 775 0 2 Builtin Signal | 120664,217872 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 777 0 2 Builtin Signal | 120664,221876 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 779 0 2 Builtin OutPort | 28880,219720 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 783 0 2 Builtin Signal | 83088,208940 "" ""
+K 788 786 0 TEXT "Comments" | 118800,50912 1 0 0 "Insert delay to allow USBEndPControlReg to update"
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+S 786 377 98304 ELLIPSE "States" | 123152,53144 6500 6500
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/17/"
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+                                            105236,81091 81842,75191 69908,73378
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+                                            60717,97705 62441,84600 62616,78575
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+                                              53866,34676 56339,23332 57169,17564
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+                                           209214,43082 209522,23062 208983,17094 208444,11127\
+                                           205980,7277 191773,6353 177567,5429 123205,5583\
+                                           106804,9317 90403,13052 79161,27836 75696,31763\
+                                           72231,35690 70888,36159 69579,36621
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+C 535 532 0 TEXT "Conditions" | 73577,60437 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1"
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/RTL/wrapper/usbHostSlave.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/RTL/wrapper/usbHostSlave.v	(revision 264)
@@ -0,0 +1,515 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlave.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostSlave.v,v 1.1.1.1 2004-10-11 04:01:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module usbHostSlave(
+	clk, 
+  rst,
+  address_i, 
+  data_i, 
+  data_o, 
+  writeEn, 
+  strobe_i,
+  ack_o,
+  hostSOFSentIntOut, 
+  hostConnEventIntOut, 
+  hostResumeIntOut, 
+  hostTransDoneIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+	USBWireDataIn,
+	USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+	USBWireCtrlOut
+	 );
+	parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+  parameter HOST_FIFO_ADDR_WIDTH = 6;   
+	parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+	parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+	parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+	parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk;
+input rst;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input writeEn; 
+input strobe_i;
+output ack_o;
+output hostSOFSentIntOut; 
+output hostConnEventIntOut; 
+output hostResumeIntOut; 
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+
+wire clk;
+wire rst;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire writeEn; 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel; 
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE; 
+wire [7:0] hostTxFifoData; 
+wire hostTxFifoEmpty;
+wire hostRxFifoWE; 
+wire [7:0] hostRxFifoData; 
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost; 
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+
+usbHostControl u_usbHostControl(
+  .clk(clk), 
+  .rst(rst),
+	.TxFifoRE(hostTxFifoRE), 
+  .TxFifoData(hostTxFifoData), 
+  .TxFifoEmpty(hostTxFifoEmpty),
+	.RxFifoWE(hostRxFifoWE), 
+  .RxFifoData(hostRxFifoData), 
+  .RxFifoFull(hostRxFifoFull),
+	.RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+	.SIERxTimeOut(noActivityTimeOut),
+	.fullSpeedRate(fullSpeedBitRateFromHost), 
+  .fullSpeedPol(fullSpeedPolarityFromHost),
+	.HCTxPortEn(SIEPortWEnFromHost), 
+  .HCTxPortRdy(SIEPortTxRdy),
+	.HCTxPortData(SIEPortDataInFromHost), 
+  .HCTxPortCtrl(SIEPortCtrlInFromHost),
+	.connectStateIn(connectState), 
+	.resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[3:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+	.SOFSentIntOut(hostSOFSentIntOut), 
+  .connEventIntOut(hostConnEventIntOut), 
+  .resumeIntOut(hostResumeIntOut), 
+  .transDoneIntOut(hostTransDoneIntOut),
+  .hostControlSelect(hostControlSel) );
+  
+
+usbSlaveControl u_usbSlaveControl(
+  .clk(clk), 
+  .rst(rst),
+	.RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+	.SIERxTimeOut(noActivityTimeOut), 
+  .RxFifoData(slaveRxFifoData),
+	.fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+	.SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+	.SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+	.connectStateIn(connectState), 
+	.resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+	.SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk), 
+  .rst(rst),
+	.hostControlSel(hostControlSel), 
+  .hostRxFifoSel(hostRxFifoSel), 
+  .hostTxFifoSel(hostTxFifoSel),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(dataFromHostControl),
+  .dataFromHostRxFifo(dataFromHostRxFifo),
+  .dataFromHostTxFifo(dataFromHostTxFifo),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+	 );
+
+hostSlaveMux u_hostSlaveMux(
+	.SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+	.SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+	.SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+	.SIEPortDataInToSIE(SIEPortDataInToSIE), 
+	.SIEPortDataInFromHost(SIEPortDataInFromHost), 
+	.SIEPortDataInFromSlave(SIEPortDataInFromSlave), 
+	.SIEPortWEnToSIE(SIEPortWEnToSIE), 
+	.SIEPortWEnFromHost(SIEPortWEnFromHost), 
+	.SIEPortWEnFromSlave(SIEPortWEnFromSlave), 
+	.fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+	.fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+	.fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+	.fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+	.fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+	.fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux), 
+  .writeEn(writeEn),
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(clk), 
+  .rst(rst),
+	.USBWireDataIn(USBWireDataIn),
+	.USBWireDataOut(USBWireDataOut),
+	.USBWireDataInTick(USBWireDataInTick),
+	.USBWireDataOutTick(USBWireDataOutTick),
+	.USBWireCtrlOut(USBWireCtrlOut),
+	.connectState(connectState),
+	.resumeDetected(resumeDetected),
+	.RxCtrlOut(RxCtrlOut), 
+	.RxDataOutWEn(RxDataOutWEn), 
+	.RxDataOut(RxDataFromSIE), 
+	.SIEPortCtrlIn(SIEPortCtrlInToSIE),
+	.SIEPortDataIn(SIEPortDataInToSIE), 
+	.SIEPortTxRdy(SIEPortTxRdy), 
+	.SIEPortWEn(SIEPortWEnToSIE), 
+	.fullSpeedPolarity(fullSpeedPolarityToSIE),
+	.fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(hostTxFifoRE), 
+  .fifoEmpty(hostTxFifoEmpty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostTxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostTxFifo),
+  .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(hostRxFifoWE), 
+  .fifoFull(hostRxFifoFull),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostRxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostRxFifo),
+  .fifoDataIn(hostRxFifoData)  );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+  TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+  TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+endmodule
+
+	
+	
+
+
+
+

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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/css/lst.css	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/css/lst.css	(revision 264)
@@ -0,0 +1,14 @@
+body   { background-color: silver; margin: 0 }
+#title { color: #000000; background-color: silver;
+         font-family: Arial; font-size: 10pt;
+         text-align: center; }
+#divider { background-color: #808080; }
+#value { color: #000000; background-color: #FFFFFF;
+         font-family: Arial; font-size: 10pt;
+         text-align: center }
+#time  { color: #000000; background-color: #FFFFDE;
+         font-family: Arial; font-size: 10pt;
+         text-align: right }
+#delta { color: #000000; background-color: #FFFFDE;
+         font-family: Arial; font-size: 10pt;
+         text-align: right }

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Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoomoutover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/ahw.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/ahw.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/gotoover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/gotoover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/newwindowover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/newwindowover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/panmodeover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/panmodeover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/popover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/popover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/prevover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/prevover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/printover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/printover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/selectmodeover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/selectmodeover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/tblover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/tblover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoomindown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoomindown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoommodedown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoommodedown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoomoutdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoomoutdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/acpselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/acpselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/aldec.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/aldec.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/blank.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/blank.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/codeover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/codeover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/fitover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/fitover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/fulldown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/fulldown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/gotodown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/gotodown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/newwindowdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/newwindowdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/panmodedown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/panmodedown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/popdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/popdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/prevdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/prevdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/printdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/printdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/selectmodedown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/selectmodedown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/tbldown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/tbldown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoomin.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoomin.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoommode.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoommode.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoomout.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/bde/zoomout.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/acp.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/acp.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/asfselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/asfselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/bas.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/bas.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/bdeselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/bdeselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/cpp.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/cpp.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/dlmselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/dlmselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/drw.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/drw.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/ednselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/ednselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/asf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/asf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/awfselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/awfselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/bde.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/bde.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/confselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/confselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/dlm.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/dlm.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/doselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/doselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/edn.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/edn.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/htm.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/htm.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/lstselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/lstselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/sdf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/sdf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/symbselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/symbselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/txt.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/txt.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/undef.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/undef.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/v.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/v.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/hpselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/hpselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/lst.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/lst.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/plselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/plselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/symb.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/symb.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/tclselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/tclselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/und.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/und.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/undselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/undselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/ahwselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/ahwselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/awf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/awf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/basselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/basselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/conf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/conf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/cppselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/cppselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/do.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/do.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/drwselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/drwselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/hp.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/hp.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/htmselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/htmselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/pl.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/pl.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/sdfselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/sdfselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/tcl.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/tcl.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/txtselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/txtselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/undefselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/undefselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vhd.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vhd.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vls.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vls.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vtb.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vtb.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/xnfselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/xnfselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/codedown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/codedown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fitdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fitdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vhdselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vhdselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/xnf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/xnf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/code.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/code.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fit.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fit.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/full.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/full.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/newwindow.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/newwindow.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/prev.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/prev.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/print.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/print.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomin.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomin.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomout.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomout.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ico/ahdl.ico
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ico/ahdl.ico
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/left_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/left_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/n_nr.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/n_nr.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/right_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/right_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vlsselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vlsselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vtbselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/ext/vtbselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/bar.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/bar.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/codeover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/codeover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fitover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fitover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fulldown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fulldown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/newwindowdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/newwindowdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/prevdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/prevdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/printdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/printdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomindown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomindown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomoutdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomoutdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/back.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/back.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/left_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/left_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/n_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/n_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/tab_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/tab_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/logoback.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/logoback.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/sig.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/sig.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/frame.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/frame.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fullover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/fullover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/newwindowover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/newwindowover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/prevover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/prevover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/printover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/printover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoominover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoominover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomoutover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/fsm/zoomoutover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/empty.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/empty.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/n_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/n_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/right_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/right_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/tab_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/tab_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/logoback.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/logoback.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/out.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/out.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/doc.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/doc.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/msie_doc_sel.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/msie_doc_sel.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/ns_doc_sel.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/ns_doc_sel.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/folderopen.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/folderopen.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/jointop.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/jointop.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/minusbottom.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/minusbottom.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/plus.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/plus.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/plustop.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/plustop.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/s_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/itab/s_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/logo.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/logo.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/in.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/in.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/sig.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/sig.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/msie_doc.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/msie_doc.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/ns_doc.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/ns_doc.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/blank.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/blank.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/join.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/join.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/line.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/line.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/minusonly.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/minusonly.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/expandall.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/expandall.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/home_f2.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/home_f2.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/set/exp.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/set/exp.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/empty.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/empty.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/n_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/n_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/var.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/lst/var.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/msie_doc_mo.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/msie_doc_mo.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/ns_doc_mo.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/ns_doc_mo.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/folderclosed.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/folderclosed.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/joinbottom.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/joinbottom.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/minus.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/minus.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/minustop.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/minustop.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/plusonly.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/plusonly.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/collapseall_f2.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/collapseall_f2.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/home.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/home.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/set/coll.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/set/coll.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/back.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/back.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/left_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/left_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/plusbottom.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menu/win/plusbottom.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/collapseall.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/collapseall.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/expandall_f2.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/menucntrl/expandall_f2.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/right_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/right_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/tab_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/tab_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/folder_o.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/folder_o.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/join_l.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/join_l.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/minus.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/minus.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/minus_t.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/minus_t.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/plus_o.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/plus_o.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/right_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/right_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/tab_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tab/tab_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/folder_c.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/folder_c.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/join_b.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/join_b.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/line.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/line.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/minus_o.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/minus_o.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/plus_b.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/plus_b.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/back.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/back.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/downdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/downdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/firstdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/firstdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/lastdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/lastdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/nextdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/nextdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/prevdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/prevdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/updown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/updown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/info/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/info/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/info/index.htm	(revision 264)
@@ -0,0 +1,59 @@
+<html>
+<head>
+<title>Active-HDL: "usbhostslave" </title>
+<style type="text/css">
+td,caption {font-size:17px; font-family: courier;}
+</style>
+</head>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" 
+marginwidth="0" bgcolor="silver">
+
+<table cellpadding=5 width=100%>
+<caption ><b>PROJECT INFORMATION:</b><hr></caption>
+<tr>
+  <td width=200px><b>#WORKSPACE NAME:</b></td>
+  <td>usbhostslave</td>
+</tr>
+<tr>
+  <td><b>#DESIGN NAME:</b></td>
+  <td>usbhostslave</td>
+</tr>
+<tr>
+  <td><b>#SYNTHESIS TOOL:</b></td>
+  <td><none></td>
+</tr>
+<tr>
+  <td><b>#IMPLEMENTATION TOOL:</b></td>
+  <td><none></td>
+</tr>
+<tr>
+  <td><b>#AUTHOR:</b></td>
+  <td>Steve</td>
+</tr>
+<tr>
+  <td><b>#COMPANY:</b></td>
+  <td>Base2Designs</td>
+</tr>
+<tr>
+  <td><b>#E-MAIL:</b></td>
+  <td><A href="mailto:sfielding@base2designs.com">sfielding@base2designs.com</A></td>
+</tr>
+<tr>
+  <td  valign=top><b>#HTML GENERATOR:</b></td>
+  <td>HDE converter 1.0<br>LST converter 1.0<br>BDE converter 1.0<br>FSM converter 1.0<br>WVF converter 1.0</td>
+</tr>
+<tr>
+  <td  valign=top><b>#DESCRIPTION:</b></td>
+  <td></td>
+</tr>
+<tr>
+  <td  valign=top><b>#COMMENT:</b></td>
+  <td></td>
+</tr>
+</table>
+
+<hr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/info/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/project.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/tree/project.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/down.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/down.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/first.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/first.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/last.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/last.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/next.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/next.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/prev.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/prev.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/up.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/up.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/index.htm	(revision 264)
@@ -0,0 +1,1186 @@
+<HTML>
+<HEAD>
+<TITLE>usbhostslave</TITLE>
+<meta name="Author" content="Steve">
+<meta name="Generator" content="ActiveHDL 6.2">
+
+<!--
+Joust Outliner Version 2.5.4
+(c) Copyright 1996-2001, MITEM (Europe) Ltd. All rights reserved.
+This code may be freely copied and distributed provided that it is accompanied by this 
+header.  For full details of the Joust license, as well as documentation and help, go 
+to http://www.ivanpeters.com/.
+
+Do not modify anything between here and the "End of Joust" marker unless you know what you
+are doing.  
+-->
+<script language="JavaScript">
+<!--
+function getDHTMLObj(docName, objName) {
+	if 	(theBrowser.hasW3CDOM) {
+		return eval(docName + '.getElementById("' + objName + '").style');
+	} else {
+		return eval(docName + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLStyleObj);
+	}
+}
+function getDHTMLObjTop(theObj) {return (theBrowser.code == "MSIE") ? theObj.pixelTop : theObj.top;}
+function getDHTMLObjHeight(docName, objName) {
+	if 	(theBrowser.hasW3CDOM) {
+		return parseInt(eval(docName + '.getElementById("' + objName + '").offsetHeight'),10);
+	} else {
+		return eval(docName + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLDivHeight);
+	}
+}
+function getDHTMLImg(docName, objName, imgName) {
+	if 	(document.layers) {
+		return getDHTMLObj(docName, objName).document.images[imgName];
+	} else {
+		return eval(docName + '.images.' + imgName);
+	}
+}
+function simpleArray() {this.item = 0;}
+function imgStoreItem(n, s, w, h) {
+	this.name = n;
+	this.src = s;
+	this.obj = null;
+	this.w = w;
+	this.h = h;
+	if ((theBrowser.canCache) && (s)) {
+		this.obj = new Image(w, h);
+		this.obj.src = s;
+	}
+}
+function imgStoreObject() {
+	this.count = -1;
+	this.img = new imgStoreItem;
+	this.find = imgStoreFind;
+	this.add = imgStoreAdd;
+	this.getSrc = imgStoreGetSrc;
+	this.getTag = imgStoreGetTag;
+}
+function imgStoreFind(theName) {
+	var foundItem = -1;
+	for (var i = 0; i <= this.count; i++) {if (this.img[i].name == theName) {foundItem = i;break;}}
+	return foundItem;
+}
+function imgStoreAdd(n, s, w, h) {
+	var i = this.find(n);
+	if (i == -1) {i = ++this.count;}
+	this.img[i] = new imgStoreItem(n, s, parseInt(w, 10), parseInt(h, 10));
+}
+function imgStoreGetSrc(theName) {
+	var i = this.find(theName);
+	var img = this.img[i];
+	return (i == -1) ? '' : ((img.obj) ? img.obj.src : img.src);
+}
+function imgStoreGetTag(theName, iconID, altText) {
+	var i = this.find(theName);
+	if (i < 0) {return ''}
+	with (this.img[i]) {
+		if (src == '') {return ''}
+		var tag = '<img src="' + src + '" width="' + w + '" height="' + h + '" border="0" align="left" hspace="0" vspace="0"';
+		tag += (iconID != '') ? ' name="' + iconID + '"' : '';
+		tag += ' alt="' + ((altText)?altText:'') + '">';
+	}
+	return tag;
+}
+// The MenuItem object.  This contains the data and functions for drawing each item.
+function MenuItem (owner, id, type, text, url, status, nItem, pItem, parent) {
+	var t = this;
+	this.owner = owner;
+	this.id = id;
+	this.type = type;
+	this.text = text;
+	this.url = url;
+	this.status = status;
+	this.target = owner.defaultTarget;
+	this.nextItem = nItem;
+	this.prevItem = pItem;
+	this.FirstChild = -1;
+	this.parent = parent;
+	this.isopen = false;
+	this.isSelected = false;
+	this.draw = MIDraw;
+	this.PMIconName = MIGetPMIconName;
+	this.docIconName = MIGetDocIconName;
+	this.setImg = MISetImage;
+	this.setIsOpen = MISetIsOpen;
+	this.setSelected = MISetSelected;
+	this.setIcon = MISetIcon;
+	this.mouseOver = MIMouseOver;
+	this.mouseOut = MIMouseOut;
+	var i = (this.owner.imgStore) ? this.owner.imgStore.find(type) : -2;
+	if (i == -1) {i = this.owner.imgStore.find('iconPlus');}
+	this.height = (i > -1) ? this.owner.imgStore.img[i].h : 0;
+}
+function MIDraw (indentStr) {
+	var o = this.owner;
+	var mRef = '="return ' + o.reverseRef + "." + o.name;
+	var tmp = mRef + '.entry[' + this.id + '].';
+	var MOver = ' onMouseOver' + tmp + 'mouseOver(\''
+	var MOut = ' onMouseOut' + tmp + 'mouseOut(\''
+	var iconTag = o.imgStore.getTag(this.PMIconName(), 'plusMinusIcon' + this.id, '');
+	var aLine = '<nobr>' + indentStr;
+	if (!this.noOutlineImg) {
+		if (this.FirstChild != -1) {
+			aLine += '<A HREF="#" onClick' + mRef + '.toggle(' + this.id + ');"' + MOver + 'plusMinusIcon\',this);"' + MOut + 'plusMinusIcon\');">' + iconTag + '</A>';				
+		} else {
+			aLine += iconTag;
+		}
+	}
+	var tip = (o.tipText == 'text') ? this.text : ((o.tipText == 'status') ? this.status : '');
+	var theEntry = o.imgStore.getTag(this.docIconName(), 'docIcon' + this.id, tip) + this.text;
+	var theImg = o.imgStore.getTag(this.docIconName(), 'docIcon' + this.id, tip);
+	var sTxt = '<SPAN CLASS="' + ((this.CSSClass) ? this.CSSClass : ((this.FirstChild != -1) ? 'node' : 'leaf')) + '">';
+	var lTxt = '<A NAME="joustEntry' + this.id + '"';
+	var theUrl = (((this.url == '') && theBrowser.canJSVoid && o.showAllAsLinks) || o.wizardInstalled) ? 'javascript:void(0);' : this.url;
+	if (theUrl != '') {
+		if (this.target.charAt(1) == "_") {theUrl = "javascript:" + o.reverseRef + ".loadURLInTarget('" + theUrl + "', '" + this.target + "');";}
+			lTxt += ' HREF="' + theUrl + '" TARGET="' + this.target + '" onClick' + mRef + '.itemClicked(' + this.id + ');"'
+			+ MOver + 'docIcon\',this);"' + MOut + 'docIcon\');"';
+	}
+	lTxt += (tip) ? ' TITLE="' + tip + '">' : '>';
+	aLine += sTxt + lTxt + theImg;
+	if (this.multiLine) {
+		aLine += '</A></SPAN><TABLE BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD>' + sTxt + lTxt + this.text + '</A></SPAN></TD></TR></TABLE>';
+	} else {
+		aLine += this.text + '</A></SPAN>';
+	}
+	aLine += '</nobr>';
+	if ((theBrowser.hasW3CDOM) && (theBrowser.hasDHTML) && (!this.multiLine))  { aLine += '<br>'; }
+	return aLine
+}
+function MIGetPMIconName() {
+	var n = 'icon' + ((this.FirstChild != -1) ? ((this.isopen == true) ? 'Minus' : 'Plus') : 'Join');
+	n += (this.id == this.owner.firstEntry) ? ((this.nextItem == -1) ? 'Only' : 'Top') : ((this.nextItem == -1) ? 'Bottom' : '');
+	return n;
+}
+function MIGetDocIconName() {
+	var is = this.owner.imgStore; var n = this.type;
+	n += ((this.isopen) && (is.getSrc(n + 'Expanded') != '')) ? 'Expanded' : '';
+	n += ((this.isSelected) && (is.getSrc(n + 'Selected') != '')) ? 'Selected' : '';
+	return n;
+}
+function MISetImage(imgID, imgName) {
+	var o = this.owner; var s = o.imgStore.getSrc(imgName);
+	if ((s != '') && (theBrowser.canCache) && (!o.amBusy)) {
+		var img = (theBrowser.hasDHTML) ? getDHTMLImg(o.container + '.document', 'entryDIV' + this.id, imgID) : eval(o.container).document.images[imgID];
+		if (img && img.src != s) {img.src = s;} 
+	}
+}
+function MISetIsOpen (isOpen) {
+	if ((this.isopen != isOpen) && (this.FirstChild != -1)) {
+		this.isopen = isOpen;
+		this.setImg('plusMinusIcon' + this.id, this.PMIconName());
+		this.setImg('docIcon' + this.id, this.docIconName());
+		return true;
+	} else {
+		return false;
+	}
+}
+function MISetSelected (isSelected) {
+	this.isSelected = isSelected;
+	this.setImg('docIcon' + this.id, this.docIconName());
+	if ((this.parent >= 0) && this.owner.selectParents) {this.owner.entry[this.parent].setSelected(isSelected);}
+}
+function MISetIcon (newType) {
+	this.type = newType;
+	this.setImg('docIcon' + this.id, this.docIconName());
+}
+function MIMouseOver(imgName, theURL) {
+	eval(this.owner.container).status = '';  //Needed for setStatus to work on MSIE 3 - Go figure!?
+	var newImg = '';
+	var s = '';
+	if (imgName == 'plusMinusIcon') {
+		newImg = this.PMIconName();
+		s = 'Click to ' + ((this.isopen == true) ? 'collapse.' : 'expand.');
+	} else {
+		if (imgName == 'docIcon') {
+			newImg = this.docIconName();
+			s = (this.status != null) ? this.status : theURL;
+		}
+	}
+	setStatus(s);
+	if (theBrowser.canOnMouseOut) {this.setImg(imgName + this.id, newImg + 'MouseOver');}
+	if(this.onMouseOver) {var me=this;eval(me.onMouseOver);}
+	return true;
+}
+function MIMouseOut(imgName) {
+	clearStatus();
+	var newImg = '';
+	if (imgName == 'plusMinusIcon') {
+		newImg = this.PMIconName();
+	} else {
+		if (imgName == 'docIcon') {newImg = this.docIconName();}
+	}
+	this.setImg(imgName + this.id, newImg);
+	if(this.onMouseOut) {var me=this;eval(me.onMouseOut);}
+	return true;
+}
+// The Menu object.  This is basically an array object although the data in it is a tree.
+function Menu () {
+	this.count = -1;
+	this.version = '2.5.4';
+	this.firstEntry = -1;
+	this.autoScrolling = false;
+	this.modalFolders = false;
+	this.linkOnExpand = false;
+	this.toggleOnLink = false;
+	this.showAllAsLinks = false;
+	this.savePage = true;
+	this.name = 'theMenu';
+	this.container = 'menu';
+	this.reverseRef = 'parent';
+	this.contentFrame = 'text';
+	this.defaultTarget = 'text';
+	this.tipText = 'none';
+	this.selectParents = false;
+	this.lastPMClicked = -1;
+	this.selectedEntry = -1;
+	this.wizardInstalled = false;
+	this.amBusy = true;
+	this.maxHeight = 0;
+	this.imgStore = new imgStoreObject;
+	this.entry = new MenuItem(this, 0, '', '', '', '', -1, -1, -1);
+	this.contentWin = MenuGetContentWin;
+	this.getEmptyEntry = MenuGetEmptyEntry;
+	this.addEntry = MenuAddEntry;
+	this.addMenu = MenuAddEntry;
+	this.addChild = MenuAddChild;
+	this.rmvEntry = MenuRmvEntry;
+	this.rmvChildren = MenuRmvChildren;
+	this.draw = MenuDraw;
+	this.drawALevel = MenuDrawALevel;
+	this.refresh = MenuRefresh;
+	this.reload = MenuReload;
+	this.refreshDHTML = MenuRefreshDHTML;
+	this.scrollTo = MenuScrollTo;
+	this.itemClicked = MenuItemClicked;
+	this.selectEntry = MenuSelectEntry;
+	this.setEntry = MenuSetEntry;
+	this.setEntryByURL = MenuSetEntryByURL;
+	this.setAllChildren = MenuSetAllChildren;
+	this.setAll = MenuSetAll;
+	this.openAll = MenuOpenAll;
+	this.closeAll = MenuCloseAll;
+	this.findEntry = MenuFindEntry;
+	this.toggle = MenuToggle;
+}
+function MenuGetContentWin() {
+	return eval(((myOpener != null) ? 'myOpener.' : 'self.') + this.contentFrame);
+}
+function MenuGetEmptyEntry() {
+	for (var i = 0; i <= this.count; i++) {if (this.entry[i] == null) {break;}}
+	if (i > this.count) {this.count = i};
+	return i
+}
+function MenuAddEntry (addTo, type, text, url, status, insert) {
+	if (!insert) {insert=false;}
+	var theNI = -1;var theP = -1;var thePI = -1;
+	if (addTo < 0) {
+		var i = addTo = this.firstEntry;
+		if (!insert) {while (i > -1) {addTo = i;i = this.entry[i].nextItem;}}
+	}
+	if (addTo >= 0) {
+		var e = this.entry[addTo];
+		if (!e) {return -1;}
+		thePI = (insert)?e.prevItem:addTo;
+		theNI = (insert)?addTo:e.nextItem;
+		theP = e.parent;
+	}
+	var eNum = this.getEmptyEntry();
+	if (thePI >= 0) {
+		this.entry[thePI].nextItem = eNum;
+	} else {
+		if (theP >= 0) {
+			this.entry[theP].FirstChild = eNum;
+		} else {
+			this.firstEntry = eNum;
+		}
+	}
+	if (theNI >= 0) {this.entry[theNI].prevItem = eNum;}
+	this.entry[eNum] = new MenuItem(this, eNum, type, text, url, status, theNI, thePI, theP);
+	return eNum;
+}
+function MenuAddChild (addTo, type, text, url, status, insert) {
+	if (!insert) {insert=false;}
+	var eNum = -1;
+	if ((this.count == -1) || (addTo < 0)) {
+		eNum = this.addEntry(-1, type, text, url, status, false);
+	} else {
+		var e = this.entry[addTo];
+		if (!e) {return -1;}
+		var cID = e.FirstChild;
+		if (cID < 0) {
+			e.FirstChild = eNum = this.getEmptyEntry();
+			this.entry[eNum] = new MenuItem(this, eNum, type, text, url, status, -1, -1, addTo);	
+		} else {
+			while (!insert && (this.entry[cID].nextItem >= 0)) {cID = this.entry[cID].nextItem;}
+			eNum = this.addEntry(cID, type, text, url, status, insert);
+		}
+	}
+	return eNum;
+}
+function MenuRmvEntry (theEntry) {
+	var e = this.entry[theEntry];
+	if (e == null) {return;}
+	var p = e.prevItem;
+	var n = e.nextItem;
+	if (e.FirstChild > -1) {this.rmvChildren(theEntry);}
+	if (this.firstEntry == theEntry) {this.firstEntry = n}
+	if (this.selectedEntry == theEntry) {this.selectedEntry = n}
+	if (p > -1) {
+		this.entry[p].nextItem = n;
+	} else { 
+		if (e.parent > -1) {
+			this.entry[e.parent].FirstChild = n;
+		} else {
+			if (this.firstEntry == theEntry) {this.firstEntry = n}
+		}
+	} 
+	if (n > -1) {this.entry[n].prevItem = p;}
+	this.entry[theEntry] = null;
+}
+function MenuRmvChildren (theP) {
+	var eNum;var e;var tmp;
+	if (theP == -1) {
+		eNum = this.firstEntry;
+		this.firstEntry = -1;
+	} else {
+		eNum = this.entry[theP].FirstChild;
+		this.entry[theP].FirstChild = -1;
+	}
+	while (eNum > -1) {
+		e = this.entry[eNum];
+		if (e.FirstChild > -1) {this.rmvChildren(eNum);}
+		if (this.selectedEntry == eNum) {this.selectedEntry = e.parent;}
+		tmp = eNum;
+		eNum = e.nextItem;
+		this.entry[tmp] = null;
+	}
+}
+function MenuDraw() {
+	this.maxHeight = 0;
+	var theDoc = eval(this.container + ".document");
+	eval(this.container).document.writeln(this.drawALevel(this.firstEntry, '', true, theDoc));
+	if (theBrowser.hasDHTML) {
+		for (var i = 0; i <= this.count; i++) {
+			if (this.entry[i]) {
+				this.maxHeight += getDHTMLObjHeight(this.container + '.document', 'entryDIV' + i);
+			}
+		}
+	} else {
+		if ((this.lastPMClicked > 0) && theBrowser.mustMoveAfterLoad && this.autoScrolling) {
+			this.scrollTo(this.lastPMClicked);
+		}
+	}
+}
+function MenuDrawALevel(firstItem, indentStr, isVisible, theDoc) {
+	var currEntry = firstItem;
+	var padImg = "";
+	var aLine = "";
+	var theLevel = "";
+	var e = null;
+	while (currEntry > -1) {
+		e = this.entry[currEntry];
+		aLine = e.draw(indentStr);
+		if (theBrowser.hasDHTML) {
+			aLine = '<DIV ID="entryDIV' + currEntry + '" CLASS="menuItem">' + aLine + '</DIV>';
+		} else {
+			aLine += '<BR CLEAR="ALL">';
+		}
+		theBrowser.lineByLine = true;
+		if (theBrowser.lineByLine) {theDoc.writeln(aLine);} else {theLevel += aLine;}
+		if ((e.FirstChild > -1) && ((theBrowser.hasDHTML || (e.isopen && isVisible)))) {
+			padImg = (e.noOutlineImg) ? '' : this.imgStore.getTag((e.nextItem == -1) ? 'iconBlank' : 'iconLine', '', '');
+			theLevel += this.drawALevel(e.FirstChild, indentStr + padImg, (e.isopen && isVisible), theDoc);
+		}
+		currEntry = e.nextItem;
+	}
+	return theLevel;
+}
+function MenuRefresh() {
+	if (theBrowser.hasDHTML) {
+		if (!this.amBusy) {
+			this.refreshDHTML();
+			if (this.autoScrolling) {this.scrollTo(this.lastPMClicked);}
+		}
+	} else {
+		this.reload();
+	}
+}
+function MenuReload() {
+	if (!this.amBusy) {
+		this.amBusy = true;
+		var l = eval(this.container).location;
+		var rm = theBrowser.reloadMethod;
+		var newLoc = fixPath(l.pathname);
+		var s = '';
+		if (l.search) {s = l.search;}
+		if (theBrowser.needsMenuSearch) {
+			if (s == '') {
+				s = '?jtoggle=1';
+			} else {
+				var p = s.indexOf('jtoggle=');
+				if (p < 0) {
+					s += '&jtoggle=1';
+				} else {
+					var t = (s.substring(p + 8, p + 9) == "1") ? "2" : "1";
+					s = s.substring(0, p+8) + t;
+				}
+			}
+		}
+		newLoc += s;
+		if (this.autoScrolling && (this.lastPMClicked > 0) && !theBrowser.mustMoveAfterLoad) {
+			newLoc += "#joustEntry" + this.lastPMClicked;
+		}
+		if (rm == 'replace') {
+			l.replace(newLoc);
+		} else {
+			if (rm == 'reload') {
+				l.reload();
+			} else {
+				if (rm == 'timeout') {
+					setTimeout(this.container + ".location.href ='" + newLoc + "';", 100);
+				} else {
+					l.href = newLoc;
+				}
+			}
+		}
+	}
+}
+function MenuRefreshDHTML() {
+	var nextItemArray = new simpleArray;
+	var currEntry = this.firstEntry;
+	var level = (currEntry == -1) ? 0 : 1;
+	var isVisible = true;
+	var lastVisibleLevel = 1;
+	var co = eval(this.container);
+	var yPos = co.menuStart;
+	var d = this.container + '.document';
+	var e = null;var s = null;
+	while (level > 0) {
+		e = this.entry[currEntry];
+		s = getDHTMLObj(d, 'entryDIV' + currEntry);
+		if (isVisible) {
+			s.top = yPos;
+			s.visibility = 'visible';
+			yPos += getDHTMLObjHeight(d, 'entryDIV' + currEntry);
+			lastVisibleLevel = level;
+		} else {
+			s.visibility = 'hidden';
+			s.top = 0;
+		}
+		if (e.FirstChild > -1) {
+			isVisible = (e.isopen == true) && isVisible;
+			nextItemArray[level++] = e.nextItem;
+			currEntry = e.FirstChild;
+		} else {
+			if (e.nextItem != -1) {
+				currEntry = e.nextItem;
+			} else {
+				while (level > 0) {
+					if (nextItemArray[--level] != -1) {
+						currEntry = nextItemArray[level];
+						isVisible = (lastVisibleLevel >= level);
+						break;
+					}
+				}
+			}
+		}
+	}
+	this.maxHeight = yPos;
+	co.setMenuHeight(yPos);
+}
+function MenuScrollTo(entryNo) {
+	if (theBrowser.hasDHTML) {
+		var e = this.entry[entryNo];
+		if (!e) {return;}
+		var co = eval(this.container);
+		var d = this.container + '.document';
+		var srTop = getDHTMLObjTop(getDHTMLObj(d, 'entryDIV' + entryNo));
+		var srBot = (e.nextItem > 0) ? getDHTMLObjTop(getDHTMLObj(d, 'entryDIV' + e.nextItem)) : this.maxHeight;
+		if (theBrowser.code == 'MSIE') {
+			var curTop = co.document.body.scrollTop;
+			var curBot = curTop + co.document.body.clientHeight;
+		} else {
+			var curTop = co.pageYOffset;
+			var curBot = curTop + co.innerHeight;
+		}
+		if ((srBot > curBot) || (srTop < curTop)) {
+			var scrBy = srBot - curBot;
+			if (srTop < (curTop + scrBy)) {scrBy = srTop - curTop;}
+			co.setTimeout('self.scrollBy(0, ' + scrBy + ');', 100);
+		}
+	} else {
+		var l = fixPath(eval(this.container).location.pathname) + '#joustEntry' + entryNo;
+		setTimeout(this.container + '.location.href = "' + l + '";', 100);
+	}
+}
+function MenuItemClicked(entryNo, fromToggle) {
+	var r = true;
+	var e = this.entry[entryNo];
+	var w = this.contentWin();
+	var b = theBrowser;
+
+	this.selectEntry(entryNo);
+	if (this.wizardInstalled) {w.menuItemClicked(entryNo);}
+	if(e.onClickFunc) {e.onClick = e.onClickFunc;}
+	if(e.onClick) {var me=e;if(eval(e.onClick) == false) {r = false;}}
+	if (r) {
+		if (((this.toggleOnLink) && (e.FirstChild != -1) && !(fromToggle)) || e.noOutlineImg) {
+			if (b.hasDHTML) {
+				this.toggle(entryNo, true);
+			} else {
+				setTimeout(this.name + '.toggle(' + entryNo + ', true);', 100);
+			}
+		}
+	}
+	return (e.url != '') ? r : false;
+}
+function MenuSelectEntry(entryNo) {
+	var oe = this.entry[this.selectedEntry];
+	if (oe) {oe.setSelected(false);}
+	var e = this.entry[entryNo];
+	if (e) {e.setSelected(true);}
+	this.selectedEntry = entryNo;
+}
+function MenuSetEntry(entryNo, state) {
+	var cl = ',' + entryNo + ',';
+	var e = this.entry[entryNo];
+	this.lastPMClicked = entryNo;
+	var mc = e.setIsOpen(state);
+	var p = e.parent;
+	while (p >= 0) {
+		cl += p + ',';
+		e = this.entry[p];
+		mc |= (e.setIsOpen(true));
+		p = e.parent;
+	}
+	if (this.modalFolders) {
+		for (var i = 0; i <= this.count; i++) {
+			e = this.entry[i];
+			if ((cl.indexOf(',' + i + ',') < 0) && e) {mc |= e.setIsOpen(false);}
+		}
+	}
+	return mc;
+}
+function MenuSetEntryByURL(theURL, state) {
+	var i = this.findEntry(theURL, 'url', 'right', 0);
+	return (i != -1) ? this.setEntry(i, state) : false;
+}
+function MenuSetAllChildren(state, parentID) {
+	var hasChanged = false;
+	var currEntry = (parentID > -1) ? this.entry[parentID].FirstChild : this.firstEntry;
+	while (currEntry > -1) {
+		var e = this.entry[currEntry];
+		hasChanged |= e.setIsOpen(state);
+		if (e.FirstChild > -1) {hasChanged |= this.setAllChildren(state, currEntry);}
+		currEntry = e.nextItem;
+	}
+	return hasChanged;
+}
+function MenuSetAll(state, parentID) {
+	if (theBrowser.version >= 4) {
+		if (parentID == 'undefined') {parentID = -1;}
+	} else {
+		if (parentID == null) {parentID = -1;}
+	}
+	var hasChanged = false;
+	if (parentID > -1) {hasChanged |= this.entry[parentID].setIsOpen(state);}
+	hasChanged |= this.setAllChildren(state, parentID);
+	if (hasChanged) {
+		this.lastPMClicked = this.firstEntry;
+		this.refresh();
+	}
+}
+function MenuOpenAll() {this.setAll(true, -1);}
+function MenuCloseAll() {this.setAll(false, -1)}
+function MenuFindEntry(srchVal, srchProp, matchType, start) {
+	var e;
+	var sf;
+	if (srchVal == "") {return -1;}
+	if (!srchProp) {srchProp = "url";}
+	if (!matchType) {matchType = "exact";}
+	if (!start) {start = 0;}
+	if (srchProp == "URL") {srchProp = "url";}
+	if (srchProp == "title") {srchProp = "text";}
+	eval("sf = cmp_" + matchType);
+	for (var i = start; i <= this.count; i++) {
+		if (this.entry[i]) {
+			e = this.entry[i];
+			if (sf(eval("e." + srchProp), srchVal)) {return i;}
+		}		
+	}
+	return -1;
+}
+function cmp_exact(c, s) {return (c == s);}
+function cmp_left(c, s) {
+	var l = Math.min(c.length, s.length);
+	return ((c.substring(1, l) == s.substring(1, l)) && (c != ""));
+}
+function cmp_right(c, s) {
+	var l = Math.min(c.length, s.length);
+	return ((c.substring(c.length-l) == s.substring(s.length-l)) && (c != ""));
+}
+function cmp_contains(c, s) {return (c.indexOf(s) >= 0);}
+function MenuToggle(entryNo, fromClicked) {
+	var r = true;
+	var e = this.entry[entryNo];
+	if (e.onToggle) {var me=e;if(eval(e.onToggle) == false) {r = false;}}
+	if (r) {
+		var chg = this.setEntry(entryNo, e.isopen ^ 1);
+		if (this.linkOnExpand && e.isopen) {
+			if (e.url != '') {loadURLInTarget(e.url, e.target);}
+			if (!fromClicked) {this.itemClicked(entryNo, true);}
+		}
+		if (chg) {this.refresh();}
+	}
+	return false;
+}
+// Other functions
+function DrawMenu(m) {
+	m.draw();
+}
+function browserInfo() {
+	this.code = 'unknown';
+	this.version = 0;
+	this.platform = 'Win';
+	var ua = navigator.userAgent;
+	var i = ua.indexOf('WebTV');
+	if (i >= 0) {
+		this.code = 'WebTV';
+		i += 6;
+	} else {
+		i = ua.indexOf('Opera');
+		if (i >= 0) {
+			this.code = 'OP';
+			i = ua.indexOf(') ') + 2;
+		} else {
+			i = ua.indexOf('MSIE');
+			if (i >= 0) {
+				this.code = 'MSIE';
+				i += 5;
+			} else {
+				i = ua.indexOf('Mozilla/');
+				if (i >= 0) {
+					this.code = 'NS';
+					i += 8;
+				}
+			}
+		}
+	}
+	this.version = parseFloat(ua.substring(i, i+4));
+	if (ua.indexOf('Mac') >= 0) {this.platform = 'Mac';}
+	if (ua.indexOf('OS/2') >= 0) {this.platform = 'OS/2';}
+	if (ua.indexOf('X11') >= 0) {this.platform = 'UNIX';}
+	var v = this.version;
+	var p = this.platform;
+	var NS = (this.code == 'NS');
+	var IE = (this.code == 'MSIE');
+	var WTV = (this.code == 'WebTV');
+	var OP = (this.code == 'OP');
+	var OP32up = (OP && (v >= 3.2));
+	var OP5up = (OP && (v >= 5));
+	var IE4up = (IE && (v >= 4));
+	var NS3up = (NS && (v >= 3));
+	var NS6up = (NS && (v >= 5));
+	this.canCache = NS3up || IE4up || OP32up || WTV;
+	this.canOnMouseOut = this.canCache;
+	this.canOnError = NS3up || IE4up || OP32up;
+	this.canJSVoid = !((NS && !NS3up) || (IE && !IE4up) || (OP && (v < 3.5)));
+	this.lineByLine = (v < 4);
+	this.mustMoveAfterLoad = NS3up || (IE4up && (p != 'Mac')) || WTV;
+	if (NS6up == true) {
+		this.reloadMethod = 'reload';
+	} else {
+		if (NS3up || IE4up || WTV || OP5up) {
+			this.reloadMethod = 'replace';
+		} else {
+			this.reloadMethod = (NS && (v == 2.01) && (p != 'Win')) ? 'timeout' : 'href';
+		}
+	}
+	this.needsMenuSearch = (OP && !OP5up);
+	this.canFloat = NS || (IE && !((p == 'Mac') && (v >= 4) && (v < 5)));
+	this.hasDHTML = ((NS || IE) && (v >= 4)) && !(IE && (p == 'Mac') && (v < 4.5));
+	this.slowDHTML = IE4up || NS6up;
+	this.hasW3CDOM = (document.getElementById) ? true : false;
+	this.needLM = (!this.hasW3CDOM && NS) || (IE && (p == 'Mac') && (v >= 4.5));
+	this.DHTMLRange = IE ? '.all' : '';
+	this.DHTMLStyleObj = IE ? '.style' : '';
+	this.DHTMLDivHeight = IE ? '.offsetHeight' : '.clip.height';
+}
+function getWindow() {return (floatingMode) ? myOpener : self;}
+function setStatus(theText) {
+	var theWindow = getWindow();
+	if (theWindow) {
+		theWindow.status = theText;
+		if (!theBrowser.canOnMouseOut) {
+			clearTimeout(statusTimeout);
+			statusTimeout = setTimeout('clearStatus()', 5000);
+		}
+	}
+	return true;
+}
+function clearStatus() {
+	var theWindow = getWindow();
+	if (theWindow) {theWindow.status = '';}
+}
+function unloadFloating() {
+	if (myOpener) {
+		if (myOpener.JoustFrameset) {myOpener.setTimeout('menuClosed();', 100);}
+	}
+}
+function getMode() {
+	var theMode = getParm(document.cookie, 'mode', ';');
+	return ((theMode == "Floating") || (theMode == "NoFrames")) ? theMode : "Frames";
+}
+function smOnError (msg, url, lno) {
+	smCallerWin.onerror = oldErrorHandler;
+	if (confirm(smSecurityMsg)) {setTimeout('setMode("' + smNewMode + '");', 100);}
+	return true;
+}
+function smSetCookie(theMode) {
+	document.cookie = 'mode=' + theMode + '; path=/';
+	if (getMode() != theMode) {
+		alert(smCookieMsg);
+		return false;
+	} else {
+		return true;
+	}
+}
+function setMode(theMode, callerWin) {
+	smNewMode = theMode
+	smCallerWin = (theBrowser.code == 'NS') ? callerWin : self;
+	var okToGo = true;
+	var currentMode = getMode();
+	if (theMode != currentMode) {
+		if (currentMode == 'Floating') {
+			if (smSetCookie(theMode)) {self.close();}
+		} else {
+			var dest = '';
+			if (theBrowser.canFloat) {
+				if ((theMenu.savePage) && (callerWin)) {
+					if (theBrowser.canOnError) {
+						oldErrorHandler = smCallerWin.onerror;
+						smCallerWin.onerror = smOnError;
+					}
+					var l = theMenu.contentWin().location;
+					var p = l.pathname;
+					if (theBrowser.canOnError) {smCallerWin.onerror = oldErrorHandler;}
+					if (p) {
+						dest = fixPath(p) + l.search;
+					} else {
+						if (!confirm(smSecurityMsg)) {okToGo = false;}
+					}
+				}
+			} else {
+				okToGo = false;
+			}
+			if (okToGo && smSetCookie(theMode)) {
+				if (theMode == 'NoFrames') {
+					location.href = (index3 == '') ? ((dest == '') ? '/' : dest) : index3;
+				} else {
+					location.href = index2 + ((dest == '') ? '' : '?page=' + escape(dest));
+				}
+			}
+		}
+	}
+}
+function fixPath(p) {
+	var i = p.indexOf('?', 0);
+	if (i >= 0) {p = p.substring(0,i);}
+	if (p.substring(0,2) == '/:') {p = p.substring(p.indexOf('/', 2), p.length);}
+	i = p.indexOf('\\', 0);
+	while (i >= 0) {
+		p = p.substring(0,i) + '/' + p.substring(i+1,p.length);
+		i = p.indexOf('\\', i);
+	}
+	return p;
+}
+function fileFromPath(p) {
+	p = fixPath(p);
+	var i = p.lastIndexOf('\\');
+	if (i >= 0) {p = p.substring(i+1,p.length);}
+	return p;
+}
+function getParm(theStr, parm, delim) {
+	// returns value of parm from string
+	if (theStr.length == 0) {return '';}
+	var sPos = theStr.indexOf(parm + "=");
+	if (sPos == -1) {return '';}
+	sPos = sPos + parm.length + 1;
+	var ePos = theStr.indexOf(delim, sPos);
+	if (ePos == -1) {ePos = theStr.length;}
+	return unescape(theStr.substring(sPos, ePos));
+}
+function pageFromSearch(def, m, selIt) {
+	var s = self.location.search;
+	if ((s == null) || (s.length <= 1)) {return def;}
+	var p = getParm(s, 'page', '&');
+	p = (p != '') ? fixPath(p) : def;
+	if (m != null) {
+		var e = m.findEntry(p, 'URL', 'exact');
+		if ((e != -1) && selIt) {
+			m.setEntry(e, true);
+			m.selectEntry(e);
+		}
+	}
+	return p;
+}
+function loadURLInTarget(u, t) {
+	var w = eval("self." + t);
+	if (!w && myOpener) {w = eval("myOpener." + t);}
+	if (!w && ("_top,_parent,_self".indexOf(t) >= 0)) {
+		w = eval("getWindow()." + t.substring(1));}
+	if (w) {w.location.href = u;} else {window.open(u, t);}
+}
+function defOnError(msg, url, lno) {
+	if (jsErrorMsg == '') {
+		return false;
+	} else {
+		alert(jsErrorMsg + '.\n\nError: ' + msg + '\nPage: ' + url + '\nLine: ' + lno + '\nBrowser: ' + navigator.userAgent);
+		return true;
+	}
+}
+function defaultResizeHandler() {
+	if ((theBrowser.code == "NS") && theBrowser.hasDHTML && (self.frames.length != 0)) {
+		if (!eval(theMenu.container + ".document.menuBottom")) {
+			theMenu.reload();
+		}
+	}
+}
+// Declare global variables
+var theBrowser = new browserInfo;
+
+var jsErrorMsg = 'A JavaScript error has occurred on this page!  Please note down the ';
+jsErrorMsg += 'following information and pass it on to the Webmaster.';
+if (theBrowser.canOnError) {self.onerror = defOnError;}
+
+var theMenu = new Menu;
+var JoustFrameset = true;
+var statusTimeout = 0;
+var index1 = 'index.htm';
+var index2 = 'index2.htm';
+var index3 = 'index3.htm';
+var smCallerWin;
+var smNewMode;
+var oldErrorHandler;
+var smNoFloat = 'Sorry, your browser does not support this feature!';
+var smCookieMsg = 'You must have Cookies enabled to change the display mode!';
+var smSecurityMsg = 'Due to security restrictions imposed by your browser, I cannot ';
+smSecurityMsg += 'change modes while a page from another server is being displayed. ';
+smSecurityMsg += 'The default home page for this site will be displayed instead.';
+
+var floatingMode = (getMode() == 'Floating');
+var myOpener = null;
+if (floatingMode == true) {
+	if (self.opener) {
+		myOpener = self.opener;
+		if (myOpener.JoustFrameset) {myOpener.setTimeout('setGlobals();', 100);}
+	} else {
+		document.cookie = 'mode=Frames; path=/';
+		floatingMode = false;
+	}
+} else {
+	if (getMode() != 'Frames') {document.cookie = 'mode=Frames; path=/';}
+}
+
+//	############################   End of Joust   ############################
+
+function initOutlineIcons(imgStore) {
+	var ip = 'images/menu/';
+	ip += (theBrowser.platform == 'Mac') ? 'mac/' : ((theBrowser.platform == 'OS/2') ? 'os2/' : 'win/');
+	
+	imgStore.add('iconPlusTop', ip + 'plustop.gif', 18, 16);
+	imgStore.add('iconPlus', ip + 'plus.gif', 18, 16);
+	imgStore.add('iconPlusBottom', ip + 'plusbottom.gif', 18, 16);
+	imgStore.add('iconPlusOnly', ip + 'plusonly.gif', 18, 16);
+	imgStore.add('iconMinusTop', ip + 'minustop.gif', 18, 16);
+	imgStore.add('iconMinus', ip + 'minus.gif', 18, 16);
+	imgStore.add('iconMinusBottom', ip + 'minusbottom.gif', 18, 16);
+	imgStore.add('iconMinusOnly', ip + 'minusonly.gif', 18, 16);
+	imgStore.add('iconLine', ip + 'line.gif', 18, 16);
+	imgStore.add('iconBlank', ip + 'blank.gif', 18, 16);
+	imgStore.add('iconJoinTop', ip + 'jointop.gif', 18, 16);
+	imgStore.add('iconJoin', ip + 'join.gif', 18, 16);
+	imgStore.add('iconJoinBottom', ip + 'joinbottom.gif', 18, 16);
+
+	//Add folder and document images to the imgStore.
+	imgStore.add('Folder', ip + 'folderclosed.gif', 18, 16);
+	
+	var di = 'images/menu/';
+	if ((theBrowser.code == 'NS') || (theBrowser.code == 'MSIE')) {
+		di += theBrowser.code.toLowerCase() + '_doc';
+		imgStore.add('Document', di + '.gif', 18, 16);
+		imgStore.add('DocumentMouseOver', di + '_mo.gif', 18, 16);
+		imgStore.add('DocumentSelected', di + '_sel.gif', 18, 16);
+	} else {
+		imgStore.add('Document', di + 'doc.gif', 18, 16);
+	}
+	var prjImages='images/ext/';	
+	imgStore.add('ACP', prjImages + 'acp.gif', 18, 16);
+	imgStore.add('ACPSelected', prjImages + 'acpselected.gif', 18, 16);
+	imgStore.add('ACPMouseOver', prjImages + 'acpselected.gif', 18, 16);
+	imgStore.add('AHW', prjImages + 'ahw.gif', 18, 16);
+	imgStore.add('AHWSelected', prjImages + 'ahwselected.gif', 18, 16);
+	imgStore.add('AHWMouseOver', prjImages + 'ahwselected.gif', 18, 16);
+	imgStore.add('ASF', prjImages + 'asf.gif', 18, 16);
+	imgStore.add('ASFSelected', prjImages + 'asfselected.gif', 18, 16);
+	imgStore.add('ASFMouseOver', prjImages + 'asfselected.gif', 18, 16);
+	imgStore.add('AWF', prjImages + 'awf.gif', 18, 16);
+	imgStore.add('AWFSelected', prjImages + 'awfselected.gif', 18, 16);
+	imgStore.add('AWFMouseOver', prjImages + 'awfselected.gif', 18, 16);
+	imgStore.add('BAS', prjImages + 'bas.gif', 18, 16);
+	imgStore.add('BASSelected', prjImages + 'basselected.gif', 18, 16);
+	imgStore.add('BASMouseOver', prjImages + 'basselected.gif', 18, 16);
+	imgStore.add('BDE', prjImages + 'bde.gif', 18, 16);
+	imgStore.add('BDESelected', prjImages + 'bdeselected.gif', 18, 16);
+	imgStore.add('BDEMouseOver', prjImages + 'bdeselected.gif', 18, 16);
+	imgStore.add('CONF', prjImages + 'conf.gif', 18, 16);
+	imgStore.add('CONFSelected', prjImages + 'confselected.gif', 18, 16);
+	imgStore.add('CONFMouseOver', prjImages + 'confselected.gif', 18, 16);
+	imgStore.add('CPP', prjImages + 'cpp.gif', 18, 16);
+	imgStore.add('CPPSelected', prjImages + 'cppselected.gif', 18, 16);
+	imgStore.add('CPPMouseOver', prjImages + 'cppselected.gif', 18, 16);
+	imgStore.add('DLM', prjImages + 'dlm.gif', 18, 16);
+	imgStore.add('DLMSelected', prjImages + 'dlmselected.gif', 18, 16);
+	imgStore.add('DLMMouseOver', prjImages + 'dlmselected.gif', 18, 16);
+	imgStore.add('DO', prjImages + 'do.gif', 18, 16);
+	imgStore.add('DOSelected', prjImages + 'doselected.gif', 18, 16);
+	imgStore.add('DOMouseOver', prjImages + 'doselected.gif', 18, 16);
+	imgStore.add('DRW', prjImages + 'drw.gif', 18, 16);
+	imgStore.add('DRWSelected', prjImages + 'drwselected.gif', 18, 16);
+	imgStore.add('DRWMouseOver', prjImages + 'drwselected.gif', 18, 16);
+	imgStore.add('EDN', prjImages + 'edn.gif', 18, 16);
+	imgStore.add('EDNSelected', prjImages + 'ednselected.gif', 18, 16);
+	imgStore.add('EDNMouseOver', prjImages + 'ednselected.gif', 18, 16);
+	imgStore.add('HP', prjImages + 'hp.gif', 18, 16);
+	imgStore.add('HPSelected', prjImages + 'hpselected.gif', 18, 16);
+	imgStore.add('HPMouseOver', prjImages + 'hpselected.gif', 18, 16);
+	imgStore.add('HTM', prjImages + 'htm.gif', 18, 16);
+	imgStore.add('HTMSelected', prjImages + 'htmselected.gif', 18, 16);
+	imgStore.add('HTMMouseOver', prjImages + 'htmselected.gif', 18, 16);
+	imgStore.add('LST', prjImages + 'lst.gif', 18, 16);
+	imgStore.add('LSTSelected', prjImages + 'lstselected.gif', 18, 16);
+	imgStore.add('LSTMouseOver', prjImages + 'lstselected.gif', 18, 16);
+	imgStore.add('PL', prjImages + 'pl.gif', 18, 16);
+	imgStore.add('PLSelected', prjImages + 'plselected.gif', 18, 16);
+	imgStore.add('PLMouseOver', prjImages + 'plselected.gif', 18, 16);
+	imgStore.add('SDF', prjImages + 'sdf.gif', 18, 16);
+	imgStore.add('SDFSelected', prjImages + 'sdfselected.gif', 18, 16);
+	imgStore.add('SDFMouseOver', prjImages + 'sdfselected.gif', 18, 16);
+	imgStore.add('SYMB', prjImages + 'symb.gif', 18, 16);
+	imgStore.add('SYMBSelected', prjImages + 'symbselected.gif', 18, 16);
+	imgStore.add('SYMBMouseOver', prjImages + 'symbselected.gif', 18, 16);
+	imgStore.add('TCL', prjImages + 'tcl.gif', 18, 16);
+	imgStore.add('TCLSelected', prjImages + 'tclselected.gif', 18, 16);
+	imgStore.add('TCLMouseOver', prjImages + 'tclselected.gif', 18, 16);
+	imgStore.add('TXT', prjImages + 'txt.gif', 18, 16);
+	imgStore.add('TXTSelected', prjImages + 'txtselected.gif', 18, 16);
+	imgStore.add('TXTMouseOver', prjImages + 'txtselected.gif', 18, 16);
+	imgStore.add('UND', prjImages + 'und.gif', 18, 16);
+	imgStore.add('UNDSelected', prjImages + 'undselected.gif', 18, 16);
+	imgStore.add('UNDMouseOver', prjImages + 'undselected.gif', 18, 16);
+	imgStore.add('UNDEF', prjImages + 'undef.gif', 18, 16);
+	imgStore.add('UNDEFSelected', prjImages + 'undefselected.gif', 18, 16);
+	imgStore.add('UNDEFMouseOver', prjImages + 'undefselected.gif', 18, 16);
+	imgStore.add('V', prjImages + 'v.gif', 18, 16);
+	imgStore.add('VSelected', prjImages + 'vselected.gif', 18, 16);
+	imgStore.add('VMouseOver', prjImages + 'vselected.gif', 18, 16);
+	imgStore.add('VHD', prjImages + 'vhd.gif', 18, 16);
+	imgStore.add('VHDSelected', prjImages + 'vhdselected.gif', 18, 16);
+	imgStore.add('VHDMouseOver', prjImages + 'vhdselected.gif', 18, 16);
+	imgStore.add('VLS', prjImages + 'vls.gif', 18, 16);
+	imgStore.add('VLSSelected', prjImages + 'vlsselected.gif', 18, 16);
+	imgStore.add('VLSMouseOver', prjImages + 'vlsselected.gif', 18, 16);
+	imgStore.add('VSSVER', prjImages + 'vssver.gif', 18, 16);
+	imgStore.add('VSSVERSelected', prjImages + 'vssverselected.gif', 18, 16);
+	imgStore.add('VSSVERMouseOver', prjImages + 'vssverselected.gif', 18, 16);
+	imgStore.add('VTB', prjImages + 'vtb.gif', 18, 16);
+	imgStore.add('VTBSelected', prjImages + 'vtbselected.gif', 18, 16);
+	imgStore.add('VTBMouseOver', prjImages + 'vtbselected.gif', 18, 16);
+	imgStore.add('XNF', prjImages + 'xnf.gif', 18, 16);
+	imgStore.add('XNFSelected', prjImages + 'xnfselected.gif', 18, 16);
+	imgStore.add('XNFMouseOver', prjImages + 'xnfselected.gif', 18, 16);
+
+}
+function initialise() {
+if ((theBrowser.hasDHTML) && (theBrowser.slowDHTML)) {theBrowser.hasDHTML = false;}
+
+	// Tell joust where to find the various index files it needs
+	index1 = 'index.htm';
+	index2 = 'index2.htm';
+	index3 = 'index3.htm';
+	
+	// Set up parameters to control menu behaviour
+	theMenu.autoScrolling = true;	
+	theMenu.modalFolders = false;
+	theMenu.linkOnExpand = false;
+	theMenu.toggleOnLink = false;
+	theMenu.showAllAsLinks = false;
+	theMenu.savePage = true;
+	theMenu.tipText = "status";
+	theMenu.selectParents = false;
+	theMenu.name = "theMenu";
+	theMenu.container = "self.menu";
+	theMenu.reverseRef = "parent";
+	theMenu.contentFrame = "text";
+	theMenu.defaultTarget = "text";
+	
+	// Initialise all the icons
+	initOutlineIcons(theMenu.imgStore);
+	
+	// Now set up the menu with a whole lot of addEntry and addChild function calls
+var level0ID = -1;
+var level1ID = -1;
+var level2ID = -1;
+level0ID = theMenu.addChild(level0ID, "ACP", "usbhostslave", "info/index.htm", "");
+theMenu.entry[level0ID].isopen=true;
+level1ID = theMenu.addChild(level0ID, "Folder", "buffers", "", ""
+);level2ID = theMenu.addChild(level1ID, "V", "TxFifoBI.v", "src/buffers/TxFifoBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "fifoMem.v", "src/buffers/fifoMem.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "fifoRTL.v", "src/buffers/fifoRTL.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "RxFifo.v", "src/buffers/RxFifo.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "RxFifoBI.v", "src/buffers/RxFifoBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "simFifoMem.v", "src/buffers/simFifoMem.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "TxFifo.v", "src/buffers/TxFifo.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "busInterface", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "wishBoneBI.v", "src/busInterface/wishBoneBI.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "hostController", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "USBHostControlBI.v", "src/hostController/USBHostControlBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "directcontrol.asf", "src/hostController/directcontrol.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "directcontrol.v", "src/hostController/directcontrol.asf/directcontrol.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "getpacket.asf", "src/hostController/getpacket.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "getpacket.v", "src/hostController/getpacket.asf/getpacket.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "hctxportarbiter.asf", "src/hostController/hctxportarbiter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "hctxportarbiter.v", "src/hostController/hctxportarbiter.asf/hctxportarbiter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "hostcontroller.asf", "src/hostController/hostcontroller.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "hostcontroller.v", "src/hostController/hostcontroller.asf/hostcontroller.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sendpacket.asf", "src/hostController/sendpacket.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sendpacket.v", "src/hostController/sendpacket.asf/sendpacket.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sendpacketarbiter.asf", "src/hostController/sendpacketarbiter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sendpacketarbiter.v", "src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sendpacketcheckpreamble.asf", "src/hostController/sendpacketcheckpreamble.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sendpacketcheckpreamble.v", "src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sofcontroller.asf", "src/hostController/sofcontroller.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sofcontroller.v", "src/hostController/sofcontroller.asf/sofcontroller.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "softransmit.asf", "src/hostController/softransmit.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "softransmit.v", "src/hostController/softransmit.asf/softransmit.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "rxStatusMonitor.v", "src/hostController/rxStatusMonitor.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "speedCtrlMux.v", "src/hostController/speedCtrlMux.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbHostControl.v", "src/hostController/usbHostControl.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "hostSlaveMux", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "hostSlaveMuxBI.v", "src/hostSlaveMux/hostSlaveMuxBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "hostSlaveMux.v", "src/hostSlaveMux/hostSlaveMux.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "include", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "wishBoneBus_h.v", "src/include/wishBoneBus_h.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbConstants_h.v", "src/include/usbConstants_h.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbHostControl_h.v", "src/include/usbHostControl_h.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbSerialInterfaceEngine_h.v", "src/include/usbSerialInterfaceEngine_h.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbSlaveControl_h.v", "src/include/usbSlaveControl_h.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "serialInterfaceEngine", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "writeUSBWireData.v", "src/serialInterfaceEngine/writeUSBWireData.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "processRxBit.asf", "src/serialInterfaceEngine/processRxBit.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "processRxBit.v", "src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "processRxByte.asf", "src/serialInterfaceEngine/processRxByte.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "processRxByte.v", "src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "processTxByte.asf", "src/serialInterfaceEngine/processTxByte.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "processTxByte.v", "src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "siereceiver.asf", "src/serialInterfaceEngine/siereceiver.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "siereceiver.v", "src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "SIETransmitter.asf", "src/serialInterfaceEngine/SIETransmitter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "SIETransmitter.v", "src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "usbTxWireArbiter.asf", "src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "usbTxWireArbiter.v", "src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "lineControlUpdate.v", "src/serialInterfaceEngine/lineControlUpdate.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "readUSBWireData.v", "src/serialInterfaceEngine/readUSBWireData.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "updateCRC5.v", "src/serialInterfaceEngine/updateCRC5.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "updateCRC16.v", "src/serialInterfaceEngine/updateCRC16.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbSerialInterfaceEngine.v", "src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "slaveController", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "USBSlaveControlBI.v", "src/slaveController/USBSlaveControlBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sctxportarbiter.asf", "src/slaveController/sctxportarbiter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sctxportarbiter.v", "src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "slavecontroller.asf", "src/slaveController/slavecontroller.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "slavecontroller.v", "src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "slaveDirectcontrol.asf", "src/slaveController/slaveDirectcontrol.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "slaveDirectcontrol.v", "src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "slaveGetpacket.asf", "src/slaveController/slaveGetpacket.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "slaveGetpacket.v", "src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "slaveSendpacket.asf", "src/slaveController/slaveSendpacket.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "slaveSendpacket.v", "src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "endpMux.v", "src/slaveController/endpMux.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "fifoMux.v", "src/slaveController/fifoMux.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "slaveRxStatusMonitor.v", "src/slaveController/slaveRxStatusMonitor.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbSlaveControl.v", "src/slaveController/usbSlaveControl.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "wrapper", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "usbHostSlave.v", "src/wrapper/usbHostSlave.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "TestBench", "", "");
+level2ID = theMenu.addChild(level1ID, "VTB", "usbHostSlave_TB.v", "src/TestBench/usbHostSlave_TB.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "DO", "usbHostSlave_TB_runtest.do", "src/TestBench/usbHostSlave_TB_runtest.do/index.htm", "");
+
+	
+}
+
+self.defaultStatus = "";	
+
+//-->
+</script>
+
+</HEAD>
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+if (self.name == 'menu') {
+	// Sometimes, Netscape will try to load this index inside the menu frame.  I haven't
+	// worked out why but this will detect that situation and reset the location property.
+	self.location.href = "menu.htm";
+} else {
+	initialise();
+	var thePage = pageFromSearch('./splash/info.htm', theMenu, true);
+	
+	if (floatingMode) {
+		self.document.writeln('<frameset cols="100%" rows="*,48" onUnload="unloadFloating();" onResize="defaultResizeHandler();">');
+		self.document.writeln('<frame name="menu" src="menu.htm" scrolling="auto" marginwidth="1" marginheight="1" APPLICATION="yes">');
+		self.document.writeln('<frame name="menuCntrl" src="menucntrl.htm" scrolling="no" marginwidth="0" marginheight="0" APPLICATION="yes">');
+		self.document.writeln('</frameset>');
+	} else {
+		self.document.writeln('<frameset cols="230,*" rows="100%">');
+		self.document.writeln('<frameset cols="100%" rows="30,*,48">');
+		self.document.writeln('<frame name="menuCntrl" src="menucntrl.htm"  scrolling="no" FrameBorder="no" marginwidth="0" marginheight="0"  APPLICATION="yes">');
+		self.document.writeln('<frame name="menu" src="menu.htm" scrolling="auto" noresize="noresize"  marginwidth="1" marginheight="1" APPLICATION="yes">');
+		self.document.writeln('<frame name="Aldec" src="struct/aldec.htm" scrolling="no" FrameBorder="no"  marginwidth="0" marginheight="0" noresize="noresize" APPLICATION="yes">');
+		
+		self.document.writeln('</frameset>');
+		self.document.writeln('<frame name="text" src="' + thePage +'" scrolling="auto" APPLICATION="yes">');
+		self.document.writeln('</frameset>');
+		self.document.writeln('</frameset>');
+	}
+}
+//-->
+</SCRIPT>
+<NOSCRIPT>
+<BODY BGCOLOR="#FFFFCC">
+<h1>Joust Outliner</h1>
+<P>Your browser does not support JavaScript (if you are using Netscape 3 or higher or Microsoft Internet
+Explorer 4 or higher you may have JavaScript turned off in your preferences), so this page,
+does not include site navigation features. If you use
+a JavaScript-capable browser, such as Microsoft <A HREF="http://microsoft.com/ie/ie.htm">Internet
+Explorer version 3.0</A> or <A HREF="http://www.netscape.com/comprod/mirror/">Netscape Navigator
+version 2.0</A>, you'll have a much more pleasant experience navigating around this site.</P>
+
+<P><I><B>Opera Users:</B> Although Opera 3.0 supports JavaScript, there is a bug in their implementation 
+which prevents the menu system on this site from working.  Opera 3.2 fixes the problem.</I></P>
+
+<P><I><B>Note:</B> There is a know bug in Netscape Navigator version 4.0.x which will cause you to see this message
+if you have the local cache turned off.</I></P>
+
+<P>If you have any problems with this site, please contact the Webmaster.</P>
+
+<P>Click <a HREF="index3.htm">here</a> to see the non-JavaScript version of this site.</P>
+
+<A HREF="robots.htm"> </A>
+</BODY>
+</NOSCRIPT>
+
+</HTML>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/menucntrl.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/menucntrl.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/menucntrl.htm	(revision 264)
@@ -0,0 +1,70 @@
+<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML//EN">
+<HTML>
+<HEAD>
+<TITLE>Aldec Menu Control</TITLE>
+<META NAME="ROBOTS" CONTENT="NOINDEX,NOFOLLOW">
+<script language="JavaScript">
+<!--
+if ((self.name != 'menuCntrl') & (self.location.protocol != "file:")) {
+	self.location = "index.htm";
+}
+if (parent.theBrowser) {
+	if (parent.theBrowser.canOnError) {window.onerror = parent.defOnError;}
+}
+
+
+
+/* Function that displays status bar messages. */
+function MM_displayStatusMsg(msgStr)  { //v3.0
+	status=msgStr; document.MM_returnValue = true;
+}
+
+function MM_findObj(n, d) { //v3.0
+  var p,i,x;  if(!d) d=document; if((p=n.indexOf("?"))>0&&parent.frames.length) {
+    d=parent.frames[n.substring(p+1)].document; n=n.substring(0,p);}
+  if(!(x=d[n])&&d.all) x=d.all[n]; for (i=0;!x&&i<d.forms.length;i++) x=d.forms[i][n];
+  for(i=0;!x&&d.layers&&i<d.layers.length;i++) x=MM_findObj(n,d.layers[i].document); return x;
+}
+
+/* Functions that swaps images. */
+function MM_swapImage() { //v3.0
+  var i,j=0,x,a=MM_swapImage.arguments; document.MM_sr=new Array; for(i=0;i<(a.length-2);i+=3)
+   if ((x=MM_findObj(a[i]))!=null){document.MM_sr[j++]=x; if(!x.oSrc) x.oSrc=x.src; x.src=a[i+2];}
+}
+function MM_swapImgRestore() { //v3.0
+  var i,x,a=document.MM_sr; for(i=0;a&&i<a.length&&(x=a[i])&&x.oSrc;i++) x.src=x.oSrc;
+}
+
+if (document.images) {
+  expandall_f2 = new Image(18 ,16); expandall_f2.src = "images/menucntrl/expandall_f2.gif";
+  expandall_f1 = new Image(18 ,16); expandall_f1.src = "images/menucntrl/expandall.gif";
+  collapseall_f2 = new Image(18 ,16); collapseall_f2.src = "images/menucntrl/collapseall_f2.gif";
+  collapseall_f1 = new Image(18 ,16); collapseall_f1.src = "images/menucntrl/collapseall.gif";
+  normalview_f2 = new Image(18 ,16); normalview_f2.src = "images/menucntrl/normalview_f2.gif";
+  normalview_f1 = new Image(18 ,16); normalview_f1.src = "images/menucntrl/normalview.gif";
+}
+
+//-->
+</script>
+</HEAD>
+<BODY bgcolor="white" marginwidth="0" marginheight="0" background="images/aldec.gif">
+
+<table border="0" cellpadding="0" cellspacing="0">
+  <tr>
+  <tr valign="top"><!-- row 1 -->
+   <td><img src="images/menucntrl/shim.gif" width="1" height="4" border="0"></td>
+   <td><img src="images/menucntrl/shim.gif" width="1" height="4" border="0"></td>
+  </tr>
+  <tr valign="top">
+   <td><img src="images/menucntrl/shim.gif" width="7" height="20" border="0"></td>
+   <td rowspan="1" colspan="1"><a href="javascript:parent.theMenu.openAll();" onMouseOut="MM_swapImgRestore();"  onMouseOver="MM_displayStatusMsg('Click to expand all folders in the outline.');MM_swapImage('expandall','','images/menucntrl/expandall_f2.gif',1);return document.MM_returnValue" ><img name="expandall" src="images/menucntrl/expandall.gif" width="18" height="16" border="0" alt="Expand All"></a></td>
+   <td rowspan="1" colspan="1"><a href="javascript:parent.theMenu.closeAll();" onMouseOut="MM_swapImgRestore();"  onMouseOver="MM_displayStatusMsg('Click to collapse all folders in the outline');MM_swapImage('collapseall','','images/menucntrl/collapseall_f2.gif',1);return document.MM_returnValue" ><img name="collapseall" src="images/menucntrl/collapseall.gif" width="18" height="16" border="0" alt="Collapse All"></a></td>
+   <td><a href="./splash/info.htm" target="text" onMouseOut="MM_swapImgRestore();"  onMouseOver="MM_displayStatusMsg('Click to go to the Home page.');MM_swapImage('home','','images/menucntrl/home_f2.gif',1);return document.MM_returnValue" ><img name="home" src="images/menucntrl/home.gif" width="18" height="16" border="0" alt="Home"></a></td>
+  </tr>
+</tr>
+</table>
+
+</BODY>
+</HTML>
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/menucntrl.htm
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Added: svn:executable
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+*
\ No newline at end of property
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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/TestBench/usbHostSlave_TB.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/TestBench/usbHostSlave_TB.v/index.htm	(revision 264)
@@ -0,0 +1,111 @@
+<html>
+<head>
+<title>usbHostSlave_TB.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//--------------------------------------------------------------------------------------------------</span>
+<span id=t_com>//</span>
+<span id=t_com>// Title       : usbHostSlave_tb</span>
+<span id=t_com>// Design      : usbhostslave</span>
+<span id=t_com>// Author      : Steve</span>
+<span id=t_com>// Company     : Base2Designs</span>
+<span id=t_com>//</span>
+<span id=t_com>//-------------------------------------------------------------------------------------------------</span>
+<span id=t_com>//</span>
+<span id=t_com>// File        : usbHostSlave_TB.v</span>
+<span id=t_com>// Generated   : Thu Jun 10 22:02:35 2004</span>
+<span id=t_com>// From        : usbHostSlave_TB_settings.txt</span>
+<span id=t_com>// By          : tb_verilog.pl ver. ver 1.2s</span>
+<span id=t_com>//</span>
+<span id=t_com>//-------------------------------------------------------------------------------------------------</span>
+<span id=t_com>//</span>
+<span id=t_com>// Description : </span>
+<span id=t_com>//</span>
+<span id=t_com>//-------------------------------------------------------------------------------------------------</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ps</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_kwd>module</span> <span id=t_idt>usbHostSlave_tb</span>;
+<span id=t_com>//Parameters declaration: </span>
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>HOST_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>HOST_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>HOST_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>HOST_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP0_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP0_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP0_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP0_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP1_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP1_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP1_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP1_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP2_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP2_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP2_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP2_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP3_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP3_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP3_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP3_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+
+<span id=t_com>//Internal signals declarations:</span>
+<span id=t_kwd>reg</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>address_i</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>data_i</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>data_o</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>ack_o</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSOFSentIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostConnEventIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostResumeIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostTransDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveSOFRxedIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveResetEventIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveResumeIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveTransDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveNAKSentIntOut</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataInTick</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataOutTick</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireCtrlOut</span>;
+
+
+
+<span id=t_com>// Unit Under Test port map</span>
+  <span id=t_idt>usbHostSlave</span> <span id=t_idt>UUT</span> (
+   .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+   .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+   .<span id=t_idt>address_i</span>(<span id=t_idt>address_i</span>),
+   .<span id=t_idt>data_i</span>(<span id=t_idt>data_i</span>),
+   .<span id=t_idt>data_o</span>(<span id=t_idt>data_o</span>),
+   .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>),
+   .<span id=t_idt>strobe_i</span>(<span id=t_idt>strobe_i</span>),
+   .<span id=t_idt>ack_o</span>(<span id=t_idt>ack_o</span>),
+   .<span id=t_idt>hostSOFSentIntOut</span>(<span id=t_idt>hostSOFSentIntOut</span>),
+   .<span id=t_idt>hostConnEventIntOut</span>(<span id=t_idt>hostConnEventIntOut</span>),
+   .<span id=t_idt>hostResumeIntOut</span>(<span id=t_idt>hostResumeIntOut</span>),
+   .<span id=t_idt>hostTransDoneIntOut</span>(<span id=t_idt>hostTransDoneIntOut</span>),
+   .<span id=t_idt>slaveSOFRxedIntOut</span>(<span id=t_idt>slaveSOFRxedIntOut</span>),
+   .<span id=t_idt>slaveResetEventIntOut</span>(<span id=t_idt>slaveResetEventIntOut</span>),
+   .<span id=t_idt>slaveResumeIntOut</span>(<span id=t_idt>slaveResumeIntOut</span>),
+   .<span id=t_idt>slaveTransDoneIntOut</span>(<span id=t_idt>slaveTransDoneIntOut</span>),
+    .<span id=t_idt>slaveNAKSentIntOut</span>(<span id=t_idt>slaveNAKSentIntOut</span>),
+   .<span id=t_idt>USBWireDataIn</span>(<span id=t_idt>USBWireDataIn</span>),
+   .<span id=t_idt>USBWireDataInTick</span>(<span id=t_idt>USBWireDataInTick</span>),
+   .<span id=t_idt>USBWireDataOut</span>(<span id=t_idt>USBWireDataOut</span>),
+   .<span id=t_idt>USBWireDataOutTick</span>(<span id=t_idt>USBWireDataOutTick</span>),
+   .<span id=t_idt>USBWireCtrlOut</span>(<span id=t_idt>USBWireCtrlOut</span>));
+
+<span id=t_kwd>initial</span>
+  <span id=t_sys>$monitor</span>(<span id=t_sys>$realtime</span>,,<span id=t_cns>"ps %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h "</span>,<span id=t_idt>clk</span>,<span id=t_idt>rst</span>,<span id=t_idt>address_i</span>,<span id=t_idt>data_i</span>,<span id=t_idt>data_o</span>,<span id=t_idt>writeEn</span>,<span id=t_idt>strobe_i</span>,<span id=t_idt>ack_o</span>,<span id=t_idt>hostSOFSentIntOut</span>,<span id=t_idt>hostConnEventIntOut</span>,<span id=t_idt>hostResumeIntOut</span>,<span id=t_idt>hostTransDoneIntOut</span>,<span id=t_idt>slaveSOFRxedIntOut</span>,<span id=t_idt>slaveResetEventIntOut</span>,<span id=t_idt>slaveResumeIntOut</span>,<span id=t_idt>slaveTransDoneIntOut</span>,<span id=t_idt>USBWireDataIn</span>,<span id=t_idt>USBWireDataInTick</span>,<span id=t_idt>USBWireDataOut</span>,<span id=t_idt>USBWireDataOutTick</span>,<span id=t_idt>USBWireCtrlOut</span>);
+<span id=t_kwd>endmodule</span>
+
+</pre>
+</body>
+</html>

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+*
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+*
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+application/octet-stream
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+application/octet-stream
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+*
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+application/octet-stream
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+*
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+*
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+application/octet-stream
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+*
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+application/octet-stream
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/firstover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/lastover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/lastover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/nextover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/nextover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/prevover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/prevover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/upover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/images/wfm/upover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/menu.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/menu.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/menu.htm	(revision 264)
@@ -0,0 +1,209 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<HTML>
+<HEAD>
+<TITLE>The Joust Outliner - The Menu</TITLE>
+<META NAME="ROBOTS" CONTENT="NOINDEX,NOFOLLOW">
+
+<STYLE ID="JoustStyles" TYPE="text/css">
+<!--
+	.menuItem {position:absolute; visibility:hidden; left:0px;}
+	.menuItem BR { clear: both; }
+	.node { color: black;
+		font-family : "Helvetica", "Arial", "MS Sans Serif", sans-serif;
+		font-size : 9pt;}
+	.node A:link { color: black; text-decoration: none; }
+	.node A:visited { color: black; text-decoration: none; }
+	.node A:active { color: black; text-decoration: none; }
+	.node A:hover { color: black; text-decoration: none; }
+	.leaf { color: black;
+		font-family : "Helvetica", "Arial", "MS Sans Serif", sans-serif;
+		font-size : 9pt;}
+	.leaf A:link { color: black; text-decoration: none;}
+	.leaf A:visited { color: black; text-decoration: none; }
+	.leaf A:active { color: black; text-decoration: none; }
+	.leaf A:hover { color: black; text-decoration: none; }
+	.nolink { color: #808080;
+		font-family : "Helvetica", "Arial", "MS Sans Serif", sans-serif;
+		font-size : 9pt;}
+	.nolink A:link { color: #808080; text-decoration: none;}
+	.nolink A:visited { color: #808080; text-decoration: none; }
+	.nolink A:active { color: #808080; text-decoration: none; }
+	.nolink A:hover { color: #808080; text-decoration: none; }
+-->
+</STYLE>
+
+<!--
+Joust Outliner Version 2.5.4
+(c) Copyright 1996-2001, MITEM (Europe) Ltd. All rights reserved.
+This code may be freely copied and distributed provided that it is accompanied by this 
+header.  For full details of the Joust license, as well as documentation and help, go 
+to http://www.ivanpeters.com/.
+
+Do not modify anything between here and the "End of Joust" marker unless you know what you
+are doing.  
+-->
+<script language="JavaScript">
+<!--  
+var theMenuRef = "parent.theMenu";
+var theMenu = eval(theMenuRef);
+var theBrowser = parent.theBrowser;
+var belowMenu = null;
+var menuStart = 0;
+
+if (parent.theBrowser) {
+	if (parent.theBrowser.canOnError) {window.onerror = parent.defOnError;}
+}
+
+if (theMenu) {
+	theMenu.amBusy = true;
+	if (theBrowser.hasDHTML) {
+		if (document.all) {
+			with (document.styleSheets["JoustStyles"]) {
+				addRule ("#menuTop", "position:absolute");
+				addRule ("#menuBottom", "position:absolute");
+				addRule ("#menuBottom", "visibility:hidden");
+				addRule ("#statusMsgDiv", "position:absolute");
+			}
+		} else {
+			if (document.layers) {
+				document.ids.menuTop.position = "absolute";
+				document.ids.menuBottom.position = "absolute";
+				document.ids.menuBottom.visibility = "hidden";
+				document.ids.statusMsgDiv.position = "absolute";
+			} else {
+				if (theBrowser.hasW3CDOM) {
+					var styleSheetElement = document.styleSheets[0];
+    				var styleSheetLength = styleSheetElement.cssRules.length;
+					styleSheetElement.insertRule("#menuTop { position:absolute } ", styleSheetLength++);
+					styleSheetElement.insertRule("#menuBottom { position:absolute } ", styleSheetLength++);
+					styleSheetElement.insertRule("#menuBottom { visibility:hidden } ", styleSheetLength++);
+					styleSheetElement.insertRule("#statusMsgDiv { position:absolute } ", styleSheetLength++);
+				}
+			}
+		}
+	}
+}
+function getDHTMLObj(objName) {
+	if (theBrowser.hasW3CDOM) {
+		return document.getElementById(objName).style;
+	} else {
+		return eval('document' + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLStyleObj);
+	}
+}
+function getDHTMLObjHeight(objName) {
+	if (theBrowser.hasW3CDOM) {
+		return document.getElementById(objName).offsetHeight;
+	} else {
+		return eval('document' + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLDivHeight);
+	}
+}
+function myVoid() { ; }
+function setMenuHeight(theHeight) {
+	getDHTMLObj('menuBottom').top = theHeight;
+}
+function drawStatusMsg() {
+	if (document.layers) {
+		document.ids.statusMsgDiv.top = menuStart;
+	} else{
+		if (document.all) {
+			document.styleSheets["JoustStyles"].addRule ("#statusMsgDiv", "top:" + menuStart);
+		}
+	}
+	document.writeln('<DIV ID="statusMsgDiv"><CENTER>Building Menu...</CENTER></DIV>');
+}
+function drawLimitMarker() {
+	var b = theBrowser;
+	if (theMenu && b.hasDHTML && b.needLM) {
+		var limitPos = theMenu.maxHeight + menuStart + getDHTMLObjHeight('menuBottom');
+		if (b.code == 'NS') {
+			document.ids.limitMarker.position = "absolute";
+			document.ids.limitMarker.visibility = "hidden";
+			document.ids.limitMarker.top = limitPos;
+		}
+		if (b.code == 'MSIE') {
+			with (document.styleSheets["JoustStyles"]) {
+				addRule ("#limitMarker", "position:absolute");
+				addRule ("#limitMarker", "visibility:hidden");
+				addRule ("#limitMarker", "top:" + limitPos + "px");
+			}
+		}
+		document.writeln('<DIV ID="limitMarker">&nbsp;</DIV>');
+	}
+}
+function setTop() {
+	if (theMenu && theBrowser.hasDHTML) {
+		if (getDHTMLObj('menuTop')) {
+			drawStatusMsg();
+			menuStart = getDHTMLObjHeight("menuTop");
+		} else {
+			theBrowser.hasDHTML = false;
+		}
+	}
+}
+function setBottom() {
+	if (theMenu) {
+		if (theBrowser.hasDHTML) {
+			var mb = getDHTMLObj('menuBottom');
+			if (mb) {
+				drawLimitMarker();
+				getDHTMLObj("statusMsgDiv").visibility = 'hidden';
+				menuStart = getDHTMLObjHeight("menuTop");
+				theMenu.refreshDHTML();
+				if (theMenu.autoScrolling) {theMenu.scrollTo(theMenu.lastPMClicked);}
+				mb.visibility = 'visible';
+			} else {
+				theBrowser.hasDHTML = false;
+				self.location.reload();
+			}
+		}
+		theMenu.amBusy = false;
+	}
+}
+
+function frameResized() {if (theBrowser.hasDHTML) {theMenu.refreshDHTML();}}
+
+//	############################   End of Joust   ############################
+
+if (self.name != 'menu') { self.location.href = 'index.htm'; }
+//-->
+</script>
+</HEAD>
+<BODY bgcolor="white" LINK="#000000" marginwidth="1" marginheight="1" onResize="frameResized();" background="images/aldec.gif" bgproperties="FIXED">
+
+<DIV ID="menuTop">
+<!-- Place anything you want to appear before the menu between these DIV tags. -->
+</DIV>
+
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+setTop();
+//-->
+</SCRIPT>
+
+<!-- Set up any font's, colours, etc. that should apply to the menu here -->
+<FONT FACE="GENEVA, ARIAL, MS SANS SERIF, SANS-SERIF" SIZE="1">
+
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+if (theMenu) {
+	parent.DrawMenu(theMenu);
+}
+//-->
+</SCRIPT>
+
+<!-- Close any tags you set up for the menu here -->
+</FONT>
+
+<DIV ID="menuBottom">
+<!-- Place anything you want to appear after the menu between these DIV tags. -->
+&nbsp;
+</DIV>
+
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+setBottom();
+//-->
+</SCRIPT>
+
+</BODY>
+</HTML>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/menu.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/splash/info.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/splash/info.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/splash/info.htm	(revision 264)
@@ -0,0 +1,22 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<title>Active-HDL HTML Export</TITLE>
+</head>
+<body
+		bgcolor="#C0C0C0"
+		background="./../images/aldec.gif">
+
+<div align="center">
+<h1><a name="top">Active-HDL HTML Export</a></h1>
+<hr>
+<img src="avhdlregular.bmp" width="300" height="268" 
+		ALT="Aldec logo"   
+		hspace="0" vspace="0" border="0" align="middle">
+<hr>
+<h4>Copyright&copy 2004 ALDEC, Inc., Henderson, NV USA.<br> 
+All Rights Reserved.</h4><br>
+<h4>Aldec homepage <A HREF="http://www.aldec.com/">http://www.aldec.com</A></h4>
+</div>
+</body>
+</html>
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/splash/info.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/splash/AVhdlRegular.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/splash/AVhdlRegular.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/TestBench/usbHostSlave_TB_runtest.do/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/TestBench/usbHostSlave_TB_runtest.do/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/TestBench/usbHostSlave_TB_runtest.do/index.htm	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<head>
+<title>usbHostSlave_TB_runtest.do</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_kwd>SetActiveLib</span> -work
+<span id=t_com>#Compiling UUT module design files</span>
+
+<span id=t_kwd>comp</span> -include "$DSN\src\TestBench\usbHostSlave_TB.v"
+<span id=t_kwd>asim</span> usbHostSlave_tb
+
+<span id=t_kwd>wave</span>
+<span id=t_kwd>wave</span> -noreg clk
+<span id=t_kwd>wave</span> -noreg rst
+<span id=t_kwd>wave</span> -noreg address_i
+<span id=t_kwd>wave</span> -noreg data_i
+<span id=t_kwd>wave</span> -noreg data_o
+<span id=t_kwd>wave</span> -noreg writeEn
+<span id=t_kwd>wave</span> -noreg strobe_i
+<span id=t_kwd>wave</span> -noreg ack_o
+<span id=t_kwd>wave</span> -noreg hostSOFSentIntOut
+<span id=t_kwd>wave</span> -noreg hostConnEventIntOut
+<span id=t_kwd>wave</span> -noreg hostResumeIntOut
+<span id=t_kwd>wave</span> -noreg hostTransDoneIntOut
+<span id=t_kwd>wave</span> -noreg slaveSOFRxedIntOut
+<span id=t_kwd>wave</span> -noreg slaveResetEventIntOut
+<span id=t_kwd>wave</span> -noreg slaveResumeIntOut
+<span id=t_kwd>wave</span> -noreg slaveTransDoneIntOut
+<span id=t_kwd>wave</span> -noreg USBWireDataIn
+<span id=t_kwd>wave</span> -noreg USBWireDataInTick
+<span id=t_kwd>wave</span> -noreg USBWireDataOut
+<span id=t_kwd>wave</span> -noreg USBWireDataOutTick
+<span id=t_kwd>wave</span> -noreg USBWireCtrlOut
+
+<span id=t_kwd>run</span>
+
+<span id=t_com>#End simulation macro</span>
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/TestBench/usbHostSlave_TB_runtest.do/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/TxFifo.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/TxFifo.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/TxFifo.v/index.htm	(revision 264)
@@ -0,0 +1,140 @@
+<html>
+<head>
+<title>TxFifo.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// TxFifo.v                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536</span>
+<span id=t_com>////  fifo write access via bus interface, fifo read access is direct</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:30 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>TxFifo</span>(
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>, 
+  <span id=t_idt>fifoREn</span>, 
+  <span id=t_idt>fifoEmpty</span>,
+  <span id=t_idt>busAddress</span>, 
+  <span id=t_idt>busWriteEn</span>, 
+  <span id=t_idt>busStrobe_i</span>,
+  <span id=t_idt>busFifoSelect</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>,
+  <span id=t_idt>fifoDataOut</span> ); 
+  <span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>fifoREn</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busWriteEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>busFifoSelect</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataOut</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fifoREn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busWriteEn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>busFifoSelect</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataOut</span>;
+
+<span id=t_com>//internal wires and regs</span>
+<span id=t_kwd>wire</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoFull</span>;
+
+<span id=t_idt>fifoRTL</span> #(<span id=t_cns>8</span>, <span id=t_idt>FIFO_DEPTH</span>, <span id=t_idt>ADDR_WIDTH</span>) <span id=t_idt>u_fifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>fifoDataOut</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>fifoWEn</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>fifoREn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>fifoFull</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>fifoEmpty</span>), 
+  .<span id=t_idt>forceEmpty</span>(<span id=t_idt>forceEmpty</span>), 
+  .<span id=t_idt>numElementsInFifo</span>(<span id=t_idt>numElementsInFifo</span>) );
+  
+<span id=t_idt>TxfifoBI</span> <span id=t_idt>u_TxfifoBI</span>(
+  .<span id=t_idt>address</span>(<span id=t_idt>busAddress</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>busWriteEn</span>), 
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>busStrobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoSelect</span>(<span id=t_idt>busFifoSelect</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>busDataOut</span>),
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>fifoWEn</span>),
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>fifoFull</span>),
+  .<span id=t_idt>forceEmpty</span>(<span id=t_idt>forceEmpty</span>),
+  .<span id=t_idt>numElementsInFifo</span>(<span id=t_idt>numElementsInFifo</span>)
+  );
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/TxFifo.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/fifoRTL.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/fifoRTL.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/fifoRTL.v/index.htm	(revision 264)
@@ -0,0 +1,158 @@
+<html>
+<head>
+<title>fifoRTL.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// fifoRTL.v                                                    ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////  parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH</span>
+<span id=t_com>////  No protection against over runs and under runs.</span>
+<span id=t_com>////  User must check full and empty flags before accessing fifo</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:28 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>fifoRTL</span>(<span id=t_idt>clk</span>, <span id=t_idt>rst</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>fifoWEn</span>, <span id=t_idt>fifoREn</span>, <span id=t_idt>fifoFull</span>, <span id=t_idt>fifoEmpty</span>, <span id=t_idt>forceEmpty</span>, <span id=t_idt>numElementsInFifo</span>);
+<span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_WIDTH</span> = <span id=t_cns>8</span>;
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>output</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>]<span id=t_idt>numElementsInFifo</span>; <span id=t_com>//note that this implies a max fifo depth of 65536</span>
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>reg</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>15</span>:<span id=t_cns>0</span>]<span id=t_idt>numElementsInFifo</span>;
+
+
+<span id=t_com>// local registers</span>
+<span id=t_kwd>reg</span>  [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferInIndex</span>;
+<span id=t_kwd>reg</span>  [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferOutIndex</span>;
+<span id=t_kwd>reg</span>  [<span id=t_idt>ADDR_WIDTH</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferCnt</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>fifoREnDelayed</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromMem</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span> || <span id=t_idt>forceEmpty</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>bufferCnt</span> &lt;= <span id=t_cns>0</span>;
+    <span id=t_idt>fifoFull</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_idt>fifoEmpty</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_cns>0</span>;
+   <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_cns>0</span>;
+    <span id=t_idt>fifoREnDelayed</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span>
+    <span id=t_kwd>begin</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>fifoREn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREnDelayed</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromMem</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>fifoREnDelayed</span> &lt;= <span id=t_idt>fifoREn</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>fifoWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREn</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> + <span id=t_cns>1</span>;
+        <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_idt>bufferInIndex</span> + <span id=t_cns>1</span>;
+      <span id=t_kwd>end</span> 
+      <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>fifoWEn</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>fifoREn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREnDelayed</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> - <span id=t_cns>1</span>;
+        <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_idt>bufferOutIndex</span> + <span id=t_cns>1</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>fifoWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREnDelayed</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_idt>bufferOutIndex</span> + <span id=t_cns>1</span>;
+        <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_idt>bufferInIndex</span> + <span id=t_cns>1</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span>[<span id=t_idt>ADDR_WIDTH</span>] == <span id=t_cns>1'b1</span>)
+        <span id=t_idt>fifoFull</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>else</span>
+        <span id=t_idt>fifoFull</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_kwd>if</span> (|<span id=t_idt>bufferCnt</span> == <span id=t_cns>1'b0</span>) 
+        <span id=t_idt>fifoEmpty</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>else</span>
+        <span id=t_idt>fifoEmpty</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//pad bufferCnt with leading zeroes</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>bufferCnt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>numElementsInFifo</span> &lt;= { {<span id=t_cns>16</span>-<span id=t_idt>ADDR_WIDTH</span>+<span id=t_cns>1</span>{<span id=t_cns>1'b0</span>}}, <span id=t_idt>bufferCnt</span> };
+<span id=t_kwd>end</span>
+
+<span id=t_idt>fifoMem</span> #(<span id=t_idt>FIFO_WIDTH</span>, <span id=t_idt>FIFO_DEPTH</span>, <span id=t_idt>ADDR_WIDTH</span>)  <span id=t_idt>u_fifoMem</span> (
+  .<span id=t_idt>addrIn</span>(<span id=t_idt>bufferInIndex</span>),
+  .<span id=t_idt>addrOut</span>(<span id=t_idt>bufferOutIndex</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>dataIn</span>),
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>fifoWEn</span>),
+  .<span id=t_idt>readEn</span>(<span id=t_idt>fifoREn</span>),
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataFromMem</span>));
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/fifoRTL.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/RxFifoBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/RxFifoBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/RxFifoBI.v/index.htm	(revision 264)
@@ -0,0 +1,143 @@
+<html>
+<head>
+<title>RxFifoBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// RxfifoBI.v                                                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:29 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"wishBoneBus_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>RxfifoBI</span> (
+  <span id=t_idt>address</span>, 
+  <span id=t_idt>writeEn</span>, 
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>, 
+  <span id=t_idt>fifoSelect</span>,
+  <span id=t_idt>fifoDataIn</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>,
+  <span id=t_idt>fifoREn</span>,
+  <span id=t_idt>fifoEmpty</span>,
+  <span id=t_idt>forceEmpty</span>,
+  <span id=t_idt>numElementsInFifo</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>output</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoSelect</span>;
+
+
+<span id=t_kwd>wire</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoSelect</span>;
+
+
+<span id=t_com>//sync write</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoSelect</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+  <span id=t_idt>address</span> == `<span id=t_idt>FIFO_CONTROL_REG</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>busDataIn</span>[<span id=t_cns>0</span>] == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>forceEmpty</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+    <span id=t_idt>forceEmpty</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span> <span id=t_idt>fifoDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>numElementsInFifo</span> <span id=t_kwd>or</span> <span id=t_idt>fifoEmpty</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+      `<span id=t_idt>FIFO_DATA_REG</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>fifoDataIn</span>;
+      `<span id=t_idt>FIFO_STATUS_REG</span> : <span id=t_idt>busDataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>fifoEmpty</span>};
+      `<span id=t_idt>FIFO_DATA_COUNT_MSB</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>numElementsInFifo</span>[<span id=t_cns>15</span>:<span id=t_cns>8</span>];
+      `<span id=t_idt>FIFO_DATA_COUNT_LSB</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>numElementsInFifo</span>[<span id=t_cns>7</span>:<span id=t_cns>0</span>];
+      <span id=t_kwd>default</span>: <span id=t_idt>busDataOut</span> &lt;= <span id=t_cns>8'h00</span>; 
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//generate fifo read strobe</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span> <span id=t_idt>writeEn</span> <span id=t_kwd>or</span> <span id=t_idt>strobe_i</span> <span id=t_kwd>or</span> <span id=t_idt>fifoSelect</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>address</span> == `<span id=t_idt>FIFO_DATA_REG</span> &amp;&amp;   <span id=t_idt>writeEn</span> == <span id=t_cns>1'b0</span> &amp;&amp; 
+  <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp;   <span id=t_idt>fifoSelect</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>fifoREn</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+    <span id=t_idt>fifoREn</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/RxFifoBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/fifoMem.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/fifoMem.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/fifoMem.v/index.htm	(revision 264)
@@ -0,0 +1,114 @@
+<html>
+<head>
+<title>fifoMem.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// fifoMem.v                                                    ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:28 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>fifoMem</span>( <span id=t_idt>addrIn</span>, <span id=t_idt>addrOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>writeEn</span>, <span id=t_idt>readEn</span>, <span id=t_idt>dataOut</span>);
+  <span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_WIDTH</span> = <span id=t_cns>8</span>;
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>output</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>readEn</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrIn</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrOut</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>readEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrOut</span>;
+
+
+<span id=t_com>/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(</span>
+<span id=t_com>  // Generic synchronous dual-port RAM interface</span>
+<span id=t_com>  .rclk(clk), </span>
+<span id=t_com>  .rrst(1'b0), </span>
+<span id=t_com>  .rce(1'b1), </span>
+<span id=t_com>  .oe(readEn), </span>
+<span id=t_com>  .raddr(addrOut), </span>
+<span id=t_com>  .do(dataOut),</span>
+<span id=t_com>  .wclk(clk), </span>
+<span id=t_com>  .wrst(1'b0), </span>
+<span id=t_com>  .wce(1'b1),</span>
+<span id=t_com>  .we(writeEn), </span>
+<span id=t_com>  .waddr(addrIn), </span>
+<span id=t_com>  .di(dataIn)</span>
+<span id=t_com>); */</span>
+
+
+ <span id=t_idt>simFifoMem</span> #(<span id=t_idt>FIFO_WIDTH</span>, <span id=t_idt>FIFO_DEPTH</span>, <span id=t_idt>ADDR_WIDTH</span>)  <span id=t_idt>u_simFifoMem</span> (
+  .<span id=t_idt>addrIn</span>(<span id=t_idt>addrIn</span>),
+  .<span id=t_idt>addrOut</span>(<span id=t_idt>addrOut</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>dataIn</span>),
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>),
+  .<span id=t_idt>readEn</span>(<span id=t_idt>readEn</span>),
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataOut</span>));  
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/fifoMem.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/RxFifo.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/RxFifo.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/RxFifo.v/index.htm	(revision 264)
@@ -0,0 +1,142 @@
+<html>
+<head>
+<title>RxFifo.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// RxFifo.v                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536</span>
+<span id=t_com>////  fifo read access via bus interface, fifo write access is direct</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:29 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>RxFifo</span>(
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>, 
+  <span id=t_idt>fifoWEn</span>, 
+  <span id=t_idt>fifoFull</span>,
+  <span id=t_idt>busAddress</span>, 
+  <span id=t_idt>busWriteEn</span>, 
+  <span id=t_idt>busStrobe_i</span>,
+  <span id=t_idt>busFifoSelect</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>,
+  <span id=t_idt>fifoDataIn</span>  );
+  <span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busWriteEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>busFifoSelect</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fifoWEn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busWriteEn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>busFifoSelect</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataIn</span>;
+
+<span id=t_com>//internal wires and regs</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromFifoToBus</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoEmpty</span>;
+
+<span id=t_idt>fifoRTL</span> #(<span id=t_cns>8</span>, <span id=t_idt>FIFO_DEPTH</span>, <span id=t_idt>ADDR_WIDTH</span>) <span id=t_idt>u_fifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>fifoDataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataFromFifoToBus</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>fifoWEn</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>fifoREn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>fifoFull</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>fifoEmpty</span>), 
+  .<span id=t_idt>forceEmpty</span>(<span id=t_idt>forceEmpty</span>), 
+  .<span id=t_idt>numElementsInFifo</span>(<span id=t_idt>numElementsInFifo</span>) );
+  
+<span id=t_idt>RxfifoBI</span> <span id=t_idt>u_RxfifoBI</span>(
+  .<span id=t_idt>address</span>(<span id=t_idt>busAddress</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>busWriteEn</span>), 
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>busStrobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoSelect</span>(<span id=t_idt>busFifoSelect</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>dataFromFifoToBus</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>busDataOut</span>),
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>fifoREn</span>),
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>fifoEmpty</span>),
+  .<span id=t_idt>forceEmpty</span>(<span id=t_idt>forceEmpty</span>),
+  .<span id=t_idt>numElementsInFifo</span>(<span id=t_idt>numElementsInFifo</span>)
+  );
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/RxFifo.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/TxFifoBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/TxFifoBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/TxFifoBI.v/index.htm	(revision 264)
@@ -0,0 +1,135 @@
+<html>
+<head>
+<title>TxFifoBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// TxfifoBI.v                                                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:30 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"wishBoneBus_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>TxfifoBI</span> (
+  <span id=t_idt>address</span>, <span id=t_idt>writeEn</span>, <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>, <span id=t_idt>fifoSelect</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>,
+  <span id=t_idt>fifoWEn</span>,
+  <span id=t_idt>fifoFull</span>,
+  <span id=t_idt>forceEmpty</span>,
+  <span id=t_idt>numElementsInFifo</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>output</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoSelect</span>;
+
+
+<span id=t_kwd>wire</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoSelect</span>;
+
+
+<span id=t_com>//sync write</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoSelect</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+  <span id=t_idt>address</span> == `<span id=t_idt>FIFO_CONTROL_REG</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>busDataIn</span>[<span id=t_cns>0</span>] == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>forceEmpty</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+    <span id=t_idt>forceEmpty</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span> <span id=t_idt>fifoFull</span> <span id=t_kwd>or</span> <span id=t_idt>numElementsInFifo</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+      `<span id=t_idt>FIFO_STATUS_REG</span> : <span id=t_idt>busDataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>fifoFull</span>};
+      `<span id=t_idt>FIFO_DATA_COUNT_MSB</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>numElementsInFifo</span>[<span id=t_cns>15</span>:<span id=t_cns>8</span>];
+      `<span id=t_idt>FIFO_DATA_COUNT_LSB</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>numElementsInFifo</span>[<span id=t_cns>7</span>:<span id=t_cns>0</span>];
+      <span id=t_kwd>default</span>: <span id=t_idt>busDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//generate fifo write strobe</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span> <span id=t_idt>writeEn</span> <span id=t_kwd>or</span> <span id=t_idt>strobe_i</span> <span id=t_kwd>or</span> <span id=t_idt>fifoSelect</span> <span id=t_kwd>or</span> <span id=t_idt>busDataIn</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>address</span> == `<span id=t_idt>FIFO_DATA_REG</span> &amp;&amp;   <span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+  <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp;   <span id=t_idt>fifoSelect</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>fifoWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+    <span id=t_idt>fifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/TxFifoBI.v/index.htm
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="directcontrol" alt="directcontrol"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram1.html
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+*
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===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/directcontrol.png
___________________________________________________________________
Added: svn:executable
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+*
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Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/directcontrol_IDLE.png
===================================================================
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svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/directcontrol_IDLE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index78.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index78.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index78.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar78.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram78.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index78.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar78.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar78.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar78.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 78 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./directcontrol_DRCT_CNTL.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./directcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar78.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm	(revision 264)
@@ -0,0 +1,276 @@
+<html>
+<head>
+<title>USBHostControlBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBHostControlBI.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+ 
+<span id=t_kwd>module</span> <span id=t_idt>USBHostControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>SOFSentIntOut</span>, <span id=t_idt>connEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>TxTransTypeReg</span>, <span id=t_idt>TxSOFEnableReg</span>,
+  <span id=t_idt>TxAddrReg</span>, <span id=t_idt>TxEndPReg</span>, <span id=t_idt>frameNumIn</span>, 
+  <span id=t_idt>RxPktStatusIn</span>, <span id=t_idt>RxPIDIn</span>,
+  <span id=t_idt>connectStateIn</span>,
+  <span id=t_idt>SOFSentIn</span>, <span id=t_idt>connEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>,
+  <span id=t_idt>hostControlSelect</span>,
+  <span id=t_idt>clrTransReq</span>,
+  <span id=t_idt>preambleEn</span>,
+  <span id=t_idt>SOFSync</span>,
+  <span id=t_idt>TxLineState</span>,
+  <span id=t_idt>LineDirectControlEn</span>,
+  <span id=t_idt>fullSpeedPol</span>, 
+  <span id=t_idt>fullSpeedRate</span>,
+  <span id=t_idt>transReq</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>output</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transReq</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transReq</span>;
+
+<span id=t_com>//internal wire and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineControlReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrConnEvtReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>setTransReq</span>;
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResInReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>setTransReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>hostControlSelect</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>preambleEn</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>SOFSync</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>setTransReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>TxTransTypeReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>TxLineControlReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>TxSOFEnableReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>TxAddrReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>TxEndPReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_kwd>begin</span>
+        <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>clrResInReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>interruptMaskReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+   <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//interrupt control</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>SOFSentIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>connEventIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrConnEvtReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b0</span>;  
+
+  <span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//mask interrupts</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSentInt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>transDoneIntOut</span> &lt;= <span id=t_idt>transDoneInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>];
+  <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_idt>resumeInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>];
+  <span id=t_idt>connEventIntOut</span> &lt;= <span id=t_idt>connEventInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>CONNECTION_EVENT_BIT</span>];
+  <span id=t_idt>SOFSentIntOut</span> &lt;= <span id=t_idt>SOFSentInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_SENT_BIT</span>];
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//transaction request set/clear</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>setTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//break out control signals</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>TxLineState</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>TX_LINE_STATE_LSBIT</span>];
+  <span id=t_idt>LineDirectControlEn</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>DIRECT_CONTROL_BIT</span>];
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span>]; 
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span>];
+<span id=t_kwd>end</span>
+  
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxSOFEnableReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndPReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNumIn</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SOFSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span>
+  <span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>RxPktStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxPIDIn</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>preambleEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSync</span> <span id=t_kwd>or</span> <span id=t_idt>transReq</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>preambleEn</span>, <span id=t_idt>SOFSync</span>, <span id=t_idt>transReq</span>} ;
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>TxTransTypeReg</span>};
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>TxLineControlReg</span>};
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>TxSOFEnableReg</span>};
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxAddrReg</span>};
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>TxEndPReg</span>};
+     `<span id=t_idt>FRAME_NUM_MSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>frameNumIn</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>];
+     `<span id=t_idt>FRAME_NUM_LSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNumIn</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]};
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>SOFSentInt</span>, <span id=t_idt>connEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>};
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>interruptMaskReg</span>};
+     `<span id=t_idt>RX_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>RxPktStatusIn</span>;
+     `<span id=t_idt>RX_PID_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'b0000</span>, <span id=t_idt>RxPIDIn</span>};
+     `<span id=t_idt>RX_CONNECT_STATE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>};
+      <span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram78.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram78.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram78.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="directcontrol DRCT_CNTL" alt="directcontrol DRCT_CNTL"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram78.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram33.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram33.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="getpacket PROC_PKT" alt="getpacket PROC_PKT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/simFifoMem.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/simFifoMem.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/simFifoMem.v/index.htm	(revision 264)
@@ -0,0 +1,101 @@
+<html>
+<head>
+<title>simFifoMem.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// simFifoMem.v                                                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:29 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>simFifoMem</span>(  <span id=t_idt>addrIn</span>, <span id=t_idt>addrOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>writeEn</span>, <span id=t_idt>readEn</span>, <span id=t_idt>dataOut</span>);
+  <span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_WIDTH</span> = <span id=t_cns>8</span>;
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>output</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>readEn</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrIn</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrOut</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>reg</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>readEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrOut</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>buffer</span> [<span id=t_cns>0</span>:<span id=t_idt>FIFO_DEPTH</span>-<span id=t_cns>1</span>];
+
+<span id=t_com>// synchronous read. Introduces one clock cycle delay</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>buffer</span>[<span id=t_idt>addrOut</span>];
+<span id=t_kwd>end</span>
+
+<span id=t_com>// synchronous write</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>buffer</span>[<span id=t_idt>addrIn</span>] &lt;= <span id=t_idt>dataIn</span>;
+<span id=t_kwd>end</span>                  
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/buffers/simFifoMem.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram127.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram127.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram127.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="directcontrol IDLE" alt="directcontrol IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/diagram127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/directcontrol.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/directcontrol.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/directcontrol.v/index.htm	(revision 264)
@@ -0,0 +1,210 @@
+<html>
+<head>
+<title>directcontrol.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// directControl</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:36 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>directControl</span> (<span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortGnt</span>, <span id=t_idt>HCTxPortRdy</span>, <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>directControlEn</span>, <span id=t_idt>directControlLineState</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directControlEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directControlLineState</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortWEn</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>next_HCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>, <span id=t_idt>next_HCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>next_HCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>next_HCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directControlEn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directControlLineState</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: drctCntl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_DC</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_DRCT_CNTL</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_WAIT_GNT</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_CHK_LOOP</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_WAIT_RDY</span> <span id=t_cns>3'b100</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_FIN</span> <span id=t_cns>3'b101</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_GNT</span> <span id=t_cns>3'b110</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_RDY</span> <span id=t_cns>3'b111</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_drctCntl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_drctCntl</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// diagram ACTION</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: drctCntl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>directControlLineState</span> <span id=t_kwd>or</span> <span id=t_idt>directControlEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_drctCntl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>drctCntl_NextState</span>
+  <span id=t_idt>NextState_drctCntl</span> &lt;= <span id=t_idt>CurrState_drctCntl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_idt>HCTxPortReq</span>;
+  <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_idt>HCTxPortWEn</span>;
+  <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>HCTxPortData</span>;
+  <span id=t_idt>next_HCTxPortCntl</span> &lt;= <span id=t_idt>HCTxPortCntl</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_drctCntl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_DC</span>:
+     <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+   `<span id=t_idt>CHK_DRCT_CNTL</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>directControlEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_GNT</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>IDLE_WAIT_GNT</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DRCT_CNTL_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>;
+   `<span id=t_idt>DRCT_CNTL_CHK_LOOP</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>directControlEn</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_CHK_LOOP</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>directControlLineState</span>};
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_DIRECT_CONTROL</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>IDLE_WAIT_RDY</span>;
+   `<span id=t_idt>IDLE_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>IDLE_FIN</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_IDLE</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>drctCntl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_drctCntl</span> &lt;= `<span id=t_idt>START_DC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_drctCntl</span> &lt;= <span id=t_idt>NextState_drctCntl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>drctCntl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>next_HCTxPortCntl</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>next_HCTxPortData</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_idt>next_HCTxPortWEn</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_idt>next_HCTxPortReq</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/directcontrol.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(488,1130,591,1232,Click78,Over78);
+FUB[1] = new Array(1112,1183,1215,1285,Click127,Over127);
+
+//----------------------------------------------------------------------------
+function Click78(){fubclick('./index78.htm');}
+function Over78(){window.status='Hierarchical State DRCT_CNTL';};
+function Click127(){fubclick('./index127.htm');}
+function Over127(){window.status='Hierarchical State IDLE';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./directcontrol.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./directcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="getpacket" alt="getpacket"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram58.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram58.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram58.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="getpacket DATA" alt="getpacket DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram58.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket_DATA.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index58.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index58.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index58.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar58.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram58.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index58.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar33.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar33.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1244,949,1347,1051,Click58,Over58);
+
+//----------------------------------------------------------------------------
+function Click58(){fubclick('./index58.htm');}
+function Over58(){window.status='Hierarchical State DATA';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 33 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./getpacket_PROC_PKT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./getpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 3400 ;
+var PageY = 4400 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 2040;
+var h = 2640;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hctxportarbiter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hctxportarbiter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram47.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram47.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram47.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller IN" alt="hostcontroller IN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram47.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller_OUT0.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller_OUT0.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index49.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index49.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index49.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar49.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram49.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index49.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar45.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar45.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar45.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 45 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller_SETUP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar51.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar51.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar51.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 51 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller_OUT1.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar51.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram21.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram21.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram21.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket SEND_PID" alt="sendpacket SEND_PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram21.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram45.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram45.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram45.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket DATA0_DATA1" alt="sendpacket DATA0_DATA1"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket.v/index.htm	(revision 264)
@@ -0,0 +1,380 @@
+<html>
+<head>
+<title>getpacket.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// getPacket</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:41 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>getPacket</span> (<span id=t_idt>RXDataIn</span>, <span id=t_idt>RXDataValid</span>, <span id=t_idt>RXFifoData</span>, <span id=t_idt>RXFifoFull</span>, <span id=t_idt>RXFifoWEn</span>, <span id=t_idt>RXPacketRdy</span>, <span id=t_idt>RXPktStatus</span>, <span id=t_idt>RXStreamStatusIn</span>, <span id=t_idt>RxPID</span>, <span id=t_idt>SIERxTimeOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>getPacketEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXDataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RXDataValid</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RXFifoFull</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStreamStatusIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIERxTimeOut</span>;   <span id=t_com>// Single cycle pulse</span>
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>getPacketEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXFifoData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXFifoWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXPacketRdy</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXPktStatus</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXDataIn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RXDataValid</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXFifoData</span>, <span id=t_idt>next_RXFifoData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RXFifoFull</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXFifoWEn</span>, <span id=t_idt>next_RXFifoWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXPacketRdy</span>, <span id=t_idt>next_RXPacketRdy</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXPktStatus</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStreamStatusIn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>, <span id=t_idt>next_RxPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>getPacketEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>ACKRxed</span>, <span id=t_idt>next_ACKRxed</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>CRCError</span>, <span id=t_idt>next_CRCError</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>NAKRxed</span>, <span id=t_idt>next_NAKRxed</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteOld</span>, <span id=t_idt>next_RXByteOld</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteOldest</span>, <span id=t_idt>next_RXByteOldest</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByte</span>, <span id=t_idt>next_RXByte</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>RXOverflow</span>, <span id=t_idt>next_RXOverflow</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXStreamStatus</span>, <span id=t_idt>next_RXStreamStatus</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>RXTimeOut</span>, <span id=t_idt>next_RXTimeOut</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>bitStuffError</span>, <span id=t_idt>next_bitStuffError</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>dataSequence</span>, <span id=t_idt>next_dataSequence</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>stallRxed</span>, <span id=t_idt>next_stallRxed</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: getPkt</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_CHK_PID</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_HS</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D1</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D1</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D2</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_FIN</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D2</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D3</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D3</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_GP</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_PKT</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PKT_START</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_EN</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_RDY</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span> <span id=t_cns>5'b10001</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_getPkt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_getPkt</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_kwd>always</span> @
+(<span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RXOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RXTimeOut</span> <span id=t_kwd>or</span>
+  <span id=t_idt>NAKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>stallRxed</span> <span id=t_kwd>or</span>
+  <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>dataSequence</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>RXPktStatus</span> = {
+    <span id=t_idt>dataSequence</span>, <span id=t_idt>ACKRxed</span>,
+    <span id=t_idt>stallRxed</span>, <span id=t_idt>NAKRxed</span>,
+    <span id=t_idt>RXTimeOut</span>, <span id=t_idt>RXOverflow</span>,
+    <span id=t_idt>bitStuffError</span>, <span id=t_idt>CRCError</span>};
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: getPkt</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RXDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>RXStreamStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RXByte</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteOldest</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteOld</span> <span id=t_kwd>or</span> <span id=t_idt>SIERxTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>RXDataValid</span> <span id=t_kwd>or</span> <span id=t_idt>RXStreamStatus</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoFull</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>RXOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RXTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>NAKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>stallRxed</span> <span id=t_kwd>or</span> <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>dataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>RxPID</span> <span id=t_kwd>or</span> <span id=t_idt>RXPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoData</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_getPkt</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>getPkt_NextState</span>
+  <span id=t_idt>NextState_getPkt</span> &lt;= <span id=t_idt>CurrState_getPkt</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>CRCError</span>;
+  <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>bitStuffError</span>;
+  <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_idt>RXOverflow</span>;
+  <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_idt>RXTimeOut</span>;
+  <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_idt>NAKRxed</span>;
+  <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_idt>stallRxed</span>;
+  <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>ACKRxed</span>;
+  <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>dataSequence</span>;
+  <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXByte</span>;
+  <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatus</span>;
+  <span id=t_idt>next_RxPID</span> &lt;= <span id=t_idt>RxPID</span>;
+  <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_idt>RXPacketRdy</span>;
+  <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByteOldest</span>;
+  <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByteOld</span>;
+  <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_idt>RXFifoWEn</span>;
+  <span id=t_idt>next_RXFifoData</span> &lt;= <span id=t_idt>RXFifoData</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_getPkt</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_GP</span>:
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>WAIT_EN</span>;
+   `<span id=t_idt>WAIT_PKT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIERxTimeOut</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>CHK_PKT_START</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PKT_START</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_START</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_CHK_PID</span>;
+      <span id=t_idt>next_RxPID</span> &lt;= <span id=t_idt>RXByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_EN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketEn</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>WAIT_PKT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_CHK_PID</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>HANDSHAKE</span>) 
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_HS</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>DATA</span>) 
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+   `<span id=t_idt>PROC_PKT_HS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>RX_OVERFLOW_BIT</span>];
+      <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>NAK_RXED_BIT</span>];
+      <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>STALL_RXED_BIT</span>];
+      <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>ACK_RXED_BIT</span>];
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_W_D1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D1</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D2</span>;
+      <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_W_D2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D2</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>CRC_ERROR_BIT</span>];
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>BIT_STUFF_ERROR_BIT</span>];
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>DATA_SEQUENCE_BIT</span>];
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D3</span>;
+      <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_W_D3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D3</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXFifoFull</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span>;
+      <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>;
+      <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_RXFifoData</span> &lt;= <span id=t_idt>RXByteOldest</span>;
+      <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByteOld</span>;
+      <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span>:
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>;
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> ((<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStreamStatusIn</span> == `<span id=t_idt>RX_PACKET_STREAM</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span>:
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>getPkt_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_getPkt</span> &lt;= `<span id=t_idt>START_GP</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_getPkt</span> &lt;= <span id=t_idt>NextState_getPkt</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>getPkt_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXByteOld</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXByteOldest</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXStreamStatus</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXFifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXFifoData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxPID</span> &lt;= <span id=t_cns>4'h0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXByteOld</span> &lt;= <span id=t_idt>next_RXByteOld</span>;
+   <span id=t_idt>RXByteOldest</span> &lt;= <span id=t_idt>next_RXByteOldest</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_idt>next_CRCError</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_idt>next_bitStuffError</span>;
+   <span id=t_idt>RXOverflow</span> &lt;= <span id=t_idt>next_RXOverflow</span>;
+   <span id=t_idt>RXTimeOut</span> &lt;= <span id=t_idt>next_RXTimeOut</span>;
+   <span id=t_idt>NAKRxed</span> &lt;= <span id=t_idt>next_NAKRxed</span>;
+   <span id=t_idt>stallRxed</span> &lt;= <span id=t_idt>next_stallRxed</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_idt>next_ACKRxed</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_idt>next_dataSequence</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_idt>next_RXByte</span>;
+   <span id=t_idt>RXStreamStatus</span> &lt;= <span id=t_idt>next_RXStreamStatus</span>;
+   <span id=t_idt>RXPacketRdy</span> &lt;= <span id=t_idt>next_RXPacketRdy</span>;
+   <span id=t_idt>RXFifoWEn</span> &lt;= <span id=t_idt>next_RXFifoWEn</span>;
+   <span id=t_idt>RXFifoData</span> &lt;= <span id=t_idt>next_RXFifoData</span>;
+   <span id=t_idt>RxPID</span> &lt;= <span id=t_idt>next_RxPID</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket_PROC_PKT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket_PROC_PKT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index33.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index33.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar33.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram33.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index33.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar112.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar112.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar112.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 112 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./getpacket_LOOP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./getpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar112.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hctxportarbiter" alt="hctxportarbiter"
+				width=2040 height=2640 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram45.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram45.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram45.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller SETUP" alt="hostcontroller SETUP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram51.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram51.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram51.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller OUT1" alt="hostcontroller OUT1"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram51.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller_IN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller_IN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller_SETUP.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller_SETUP.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index47.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index47.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index47.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar47.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram47.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index47.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(341,1398,444,1500,Click45,Over45);
+FUB[1] = new Array(733,1389,836,1492,Click47,Over47);
+FUB[2] = new Array(1416,1391,1519,1494,Click51,Over51);
+FUB[3] = new Array(965,1392,1068,1495,Click49,Over49);
+
+//----------------------------------------------------------------------------
+function Click45(){fubclick('./index45.htm');}
+function Over45(){window.status='Hierarchical State SETUP';};
+function Click47(){fubclick('./index47.htm');}
+function Over47(){window.status='Hierarchical State IN';};
+function Click51(){fubclick('./index51.htm');}
+function Over51(){window.status='Hierarchical State OUT1';};
+function Click49(){fubclick('./index49.htm');}
+function Over49(){window.status='Hierarchical State OUT0';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar49.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar49.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar49.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 49 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller_OUT0.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar49.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket" alt="sendpacket"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram43.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram43.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram43.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket SEND_SOF" alt="sendpacket SEND_SOF"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram43.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/directcontrol_DRCT_CNTL.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/directcontrol_DRCT_CNTL.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index127.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index127.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index127.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar127.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram127.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/index127.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar127.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar127.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar127.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 127 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./directcontrol_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./directcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/directcontrol.asf/toolbar127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram112.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram112.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram112.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="getpacket LOOP" alt="getpacket LOOP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/diagram112.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index21.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index21.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index21.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar21.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram21.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index21.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index45.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index45.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index45.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar45.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram45.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index45.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket_LOOP.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/getpacket_LOOP.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index112.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index112.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index112.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar112.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram112.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/index112.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1059,1575,1161,1677,Click33,Over33);
+
+//----------------------------------------------------------------------------
+function Click33(){fubclick('./index33.htm');}
+function Over33(){window.status='Hierarchical State PROC_PKT';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./getpacket.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./getpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar58.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar58.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar58.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(662,1601,764,1703,Click112,Over112);
+
+//----------------------------------------------------------------------------
+function Click112(){fubclick('./index112.htm');}
+function Over112(){window.status='Hierarchical State LOOP';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 58 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./getpacket_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./getpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/getpacket.asf/toolbar58.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.v/index.htm	(revision 264)
@@ -0,0 +1,253 @@
+<html>
+<head>
+<title>hctxportarbiter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// HCTxPortArbiter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:45 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>HCTxPortArbiter</span> (<span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortWEnable</span>, <span id=t_idt>SOFCntlCntl</span>, <span id=t_idt>SOFCntlData</span>, <span id=t_idt>SOFCntlGnt</span>, <span id=t_idt>SOFCntlReq</span>, <span id=t_idt>SOFCntlWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>directCntlCntl</span>, <span id=t_idt>directCntlData</span>, <span id=t_idt>directCntlGnt</span>, <span id=t_idt>directCntlReq</span>, <span id=t_idt>directCntlWEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketCntl</span>, <span id=t_idt>sendPacketData</span>, <span id=t_idt>sendPacketGnt</span>, <span id=t_idt>sendPacketReq</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFCntlReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFCntlWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortWEnable</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SOFCntlGnt</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>directCntlGnt</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketGnt</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>next_HCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>, <span id=t_idt>next_HCTxPortData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortWEnable</span>, <span id=t_idt>next_HCTxPortWEnable</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFCntlGnt</span>, <span id=t_idt>next_SOFCntlGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFCntlReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFCntlWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>directCntlGnt</span>, <span id=t_idt>next_directCntlGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketGnt</span>, <span id=t_idt>next_sendPacketGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketWEn</span>;
+
+
+<span id=t_com>// Constants</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIRECT_CTRL_MUX</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_PACKET_MUX</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_CTRL_MUX</span> <span id=t_cns>2'b01</span>
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>muxCntl</span>, <span id=t_idt>next_muxCntl</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: HCTxArb</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_HARB</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_REQ</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_PACKET</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIRECT_CONTROL</span> <span id=t_cns>3'b100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_HCTxArb</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_HCTxArb</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// SOFController/directContol/sendPacket mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>muxCntl</span> <span id=t_kwd>or</span> <span id=t_idt>SOFCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>SOFCntlCntl</span> <span id=t_kwd>or</span>
+        <span id=t_idt>directCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlCntl</span> <span id=t_kwd>or</span>
+                  <span id=t_idt>directCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlCntl</span> <span id=t_kwd>or</span>
+          <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketData</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketCntl</span>)
+<span id=t_kwd>begin</span>
+<span id=t_kwd>case</span> (<span id=t_idt>muxCntl</span>)
+    `<span id=t_idt>SOF_CTRL_MUX</span> :
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>HCTxPortWEnable</span> &lt;= <span id=t_idt>SOFCntlWEn</span>;
+        <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>SOFCntlData</span>;
+        <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>SOFCntlCntl</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>DIRECT_CTRL_MUX</span> :
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>HCTxPortWEnable</span> &lt;= <span id=t_idt>directCntlWEn</span>;
+        <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>directCntlData</span>;
+        <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>directCntlCntl</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>SEND_PACKET_MUX</span> :
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>HCTxPortWEnable</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+        <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>sendPacketData</span>;
+        <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>sendPacketCntl</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>default</span> :
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>HCTxPortWEnable</span> &lt;= <span id=t_cns>1'b0</span>;
+        <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+        <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: HCTxArb</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>SOFCntlReq</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketReq</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlReq</span> <span id=t_kwd>or</span> <span id=t_idt>SOFCntlGnt</span> <span id=t_kwd>or</span> <span id=t_idt>muxCntl</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketGnt</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlGnt</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_HCTxArb</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>HCTxArb_NextState</span>
+  <span id=t_idt>NextState_HCTxArb</span> &lt;= <span id=t_idt>CurrState_HCTxArb</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_SOFCntlGnt</span> &lt;= <span id=t_idt>SOFCntlGnt</span>;
+  <span id=t_idt>next_muxCntl</span> &lt;= <span id=t_idt>muxCntl</span>;
+  <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_idt>sendPacketGnt</span>;
+  <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_idt>directCntlGnt</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_HCTxArb</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_HARB</span>:
+     <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>WAIT_REQ</span>;
+   `<span id=t_idt>WAIT_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFCntlReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>SEND_SOF</span>;
+      <span id=t_idt>next_SOFCntlGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxCntl</span> &lt;= `<span id=t_idt>SOF_CTRL_MUX</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>sendPacketReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>SEND_PACKET</span>;
+      <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxCntl</span> &lt;= `<span id=t_idt>SEND_PACKET_MUX</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>directCntlReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>DIRECT_CONTROL</span>;
+      <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxCntl</span> &lt;= `<span id=t_idt>DIRECT_CTRL_MUX</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFCntlReq</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>WAIT_REQ</span>;
+      <span id=t_idt>next_SOFCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_PACKET</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>WAIT_REQ</span>;
+      <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DIRECT_CONTROL</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>directCntlReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>WAIT_REQ</span>;
+      <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>HCTxArb_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_HCTxArb</span> &lt;= `<span id=t_idt>START_HARB</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_HCTxArb</span> &lt;= <span id=t_idt>NextState_HCTxArb</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>HCTxArb_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxCntl</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>SOFCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>directCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxCntl</span> &lt;= <span id=t_idt>next_muxCntl</span>;
+   <span id=t_idt>SOFCntlGnt</span> &lt;= <span id=t_idt>next_SOFCntlGnt</span>;
+   <span id=t_idt>sendPacketGnt</span> &lt;= <span id=t_idt>next_sendPacketGnt</span>;
+   <span id=t_idt>directCntlGnt</span> &lt;= <span id=t_idt>next_directCntlGnt</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller" alt="hostcontroller"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram49.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram49.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram49.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller OUT0" alt="hostcontroller OUT0"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/diagram49.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller.v/index.htm	(revision 264)
@@ -0,0 +1,391 @@
+<html>
+<head>
+<title>hostcontroller.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// hostController</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:52 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>hostcontroller</span> (<span id=t_idt>RXStatus</span>, <span id=t_idt>clearTXReq</span>, <span id=t_idt>clk</span>, <span id=t_idt>getPacketREn</span>, <span id=t_idt>getPacketRdy</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketArbiterGnt</span>, <span id=t_idt>sendPacketArbiterReq</span>, <span id=t_idt>sendPacketPID</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>transDone</span>, <span id=t_idt>transReq</span>, <span id=t_idt>transType</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStatus</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketArbiterGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>transReq</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>clearTXReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>getPacketREn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketArbiterReq</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>transDone</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStatus</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>clearTXReq</span>, <span id=t_idt>next_clearTXReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>getPacketREn</span>, <span id=t_idt>next_getPacketREn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketArbiterGnt</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketArbiterReq</span>, <span id=t_idt>next_sendPacketArbiterReq</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>, <span id=t_idt>next_sendPacketPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>next_sendPacketWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>transDone</span>, <span id=t_idt>next_transDone</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>transReq</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: hstCntrl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_HC</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_REQ</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_TYPE</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>FLAG</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_DATA_RXED</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_CHK_FOR_ERROR</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_CLR_SP_WEN2</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_CLR_SP_WEN1</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_CLR_SP_WEN2</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIN</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_GNT</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_WAIT_PKT_RXED</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_IN_SENT</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_WAIT_RX_DATA</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_WAIT_DATA0_SENT</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_WAIT_OUT_SENT</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_HC_WAIT_RDY</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_SP_RDY1</span> <span id=t_cns>5'b10001</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_SP_RDY2</span> <span id=t_cns>5'b10010</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_WAIT_SP_RDY1</span> <span id=t_cns>5'b10011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_WAIT_SETUP_SENT</span> <span id=t_cns>5'b10100</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_WAIT_DATA_SENT</span> <span id=t_cns>5'b10101</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_CLR_SP_WEN1</span> <span id=t_cns>5'b10110</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_ACK_SENT</span> <span id=t_cns>5'b10111</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_CLR_WEN1</span> <span id=t_cns>5'b11000</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_CLR_WEN2</span> <span id=t_cns>5'b11001</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_WAIT_RX_DATA</span> <span id=t_cns>5'b11010</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_WAIT_OUT_SENT</span> <span id=t_cns>5'b11011</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_WAIT_DATA1_SENT</span> <span id=t_cns>5'b11100</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_WAIT_SP_RDY1</span> <span id=t_cns>5'b11101</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_CLR_WEN1</span> <span id=t_cns>5'b11110</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_CLR_WEN2</span> <span id=t_cns>5'b11111</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_hstCntrl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_hstCntrl</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: hstCntrl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>transReq</span> <span id=t_kwd>or</span> <span id=t_idt>transType</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketArbiterGnt</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>RXStatus</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketArbiterReq</span> <span id=t_kwd>or</span> <span id=t_idt>transDone</span> <span id=t_kwd>or</span> <span id=t_idt>clearTXReq</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketREn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketPID</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_hstCntrl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>hstCntrl_NextState</span>
+  <span id=t_idt>NextState_hstCntrl</span> &lt;= <span id=t_idt>CurrState_hstCntrl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_idt>sendPacketArbiterReq</span>;
+  <span id=t_idt>next_transDone</span> &lt;= <span id=t_idt>transDone</span>;
+  <span id=t_idt>next_clearTXReq</span> &lt;= <span id=t_idt>clearTXReq</span>;
+  <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+  <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_idt>getPacketREn</span>;
+  <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketPID</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_hstCntrl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_HC</span>:
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>TX_REQ</span>;
+   `<span id=t_idt>TX_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>transReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>WAIT_GNT</span>;
+      <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_TYPE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>transType</span> == `<span id=t_idt>OUTDATA0_TRANS</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_WAIT_SP_RDY1</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>transType</span> == `<span id=t_idt>IN_TRANS</span>) 
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_SP_RDY1</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>transType</span> == `<span id=t_idt>SETUP_TRANS</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_HC_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>transType</span> == `<span id=t_idt>OUTDATA1_TRANS</span>) 
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_WAIT_SP_RDY1</span>;
+   `<span id=t_idt>FLAG</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_transDone</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_clearTXReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FIN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_transDone</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_clearTXReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>TX_REQ</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketArbiterGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>CHK_TYPE</span>;
+   `<span id=t_idt>SETUP_CLR_SP_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_WAIT_SETUP_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_CLR_SP_WEN2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_WAIT_DATA_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_WAIT_PKT_RXED</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_HC_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_CLR_SP_WEN1</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>SETUP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_WAIT_SETUP_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_CLR_SP_WEN2</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_WAIT_DATA_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_WAIT_PKT_RXED</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_DATA_RXED</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_CHK_FOR_ERROR</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_CHK_FOR_ERROR</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_CRC_ERROR_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_BIT_STUFF_ERROR_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_RX_OVERFLOW_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_NAK_RXED_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_STALL_RXED_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_RX_TIME_OUT_BIT</span>] == <span id=t_cns>1'b0</span>) 
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_SP_RDY2</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   `<span id=t_idt>IN_CLR_SP_WEN2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_ACK_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_IN_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_DATA_RXED</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_SP_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_CLR_SP_WEN1</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>IN</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_SP_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_CLR_SP_WEN2</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>ACK</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_CLR_SP_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_IN_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_ACK_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   `<span id=t_idt>OUT0_WAIT_RX_DATA</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_WAIT_DATA0_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_WAIT_RX_DATA</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_WAIT_OUT_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_CLR_WEN2</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_WAIT_SP_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_CLR_WEN1</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>OUT</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_CLR_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_WAIT_OUT_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_CLR_WEN2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_WAIT_DATA0_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_WAIT_RX_DATA</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_WAIT_OUT_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_CLR_WEN2</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_WAIT_DATA1_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_WAIT_RX_DATA</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_WAIT_SP_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_CLR_WEN1</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>OUT</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_CLR_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_WAIT_OUT_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_CLR_WEN2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_WAIT_DATA1_SENT</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>hstCntrl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_hstCntrl</span> &lt;= `<span id=t_idt>START_HC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_hstCntrl</span> &lt;= <span id=t_idt>NextState_hstCntrl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>hstCntrl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>transDone</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>clearTXReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_cns>4'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>transDone</span> &lt;= <span id=t_idt>next_transDone</span>;
+   <span id=t_idt>clearTXReq</span> &lt;= <span id=t_idt>next_clearTXReq</span>;
+   <span id=t_idt>getPacketREn</span> &lt;= <span id=t_idt>next_getPacketREn</span>;
+   <span id=t_idt>sendPacketArbiterReq</span> &lt;= <span id=t_idt>next_sendPacketArbiterReq</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_idt>next_sendPacketWEn</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_idt>next_sendPacketPID</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller_OUT1.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/hostcontroller_OUT1.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index45.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index45.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index45.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar45.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram45.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index45.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index51.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index51.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index51.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar51.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram51.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/index51.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar47.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar47.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar47.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 47 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller_IN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/hostcontroller.asf/toolbar47.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/rxStatusMonitor.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/rxStatusMonitor.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/rxStatusMonitor.v/index.htm	(revision 264)
@@ -0,0 +1,111 @@
+<html>
+<head>
+<title>rxStatusMonitor.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// rxStatusMonitor.v                                            ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:53 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+<span id=t_kwd>module</span> <span id=t_idt>rxStatusMonitor</span>(<span id=t_idt>connectStateIn</span>, <span id=t_idt>connectStateOut</span>, <span id=t_idt>resumeDetectedIn</span>, <span id=t_idt>connectionEventOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> <span id=t_idt>connectionEventOut</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connectionEventOut</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>oldConnectState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>oldResumeDetected</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_idt>connectStateIn</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>connectStateOut</span> &lt;= <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>oldConnectState</span> &lt;= <span id=t_idt>connectStateIn</span>;
+   <span id=t_idt>oldResumeDetected</span> &lt;= <span id=t_idt>resumeDetectedIn</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>oldConnectState</span> &lt;= <span id=t_idt>connectStateIn</span>;
+   <span id=t_idt>oldResumeDetected</span> &lt;= <span id=t_idt>resumeDetectedIn</span>;
+   <span id=t_kwd>if</span> (<span id=t_idt>oldConnectState</span> != <span id=t_idt>connectStateIn</span>)
+     <span id=t_idt>connectionEventOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>else</span>
+     <span id=t_idt>connectionEventOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>if</span> (<span id=t_idt>resumeDetectedIn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>oldResumeDetected</span> == <span id=t_cns>1'b0</span>)
+     <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>else</span> 
+     <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/rxStatusMonitor.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram41.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram41.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram41.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket OUT_IN_SETUP" alt="sendpacket OUT_IN_SETUP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/diagram41.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index43.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index43.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index43.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar43.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram43.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index43.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket.v/index.htm	(revision 264)
@@ -0,0 +1,340 @@
+<html>
+<head>
+<title>sendpacket.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// sendPacket</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:01 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+
+
+<span id=t_kwd>module</span> <span id=t_idt>sendPacket</span> (<span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortGnt</span>, <span id=t_idt>HCTxPortRdy</span>, <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>PID</span>, <span id=t_idt>TxAddr</span>, <span id=t_idt>TxEndP</span>, <span id=t_idt>clk</span>, <span id=t_idt>fifoData</span>, <span id=t_idt>fifoEmpty</span>, <span id=t_idt>fifoReadEn</span>, <span id=t_idt>frameNum</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>PID</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddr</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndP</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fifoReadEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketRdy</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>next_HCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>, <span id=t_idt>next_HCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>next_HCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>next_HCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>PID</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddr</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndP</span>, <span id=t_idt>next_TxEndP</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>fifoReadEn</span>, <span id=t_idt>next_fifoReadEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>, <span id=t_idt>next_frameNum</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>next_sendPacketRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>PIDNotPID</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: sndPkt</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SP</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_ENABLE</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_WAIT_GNT</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_PID_WAIT_RDY</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_PID_FIN</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIN_SP</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT_IN_SETUP_WAIT_RDY1</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT_IN_SETUP_WAIT_RDY2</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT_IN_SETUP_FIN</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF_FIN1</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF_WAIT_RDY3</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF_WAIT_RDY4</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_READ_FIFO</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_WAIT_READ_FIFO</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_FIFO_EMPTY</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_FIN</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_TERM_BYTE</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT_IN_SETUP_CLR_WEN1</span> <span id=t_cns>5'b10001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF_CLR_WEN1</span> <span id=t_cns>5'b10010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_CLR_WEN</span> <span id=t_cns>5'b10011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_CLR_REN</span> <span id=t_cns>5'b10100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_sndPkt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_sndPkt</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>PID</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>PIDNotPID</span> &lt;=  { (<span id=t_idt>PID</span> ^ <span id=t_cns>4'hf</span>), <span id=t_idt>PID</span> };
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: sndPkt</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>PIDNotPID</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndP</span> <span id=t_kwd>or</span> <span id=t_idt>TxAddr</span> <span id=t_kwd>or</span> <span id=t_idt>frameNum</span> <span id=t_kwd>or</span> <span id=t_idt>fifoData</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>PID</span> <span id=t_kwd>or</span> <span id=t_idt>fifoEmpty</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>fifoReadEn</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_sndPkt</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sndPkt_NextState</span>
+  <span id=t_idt>NextState_sndPkt</span> &lt;= <span id=t_idt>CurrState_sndPkt</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_idt>sendPacketRdy</span>;
+  <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_idt>HCTxPortReq</span>;
+  <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_idt>HCTxPortWEn</span>;
+  <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>HCTxPortData</span>;
+  <span id=t_idt>next_HCTxPortCntl</span> &lt;= <span id=t_idt>HCTxPortCntl</span>;
+  <span id=t_idt>next_frameNum</span> &lt;= <span id=t_idt>frameNum</span>;
+  <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_idt>fifoReadEn</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_sndPkt</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SP</span>:
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>WAIT_ENABLE</span>;
+   `<span id=t_idt>WAIT_ENABLE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketWEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SP_WAIT_GNT</span>;
+      <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_PID_WAIT_RDY</span>;
+   `<span id=t_idt>FIN_SP</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>WAIT_ENABLE</span>;
+     <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_PID_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_PID_FIN</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>PIDNotPID</span>;
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_START</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_PID_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>PID</span> == `<span id=t_idt>DATA0</span> || <span id=t_idt>PID</span> == `<span id=t_idt>DATA1</span>)  
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_FIFO_EMPTY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>PID</span> == `<span id=t_idt>SOF</span>)  
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_SOF_WAIT_RDY3</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>PID</span> == `<span id=t_idt>OUT</span> || 
+      <span id=t_idt>PID</span> == `<span id=t_idt>IN</span> || 
+      <span id=t_idt>PID</span> == `<span id=t_idt>SETUP</span>)  
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>OUT_IN_SETUP_WAIT_RDY1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>FIN_SP</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT_IN_SETUP_WAIT_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>OUT_IN_SETUP_CLR_WEN1</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= {<span id=t_idt>TxEndP</span>[<span id=t_cns>0</span>], <span id=t_idt>TxAddr</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>]};
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT_IN_SETUP_WAIT_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>OUT_IN_SETUP_FIN</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>TxEndP</span>[<span id=t_cns>3</span>:<span id=t_cns>1</span>]};
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT_IN_SETUP_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>FIN_SP</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT_IN_SETUP_CLR_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>OUT_IN_SETUP_WAIT_RDY2</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF_FIN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_frameNum</span> &lt;= <span id=t_idt>frameNum</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>FIN_SP</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF_WAIT_RDY3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_SOF_CLR_WEN1</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>frameNum</span>[<span id=t_cns>7</span>:<span id=t_cns>0</span>];
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF_WAIT_RDY4</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_SOF_FIN1</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNum</span>[<span id=t_cns>10</span>:<span id=t_cns>8</span>]};
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF_CLR_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_SOF_WAIT_RDY4</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_READ_FIFO</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>fifoData</span>;
+     <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_CLR_WEN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_WAIT_READ_FIFO</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_CLR_REN</span>;
+      <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_FIFO_EMPTY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>fifoEmpty</span> == <span id=t_cns>1'b0</span>) 
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_WAIT_READ_FIFO</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_TERM_BYTE</span>;
+   `<span id=t_idt>DATA0_DATA1_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>FIN_SP</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_TERM_BYTE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_FIN</span>;
+      <span id=t_com>//Last byte is not valid data,</span>
+      <span id=t_com>//but the 'TX_PACKET_STOP' flag is required</span>
+      <span id=t_com>//by the SIE state machine to detect end of data packet</span>
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_CLR_WEN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_FIFO_EMPTY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_CLR_REN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_READ_FIFO</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sndPkt_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_sndPkt</span> &lt;= `<span id=t_idt>START_SP</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_sndPkt</span> &lt;= <span id=t_idt>NextState_sndPkt</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sndPkt_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>frameNum</span> &lt;= <span id=t_cns>11'h000</span>;
+   <span id=t_idt>fifoReadEn</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketRdy</span> &lt;= <span id=t_idt>next_sendPacketRdy</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_idt>next_HCTxPortReq</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_idt>next_HCTxPortWEn</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>next_HCTxPortData</span>;
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>next_HCTxPortCntl</span>;
+   <span id=t_idt>frameNum</span> &lt;= <span id=t_idt>next_frameNum</span>;
+   <span id=t_idt>fifoReadEn</span> &lt;= <span id=t_idt>next_fifoReadEn</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket_SEND_PID.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket_SEND_PID.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar21.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar21.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar21.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 21 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket_SEND_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar21.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar45.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar45.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar45.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 45 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket_DATA0_DATA1.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index41.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index41.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index41.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar41.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram41.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/index41.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket_OUT_IN_SETUP.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket_OUT_IN_SETUP.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(846,1408,949,1511,Click21,Over21);
+FUB[1] = new Array(1383,1784,1485,1886,Click45,Over45);
+FUB[2] = new Array(863,1765,965,1867,Click43,Over43);
+FUB[3] = new Array(433,1750,536,1853,Click41,Over41);
+
+//----------------------------------------------------------------------------
+function Click21(){fubclick('./index21.htm');}
+function Over21(){window.status='Hierarchical State SEND_PID';};
+function Click45(){fubclick('./index45.htm');}
+function Over45(){window.status='Hierarchical State DATA0_DATA1';};
+function Click43(){fubclick('./index43.htm');}
+function Over43(){window.status='Hierarchical State SEND_SOF';};
+function Click41(){fubclick('./index41.htm');}
+function Over41(){window.status='Hierarchical State OUT_IN_SETUP';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar43.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar43.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar43.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 43 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket_SEND_SOF.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar43.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacketarbiter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacketarbiter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram95.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram95.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram95.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacketcheckpreamble REG_PKT" alt="sendpacketcheckpreamble REG_PKT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram95.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index95.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index95.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index95.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar95.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram95.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index95.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket_DATA0_DATA1.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket_DATA0_DATA1.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket_SEND_SOF.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/sendpacket_SEND_SOF.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar41.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar41.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar41.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 41 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket_OUT_IN_SETUP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacket.asf/toolbar41.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacketarbiter" alt="sendpacketarbiter"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm	(revision 264)
@@ -0,0 +1,196 @@
+<html>
+<head>
+<title>sendpacketarbiter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// sendPacketArbiter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:02 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>sendPacketArbiter</span> (<span id=t_idt>HCTxGnt</span>, <span id=t_idt>HCTxReq</span>, <span id=t_idt>HC_PID</span>, <span id=t_idt>HC_SP_WEn</span>, <span id=t_idt>SOFTxGnt</span>, <span id=t_idt>SOFTxReq</span>, <span id=t_idt>SOF_SP_WEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketPID</span>, <span id=t_idt>sendPacketWEnable</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxReq</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>HC_PID</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>HC_SP_WEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFTxReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOF_SP_WEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxGnt</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SOFTxGnt</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEnable</span>;
+
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxGnt</span>, <span id=t_idt>next_HCTxGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxReq</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>HC_PID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HC_SP_WEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFTxGnt</span>, <span id=t_idt>next_SOFTxGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFTxReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOF_SP_WEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>, <span id=t_idt>next_sendPacketPID</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEnable</span>, <span id=t_idt>next_sendPacketWEnable</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>muxSOFNotHC</span>, <span id=t_idt>next_muxSOFNotHC</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: sendPktArb</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_ACT</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_ACT</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>SARB_WAIT_REQ</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SARB</span> <span id=t_cns>2'b11</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_sendPktArb</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_sendPktArb</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// hostController/SOFTransmit mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>muxSOFNotHC</span> <span id=t_kwd>or</span> <span id=t_idt>SOF_SP_WEn</span> <span id=t_kwd>or</span> <span id=t_idt>HC_SP_WEn</span> <span id=t_kwd>or</span> <span id=t_idt>HC_PID</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>muxSOFNotHC</span>  == <span id=t_cns>1'b1</span>)
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>sendPacketWEnable</span> &lt;= <span id=t_idt>SOF_SP_WEn</span>;
+        <span id=t_idt>sendPacketPID</span> &lt;= `<span id=t_idt>SOF</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span>
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>sendPacketWEnable</span> &lt;= <span id=t_idt>HC_SP_WEn</span>;
+        <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_idt>HC_PID</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: sendPktArb</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>HCTxReq</span> <span id=t_kwd>or</span> <span id=t_idt>SOFTxReq</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxGnt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFTxGnt</span> <span id=t_kwd>or</span> <span id=t_idt>muxSOFNotHC</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_sendPktArb</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktArb_NextState</span>
+  <span id=t_idt>NextState_sendPktArb</span> &lt;= <span id=t_idt>CurrState_sendPktArb</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_HCTxGnt</span> &lt;= <span id=t_idt>HCTxGnt</span>;
+  <span id=t_idt>next_SOFTxGnt</span> &lt;= <span id=t_idt>SOFTxGnt</span>;
+  <span id=t_idt>next_muxSOFNotHC</span> &lt;= <span id=t_idt>muxSOFNotHC</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_sendPktArb</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>HC_ACT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>SARB_WAIT_REQ</span>;
+      <span id=t_idt>next_HCTxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SOF_ACT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTxReq</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>SARB_WAIT_REQ</span>;
+      <span id=t_idt>next_SOFTxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SARB_WAIT_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTxReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>SOF_ACT</span>;
+      <span id=t_idt>next_SOFTxGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxSOFNotHC</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>HCTxReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>HC_ACT</span>;
+      <span id=t_idt>next_HCTxGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxSOFNotHC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>START_SARB</span>:
+     <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>SARB_WAIT_REQ</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktArb_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_sendPktArb</span> &lt;= `<span id=t_idt>START_SARB</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_sendPktArb</span> &lt;= <span id=t_idt>NextState_sendPktArb</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktArb_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxSOFNotHC</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SOFTxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxSOFNotHC</span> &lt;= <span id=t_idt>next_muxSOFNotHC</span>;
+   <span id=t_idt>SOFTxGnt</span> &lt;= <span id=t_idt>next_SOFTxGnt</span>;
+   <span id=t_idt>HCTxGnt</span> &lt;= <span id=t_idt>next_HCTxGnt</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram32.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram32.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram32.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacketcheckpreamble PREAM_PKT" alt="sendpacketcheckpreamble PREAM_PKT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram32.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index32.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index32.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index32.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar32.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram32.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index32.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm	(revision 264)
@@ -0,0 +1,235 @@
+<html>
+<head>
+<title>sendpacketcheckpreamble.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// sendPacketCheckPreamble</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:06 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>sendPacketCheckPreamble</span> (<span id=t_idt>clk</span>, <span id=t_idt>fullSpeedBitRate</span>, <span id=t_idt>fullSpeedPolarity</span>, <span id=t_idt>grabLineControl</span>, <span id=t_idt>preAmbleEnable</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketCPPID</span>, <span id=t_idt>sendPacketCPReady</span>, <span id=t_idt>sendPacketCPWEn</span>, <span id=t_idt>sendPacketPID</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>preAmbleEnable</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCPPID</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketCPWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fullSpeedBitRate</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>grabLineControl</span>;   <span id=t_com>// mux select</span>
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketCPReady</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>fullSpeedBitRate</span>, <span id=t_idt>next_fullSpeedBitRate</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>fullSpeedPolarity</span>, <span id=t_idt>next_fullSpeedPolarity</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>grabLineControl</span>, <span id=t_idt>next_grabLineControl</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>preAmbleEnable</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCPPID</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketCPReady</span>, <span id=t_idt>next_sendPacketCPReady</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketCPWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>, <span id=t_idt>next_sendPacketPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>next_sendPacketWEn</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: sendPktCP</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>SPC_WAIT_EN</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SPC</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PREAM</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_SND_PREAM</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_WAIT_RDY1</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_WAIT_RDY2</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_SND_PID</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_WAIT_RDY3</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>REG_PKT_SEND_PID</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>REG_PKT_WAIT_RDY1</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>REG_PKT_WAIT_RDY</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>READY</span> <span id=t_cns>4'b1011</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_sendPktCP</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_sendPktCP</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: sendPktCP</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>sendPacketCPPID</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketCPWEn</span> <span id=t_kwd>or</span> <span id=t_idt>preAmbleEnable</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketCPReady</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketPID</span> <span id=t_kwd>or</span> <span id=t_idt>fullSpeedBitRate</span> <span id=t_kwd>or</span> <span id=t_idt>fullSpeedPolarity</span> <span id=t_kwd>or</span> <span id=t_idt>grabLineControl</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_sendPktCP</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktCP_NextState</span>
+  <span id=t_idt>NextState_sendPktCP</span> &lt;= <span id=t_idt>CurrState_sendPktCP</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketCPReady</span> &lt;= <span id=t_idt>sendPacketCPReady</span>;
+  <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+  <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketPID</span>;
+  <span id=t_idt>next_fullSpeedBitRate</span> &lt;= <span id=t_idt>fullSpeedBitRate</span>;
+  <span id=t_idt>next_fullSpeedPolarity</span> &lt;= <span id=t_idt>fullSpeedPolarity</span>;
+  <span id=t_idt>next_grabLineControl</span> &lt;= <span id=t_idt>grabLineControl</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_sendPktCP</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>SPC_WAIT_EN</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketCPWEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>CHK_PREAM</span>;
+      <span id=t_idt>next_sendPacketCPReady</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>START_SPC</span>:
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>SPC_WAIT_EN</span>;
+   `<span id=t_idt>CHK_PREAM</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>preAmbleEnable</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_WAIT_RDY1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>REG_PKT_WAIT_RDY1</span>;
+   `<span id=t_idt>READY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketCPReady</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>SPC_WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_SND_PREAM</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>PREAMBLE</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_WAIT_RDY2</span>;
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_WAIT_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_SND_PREAM</span>;
+      <span id=t_idt>next_fullSpeedBitRate</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_fullSpeedPolarity</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_grabLineControl</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_WAIT_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_SND_PID</span>;
+      <span id=t_idt>next_fullSpeedBitRate</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_SND_PID</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketCPPID</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_WAIT_RDY3</span>;
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_WAIT_RDY3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>READY</span>;
+      <span id=t_idt>next_grabLineControl</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>REG_PKT_SEND_PID</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketCPPID</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>REG_PKT_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>REG_PKT_WAIT_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>REG_PKT_SEND_PID</span>;
+   `<span id=t_idt>REG_PKT_WAIT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>READY</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktCP_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_sendPktCP</span> &lt;= `<span id=t_idt>START_SPC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_sendPktCP</span> &lt;= <span id=t_idt>NextState_sendPktCP</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktCP_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_cns>4'b0</span>;
+   <span id=t_idt>fullSpeedBitRate</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>fullSpeedPolarity</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>grabLineControl</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketCPReady</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_idt>next_sendPacketWEn</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_idt>next_sendPacketPID</span>;
+   <span id=t_idt>fullSpeedBitRate</span> &lt;= <span id=t_idt>next_fullSpeedBitRate</span>;
+   <span id=t_idt>fullSpeedPolarity</span> &lt;= <span id=t_idt>next_fullSpeedPolarity</span>;
+   <span id=t_idt>grabLineControl</span> &lt;= <span id=t_idt>next_grabLineControl</span>;
+   <span id=t_idt>sendPacketCPReady</span> &lt;= <span id=t_idt>next_sendPacketCPReady</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(396,1432,498,1534,Click32,Over32);
+FUB[1] = new Array(1299,1396,1401,1499,Click95,Over95);
+
+//----------------------------------------------------------------------------
+function Click32(){fubclick('./index32.htm');}
+function Over32(){window.status='Hierarchical State PREAM_PKT';};
+function Click95(){fubclick('./index95.htm');}
+function Over95(){window.status='Hierarchical State REG_PKT';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacketcheckpreamble.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacketcheckpreamble.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="softransmit" alt="softransmit"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./softransmit.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./softransmit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm	(revision 264)
@@ -0,0 +1,104 @@
+<html>
+<head>
+<title>hostSlaveMuxBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// hostSlaveMuxBI.v                                             ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:12 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+ <span id=t_kwd>module</span> <span id=t_idt>hostSlaveMuxBI</span> (<span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>, <span id=t_idt>strobe_i</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>hostMode</span>, <span id=t_idt>hostSlaveMuxSel</span>);
+
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostSlaveMuxSel</span>;
+<span id=t_kwd>output</span> <span id=t_idt>hostMode</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSlaveMuxSel</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>hostMode</span>;
+
+<span id=t_com>//internal wire and regs</span>
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>hostMode</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>hostSlaveMuxSel</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span>)
+     <span id=t_idt>hostMode</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>hostMode</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>7'h0</span>, <span id=t_idt>hostMode</span>};
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacketcheckpreamble" alt="sendpacketcheckpreamble"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble_REG_PKT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble_REG_PKT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sofcontroller" alt="sofcontroller"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sofcontroller.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sofcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm	(revision 264)
@@ -0,0 +1,189 @@
+<html>
+<head>
+<title>softransmit.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SOFTransmit</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:09 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>SOFTransmit</span> (<span id=t_idt>SOFEnable</span>, <span id=t_idt>SOFSent</span>, <span id=t_idt>SOFSyncEn</span>, <span id=t_idt>SOFTimerClr</span>, <span id=t_idt>SOFTimer</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketArbiterGnt</span>, <span id=t_idt>sendPacketArbiterReq</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>SOFEnable</span>;   <span id=t_com>// After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn</span>
+<span id=t_kwd>input</span>   <span id=t_idt>SOFSyncEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketArbiterGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SOFSent</span>;   <span id=t_com>// single cycle pulse</span>
+<span id=t_kwd>output</span>  <span id=t_idt>SOFTimerClr</span>;   <span id=t_com>// Single cycle pulse</span>
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketArbiterReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFEnable</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFSent</span>, <span id=t_idt>next_SOFSent</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFSyncEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFTimerClr</span>, <span id=t_idt>next_SOFTimerClr</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketArbiterGnt</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketArbiterReq</span>, <span id=t_idt>next_sendPacketArbiterReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>next_sendPacketWEn</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: SOFTx</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_STX</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SOF_NEAR</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SP_GNT</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SOF_NOW</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_FIN</span> <span id=t_cns>3'b100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_SOFTx</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_SOFTx</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: SOFTx</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>SOFTimer</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSyncEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFEnable</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketArbiterGnt</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketArbiterReq</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFTimerClr</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSent</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_SOFTx</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SOFTx_NextState</span>
+  <span id=t_idt>NextState_SOFTx</span> &lt;= <span id=t_idt>CurrState_SOFTx</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_idt>sendPacketArbiterReq</span>;
+  <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+  <span id=t_idt>next_SOFTimerClr</span> &lt;= <span id=t_idt>SOFTimerClr</span>;
+  <span id=t_idt>next_SOFSent</span> &lt;= <span id=t_idt>SOFSent</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_SOFTx</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_STX</span>:
+     <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>WAIT_SOF_NEAR</span>;
+   `<span id=t_idt>WAIT_SOF_NEAR</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTimer</span> &gt;= `<span id=t_idt>SOF_TX_TIME</span> - `<span id=t_idt>SOF_TX_MARGIN</span> ||
+      (<span id=t_idt>SOFSyncEn</span> == <span id=t_cns>1'b1</span> &amp;&amp;
+      <span id=t_idt>SOFEnable</span> == <span id=t_cns>1'b1</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>WAIT_SP_GNT</span>;
+      <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_SP_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketArbiterGnt</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>WAIT_SOF_NOW</span>;
+   `<span id=t_idt>WAIT_SOF_NOW</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTimer</span> &gt;= `<span id=t_idt>SOF_TX_TIME</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>SOF_FIN</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SOFTimerClr</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SOFSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SOFEnable</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>SOF_FIN</span>;
+      <span id=t_idt>next_SOFTimerClr</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SOF_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SOFTimerClr</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SOFSent</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>WAIT_SOF_NEAR</span>;
+     <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SOFTx_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_SOFTx</span> &lt;= `<span id=t_idt>START_STX</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_SOFTx</span> &lt;= <span id=t_idt>NextState_SOFTx</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SOFTx_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SOFSent</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SOFTimerClr</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SOFSent</span> &lt;= <span id=t_idt>next_SOFSent</span>;
+   <span id=t_idt>SOFTimerClr</span> &lt;= <span id=t_idt>next_SOFTimerClr</span>;
+   <span id=t_idt>sendPacketArbiterReq</span> &lt;= <span id=t_idt>next_sendPacketArbiterReq</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_idt>next_sendPacketWEn</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMux.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostSlaveMux/hostSlaveMux.v/index.htm	(revision 264)
@@ -0,0 +1,180 @@
+<html>
+<head>
+<title>hostSlaveMux.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// hostSlaveMux.v                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:12 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>hostSlaveMux</span> (
+  <span id=t_idt>SIEPortCtrlInToSIE</span>,
+  <span id=t_idt>SIEPortCtrlInFromHost</span>,
+  <span id=t_idt>SIEPortCtrlInFromSlave</span>,
+  <span id=t_idt>SIEPortDataInToSIE</span>, 
+  <span id=t_idt>SIEPortDataInFromHost</span>, 
+  <span id=t_idt>SIEPortDataInFromSlave</span>, 
+  <span id=t_idt>SIEPortWEnToSIE</span>, 
+  <span id=t_idt>SIEPortWEnFromHost</span>, 
+  <span id=t_idt>SIEPortWEnFromSlave</span>, 
+  <span id=t_idt>fullSpeedPolarityToSIE</span>,
+  <span id=t_idt>fullSpeedPolarityFromHost</span>,
+  <span id=t_idt>fullSpeedPolarityFromSlave</span>,
+  <span id=t_idt>fullSpeedBitRateToSIE</span>,
+  <span id=t_idt>fullSpeedBitRateFromHost</span>,
+  <span id=t_idt>fullSpeedBitRateFromSlave</span>,
+  <span id=t_idt>dataIn</span>, 
+  <span id=t_idt>dataOut</span>, 
+  <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>,
+  <span id=t_idt>hostSlaveMuxSel</span>  );
+
+
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInToSIE</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromHost</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromSlave</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInToSIE</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromHost</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromSlave</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>SIEPortWEnToSIE</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>SIEPortWEnFromHost</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>SIEPortWEnFromSlave</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPolarityToSIE</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedPolarityFromHost</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedPolarityFromSlave</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedBitRateToSIE</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedBitRateFromHost</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedBitRateFromSlave</span>;
+<span id=t_com>//hostSlaveMuxBI</span>
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostSlaveMuxSel</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInToSIE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromHost</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromSlave</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInToSIE</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromHost</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromSlave</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>SIEPortWEnToSIE</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnFromHost</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnFromSlave</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPolarityToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityFromHost</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityFromSlave</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedBitRateToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateFromHost</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateFromSlave</span>;
+<span id=t_com>//hostSlaveMuxBI</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSlaveMuxSel</span>;
+
+<span id=t_com>//internal wires and regs</span>
+<span id=t_kwd>wire</span> <span id=t_idt>hostMode</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_idt>hostMode</span> <span id=t_kwd>or</span>
+  <span id=t_idt>SIEPortCtrlInFromHost</span> <span id=t_kwd>or</span>
+  <span id=t_idt>SIEPortCtrlInFromSlave</span> <span id=t_kwd>or</span>
+  <span id=t_idt>SIEPortDataInFromHost</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SIEPortDataInFromSlave</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SIEPortWEnFromHost</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SIEPortWEnFromSlave</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>fullSpeedPolarityFromHost</span> <span id=t_kwd>or</span>
+  <span id=t_idt>fullSpeedPolarityFromSlave</span> <span id=t_kwd>or</span>
+  <span id=t_idt>fullSpeedBitRateFromHost</span> <span id=t_kwd>or</span>
+  <span id=t_idt>fullSpeedBitRateFromSlave</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>hostMode</span> == <span id=t_cns>1'b1</span>) 
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>SIEPortCtrlInToSIE</span> &lt;= <span id=t_idt>SIEPortCtrlInFromHost</span>;
+    <span id=t_idt>SIEPortDataInToSIE</span> &lt;=  <span id=t_idt>SIEPortDataInFromHost</span>;
+    <span id=t_idt>SIEPortWEnToSIE</span> &lt;= <span id=t_idt>SIEPortWEnFromHost</span>;
+    <span id=t_idt>fullSpeedPolarityToSIE</span> &lt;= <span id=t_idt>fullSpeedPolarityFromHost</span>;
+    <span id=t_idt>fullSpeedBitRateToSIE</span> &lt;= <span id=t_idt>fullSpeedBitRateFromHost</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>SIEPortCtrlInToSIE</span> &lt;= <span id=t_idt>SIEPortCtrlInFromSlave</span>;
+    <span id=t_idt>SIEPortDataInToSIE</span> &lt;=  <span id=t_idt>SIEPortDataInFromSlave</span>;
+    <span id=t_idt>SIEPortWEnToSIE</span> &lt;= <span id=t_idt>SIEPortWEnFromSlave</span>;
+    <span id=t_idt>fullSpeedPolarityToSIE</span> &lt;= <span id=t_idt>fullSpeedPolarityFromSlave</span>;
+    <span id=t_idt>fullSpeedBitRateToSIE</span> &lt;= <span id=t_idt>fullSpeedBitRateFromSlave</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>      
+
+<span id=t_idt>hostSlaveMuxBI</span> <span id=t_idt>u_hostSlaveMuxBI</span> (
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>dataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataOut</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>hostMode</span>(<span id=t_idt>hostMode</span>), 
+  .<span id=t_idt>hostSlaveMuxSel</span>(<span id=t_idt>hostSlaveMuxSel</span>)  );
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 95 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacketcheckpreamble_REG_PKT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacketcheckpreamble.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm	(revision 264)
@@ -0,0 +1,195 @@
+<html>
+<head>
+<title>sofcontroller.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SOFController</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:07 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>SOFController</span> (<span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortGnt</span>, <span id=t_idt>HCTxPortRdy</span>, <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>SOFEnable</span>, <span id=t_idt>SOFTimerClr</span>, <span id=t_idt>SOFTimer</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFEnable</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFTimerClr</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>next_HCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>, <span id=t_idt>next_HCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>next_HCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>next_HCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFEnable</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFTimerClr</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>, <span id=t_idt>next_SOFTimer</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: sofCntl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SC</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SOF_EN</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SEND_RESUME</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>INC_TIMER</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_WAIT_GNT</span> <span id=t_cns>3'b100</span>
+<span id=t_dir>`define</span> <span id=t_idt>CLR_WEN</span> <span id=t_cns>3'b101</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_sofCntl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_sofCntl</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: sofCntl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>SOFTimerClr</span> <span id=t_kwd>or</span> <span id=t_idt>SOFTimer</span> <span id=t_kwd>or</span> <span id=t_idt>SOFEnable</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_sofCntl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sofCntl_NextState</span>
+  <span id=t_idt>NextState_sofCntl</span> &lt;= <span id=t_idt>CurrState_sofCntl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_idt>HCTxPortReq</span>;
+  <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_idt>HCTxPortWEn</span>;
+  <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>HCTxPortData</span>;
+  <span id=t_idt>next_HCTxPortCntl</span> &lt;= <span id=t_idt>HCTxPortCntl</span>;
+  <span id=t_idt>next_SOFTimer</span> &lt;= <span id=t_idt>SOFTimer</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_sofCntl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SC</span>:
+     <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>WAIT_SOF_EN</span>;
+   `<span id=t_idt>WAIT_SOF_EN</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFEnable</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>SC_WAIT_GNT</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_SEND_RESUME</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>CLR_WEN</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_RESUME_START</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>INC_TIMER</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTimerClr</span> == <span id=t_cns>1'b1</span>)
+       <span id=t_idt>next_SOFTimer</span> &lt;= <span id=t_cns>16'h0000</span>;
+     <span id=t_kwd>else</span>
+       <span id=t_idt>next_SOFTimer</span> &lt;= <span id=t_idt>SOFTimer</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFEnable</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>WAIT_SOF_EN</span>;
+      <span id=t_idt>next_SOFTimer</span> &lt;= <span id=t_cns>16'h0000</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SC_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>WAIT_SEND_RESUME</span>;
+   `<span id=t_idt>CLR_WEN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>INC_TIMER</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sofCntl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_sofCntl</span> &lt;= `<span id=t_idt>START_SC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_sofCntl</span> &lt;= <span id=t_idt>NextState_sofCntl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sofCntl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SOFTimer</span> &lt;= <span id=t_cns>16'h0000</span>;
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SOFTimer</span> &lt;= <span id=t_idt>next_SOFTimer</span>;
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>next_HCTxPortCntl</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>next_HCTxPortData</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_idt>next_HCTxPortWEn</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_idt>next_HCTxPortReq</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/softransmit.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/usbHostControl.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/usbHostControl.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/usbHostControl.v/index.htm	(revision 264)
@@ -0,0 +1,416 @@
+<html>
+<head>
+<title>usbHostControl.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbHostControl.v                                             ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:10 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+<span id=t_kwd>module</span> <span id=t_idt>usbHostControl</span>(
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_com>//sendPacket</span>
+  <span id=t_idt>TxFifoRE</span>, <span id=t_idt>TxFifoData</span>, <span id=t_idt>TxFifoEmpty</span>,
+  <span id=t_com>//getPacket</span>
+  <span id=t_idt>RxFifoWE</span>, <span id=t_idt>RxFifoData</span>, <span id=t_idt>RxFifoFull</span>,
+  <span id=t_idt>RxByteStatus</span>, <span id=t_idt>RxData</span>, <span id=t_idt>RxDataValid</span>,
+  <span id=t_idt>SIERxTimeOut</span>,
+  <span id=t_com>//speedCtrlMux</span>
+  <span id=t_idt>fullSpeedRate</span>, <span id=t_idt>fullSpeedPol</span>,
+  <span id=t_com>//HCTxPortArbiter</span>
+  <span id=t_idt>HCTxPortEn</span>, <span id=t_idt>HCTxPortRdy</span>,
+  <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortCtrl</span>,
+  <span id=t_com>//rxStatusMonitor</span>
+  <span id=t_idt>connectStateIn</span>, 
+  <span id=t_idt>resumeDetectedIn</span>,
+  <span id=t_com>//USBHostControlBI </span>
+  <span id=t_idt>busAddress</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>, 
+  <span id=t_idt>busWriteEn</span>,
+  <span id=t_idt>busStrobe_i</span>,
+  <span id=t_idt>SOFSentIntOut</span>, 
+  <span id=t_idt>connEventIntOut</span>, 
+  <span id=t_idt>resumeIntOut</span>, 
+  <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>hostControlSelect</span>
+   );
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>, <span id=t_idt>rst</span>;
+<span id=t_com>//sendPacket</span>
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoRE</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_com>//getPacket</span>
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoWE</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxFifoData</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteStatus</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxData</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxDataValid</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_com>//speedCtrlMux</span>
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>;
+<span id=t_com>//HCTxPortArbiter</span>
+<span id=t_kwd>output</span> <span id=t_idt>HCTxPortEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCtrl</span>;
+<span id=t_com>//rxStatusMonitor</span>
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_com>//USBHostControlBI </span>
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busWriteEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoRE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoWE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxFifoData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteStatus</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxDataValid</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPol</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HCTxPortEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCtrl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busWriteEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>connEventIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>;
+
+<span id=t_com>//internal wiring</span>
+<span id=t_kwd>wire</span> <span id=t_idt>SOFTimerClr</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>getPacketREn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HCTxGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HCTxReq</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>HC_PID</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HC_SP_WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFTxGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFTxReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOF_SP_WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFEnable</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSyncEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPReadyIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPReadyOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCPPIDIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCPPIDOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPWEnIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPWEnOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPFSRate</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPFSPol</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPGrabLine</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFCntlGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFCntlReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFCntlWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketWEn</span>;   
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrTxReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDone</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transReq</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>preAmbleEnable</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directLineState</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directLineCtrlEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddr</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndP</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatus</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCtrlRate</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCtrlPol</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntFromRxStatusMon</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>connectionEventFromRxStatusMon</span>;
+
+<span id=t_idt>USBHostControlBI</span> <span id=t_idt>u_USBHostControlBI</span> 
+  (.<span id=t_idt>address</span>(<span id=t_idt>busAddress</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>busDataOut</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>busWriteEn</span>),
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>busStrobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>SOFSentIntOut</span>(<span id=t_idt>SOFSentIntOut</span>), 
+  .<span id=t_idt>connEventIntOut</span>(<span id=t_idt>connEventIntOut</span>), 
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>resumeIntOut</span>), 
+  .<span id=t_idt>transDoneIntOut</span>(<span id=t_idt>transDoneIntOut</span>),
+  .<span id=t_idt>TxTransTypeReg</span>(<span id=t_idt>transType</span>), 
+  .<span id=t_idt>TxSOFEnableReg</span>(<span id=t_idt>SOFEnable</span>),
+  .<span id=t_idt>TxAddrReg</span>(<span id=t_idt>TxAddr</span>), 
+  .<span id=t_idt>TxEndPReg</span>(<span id=t_idt>TxEndP</span>), 
+  .<span id=t_idt>frameNumIn</span>(<span id=t_idt>frameNum</span>), 
+  .<span id=t_idt>RxPktStatusIn</span>(<span id=t_idt>RxPktStatus</span>), 
+  .<span id=t_idt>RxPIDIn</span>(<span id=t_idt>RxPID</span>),
+  .<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectStateOut</span>),
+  .<span id=t_idt>SOFSentIn</span>(<span id=t_idt>SOFSent</span>), 
+  .<span id=t_idt>connEventIn</span>(<span id=t_idt>connectionEventFromRxStatusMon</span>), 
+  .<span id=t_idt>resumeIntIn</span>(<span id=t_idt>resumeIntFromRxStatusMon</span>), 
+  .<span id=t_idt>transDoneIn</span>(<span id=t_idt>transDone</span>),
+  .<span id=t_idt>hostControlSelect</span>(<span id=t_idt>hostControlSelect</span>),
+  .<span id=t_idt>clrTransReq</span>(<span id=t_idt>clrTxReq</span>),
+  .<span id=t_idt>preambleEn</span>(<span id=t_idt>preAmbleEnable</span>),
+  .<span id=t_idt>SOFSync</span>(<span id=t_idt>SOFSyncEn</span>),
+  .<span id=t_idt>TxLineState</span>(<span id=t_idt>directLineState</span>),
+  .<span id=t_idt>LineDirectControlEn</span>(<span id=t_idt>directLineCtrlEn</span>),
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>directCtrlPol</span>), 
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>directCtrlRate</span>),
+  .<span id=t_idt>transReq</span>(<span id=t_idt>transReq</span>)
+  
+  );
+
+
+<span id=t_idt>hostcontroller</span> <span id=t_idt>u_hostController</span>
+  (.<span id=t_idt>RXStatus</span>(<span id=t_idt>RxPktStatus</span>), 
+  .<span id=t_idt>clearTXReq</span>(<span id=t_idt>clrTxReq</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>getPacketREn</span>(<span id=t_idt>getPacketREn</span>),
+  .<span id=t_idt>getPacketRdy</span>(<span id=t_idt>getPacketRdy</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketArbiterGnt</span>(<span id=t_idt>HCTxGnt</span>),
+  .<span id=t_idt>sendPacketArbiterReq</span>(<span id=t_idt>HCTxReq</span>),
+  .<span id=t_idt>sendPacketPID</span>(<span id=t_idt>HC_PID</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>sendPacketCPReadyOut</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>HC_SP_WEn</span>),
+  .<span id=t_idt>transDone</span>(<span id=t_idt>transDone</span>),
+  .<span id=t_idt>transReq</span>(<span id=t_idt>transReq</span>),
+  .<span id=t_idt>transType</span>(<span id=t_idt>transType</span>) );
+
+<span id=t_idt>SOFController</span> <span id=t_idt>u_SOFController</span>
+  (.<span id=t_idt>HCTxPortCntl</span>(<span id=t_idt>SOFCntlCntl</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>SOFCntlData</span>),
+  .<span id=t_idt>HCTxPortGnt</span>(<span id=t_idt>SOFCntlGnt</span>),
+  .<span id=t_idt>HCTxPortRdy</span>(<span id=t_idt>HCTxPortRdy</span>),
+  .<span id=t_idt>HCTxPortReq</span>(<span id=t_idt>SOFCntlReq</span>),
+  .<span id=t_idt>HCTxPortWEn</span>(<span id=t_idt>SOFCntlWEn</span>),
+  .<span id=t_idt>SOFEnable</span>(<span id=t_idt>SOFEnable</span>),
+  .<span id=t_idt>SOFTimerClr</span>(<span id=t_idt>SOFTimerClr</span>),
+  .<span id=t_idt>SOFTimer</span>(<span id=t_idt>SOFTimer</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>SOFTransmit</span> <span id=t_idt>u_SOFTransmit</span>
+  (.<span id=t_idt>SOFEnable</span>(<span id=t_idt>SOFEnable</span>),
+  .<span id=t_idt>SOFSent</span>(<span id=t_idt>SOFSent</span>),
+  .<span id=t_idt>SOFSyncEn</span>(<span id=t_idt>SOFSyncEn</span>),
+  .<span id=t_idt>SOFTimerClr</span>(<span id=t_idt>SOFTimerClr</span>),
+  .<span id=t_idt>SOFTimer</span>(<span id=t_idt>SOFTimer</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketArbiterGnt</span>(<span id=t_idt>SOFTxGnt</span>),
+  .<span id=t_idt>sendPacketArbiterReq</span>(<span id=t_idt>SOFTxReq</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>sendPacketCPReadyOut</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>SOF_SP_WEn</span>) );  
+
+
+<span id=t_idt>sendPacketArbiter</span> <span id=t_idt>u_sendPacketArbiter</span>
+  (.<span id=t_idt>HCTxGnt</span>(<span id=t_idt>HCTxGnt</span>),
+  .<span id=t_idt>HCTxReq</span>(<span id=t_idt>HCTxReq</span>),
+  .<span id=t_idt>HC_PID</span>(<span id=t_idt>HC_PID</span>),
+  .<span id=t_idt>HC_SP_WEn</span>(<span id=t_idt>HC_SP_WEn</span>),
+  .<span id=t_idt>SOFTxGnt</span>(<span id=t_idt>SOFTxGnt</span>),
+  .<span id=t_idt>SOFTxReq</span>(<span id=t_idt>SOFTxReq</span>),
+  .<span id=t_idt>SOF_SP_WEn</span>(<span id=t_idt>SOF_SP_WEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketPID</span>(<span id=t_idt>sendPacketCPPIDIn</span>),
+  .<span id=t_idt>sendPacketWEnable</span>(<span id=t_idt>sendPacketCPWEnIn</span>) );   
+
+<span id=t_idt>sendPacketCheckPreamble</span> <span id=t_idt>u_sendPacketCheckPreamble</span>
+  (.<span id=t_idt>sendPacketCPPID</span>(<span id=t_idt>sendPacketCPPIDIn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>fullSpeedBitRate</span>(<span id=t_idt>sendPacketCPFSRate</span>),
+  .<span id=t_idt>fullSpeedPolarity</span>(<span id=t_idt>sendPacketCPFSPol</span>),
+  .<span id=t_idt>grabLineControl</span>(<span id=t_idt>sendPacketCPGrabLine</span>),
+  .<span id=t_idt>preAmbleEnable</span>(<span id=t_idt>preAmbleEnable</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketCPReady</span>(<span id=t_idt>sendPacketCPReadyOut</span>),
+  .<span id=t_idt>sendPacketCPWEn</span>(<span id=t_idt>sendPacketCPWEnIn</span>),
+  .<span id=t_idt>sendPacketPID</span>(<span id=t_idt>sendPacketCPPIDOut</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>sendPacketCPReadyIn</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>sendPacketCPWEnOut</span>) );
+
+<span id=t_idt>sendPacket</span> <span id=t_idt>u_sendPacket</span>
+  (.<span id=t_idt>HCTxPortCntl</span>(<span id=t_idt>sendPacketCntl</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>sendPacketData</span>),
+  .<span id=t_idt>HCTxPortGnt</span>(<span id=t_idt>sendPacketGnt</span>),
+  .<span id=t_idt>HCTxPortRdy</span>(<span id=t_idt>HCTxPortRdy</span>),
+  .<span id=t_idt>HCTxPortReq</span>(<span id=t_idt>sendPacketReq</span>),
+  .<span id=t_idt>HCTxPortWEn</span>(<span id=t_idt>sendPacketWEn</span>),
+  .<span id=t_idt>PID</span>(<span id=t_idt>sendPacketCPPIDOut</span>),
+  .<span id=t_idt>TxAddr</span>(<span id=t_idt>TxAddr</span>),
+  .<span id=t_idt>TxEndP</span>(<span id=t_idt>TxEndP</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>fifoData</span>(<span id=t_idt>TxFifoData</span>),
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEmpty</span>),
+  .<span id=t_idt>fifoReadEn</span>(<span id=t_idt>TxFifoRE</span>),
+  .<span id=t_idt>frameNum</span>(<span id=t_idt>frameNum</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>sendPacketCPReadyIn</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>sendPacketCPWEnOut</span>) );
+  
+<span id=t_idt>directControl</span> <span id=t_idt>u_directControl</span>
+  (.<span id=t_idt>HCTxPortCntl</span>(<span id=t_idt>directCntlCntl</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>directCntlData</span>),
+  .<span id=t_idt>HCTxPortGnt</span>(<span id=t_idt>directCntlGnt</span>),
+  .<span id=t_idt>HCTxPortRdy</span>(<span id=t_idt>HCTxPortRdy</span>),
+  .<span id=t_idt>HCTxPortReq</span>(<span id=t_idt>directCntlReq</span>),
+  .<span id=t_idt>HCTxPortWEn</span>(<span id=t_idt>directCntlWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>directControlEn</span>(<span id=t_idt>directLineCtrlEn</span>),
+  .<span id=t_idt>directControlLineState</span>(<span id=t_idt>directLineState</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>HCTxPortArbiter</span> <span id=t_idt>u_HCTxPortArbiter</span>
+  (.<span id=t_idt>HCTxPortCntl</span>(<span id=t_idt>HCTxPortCtrl</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>HCTxPortData</span>),
+  .<span id=t_idt>HCTxPortWEnable</span>(<span id=t_idt>HCTxPortEn</span>),
+  .<span id=t_idt>SOFCntlCntl</span>(<span id=t_idt>SOFCntlCntl</span>),
+  .<span id=t_idt>SOFCntlData</span>(<span id=t_idt>SOFCntlData</span>),
+  .<span id=t_idt>SOFCntlGnt</span>(<span id=t_idt>SOFCntlGnt</span>),
+  .<span id=t_idt>SOFCntlReq</span>(<span id=t_idt>SOFCntlReq</span>),
+  .<span id=t_idt>SOFCntlWEn</span>(<span id=t_idt>SOFCntlWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>directCntlCntl</span>(<span id=t_idt>directCntlCntl</span>),
+  .<span id=t_idt>directCntlData</span>(<span id=t_idt>directCntlData</span>),
+  .<span id=t_idt>directCntlGnt</span>(<span id=t_idt>directCntlGnt</span>),
+  .<span id=t_idt>directCntlReq</span>(<span id=t_idt>directCntlReq</span>),
+  .<span id=t_idt>directCntlWEn</span>(<span id=t_idt>directCntlWEn</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketCntl</span>(<span id=t_idt>sendPacketCntl</span>),
+  .<span id=t_idt>sendPacketData</span>(<span id=t_idt>sendPacketData</span>),
+  .<span id=t_idt>sendPacketGnt</span>(<span id=t_idt>sendPacketGnt</span>),
+  .<span id=t_idt>sendPacketReq</span>(<span id=t_idt>sendPacketReq</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>sendPacketWEn</span>) );   
+
+<span id=t_idt>getPacket</span> <span id=t_idt>u_getPacket</span>
+  (.<span id=t_idt>RXDataIn</span>(<span id=t_idt>RxData</span>),
+  .<span id=t_idt>RXDataValid</span>(<span id=t_idt>RxDataValid</span>),
+  .<span id=t_idt>RXFifoData</span>(<span id=t_idt>RxFifoData</span>),
+  .<span id=t_idt>RXFifoFull</span>(<span id=t_idt>RxFifoFull</span>),
+  .<span id=t_idt>RXFifoWEn</span>(<span id=t_idt>RxFifoWE</span>),
+  .<span id=t_idt>RXPacketRdy</span>(<span id=t_idt>getPacketRdy</span>),
+  .<span id=t_idt>RXPktStatus</span>(<span id=t_idt>RxPktStatus</span>),
+  .<span id=t_idt>RXStreamStatusIn</span>(<span id=t_idt>RxByteStatus</span>),
+  .<span id=t_idt>RxPID</span>(<span id=t_idt>RxPID</span>),
+  .<span id=t_idt>SIERxTimeOut</span>(<span id=t_idt>SIERxTimeOut</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>getPacketEn</span>(<span id=t_idt>getPacketREn</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>speedCtrlMux</span> <span id=t_idt>u_speedCtrlMux</span>
+  (.<span id=t_idt>directCtrlRate</span>(<span id=t_idt>directCtrlRate</span>),
+  .<span id=t_idt>directCtrlPol</span>(<span id=t_idt>directCtrlPol</span>),
+  .<span id=t_idt>sendPacketRate</span>(<span id=t_idt>sendPacketCPFSRate</span>),
+  .<span id=t_idt>sendPacketPol</span>(<span id=t_idt>sendPacketCPFSPol</span>),
+  .<span id=t_idt>sendPacketSel</span>(<span id=t_idt>sendPacketCPGrabLine</span>),
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedRate</span>),
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>fullSpeedPol</span>) );
+
+<span id=t_idt>rxStatusMonitor</span> <span id=t_idt>u_rxStatusMonitor</span>
+  (.<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectStateIn</span>),
+  .<span id=t_idt>connectStateOut</span>(<span id=t_idt>connectStateOut</span>),
+  .<span id=t_idt>resumeDetectedIn</span>(<span id=t_idt>resumeDetectedIn</span>),
+  .<span id=t_idt>connectionEventOut</span>(<span id=t_idt>connectionEventFromRxStatusMon</span>),
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>resumeIntFromRxStatusMon</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>)  );
+
+<span id=t_kwd>endmodule</span>
+
+  
+  
+
+
+
+
+
+</pre>
+</body>
+</html>

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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbHostControl_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbHostControl_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbHostControl_h.v/index.htm	(revision 264)
@@ -0,0 +1,124 @@
+<html>
+<head>
+<title>usbHostControl_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbHostControl_h.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:13 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_com>//HCRegIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_CONTROL_REG</span> <span id=t_cns>4'h0</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_TRANS_TYPE_REG</span> <span id=t_cns>4'h1</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_LINE_CONTROL_REG</span> <span id=t_cns>4'h2</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_SOF_ENABLE_REG</span> <span id=t_cns>4'h3</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_ADDR_REG</span> <span id=t_cns>4'h4</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_ENDP_REG</span> <span id=t_cns>4'h5</span>
+<span id=t_dir>`define</span> <span id=t_idt>FRAME_NUM_MSB_REG</span> <span id=t_cns>4'h6</span>
+<span id=t_dir>`define</span> <span id=t_idt>FRAME_NUM_LSB_REG</span> <span id=t_cns>4'h7</span>
+<span id=t_dir>`define</span> <span id=t_idt>INTERRUPT_STATUS_REG</span> <span id=t_cns>4'h8</span>
+<span id=t_dir>`define</span> <span id=t_idt>INTERRUPT_MASK_REG</span> <span id=t_cns>4'h9</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_STATUS_REG</span> <span id=t_cns>4'ha</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PID_REG</span> <span id=t_cns>4'hb</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_ADDR_REG</span> <span id=t_cns>4'hc</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_ENDP_REG</span> <span id=t_cns>4'hd</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_CONNECT_STATE_REG</span> <span id=t_cns>4'he</span>
+<span id=t_dir>`define</span> <span id=t_idt>HCREG_BUFFER_LEN</span> <span id=t_cns>4'hf</span>
+<span id=t_dir>`define</span> <span id=t_idt>HCREG_MASK</span> <span id=t_cns>4'hf</span>
+
+<span id=t_com>//TXControlRegIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>TRANS_REQ_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_SYNC_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAMBLE_ENABLE_BIT</span> <span id=t_cns>2</span>
+
+<span id=t_com>//interruptRegIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>TRANS_DONE_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_INT_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>CONNECTION_EVENT_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_SENT_BIT</span> <span id=t_cns>3</span>
+
+<span id=t_com>//TXTransactionTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_TRANS</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_TRANS</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUTDATA0_TRANS</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUTDATA1_TRANS</span> <span id=t_cns>3</span>
+ 
+ <span id=t_com>//TXLineControlIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_LINE_STATE_LSBIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_LINE_STATE_MSBIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIRECT_CONTROL_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span> <span id=t_cns>4</span>
+
+<span id=t_com>//TXSOFEnableIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_EN_BIT</span> <span id=t_cns>0</span>
+
+<span id=t_com>//SOFTimeConstants </span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_TX_TIME</span> <span id=t_cns>80</span>     <span id=t_com>//Fix this. Need correct SOF TX interval</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_TX_MARGIN</span> <span id=t_cns>2</span>
+       
+<span id=t_com>//Host RXStatusRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_CRC_ERROR_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_BIT_STUFF_ERROR_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_RX_OVERFLOW_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_RX_TIME_OUT_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_NAK_RXED_BIT</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_STALL_RXED_BIT</span> <span id=t_cns>5</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_ACK_RXED_BIT</span> <span id=t_cns>6</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_DATA_SEQUENCE_BIT</span> <span id=t_cns>7</span>
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbHostControl_h.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 32 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacketcheckpreamble_PREAM_PKT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacketcheckpreamble.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/sofcontroller.asf/sofcontroller.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/softransmit.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/speedCtrlMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/speedCtrlMux.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/speedCtrlMux.v/index.htm	(revision 264)
@@ -0,0 +1,94 @@
+<html>
+<head>
+<title>speedCtrlMux.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// speedCtrlMux.v                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:09 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+<span id=t_kwd>module</span> <span id=t_idt>speedCtrlMux</span> (<span id=t_idt>directCtrlRate</span>, <span id=t_idt>directCtrlPol</span>, <span id=t_idt>sendPacketRate</span>, <span id=t_idt>sendPacketPol</span>, <span id=t_idt>sendPacketSel</span>, <span id=t_idt>fullSpeedRate</span>, <span id=t_idt>fullSpeedPol</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>directCtrlRate</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCtrlPol</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRate</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketPol</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketSel</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fullSpeedPol</span>;
+
+<span id=t_kwd>wire</span>   <span id=t_idt>directCtrlRate</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>directCtrlPol</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>sendPacketRate</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>sendPacketPol</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>sendPacketSel</span>;
+<span id=t_kwd>reg</span>   <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span>   <span id=t_idt>fullSpeedPol</span>;
+
+
+<span id=t_kwd>always</span> @(<span id=t_idt>directCtrlRate</span> <span id=t_kwd>or</span> <span id=t_idt>directCtrlPol</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRate</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketPol</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketSel</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>sendPacketSel</span> == <span id=t_cns>1'b1</span>) 
+  <span id=t_kwd>begin</span>
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>sendPacketRate</span>;
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>sendPacketPol</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>directCtrlRate</span>;
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>directCtrlPol</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/hostController/speedCtrlMux.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbConstants_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbConstants_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbConstants_h.v/index.htm	(revision 264)
@@ -0,0 +1,88 @@
+<html>
+<head>
+<title>usbConstants_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbConstants_h.v                                             ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////  USB global constants as defined by USB spec 1.1</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:12 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_com>//PIDTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT</span> <span id=t_cns>4'h1</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN</span> <span id=t_cns>4'h9</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF</span> <span id=t_cns>4'h5</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP</span> <span id=t_cns>4'hd</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0</span> <span id=t_cns>4'h3</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA1</span> <span id=t_cns>4'hb</span>
+<span id=t_dir>`define</span> <span id=t_idt>ACK</span> <span id=t_cns>4'h2</span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK</span> <span id=t_cns>4'ha</span>
+<span id=t_dir>`define</span> <span id=t_idt>STALL</span> <span id=t_cns>4'he</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAMBLE</span> <span id=t_cns>4'hc</span> 
+     
+
+<span id=t_com>//PIDGroups</span>
+<span id=t_dir>`define</span> <span id=t_idt>SPECIAL</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>HANDSHAKE</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA</span> <span id=t_cns>2'b11</span>
+
+<span id=t_com>// start of packet SyncByte</span>
+<span id=t_dir>`define</span> <span id=t_idt>SYNC_BYTE</span> <span id=t_cns>8'h80</span>
+
+       
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbConstants_h.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/wishBoneBus_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/wishBoneBus_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/wishBoneBus_h.v/index.htm	(revision 264)
@@ -0,0 +1,91 @@
+<html>
+<head>
+<title>wishBoneBus_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// wishBoneBus_h.v                                              ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:14 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+ 
+<span id=t_com>//memoryMap</span>
+<span id=t_dir>`define</span> <span id=t_idt>HCREG_BASE</span> <span id=t_cns>8'h00</span>
+<span id=t_dir>`define</span> <span id=t_idt>HCREG_BASE_PLUS_0X10</span> <span id=t_cns>8'h10</span>
+<span id=t_dir>`define</span> <span id=t_idt>HOST_RX_FIFO_BASE</span> <span id=t_cns>8'h20</span>
+<span id=t_dir>`define</span> <span id=t_idt>HOST_TX_FIFO_BASE</span> <span id=t_cns>8'h30</span>
+<span id=t_dir>`define</span> <span id=t_idt>SCREG_BASE</span> <span id=t_cns>8'h40</span>
+<span id=t_dir>`define</span> <span id=t_idt>SCREG_BASE_PLUS_0X10</span> <span id=t_cns>8'h50</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_RX_FIFO_BASE</span> <span id=t_cns>8'h60</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_TX_FIFO_BASE</span> <span id=t_cns>8'h70</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_RX_FIFO_BASE</span> <span id=t_cns>8'h80</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_TX_FIFO_BASE</span> <span id=t_cns>8'h90</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_RX_FIFO_BASE</span> <span id=t_cns>8'ha0</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_TX_FIFO_BASE</span> <span id=t_cns>8'hb0</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_RX_FIFO_BASE</span> <span id=t_cns>8'hc0</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_TX_FIFO_BASE</span> <span id=t_cns>8'hd0</span>
+<span id=t_dir>`define</span> <span id=t_idt>HOST_SLAVE_CONTROL_BASE</span> <span id=t_cns>8'he0</span>
+<span id=t_dir>`define</span> <span id=t_idt>ADDRESS_DECODE_MASK</span> <span id=t_cns>8'hf0</span>
+
+<span id=t_com>//FifoAddresses</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_DATA_REG</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_STATUS_REG</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_DATA_COUNT_MSB</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_DATA_COUNT_LSB</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_CONTROL_REG</span> <span id=t_cns>3'b100</span>
+
+
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/wishBoneBus_h.v/index.htm
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+*
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===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_CRC.png
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Added: svn:mime-type
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+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_IDLE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_IDLE.png
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSlaveControl_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSlaveControl_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSlaveControl_h.v/index.htm	(revision 264)
@@ -0,0 +1,135 @@
+<html>
+<head>
+<title>usbSlaveControl_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbSlaveControl.v                                            ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:13 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_com>//endPointConstants </span>
+<span id=t_dir>`define</span> <span id=t_idt>NUM_OF_ENDPOINTS</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>NUM_OF_REGISTERS_PER_ENDPOINT</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>BASE_INDEX_FOR_ENDPOINT_REGS</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_CONTROL_REG</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_STATUS_REG</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_TRANSTYPE_STATUS_REG</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK_TRANSTYPE_STATUS_REG</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_CTRL_REG</span> <span id=t_cns>5'h0</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_STS_REG</span> <span id=t_cns>5'h1</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'h2</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_NAK_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'h3</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_CTRL_REG</span> <span id=t_cns>5'h4</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_STS_REG</span> <span id=t_cns>5'h5</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'h6</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_NAK_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'h7</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_CTRL_REG</span> <span id=t_cns>5'h8</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_STS_REG</span> <span id=t_cns>5'h9</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'ha</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_NAK_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'hb</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_CTRL_REG</span> <span id=t_cns>5'hc</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_STS_REG</span> <span id=t_cns>5'hd</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'he</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_NAK_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'hf</span>
+
+
+<span id=t_com>//SCRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>LAST_ENDP_REG</span> = `<span id=t_idt>BASE_INDEX_FOR_ENDPOINT_REGS</span> + (`<span id=t_idt>NUM_OF_REGISTERS_PER_ENDPOINT</span> * `<span id=t_idt>NUM_OF_ENDPOINTS</span>) - <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_CONTROL_REG</span> <span id=t_cns>5'h10</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_LINE_STATUS_REG</span> <span id=t_cns>5'h11</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_INTERRUPT_STATUS_REG</span> <span id=t_cns>5'h12</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_INTERRUPT_MASK_REG</span> <span id=t_cns>5'h13</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_ADDRESS</span> <span id=t_cns>5'h14</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_FRAME_NUM_MSP</span> <span id=t_cns>5'h15</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_FRAME_NUM_LSP</span> <span id=t_cns>5'h16</span>
+<span id=t_dir>`define</span> <span id=t_idt>SCREG_BUFFER_LEN</span> <span id=t_cns>5'h17</span>
+<span id=t_com>//SCRXStatusRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK_SET_MASK</span> <span id=t_cns>8'h10</span>
+<span id=t_com>//`define CRC_ERROR_BIT 0</span>
+<span id=t_com>//`define BIT_STUFF_ERROR_BIT 1</span>
+<span id=t_com>//`define RX_OVERFLOW_BIT 2</span>
+<span id=t_com>//`define RX_TIME_OUT_BIT 3</span>
+<span id=t_com>//`define NAK_SENT_BIT 4</span>
+<span id=t_com>//`define STALL_SENT_BIT 5</span>
+<span id=t_com>//`define ACK_RXED_BIT 6</span>
+<span id=t_com>//`define DATA_SEQUENCE_BIT 7</span>
+<span id=t_com>//SCEndPointControlRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_ENABLE_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_READY_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_OUTDATA_SEQUENCE_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_SEND_STALL_BIT</span> <span id=t_cns>3</span>
+<span id=t_com>//SCMasterControlegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_GLOBAL_ENABLE_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_TX_LINE_STATE_LSBIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_TX_LINE_STATE_MSBIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_DIRECT_CONTROL_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_FULL_SPEED_LINE_POLARITY_BIT</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_FULL_SPEED_LINE_RATE_BIT</span> <span id=t_cns>5</span>
+<span id=t_com>//SCinterruptRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>TRANS_DONE_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_INT_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESET_EVENT_BIT</span> <span id=t_cns>2</span>  <span id=t_com>//Line has entered reset state or left reset state</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_RECEIVED_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK_SENT_INT_BIT</span> <span id=t_cns>4</span>
+<span id=t_com>//TXTransactionTypes </span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_SETUP_TRANS</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_IN_TRANS</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_OUTDATA_TRANS</span> <span id=t_cns>2</span>
+<span id=t_com>//timeOuts </span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_RX_PACKET_TOUT</span> <span id=t_cns>18</span>
+       
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSlaveControl_h.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_BYTE1.png
===================================================================
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___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Added: svn:mime-type
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+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_HS.png
===================================================================
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___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_RES_ST.png
===================================================================
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Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_RES_ST.png
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram16.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram16.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram16.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter RES_ST" alt="SIETransmitter RES_ST"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter SPCL" alt="SIETransmitter SPCL"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter PID" alt="SIETransmitter PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter PID" alt="SIETransmitter PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm	(revision 264)
@@ -0,0 +1,147 @@
+<html>
+<head>
+<title>usbSerialInterfaceEngine_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbSerialInterfaceEngine_h.v                                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:13 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+ <span id=t_com>// Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate</span>
+<span id=t_dir>`define</span> <span id=t_idt>OVER_SAMPLE_RATE</span> <span id=t_cns>4</span>
+
+<span id=t_com>//timeOuts</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PACKET_TOUT</span> <span id=t_cns>18</span>
+
+<span id=t_com>//TXStreamControlTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_DIRECT_CONTROL</span> <span id=t_cns>8'h00</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_RESUME_START</span> <span id=t_cns>8'h01</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_PACKET_START</span> <span id=t_cns>8'h02</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_PACKET_STREAM</span> <span id=t_cns>8'h03</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_PACKET_STOP</span> <span id=t_cns>8'h04</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_IDLE</span> <span id=t_cns>8'h05</span>
+
+<span id=t_com>//RXStreamControlTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PACKET_START</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PACKET_STREAM</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PACKET_STOP</span> <span id=t_cns>2</span>
+
+<span id=t_com>//USBLineStates</span>
+<span id=t_com>// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo</span>
+<span id=t_dir>`define</span> <span id=t_idt>ONE_ZERO</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>ZERO_ONE</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>SE0</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>SE1</span> <span id=t_cns>2'b11</span>
+
+<span id=t_com>//RXStatusIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>CRC_ERROR_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>BIT_STUFF_ERROR_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_OVERFLOW_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK_RXED_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>STALL_RXED_BIT</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>ACK_RXED_BIT</span> <span id=t_cns>5</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_SEQUENCE_BIT</span> <span id=t_cns>6</span>
+
+<span id=t_com>//usbWireControlStates</span>
+<span id=t_dir>`define</span> <span id=t_idt>TRI_STATE</span> <span id=t_cns>1'b0</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRIVE</span> <span id=t_cns>1'b1</span>
+
+<span id=t_com>//limits</span>
+<span id=t_dir>`define</span> <span id=t_idt>MAX_CONSEC_SAME_BITS</span> <span id=t_cns>6</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_WAIT_TIME</span> <span id=t_cns>10</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_WAIT_TIME_MINUS1</span> <span id=t_cns>9</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_LEN</span> <span id=t_cns>20</span>
+<span id=t_dir>`define</span> <span id=t_idt>CONNECT_WAIT_TIME</span> <span id=t_cns>8'd20</span>
+<span id=t_dir>`define</span> <span id=t_idt>DISCONNECT_WAIT_TIME</span> <span id=t_cns>8'd20</span>
+
+<span id=t_com>//RXConnectStates</span>
+<span id=t_dir>`define</span> <span id=t_idt>DISCONNECT</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>LOW_SPEED_CONNECT</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>FULL_SPEED_CONNECT</span> <span id=t_cns>2'b10</span>
+
+<span id=t_com>//TX_RX_InternalStreamTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_START</span> <span id=t_cns>8'h00</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_STOP</span> <span id=t_cns>8'h01</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_STREAM</span> <span id=t_cns>8'h02</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_BIT_STUFF_ERROR</span> <span id=t_cns>8'h03</span>
+
+<span id=t_com>//RXStMach states</span>
+<span id=t_dir>`define</span> <span id=t_idt>DISCONNECT_ST</span> <span id=t_cns>4'h0</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FULL_SPEED_CONN_ST</span> <span id=t_cns>4'h1</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LOW_SPEED_CONN_ST</span> <span id=t_cns>4'h2</span>
+<span id=t_dir>`define</span> <span id=t_idt>CONNECT_LOW_SPEED_ST</span> <span id=t_cns>4'h3</span>
+<span id=t_dir>`define</span> <span id=t_idt>CONNECT_FULL_SPEED_ST</span> <span id=t_cns>4'h4</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LOW_SP_DISCONNECT_ST</span> <span id=t_cns>4'h5</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FULL_SP_DISCONNECT_ST</span> <span id=t_cns>4'h6</span>
+
+<span id=t_com>//RXBitStateMachStates</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_BIT_ST</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RECEIVE_BIT_ST</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_RESUME_ST</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_END_WAIT_ST</span> <span id=t_cns>2'b11</span>
+
+<span id=t_com>//RXByteStateMachStates </span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_BYTE_ST</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHECK_SYNC_ST</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHECK_PID_ST</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>HS_BYTE_ST</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN_BYTE_ST</span> <span id=t_cns>3'b100</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_BYTE_ST</span> <span id=t_cns>3'b101</span>
+
+
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm
===================================================================
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+<html>
+<head>
+<title>SIETransmitter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SIETransmitter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:02 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>SIETransmitter</span> (<span id=t_idt>CRC16En</span>, <span id=t_idt>CRC16Result</span>, <span id=t_idt>CRC16UpdateRdy</span>, <span id=t_idt>CRC5En</span>, <span id=t_idt>CRC5Result</span>, <span id=t_idt>CRC5UpdateRdy</span>, <span id=t_idt>CRC5_8Bit</span>, <span id=t_idt>CRCData</span>, <span id=t_idt>JBit</span>, <span id=t_idt>KBit</span>, <span id=t_idt>SIEPortCtrlIn</span>, <span id=t_idt>SIEPortDataIn</span>, <span id=t_idt>SIEPortTxRdy</span>, <span id=t_idt>SIEPortWEn</span>, <span id=t_idt>TxByteOutCtrl</span>, <span id=t_idt>TxByteOut</span>, <span id=t_idt>USBWireCtrl</span>, <span id=t_idt>USBWireData</span>, <span id=t_idt>USBWireGnt</span>, <span id=t_idt>USBWireRdy</span>, <span id=t_idt>USBWireReq</span>, <span id=t_idt>USBWireWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>processTxByteRdy</span>, <span id=t_idt>processTxByteWEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>rstCRC</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC16Result</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC16UpdateRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC5Result</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC5UpdateRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlIn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIEPortWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processTxByteRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC16En</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC5En</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC5_8Bit</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SIEPortTxRdy</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteOutCtrl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireCtrl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processTxByteWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>rstCRC</span>;
+
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC16En</span>, <span id=t_idt>next_CRC16En</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC16Result</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>CRC16UpdateRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC5En</span>, <span id=t_idt>next_CRC5En</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC5Result</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>CRC5UpdateRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC5_8Bit</span>, <span id=t_idt>next_CRC5_8Bit</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCData</span>, <span id=t_idt>next_CRCData</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlIn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SIEPortTxRdy</span>, <span id=t_idt>next_SIEPortTxRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIEPortWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteOutCtrl</span>, <span id=t_idt>next_TxByteOutCtrl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteOut</span>, <span id=t_idt>next_TxByteOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireCtrl</span>, <span id=t_idt>next_USBWireCtrl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireData</span>, <span id=t_idt>next_USBWireData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireReq</span>, <span id=t_idt>next_USBWireReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireWEn</span>, <span id=t_idt>next_USBWireWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processTxByteRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processTxByteWEn</span>, <span id=t_idt>next_processTxByteWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>rstCRC</span>, <span id=t_idt>next_rstCRC</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>SIEPortCtrl</span>, <span id=t_idt>next_SIEPortCtrl</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>SIEPortData</span>, <span id=t_idt>next_SIEPortData</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>4</span>:<span id=t_cns>0</span>]<span id=t_idt>i</span>, <span id=t_idt>next_i</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: SIETx</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_CHK_FIN</span> <span id=t_cns>6'b000000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_CHK_FIN</span> <span id=t_cns>6'b000001</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIR_CTL_CHK_FIN</span> <span id=t_cns>6'b000010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_CHK_PID</span> <span id=t_cns>6'b000011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_CHK_STOP</span> <span id=t_cns>6'b000100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_PKT_SENT</span> <span id=t_cns>6'b000101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_PKT_SENT</span> <span id=t_cns>6'b000110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_PID_PKT_SENT</span> <span id=t_cns>6'b000111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_PKT_SENT</span> <span id=t_cns>6'b001000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_PID_PKT_SENT</span> <span id=t_cns>6'b001001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_HS_PKT_SENT</span> <span id=t_cns>6'b001010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT1</span> <span id=t_cns>6'b001011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_PKT_SENT1</span> <span id=t_cns>6'b001100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT2</span> <span id=t_cns>6'b001101</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S1</span> <span id=t_cns>6'b001110</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S3</span> <span id=t_cns>6'b001111</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S4</span> <span id=t_cns>6'b010000</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S5</span> <span id=t_cns>6'b010001</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S6</span> <span id=t_cns>6'b010010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_SEND_IDLE1</span> <span id=t_cns>6'b010011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_SEND_IDLE2</span> <span id=t_cns>6'b010100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_SEND_IDLE3</span> <span id=t_cns>6'b010101</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SIETX</span> <span id=t_cns>6'b010110</span>
+<span id=t_dir>`define</span> <span id=t_idt>STX_CHK_ST</span> <span id=t_cns>6'b010111</span>
+<span id=t_dir>`define</span> <span id=t_idt>STX_WAIT_BYTE</span> <span id=t_cns>6'b011000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_STX_WAIT_GNT</span> <span id=t_cns>6'b011001</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_STX_WAIT_RDY</span> <span id=t_cns>6'b011010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_UPD_CRC</span> <span id=t_cns>6'b011011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_UPD_CRC</span> <span id=t_cns>6'b011100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_UPD_CRC</span> <span id=t_cns>6'b011101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_WAIT_BYTE</span> <span id=t_cns>6'b011110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_BYTE</span> <span id=t_cns>6'b011111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_WAIT_BYTE</span> <span id=t_cns>6'b100000</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIR_CTL_WAIT_GNT</span> <span id=t_cns>6'b100001</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_WAIT_GNT</span> <span id=t_cns>6'b100010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_HS_WAIT_RDY</span> <span id=t_cns>6'b100011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_PID_WAIT_RDY</span> <span id=t_cns>6'b100100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_WAIT_RDY</span> <span id=t_cns>6'b100101</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_WAIT_RDY</span> <span id=t_cns>6'b100110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_WAIT_RDY</span> <span id=t_cns>6'b100111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_PID_WAIT_RDY</span> <span id=t_cns>6'b101000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_WAIT_RDY</span> <span id=t_cns>6'b101001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_RDY</span> <span id=t_cns>6'b101010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIR_CTL_WAIT_RDY</span> <span id=t_cns>6'b101011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY1</span> <span id=t_cns>6'b101100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY2</span> <span id=t_cns>6'b101101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_WAIT_RDY_PKT</span> <span id=t_cns>6'b101110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_WAIT_WIRE</span> <span id=t_cns>6'b101111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_WAIT_RDY_WIRE</span> <span id=t_cns>6'b110000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_WAIT_GNT</span> <span id=t_cns>6'b110001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_WAIT_CRC_RDY</span> <span id=t_cns>6'b110010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_WAIT_CRC_RDY</span> <span id=t_cns>6'b110011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_CRC_RDY</span> <span id=t_cns>6'b110100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>5</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_SIETx</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>5</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_SIETx</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: SIETx</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>SIEPortDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortCtrlIn</span> <span id=t_kwd>or</span> <span id=t_idt>i</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortData</span> <span id=t_kwd>or</span> <span id=t_idt>JBit</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16Result</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5Result</span> <span id=t_kwd>or</span> <span id=t_idt>KBit</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireGnt</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireRdy</span> <span id=t_kwd>or</span> <span id=t_idt>processTxByteRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16UpdateRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5UpdateRdy</span> <span id=t_kwd>or</span> <span id=t_idt>processTxByteWEn</span> <span id=t_kwd>or</span> <span id=t_idt>TxByteOut</span> <span id=t_kwd>or</span> <span id=t_idt>TxByteOutCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireData</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireReq</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireWEn</span> <span id=t_kwd>or</span> <span id=t_idt>rstCRC</span> <span id=t_kwd>or</span> <span id=t_idt>CRCData</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5En</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5_8Bit</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16En</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortTxRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_SIETx</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SIETx_NextState</span>
+  <span id=t_idt>NextState_SIETx</span> &lt;= <span id=t_idt>CurrState_SIETx</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_idt>processTxByteWEn</span>;
+  <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>TxByteOut</span>;
+  <span id=t_idt>next_TxByteOutCtrl</span> &lt;= <span id=t_idt>TxByteOutCtrl</span>;
+  <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>USBWireData</span>;
+  <span id=t_idt>next_USBWireCtrl</span> &lt;= <span id=t_idt>USBWireCtrl</span>;
+  <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_idt>USBWireReq</span>;
+  <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_idt>USBWireWEn</span>;
+  <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_idt>rstCRC</span>;
+  <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>CRCData</span>;
+  <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_idt>CRC5En</span>;
+  <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_idt>CRC5_8Bit</span>;
+  <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_idt>CRC16En</span>;
+  <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_idt>SIEPortTxRdy</span>;
+  <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortData</span>;
+  <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrl</span>;
+  <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_SIETx</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SIETX</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_TxByteOutCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_i</span> &lt;= <span id=t_cns>5'h0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STX_CHK_ST</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_PACKET_START</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_WAIT_GNT</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_IDLE</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>IDLE_STX_WAIT_GNT</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_DIRECT_CONTROL</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>DIR_CTL_WAIT_GNT</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_RESUME_START</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_WAIT_GNT</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_i</span> &lt;= <span id=t_cns>5'h0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>STX_WAIT_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_CHK_ST</span>;
+      <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortDataIn</span>;
+      <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrlIn</span>;
+      <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DIR_CTL_CHK_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>5'h7</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>DIR_CTL_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DIR_CTL_WAIT_GNT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_i</span> &lt;= <span id=t_cns>5'h0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>DIR_CTL_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DIR_CTL_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>DIR_CTL_CHK_FIN</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>];
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_CHK_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>5'h7</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>IDLE_STX_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_STX_WAIT_GNT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_i</span> &lt;= <span id=t_cns>5'h0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>IDLE_STX_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_STX_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>IDLE_CHK_FIN</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_CHK_PID</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>HANDSHAKE</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_HS_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>TOKEN</span>) 
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_PID_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>SPECIAL</span>) 
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>DATA</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_PID_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_WAIT_RDY_PKT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_CHK_PID</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= `<span id=t_idt>SYNC_BYTE</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_START</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_WAIT_RDY_WIRE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_WAIT_RDY_PKT</span>;
+      <span id=t_com>//actively drive the first J bit</span>
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_WAIT_RDY_WIRE</span>;
+   `<span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY2</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT1</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= ~<span id=t_idt>CRC16Result</span>[<span id=t_cns>7</span>:<span id=t_cns>0</span>];
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT2</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= ~<span id=t_idt>CRC16Result</span>[<span id=t_cns>15</span>:<span id=t_cns>8</span>];
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_CHK_STOP</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_PACKET_STOP</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_CRC_RDY</span>;
+   `<span id=t_idt>PKT_ST_DATA_DATA_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_UPD_CRC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>SIEPortData</span>;
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_CHK_STOP</span>;
+      <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortDataIn</span>;
+      <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrlIn</span>;
+      <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_CRC_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC16UpdateRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_UPD_CRC</span>;
+   `<span id=t_idt>PKT_ST_DATA_PID_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_PID_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_PID_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+      <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_HS_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_HS_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_HS_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_WAIT_WIRE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE2</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE3</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE3</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_WAIT_WIRE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_PKT_SENT1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_UPD_CRC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>SIEPortData</span>;
+     <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_CRC_RDY</span>;
+      <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortDataIn</span>;
+      <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrlIn</span>;
+      <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_PKT_SENT1</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_CRC_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC5UpdateRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_UPD_CRC</span>;
+   `<span id=t_idt>PKT_ST_TKN_CRC_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_CRC_UPD_CRC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>SIEPortData</span>;
+     <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_CRC_RDY</span>;
+      <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortDataIn</span>;
+      <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrlIn</span>;
+      <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= {~<span id=t_idt>CRC5Result</span>, <span id=t_idt>SIEPortData</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>] };
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_CRC_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC5UpdateRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_UPD_CRC</span>;
+   `<span id=t_idt>PKT_ST_TKN_PID_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_PID_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_PID_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+      <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_CHK_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>i</span> == `<span id=t_idt>RESUME_LEN</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S3</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= `<span id=t_idt>SE0</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S3</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S4</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= `<span id=t_idt>SE0</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S4</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S5</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S5</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S6</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S6</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_WAIT_RDY</span>;
+   `<span id=t_idt>RES_ST_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_CHK_FIN</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>KBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SIETx_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_SIETx</span> &lt;= `<span id=t_idt>START_SIETX</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_SIETx</span> &lt;= <span id=t_idt>NextState_SIETx</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SIETx_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SIEPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>SIEPortCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>i</span> &lt;= <span id=t_cns>5'h0</span>;
+   <span id=t_idt>processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>TxByteOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>TxByteOutCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+   <span id=t_idt>USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRCData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SIEPortData</span> &lt;= <span id=t_idt>next_SIEPortData</span>;
+   <span id=t_idt>SIEPortCtrl</span> &lt;= <span id=t_idt>next_SIEPortCtrl</span>;
+   <span id=t_idt>i</span> &lt;= <span id=t_idt>next_i</span>;
+   <span id=t_idt>processTxByteWEn</span> &lt;= <span id=t_idt>next_processTxByteWEn</span>;
+   <span id=t_idt>TxByteOut</span> &lt;= <span id=t_idt>next_TxByteOut</span>;
+   <span id=t_idt>TxByteOutCtrl</span> &lt;= <span id=t_idt>next_TxByteOutCtrl</span>;
+   <span id=t_idt>USBWireData</span> &lt;= <span id=t_idt>next_USBWireData</span>;
+   <span id=t_idt>USBWireCtrl</span> &lt;= <span id=t_idt>next_USBWireCtrl</span>;
+   <span id=t_idt>USBWireReq</span> &lt;= <span id=t_idt>next_USBWireReq</span>;
+   <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_idt>next_USBWireWEn</span>;
+   <span id=t_idt>rstCRC</span> &lt;= <span id=t_idt>next_rstCRC</span>;
+   <span id=t_idt>CRCData</span> &lt;= <span id=t_idt>next_CRCData</span>;
+   <span id=t_idt>CRC5En</span> &lt;= <span id=t_idt>next_CRC5En</span>;
+   <span id=t_idt>CRC5_8Bit</span> &lt;= <span id=t_idt>next_CRC5_8Bit</span>;
+   <span id=t_idt>CRC16En</span> &lt;= <span id=t_idt>next_CRC16En</span>;
+   <span id=t_idt>SIEPortTxRdy</span> &lt;= <span id=t_idt>next_SIEPortTxRdy</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_DIR_CTL.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_DIR_CTL.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_PKT_ST.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_PKT_ST.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter" alt="SIETransmitter"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram359.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram359.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram359.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter PKT_ST" alt="SIETransmitter PKT_ST"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram359.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram483.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram483.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram483.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter TKN" alt="SIETransmitter TKN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram483.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter DATA" alt="SIETransmitter DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_DATA.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_PID.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_PID.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_TKN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_TKN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter IDLE" alt="SIETransmitter IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter HS" alt="SIETransmitter HS"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter CRC" alt="SIETransmitter CRC"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar213.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram213.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar465.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram465.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar617.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram617.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar16.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram16.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar455.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram455.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar609.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram609.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index359.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index359.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index359.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar359.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram359.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index359.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar483.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram483.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar717.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram717.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_SPCL.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_SPCL.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter DIR_CTL" alt="SIETransmitter DIR_CTL"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter DATA" alt="SIETransmitter DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter BYTE1" alt="SIETransmitter BYTE1"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter CRC" alt="SIETransmitter CRC"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar216.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram216.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar474.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram474.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar626.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram626.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar720.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram720.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 216 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 474 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_HS.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 626 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_CRC.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm	(revision 264)
@@ -0,0 +1,94 @@
+<html>
+<head>
+<title>lineControlUpdate.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// lineControlUpdate.v                                          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:14 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>lineControlUpdate</span>(<span id=t_idt>fullSpeedPolarity</span>, <span id=t_idt>fullSpeedBitRate</span>, <span id=t_idt>JBit</span>, <span id=t_idt>KBit</span>);
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedBitRate</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRate</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+
+
+
+<span id=t_kwd>always</span> @(<span id=t_idt>fullSpeedPolarity</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>fullSpeedPolarity</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+      <span id=t_idt>JBit</span> = `<span id=t_idt>ONE_ZERO</span>;
+      <span id=t_idt>KBit</span> = `<span id=t_idt>ZERO_ONE</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+      <span id=t_idt>JBit</span> = `<span id=t_idt>ZERO_ONE</span>;
+      <span id=t_idt>KBit</span> = `<span id=t_idt>ONE_ZERO</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit IDLE" alt="processRxBit IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar718.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram718.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 213 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_DIR_CTL.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html	(revision 264)
@@ -0,0 +1,54 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 3;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(848,524,951,626,Click718,Over718);
+FUB[1] = new Array(866,923,969,1025,Click717,Over717);
+FUB[2] = new Array(856,1388,958,1490,Click720,Over720);
+
+//----------------------------------------------------------------------------
+function Click718(){fubclick('./index718.htm');}
+function Over718(){window.status='Hierarchical State PID';};
+function Click717(){fubclick('./index717.htm');}
+function Over717(){window.status='Hierarchical State DATA';};
+function Click720(){fubclick('./index720.htm');}
+function Over720(){window.status='Hierarchical State CRC';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 465 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 617 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_BYTE1.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 720 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_CRC.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit ERROR" alt="processRxBit ERROR"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit RES_END" alt="processRxBit RES_END"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 16 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_RES_ST.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 455 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_SPCL.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 609 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 718 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit BYTE" alt="processRxBit BYTE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit RES_RX" alt="processRxBit RES_RX"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit DATA" alt="processRxBit DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar16.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram16.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar97.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram97.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar115.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram115.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar42.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram42.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_BYTE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_BYTE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(857,1179,959,1281,Click16,Over16);
+FUB[1] = new Array(864,1384,966,1486,Click359,Over359);
+FUB[2] = new Array(841,912,944,1014,Click216,Over216);
+FUB[3] = new Array(845,1042,948,1144,Click213,Over213);
+
+//----------------------------------------------------------------------------
+function Click16(){fubclick('./index16.htm');}
+function Over16(){window.status='Hierarchical State RES_ST';};
+function Click359(){fubclick('./index359.htm');}
+function Over359(){window.status='Hierarchical State PKT_ST';};
+function Click216(){fubclick('./index216.htm');}
+function Over216(){window.status='Hierarchical State IDLE';};
+function Click213(){fubclick('./index213.htm');}
+function Over213(){window.status='Hierarchical State DIR_CTL';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(990,1164,1092,1266,Click455,Over455);
+FUB[1] = new Array(1010,1864,1112,1966,Click465,Over465);
+FUB[2] = new Array(1005,1606,1107,1708,Click474,Over474);
+FUB[3] = new Array(1007,1335,1110,1437,Click483,Over483);
+
+//----------------------------------------------------------------------------
+function Click455(){fubclick('./index455.htm');}
+function Over455(){window.status='Hierarchical State SPCL';};
+function Click465(){fubclick('./index465.htm');}
+function Over465(){window.status='Hierarchical State DATA';};
+function Click474(){fubclick('./index474.htm');}
+function Over474(){window.status='Hierarchical State HS';};
+function Click483(){fubclick('./index483.htm');}
+function Over483(){window.status='Hierarchical State TKN';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 359 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_PKT_ST.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html	(revision 264)
@@ -0,0 +1,54 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 3;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(847,986,949,1089,Click617,Over617);
+FUB[1] = new Array(829,587,931,690,Click609,Over609);
+FUB[2] = new Array(836,1451,938,1553,Click626,Over626);
+
+//----------------------------------------------------------------------------
+function Click617(){fubclick('./index617.htm');}
+function Over617(){window.status='Hierarchical State BYTE1';};
+function Click609(){fubclick('./index609.htm');}
+function Over609(){window.status='Hierarchical State PID';};
+function Click626(){fubclick('./index626.htm');}
+function Over626(){window.status='Hierarchical State CRC';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 483 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_TKN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 717 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit" alt="processRxBit"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit DATA_RX" alt="processRxBit DATA_RX"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar24.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram24.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA_RX.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA_RX.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_END.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_END.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 115 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_ERROR.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 42 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_RES_END.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte FIRST_BYTE" alt="processRxByte FIRST_BYTE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte TOKEN" alt="processRxByte TOKEN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_IDLE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_IDLE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 113 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_BYTE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 33 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_RES_RX.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte CHK_PID" alt="processRxByte CHK_PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte HSHAKE" alt="processRxByte HSHAKE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar16.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram16.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar113.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram113.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar33.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram33.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm	(revision 264)
@@ -0,0 +1,415 @@
+<html>
+<head>
+<title>processRxBit.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// processRxBit</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:23 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>processRxBit</span> (<span id=t_idt>JBit</span>, <span id=t_idt>KBit</span>, <span id=t_idt>RxBitsIn</span>, <span id=t_idt>RxCtrlOut</span>, <span id=t_idt>RxDataOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>processRxBitRdy</span>, <span id=t_idt>processRxBitsWEn</span>, <span id=t_idt>processRxByteRdy</span>, <span id=t_idt>processRxByteWEn</span>, <span id=t_idt>resumeDetected</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processRxBitsWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processRxByteRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processRxBitRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processRxByteWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>resumeDetected</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsIn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>, <span id=t_idt>next_RxCtrlOut</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>, <span id=t_idt>next_RxDataOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processRxBitRdy</span>, <span id=t_idt>next_processRxBitRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processRxBitsWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processRxByteRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processRxByteWEn</span>, <span id=t_idt>next_processRxByteWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>resumeDetected</span>, <span id=t_idt>next_resumeDetected</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>RXBitCount</span>, <span id=t_idt>next_RXBitCount</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>RXBitStMachCurrState</span>, <span id=t_idt>next_RXBitStMachCurrState</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByte</span>, <span id=t_idt>next_RXByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>RXSameBitCount</span>, <span id=t_idt>next_RXSameBitCount</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>RxBits</span>, <span id=t_idt>next_RxBits</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>bitStuffError</span>, <span id=t_idt>next_bitStuffError</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>oldRXBits</span>, <span id=t_idt>next_oldRXBits</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>resumeWaitCnt</span>, <span id=t_idt>next_resumeWaitCnt</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: prRxBit</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_FIRST_BIT</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BITS</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_CHK_KBIT</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_LAST_BIT</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_CHK_SE0</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_DATA_DESTUFF</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_BYTE_SEND2</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_BYTE_WAIT_RDY</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_RX_CHK</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_ERROR_CHK_RES</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_END_CHK1</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_PRB_RDY</span> <span id=t_cns>4'b1100</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_WAIT_PRB_RDY</span> <span id=t_cns>4'b1101</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_ERROR_WAIT_RDY</span> <span id=t_cns>4'b1110</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_prRxBit</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_prRxBit</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: prRxBit</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RxBitsIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxBits</span> <span id=t_kwd>or</span> <span id=t_idt>oldRXBits</span> <span id=t_kwd>or</span> <span id=t_idt>RXSameBitCount</span> <span id=t_kwd>or</span> <span id=t_idt>RXBitCount</span> <span id=t_kwd>or</span> <span id=t_idt>RXByte</span> <span id=t_kwd>or</span> <span id=t_idt>JBit</span> <span id=t_kwd>or</span> <span id=t_idt>KBit</span> <span id=t_kwd>or</span> <span id=t_idt>resumeWaitCnt</span> <span id=t_kwd>or</span> <span id=t_idt>processRxBitsWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXBitStMachCurrState</span> <span id=t_kwd>or</span> <span id=t_idt>processRxByteRdy</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>processRxByteWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RxCtrlOut</span> <span id=t_kwd>or</span> <span id=t_idt>RxDataOut</span> <span id=t_kwd>or</span> <span id=t_idt>resumeDetected</span> <span id=t_kwd>or</span> <span id=t_idt>processRxBitRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_prRxBit</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxBit_NextState</span>
+  <span id=t_idt>NextState_prRxBit</span> &lt;= <span id=t_idt>CurrState_prRxBit</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_idt>processRxByteWEn</span>;
+  <span id=t_idt>next_RxCtrlOut</span> &lt;= <span id=t_idt>RxCtrlOut</span>;
+  <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxDataOut</span>;
+  <span id=t_idt>next_resumeDetected</span> &lt;= <span id=t_idt>resumeDetected</span>;
+  <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= <span id=t_idt>RXBitStMachCurrState</span>;
+  <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBits</span>;
+  <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_idt>RXSameBitCount</span>;
+  <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_idt>RXBitCount</span>;
+  <span id=t_idt>next_oldRXBits</span> &lt;= <span id=t_idt>oldRXBits</span>;
+  <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXByte</span>;
+  <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>bitStuffError</span>;
+  <span id=t_idt>next_resumeWaitCnt</span> &lt;= <span id=t_idt>resumeWaitCnt</span>;
+  <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_idt>processRxBitRdy</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_prRxBit</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxCtrlOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_resumeDetected</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+     <span id=t_idt>next_RxBits</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>next_oldRXBits</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_resumeWaitCnt</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_BITS</span>:
+     <span id=t_kwd>if</span> ((<span id=t_idt>processRxBitsWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXBitStMachCurrState</span> == `<span id=t_idt>WAIT_RESUME_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>RES_RX_CHK</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>processRxBitsWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXBitStMachCurrState</span> == `<span id=t_idt>DATA_RECEIVE_BIT_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_CHK_SE0</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>processRxBitsWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXBitStMachCurrState</span> == `<span id=t_idt>IDLE_BIT_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>IDLE_CHK_KBIT</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>processRxBitsWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXBitStMachCurrState</span> == `<span id=t_idt>RESUME_END_WAIT_ST</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>RES_END_CHK1</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_FIRST_BIT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>DATA_RECEIVE_BIT_ST</span>;
+     <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_cns>4'h1</span>;
+     <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_cns>4'h1</span>;
+     <span id=t_idt>next_oldRXBits</span> &lt;= <span id=t_idt>RxBits</span>;
+     <span id=t_com>//zero is always the first RZ data bit of a new packet</span>
+     <span id=t_idt>next_RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_CHK_KBIT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == <span id=t_idt>KBit</span>)  
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>IDLE_WAIT_PRB_RDY</span>;
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_WAIT_PRB_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>IDLE_FIRST_BIT</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_com>//redundant data</span>
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>DATA_START</span>;
+      <span id=t_com>//start of packet</span>
+      <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_LAST_BIT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_CHK_SE0</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)  
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_WAIT_PRB_RDY</span>;
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_DATA_DESTUFF</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == <span id=t_idt>oldRXBits</span>)                 <span id=t_com>//if the current 'RxBits' are the same as the old 'RxBits', then</span>
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_idt>RXSameBitCount</span> + <span id=t_cns>1'b1</span>;
+          <span id=t_com>//inc 'RXSameBitCount'</span>
+          <span id=t_kwd>if</span> (<span id=t_idt>RXSameBitCount</span> == `<span id=t_idt>MAX_CONSEC_SAME_BITS</span>) <span id=t_com>//if 'RXSameBitCount' == 7 there has been a bit stuff error</span>
+          <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b1</span>;
+              <span id=t_com>//flag 'bitStuffError'</span>
+          <span id=t_kwd>else</span>                                          <span id=t_com>//else no bit stuffing error</span>
+          <span id=t_kwd>begin</span>
+          <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_idt>RXBitCount</span> + <span id=t_cns>1'b1</span>;
+              <span id=t_kwd>if</span> (<span id=t_idt>RXBitCount</span> != <span id=t_cns>4'h7</span>) <span id=t_kwd>begin</span>
+            <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+                  <span id=t_com>//early indication of ready</span>
+         <span id=t_kwd>end</span>
+          <span id=t_idt>next_RXByte</span> &lt;= { <span id=t_cns>1'b1</span>, <span id=t_idt>RXByte</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>]};
+              <span id=t_com>//RZ bit = 1 (ie no change in 'RxBits')</span>
+          <span id=t_kwd>end</span>
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span>                                            <span id=t_com>//else current 'RxBits' are different from old 'RxBits'</span>
+      <span id=t_kwd>begin</span>
+          <span id=t_kwd>if</span> (<span id=t_idt>RXSameBitCount</span> != `<span id=t_idt>MAX_CONSEC_SAME_BITS</span>)  <span id=t_com>//if this is not the RZ 0 bit after 6 consecutive RZ 1s, then</span>
+          <span id=t_kwd>begin</span>
+          <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_idt>RXBitCount</span> + <span id=t_cns>1'b1</span>;
+              <span id=t_kwd>if</span> (<span id=t_idt>RXBitCount</span> != <span id=t_cns>4'h7</span>) <span id=t_kwd>begin</span>
+            <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+                  <span id=t_com>//early indication of ready</span>
+         <span id=t_kwd>end</span>
+          <span id=t_idt>next_RXByte</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>RXByte</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>]};
+              <span id=t_com>//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')</span>
+          <span id=t_kwd>end</span>
+        <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_cns>4'h1</span>;
+          <span id=t_com>//reset 'RXSameBitCount'</span>
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_oldRXBits</span> &lt;= <span id=t_idt>RxBits</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_WAIT_PRB_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_LAST_BIT</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_com>//redundant data</span>
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+      <span id=t_com>//end of packet</span>
+      <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_DATA_DESTUFF</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXBitCount</span> == <span id=t_cns>4'h8</span> &amp; <span id=t_idt>bitStuffError</span> == <span id=t_cns>1'b0</span>)  
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_BYTE_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>bitStuffError</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_ERROR_WAIT_RDY</span>;
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_BYTE_SEND2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_BYTE_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_BYTE_SEND2</span>;
+      <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RXByte</span>;
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+      <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_ERROR_CHK_RES</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == <span id=t_idt>JBit</span>)                           <span id=t_com>//if current bit is a JBit, then</span>
+       <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+         <span id=t_com>//next state is idle</span>
+     <span id=t_kwd>else</span>                                          <span id=t_com>//else</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_RESUME_ST</span>;
+         <span id=t_com>//check for resume</span>
+       <span id=t_idt>next_resumeWaitCnt</span> &lt;= <span id=t_cns>0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_ERROR_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_ERROR_CHK_RES</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_com>//redundant data</span>
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>DATA_BIT_STUFF_ERROR</span>;
+      <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_RX_CHK</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> != <span id=t_idt>KBit</span>)  <span id=t_com>//can only be a resume if line remains in Kbit state</span>
+       <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_resumeWaitCnt</span> &lt;= <span id=t_idt>resumeWaitCnt</span> + <span id=t_cns>1'b1</span>;
+         <span id=t_com>//if we've waited long enough, then</span>
+         <span id=t_kwd>if</span> (<span id=t_idt>resumeWaitCnt</span> == `<span id=t_idt>RESUME_WAIT_TIME_MINUS1</span>)
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>RESUME_END_WAIT_ST</span>;
+         <span id=t_idt>next_resumeDetected</span> &lt;= <span id=t_cns>1'b1</span>;
+             <span id=t_com>//report resume detected</span>
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_END_CHK1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> != <span id=t_idt>KBit</span>)  <span id=t_com>//line must leave KBit state for the end of resume</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+       <span id=t_idt>next_resumeDetected</span> &lt;= <span id=t_cns>1'b0</span>;
+         <span id=t_com>//clear resume detected flag</span>
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxBit_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_prRxBit</span> &lt;= `<span id=t_idt>START</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_prRxBit</span> &lt;= <span id=t_idt>NextState_prRxBit</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxBit_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+   <span id=t_idt>RxBits</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>RXSameBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>RXBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>oldRXBits</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>resumeWaitCnt</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RxCtrlOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>resumeDetected</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXBitStMachCurrState</span> &lt;= <span id=t_idt>next_RXBitStMachCurrState</span>;
+   <span id=t_idt>RxBits</span> &lt;= <span id=t_idt>next_RxBits</span>;
+   <span id=t_idt>RXSameBitCount</span> &lt;= <span id=t_idt>next_RXSameBitCount</span>;
+   <span id=t_idt>RXBitCount</span> &lt;= <span id=t_idt>next_RXBitCount</span>;
+   <span id=t_idt>oldRXBits</span> &lt;= <span id=t_idt>next_oldRXBits</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_idt>next_RXByte</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_idt>next_bitStuffError</span>;
+   <span id=t_idt>resumeWaitCnt</span> &lt;= <span id=t_idt>next_resumeWaitCnt</span>;
+   <span id=t_idt>processRxByteWEn</span> &lt;= <span id=t_idt>next_processRxByteWEn</span>;
+   <span id=t_idt>RxCtrlOut</span> &lt;= <span id=t_idt>next_RxCtrlOut</span>;
+   <span id=t_idt>RxDataOut</span> &lt;= <span id=t_idt>next_RxDataOut</span>;
+   <span id=t_idt>resumeDetected</span> &lt;= <span id=t_idt>next_resumeDetected</span>;
+   <span id=t_idt>processRxBitRdy</span> &lt;= <span id=t_idt>next_processRxBitRdy</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_ERROR.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_ERROR.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(868,1404,970,1507,Click24,Over24);
+FUB[1] = new Array(862,1179,965,1281,Click16,Over16);
+FUB[2] = new Array(892,1858,994,1961,Click42,Over42);
+FUB[3] = new Array(879,1639,981,1741,Click33,Over33);
+
+//----------------------------------------------------------------------------
+function Click24(){fubclick('./index24.htm');}
+function Over24(){window.status='Hierarchical State DATA_RX';};
+function Click16(){fubclick('./index16.htm');}
+function Over16(){window.status='Hierarchical State IDLE';};
+function Click42(){fubclick('./index42.htm');}
+function Over42(){window.status='Hierarchical State RES_END';};
+function Click33(){fubclick('./index33.htm');}
+function Over33(){window.status='Hierarchical State RES_RX';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar24.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar24.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar24.html	(revision 264)
@@ -0,0 +1,54 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 3;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(471,1029,574,1132,Click97,Over97);
+FUB[1] = new Array(274,1611,376,1714,Click113,Over113);
+FUB[2] = new Array(865,1611,967,1714,Click115,Over115);
+
+//----------------------------------------------------------------------------
+function Click97(){fubclick('./index97.htm');}
+function Over97(){window.status='Hierarchical State DATA';};
+function Click113(){fubclick('./index113.htm');}
+function Over113(){window.status='Hierarchical State BYTE';};
+function Click115(){fubclick('./index115.htm');}
+function Over115(){window.status='Hierarchical State ERROR';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 24 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_DATA_RX.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar24.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte" alt="processRxByte"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram216.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram216.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram216.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte IDLE" alt="processRxByte IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram216.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar18.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram18.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar33.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram33.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_CHK_PID.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_CHK_PID.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_HSHAKE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_HSHAKE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar24.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram24.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_RX.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_RX.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 16 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 97 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram213.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram213.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram213.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte CHK_SYNC" alt="processRxByte CHK_SYNC"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram213.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram42.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram42.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram42.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte DATA" alt="processRxByte DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram42.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar213.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram213.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar16.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar16.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar16.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(808,925,911,1027,Click18,Over18);
+
+//----------------------------------------------------------------------------
+function Click18(){fubclick('./index18.htm');}
+function Over18(){window.status='Hierarchical State FIRST_BYTE';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 16 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_CHK_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index216.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index216.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index216.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar216.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram216.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index216.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_DATA.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_TOKEN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_TOKEN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar213.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar213.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar213.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 213 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_CHK_SYNC.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar213.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar42.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar42.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar42.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 42 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar42.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar24.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar24.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar24.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 24 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_HSHAKE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar24.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram874.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram874.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram874.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processTxByte SEND_BYTE" alt="processTxByte SEND_BYTE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram874.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
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+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram887.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
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+</frameset>
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm	(revision 264)
@@ -0,0 +1,351 @@
+<html>
+<head>
+<title>processTxByte.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// processTxByte</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:39 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>processTxByte</span> (<span id=t_idt>JBit</span>, <span id=t_idt>KBit</span>, <span id=t_idt>TxByteCtrlIn</span>, <span id=t_idt>TxByteIn</span>, <span id=t_idt>USBWireCtrl</span>, <span id=t_idt>USBWireData</span>, <span id=t_idt>USBWireGnt</span>, <span id=t_idt>USBWireRdy</span>, <span id=t_idt>USBWireReq</span>, <span id=t_idt>USBWireWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>processTxByteRdy</span>, <span id=t_idt>processTxByteWEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteCtrlIn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processTxByteWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireCtrl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processTxByteRdy</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteCtrlIn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireCtrl</span>, <span id=t_idt>next_USBWireCtrl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireData</span>, <span id=t_idt>next_USBWireData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireReq</span>, <span id=t_idt>next_USBWireReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireWEn</span>, <span id=t_idt>next_USBWireWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processTxByteRdy</span>, <span id=t_idt>next_processTxByteRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processTxByteWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>TXLineState</span>, <span id=t_idt>next_TXLineState</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>TXOneCount</span>, <span id=t_idt>next_TXOneCount</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>TxByteCtrl</span>, <span id=t_idt>next_TxByteCtrl</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>TxByte</span>, <span id=t_idt>next_TxByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>i</span>, <span id=t_idt>next_i</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: prcTxB</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_PTBY</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PTBY_WAIT_EN</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_UPDATE_BYTE</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_WAIT_RDY</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_CHK</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_BIT_STUFF</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_WAIT_RDY2</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_CHK_FIN</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PTBY_WAIT_GNT</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_SND_SE0_2</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_SND_SE0_1</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_CHK</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_SND_J</span> <span id=t_cns>4'b1100</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_SND_IDLE</span> <span id=t_cns>4'b1101</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_FIN</span> <span id=t_cns>4'b1110</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_prcTxB</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_prcTxB</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: prcTxB</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>TxByteIn</span> <span id=t_kwd>or</span> <span id=t_idt>TxByteCtrlIn</span> <span id=t_kwd>or</span> <span id=t_idt>JBit</span> <span id=t_kwd>or</span> <span id=t_idt>i</span> <span id=t_kwd>or</span> <span id=t_idt>TxByte</span> <span id=t_kwd>or</span> <span id=t_idt>TXOneCount</span> <span id=t_kwd>or</span> <span id=t_idt>TXLineState</span> <span id=t_kwd>or</span> <span id=t_idt>KBit</span> <span id=t_kwd>or</span> <span id=t_idt>processTxByteWEn</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireGnt</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireRdy</span> <span id=t_kwd>or</span> <span id=t_idt>TxByteCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>processTxByteRdy</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireData</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireReq</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireWEn</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_prcTxB</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prcTxB_NextState</span>
+  <span id=t_idt>NextState_prcTxB</span> &lt;= <span id=t_idt>CurrState_prcTxB</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_idt>processTxByteRdy</span>;
+  <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>USBWireData</span>;
+  <span id=t_idt>next_USBWireCtrl</span> &lt;= <span id=t_idt>USBWireCtrl</span>;
+  <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_idt>USBWireReq</span>;
+  <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_idt>USBWireWEn</span>;
+  <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span>;
+  <span id=t_idt>next_TxByte</span> &lt;= <span id=t_idt>TxByte</span>;
+  <span id=t_idt>next_TxByteCtrl</span> &lt;= <span id=t_idt>TxByteCtrl</span>;
+  <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>TXLineState</span>;
+  <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_idt>TXOneCount</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_prcTxB</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_PTBY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_i</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>next_TxByte</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_TxByteCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_cns>2'b0</span>;
+     <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>PTBY_WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PTBY_WAIT_EN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> ((<span id=t_idt>processTxByteWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>TxByteCtrlIn</span> == `<span id=t_idt>DATA_START</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>PTBY_WAIT_GNT</span>;
+      <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_TxByte</span> &lt;= <span id=t_idt>TxByteIn</span>;
+      <span id=t_idt>next_TxByteCtrl</span> &lt;= <span id=t_idt>TxByteCtrlIn</span>;
+      <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_cns>1</span>;
+      <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>processTxByteWEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>;
+      <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_TxByte</span> &lt;= <span id=t_idt>TxByteIn</span>;
+      <span id=t_idt>next_TxByteCtrl</span> &lt;= <span id=t_idt>TxByteCtrlIn</span>;
+      <span id=t_idt>next_i</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PTBY_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>;
+      <span id=t_idt>next_i</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_TxByte</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxByte</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>] };
+     <span id=t_kwd>if</span> (<span id=t_idt>TxByte</span>[<span id=t_cns>0</span>] == <span id=t_cns>1'b1</span>)                      <span id=t_com>//If this bit is 1, then</span>
+       <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_idt>TXOneCount</span> + <span id=t_cns>1'b1</span>;
+         <span id=t_com>//increment 'TXOneCount'</span>
+     <span id=t_kwd>else</span>                                        <span id=t_com>//else this is a zero bit</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_cns>4'h1</span>;
+         <span id=t_com>//reset 'TXOneCount'</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>TXLineState</span> == <span id=t_idt>JBit</span>) <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>KBit</span>;
+         <span id=t_com>//toggle the line state</span>
+       <span id=t_kwd>else</span> <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>JBit</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_CHK</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>TXLineState</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_CHK</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>TXOneCount</span> == <span id=t_cns>4'h6</span>)  
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_BIT_STUFF</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>i</span> != <span id=t_cns>4'h8</span>)  
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_CHK</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_BIT_STUFF</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_cns>4'h1</span>;
+     <span id=t_com>//reset 'TXOneCount'</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>TXLineState</span> == <span id=t_idt>JBit</span>) <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>KBit</span>;
+     <span id=t_com>//toggle the line state</span>
+     <span id=t_kwd>else</span> <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>JBit</span>;
+     <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_WAIT_RDY2</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_WAIT_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_CHK_FIN</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>TXLineState</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_CHK_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>4'h8</span>) 
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_CHK</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_SND_SE0_2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_SND_J</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= `<span id=t_idt>SE0</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_SND_SE0_1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_SND_SE0_2</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= `<span id=t_idt>SE0</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_CHK</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>TxByteCtrl</span> == `<span id=t_idt>DATA_STOP</span>)  
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_SND_SE0_1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>PTBY_WAIT_EN</span>;
+   `<span id=t_idt>STOP_SND_J</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_SND_IDLE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_SND_IDLE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_FIN</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_com>//release the wire</span>
+     <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>PTBY_WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prcTxB_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_prcTxB</span> &lt;= `<span id=t_idt>START_PTBY</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_prcTxB</span> &lt;= <span id=t_idt>NextState_prcTxB</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prcTxB_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>TxByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>TxByteCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>TXLineState</span> &lt;= <span id=t_cns>2'b0</span>;
+   <span id=t_idt>TXOneCount</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>processTxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+   <span id=t_idt>USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>i</span> &lt;= <span id=t_idt>next_i</span>;
+   <span id=t_idt>TxByte</span> &lt;= <span id=t_idt>next_TxByte</span>;
+   <span id=t_idt>TxByteCtrl</span> &lt;= <span id=t_idt>next_TxByteCtrl</span>;
+   <span id=t_idt>TXLineState</span> &lt;= <span id=t_idt>next_TXLineState</span>;
+   <span id=t_idt>TXOneCount</span> &lt;= <span id=t_idt>next_TXOneCount</span>;
+   <span id=t_idt>processTxByteRdy</span> &lt;= <span id=t_idt>next_processTxByteRdy</span>;
+   <span id=t_idt>USBWireData</span> &lt;= <span id=t_idt>next_USBWireData</span>;
+   <span id=t_idt>USBWireCtrl</span> &lt;= <span id=t_idt>next_USBWireCtrl</span>;
+   <span id=t_idt>USBWireReq</span> &lt;= <span id=t_idt>next_USBWireReq</span>;
+   <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_idt>next_USBWireWEn</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index42.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index42.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/index42.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar42.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram42.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

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+*
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===================================================================
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+*
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+application/octet-stream
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===================================================================
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+*
\ No newline at end of property
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
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===================================================================
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+*
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+application/octet-stream
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm	(revision 264)
@@ -0,0 +1,210 @@
+<html>
+<head>
+<title>readUSBWireData.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// readUSBWireData.v                                            ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:39 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>readUSBWireData</span> (<span id=t_idt>RxBitsIn</span>, <span id=t_idt>RxDataInTick</span>, <span id=t_idt>RxBitsOut</span>, <span id=t_idt>SIERxRdyIn</span>, <span id=t_idt>SIERxWEn</span>, <span id=t_idt>fullSpeedRate</span>, <span id=t_idt>disableWireRead</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsIn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RxDataInTick</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIERxRdyIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>disableWireRead</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SIERxWEn</span>;
+
+<span id=t_kwd>wire</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsIn</span>;
+<span id=t_kwd>reg</span>    <span id=t_idt>RxDataInTick</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>SIERxRdyIn</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsOut</span>;
+<span id=t_kwd>reg</span>    <span id=t_idt>SIERxWEn</span>;
+
+<span id=t_com>// local registers</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer0</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer1</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer2</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer3</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferInIndex</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferOutIndex</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>decBufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>4</span>:<span id=t_cns>0</span>]<span id=t_idt>i</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>incBufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>oldRxBitsIn</span>;
+
+<span id=t_com>// buffer output state machine state codes:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BUFFER_NOT_EMPTY</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SIE_RX_READY</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>SIE_RX_WRITE</span> <span id=t_cns>2'b10</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>bufferOutStMachCurrState</span>;
+
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>bufferCnt</span> &lt;= <span id=t_cns>3'b000</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>incBufferCnt</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>decBufferCnt</span> == <span id=t_cns>1'b0</span>)
+      <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>incBufferCnt</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>decBufferCnt</span> == <span id=t_cns>1'b1</span>)
+      <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> - <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+
+<span id=t_com>//Perform line rate clock recovery</span>
+<span id=t_com>//Recover the wire data, and store data to buffer</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>i</span> &lt;= <span id=t_cns>5'b00000</span>;
+    <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer0</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer1</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer2</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer3</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>RxDataInTick</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;         <span id=t_com>//default value</span>
+    <span id=t_idt>oldRxBitsIn</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+    <span id=t_kwd>if</span> (<span id=t_idt>oldRxBitsIn</span> != <span id=t_idt>RxBitsIn</span>)  <span id=t_com>//if edge detected then</span>
+     <span id=t_idt>i</span> &lt;= <span id=t_cns>5'b00000</span>;              <span id=t_com>//reset the counter</span>
+    <span id=t_kwd>else</span>
+     <span id=t_idt>i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>if</span> ( (<span id=t_idt>fullSpeedRate</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>i</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == <span id=t_cns>2'b10</span>) || (<span id=t_idt>fullSpeedRate</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>i</span> == <span id=t_cns>5'b10000</span>) )
+    <span id=t_kwd>begin</span>
+      <span id=t_idt>RxDataInTick</span> &lt;= !<span id=t_idt>RxDataInTick</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>disableWireRead</span> != <span id=t_cns>1'b1</span>)  <span id=t_com>//do not read wire data when transmitter is active</span>
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b1</span>;
+       <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_idt>bufferInIndex</span> + <span id=t_cns>1'b1</span>;
+       <span id=t_kwd>case</span> (<span id=t_idt>bufferInIndex</span>)
+         <span id=t_cns>2'b00</span> : <span id=t_idt>buffer0</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+         <span id=t_cns>2'b01</span> : <span id=t_idt>buffer1</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+         <span id=t_cns>2'b10</span> : <span id=t_idt>buffer2</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+         <span id=t_cns>2'b11</span> : <span id=t_idt>buffer3</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+       <span id=t_kwd>endcase</span>
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+      
+
+<span id=t_com>//read from buffer, and output to SIEReceiver</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>SIERxWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_NOT_EMPTY</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>case</span> (<span id=t_idt>bufferOutStMachCurrState</span>)
+     `<span id=t_idt>WAIT_BUFFER_NOT_EMPTY</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span> != <span id=t_cns>3'b000</span>)
+        <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_SIE_RX_READY</span>;
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>WAIT_SIE_RX_READY</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>SIERxRdyIn</span> == <span id=t_cns>1'b1</span>)
+       <span id=t_kwd>begin</span> 
+        <span id=t_idt>SIERxWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>SIE_RX_WRITE</span>;
+        <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_idt>bufferOutIndex</span> + <span id=t_cns>1'b1</span>;
+        <span id=t_kwd>case</span> (<span id=t_idt>bufferOutIndex</span>)
+           <span id=t_cns>2'b00</span> :  <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>buffer0</span>;
+          <span id=t_cns>2'b01</span> : <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>buffer1</span>;
+          <span id=t_cns>2'b10</span> : <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>buffer2</span>;
+          <span id=t_cns>2'b11</span> : <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>buffer3</span>;
+        <span id=t_kwd>endcase</span>
+       <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>SIE_RX_WRITE</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>SIERxWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+       <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+       <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_NOT_EMPTY</span>;
+     <span id=t_kwd>end</span>
+    <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+     
+
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm	(revision 264)
@@ -0,0 +1,499 @@
+<html>
+<head>
+<title>processRxByte.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// processRxByte</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:34 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>processRxByte</span> (<span id=t_idt>CRC16En</span>, <span id=t_idt>CRC16Result</span>, <span id=t_idt>CRC16UpdateRdy</span>, <span id=t_idt>CRC5En</span>, <span id=t_idt>CRC5Result</span>, <span id=t_idt>CRC5UpdateRdy</span>, <span id=t_idt>CRC5_8Bit</span>, <span id=t_idt>CRCData</span>, <span id=t_idt>RxByteIn</span>, <span id=t_idt>RxCtrlIn</span>, <span id=t_idt>RxCtrlOut</span>, <span id=t_idt>RxDataOutWEn</span>, <span id=t_idt>RxDataOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>processRxByteRdy</span>, <span id=t_idt>processRxDataInWEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>rstCRC</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC16Result</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC16UpdateRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC5Result</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC5UpdateRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteIn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processRxDataInWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC16En</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC5En</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC5_8Bit</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCData</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RxDataOutWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processRxByteRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>rstCRC</span>;
+
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC16En</span>, <span id=t_idt>next_CRC16En</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC16Result</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>CRC16UpdateRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC5En</span>, <span id=t_idt>next_CRC5En</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC5Result</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>CRC5UpdateRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC5_8Bit</span>, <span id=t_idt>next_CRC5_8Bit</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCData</span>, <span id=t_idt>next_CRCData</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteIn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlIn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>, <span id=t_idt>next_RxCtrlOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RxDataOutWEn</span>, <span id=t_idt>next_RxDataOutWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>, <span id=t_idt>next_RxDataOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processRxByteRdy</span>, <span id=t_idt>next_processRxByteRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processRxDataInWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>rstCRC</span>, <span id=t_idt>next_rstCRC</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>ACKRxed</span>, <span id=t_idt>next_ACKRxed</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>CRCError</span>, <span id=t_idt>next_CRCError</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>NAKRxed</span>, <span id=t_idt>next_NAKRxed</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteStMachCurrState</span>, <span id=t_idt>next_RXByteStMachCurrState</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>9</span>:<span id=t_cns>0</span>]<span id=t_idt>RXDataByteCnt</span>, <span id=t_idt>next_RXDataByteCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RxByte</span>, <span id=t_idt>next_RxByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RxCtrl</span>, <span id=t_idt>next_RxCtrl</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>RxOverflow</span>, <span id=t_idt>next_RxOverflow</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RxStatus</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>RxTimeOut</span>, <span id=t_idt>next_RxTimeOut</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>Signal1</span>, <span id=t_idt>next_Signal1</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>bitStuffError</span>, <span id=t_idt>next_bitStuffError</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>dataSequence</span>, <span id=t_idt>next_dataSequence</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>stallRxed</span>, <span id=t_idt>next_stallRxed</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: prRxByte</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_ST</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_PRBY</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BYTE</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_CHK_START</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_SYNC_DO</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PID_DO_CHK</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PID_FIRST_BYTE_PROC</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>HSHAKE_FIN</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>HSHAKE_CHK</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN_CHK_STRM</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN_FIN</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_FIN</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_CHK_STRM</span> <span id=t_cns>4'b1100</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN_WAIT_CRC</span> <span id=t_cns>4'b1101</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_WAIT_CRC</span> <span id=t_cns>4'b1110</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_prRxByte</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_prRxByte</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_kwd>always</span> @
+(<span id=t_idt>next_CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>next_bitStuffError</span> <span id=t_kwd>or</span>
+  <span id=t_idt>next_RxOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>next_NAKRxed</span> <span id=t_kwd>or</span>
+  <span id=t_idt>next_stallRxed</span> <span id=t_kwd>or</span> <span id=t_idt>next_ACKRxed</span> <span id=t_kwd>or</span>
+  <span id=t_idt>next_dataSequence</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>RxStatus</span> &lt;=
+    {<span id=t_cns>1'b0</span>, <span id=t_idt>next_dataSequence</span>,
+    <span id=t_idt>next_ACKRxed</span>,
+    <span id=t_idt>next_stallRxed</span>, <span id=t_idt>next_NAKRxed</span>,
+    <span id=t_idt>next_RxOverflow</span>,
+    <span id=t_idt>next_bitStuffError</span>, <span id=t_idt>next_CRCError</span> };
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: prRxByte</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RxByteIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxCtrlIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>RxStatus</span> <span id=t_kwd>or</span> <span id=t_idt>RxByte</span> <span id=t_kwd>or</span> <span id=t_idt>RXDataByteCnt</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16Result</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5Result</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteStMachCurrState</span> <span id=t_kwd>or</span> <span id=t_idt>processRxDataInWEn</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16UpdateRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5UpdateRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>RxOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RxTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>NAKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>stallRxed</span> <span id=t_kwd>or</span> <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>dataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>RxDataOut</span> <span id=t_kwd>or</span> <span id=t_idt>RxCtrlOut</span> <span id=t_kwd>or</span> <span id=t_idt>RxDataOutWEn</span> <span id=t_kwd>or</span> <span id=t_idt>rstCRC</span> <span id=t_kwd>or</span> <span id=t_idt>CRCData</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5En</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5_8Bit</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16En</span> <span id=t_kwd>or</span> <span id=t_idt>processRxByteRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_prRxByte</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxByte_NextState</span>
+  <span id=t_idt>NextState_prRxByte</span> &lt;= <span id=t_idt>CurrState_prRxByte</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_RxByte</span> &lt;= <span id=t_idt>RxByte</span>;
+  <span id=t_idt>next_RxCtrl</span> &lt;= <span id=t_idt>RxCtrl</span>;
+  <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= <span id=t_idt>RXByteStMachCurrState</span>;
+  <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>CRCError</span>;
+  <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>bitStuffError</span>;
+  <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_idt>RxOverflow</span>;
+  <span id=t_idt>next_RxTimeOut</span> &lt;= <span id=t_idt>RxTimeOut</span>;
+  <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_idt>NAKRxed</span>;
+  <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_idt>stallRxed</span>;
+  <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>ACKRxed</span>;
+  <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>dataSequence</span>;
+  <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxDataOut</span>;
+  <span id=t_idt>next_RxCtrlOut</span> &lt;= <span id=t_idt>RxCtrlOut</span>;
+  <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_idt>RxDataOutWEn</span>;
+  <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_idt>rstCRC</span>;
+  <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>CRCData</span>;
+  <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_idt>CRC5En</span>;
+  <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_idt>CRC5_8Bit</span>;
+  <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_idt>CRC16En</span>;
+  <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_idt>RXDataByteCnt</span>;
+  <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_idt>processRxByteRdy</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_prRxByte</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>CHK_ST</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>TOKEN_BYTE_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>TOKEN_WAIT_CRC</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>HS_BYTE_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>HSHAKE_CHK</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>CHECK_PID_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>CHK_PID_DO_CHK</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>CHECK_SYNC_ST</span>)  
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>CHK_SYNC_DO</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>IDLE_BYTE_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>IDLE_CHK_START</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>DATA_BYTE_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>DATA_WAIT_CRC</span>;
+   `<span id=t_idt>START_PRBY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RxByte</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RxCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RxCtrlOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_cns>10'h00</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_BYTE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxDataInWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>CHK_ST</span>;
+      <span id=t_idt>next_RxByte</span> &lt;= <span id=t_idt>RxByteIn</span>;
+      <span id=t_idt>next_RxCtrl</span> &lt;= <span id=t_idt>RxCtrlIn</span>;
+      <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>HSHAKE_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>HSHAKE_CHK</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>HSHAKE_FIN</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RxCtrl</span> != `<span id=t_idt>DATA_STOP</span>) <span id=t_com>//If more than PID rxed, then report error</span>
+       <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+     <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PID_DO_CHK</span>:
+     <span id=t_kwd>if</span> ((<span id=t_idt>RxByte</span>[<span id=t_cns>7</span>:<span id=t_cns>4</span>] ^ <span id=t_idt>RxByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] ) != <span id=t_cns>4'hf</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+      <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+      <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>CHK_PID_FIRST_BYTE_PROC</span>;
+      <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_RxTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_cns>0</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxByte</span>;
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_START</span>;
+      <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PID_FIRST_BYTE_PROC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>case</span> (<span id=t_idt>RxByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] )
+         `<span id=t_idt>SPECIAL</span>:                              <span id=t_com>//Special PID.</span>
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         `<span id=t_idt>TOKEN</span>:                                <span id=t_com>//Token PID</span>
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>TOKEN_BYTE_ST</span>;
+         <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_cns>0</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>HANDSHAKE</span>:                            <span id=t_com>//Handshake PID</span>
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>case</span> (<span id=t_idt>RxByte</span>[<span id=t_cns>3</span>:<span id=t_cns>2</span>] )
+                 <span id=t_cns>2'b00</span>:
+             <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b1</span>;
+                 <span id=t_cns>2'b10</span>:
+             <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_cns>1'b1</span>;
+                 <span id=t_cns>2'b11</span>:
+             <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_cns>1'b1</span>;
+                 <span id=t_kwd>default</span>:
+                 <span id=t_kwd>begin</span>
+                     <span id=t_sys>$display</span> (<span id=t_cns>"Invalid Handshake PID detected in ProcessRXByte\n"</span>);
+                 <span id=t_kwd>end</span>
+             <span id=t_kwd>endcase</span>
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>HS_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA</span>:                                  <span id=t_com>//Data PID</span>
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>case</span> (<span id=t_idt>RxByte</span>[<span id=t_cns>3</span>:<span id=t_cns>2</span>] )
+                 <span id=t_cns>2'b00</span>:
+             <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+                 <span id=t_cns>2'b10</span>:
+             <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b1</span>;
+                 <span id=t_kwd>default</span>:
+                     <span id=t_sys>$display</span> (<span id=t_cns>"Invalid DATA PID detected in ProcessRXByte\n"</span>);
+             <span id=t_kwd>endcase</span>
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>DATA_BYTE_ST</span>;
+         <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_cns>0</span>;
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>endcase</span>
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_CHK_STRM</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_idt>RXDataByteCnt</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>case</span> (<span id=t_idt>RxCtrl</span>)
+         `<span id=t_idt>DATA_STOP</span>:
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>if</span> (<span id=t_idt>CRC16Result</span> != <span id=t_cns>16'hb001</span>)
+           <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA_BIT_STUFF_ERROR</span>:
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA_STREAM</span>:
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxByte</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STREAM</span>;
+         <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>RxByte</span>;
+         <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>endcase</span>
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>DATA_FIN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_WAIT_CRC</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC16UpdateRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>DATA_CHK_STRM</span>;
+   `<span id=t_idt>TOKEN_CHK_STRM</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_idt>RXDataByteCnt</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>case</span> (<span id=t_idt>RxCtrl</span>)
+         `<span id=t_idt>DATA_STOP</span>:
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>if</span> (<span id=t_idt>CRC5Result</span> != <span id=t_cns>5'h6</span>)
+           <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA_BIT_STUFF_ERROR</span>:
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA_STREAM</span>:
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>if</span> (<span id=t_idt>RXDataByteCnt</span> &gt; <span id=t_cns>10'h2</span>)
+             <span id=t_kwd>begin</span>
+           <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_cns>1'b1</span>;
+           <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+           <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+           <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+             <span id=t_kwd>end</span>
+             <span id=t_kwd>else</span>
+             <span id=t_kwd>begin</span>
+           <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxByte</span>;
+           <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STREAM</span>;
+           <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>RxByte</span>;
+           <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b1</span>;
+           <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b1</span>;
+             <span id=t_kwd>end</span>
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>endcase</span>
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>TOKEN_FIN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>TOKEN_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>TOKEN_WAIT_CRC</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC5UpdateRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>TOKEN_CHK_STRM</span>;
+   `<span id=t_idt>CHK_SYNC_DO</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxByte</span> == `<span id=t_idt>SYNC_BYTE</span>)
+       <span id=t_idt>next_RXByteStMachCurrState</span> = `<span id=t_idt>CHECK_PID_ST</span>;
+     <span id=t_kwd>else</span>
+       <span id=t_idt>next_RXByteStMachCurrState</span> = `<span id=t_idt>IDLE_BYTE_ST</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_CHK_START</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxCtrl</span> == `<span id=t_idt>DATA_START</span>)
+       <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>CHECK_SYNC_ST</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxByte_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_prRxByte</span> &lt;= `<span id=t_idt>START_PRBY</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_prRxByte</span> &lt;= <span id=t_idt>NextState_prRxByte</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxByte_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RxByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RxOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RxTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXDataByteCnt</span> &lt;= <span id=t_cns>10'h00</span>;
+   <span id=t_idt>RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxCtrlOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRCData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RxByte</span> &lt;= <span id=t_idt>next_RxByte</span>;
+   <span id=t_idt>RxCtrl</span> &lt;= <span id=t_idt>next_RxCtrl</span>;
+   <span id=t_idt>RXByteStMachCurrState</span> &lt;= <span id=t_idt>next_RXByteStMachCurrState</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_idt>next_CRCError</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_idt>next_bitStuffError</span>;
+   <span id=t_idt>RxOverflow</span> &lt;= <span id=t_idt>next_RxOverflow</span>;
+   <span id=t_idt>RxTimeOut</span> &lt;= <span id=t_idt>next_RxTimeOut</span>;
+   <span id=t_idt>NAKRxed</span> &lt;= <span id=t_idt>next_NAKRxed</span>;
+   <span id=t_idt>stallRxed</span> &lt;= <span id=t_idt>next_stallRxed</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_idt>next_ACKRxed</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_idt>next_dataSequence</span>;
+   <span id=t_idt>RXDataByteCnt</span> &lt;= <span id=t_idt>next_RXDataByteCnt</span>;
+   <span id=t_idt>RxDataOut</span> &lt;= <span id=t_idt>next_RxDataOut</span>;
+   <span id=t_idt>RxCtrlOut</span> &lt;= <span id=t_idt>next_RxCtrlOut</span>;
+   <span id=t_idt>RxDataOutWEn</span> &lt;= <span id=t_idt>next_RxDataOutWEn</span>;
+   <span id=t_idt>rstCRC</span> &lt;= <span id=t_idt>next_rstCRC</span>;
+   <span id=t_idt>CRCData</span> &lt;= <span id=t_idt>next_CRCData</span>;
+   <span id=t_idt>CRC5En</span> &lt;= <span id=t_idt>next_CRC5En</span>;
+   <span id=t_idt>CRC5_8Bit</span> &lt;= <span id=t_idt>next_CRC5_8Bit</span>;
+   <span id=t_idt>CRC16En</span> &lt;= <span id=t_idt>next_CRC16En</span>;
+   <span id=t_idt>processRxByteRdy</span> &lt;= <span id=t_idt>next_processRxByteRdy</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_FIRST_BYTE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_FIRST_BYTE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,63 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 6;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(861,1403,963,1505,Click24,Over24);
+FUB[1] = new Array(859,1176,962,1279,Click16,Over16);
+FUB[2] = new Array(883,1858,986,1961,Click42,Over42);
+FUB[3] = new Array(874,1639,976,1741,Click33,Over33);
+FUB[4] = new Array(841,912,944,1014,Click216,Over216);
+FUB[5] = new Array(845,1042,948,1144,Click213,Over213);
+
+//----------------------------------------------------------------------------
+function Click24(){fubclick('./index24.htm');}
+function Over24(){window.status='Hierarchical State HSHAKE';};
+function Click16(){fubclick('./index16.htm');}
+function Over16(){window.status='Hierarchical State CHK_PID';};
+function Click42(){fubclick('./index42.htm');}
+function Over42(){window.status='Hierarchical State DATA';};
+function Click33(){fubclick('./index33.htm');}
+function Over33(){window.status='Hierarchical State TOKEN';};
+function Click216(){fubclick('./index216.htm');}
+function Over216(){window.status='Hierarchical State IDLE';};
+function Click213(){fubclick('./index213.htm');}
+function Over213(){window.status='Hierarchical State CHK_SYNC';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar216.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar216.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar216.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 216 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar216.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processTxByte" alt="processTxByte"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar874.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar874.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar874.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 874 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processTxByte_SEND_BYTE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processTxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar874.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram23.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram23.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram23.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver DISCNCT" alt="siereceiver DISCNCT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram23.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram73.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram73.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram73.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver FS_CONN" alt="siereceiver FS_CONN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram73.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index23.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index23.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index23.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar23.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram23.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index23.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index73.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index73.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index73.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar73.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram73.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index73.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 18 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_FIRST_BYTE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 33 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_TOKEN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processTxByte STOP" alt="processTxByte STOP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(330,1478,432,1580,Click874,Over874);
+FUB[1] = new Array(342,1793,444,1895,Click887,Over887);
+
+//----------------------------------------------------------------------------
+function Click874(){fubclick('./index874.htm');}
+function Over874(){window.status='Hierarchical State SEND_BYTE';};
+function Click887(){fubclick('./index887.htm');}
+function Over887(){window.status='Hierarchical State STOP';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processTxByte.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processTxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver" alt="siereceiver"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram64.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram64.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram64.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver LS_CONN" alt="siereceiver LS_CONN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram64.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver WAIT_LS_CONN" alt="siereceiver WAIT_LS_CONN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram91.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram91.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram91.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver WAIT_FS_DIS" alt="siereceiver WAIT_FS_DIS"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram91.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index874.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index874.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index874.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar874.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram874.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/index874.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte_SEND_BYTE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte_SEND_BYTE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar887.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar887.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar887.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 887 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processTxByte_STOP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processTxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar887.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram46.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram46.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram46.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver WAIT_FS_CONN" alt="siereceiver WAIT_FS_CONN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram46.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm	(revision 264)
@@ -0,0 +1,371 @@
+<html>
+<head>
+<title>siereceiver.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SIEReceiver</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:47 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>SIEReceiver</span> (<span id=t_idt>RxBitsOut</span>, <span id=t_idt>RxWireDataIn</span>, <span id=t_idt>RxWireDataWEn</span>, <span id=t_idt>SIERxRdyOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>connectState</span>, <span id=t_idt>processRxBitRdyIn</span>, <span id=t_idt>processRxBitsWEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxWireDataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RxWireDataWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processRxBitRdyIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SIERxRdyOut</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processRxBitsWEn</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsOut</span>, <span id=t_idt>next_RxBitsOut</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxWireDataIn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RxWireDataWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SIERxRdyOut</span>, <span id=t_idt>next_SIERxRdyOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>, <span id=t_idt>next_connectState</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processRxBitRdyIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processRxBitsWEn</span>, <span id=t_idt>next_processRxBitsWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>RXStMachCurrState</span>, <span id=t_idt>next_RXStMachCurrState</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXWaitCount</span>, <span id=t_idt>next_RXWaitCount</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>RxBits</span>, <span id=t_idt>next_RxBits</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: rcvr</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FS_CONN_CHK_RX_BITS</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LS_CONN_CHK_RX_BITS</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>LS_CONN_CHK_RX_BITS</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DISCNCT_CHK_RXBITS</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BIT</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SRX</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>LS_CONN_PROC_RX_BITS</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>FS_CONN_CHK_RX_BITS1</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LS_DIS_CHK_RX_BITS</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LS_DIS_PROC_RX_BITS</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FS_DIS_PROC_RX_BITS2</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FS_DIS_CHK_RX_BITS2</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>FS_CONN_PROC_RX_BITS1</span> <span id=t_cns>4'b1100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_rcvr</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_rcvr</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: rcvr</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RxWireDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxBits</span> <span id=t_kwd>or</span> <span id=t_idt>RXWaitCount</span> <span id=t_kwd>or</span> <span id=t_idt>RxWireDataWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXStMachCurrState</span> <span id=t_kwd>or</span> <span id=t_idt>processRxBitRdyIn</span> <span id=t_kwd>or</span> <span id=t_idt>SIERxRdyOut</span> <span id=t_kwd>or</span> <span id=t_idt>connectState</span> <span id=t_kwd>or</span> <span id=t_idt>RxBitsOut</span> <span id=t_kwd>or</span> <span id=t_idt>processRxBitsWEn</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_rcvr</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>rcvr_NextState</span>
+  <span id=t_idt>NextState_rcvr</span> &lt;= <span id=t_idt>CurrState_rcvr</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBits</span>;
+  <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_idt>SIERxRdyOut</span>;
+  <span id=t_idt>next_RXStMachCurrState</span> &lt;= <span id=t_idt>RXStMachCurrState</span>;
+  <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span>;
+  <span id=t_idt>next_connectState</span> &lt;= <span id=t_idt>connectState</span>;
+  <span id=t_idt>next_RxBitsOut</span> &lt;= <span id=t_idt>RxBitsOut</span>;
+  <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_idt>processRxBitsWEn</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_rcvr</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>WAIT_BIT</span>:
+     <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>WAIT_LOW_SPEED_CONN_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_LS_CONN_CHK_RX_BITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>CONNECT_LOW_SPEED_ST</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>LS_CONN_CHK_RX_BITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>CONNECT_FULL_SPEED_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>FS_CONN_CHK_RX_BITS1</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>WAIT_LOW_SP_DISCONNECT_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_LS_DIS_CHK_RX_BITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>WAIT_FULL_SP_DISCONNECT_ST</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_FS_DIS_CHK_RX_BITS2</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>DISCONNECT_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>DISCNCT_CHK_RXBITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>WAIT_FULL_SPEED_CONN_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_FS_CONN_CHK_RX_BITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>START_SRX</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>DISCONNECT_ST</span>;
+     <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_connectState</span> &lt;= `<span id=t_idt>DISCONNECT</span>;
+     <span id=t_idt>next_RxBits</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_RxBitsOut</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DISCNCT_CHK_RXBITS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>ZERO_ONE</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+      <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_LOW_SPEED_CONN_ST</span>;
+      <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>ONE_ZERO</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+      <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_FULL_SPEED_CONN_ST</span>;
+      <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_FS_CONN_CHK_RX_BITS</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>ONE_ZERO</span>)
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span> + <span id=t_cns>1'b1</span>;
+         <span id=t_kwd>if</span> (<span id=t_idt>RXWaitCount</span> == `<span id=t_idt>CONNECT_WAIT_TIME</span>)
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_connectState</span> &lt;= `<span id=t_idt>FULL_SPEED_CONNECT</span>;
+         <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>CONNECT_FULL_SPEED_ST</span>;
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXStMachCurrState</span> = `<span id=t_idt>DISCONNECT_ST</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_LS_CONN_CHK_RX_BITS</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>ZERO_ONE</span>)
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span> + <span id=t_cns>1'b1</span>;
+         <span id=t_kwd>if</span> (<span id=t_idt>RXWaitCount</span> == `<span id=t_idt>CONNECT_WAIT_TIME</span>)
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_connectState</span> &lt;= `<span id=t_idt>LOW_SPEED_CONNECT</span>;
+         <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>CONNECT_LOW_SPEED_ST</span>;
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXStMachCurrState</span> = `<span id=t_idt>DISCONNECT_ST</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>LS_CONN_CHK_RX_BITS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxBitRdyIn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>LS_CONN_PROC_RX_BITS</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_LOW_SP_DISCONNECT_ST</span>;
+        <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>0</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_RxBitsOut</span> &lt;= <span id=t_idt>RxBits</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>LS_CONN_PROC_RX_BITS</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>FS_CONN_CHK_RX_BITS1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxBitRdyIn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>FS_CONN_PROC_RX_BITS1</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_FULL_SP_DISCONNECT_ST</span>;
+        <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>0</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_RxBitsOut</span> &lt;= <span id=t_idt>RxBits</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_com>//early indication of ready</span>
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>FS_CONN_PROC_RX_BITS1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_LS_DIS_CHK_RX_BITS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxBitRdyIn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_LS_DIS_PROC_RX_BITS</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span> + <span id=t_cns>1'b1</span>;
+          <span id=t_kwd>if</span> (<span id=t_idt>RXWaitCount</span> == `<span id=t_idt>DISCONNECT_WAIT_TIME</span>)
+          <span id=t_kwd>begin</span>
+          <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>DISCONNECT_ST</span>;
+          <span id=t_idt>next_connectState</span> = `<span id=t_idt>DISCONNECT</span>;
+          <span id=t_kwd>end</span>
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span>
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXStMachCurrState</span> = `<span id=t_idt>CONNECT_LOW_SPEED_ST</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_LS_DIS_PROC_RX_BITS</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_FS_DIS_PROC_RX_BITS2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_FS_DIS_CHK_RX_BITS2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxBitRdyIn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_FS_DIS_PROC_RX_BITS2</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span> + <span id=t_cns>1'b1</span>;
+          <span id=t_kwd>if</span> (<span id=t_idt>RXWaitCount</span> == `<span id=t_idt>DISCONNECT_WAIT_TIME</span>)
+          <span id=t_kwd>begin</span>
+          <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>DISCONNECT_ST</span>;
+          <span id=t_idt>next_connectState</span> = `<span id=t_idt>DISCONNECT</span>;
+          <span id=t_kwd>end</span>
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span>
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXStMachCurrState</span> = `<span id=t_idt>CONNECT_FULL_SPEED_ST</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>rcvr_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_rcvr</span> &lt;= `<span id=t_idt>START_SRX</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_rcvr</span> &lt;= <span id=t_idt>NextState_rcvr</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>rcvr_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXStMachCurrState</span> &lt;= `<span id=t_idt>DISCONNECT_ST</span>;
+   <span id=t_idt>RXWaitCount</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxBits</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>connectState</span> &lt;= `<span id=t_idt>DISCONNECT</span>;
+   <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXStMachCurrState</span> &lt;= <span id=t_idt>next_RXStMachCurrState</span>;
+   <span id=t_idt>RXWaitCount</span> &lt;= <span id=t_idt>next_RXWaitCount</span>;
+   <span id=t_idt>RxBits</span> &lt;= <span id=t_idt>next_RxBits</span>;
+   <span id=t_idt>connectState</span> &lt;= <span id=t_idt>next_connectState</span>;
+   <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>next_RxBitsOut</span>;
+   <span id=t_idt>processRxBitsWEn</span> &lt;= <span id=t_idt>next_processRxBitsWEn</span>;
+   <span id=t_idt>SIERxRdyOut</span> &lt;= <span id=t_idt>next_SIERxRdyOut</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_FS_CONN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_FS_CONN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,66 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 7;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1080,1893,1182,1996,Click23,Over23);
+FUB[1] = new Array(1073,1755,1175,1857,Click46,Over46);
+FUB[2] = new Array(1062,1607,1164,1709,Click55,Over55);
+FUB[3] = new Array(1045,1312,1147,1414,Click73,Over73);
+FUB[4] = new Array(1051,1466,1154,1569,Click64,Over64);
+FUB[5] = new Array(1025,981,1127,1083,Click91,Over91);
+FUB[6] = new Array(1034,1153,1136,1255,Click82,Over82);
+
+//----------------------------------------------------------------------------
+function Click23(){fubclick('./index23.htm');}
+function Over23(){window.status='Hierarchical State DISCNCT';};
+function Click46(){fubclick('./index46.htm');}
+function Over46(){window.status='Hierarchical State WAIT_FS_CONN';};
+function Click55(){fubclick('./index55.htm');}
+function Over55(){window.status='Hierarchical State WAIT_LS_CONN';};
+function Click73(){fubclick('./index73.htm');}
+function Over73(){window.status='Hierarchical State FS_CONN';};
+function Click64(){fubclick('./index64.htm');}
+function Over64(){window.status='Hierarchical State LS_CONN';};
+function Click91(){fubclick('./index91.htm');}
+function Over91(){window.status='Hierarchical State WAIT_FS_DIS';};
+function Click82(){fubclick('./index82.htm');}
+function Over82(){window.status='Hierarchical State WAIT_LS_DIS';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index64.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index64.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index64.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar64.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram64.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index64.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar55.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram55.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar91.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram91.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram82.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram82.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram82.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver WAIT_LS_DIS" alt="siereceiver WAIT_LS_DIS"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram82.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar46.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram46.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_LS_CONN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_LS_CONN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_LS_DIS.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_LS_DIS.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_FS_CONN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_FS_CONN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_LS_CONN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_LS_CONN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar46.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar46.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar46.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 46 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_WAIT_FS_CONN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar46.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 82 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_WAIT_LS_DIS.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm	(revision 264)
@@ -0,0 +1,388 @@
+<html>
+<head>
+<title>usbSerialInterfaceEngine.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbSerialInterfaceEngine.v                                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:05 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>usbSerialInterfaceEngine</span>(
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_com>//readUSBWireData</span>
+  <span id=t_idt>USBWireDataIn</span>,
+  <span id=t_idt>USBWireDataInTick</span>,
+  <span id=t_com>//writeUSBWireData</span>
+  <span id=t_idt>USBWireDataOut</span>,
+  <span id=t_idt>USBWireCtrlOut</span>,
+  <span id=t_idt>USBWireDataOutTick</span>,
+  <span id=t_com>//SIEReceiver</span>
+  <span id=t_idt>connectState</span>,
+  <span id=t_com>//processRxBit</span>
+  <span id=t_idt>resumeDetected</span>,
+  <span id=t_com>//processRxByte</span>
+  <span id=t_idt>RxCtrlOut</span>, 
+  <span id=t_idt>RxDataOutWEn</span>, 
+  <span id=t_idt>RxDataOut</span>, 
+    <span id=t_com>//SIETransmitter</span>
+  <span id=t_idt>SIEPortCtrlIn</span>,
+  <span id=t_idt>SIEPortDataIn</span>, 
+  <span id=t_idt>SIEPortTxRdy</span>, 
+  <span id=t_idt>SIEPortWEn</span>, 
+    <span id=t_com>//lineControlUpdate</span>
+  <span id=t_idt>fullSpeedPolarity</span>,
+  <span id=t_idt>fullSpeedBitRate</span>,
+  <span id=t_idt>noActivityTimeOut</span>
+);
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>, <span id=t_idt>rst</span>;
+<span id=t_com>//readUSBWireData</span>
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireDataInTick</span>;
+
+<span id=t_com>//writeUSBWireData</span>
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireCtrlOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>noActivityTimeOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireDataOutTick</span>;
+
+<span id=t_com>//SIEReceiver</span>
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>;
+<span id=t_com>//processRxBit</span>
+<span id=t_kwd>output</span> <span id=t_idt>resumeDetected</span>;
+<span id=t_com>//processRxByte</span>
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>RxDataOutWEn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>; 
+<span id=t_com>//SIETransmitter</span>
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataIn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SIEPortTxRdy</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>SIEPortWEn</span>;
+<span id=t_com>//lineControlUpdate</span>
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedBitRate</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>, <span id=t_idt>rst</span>;
+<span id=t_com>//readUSBWireData</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataInTick</span>;
+<span id=t_com>//writeUSBWireData</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireCtrlOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>noActivityTimeOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataOutTick</span>;
+<span id=t_com>//SIEReceiver</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>;
+<span id=t_com>//processRxBit</span>
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetected</span>;
+<span id=t_com>//processRxByte</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RxDataOutWEn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>; 
+<span id=t_com>//SIETransmitter</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortTxRdy</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEn</span>;
+<span id=t_com>//lineControlUpdate</span>
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRate</span>;
+
+<span id=t_com>//internal wiring</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsFromSIERxToPrRxBit</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>processRxBitsWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>processRxBitRdy</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxWireDataFromWireRxToSIERx</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxWireDataWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIERxRdyOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>disableWireRead</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsFromArbToWire</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxCtrlFromArbToWire</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireReadyFromTxArb</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>prcTxByteCtrl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>prcTxByteData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>prcTxByteGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>prcTxByteReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>prcTxByteWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIETxCtrl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>SIETxData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIETxGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIETxReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIETxWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteFromSIEToPrcTxByte</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxCtrlFromSIEToPrcTxByte</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>processRxByteWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataFromPrcRxBitToPrcRxByte</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlFromPrcRxBitToPrcRxByte</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>processRxByteRdy</span>;
+<span id=t_com>//Rx CRC</span>
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC16En</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCRC16Result</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC16UpdateRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC5En</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCRC5Result</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC5_8Bit</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCRCData</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RxRstCRC</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC5UpdateRdy</span>;
+<span id=t_com>//Tx CRC</span>
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC16En</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>TxCRC16Result</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC16UpdateRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC5En</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxCRC5Result</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC5_8Bit</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxCRCData</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>TxRstCRC</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC5UpdateRdy</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>processTxByteRdy</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>processTxByteWEn</span>; 
+
+<span id=t_idt>lineControlUpdate</span> <span id=t_idt>u_lineControlUpdate</span>
+  (.<span id=t_idt>fullSpeedPolarity</span>(<span id=t_idt>fullSpeedPolarity</span>),
+  .<span id=t_idt>fullSpeedBitRate</span>(<span id=t_idt>fullSpeedBitRate</span>),
+  .<span id=t_idt>JBit</span>(<span id=t_idt>JBit</span>),
+  .<span id=t_idt>KBit</span>(<span id=t_idt>KBit</span>) );
+
+<span id=t_idt>SIEReceiver</span> <span id=t_idt>u_SIEReceiver</span>
+  (.<span id=t_idt>RxBitsOut</span>(<span id=t_idt>RxBitsFromSIERxToPrRxBit</span>),
+  .<span id=t_idt>RxWireDataIn</span>(<span id=t_idt>RxWireDataFromWireRxToSIERx</span>), 
+  .<span id=t_idt>RxWireDataWEn</span>(<span id=t_idt>RxWireDataWEn</span>), 
+  .<span id=t_idt>SIERxRdyOut</span>(<span id=t_idt>SIERxRdyOut</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>connectState</span>(<span id=t_idt>connectState</span>),
+  .<span id=t_idt>processRxBitRdyIn</span>(<span id=t_idt>processRxBitRdy</span>), 
+  .<span id=t_idt>processRxBitsWEn</span>(<span id=t_idt>processRxBitsWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) );
+  
+<span id=t_idt>processRxBit</span> <span id=t_idt>u_processRxBit</span>
+  (.<span id=t_idt>JBit</span>(<span id=t_idt>JBit</span>), 
+  .<span id=t_idt>KBit</span>(<span id=t_idt>KBit</span>), 
+  .<span id=t_idt>RxBitsIn</span>(<span id=t_idt>RxBitsFromSIERxToPrRxBit</span>), 
+  .<span id=t_idt>RxCtrlOut</span>(<span id=t_idt>RxCtrlFromPrcRxBitToPrcRxByte</span>), 
+  .<span id=t_idt>RxDataOut</span>(<span id=t_idt>RxDataFromPrcRxBitToPrcRxByte</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>processRxBitRdy</span>(<span id=t_idt>processRxBitRdy</span>), 
+  .<span id=t_idt>processRxBitsWEn</span>(<span id=t_idt>processRxBitsWEn</span>), 
+  .<span id=t_idt>processRxByteWEn</span>(<span id=t_idt>processRxByteWEn</span>), 
+  .<span id=t_idt>resumeDetected</span>(<span id=t_idt>resumeDetected</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>processRxByteRdy</span>(<span id=t_idt>processRxByteRdy</span>) );
+  
+<span id=t_idt>processRxByte</span> <span id=t_idt>u_processRxByte</span>
+  (.<span id=t_idt>CRC16En</span>(<span id=t_idt>RxCRC16En</span>), 
+  .<span id=t_idt>CRC16Result</span>(<span id=t_idt>RxCRC16Result</span>), 
+  .<span id=t_idt>CRC16UpdateRdy</span>(<span id=t_idt>RxCRC16UpdateRdy</span>),
+  .<span id=t_idt>CRC5En</span>(<span id=t_idt>RxCRC5En</span>), 
+  .<span id=t_idt>CRC5Result</span>(<span id=t_idt>RxCRC5Result</span>), 
+  .<span id=t_idt>CRC5_8Bit</span>(<span id=t_idt>RxCRC5_8Bit</span>),
+  .<span id=t_idt>CRC5UpdateRdy</span>(<span id=t_idt>RxCRC5UpdateRdy</span>),
+  .<span id=t_idt>CRCData</span>(<span id=t_idt>RxCRCData</span>), 
+  .<span id=t_idt>RxByteIn</span>(<span id=t_idt>RxDataFromPrcRxBitToPrcRxByte</span>), 
+  .<span id=t_idt>RxCtrlIn</span>(<span id=t_idt>RxCtrlFromPrcRxBitToPrcRxByte</span>), 
+  .<span id=t_idt>RxCtrlOut</span>(<span id=t_idt>RxCtrlOut</span>), 
+  .<span id=t_idt>RxDataOutWEn</span>(<span id=t_idt>RxDataOutWEn</span>), 
+  .<span id=t_idt>RxDataOut</span>(<span id=t_idt>RxDataOut</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>processRxDataInWEn</span>(<span id=t_idt>processRxByteWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>rstCRC</span>(<span id=t_idt>RxRstCRC</span>),
+  .<span id=t_idt>processRxByteRdy</span>(<span id=t_idt>processRxByteRdy</span>) ); 
+  
+  
+<span id=t_idt>updateCRC5</span> <span id=t_idt>RxUpdateCRC5</span>
+  (.<span id=t_idt>rstCRC</span>(<span id=t_idt>RxRstCRC</span>), 
+  .<span id=t_idt>CRCResult</span>(<span id=t_idt>RxCRC5Result</span>), 
+  .<span id=t_idt>CRCEn</span>(<span id=t_idt>RxCRC5En</span>), 
+  .<span id=t_idt>CRC5_8BitIn</span>(<span id=t_idt>RxCRC5_8Bit</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>RxCRCData</span>), 
+  .<span id=t_idt>ready</span>(<span id=t_idt>RxCRC5UpdateRdy</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) );  
+  
+<span id=t_idt>updateCRC16</span> <span id=t_idt>RxUpdateCRC16</span>
+  (.<span id=t_idt>rstCRC</span>(<span id=t_idt>RxRstCRC</span>), 
+  .<span id=t_idt>CRCResult</span>(<span id=t_idt>RxCRC16Result</span>), 
+  .<span id=t_idt>CRCEn</span>(<span id=t_idt>RxCRC16En</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>RxCRCData</span>), 
+  .<span id=t_idt>ready</span>(<span id=t_idt>RxCRC16UpdateRdy</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+  
+<span id=t_idt>SIETransmitter</span> <span id=t_idt>u_SIETransmitter</span>
+  (.<span id=t_idt>CRC16En</span>(<span id=t_idt>TxCRC16En</span>), 
+  .<span id=t_idt>CRC16Result</span>(<span id=t_idt>TxCRC16Result</span>), 
+  .<span id=t_idt>CRC5En</span>(<span id=t_idt>TxCRC5En</span>), 
+  .<span id=t_idt>CRC5Result</span>(<span id=t_idt>TxCRC5Result</span>), 
+  .<span id=t_idt>CRC5_8Bit</span>(<span id=t_idt>TxCRC5_8Bit</span>), 
+  .<span id=t_idt>CRCData</span>(<span id=t_idt>TxCRCData</span>),
+  .<span id=t_idt>CRC5UpdateRdy</span>(<span id=t_idt>TxCRC5UpdateRdy</span>),
+  .<span id=t_idt>CRC16UpdateRdy</span>(<span id=t_idt>TxCRC16UpdateRdy</span>),
+  .<span id=t_idt>JBit</span>(<span id=t_idt>JBit</span>), 
+  .<span id=t_idt>KBit</span>(<span id=t_idt>KBit</span>), 
+  .<span id=t_idt>SIEPortCtrlIn</span>(<span id=t_idt>SIEPortCtrlIn</span>),
+  .<span id=t_idt>SIEPortDataIn</span>(<span id=t_idt>SIEPortDataIn</span>), 
+  .<span id=t_idt>SIEPortTxRdy</span>(<span id=t_idt>SIEPortTxRdy</span>), 
+  .<span id=t_idt>SIEPortWEn</span>(<span id=t_idt>SIEPortWEn</span>), 
+  .<span id=t_idt>TxByteOutCtrl</span>(<span id=t_idt>TxCtrlFromSIEToPrcTxByte</span>), 
+  .<span id=t_idt>TxByteOut</span>(<span id=t_idt>TxByteFromSIEToPrcTxByte</span>), 
+  .<span id=t_idt>USBWireCtrl</span>(<span id=t_idt>SIETxCtrl</span>), 
+  .<span id=t_idt>USBWireData</span>(<span id=t_idt>SIETxData</span>), 
+  .<span id=t_idt>USBWireGnt</span>(<span id=t_idt>SIETxGnt</span>), 
+  .<span id=t_idt>USBWireRdy</span>(<span id=t_idt>USBWireReadyFromTxArb</span>), 
+  .<span id=t_idt>USBWireReq</span>(<span id=t_idt>SIETxReq</span>), 
+  .<span id=t_idt>USBWireWEn</span>(<span id=t_idt>SIETxWEn</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>processTxByteRdy</span>(<span id=t_idt>processTxByteRdy</span>), 
+  .<span id=t_idt>processTxByteWEn</span>(<span id=t_idt>processTxByteWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>rstCRC</span>(<span id=t_idt>TxRstCRC</span>) );   
+
+<span id=t_idt>updateCRC5</span> <span id=t_idt>TxUpdateCRC5</span>
+  (.<span id=t_idt>rstCRC</span>(<span id=t_idt>TxRstCRC</span>), 
+  .<span id=t_idt>CRCResult</span>(<span id=t_idt>TxCRC5Result</span>), 
+  .<span id=t_idt>CRCEn</span>(<span id=t_idt>TxCRC5En</span>), 
+  .<span id=t_idt>CRC5_8BitIn</span>(<span id=t_idt>TxCRC5_8Bit</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>TxCRCData</span>),
+  .<span id=t_idt>ready</span>(<span id=t_idt>TxCRC5UpdateRdy</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) );  
+  
+<span id=t_idt>updateCRC16</span> <span id=t_idt>TxUpdateCRC16</span>
+  (.<span id=t_idt>rstCRC</span>(<span id=t_idt>TxRstCRC</span>), 
+  .<span id=t_idt>CRCResult</span>(<span id=t_idt>TxCRC16Result</span>), 
+  .<span id=t_idt>CRCEn</span>(<span id=t_idt>TxCRC16En</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>TxCRCData</span>), 
+  .<span id=t_idt>ready</span>(<span id=t_idt>TxCRC16UpdateRdy</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>processTxByte</span> <span id=t_idt>u_processTxByte</span>
+  (.<span id=t_idt>JBit</span>(<span id=t_idt>JBit</span>), 
+  .<span id=t_idt>KBit</span>(<span id=t_idt>KBit</span>), 
+  .<span id=t_idt>TxByteCtrlIn</span>(<span id=t_idt>TxCtrlFromSIEToPrcTxByte</span>), 
+  .<span id=t_idt>TxByteIn</span>(<span id=t_idt>TxByteFromSIEToPrcTxByte</span>), 
+  .<span id=t_idt>USBWireCtrl</span>(<span id=t_idt>prcTxByteCtrl</span>), 
+  .<span id=t_idt>USBWireData</span>(<span id=t_idt>prcTxByteData</span>), 
+  .<span id=t_idt>USBWireGnt</span>(<span id=t_idt>prcTxByteGnt</span>), 
+  .<span id=t_idt>USBWireRdy</span>(<span id=t_idt>USBWireReadyFromTxArb</span>), 
+  .<span id=t_idt>USBWireReq</span>(<span id=t_idt>prcTxByteReq</span>), 
+  .<span id=t_idt>USBWireWEn</span>(<span id=t_idt>prcTxByteWEn</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>processTxByteRdy</span>(<span id=t_idt>processTxByteRdy</span>), 
+  .<span id=t_idt>processTxByteWEn</span>(<span id=t_idt>processTxByteWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+  
+<span id=t_idt>USBWireTxArbiter</span> <span id=t_idt>u_USBWireTxArbiter</span>
+  (.<span id=t_idt>SIETxCtrl</span>(<span id=t_idt>SIETxCtrl</span>), 
+  .<span id=t_idt>SIETxData</span>(<span id=t_idt>SIETxData</span>), 
+  .<span id=t_idt>SIETxGnt</span>(<span id=t_idt>SIETxGnt</span>), 
+  .<span id=t_idt>SIETxReq</span>(<span id=t_idt>SIETxReq</span>), 
+  .<span id=t_idt>SIETxWEn</span>(<span id=t_idt>SIETxWEn</span>), 
+  .<span id=t_idt>TxBits</span>(<span id=t_idt>TxBitsFromArbToWire</span>), 
+  .<span id=t_idt>TxCtl</span>(<span id=t_idt>TxCtrlFromArbToWire</span>), 
+  .<span id=t_idt>USBWireRdyIn</span>(<span id=t_idt>USBWireRdy</span>), 
+  .<span id=t_idt>USBWireRdyOut</span>(<span id=t_idt>USBWireReadyFromTxArb</span>), 
+  .<span id=t_idt>USBWireWEn</span>(<span id=t_idt>USBWireWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>prcTxByteCtrl</span>(<span id=t_idt>prcTxByteCtrl</span>), 
+  .<span id=t_idt>prcTxByteData</span>(<span id=t_idt>prcTxByteData</span>), 
+  .<span id=t_idt>prcTxByteGnt</span>(<span id=t_idt>prcTxByteGnt</span>), 
+  .<span id=t_idt>prcTxByteReq</span>(<span id=t_idt>prcTxByteReq</span>), 
+  .<span id=t_idt>prcTxByteWEn</span>(<span id=t_idt>prcTxByteWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+  
+<span id=t_idt>writeUSBWireData</span> <span id=t_idt>u_writeUSBWireData</span>
+  (.<span id=t_idt>TxBitsIn</span>(<span id=t_idt>TxBitsFromArbToWire</span>), 
+  .<span id=t_idt>TxBitsOut</span>(<span id=t_idt>USBWireDataOut</span>), 
+  .<span id=t_idt>TxDataOutTick</span>(<span id=t_idt>USBWireDataOutTick</span>),
+  .<span id=t_idt>TxCtrlIn</span>(<span id=t_idt>TxCtrlFromArbToWire</span>), 
+  .<span id=t_idt>TxCtrlOut</span>(<span id=t_idt>USBWireCtrlOut</span>), 
+  .<span id=t_idt>USBWireRdy</span>(<span id=t_idt>USBWireRdy</span>), 
+  .<span id=t_idt>USBWireWEn</span>(<span id=t_idt>USBWireWEn</span>),
+  .<span id=t_idt>disableWireReadOut</span>(<span id=t_idt>disableWireRead</span>),
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedBitRate</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>noActivityTimeOut</span>(<span id=t_idt>noActivityTimeOut</span>) );  
+  
+<span id=t_idt>readUSBWireData</span> <span id=t_idt>u_readUSBWireData</span>
+  (.<span id=t_idt>RxBitsIn</span>(<span id=t_idt>USBWireDataIn</span>), 
+  .<span id=t_idt>RxDataInTick</span>(<span id=t_idt>USBWireDataInTick</span>),
+  .<span id=t_idt>RxBitsOut</span>(<span id=t_idt>RxWireDataFromWireRxToSIERx</span>), 
+  .<span id=t_idt>SIERxRdyIn</span>(<span id=t_idt>SIERxRdyOut</span>), 
+  .<span id=t_idt>SIERxWEn</span>(<span id=t_idt>RxWireDataWEn</span>), 
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedBitRate</span>), 
+  .<span id=t_idt>disableWireRead</span>(<span id=t_idt>disableWireRead</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) );
+
+
+<span id=t_kwd>endmodule</span>
+
+  
+  
+
+
+
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index82.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index82.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index82.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar82.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram82.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/index82.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_DISCNCT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_DISCNCT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_FS_DIS.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_FS_DIS.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar23.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar23.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar23.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 23 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_DISCNCT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar23.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar73.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar73.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar73.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 73 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_FS_CONN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar73.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm	(revision 264)
@@ -0,0 +1,129 @@
+<html>
+<head>
+<title>updateCRC5.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// updateCRC5.v                                                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:03 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>updateCRC5</span> (<span id=t_idt>rstCRC</span>, <span id=t_idt>CRCResult</span>, <span id=t_idt>CRCEn</span>, <span id=t_idt>CRC5_8BitIn</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>ready</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>rstCRC</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRCEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC5_8BitIn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCResult</span>;
+<span id=t_kwd>output</span> <span id=t_idt>ready</span>;
+
+<span id=t_kwd>wire</span>   <span id=t_idt>rstCRC</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>CRCEn</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>CRC5_8BitIn</span>;
+<span id=t_kwd>wire</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>    [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCResult</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>ready</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>doUpdateCRC</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>loopEnd</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>i</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span> || <span id=t_idt>rstCRC</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>CRCResult</span> &lt;= <span id=t_cns>5'h1f</span>;
+    <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>doUpdateCRC</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>CRCEn</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b0</span>;
+        <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>data</span> &lt;= <span id=t_idt>dataIn</span>;
+        <span id=t_kwd>if</span> (<span id=t_idt>CRC5_8BitIn</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+          <span id=t_idt>loopEnd</span> &lt;= <span id=t_cns>4'h7</span>; 
+        <span id=t_kwd>end</span>
+        <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+         <span id=t_idt>loopEnd</span> &lt;= <span id=t_cns>4'h2</span>;
+        <span id=t_kwd>end</span>
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+      <span id=t_idt>i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>if</span> ( (<span id=t_idt>CRCResult</span>[<span id=t_cns>0</span>] ^ <span id=t_idt>data</span>[<span id=t_cns>0</span>]) == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+       <span id=t_idt>CRCResult</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>CRCResult</span>[<span id=t_cns>4</span>:<span id=t_cns>1</span>]} ^ <span id=t_cns>5'h14</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+        <span id=t_idt>CRCResult</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>CRCResult</span>[<span id=t_cns>4</span>:<span id=t_cns>1</span>]};
+      <span id=t_kwd>end</span>
+      <span id=t_idt>data</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>data</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>]};
+      <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_idt>loopEnd</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b0</span>; 
+       <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+        <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+   
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./usbTxWireArbiter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./usbTxWireArbiter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar55.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar55.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar55.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 55 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_WAIT_LS_CONN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar55.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 91 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_WAIT_FS_DIS.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="usbTxWireArbiter" alt="usbTxWireArbiter"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm	(revision 264)
@@ -0,0 +1,215 @@
+<html>
+<head>
+<title>usbTxWireArbiter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBWireTxArbiter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:07 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>USBWireTxArbiter</span> (<span id=t_idt>SIETxCtrl</span>, <span id=t_idt>SIETxData</span>, <span id=t_idt>SIETxGnt</span>, <span id=t_idt>SIETxReq</span>, <span id=t_idt>SIETxWEn</span>, <span id=t_idt>TxBits</span>, <span id=t_idt>TxCtl</span>, <span id=t_idt>USBWireRdyIn</span>, <span id=t_idt>USBWireRdyOut</span>, <span id=t_idt>USBWireWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>prcTxByteCtrl</span>, <span id=t_idt>prcTxByteData</span>, <span id=t_idt>prcTxByteGnt</span>, <span id=t_idt>prcTxByteReq</span>, <span id=t_idt>prcTxByteWEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>SIETxCtrl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>SIETxData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIETxReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIETxWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireRdyIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>prcTxByteCtrl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>prcTxByteData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>prcTxByteReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>prcTxByteWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SIETxGnt</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBits</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>TxCtl</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireRdyOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>prcTxByteGnt</span>;
+
+<span id=t_kwd>wire</span>    <span id=t_idt>SIETxCtrl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>SIETxData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SIETxGnt</span>, <span id=t_idt>next_SIETxGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIETxReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIETxWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBits</span>, <span id=t_idt>next_TxBits</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>TxCtl</span>, <span id=t_idt>next_TxCtl</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireRdyIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireRdyOut</span>, <span id=t_idt>next_USBWireRdyOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireWEn</span>, <span id=t_idt>next_USBWireWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>prcTxByteCtrl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>prcTxByteData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>prcTxByteGnt</span>, <span id=t_idt>next_prcTxByteGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>prcTxByteReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>prcTxByteWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>muxSIENotPTXB</span>, <span id=t_idt>next_muxSIENotPTXB</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: txWireArb</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_TARB</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>TARB_WAIT_REQ</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>PTXB_ACT</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>SIE_TX_ACT</span> <span id=t_cns>2'b11</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_txWireArb</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_txWireArb</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// processTxByte/SIETransmitter mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>USBWireRdyIn</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>USBWireRdyOut</span> &lt;= <span id=t_idt>USBWireRdyIn</span>;
+<span id=t_kwd>end</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>muxSIENotPTXB</span> <span id=t_kwd>or</span> <span id=t_idt>SIETxWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SIETxData</span> <span id=t_kwd>or</span>
+<span id=t_idt>SIETxCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>prcTxByteWEn</span> <span id=t_kwd>or</span> <span id=t_idt>prcTxByteData</span> <span id=t_kwd>or</span> <span id=t_idt>prcTxByteCtrl</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>muxSIENotPTXB</span>  == <span id=t_cns>1'b1</span>)
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_idt>SIETxWEn</span>;
+        <span id=t_idt>TxBits</span> &lt;= <span id=t_idt>SIETxData</span>;
+        <span id=t_idt>TxCtl</span> &lt;= <span id=t_idt>SIETxCtrl</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span>
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_idt>prcTxByteWEn</span>;
+        <span id=t_idt>TxBits</span> &lt;= <span id=t_idt>prcTxByteData</span>;
+        <span id=t_idt>TxCtl</span> &lt;= <span id=t_idt>prcTxByteCtrl</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: txWireArb</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>prcTxByteReq</span> <span id=t_kwd>or</span> <span id=t_idt>SIETxReq</span> <span id=t_kwd>or</span> <span id=t_idt>prcTxByteGnt</span> <span id=t_kwd>or</span> <span id=t_idt>muxSIENotPTXB</span> <span id=t_kwd>or</span> <span id=t_idt>SIETxGnt</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_txWireArb</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>txWireArb_NextState</span>
+  <span id=t_idt>NextState_txWireArb</span> &lt;= <span id=t_idt>CurrState_txWireArb</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_prcTxByteGnt</span> &lt;= <span id=t_idt>prcTxByteGnt</span>;
+  <span id=t_idt>next_muxSIENotPTXB</span> &lt;= <span id=t_idt>muxSIENotPTXB</span>;
+  <span id=t_idt>next_SIETxGnt</span> &lt;= <span id=t_idt>SIETxGnt</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_txWireArb</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_TARB</span>:
+     <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>TARB_WAIT_REQ</span>;
+   `<span id=t_idt>TARB_WAIT_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>prcTxByteReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>PTXB_ACT</span>;
+      <span id=t_idt>next_prcTxByteGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxSIENotPTXB</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIETxReq</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>SIE_TX_ACT</span>;
+      <span id=t_idt>next_SIETxGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxSIENotPTXB</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PTXB_ACT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>prcTxByteReq</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>TARB_WAIT_REQ</span>;
+      <span id=t_idt>next_prcTxByteGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SIE_TX_ACT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SIETxReq</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>TARB_WAIT_REQ</span>;
+      <span id=t_idt>next_SIETxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>txWireArb_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_txWireArb</span> &lt;= `<span id=t_idt>START_TARB</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_txWireArb</span> &lt;= <span id=t_idt>NextState_txWireArb</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>txWireArb_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxSIENotPTXB</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>prcTxByteGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SIETxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxSIENotPTXB</span> &lt;= <span id=t_idt>next_muxSIENotPTXB</span>;
+   <span id=t_idt>prcTxByteGnt</span> &lt;= <span id=t_idt>next_prcTxByteGnt</span>;
+   <span id=t_idt>SIETxGnt</span> &lt;= <span id=t_idt>next_SIETxGnt</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm
___________________________________________________________________
Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/fifoMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/fifoMux.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/fifoMux.v/index.htm	(revision 264)
@@ -0,0 +1,229 @@
+<html>
+<head>
+<title>fifoMux.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// fifoMux.v                                                    ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:09 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>fifoMux</span> (
+  <span id=t_idt>currEndP</span>,
+  <span id=t_com>//TxFifo</span>
+  <span id=t_idt>TxFifoREn</span>,
+  <span id=t_idt>TxFifoEP0REn</span>,
+  <span id=t_idt>TxFifoEP1REn</span>,
+  <span id=t_idt>TxFifoEP2REn</span>,
+  <span id=t_idt>TxFifoEP3REn</span>,
+  <span id=t_idt>TxFifoData</span>,
+  <span id=t_idt>TxFifoEP0Data</span>,
+  <span id=t_idt>TxFifoEP1Data</span>,
+  <span id=t_idt>TxFifoEP2Data</span>,
+  <span id=t_idt>TxFifoEP3Data</span>,
+  <span id=t_idt>TxFifoEmpty</span>,
+  <span id=t_idt>TxFifoEP0Empty</span>,
+  <span id=t_idt>TxFifoEP1Empty</span>,
+  <span id=t_idt>TxFifoEP2Empty</span>,
+  <span id=t_idt>TxFifoEP3Empty</span>,
+  <span id=t_com>//RxFifo</span>
+  <span id=t_idt>RxFifoWEn</span>,
+  <span id=t_idt>RxFifoEP0WEn</span>,
+  <span id=t_idt>RxFifoEP1WEn</span>,
+  <span id=t_idt>RxFifoEP2WEn</span>,
+  <span id=t_idt>RxFifoEP3WEn</span>,
+  <span id=t_idt>RxFifoFull</span>,
+  <span id=t_idt>RxFifoEP0Full</span>,
+  <span id=t_idt>RxFifoEP1Full</span>,
+  <span id=t_idt>RxFifoEP2Full</span>,
+  <span id=t_idt>RxFifoEP3Full</span>
+    );
+
+
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_com>//TxFifo</span>
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoREn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP3Empty</span>;
+  <span id=t_com>//RxFifo</span>
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoWEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP3Full</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_com>//TxFifo</span>
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoREn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3Empty</span>;
+  <span id=t_com>//RxFifo</span>
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoWEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3Full</span>;
+
+<span id=t_com>//internal wires and regs</span>
+
+<span id=t_com>//combinatorially mux TX and RX fifos for end points 0 through 3</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>currEndP</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoREn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoWEn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP0Data</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP1Data</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP2Data</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP3Data</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP0Empty</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP1Empty</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP2Empty</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP3Empty</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoEP0Full</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoEP1Full</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoEP2Full</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoEP3Full</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>currEndP</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>])
+    <span id=t_cns>2'b00</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>TxFifoEP0REn</span> &lt;= <span id=t_idt>TxFifoREn</span>;
+      <span id=t_idt>TxFifoEP1REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP2REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP3REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoData</span> &lt;= <span id=t_idt>TxFifoEP0Data</span>;
+      <span id=t_idt>TxFifoEmpty</span> &lt;= <span id=t_idt>TxFifoEP0Empty</span>;
+      <span id=t_idt>RxFifoEP0WEn</span> &lt;= <span id=t_idt>RxFifoWEn</span>;
+      <span id=t_idt>RxFifoEP1WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP2WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP3WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoFull</span> &lt;= <span id=t_idt>RxFifoEP0Full</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b01</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>TxFifoEP0REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP1REn</span> &lt;= <span id=t_idt>TxFifoREn</span>;
+      <span id=t_idt>TxFifoEP2REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP3REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoData</span> &lt;= <span id=t_idt>TxFifoEP1Data</span>;
+      <span id=t_idt>TxFifoEmpty</span> &lt;= <span id=t_idt>TxFifoEP1Empty</span>;
+      <span id=t_idt>RxFifoEP0WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP1WEn</span> &lt;= <span id=t_idt>RxFifoWEn</span>;
+      <span id=t_idt>RxFifoEP2WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP3WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoFull</span> &lt;= <span id=t_idt>RxFifoEP1Full</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b10</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>TxFifoEP0REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP1REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP2REn</span> &lt;= <span id=t_idt>TxFifoREn</span>;
+      <span id=t_idt>TxFifoEP3REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoData</span> &lt;= <span id=t_idt>TxFifoEP2Data</span>;
+      <span id=t_idt>TxFifoEmpty</span> &lt;= <span id=t_idt>TxFifoEP2Empty</span>;
+      <span id=t_idt>RxFifoEP0WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP1WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP2WEn</span> &lt;= <span id=t_idt>RxFifoWEn</span>;
+      <span id=t_idt>RxFifoEP3WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoFull</span> &lt;= <span id=t_idt>RxFifoEP2Full</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b11</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>TxFifoEP0REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP1REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP2REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP3REn</span> &lt;= <span id=t_idt>TxFifoREn</span>;
+      <span id=t_idt>TxFifoData</span> &lt;= <span id=t_idt>TxFifoEP3Data</span>;
+      <span id=t_idt>TxFifoEmpty</span> &lt;= <span id=t_idt>TxFifoEP3Empty</span>;
+      <span id=t_idt>RxFifoEP0WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP1WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP2WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP3WEn</span> &lt;= <span id=t_idt>RxFifoWEn</span>;
+      <span id=t_idt>RxFifoFull</span> &lt;= <span id=t_idt>RxFifoEP3Full</span>;
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>  
+<span id=t_kwd>end</span>      
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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===================================================================
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@@ -0,0 +1,216 @@
+<html>
+<head>
+<title>sctxportarbiter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SCTxPortArbiter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:12 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>SCTxPortArbiter</span> (<span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>SCTxPortData</span>, <span id=t_idt>SCTxPortRdyIn</span>, <span id=t_idt>SCTxPortRdyOut</span>, <span id=t_idt>SCTxPortWEnable</span>, <span id=t_idt>clk</span>, <span id=t_idt>directCntlCntl</span>, <span id=t_idt>directCntlData</span>, <span id=t_idt>directCntlGnt</span>, <span id=t_idt>directCntlReq</span>, <span id=t_idt>directCntlWEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketCntl</span>, <span id=t_idt>sendPacketData</span>, <span id=t_idt>sendPacketGnt</span>, <span id=t_idt>sendPacketReq</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortRdyIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortRdyOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortWEnable</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>directCntlGnt</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketGnt</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>next_SCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>, <span id=t_idt>next_SCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortRdyIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortRdyOut</span>, <span id=t_idt>next_SCTxPortRdyOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortWEnable</span>, <span id=t_idt>next_SCTxPortWEnable</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>directCntlGnt</span>, <span id=t_idt>next_directCntlGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketGnt</span>, <span id=t_idt>next_sendPacketGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>muxDCEn</span>, <span id=t_idt>next_muxDCEn</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: SCTxArb</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>SARB1_WAIT_REQ</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>SARB_SEND_PACKET</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>SARB_DC</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SARB</span> <span id=t_cns>2'b11</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_SCTxArb</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_SCTxArb</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// SOFController/directContol/sendPacket mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>SCTxPortRdyIn</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>SCTxPortRdyOut</span> = <span id=t_idt>SCTxPortRdyIn</span>;
+<span id=t_kwd>end</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>muxDCEn</span> <span id=t_kwd>or</span>
+        <span id=t_idt>directCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlCntl</span> <span id=t_kwd>or</span>
+                  <span id=t_idt>directCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlCntl</span> <span id=t_kwd>or</span>
+          <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketData</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketCntl</span>)
+<span id=t_kwd>begin</span>
+<span id=t_kwd>if</span> (<span id=t_idt>muxDCEn</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>SCTxPortWEnable</span> &lt;= <span id=t_idt>directCntlWEn</span>;
+        <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_idt>directCntlData</span>;
+        <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_idt>directCntlCntl</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>else</span>
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>SCTxPortWEnable</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+        <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_idt>sendPacketData</span>;
+        <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_idt>sendPacketCntl</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: SCTxArb</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>sendPacketReq</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlReq</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketGnt</span> <span id=t_kwd>or</span> <span id=t_idt>muxDCEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlGnt</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_SCTxArb</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SCTxArb_NextState</span>
+  <span id=t_idt>NextState_SCTxArb</span> &lt;= <span id=t_idt>CurrState_SCTxArb</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_idt>sendPacketGnt</span>;
+  <span id=t_idt>next_muxDCEn</span> &lt;= <span id=t_idt>muxDCEn</span>;
+  <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_idt>directCntlGnt</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_SCTxArb</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>SARB1_WAIT_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketReq</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB_SEND_PACKET</span>;
+      <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxDCEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>directCntlReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB_DC</span>;
+      <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxDCEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SARB_SEND_PACKET</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB1_WAIT_REQ</span>;
+      <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SARB_DC</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>directCntlReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB1_WAIT_REQ</span>;
+      <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>START_SARB</span>:
+     <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB1_WAIT_REQ</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SCTxArb_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_SCTxArb</span> &lt;= `<span id=t_idt>START_SARB</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_SCTxArb</span> &lt;= <span id=t_idt>NextState_SCTxArb</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SCTxArb_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxDCEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>directCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxDCEn</span> &lt;= <span id=t_idt>next_muxDCEn</span>;
+   <span id=t_idt>sendPacketGnt</span> &lt;= <span id=t_idt>next_sendPacketGnt</span>;
+   <span id=t_idt>directCntlGnt</span> &lt;= <span id=t_idt>next_directCntlGnt</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveDirectcontrol DRCT_CNTL" alt="slaveDirectcontrol DRCT_CNTL"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(488,1130,591,1232,Click78,Over78);
+FUB[1] = new Array(1112,1183,1215,1285,Click127,Over127);
+
+//----------------------------------------------------------------------------
+function Click78(){fubclick('./index78.htm');}
+function Over78(){window.status='Hierarchical State DRCT_CNTL';};
+function Click127(){fubclick('./index127.htm');}
+function Over127(){window.status='Hierarchical State IDLE';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveDirectcontrol.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveDirectcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/endpMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/endpMux.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/endpMux.v/index.htm	(revision 264)
@@ -0,0 +1,277 @@
+<html>
+<head>
+<title>endpMux.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// endpMux.v                                                    ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:08 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbSlaveControl_h.v"</span> 
+
+<span id=t_kwd>module</span> <span id=t_idt>endpMux</span> (
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>,
+  <span id=t_idt>currEndP</span>,
+  <span id=t_idt>NAKSent</span>,
+  <span id=t_idt>stallSent</span>,
+  <span id=t_idt>CRCError</span>,
+  <span id=t_idt>bitStuffError</span>,
+  <span id=t_idt>RxOverflow</span>,
+  <span id=t_idt>RxTimeOut</span>,
+  <span id=t_idt>dataSequence</span>,
+  <span id=t_idt>ACKRxed</span>,
+  <span id=t_idt>transType</span>,
+  <span id=t_idt>transTypeNAK</span>,
+  <span id=t_idt>endPControlReg</span>,
+  <span id=t_idt>clrEPRdy</span>,
+  <span id=t_idt>endPMuxErrorsWEn</span>,
+  <span id=t_idt>endP0ControlReg</span>,
+  <span id=t_idt>endP1ControlReg</span>,
+  <span id=t_idt>endP2ControlReg</span>,
+  <span id=t_idt>endP3ControlReg</span>,
+  <span id=t_idt>endP0StatusReg</span>,
+  <span id=t_idt>endP1StatusReg</span>,
+  <span id=t_idt>endP2StatusReg</span>,
+  <span id=t_idt>endP3StatusReg</span>,
+  <span id=t_idt>endP0TransTypeReg</span>,
+  <span id=t_idt>endP1TransTypeReg</span>,
+  <span id=t_idt>endP2TransTypeReg</span>,
+  <span id=t_idt>endP3TransTypeReg</span>,
+  <span id=t_idt>endP0NAKTransTypeReg</span>,
+  <span id=t_idt>endP1NAKTransTypeReg</span>,
+  <span id=t_idt>endP2NAKTransTypeReg</span>,
+  <span id=t_idt>endP3NAKTransTypeReg</span>,
+  <span id=t_idt>clrEP0Rdy</span>,
+  <span id=t_idt>clrEP1Rdy</span>,
+  <span id=t_idt>clrEP2Rdy</span>,
+  <span id=t_idt>clrEP3Rdy</span>);
+
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_kwd>input</span> <span id=t_idt>NAKSent</span>;
+<span id=t_kwd>input</span> <span id=t_idt>stallSent</span>;
+<span id=t_kwd>input</span> <span id=t_idt>CRCError</span>;
+<span id=t_kwd>input</span> <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxOverflow</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxTimeOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>dataSequence</span>;
+<span id=t_kwd>input</span> <span id=t_idt>ACKRxed</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transTypeNAK</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endPControlReg</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEPRdy</span>;
+<span id=t_kwd>input</span> <span id=t_idt>endPMuxErrorsWEn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> <span id=t_idt>clrEP0Rdy</span>;
+<span id=t_kwd>output</span> <span id=t_idt>clrEP1Rdy</span>;
+<span id=t_kwd>output</span> <span id=t_idt>clrEP2Rdy</span>;
+<span id=t_kwd>output</span> <span id=t_idt>clrEP3Rdy</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>NAKSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>stallSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>CRCError</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxOverflow</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxTimeOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>dataSequence</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>ACKRxed</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transTypeNAK</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endPControlReg</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEPRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>endPMuxErrorsWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrEP0Rdy</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrEP1Rdy</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrEP2Rdy</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrEP3Rdy</span>;
+
+<span id=t_com>//internal wires and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endPStatusCombine</span>;
+
+<span id=t_com>//mux endPControlReg and clrEPRdy</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>currEndP</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>])
+    <span id=t_cns>2'b00</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>endPControlReg</span> &lt;= <span id=t_idt>endP0ControlReg</span>;
+      <span id=t_idt>clrEP0Rdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b01</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>endPControlReg</span> &lt;= <span id=t_idt>endP1ControlReg</span>;
+      <span id=t_idt>clrEP1Rdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b10</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>endPControlReg</span> &lt;= <span id=t_idt>endP2ControlReg</span>;
+      <span id=t_idt>clrEP2Rdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b11</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>endPControlReg</span> &lt;= <span id=t_idt>endP3ControlReg</span>;
+      <span id=t_idt>clrEP3Rdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>  
+<span id=t_kwd>end</span>      
+
+<span id=t_com>//mux endPNAKTransType, endPTransType, endPStatusReg</span>
+<span id=t_com>//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.</span>
+<span id=t_com>//else update the entire status reg</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>endP0NAKTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP1NAKTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP2NAKTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP3NAKTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP0TransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP1TransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP2TransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP3TransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP0StatusReg</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>endP1StatusReg</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>endP2StatusReg</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>endP3StatusReg</span> &lt;= <span id=t_cns>4'h0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>endPMuxErrorsWEn</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>NAKSent</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+        <span id=t_kwd>case</span> (<span id=t_idt>currEndP</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>])
+          <span id=t_cns>2'b00</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP0NAKTransTypeReg</span> &lt;= <span id=t_idt>transTypeNAK</span>;
+            <span id=t_idt>endP0StatusReg</span> &lt;= <span id=t_idt>endP0StatusReg</span> | `<span id=t_idt>NAK_SET_MASK</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b01</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP1NAKTransTypeReg</span> &lt;= <span id=t_idt>transTypeNAK</span>;
+            <span id=t_idt>endP1StatusReg</span> &lt;= <span id=t_idt>endP1StatusReg</span> | `<span id=t_idt>NAK_SET_MASK</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b10</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP2NAKTransTypeReg</span> &lt;= <span id=t_idt>transTypeNAK</span>;
+            <span id=t_idt>endP2StatusReg</span> &lt;= <span id=t_idt>endP2StatusReg</span> | `<span id=t_idt>NAK_SET_MASK</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b11</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP3NAKTransTypeReg</span> &lt;= <span id=t_idt>transTypeNAK</span>;
+            <span id=t_idt>endP3StatusReg</span> &lt;= <span id=t_idt>endP3StatusReg</span> | `<span id=t_idt>NAK_SET_MASK</span>; 
+          <span id=t_kwd>end</span>
+        <span id=t_kwd>endcase</span>
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+        <span id=t_kwd>case</span> (<span id=t_idt>currEndP</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>])
+          <span id=t_cns>2'b00</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP0TransTypeReg</span> &lt;= <span id=t_idt>transType</span>;
+            <span id=t_idt>endP0StatusReg</span> &lt;= <span id=t_idt>endPStatusCombine</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b01</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP1TransTypeReg</span> &lt;= <span id=t_idt>transType</span>;
+            <span id=t_idt>endP1StatusReg</span> &lt;= <span id=t_idt>endPStatusCombine</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b10</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP2TransTypeReg</span> &lt;= <span id=t_idt>transType</span>;
+            <span id=t_idt>endP2StatusReg</span> &lt;= <span id=t_idt>endPStatusCombine</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b11</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP3TransTypeReg</span> &lt;= <span id=t_idt>transType</span>;
+            <span id=t_idt>endP3StatusReg</span> &lt;= <span id=t_idt>endPStatusCombine</span>; 
+          <span id=t_kwd>end</span>
+        <span id=t_kwd>endcase</span>
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+        
+
+<span id=t_com>//combine status bits into a single word</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>dataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>stallSent</span> <span id=t_kwd>or</span> <span id=t_idt>RxTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>RxOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>endPStatusCombine</span> &lt;= {<span id=t_idt>dataSequence</span>, <span id=t_idt>ACKRxed</span>, <span id=t_idt>stallSent</span>, <span id=t_cns>1'b0</span>, <span id=t_idt>RxTimeOut</span>, <span id=t_idt>RxOverflow</span>, <span id=t_idt>bitStuffError</span>, <span id=t_idt>CRCError</span>};
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/endpMux.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveDirectcontrol IDLE" alt="slaveDirectcontrol IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar78.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram78.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_IDLE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_IDLE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveGetpacket" alt="slaveGetpacket"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index.htm
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Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm	(revision 264)
@@ -0,0 +1,406 @@
+<html>
+<head>
+<title>USBSlaveControlBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBSlaveControlBI.v                                          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:43 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbSlaveControl_h.v"</span>
+ 
+<span id=t_kwd>module</span> <span id=t_idt>USBSlaveControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>SOFRxedIntOut</span>, <span id=t_idt>resetEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>, <span id=t_idt>NAKSentIntOut</span>,
+  <span id=t_idt>endP0TransTypeReg</span>, <span id=t_idt>endP0NAKTransTypeReg</span>,
+  <span id=t_idt>endP1TransTypeReg</span>, <span id=t_idt>endP1NAKTransTypeReg</span>,
+  <span id=t_idt>endP2TransTypeReg</span>, <span id=t_idt>endP2NAKTransTypeReg</span>,
+  <span id=t_idt>endP3TransTypeReg</span>, <span id=t_idt>endP3NAKTransTypeReg</span>,
+  <span id=t_idt>endP0ControlReg</span>,
+  <span id=t_idt>endP1ControlReg</span>,
+  <span id=t_idt>endP2ControlReg</span>,
+  <span id=t_idt>endP3ControlReg</span>,
+  <span id=t_idt>EP0StatusReg</span>,
+  <span id=t_idt>EP1StatusReg</span>,
+  <span id=t_idt>EP2StatusReg</span>,
+  <span id=t_idt>EP3StatusReg</span>,
+  <span id=t_idt>SCAddrReg</span>, <span id=t_idt>frameNum</span>,
+  <span id=t_idt>connectStateIn</span>,
+  <span id=t_idt>SOFRxedIn</span>, <span id=t_idt>resetEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>, <span id=t_idt>NAKSentIn</span>,
+  <span id=t_idt>slaveControlSelect</span>,
+  <span id=t_idt>clrEP0Ready</span>, <span id=t_idt>clrEP1Ready</span>, <span id=t_idt>clrEP2Ready</span>, <span id=t_idt>clrEP3Ready</span>,
+  <span id=t_idt>TxLineState</span>,
+  <span id=t_idt>LineDirectControlEn</span>,
+  <span id=t_idt>fullSpeedPol</span>, 
+  <span id=t_idt>fullSpeedRate</span>,
+  <span id=t_idt>SCGlobalEn</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFRxedIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resetEventIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>NAKSentIntOut</span>;
+
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP0StatusReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP1StatusReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP2StatusReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP3StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>SCAddrReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SOFRxedIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resetEventIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>NAKSentIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>slaveControlSelect</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEP0Ready</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEP1Ready</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEP2Ready</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEP3Ready</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SCGlobalEn</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>SOFRxedIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resetEventIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>NAKSentIntOut</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP0StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP1StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP2StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP3StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>SCAddrReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>SOFRxedIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resetEventIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>NAKSentIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP0Ready</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP1Ready</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP2Ready</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP3Ready</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SCGlobalEn</span>;
+
+<span id=t_com>//internal wire and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>5</span>:<span id=t_cns>0</span>] <span id=t_idt>SCControlReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrNAKReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResetReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFRxedInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resetEventInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>NAKSentInt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0SetReady</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1SetReady</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2SetReady</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3SetReady</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0SendStall</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1SendStall</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2SendStall</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3SendStall</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0DataSequence</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1DataSequence</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2DataSequence</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3DataSequence</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0Enable</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1Enable</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2Enable</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3Enable</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0Ready</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1Ready</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2Ready</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3Ready</span>;
+
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>clrNAKReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResetReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResInReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>EP0SetReady</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>EP1SetReady</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>EP2SetReady</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>EP3SetReady</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>slaveControlSelect</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+      `<span id=t_idt>EP0_CTRL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>EP0SendStall</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>EP0DataSequence</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>EP0SetReady</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>EP0Enable</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+      `<span id=t_idt>EP1_CTRL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>EP1SendStall</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>EP1DataSequence</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>EP1SetReady</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>EP1Enable</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+      `<span id=t_idt>EP2_CTRL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>EP2SendStall</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>EP2DataSequence</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>EP2SetReady</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>EP2Enable</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+      `<span id=t_idt>EP3_CTRL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>EP3SendStall</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>EP3DataSequence</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>EP3SetReady</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>EP3Enable</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>SC_CONTROL_REG</span> : <span id=t_idt>SCControlReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>5</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>SC_ADDRESS</span> : <span id=t_idt>SCAddrReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>SC_INTERRUPT_STATUS_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>clrNAKReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>];
+        <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>clrResetReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>clrResInReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>SC_INTERRUPT_MASK_REG</span> : <span id=t_idt>interruptMaskReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>];
+   <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//interrupt control </span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>NAKSentIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>NAKSentInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrNAKReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>NAKSentInt</span> &lt;= <span id=t_cns>1'b0</span>; 
+    
+  <span id=t_kwd>if</span> (<span id=t_idt>SOFRxedIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFRxedInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFRxedInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resetEventIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resetEventInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResetReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resetEventInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b0</span>;  
+
+  <span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//mask interrupts</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>resetEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFRxedInt</span> <span id=t_kwd>or</span> <span id=t_idt>NAKSentInt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>transDoneIntOut</span> &lt;= <span id=t_idt>transDoneInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>];
+  <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_idt>resumeInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>];
+  <span id=t_idt>resetEventIntOut</span> &lt;= <span id=t_idt>resetEventInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESET_EVENT_BIT</span>];
+  <span id=t_idt>SOFRxedIntOut</span> &lt;= <span id=t_idt>SOFRxedInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_RECEIVED_BIT</span>];
+  <span id=t_idt>NAKSentIntOut</span> &lt;= <span id=t_idt>NAKSentInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>NAK_SENT_INT_BIT</span>];
+<span id=t_kwd>end</span>  
+
+<span id=t_com>//end point ready, set/clear</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>EP0SetReady</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP0Ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrEP0Ready</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP0Ready</span> &lt;= <span id=t_cns>1'b0</span>;
+    
+  <span id=t_kwd>if</span> (<span id=t_idt>EP1SetReady</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP1Ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrEP1Ready</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP1Ready</span> &lt;= <span id=t_cns>1'b0</span>;
+    
+  <span id=t_kwd>if</span> (<span id=t_idt>EP2SetReady</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP2Ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrEP2Ready</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP2Ready</span> &lt;= <span id=t_cns>1'b0</span>;
+    
+  <span id=t_kwd>if</span> (<span id=t_idt>EP3SetReady</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP3Ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrEP3Ready</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP3Ready</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//break out control signals</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>SCControlReg</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>SCGlobalEn</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_GLOBAL_ENABLE_BIT</span>];
+  <span id=t_idt>TxLineState</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>SC_TX_LINE_STATE_LSBIT</span>];
+  <span id=t_idt>LineDirectControlEn</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_DIRECT_CONTROL_BIT</span>];
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_FULL_SPEED_LINE_POLARITY_BIT</span>]; 
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_FULL_SPEED_LINE_RATE_BIT</span>];
+<span id=t_kwd>end</span>
+
+<span id=t_com>//combine endpoint control signals </span>
+<span id=t_kwd>always</span> @(<span id=t_idt>EP0SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP0Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP0DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP0Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP1SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP1Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP1DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP1Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP2SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP2Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP2DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP2Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP3SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP3Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP3DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP3Enable</span>) 
+<span id=t_kwd>begin</span>
+  <span id=t_idt>endP0ControlReg</span> &lt;= {<span id=t_idt>EP0SendStall</span>, <span id=t_idt>EP0DataSequence</span>, <span id=t_idt>EP0Ready</span>, <span id=t_idt>EP0Enable</span>};
+  <span id=t_idt>endP1ControlReg</span> &lt;= {<span id=t_idt>EP1SendStall</span>, <span id=t_idt>EP1DataSequence</span>, <span id=t_idt>EP1Ready</span>, <span id=t_idt>EP1Enable</span>};
+  <span id=t_idt>endP2ControlReg</span> &lt;= {<span id=t_idt>EP2SendStall</span>, <span id=t_idt>EP2DataSequence</span>, <span id=t_idt>EP2Ready</span>, <span id=t_idt>EP2Enable</span>};
+  <span id=t_idt>endP3ControlReg</span> &lt;= {<span id=t_idt>EP3SendStall</span>, <span id=t_idt>EP3DataSequence</span>, <span id=t_idt>EP3Ready</span>, <span id=t_idt>EP3Enable</span>};
+<span id=t_kwd>end</span>
+      
+      
+      <span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP0SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP0Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP0DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP0Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP1SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP1Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP1DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP1Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP2SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP2Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP2DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP2Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP3SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP3Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP3DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP3Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP0StatusReg</span> <span id=t_kwd>or</span> <span id=t_idt>EP1StatusReg</span> <span id=t_kwd>or</span> <span id=t_idt>EP2StatusReg</span> <span id=t_kwd>or</span> <span id=t_idt>EP3StatusReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>endP0ControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP1ControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP2ControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP3ControlReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>endP0NAKTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP1NAKTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP2NAKTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP3NAKTransTypeReg</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>endP0TransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP1TransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP2TransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP3TransTypeReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>SCControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>NAKSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFRxedInt</span> <span id=t_kwd>or</span> <span id=t_idt>resetEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span>
+  <span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>SCAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNum</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+      `<span id=t_idt>EP0_CTRL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP0ControlReg</span>;
+      `<span id=t_idt>EP0_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>EP0StatusReg</span>;
+      `<span id=t_idt>EP0_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP0TransTypeReg</span>;
+      `<span id=t_idt>EP0_NAK_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP0NAKTransTypeReg</span>;
+      `<span id=t_idt>EP1_CTRL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP1ControlReg</span>;
+      `<span id=t_idt>EP1_STS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>EP1StatusReg</span>;
+      `<span id=t_idt>EP1_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP1TransTypeReg</span>;
+      `<span id=t_idt>EP1_NAK_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP1NAKTransTypeReg</span>;
+      `<span id=t_idt>EP2_CTRL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP2ControlReg</span>;
+      `<span id=t_idt>EP2_STS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>EP2StatusReg</span>;
+      `<span id=t_idt>EP2_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP2TransTypeReg</span>;
+      `<span id=t_idt>EP2_NAK_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP2NAKTransTypeReg</span>;
+      `<span id=t_idt>EP3_CTRL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP3ControlReg</span>;
+      `<span id=t_idt>EP3_STS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>EP3StatusReg</span>;
+      `<span id=t_idt>EP3_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP3TransTypeReg</span>;
+      `<span id=t_idt>EP3_NAK_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP3NAKTransTypeReg</span>;
+     `<span id=t_idt>SC_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>SCControlReg</span>;
+     `<span id=t_idt>SC_LINE_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>}; 
+     `<span id=t_idt>SC_INTERRUPT_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>NAKSentInt</span>, <span id=t_idt>SOFRxedInt</span>, <span id=t_idt>resetEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>};
+     `<span id=t_idt>SC_INTERRUPT_MASK_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>interruptMaskReg</span>};
+     `<span id=t_idt>SC_ADDRESS</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>SCAddrReg</span>};
+     `<span id=t_idt>SC_FRAME_NUM_MSP</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>frameNum</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>];
+     `<span id=t_idt>SC_FRAME_NUM_LSP</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNum</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]};
+      <span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveDirectcontrol" alt="slaveDirectcontrol"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index127.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index127.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index127.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar127.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram127.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index127.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_DRCT_CNTL.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_DRCT_CNTL.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 78 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveDirectcontrol_DRCT_CNTL.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveDirectcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveGetpacket DATA" alt="slaveGetpacket DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar58.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram58.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_LOOP.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_LOOP.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 64 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_LS_CONN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm	(revision 264)
@@ -0,0 +1,122 @@
+<html>
+<head>
+<title>updateCRC16.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// updateCRC16.v                                                ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:02 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>updateCRC16</span> (<span id=t_idt>rstCRC</span>, <span id=t_idt>CRCResult</span>, <span id=t_idt>CRCEn</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>ready</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>rstCRC</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRCEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCResult</span>;
+<span id=t_kwd>output</span> <span id=t_idt>ready</span>;
+
+<span id=t_kwd>wire</span>   <span id=t_idt>rstCRC</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>CRCEn</span>;
+<span id=t_kwd>wire</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>    [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCResult</span>;
+<span id=t_kwd>reg</span>    <span id=t_idt>ready</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>doUpdateCRC</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>i</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span> || <span id=t_idt>rstCRC</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>CRCResult</span> &lt;= <span id=t_cns>16'hffff</span>;
+    <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>doUpdateCRC</span> == <span id=t_cns>1'b0</span>)
+    <span id=t_kwd>begin</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>CRCEn</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>doUpdateCRC</span> = <span id=t_cns>1'b1</span>;
+        <span id=t_idt>data</span> &lt;= <span id=t_idt>dataIn</span>;
+        <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+      <span id=t_idt>i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>if</span> ( (<span id=t_idt>CRCResult</span>[<span id=t_cns>0</span>] ^ <span id=t_idt>data</span>[<span id=t_cns>0</span>]) == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>CRCResult</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>CRCResult</span>[<span id=t_cns>15</span>:<span id=t_cns>1</span>]} ^ <span id=t_cns>16'ha001</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+        <span id=t_idt>CRCResult</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>CRCResult</span>[<span id=t_cns>15</span>:<span id=t_cns>1</span>]};
+      <span id=t_kwd>end</span>
+      <span id=t_idt>data</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>data</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>]};
+      <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>4'h7</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b0</span>; 
+        <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+        <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+   
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm	(revision 264)
@@ -0,0 +1,320 @@
+<html>
+<head>
+<title>writeUSBWireData.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// writeUSBWireData.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:08 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_dir>`define</span> <span id=t_idt>BUFFER_FULL</span>  <span id=t_cns>3'b100</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>writeUSBWireData</span> (
+  <span id=t_idt>TxBitsIn</span>, 
+  <span id=t_idt>TxBitsOut</span>,
+  <span id=t_idt>TxDataOutTick</span>,
+  <span id=t_idt>TxCtrlIn</span>, 
+  <span id=t_idt>TxCtrlOut</span>, 
+  <span id=t_idt>USBWireRdy</span>,
+  <span id=t_idt>USBWireWEn</span>, 
+  <span id=t_idt>disableWireReadOut</span>, 
+  <span id=t_idt>fullSpeedRate</span>, 
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>,
+  <span id=t_idt>noActivityTimeOut</span> );
+  
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>TxCtrlIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxDataOutTick</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>TxCtrlOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>disableWireReadOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>noActivityTimeOut</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsIn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>TxDataOutTick</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>TxCtrlIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>TxCtrlOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>disableWireReadOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>noActivityTimeOut</span>;
+
+<span id=t_com>// local registers</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer0</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer1</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer2</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer3</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferInIndex</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferOutIndex</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>decBufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>4</span>:<span id=t_cns>0</span>]<span id=t_idt>i</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>incBufferCnt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedTick</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>lowSpeedTick</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>timeOutCnt</span>;
+
+<span id=t_com>// buffer in state machine state codes:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BUFFER_NOT_FULL</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_WRITE_REQ</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>CLR_INC_BUFFER_CNT</span> <span id=t_cns>2'b10</span>
+
+<span id=t_com>// buffer output state machine state codes:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BUFFER_FULL</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LINE_WRITE</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>LINE_WRITE</span> <span id=t_cns>2'b10</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>bufferInStMachCurrState</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>bufferOutStMachCurrState</span>;
+
+<span id=t_com>// buffer control</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>bufferCnt</span> &lt;= <span id=t_cns>3'b000</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>incBufferCnt</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>decBufferCnt</span> == <span id=t_cns>1'b0</span>)
+      <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>incBufferCnt</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>decBufferCnt</span> == <span id=t_cns>1'b1</span>)
+      <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> - <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//buffer input state machine </span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer0</span> &lt;= <span id=t_cns>3'b000</span>;
+   <span id=t_idt>buffer1</span> &lt;= <span id=t_cns>3'b000</span>;
+   <span id=t_idt>buffer2</span> &lt;= <span id=t_cns>3'b000</span>;
+   <span id=t_idt>buffer3</span> &lt;= <span id=t_cns>3'b000</span>;
+   <span id=t_idt>USBWireRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_NOT_FULL</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>case</span> (<span id=t_idt>bufferInStMachCurrState</span>)
+     `<span id=t_idt>WAIT_BUFFER_NOT_FULL</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span> != `<span id=t_idt>BUFFER_FULL</span>) 
+       <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_WRITE_REQ</span>;
+        <span id=t_idt>USBWireRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+       <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>WAIT_WRITE_REQ</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>USBWireWEn</span> == <span id=t_cns>1'b1</span>)
+       <span id=t_kwd>begin</span>
+        <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>USBWireRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+        <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_idt>bufferInIndex</span> + <span id=t_cns>1'b1</span>;
+        <span id=t_kwd>case</span> (<span id=t_idt>bufferInIndex</span>)
+          <span id=t_cns>2'b00</span> : <span id=t_idt>buffer0</span> &lt;= {<span id=t_idt>TxBitsIn</span>, <span id=t_idt>TxCtrlIn</span>};
+          <span id=t_cns>2'b01</span> : <span id=t_idt>buffer1</span> &lt;= {<span id=t_idt>TxBitsIn</span>, <span id=t_idt>TxCtrlIn</span>};
+          <span id=t_cns>2'b10</span> : <span id=t_idt>buffer2</span> &lt;= {<span id=t_idt>TxBitsIn</span>, <span id=t_idt>TxCtrlIn</span>};
+          <span id=t_cns>2'b11</span> : <span id=t_idt>buffer3</span> &lt;= {<span id=t_idt>TxBitsIn</span>, <span id=t_idt>TxCtrlIn</span>};
+        <span id=t_kwd>endcase</span>
+        <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>CLR_INC_BUFFER_CNT</span>;
+       <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>CLR_INC_BUFFER_CNT</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+       <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span> != (`<span id=t_idt>BUFFER_FULL</span> - <span id=t_cns>1'b1</span>) ) 
+       <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_WRITE_REQ</span>;
+        <span id=t_idt>USBWireRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+       <span id=t_kwd>end</span>
+        <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+         <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_NOT_FULL</span>;
+        <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+    <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+      
+<span id=t_com>//increment counter used to generate USB bit rate</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>i</span> &lt;= <span id=t_cns>5'b00000</span>;
+    <span id=t_idt>fullSpeedTick</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_idt>lowSpeedTick</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>if</span> (<span id=t_idt>i</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == <span id=t_cns>2'b00</span>)
+      <span id=t_idt>fullSpeedTick</span> &lt;= <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span>
+      <span id=t_idt>fullSpeedTick</span> &lt;= <span id=t_cns>1'b0</span>; 
+    <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>5'b00000</span>)
+      <span id=t_idt>lowSpeedTick</span> &lt;= <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span>
+      <span id=t_idt>lowSpeedTick</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//buffer output state machine</span>
+<span id=t_com>//After reset, waits for the output buffer to become full.</span>
+<span id=t_com>//Once the buffer is full then it is constantly emptied at either</span>
+<span id=t_com>//the full or low speed rate with no under run protection</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>TxCtrlOut</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+    <span id=t_idt>TxDataOutTick</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_FULL</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_kwd>case</span> (<span id=t_idt>bufferOutStMachCurrState</span>)
+     `<span id=t_idt>WAIT_BUFFER_FULL</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span> == `<span id=t_idt>BUFFER_FULL</span>)
+        <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_LINE_WRITE</span>;
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>WAIT_LINE_WRITE</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> ((<span id=t_idt>fullSpeedRate</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fullSpeedTick</span> == <span id=t_cns>1'b1</span>) || (<span id=t_idt>fullSpeedRate</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>lowSpeedTick</span> == <span id=t_cns>1'b1</span>) )
+       <span id=t_kwd>begin</span>
+          <span id=t_idt>TxDataOutTick</span> &lt;= !<span id=t_idt>TxDataOutTick</span>;
+        <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>LINE_WRITE</span>;
+        <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_idt>bufferOutIndex</span> + <span id=t_cns>1'b1</span>;
+        <span id=t_kwd>case</span> (<span id=t_idt>bufferOutIndex</span>)
+          <span id=t_cns>2'b00</span> :
+        <span id=t_kwd>begin</span> 
+          <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_idt>buffer0</span>[<span id=t_cns>2</span>:<span id=t_cns>1</span>];
+          <span id=t_idt>TxCtrlOut</span> &lt;= <span id=t_idt>buffer0</span>[<span id=t_cns>0</span>];
+        <span id=t_kwd>end</span>
+        <span id=t_cns>2'b01</span> : 
+        <span id=t_kwd>begin</span>
+          <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_idt>buffer1</span>[<span id=t_cns>2</span>:<span id=t_cns>1</span>];
+          <span id=t_idt>TxCtrlOut</span> &lt;= <span id=t_idt>buffer1</span>[<span id=t_cns>0</span>];
+        <span id=t_kwd>end</span>
+        <span id=t_cns>2'b10</span> : 
+        <span id=t_kwd>begin</span> 
+          <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_idt>buffer2</span>[<span id=t_cns>2</span>:<span id=t_cns>1</span>];
+          <span id=t_idt>TxCtrlOut</span> &lt;= <span id=t_idt>buffer2</span>[<span id=t_cns>0</span>];
+        <span id=t_kwd>end</span>
+        <span id=t_cns>2'b11</span> : 
+        <span id=t_kwd>begin</span>
+          <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_idt>buffer3</span>[<span id=t_cns>2</span>:<span id=t_cns>1</span>];
+          <span id=t_idt>TxCtrlOut</span> &lt;= <span id=t_idt>buffer3</span>[<span id=t_cns>0</span>];
+        <span id=t_kwd>end</span>
+        <span id=t_kwd>endcase</span>
+       <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>LINE_WRITE</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+       <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_LINE_WRITE</span>;
+     <span id=t_kwd>end</span>
+    <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>// control 'disableWireReadOut' </span>
+<span id=t_kwd>always</span> @(<span id=t_idt>TxCtrlOut</span>)
+<span id=t_kwd>begin</span> 
+  <span id=t_kwd>if</span> (<span id=t_idt>TxCtrlOut</span> == `<span id=t_idt>DRIVE</span>)
+   <span id=t_idt>disableWireReadOut</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>disableWireReadOut</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>timeOutCnt</span> &lt;= <span id=t_cns>16'h0000</span>;
+    <span id=t_idt>noActivityTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>TxCtrlOut</span> == `<span id=t_idt>DRIVE</span>)
+      <span id=t_idt>timeOutCnt</span> &lt;= <span id=t_cns>16'h0000</span>;
+    <span id=t_kwd>else</span> 
+      <span id=t_idt>timeOutCnt</span> &lt;= <span id=t_idt>timeOutCnt</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_com>//if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>timeOutCnt</span> == <span id=t_cns>16'h200</span>)  <span id=t_com>//temporary fix</span>
+      <span id=t_idt>noActivityTimeOut</span> &lt;= <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span>
+      <span id=t_idt>noActivityTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sctxportarbiter" alt="sctxportarbiter"
+				width=2040 height=2640 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 3400 ;
+var PageY = 4400 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 2040;
+var h = 2640;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sctxportarbiter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sctxportarbiter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm	(revision 264)
@@ -0,0 +1,210 @@
+<html>
+<head>
+<title>slaveDirectcontrol.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveDirectControl</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:26 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>slaveDirectControl</span> (<span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>SCTxPortData</span>, <span id=t_idt>SCTxPortGnt</span>, <span id=t_idt>SCTxPortRdy</span>, <span id=t_idt>SCTxPortReq</span>, <span id=t_idt>SCTxPortWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>directControlEn</span>, <span id=t_idt>directControlLineState</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directControlEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directControlLineState</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortWEn</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>next_SCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>, <span id=t_idt>next_SCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortReq</span>, <span id=t_idt>next_SCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortWEn</span>, <span id=t_idt>next_SCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directControlEn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directControlLineState</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: slvDrctCntl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SDC</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_DRCT_CNTL</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_WAIT_GNT</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_CHK_LOOP</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_WAIT_RDY</span> <span id=t_cns>3'b100</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_FIN</span> <span id=t_cns>3'b101</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_GNT</span> <span id=t_cns>3'b110</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_RDY</span> <span id=t_cns>3'b111</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_slvDrctCntl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_slvDrctCntl</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// diagram ACTION</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: slvDrctCntl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>directControlLineState</span> <span id=t_kwd>or</span> <span id=t_idt>directControlEn</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_slvDrctCntl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvDrctCntl_NextState</span>
+  <span id=t_idt>NextState_slvDrctCntl</span> &lt;= <span id=t_idt>CurrState_slvDrctCntl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_idt>SCTxPortReq</span>;
+  <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_idt>SCTxPortWEn</span>;
+  <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_idt>SCTxPortData</span>;
+  <span id=t_idt>next_SCTxPortCntl</span> &lt;= <span id=t_idt>SCTxPortCntl</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_slvDrctCntl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SDC</span>:
+     <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+   `<span id=t_idt>CHK_DRCT_CNTL</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>directControlEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_GNT</span>;
+      <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>IDLE_WAIT_GNT</span>;
+      <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DRCT_CNTL_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>;
+   `<span id=t_idt>DRCT_CNTL_CHK_LOOP</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>directControlEn</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+      <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_CHK_LOOP</span>;
+      <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SCTxPortData</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>directControlLineState</span>};
+      <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_DIRECT_CONTROL</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>IDLE_WAIT_RDY</span>;
+   `<span id=t_idt>IDLE_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>IDLE_FIN</span>;
+      <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_IDLE</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvDrctCntl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_slvDrctCntl</span> &lt;= `<span id=t_idt>START_SDC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_slvDrctCntl</span> &lt;= <span id=t_idt>NextState_slvDrctCntl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvDrctCntl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_idt>next_SCTxPortCntl</span>;
+   <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_idt>next_SCTxPortData</span>;
+   <span id=t_idt>SCTxPortWEn</span> &lt;= <span id=t_idt>next_SCTxPortWEn</span>;
+   <span id=t_idt>SCTxPortReq</span> &lt;= <span id=t_idt>next_SCTxPortReq</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 127 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveDirectcontrol_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveDirectcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveGetpacket PROC_PKT" alt="slaveGetpacket PROC_PKT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar33.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram33.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_DATA.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 112 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveGetpacket_LOOP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveGetpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_PROC_PKT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_PROC_PKT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar58.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar58.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar58.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(662,1601,764,1703,Click112,Over112);
+
+//----------------------------------------------------------------------------
+function Click112(){fubclick('./index112.htm');}
+function Over112(){window.status='Hierarchical State LOOP';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 58 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveGetpacket_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveGetpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar58.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram45.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram45.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram45.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveSendpacket SP_D0_D1" alt="slaveSendpacket SP_D0_D1"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1244,949,1347,1051,Click58,Over58);
+
+//----------------------------------------------------------------------------
+function Click58(){fubclick('./index58.htm');}
+function Over58(){window.status='Hierarchical State DATA';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 33 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveGetpacket_PROC_PKT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveGetpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveSendpacket SP_SEND_PID" alt="slaveSendpacket SP_SEND_PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index45.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index45.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index45.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar45.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram45.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index45.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram112.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram112.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram112.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveGetpacket LOOP" alt="slaveGetpacket LOOP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/diagram112.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index112.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index112.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index112.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
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+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
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+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar112.html" marginwidth="0" marginheight="0">
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+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/index112.htm
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Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm	(revision 264)
@@ -0,0 +1,351 @@
+<html>
+<head>
+<title>slaveGetpacket.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveGetPacket</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:35 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>slaveGetPacket</span> (<span id=t_idt>ACKRxed</span>, <span id=t_idt>CRCError</span>, <span id=t_idt>RXDataIn</span>, <span id=t_idt>RXDataValid</span>, <span id=t_idt>RXFifoData</span>, <span id=t_idt>RXFifoFull</span>, <span id=t_idt>RXFifoWEn</span>, <span id=t_idt>RXOverflow</span>, <span id=t_idt>RXPacketRdy</span>, <span id=t_idt>RXStreamStatusIn</span>, <span id=t_idt>RXTimeOut</span>, <span id=t_idt>RxPID</span>, <span id=t_idt>SIERxTimeOut</span>, <span id=t_idt>bitStuffError</span>, <span id=t_idt>clk</span>, <span id=t_idt>dataSequence</span>, <span id=t_idt>getPacketEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXDataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RXDataValid</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RXFifoFull</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStreamStatusIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIERxTimeOut</span>;   <span id=t_com>// Single cycle pulse</span>
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>getPacketEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>ACKRxed</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRCError</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXFifoData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXFifoWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXOverflow</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXPacketRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXTimeOut</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>dataSequence</span>;
+
+<span id=t_kwd>reg</span>     <span id=t_idt>ACKRxed</span>, <span id=t_idt>next_ACKRxed</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRCError</span>, <span id=t_idt>next_CRCError</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXDataIn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RXDataValid</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXFifoData</span>, <span id=t_idt>next_RXFifoData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RXFifoFull</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXFifoWEn</span>, <span id=t_idt>next_RXFifoWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXOverflow</span>, <span id=t_idt>next_RXOverflow</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXPacketRdy</span>, <span id=t_idt>next_RXPacketRdy</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStreamStatusIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXTimeOut</span>, <span id=t_idt>next_RXTimeOut</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>, <span id=t_idt>next_RxPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>bitStuffError</span>, <span id=t_idt>next_bitStuffError</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>dataSequence</span>, <span id=t_idt>next_dataSequence</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>getPacketEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteOld</span>, <span id=t_idt>next_RXByteOld</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteOldest</span>, <span id=t_idt>next_RXByteOldest</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByte</span>, <span id=t_idt>next_RXByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXStreamStatus</span>, <span id=t_idt>next_RXStreamStatus</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: slvGetPkt</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_CHK_PID</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_HS</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D1</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D1</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D2</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_FIN</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D2</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D3</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D3</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_GP</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_PKT</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PKT_START</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_EN</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_RDY</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span> <span id=t_cns>5'b10001</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_slvGetPkt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_slvGetPkt</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: slvGetPkt</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RXDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>RXStreamStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RXByte</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteOldest</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteOld</span> <span id=t_kwd>or</span> <span id=t_idt>RXDataValid</span> <span id=t_kwd>or</span> <span id=t_idt>RXStreamStatus</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoFull</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>RXOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RXTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>dataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>RxPID</span> <span id=t_kwd>or</span> <span id=t_idt>RXPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoData</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_slvGetPkt</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvGetPkt_NextState</span>
+  <span id=t_idt>NextState_slvGetPkt</span> &lt;= <span id=t_idt>CurrState_slvGetPkt</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>CRCError</span>;
+  <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>bitStuffError</span>;
+  <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_idt>RXOverflow</span>;
+  <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_idt>RXTimeOut</span>;
+  <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>ACKRxed</span>;
+  <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>dataSequence</span>;
+  <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXByte</span>;
+  <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatus</span>;
+  <span id=t_idt>next_RxPID</span> &lt;= <span id=t_idt>RxPID</span>;
+  <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_idt>RXPacketRdy</span>;
+  <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByteOldest</span>;
+  <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByteOld</span>;
+  <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_idt>RXFifoWEn</span>;
+  <span id=t_idt>next_RXFifoData</span> &lt;= <span id=t_idt>RXFifoData</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_slvGetPkt</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_GP</span>:
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>WAIT_EN</span>;
+   `<span id=t_idt>WAIT_PKT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>CHK_PKT_START</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PKT_START</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_START</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_CHK_PID</span>;
+      <span id=t_idt>next_RxPID</span> &lt;= <span id=t_idt>RXByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_EN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketEn</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>WAIT_PKT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_CHK_PID</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>HANDSHAKE</span>) 
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_HS</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>DATA</span>) 
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+   `<span id=t_idt>PROC_PKT_HS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>RX_OVERFLOW_BIT</span>];
+      <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>ACK_RXED_BIT</span>];
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_W_D1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D1</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D2</span>;
+      <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_W_D2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D2</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>CRC_ERROR_BIT</span>];
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>BIT_STUFF_ERROR_BIT</span>];
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>DATA_SEQUENCE_BIT</span>];
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D3</span>;
+      <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_W_D3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D3</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXFifoFull</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span>;
+      <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>;
+      <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_RXFifoData</span> &lt;= <span id=t_idt>RXByteOldest</span>;
+      <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByteOld</span>;
+      <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span>:
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>;
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> ((<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStreamStatusIn</span> == `<span id=t_idt>RX_PACKET_STREAM</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span>:
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvGetPkt_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_slvGetPkt</span> &lt;= `<span id=t_idt>START_GP</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_slvGetPkt</span> &lt;= <span id=t_idt>NextState_slvGetPkt</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvGetPkt_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXByteOld</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXByteOldest</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXStreamStatus</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXFifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXFifoData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RxPID</span> &lt;= <span id=t_cns>4'h0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXByteOld</span> &lt;= <span id=t_idt>next_RXByteOld</span>;
+   <span id=t_idt>RXByteOldest</span> &lt;= <span id=t_idt>next_RXByteOldest</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_idt>next_RXByte</span>;
+   <span id=t_idt>RXStreamStatus</span> &lt;= <span id=t_idt>next_RXStreamStatus</span>;
+   <span id=t_idt>RXPacketRdy</span> &lt;= <span id=t_idt>next_RXPacketRdy</span>;
+   <span id=t_idt>RXFifoWEn</span> &lt;= <span id=t_idt>next_RXFifoWEn</span>;
+   <span id=t_idt>RXFifoData</span> &lt;= <span id=t_idt>next_RXFifoData</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_idt>next_CRCError</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_idt>next_bitStuffError</span>;
+   <span id=t_idt>RXOverflow</span> &lt;= <span id=t_idt>next_RXOverflow</span>;
+   <span id=t_idt>RXTimeOut</span> &lt;= <span id=t_idt>next_RXTimeOut</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_idt>next_ACKRxed</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_idt>next_dataSequence</span>;
+   <span id=t_idt>RxPID</span> &lt;= <span id=t_idt>next_RxPID</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1061,1577,1163,1679,Click33,Over33);
+
+//----------------------------------------------------------------------------
+function Click33(){fubclick('./index33.htm');}
+function Over33(){window.status='Hierarchical State PROC_PKT';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveGetpacket.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveGetpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm	(revision 264)
@@ -0,0 +1,112 @@
+<html>
+<head>
+<title>slaveRxStatusMonitor.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveRxStatusMonitor.v                                       ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:36 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>slaveRxStatusMonitor</span>(<span id=t_idt>connectStateIn</span>, <span id=t_idt>connectStateOut</span>, <span id=t_idt>resumeDetectedIn</span>, <span id=t_idt>resetEventOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resetEventOut</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resetEventOut</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>oldConnectState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>oldResumeDetected</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_idt>connectStateIn</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>connectStateOut</span> &lt;= <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>oldConnectState</span> &lt;= <span id=t_idt>connectStateIn</span>;
+   <span id=t_idt>oldResumeDetected</span> &lt;= <span id=t_idt>resumeDetectedIn</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>oldConnectState</span> &lt;= <span id=t_idt>connectStateIn</span>;
+   <span id=t_idt>oldResumeDetected</span> &lt;= <span id=t_idt>resumeDetectedIn</span>;
+   <span id=t_kwd>if</span> (<span id=t_idt>oldConnectState</span> != <span id=t_idt>connectStateIn</span>)
+     <span id=t_idt>resetEventOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>else</span>
+     <span id=t_idt>resetEventOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>if</span> (<span id=t_idt>resumeDetectedIn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>oldResumeDetected</span> == <span id=t_cns>1'b0</span>)
+     <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>else</span> 
+     <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveSendpacket" alt="slaveSendpacket"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar21.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram21.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(844,1410,946,1513,Click21,Over21);
+FUB[1] = new Array(1383,1786,1485,1889,Click45,Over45);
+
+//----------------------------------------------------------------------------
+function Click21(){fubclick('./index21.htm');}
+function Over21(){window.status='Hierarchical State SP_SEND_PID';};
+function Click45(){fubclick('./index45.htm');}
+function Over45(){window.status='Hierarchical State SP_D0_D1';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveSendpacket.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveSendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram15.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram15.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram15.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller START" alt="slavecontroller START"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram15.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_SEND_PID.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_SEND_PID.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_D0_D1.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_D0_D1.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 45 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveSendpacket_SP_D0_D1.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveSendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram551.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram551.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram551.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller SETUP_OUT" alt="slavecontroller SETUP_OUT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram551.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index376.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index376.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index376.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar376.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram376.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index376.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller" alt="slavecontroller"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram580.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram580.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram580.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller IN" alt="slavecontroller IN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram580.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index551.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index551.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index551.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar551.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram551.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index551.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm	(revision 264)
@@ -0,0 +1,265 @@
+<html>
+<head>
+<title>slaveSendpacket.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveSendPacket</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:41 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>slaveSendPacket</span> (<span id=t_idt>PID</span>, <span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>SCTxPortData</span>, <span id=t_idt>SCTxPortGnt</span>, <span id=t_idt>SCTxPortRdy</span>, <span id=t_idt>SCTxPortReq</span>, <span id=t_idt>SCTxPortWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>fifoData</span>, <span id=t_idt>fifoEmpty</span>, <span id=t_idt>fifoReadEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>PID</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fifoReadEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketRdy</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>PID</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>next_SCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>, <span id=t_idt>next_SCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortReq</span>, <span id=t_idt>next_SCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortWEn</span>, <span id=t_idt>next_SCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>fifoReadEn</span>, <span id=t_idt>next_fifoReadEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>next_sendPacketRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>PIDNotPID</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: slvSndPkt</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SP1</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_WAIT_ENABLE</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP1_WAIT_GNT</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_SEND_PID_WAIT_RDY</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_SEND_PID_FIN</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIN_SP1</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_READ_FIFO</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_WAIT_READ_FIFO</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_FIFO_EMPTY</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_FIN</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_TERM_BYTE</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_NOT_DATA</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_CLR_WEN</span> <span id=t_cns>4'b1100</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_CLR_REN</span> <span id=t_cns>4'b1101</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_slvSndPkt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_slvSndPkt</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>PID</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>PIDNotPID</span> &lt;=  { (<span id=t_idt>PID</span> ^ <span id=t_cns>4'hf</span>), <span id=t_idt>PID</span> };
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: slvSndPkt</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>PIDNotPID</span> <span id=t_kwd>or</span> <span id=t_idt>fifoData</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>PID</span> <span id=t_kwd>or</span> <span id=t_idt>fifoEmpty</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>fifoReadEn</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_slvSndPkt</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvSndPkt_NextState</span>
+  <span id=t_idt>NextState_slvSndPkt</span> &lt;= <span id=t_idt>CurrState_slvSndPkt</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_idt>sendPacketRdy</span>;
+  <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_idt>SCTxPortReq</span>;
+  <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_idt>SCTxPortWEn</span>;
+  <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_idt>SCTxPortData</span>;
+  <span id=t_idt>next_SCTxPortCntl</span> &lt;= <span id=t_idt>SCTxPortCntl</span>;
+  <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_idt>fifoReadEn</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_slvSndPkt</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SP1</span>:
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_WAIT_ENABLE</span>;
+   `<span id=t_idt>SP_WAIT_ENABLE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketWEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP1_WAIT_GNT</span>;
+      <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP1_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_SEND_PID_WAIT_RDY</span>;
+   `<span id=t_idt>FIN_SP1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_WAIT_ENABLE</span>;
+     <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_NOT_DATA</span>:
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>FIN_SP1</span>;
+   `<span id=t_idt>SP_SEND_PID_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_SEND_PID_FIN</span>;
+      <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_idt>PIDNotPID</span>;
+      <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_START</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_SEND_PID_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>PID</span> == `<span id=t_idt>DATA0</span> || <span id=t_idt>PID</span> == `<span id=t_idt>DATA1</span>)  
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_FIFO_EMPTY</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_NOT_DATA</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_READ_FIFO</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_idt>fifoData</span>;
+     <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_CLR_WEN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_WAIT_READ_FIFO</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_CLR_REN</span>;
+      <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_FIFO_EMPTY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>fifoEmpty</span> == <span id=t_cns>1'b0</span>) 
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_WAIT_READ_FIFO</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_TERM_BYTE</span>;
+   `<span id=t_idt>SP_D0_D1_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>FIN_SP1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_TERM_BYTE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_FIN</span>;
+      <span id=t_com>//Last byte is not valid data,</span>
+      <span id=t_com>//but the 'TX_PACKET_STOP' flag is required</span>
+      <span id=t_com>//by the SIE state machine to detect end of data packet</span>
+      <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_CLR_WEN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_FIFO_EMPTY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_CLR_REN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_READ_FIFO</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvSndPkt_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_slvSndPkt</span> &lt;= `<span id=t_idt>START_SP1</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_slvSndPkt</span> &lt;= <span id=t_idt>NextState_slvSndPkt</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvSndPkt_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_idt>SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>fifoReadEn</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketRdy</span> &lt;= <span id=t_idt>next_sendPacketRdy</span>;
+   <span id=t_idt>SCTxPortReq</span> &lt;= <span id=t_idt>next_SCTxPortReq</span>;
+   <span id=t_idt>SCTxPortWEn</span> &lt;= <span id=t_idt>next_SCTxPortWEn</span>;
+   <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_idt>next_SCTxPortData</span>;
+   <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_idt>next_SCTxPortCntl</span>;
+   <span id=t_idt>fifoReadEn</span> &lt;= <span id=t_idt>next_fifoReadEn</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 21 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveSendpacket_SP_SEND_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveSendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index580.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index580.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index580.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar580.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram580.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index580.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_GET_TOKEN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_GET_TOKEN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_IN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_IN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram376.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram376.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram376.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller GET_TOKEN" alt="slavecontroller GET_TOKEN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/diagram376.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index15.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index15.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index15.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar15.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram15.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/index15.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(828,652,930,755,Click15,Over15);
+FUB[1] = new Array(449,1580,551,1683,Click551,Over551);
+FUB[2] = new Array(1339,1543,1441,1645,Click580,Over580);
+FUB[3] = new Array(949,1090,1051,1193,Click376,Over376);
+
+//----------------------------------------------------------------------------
+function Click15(){fubclick('./index15.htm');}
+function Over15(){window.status='Hierarchical State START';};
+function Click551(){fubclick('./index551.htm');}
+function Over551(){window.status='Hierarchical State SETUP_OUT';};
+function Click580(){fubclick('./index580.htm');}
+function Over580(){window.status='Hierarchical State IN';};
+function Click376(){fubclick('./index376.htm');}
+function Over376(){window.status='Hierarchical State GET_TOKEN';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar580.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar580.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar580.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 580 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller_IN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar580.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 15 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller_START.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/usbSlaveControl.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/usbSlaveControl.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/usbSlaveControl.v/index.htm	(revision 264)
@@ -0,0 +1,511 @@
+<html>
+<head>
+<title>usbSlaveControl.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbSlaveControl.v                                            ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:42 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>usbSlaveControl</span>(
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_com>//getPacket</span>
+  <span id=t_idt>RxByteStatus</span>, <span id=t_idt>RxData</span>, <span id=t_idt>RxDataValid</span>,
+  <span id=t_idt>SIERxTimeOut</span>, <span id=t_idt>RxFifoData</span>,
+  <span id=t_com>//speedCtrlMux</span>
+  <span id=t_idt>fullSpeedRate</span>, <span id=t_idt>fullSpeedPol</span>,
+  <span id=t_com>//SCTxPortArbiter</span>
+  <span id=t_idt>SCTxPortEn</span>, <span id=t_idt>SCTxPortRdy</span>,
+  <span id=t_idt>SCTxPortData</span>, <span id=t_idt>SCTxPortCtrl</span>,
+  <span id=t_com>//rxStatusMonitor</span>
+  <span id=t_idt>connectStateIn</span>, 
+  <span id=t_idt>resumeDetectedIn</span>,
+  <span id=t_com>//USBHostControlBI </span>
+  <span id=t_idt>busAddress</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>, 
+  <span id=t_idt>busWriteEn</span>,
+  <span id=t_idt>busStrobe_i</span>,
+  <span id=t_idt>SOFRxedIntOut</span>, 
+  <span id=t_idt>resetEventIntOut</span>, 
+  <span id=t_idt>resumeIntOut</span>, 
+  <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>NAKSentIntOut</span>,
+  <span id=t_idt>slaveControlSelect</span>,
+  <span id=t_com>//fifoMux</span>
+  <span id=t_idt>TxFifoEP0REn</span>,
+  <span id=t_idt>TxFifoEP1REn</span>,
+  <span id=t_idt>TxFifoEP2REn</span>,
+  <span id=t_idt>TxFifoEP3REn</span>,
+  <span id=t_idt>TxFifoEP0Data</span>,
+  <span id=t_idt>TxFifoEP1Data</span>,
+  <span id=t_idt>TxFifoEP2Data</span>,
+  <span id=t_idt>TxFifoEP3Data</span>,
+  <span id=t_idt>TxFifoEP0Empty</span>,
+  <span id=t_idt>TxFifoEP1Empty</span>,
+  <span id=t_idt>TxFifoEP2Empty</span>,
+  <span id=t_idt>TxFifoEP3Empty</span>,
+  <span id=t_idt>RxFifoEP0WEn</span>,
+  <span id=t_idt>RxFifoEP1WEn</span>,
+  <span id=t_idt>RxFifoEP2WEn</span>,
+  <span id=t_idt>RxFifoEP3WEn</span>,
+  <span id=t_idt>RxFifoEP0Full</span>,
+  <span id=t_idt>RxFifoEP1Full</span>,
+  <span id=t_idt>RxFifoEP2Full</span>,
+  <span id=t_idt>RxFifoEP3Full</span>
+   );
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>, <span id=t_idt>rst</span>;
+<span id=t_com>//getPacket</span>
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteStatus</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxData</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxDataValid</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxFifoData</span>;
+<span id=t_com>//speedCtrlMux</span>
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>;
+<span id=t_com>//HCTxPortArbiter</span>
+<span id=t_kwd>output</span> <span id=t_idt>SCTxPortEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCtrl</span>;
+<span id=t_com>//rxStatusMonitor</span>
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_com>//USBHostControlBI </span>
+<span id=t_kwd>input</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busWriteEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFRxedIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>resetEventIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>NAKSentIntOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>slaveControlSelect</span>;
+<span id=t_com>//fifoMux</span>
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP3Empty</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP3Full</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteStatus</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxDataValid</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxFifoData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPol</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCtrl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busWriteEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFRxedIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>resetEventIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>NAKSentIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3Full</span>;
+
+<span id=t_com>//internal wiring</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketWEn</span>;   
+<span id=t_kwd>wire</span> <span id=t_idt>SCTxPortArbRdyOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDone</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directLineState</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directLineCtrlEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntFromRxStatusMon</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>USBTgtAddress</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP0Rdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP1Rdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP2Rdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP3Rdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SCGlobalEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>ACKRxed</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>CRCError</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RXOverflow</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RXTimeOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>bitStuffError</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>dataSequence</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>stallSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>NAKSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFRxed</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endPControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transTypeNAK</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>getPacketREn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>slaveControllerPIDOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControllerReadyIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControllerWEnOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoRE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoWE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resetEventFromRxStatusMon</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEPRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>endPMuxErrorsWEn</span>;
+
+<span id=t_idt>USBSlaveControlBI</span> <span id=t_idt>u_USBSlaveControlBI</span>
+  (.<span id=t_idt>address</span>(<span id=t_idt>busAddress</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>busDataOut</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>busWriteEn</span>),
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>busStrobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>SOFRxedIntOut</span>(<span id=t_idt>SOFRxedIntOut</span>), 
+  .<span id=t_idt>resetEventIntOut</span>(<span id=t_idt>resetEventIntOut</span>), 
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>resumeIntOut</span>), 
+  .<span id=t_idt>transDoneIntOut</span>(<span id=t_idt>transDoneIntOut</span>),
+  .<span id=t_idt>NAKSentIntOut</span>(<span id=t_idt>NAKSentIntOut</span>),
+  .<span id=t_idt>endP0TransTypeReg</span>(<span id=t_idt>endP0TransTypeReg</span>), 
+  .<span id=t_idt>endP0NAKTransTypeReg</span>(<span id=t_idt>endP0NAKTransTypeReg</span>),
+  .<span id=t_idt>endP1TransTypeReg</span>(<span id=t_idt>endP1TransTypeReg</span>), 
+  .<span id=t_idt>endP1NAKTransTypeReg</span>(<span id=t_idt>endP1NAKTransTypeReg</span>),
+  .<span id=t_idt>endP2TransTypeReg</span>(<span id=t_idt>endP2TransTypeReg</span>), 
+  .<span id=t_idt>endP2NAKTransTypeReg</span>(<span id=t_idt>endP2NAKTransTypeReg</span>),
+  .<span id=t_idt>endP3TransTypeReg</span>(<span id=t_idt>endP3TransTypeReg</span>), 
+  .<span id=t_idt>endP3NAKTransTypeReg</span>(<span id=t_idt>endP3NAKTransTypeReg</span>),
+  .<span id=t_idt>endP0ControlReg</span>(<span id=t_idt>endP0ControlReg</span>),
+  .<span id=t_idt>endP1ControlReg</span>(<span id=t_idt>endP1ControlReg</span>),
+  .<span id=t_idt>endP2ControlReg</span>(<span id=t_idt>endP2ControlReg</span>),
+  .<span id=t_idt>endP3ControlReg</span>(<span id=t_idt>endP3ControlReg</span>),
+  .<span id=t_idt>EP0StatusReg</span>(<span id=t_idt>endP0StatusReg</span>),
+  .<span id=t_idt>EP1StatusReg</span>(<span id=t_idt>endP1StatusReg</span>),
+  .<span id=t_idt>EP2StatusReg</span>(<span id=t_idt>endP2StatusReg</span>),
+  .<span id=t_idt>EP3StatusReg</span>(<span id=t_idt>endP3StatusReg</span>),
+  .<span id=t_idt>SCAddrReg</span>(<span id=t_idt>USBTgtAddress</span>), 
+  .<span id=t_idt>frameNum</span>(<span id=t_idt>frameNum</span>),
+  .<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectStateOut</span>),
+  .<span id=t_idt>SOFRxedIn</span>(<span id=t_idt>SOFRxed</span>), 
+  .<span id=t_idt>resetEventIn</span>(<span id=t_idt>resetEventFromRxStatusMon</span>), 
+  .<span id=t_idt>resumeIntIn</span>(<span id=t_idt>resumeIntFromRxStatusMon</span>), 
+  .<span id=t_idt>transDoneIn</span>(<span id=t_idt>transDone</span>),
+  .<span id=t_idt>NAKSentIn</span>(<span id=t_idt>NAKSent</span>),
+  .<span id=t_idt>slaveControlSelect</span>(<span id=t_idt>slaveControlSelect</span>),
+  .<span id=t_idt>clrEP0Ready</span>(<span id=t_idt>clrEP0Rdy</span>), 
+  .<span id=t_idt>clrEP1Ready</span>(<span id=t_idt>clrEP1Rdy</span>), 
+  .<span id=t_idt>clrEP2Ready</span>(<span id=t_idt>clrEP2Rdy</span>), 
+  .<span id=t_idt>clrEP3Ready</span>(<span id=t_idt>clrEP3Rdy</span>),
+  .<span id=t_idt>TxLineState</span>(<span id=t_idt>directLineState</span>),
+  .<span id=t_idt>LineDirectControlEn</span>(<span id=t_idt>directLineCtrlEn</span>),
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>fullSpeedPol</span>), 
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedRate</span>),
+  .<span id=t_idt>SCGlobalEn</span>(<span id=t_idt>SCGlobalEn</span>)
+  );
+
+<span id=t_idt>slavecontroller</span> <span id=t_idt>u_slavecontroller</span>
+  (.<span id=t_idt>CRCError</span>(<span id=t_idt>CRCError</span>), 
+  .<span id=t_idt>NAKSent</span>(<span id=t_idt>NAKSent</span>), 
+  .<span id=t_idt>RxByte</span>(<span id=t_idt>RxData</span>), 
+  .<span id=t_idt>RxDataWEn</span>(<span id=t_idt>RxDataValid</span>), 
+  .<span id=t_idt>RxOverflow</span>(<span id=t_idt>RXOverflow</span>), 
+  .<span id=t_idt>RxStatus</span>(<span id=t_idt>RxByteStatus</span>), 
+  .<span id=t_idt>RxTimeOut</span>(<span id=t_idt>RXTimeOut</span>), 
+  .<span id=t_idt>SCGlobalEn</span>(<span id=t_idt>SCGlobalEn</span>), 
+  .<span id=t_idt>SOFRxed</span>(<span id=t_idt>SOFRxed</span>), 
+  .<span id=t_idt>USBEndPControlReg</span>(<span id=t_idt>endPControlReg</span>), 
+  .<span id=t_idt>USBEndPNakTransTypeReg</span>(<span id=t_idt>transTypeNAK</span>), 
+  .<span id=t_idt>USBEndPTransTypeReg</span>(<span id=t_idt>transType</span>), 
+  .<span id=t_idt>USBEndP</span>(<span id=t_idt>currEndP</span>), 
+  .<span id=t_idt>USBTgtAddress</span>(<span id=t_idt>USBTgtAddress</span>),
+  .<span id=t_idt>bitStuffError</span>(<span id=t_idt>bitStuffError</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>clrEPRdy</span>(<span id=t_idt>clrEPRdy</span>), 
+  .<span id=t_idt>endPMuxErrorsWEn</span>(<span id=t_idt>endPMuxErrorsWEn</span>), 
+  .<span id=t_idt>frameNum</span>(<span id=t_idt>frameNum</span>), 
+  .<span id=t_idt>getPacketREn</span>(<span id=t_idt>getPacketREn</span>), 
+  .<span id=t_idt>getPacketRdy</span>(<span id=t_idt>getPacketRdy</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>sendPacketPID</span>(<span id=t_idt>slaveControllerPIDOut</span>), 
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>slaveControllerReadyIn</span>), 
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>slaveControllerWEnOut</span>), 
+  .<span id=t_idt>stallSent</span>(<span id=t_idt>stallSent</span>), 
+  .<span id=t_idt>transDone</span>(<span id=t_idt>transDone</span>) 
+    );
+
+
+<span id=t_idt>endpMux</span> <span id=t_idt>u_endpMux</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>currEndP</span>(<span id=t_idt>currEndP</span>),
+  .<span id=t_idt>NAKSent</span>(<span id=t_idt>NAKSent</span>),
+  .<span id=t_idt>stallSent</span>(<span id=t_idt>stallSent</span>),
+  .<span id=t_idt>CRCError</span>(<span id=t_idt>CRCError</span>),
+  .<span id=t_idt>bitStuffError</span>(<span id=t_idt>bitStuffError</span>),
+  .<span id=t_idt>RxOverflow</span>(<span id=t_idt>RXOverflow</span>),
+  .<span id=t_idt>RxTimeOut</span>(<span id=t_idt>RXTimeOut</span>),
+  .<span id=t_idt>dataSequence</span>(<span id=t_idt>dataSequence</span>),
+  .<span id=t_idt>ACKRxed</span>(<span id=t_idt>ACKRxed</span>),
+  .<span id=t_idt>transType</span>(<span id=t_idt>transType</span>),
+  .<span id=t_idt>transTypeNAK</span>(<span id=t_idt>transTypeNAK</span>),
+  .<span id=t_idt>endPControlReg</span>(<span id=t_idt>endPControlReg</span>),
+  .<span id=t_idt>clrEPRdy</span>(<span id=t_idt>clrEPRdy</span>),
+  .<span id=t_idt>endPMuxErrorsWEn</span>(<span id=t_idt>endPMuxErrorsWEn</span>),
+  .<span id=t_idt>endP0ControlReg</span>(<span id=t_idt>endP0ControlReg</span>),
+  .<span id=t_idt>endP1ControlReg</span>(<span id=t_idt>endP1ControlReg</span>),
+  .<span id=t_idt>endP2ControlReg</span>(<span id=t_idt>endP2ControlReg</span>),
+  .<span id=t_idt>endP3ControlReg</span>(<span id=t_idt>endP3ControlReg</span>),
+  .<span id=t_idt>endP0StatusReg</span>(<span id=t_idt>endP0StatusReg</span>),
+  .<span id=t_idt>endP1StatusReg</span>(<span id=t_idt>endP1StatusReg</span>),
+  .<span id=t_idt>endP2StatusReg</span>(<span id=t_idt>endP2StatusReg</span>),
+  .<span id=t_idt>endP3StatusReg</span>(<span id=t_idt>endP3StatusReg</span>),
+  .<span id=t_idt>endP0TransTypeReg</span>(<span id=t_idt>endP0TransTypeReg</span>),
+  .<span id=t_idt>endP1TransTypeReg</span>(<span id=t_idt>endP1TransTypeReg</span>),
+  .<span id=t_idt>endP2TransTypeReg</span>(<span id=t_idt>endP2TransTypeReg</span>),
+  .<span id=t_idt>endP3TransTypeReg</span>(<span id=t_idt>endP3TransTypeReg</span>),
+  .<span id=t_idt>endP0NAKTransTypeReg</span>(<span id=t_idt>endP0NAKTransTypeReg</span>),
+  .<span id=t_idt>endP1NAKTransTypeReg</span>(<span id=t_idt>endP1NAKTransTypeReg</span>),
+  .<span id=t_idt>endP2NAKTransTypeReg</span>(<span id=t_idt>endP2NAKTransTypeReg</span>),
+  .<span id=t_idt>endP3NAKTransTypeReg</span>(<span id=t_idt>endP3NAKTransTypeReg</span>),
+  .<span id=t_idt>clrEP0Rdy</span>(<span id=t_idt>clrEP0Rdy</span>),
+  .<span id=t_idt>clrEP1Rdy</span>(<span id=t_idt>clrEP1Rdy</span>),
+  .<span id=t_idt>clrEP2Rdy</span>(<span id=t_idt>clrEP2Rdy</span>),
+  .<span id=t_idt>clrEP3Rdy</span>(<span id=t_idt>clrEP3Rdy</span>)
+    );
+
+<span id=t_idt>slaveSendPacket</span> <span id=t_idt>u_slaveSendPacket</span>
+  (.<span id=t_idt>PID</span>(<span id=t_idt>slaveControllerPIDOut</span>), 
+  .<span id=t_idt>SCTxPortCntl</span>(<span id=t_idt>sendPacketCntl</span>),
+  .<span id=t_idt>SCTxPortData</span>(<span id=t_idt>sendPacketData</span>),
+  .<span id=t_idt>SCTxPortGnt</span>(<span id=t_idt>sendPacketGnt</span>),
+  .<span id=t_idt>SCTxPortRdy</span>(<span id=t_idt>SCTxPortArbRdyOut</span>),
+  .<span id=t_idt>SCTxPortReq</span>(<span id=t_idt>sendPacketReq</span>),
+  .<span id=t_idt>SCTxPortWEn</span>(<span id=t_idt>sendPacketWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>fifoData</span>(<span id=t_idt>TxFifoData</span>),
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEmpty</span>),
+  .<span id=t_idt>fifoReadEn</span>(<span id=t_idt>TxFifoRE</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>slaveControllerReadyIn</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>slaveControllerWEnOut</span>) );
+
+<span id=t_idt>slaveDirectControl</span> <span id=t_idt>u_slaveDirectControl</span>
+  (.<span id=t_idt>SCTxPortCntl</span>(<span id=t_idt>directCntlCntl</span>),
+  .<span id=t_idt>SCTxPortData</span>(<span id=t_idt>directCntlData</span>),
+  .<span id=t_idt>SCTxPortGnt</span>(<span id=t_idt>directCntlGnt</span>),
+  .<span id=t_idt>SCTxPortRdy</span>(<span id=t_idt>SCTxPortArbRdyOut</span>),
+  .<span id=t_idt>SCTxPortReq</span>(<span id=t_idt>directCntlReq</span>),
+  .<span id=t_idt>SCTxPortWEn</span>(<span id=t_idt>directCntlWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>directControlEn</span>(<span id=t_idt>directLineCtrlEn</span>),
+  .<span id=t_idt>directControlLineState</span>(<span id=t_idt>directLineState</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>SCTxPortArbiter</span> <span id=t_idt>u_SCTxPortArbiter</span>
+  (.<span id=t_idt>SCTxPortCntl</span>(<span id=t_idt>SCTxPortCtrl</span>),
+  .<span id=t_idt>SCTxPortData</span>(<span id=t_idt>SCTxPortData</span>),
+  .<span id=t_idt>SCTxPortRdyIn</span>(<span id=t_idt>SCTxPortRdy</span>),
+  .<span id=t_idt>SCTxPortRdyOut</span>(<span id=t_idt>SCTxPortArbRdyOut</span>),
+  .<span id=t_idt>SCTxPortWEnable</span>(<span id=t_idt>SCTxPortEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>directCntlCntl</span>(<span id=t_idt>directCntlCntl</span>),
+  .<span id=t_idt>directCntlData</span>(<span id=t_idt>directCntlData</span>),
+  .<span id=t_idt>directCntlGnt</span>(<span id=t_idt>directCntlGnt</span>),
+  .<span id=t_idt>directCntlReq</span>(<span id=t_idt>directCntlReq</span>),
+  .<span id=t_idt>directCntlWEn</span>(<span id=t_idt>directCntlWEn</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketCntl</span>(<span id=t_idt>sendPacketCntl</span>),
+  .<span id=t_idt>sendPacketData</span>(<span id=t_idt>sendPacketData</span>),
+  .<span id=t_idt>sendPacketGnt</span>(<span id=t_idt>sendPacketGnt</span>),
+  .<span id=t_idt>sendPacketReq</span>(<span id=t_idt>sendPacketReq</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>sendPacketWEn</span>) );   
+
+
+<span id=t_idt>slaveGetPacket</span> <span id=t_idt>u_slaveGetPacket</span>
+  (.<span id=t_idt>ACKRxed</span>(<span id=t_idt>ACKRxed</span>), 
+  .<span id=t_idt>CRCError</span>(<span id=t_idt>CRCError</span>), 
+  .<span id=t_idt>RXDataIn</span>(<span id=t_idt>RxData</span>),
+  .<span id=t_idt>RXDataValid</span>(<span id=t_idt>RxDataValid</span>),
+  .<span id=t_idt>RXFifoData</span>(<span id=t_idt>RxFifoData</span>),
+  .<span id=t_idt>RXFifoFull</span>(<span id=t_idt>RxFifoFull</span>),
+  .<span id=t_idt>RXFifoWEn</span>(<span id=t_idt>RxFifoWE</span>),
+  .<span id=t_idt>RXPacketRdy</span>(<span id=t_idt>getPacketRdy</span>),
+  .<span id=t_idt>RXStreamStatusIn</span>(<span id=t_idt>RxByteStatus</span>),
+  .<span id=t_idt>RxPID</span>(<span id=t_idt>RxPID</span>),
+  .<span id=t_idt>SIERxTimeOut</span>(<span id=t_idt>SIERxTimeOut</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>RXOverflow</span>(<span id=t_idt>RXOverflow</span>), 
+  .<span id=t_idt>RXTimeOut</span>(<span id=t_idt>RXTimeOut</span>), 
+  .<span id=t_idt>bitStuffError</span>(<span id=t_idt>bitStuffError</span>), 
+  .<span id=t_idt>dataSequence</span>(<span id=t_idt>dataSequence</span>), 
+  .<span id=t_idt>getPacketEn</span>(<span id=t_idt>getPacketREn</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>slaveRxStatusMonitor</span>  <span id=t_idt>u_slaveRxStatusMonitor</span>
+  (.<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectStateIn</span>),
+  .<span id=t_idt>connectStateOut</span>(<span id=t_idt>connectStateOut</span>),
+  .<span id=t_idt>resumeDetectedIn</span>(<span id=t_idt>resumeDetectedIn</span>),
+  .<span id=t_idt>resetEventOut</span>(<span id=t_idt>resetEventFromRxStatusMon</span>),
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>resumeIntFromRxStatusMon</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>)  );    
+  
+<span id=t_idt>fifoMux</span> <span id=t_idt>u_fifoMux</span> (
+  .<span id=t_idt>currEndP</span>(<span id=t_idt>currEndP</span>),
+  <span id=t_com>//TxFifo</span>
+  .<span id=t_idt>TxFifoREn</span>(<span id=t_idt>TxFifoRE</span>),
+  .<span id=t_idt>TxFifoEP0REn</span>(<span id=t_idt>TxFifoEP0REn</span>),
+  .<span id=t_idt>TxFifoEP1REn</span>(<span id=t_idt>TxFifoEP1REn</span>),
+  .<span id=t_idt>TxFifoEP2REn</span>(<span id=t_idt>TxFifoEP2REn</span>),
+  .<span id=t_idt>TxFifoEP3REn</span>(<span id=t_idt>TxFifoEP3REn</span>),
+  .<span id=t_idt>TxFifoData</span>(<span id=t_idt>TxFifoData</span>),
+  .<span id=t_idt>TxFifoEP0Data</span>(<span id=t_idt>TxFifoEP0Data</span>),
+  .<span id=t_idt>TxFifoEP1Data</span>(<span id=t_idt>TxFifoEP1Data</span>),
+  .<span id=t_idt>TxFifoEP2Data</span>(<span id=t_idt>TxFifoEP2Data</span>),
+  .<span id=t_idt>TxFifoEP3Data</span>(<span id=t_idt>TxFifoEP3Data</span>),
+  .<span id=t_idt>TxFifoEmpty</span>(<span id=t_idt>TxFifoEmpty</span>),
+  .<span id=t_idt>TxFifoEP0Empty</span>(<span id=t_idt>TxFifoEP0Empty</span>),
+  .<span id=t_idt>TxFifoEP1Empty</span>(<span id=t_idt>TxFifoEP1Empty</span>),
+  .<span id=t_idt>TxFifoEP2Empty</span>(<span id=t_idt>TxFifoEP2Empty</span>),
+  .<span id=t_idt>TxFifoEP3Empty</span>(<span id=t_idt>TxFifoEP3Empty</span>),
+  <span id=t_com>//RxFifo</span>
+  .<span id=t_idt>RxFifoWEn</span>(<span id=t_idt>RxFifoWE</span>),
+  .<span id=t_idt>RxFifoEP0WEn</span>(<span id=t_idt>RxFifoEP0WEn</span>),
+  .<span id=t_idt>RxFifoEP1WEn</span>(<span id=t_idt>RxFifoEP1WEn</span>),
+  .<span id=t_idt>RxFifoEP2WEn</span>(<span id=t_idt>RxFifoEP2WEn</span>),
+  .<span id=t_idt>RxFifoEP3WEn</span>(<span id=t_idt>RxFifoEP3WEn</span>),
+  .<span id=t_idt>RxFifoFull</span>(<span id=t_idt>RxFifoFull</span>),
+  .<span id=t_idt>RxFifoEP0Full</span>(<span id=t_idt>RxFifoEP0Full</span>),
+  .<span id=t_idt>RxFifoEP1Full</span>(<span id=t_idt>RxFifoEP1Full</span>),
+  .<span id=t_idt>RxFifoEP2Full</span>(<span id=t_idt>RxFifoEP2Full</span>),
+  .<span id=t_idt>RxFifoEP3Full</span>(<span id=t_idt>RxFifoEP3Full</span>)
+    );
+
+<span id=t_kwd>endmodule</span>
+
+  
+  
+
+
+
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/usbSlaveControl.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/fsmtools.js
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/fsmtools.js	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/fsmtools.js	(revision 264)
@@ -0,0 +1,461 @@
+
+var zoo = 100;
+var pzoo = 100;
+var zoom_inc = 2; //or 50
+var SCHEM = "DIAGRAM"
+var ViewX=w;
+var ViewY=h;
+var DEBUG_MODE = 1;
+//----------------------------------------------------------------------------
+IRoot = RootProject + "images/fsm/";
+OV = "over.gif";
+OD = "down.gif";
+//----------------------------------------------------------------------------
+function CodeView(){
+window.parent.location = SchemCode;
+}
+//----------------------------------------------------------------------------
+function GotoPage(){
+	if(PageNext==-1){
+		alert("no page");
+		return;
+	}
+window.parent.location = "./content"+PageNext+".html"
+}
+//----------------------------------------------------------------------------
+function fubclick(lnk){
+	if(lnk!="")
+		window.parent.location = lnk;
+}
+//----------------------------------------------------------------------------
+function DUMP() { 
+	var dump_msg;
+	dump_msg= "w.........."+w+"\n";
+	dump_msg+="h.........."+h+"\n";
+	dump_msg+="zoo........"+zoo+"\n";
+	dump_msg+="pzoo......."+pzoo+"\n";
+	dump_msg+="zoo_inc...."+zoom_inc+"\n";
+	dump_msg+="schem......"+SCHEM+"\n";
+	dump_msg+="viewx......"+ViewX+"\n";
+	dump_msg+="viewy......"+ViewY+"\n";
+	dump_msg+="pagex......"+PageX+"\n";
+	dump_msg+="pagey......"+PageY+"\n";
+	dump_msg+="IE........."+ie+"\n";
+	dump_msg+="NN........."+nn+"\n";
+	alert(dump_msg);
+}
+function alertd(msg) {
+	if(DEBUG_MODE==1)
+		alert(msg)
+}
+//----------------------------------------------------------------------------
+var MyImage;
+var MyDoc;
+var MyWindow;
+//----------------------------------------------------------------------------
+function Init(){
+MyImage = window.parent.frames["xschem"].window.document.images[SCHEM];
+MyImage.src = SchemImage.src;
+MyDoc = window.parent.frames["xschem"].window.document;
+MyWindow =  window.parent.frames["xschem"].window;
+//zoomfit();
+//�������� - � ��, �᫨ ��࠭�� �� ����㦥��?
+//alert("init")
+}
+//----------------------------------------------------------------------------
+function ZRefresh(){
+	ViewX = w*zoo/100;
+	ViewY = h*zoo/100;
+
+	if(ViewX<=0 || ViewY<=0 || ViewX==NaN || ViewY==NaN){
+		alertd("Z-Error: " + ViewX + "##" + ViewY + "##" + zoo + "##" + pzoo);
+		DUMP();
+		ViewX=w;
+		ViewX=h;
+		zoo=100;
+		pzoo=100;		
+	}
+
+	MyImage.width  = ViewX;
+	MyImage.height = ViewY;
+
+	if(!ie&&!nn) //NN6
+		MyImage.src = SchemImage.src;
+	if(ie){
+		window.top.resizeBy(1, 1);  
+		window.top.resizeBy(-1, -1);
+	}
+}
+function zoomin(){
+	pzoo=zoo;
+	zoo*=zoom_inc;
+	ZRefresh();
+}
+function zoomout(){
+	if(zoo<=zoom_inc) return;
+	pzoo=zoo;
+	zoo/=zoom_inc;
+	ZRefresh();
+}
+function zoomfit(){	
+	pw=w;ph=h;
+	var cw;var ch;
+	if(ie || nn){
+		if(!MyDoc.body.clientWidth) {
+
+			if (self.screen) { // for NN4 and IE4 
+				cw = screen.width/1.5 ; // What can I do for Opera
+				ch = screen.height/1.5; // What can I do for Opera
+			} else if (self.java) { // for NN3 with enabled Java 
+				var jkit = java.awt.Toolkit.getDefaultToolkit(); 
+				var scrsize = jkit.getScreenSize(); 
+				cw = scrsize.width; 
+				ch = scrsize.height; 
+			} else
+				{
+					cw = w;
+					ch = h
+				} 
+		} 
+
+		else //FOR TRUE IE!!! with clientWidth
+		{	
+			cw=MyDoc.body.clientWidth;
+			ch=MyDoc.body.clientHeight;
+
+			if (Math.round(ViewY)>ch) ch=ch+16;
+			if (Math.round(ViewX)>cw) cw=cw+16;
+			
+		}
+	} else { //for TRUE NN :-) cheak It!!!
+		//alertd("nn"); //NN6 use it
+		
+		cw=MyWindow.innerWidth*95/100;
+		ch=MyWindow.innerHeight*95/100;
+		//alertd("cw"+cw);
+		//alertd(""ch);
+	}
+
+	fw=100*(cw/pw);
+	fh=100*(ch/ph);
+	xzoo=fh;
+	if(fw<fh)
+		xzoo=fw;
+	if(xzoo==zoo)
+		return;
+	pzoo=zoo;
+	zoo=xzoo;
+	ZRefresh();
+}
+function zoomfull(){
+	pzoo=zoo;
+	zoo=100;
+	ZRefresh();
+}
+function zoomprev(){
+	tmp=zoo;
+	zoo=pzoo;
+	pzoo=tmp;
+	ZRefresh();
+}
+//----------------------------------------------------------------------------
+// Buttons of ToolBar
+//----------------------------------------------------------------------------
+BT_TITL = 0
+BT_ZMIN = 1
+BT_ZOUT = 2
+BT_ZFIT = 3
+BT_FULL = 4
+BT_PREV = 5
+BT_CODE = 6
+BT_PAGE = 7
+BT_PMOD = 8
+BT_ZMOD = 9
+BT_SMOD =10
+BT_OBJV =11
+BT_POPP =12 
+BT_PRNT =13
+BT_NEWW =14
+BT_SYSB =15
+//----------------------------------------------------------------------------
+NRM = 0;
+OVR = 1;
+DWN = 2;
+MES = 3;
+//----------------------------------------------------------------------------
+BT_NUMBER = 16;
+//----------------------------------------------------------------------------
+IMRES = new Array()//0..15 images is here
+Present = new Array(1,1,1,0,1, 1,0,0,0,0, 0,0,0,0,1, 1)//{1/0} boolean of visibility
+//----------------------------------------------------------------------------
+function mClick(i){
+	switch(i)
+	{
+		case BT_TITL: return;
+		case BT_ZMIN: zoomin();return;
+		case BT_ZOUT: zoomout();return;
+		case BT_ZFIT: zoomfit();return;
+		case BT_FULL: zoomfull();return;
+		case BT_PREV: zoomprev();return;
+		case BT_CODE: CodeView();return;
+		case BT_PAGE: GotoPage();return;
+		case BT_PMOD: Grosser(window.top);//Grosser();
+						window.top.resizeBy(1, 1);window.resizeBy(-1, -1); //!!!
+					  return;
+		case BT_ZMOD: return;
+		case BT_SMOD: view_source();return;
+		case BT_OBJV: DUMP();return;
+		case BT_SYSB: window.parent.close();void(0);
+					  return;
+		case BT_NEWW: fullScreen2(window.parent.location);
+						//window.parent.frames["xschem"].window.document.images[SCHEM].src = SchemImage.src;
+						return;
+		case BT_PRNT: printit();return;
+		case BT_POPP: alert(":-(");return;
+	}
+}
+//----------------------------------------------------------------------------
+function mOver(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][OVR].src;
+	SetStatus(IMRES[i][MES]);
+}
+//----------------------------------------------------------------------------
+function mOut(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][NRM].src;
+	SetStatus("");
+}
+//----------------------------------------------------------------------------
+function mDown(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][DWN].src;
+	SetStatus(IMRES[i][MES]);
+}
+//----------------------------------------------------------------------------
+function mUp(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][OVR].src;
+}
+//----------------------------------------------------------------------------
+function GetBod(i)
+	{
+	switch(i)
+	{	case BT_TITL: return "bar"
+		case BT_ZMIN: return "zoomin"
+		case BT_ZOUT: return "zoomout"
+		case BT_ZFIT: return "fit"
+		case BT_FULL: return "full"
+		case BT_CODE: return "code"
+		case BT_PREV: return "prev"
+		case BT_PAGE: return "goto"
+		case BT_PMOD: return "panmode"
+		case BT_ZMOD: return "zoommode"
+		case BT_SMOD: return "selectmode"
+		case BT_OBJV: return "tbl"
+		case BT_SYSB: return "frame"
+		case BT_NEWW: return "newwindow"
+		case BT_PRNT: return "print"
+		case BT_POPP: return "pop"
+	}
+	return "blank"
+}
+//----------------------------------------------------------------------------
+function GetFile(i, mode)
+	{
+	var bod = GetBod(i)
+	var end; 
+	switch(mode)
+	{	case NRM: end=".gif";break;
+		case OVR: end=OV;break;
+		case DWN: end=OD;
+	}
+	return IRoot + bod + end; 
+}
+//----------------------------------------------------------------------------
+function GetIMessage(i){
+	switch(i)
+	{
+		case BT_ZMIN: return "Zooms in view"
+		case BT_ZOUT: return "Zooms out view"
+		case BT_ZFIT: return "Zooms to fit"
+		case BT_FULL: return "Displays full page"
+		case BT_CODE: return "View generated code"
+		case BT_PREV: return "Displays previously visible area"
+		case BT_PAGE: return "Go to page"
+		case BT_PMOD: return "Enter panning mode"
+		case BT_ZMOD: return "Enter zoom mode"
+		case BT_SMOD: return "Enter select mode"
+		case BT_OBJV: return "Show Objects Window"
+		case BT_NEWW: return "Open in new window"
+		case BT_SYSB: return "Close newly opened window"
+		case BT_PRNT: return "Print"
+		case BT_POPP: return "Enters an upper hierarchical level"
+	}
+	return ""
+}
+//----------------------------------------------------------------------------
+for(i=0;i<BT_NUMBER;i++){
+	IMRES[i] = new Array(new Image(),new Image(),new Image(),"");
+}
+//----------------------------------------------------------------------------
+for(i=0;i<BT_NUMBER;i++){
+	IMRES[i][NRM].src = GetFile(i,NRM);
+	IMRES[i][OVR].src = GetFile(i,OVR);
+	IMRES[i][DWN].src = GetFile(i,DWN);
+	IMRES[i][MES]     = GetIMessage(i);
+//	IMRES[i][HNT]     = GetIHint(i);
+}
+//----------------------------------------------------------------------------
+function GetToolBar(){
+	var tools;
+	var open = '<table align="left" border="0" cellspacing="0" cellpadding="0" valign="center" align="center"> <tr bgcolor="silver" background="silver" bordercolordark="silver" >';
+	var close = '</tr></table>';
+
+	var std0 = '<td ><img hspace="0" vspace="0" border="0" align="absmiddle" ';
+	var std1= 'width=24 height=22 ';
+	var std2 = '></td>';
+
+	tools = open;
+	for(i=0;i<BT_NUMBER;i++){
+		if(Present[i]){
+			tools+=std0;
+			if(i!=BT_SYSB && i!=BT_TITL)
+				tools+=std1;
+			//tools+='src='+ GetINorm(i) + ' ';
+			tools+='src="'+ IMRES[i][NRM].src + '" ';
+			tools+=	'onClick="mClick('    + i + ')" ';
+			tools+=	'onMouseDown="mDown(' + i + ')" ';
+			tools+=	'onMouseUp="mUp(' + i + ')" ';
+			tools+=	'onMouseOver="mOver(' + i + ')" ';
+			tools+=	'onMouseOut="mOut('   + i + ')" ';	//	tools+='name="btn_' + i +'" '
+			tools+=	'name="btn_' + i +'" ';
+			tools+= 'alt="'+GetIMessage(i)+'" ';
+			tools+=std2;								
+		}
+	}
+	tools += close;
+
+	return tools;
+}
+//----------------------------------------------------------------------------
+var NIL = -1;
+//----------------------------------------------------------------------------
+function InRect(x,y,left,top,right,bottom) {
+	if(x>=left && x<=right && y>=top  && y<=bottom)
+		return 1;
+	return 0;	
+}
+//----------------------------------------------------------------------------
+function GetSender(x,y) {
+	for(i=0;i<FUBSNUMBER;i++) {
+		var left  = FUB[i][0];
+		var top   = FUB[i][1];
+		var right = FUB[i][2];
+		var bottom= FUB[i][3];
+
+	factor = PageX / ViewX;
+
+	xx = x*factor;
+	yy = y*factor;
+
+		if(InRect(xx,yy,left,top,right,bottom))
+			return i;
+	}
+	return NIL;
+}
+//----------------------------------------------------------------------------
+function Mapper(MouseX,MouseY) {
+	var SENDER = GetSender(MouseX,MouseY);
+	if(SENDER != NIL){
+		FUB[SENDER][4]();		
+	}
+}
+//----------------------------------------------------------------------------
+function MapperOver(MouseX,MouseY) {
+	var SENDER = GetSender(MouseX,MouseY);
+	if(SENDER != NIL){
+		FUB[SENDER][5]();
+		SetCursor("hand");
+	}
+	else {
+		SetStatus("");
+		SetCursor("default");
+	}
+	
+}
+//----------------------------------------------------------------------------
+function SetStatus(status){
+	if(window.top.status!=status){
+		window.top.status=status;
+		}
+}
+//----------------------------------------------------------------------------
+function SetCursor(cursor){
+	if(ie){
+		if(MyImage.style.cursor!=cursor)
+			MyImage.style.cursor=cursor;
+	} else {
+		; 
+	}
+}
+//----------------------------------------------------------------------------
+function Grosser(Who) { //in Opera - MDI - some bugs :-( but Ok . IE - nok. NN6 - ok
+	//window.moveTo(0,0);
+//	window.resizeTo(screen.availWidth,screen.availHeight);
+	Who.moveTo(0,0);
+	Who.resizeTo(screen.availWidth,screen.availHeight);
+}
+//----------------------------------------------------------------------------
+function fullScreen2(theURL) {
+	window.open(theURL, '', 'fullscreen=yes,scrollbars=yes,status=yes,resizable=yes,location=yes');
+}
+//----------------------------------------------------------------------------
+function boom(n){
+	if (window.top.moveBy)
+	{
+		for (i = 10; i > 0; i--){
+			for (j = n; j > 0; j--){
+				window.top.moveBy(0,i);
+				window.top.moveBy(i,0);
+				window.top.moveBy(0,-i);
+				window.top.moveBy(-i,0);
+			}//for
+		}//for
+	}//if
+}
+//----------------------------------------------------------------------------
+function view_source(){ //Opera - nok; IE - ok. NN6 - ok.
+MyWindow.location = "view-source:" + MyWindow.location.href;
+} 
+//----------------------------------------------------------------------------
+function printit(){
+	var browser_name = navigator.appName;
+	if (browser_name == "Netscape") {
+    	MyWindow.print() ;
+	} else {
+    	var WebBrowser = '<object id="WebBrowser1" width=0 height=0 classid="clsid:8856F961-340A-11D0-A96B-00C04FD705A2"></object>';
+	    document.body.insertAdjacentHTML('beforeEnd', WebBrowser);
+    	WebBrowser1.ExecWB(6, 2);
+	}
+}
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/fsmtools.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/navig.js
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/navig.js	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/navig.js	(revision 264)
@@ -0,0 +1,178 @@
+
+// styles definition
+
+document.writeln ('<style>');
+document.writeln ('body { margin: 0px}');
+document.writeln ('#tabs { margin: 0px; border-width: 0px }');
+document.writeln ('</style>');
+
+// paths
+
+var TreePath = "./" + RootProject + "images/tree/";
+var TabsPath = "./" + RootProject + "images/tab/";
+if (DownTabs == 1)
+ TabsPath = "./" + RootProject + "images/itab/";
+var ExtPath = "./" + RootProject + "images/ext/";
+
+// preloading images
+
+LeftNot = new Image ();
+RightNot = new Image ();
+
+LeftSel = new Image ();
+RightSel = new Image ();
+
+SelNot = new Image ();
+NotSel = new Image ();
+NotNot = new Image ();
+
+TabNot = new Image ();
+TabSel = new Image ();
+
+Project = new Image ();
+VHD = new Image ();
+V = new Image ();
+EDN = new Image ();
+BDE = new Image ();
+AWF = new Image ();
+ASF = new Image ();
+LST = new Image ();
+TXT = new Image ();
+PL = new Image ();
+TCL = new Image ();
+DO = new Image ();
+CPP = new Image ();
+UNDEF = new Image ();
+
+Empty = new Image ();
+
+LeftNot.src = TabsPath + "left_n.bmp";
+RightNot.src = TabsPath + "right_n.bmp";
+
+LeftSel.src = TabsPath + "left_s.bmp";
+RightSel.src = TabsPath + "right_s.bmp";
+
+SelNot.src = TabsPath + "s_n.bmp";
+NotSel.src = TabsPath + "n_s.bmp";
+NotNot.src = TabsPath + "n_n.bmp";
+
+TabNot.src = TabsPath + "tab_n.bmp";
+TabSel.src = TabsPath + "tab_s.bmp";
+
+Project.src = TreePath + "project.bmp";
+
+VHD.src = ExtPath + "vhd.gif";
+V.src = ExtPath + "v.gif";
+EDN.src = ExtPath + "edn.gif";
+BDE.src = ExtPath + "bde.gif";
+AWF.src = ExtPath + "awf.gif";
+ASF.src = ExtPath + "asf.gif";
+LST.src = ExtPath + "lst.gif";
+TXT.src = ExtPath + "txt.gif";
+PL.src = ExtPath + "pl.gif";
+TCL.src = ExtPath + "tcl.gif";
+DO.src = ExtPath + "do.gif";
+CPP.src = ExtPath + "cpp.gif";
+UNDEF.src = ExtPath + "undef.gif";
+
+Empty.src = TabsPath + "empty.gif";
+
+// working with tab
+
+var ID = 0;
+
+function SetTab (Type, Name, URL)
+ {
+  var str;
+  str = '<td id=tab background="' + TabNot.src + '" valign="middle"><nobr>';
+  str += '<a style="text-decoration: none; font-size: 12px" href="' + URL + '" target=' + Target + ' onClick="ChangeButtons(\'' + ID + '\')">';         ChangeButtons
+  str += '&nbsp;<img hspace="0" vspace="0" border="0" align="absmiddle" width="18" height="16" src="' + Type.src + '">&nbsp;';
+  str += '&nbsp;' + Name + '&nbsp;';
+  str += '</a>';
+  str += '</td>';
+  this.document.writeln (str);
+  ++ID;
+ }
+
+// working with limiters
+
+function SetLeft ()
+ {
+  this.document.writeln ('<td><img width="7" height="21" src="' + LeftNot.src + '"></td>');
+ }
+
+function SetRight ()
+ {
+  this.document.writeln ('<td><img width="7" height="21" src="' + RightNot.src + '"></td>');
+ }
+
+function SetBTab ()
+ {
+  this.document.writeln ('<td><img width="7" height="21" src="' + NotNot.src + '"></td>');
+ }
+
+var CurTab = 1;
+
+function ChangeButtons (ID)
+ {
+
+  var off = 1 - DownTabs;
+
+  if (CurTab == ID)
+   return;
+
+  if (CurTab == 0)
+   {
+    this.document.images(off+0).src = LeftNot.src;
+    this.document.images(off+2).src = NotNot.src;
+   }
+  if (CurTab == (ColTabs - 1))
+   {
+    this.document.images(off+ColTabs*2 - 2).src = NotNot.src;
+    this.document.images(off+ColTabs*2).src = RightNot.src;
+   }
+  if (CurTab > 0 && CurTab < (ColTabs - 1))
+   {
+    this.document.images(off+CurTab*2).src = NotNot.src;
+    this.document.images(off+CurTab*2 + 2).src = NotNot.src;
+   }
+  if(ColTabs!=1)
+  this.document.all ('tab', CurTab).background = TabNot.src;
+
+  CurTab = ID;
+
+  if (CurTab == 0)
+   {
+    this.document.images(off+0).src = LeftSel.src;
+    this.document.images(off+2).src = SelNot.src;
+   }
+  if (CurTab == (ColTabs - 1))
+   {
+    this.document.images(off+ColTabs*2 - 2).src = NotSel.src;
+    this.document.images(off+ColTabs*2).src = RightSel.src;
+   }
+  if (CurTab > 0 && CurTab < (ColTabs - 1))
+   {
+    this.document.images(off+CurTab*2).src = NotSel.src;
+    this.document.images(off+CurTab*2 + 2).src = SelNot.src;
+   }
+
+  this.document.all ('tab', CurTab).background = TabSel.src;
+
+ }
+
+// working with tabs
+
+function BeginTabs ()
+ {
+  if (!DownTabs)
+   this.document.writeln ('<img height="4" src="' + Empty.src + '"><br>');
+  this.document.writeln ('<table id=tabs cellspacing="0" cellpadding="0"><tr>');
+ }
+
+function EndTabs ()
+ {
+  document.writeln ('</tr></table>');
+  ChangeButtons (0);
+ }
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/navig.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/README.txt	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/README.txt	(revision 264)
@@ -0,0 +1,5 @@
+USBHostSlave has been successfully compiled using Quartus 4.1
+However, you will need to set the path to the include files before you get it to compile.
+Assignments>>EDA Tool Settings>>User Libraries.
+Remove the existing library mapping, and add absolute path to USBHostSlave/rtl/include
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qpf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qpf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qpf	(revision 264)
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+# support information,  device programming or simulation file,  and any other
+# associated  documentation or information  provided by  Altera  or a partner
+# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+# other  use  of such  megafunction  design,  netlist,  support  information,
+# device programming or simulation file,  or any other  related documentation
+# or information  is prohibited  for  any  other purpose,  including, but not
+# limited to  modification,  reverse engineering,  de-compiling, or use  with
+# any other  silicon devices,  unless such use is  explicitly  licensed under
+# a separate agreement with  Altera  or a megafunction partner.  Title to the
+# intellectual property,  including patents,  copyrights,  trademarks,  trade
+# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+# support  information,  device programming or simulation file,  or any other
+# related documentation or information provided by  Altera  or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.1"
+DATE = "05:38:41  October 04, 2004"
+
+
+# Revisions
+
+PROJECT_REVISION = "usbHostSlave"

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qpf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifoBI.v	(revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: RxFifoBI.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:51  sfielding
+// Created
+//
+//
+
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+  address, 
+  writeEn, 
+  strobe_i,
+  clk, 
+  rst, 
+  fifoSelect,
+  fifoDataIn,
+  busDataIn, 
+  busDataOut,
+  fifoREn,
+  fifoEmpty,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoREn;
+input fifoEmpty;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoREn;
+wire fifoEmpty;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)
+begin
+  case (address)
+      `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00; 
+  endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b0 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoREn <= 1'b1;
+  else
+    fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoRTL.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoRTL.v	(revision 264)
@@ -0,0 +1,149 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoRTL.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+////  User must check full and empty flags before accessing fifo
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoRTL.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:51  sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input rst;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoWEn;
+input fifoREn;
+output fifoFull;
+output fifoEmpty;
+input forceEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire clk;
+wire rst;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg  [15:0]numElementsInFifo;
+
+
+// local registers
+reg  [ADDR_WIDTH-1:0]bufferInIndex;
+reg  [ADDR_WIDTH-1:0]bufferOutIndex;
+reg  [ADDR_WIDTH:0]bufferCnt;
+reg  fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || forceEmpty == 1'b1)
+  begin
+    bufferCnt <= 0;
+    fifoFull <= 1'b0;
+    fifoEmpty <= 1'b1;
+    bufferInIndex <= 0;
+    bufferOutIndex <= 0;
+    fifoREnDelayed <= 1'b0;
+  end
+    else
+    begin
+      if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        dataOut <= dataFromMem;
+      end
+      fifoREnDelayed <= fifoREn;
+      if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
+        bufferCnt <= bufferCnt + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end 
+      else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferCnt <= bufferCnt - 1;
+        bufferOutIndex <= bufferOutIndex + 1;
+      end
+      else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferOutIndex <= bufferOutIndex + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end
+      if (bufferCnt[ADDR_WIDTH] == 1'b1)
+        fifoFull <= 1'b1;
+      else
+        fifoFull <= 1'b0;
+      if (|bufferCnt == 1'b0) 
+        fifoEmpty <= 1'b1;
+      else
+        fifoEmpty <= 1'b0;
+    end
+end
+
+//pad bufferCnt with leading zeroes
+always @(bufferCnt) begin
+  numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
+end
+
+fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_fifoMem (
+  .addrIn(bufferInIndex),
+  .addrOut(bufferOutIndex),
+  .clk(clk),
+  .dataIn(dataIn),
+  .writeEn(fifoWEn),
+  .readEn(fifoREn),
+  .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm	(revision 264)
@@ -0,0 +1,449 @@
+<html>
+<head>
+<title>slavecontroller.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveController</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:21 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSlaveControl_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>slavecontroller</span> (<span id=t_idt>CRCError</span>, <span id=t_idt>NAKSent</span>, <span id=t_idt>RxByte</span>, <span id=t_idt>RxDataWEn</span>, <span id=t_idt>RxOverflow</span>, <span id=t_idt>RxStatus</span>, <span id=t_idt>RxTimeOut</span>, <span id=t_idt>SCGlobalEn</span>, <span id=t_idt>SOFRxed</span>, <span id=t_idt>USBEndPControlReg</span>, <span id=t_idt>USBEndPNakTransTypeReg</span>, <span id=t_idt>USBEndPTransTypeReg</span>, <span id=t_idt>USBEndP</span>, <span id=t_idt>USBTgtAddress</span>, <span id=t_idt>bitStuffError</span>, <span id=t_idt>clk</span>, <span id=t_idt>clrEPRdy</span>, <span id=t_idt>endPMuxErrorsWEn</span>, <span id=t_idt>frameNum</span>, <span id=t_idt>getPacketREn</span>, <span id=t_idt>getPacketRdy</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketPID</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>stallSent</span>, <span id=t_idt>transDone</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>CRCError</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByte</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RxDataWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RxOverflow</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxStatus</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RxTimeOut</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SCGlobalEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPControlReg</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>USBTgtAddress</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>NAKSent</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SOFRxed</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPNakTransTypeReg</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPTransTypeReg</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndP</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>clrEPRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>endPMuxErrorsWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>getPacketREn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>stallSent</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>transDone</span>;
+
+<span id=t_kwd>wire</span>    <span id=t_idt>CRCError</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>NAKSent</span>, <span id=t_idt>next_NAKSent</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByte</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RxDataWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RxOverflow</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxStatus</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RxTimeOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCGlobalEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFRxed</span>, <span id=t_idt>next_SOFRxed</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPControlReg</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPNakTransTypeReg</span>, <span id=t_idt>next_USBEndPNakTransTypeReg</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPTransTypeReg</span>, <span id=t_idt>next_USBEndPTransTypeReg</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndP</span>, <span id=t_idt>next_USBEndP</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>USBTgtAddress</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>clrEPRdy</span>, <span id=t_idt>next_clrEPRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>endPMuxErrorsWEn</span>, <span id=t_idt>next_endPMuxErrorsWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>, <span id=t_idt>next_frameNum</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>getPacketREn</span>, <span id=t_idt>next_getPacketREn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>, <span id=t_idt>next_sendPacketPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>next_sendPacketWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>stallSent</span>, <span id=t_idt>next_stallSent</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>transDone</span>, <span id=t_idt>next_transDone</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>PIDByte</span>, <span id=t_idt>next_PIDByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>6</span>:<span id=t_cns>0</span>]<span id=t_idt>USBAddress</span>, <span id=t_idt>next_USBAddress</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>addrEndPTemp</span>, <span id=t_idt>next_addrEndPTemp</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>endpCRCTemp</span>, <span id=t_idt>next_endpCRCTemp</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>tempUSBEndPTransTypeReg</span>, <span id=t_idt>next_tempUSBEndPTransTypeReg</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: slvCntrl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_RX1</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIN_SC</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_WAIT_CRC</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_WAIT_ADDR</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_WAIT_STOP</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PID</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_CHK_SOF</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PID_ERROR</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_RDY</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_NAK_STALL</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_CHK_RDY</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_DATA</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_GET_RESP</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_OUT_CHK</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_OUT_SEND</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_OUT_GET_PKT</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_S1</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_DELAY</span> <span id=t_cns>5'b10001</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_CHK_ADDR</span> <span id=t_cns>5'b10010</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_slvCntrl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_slvCntrl</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: slvCntrl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RxByte</span> <span id=t_kwd>or</span> <span id=t_idt>tempUSBEndPTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endpCRCTemp</span> <span id=t_kwd>or</span> <span id=t_idt>addrEndPTemp</span> <span id=t_kwd>or</span> <span id=t_idt>RxDataWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RxStatus</span> <span id=t_kwd>or</span> <span id=t_idt>PIDByte</span> <span id=t_kwd>or</span> <span id=t_idt>USBEndPControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>NAKSent</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>RxOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RxTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>USBEndP</span> <span id=t_kwd>or</span> <span id=t_idt>USBAddress</span> <span id=t_kwd>or</span> <span id=t_idt>USBTgtAddress</span> <span id=t_kwd>or</span> <span id=t_idt>SCGlobalEn</span> <span id=t_kwd>or</span> <span id=t_idt>stallSent</span> <span id=t_kwd>or</span> <span id=t_idt>SOFRxed</span> <span id=t_kwd>or</span> <span id=t_idt>transDone</span> <span id=t_kwd>or</span> <span id=t_idt>clrEPRdy</span> <span id=t_kwd>or</span> <span id=t_idt>endPMuxErrorsWEn</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketREn</span> <span id=t_kwd>or</span> <span id=t_idt>USBEndPTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>USBEndPNakTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketPID</span> <span id=t_kwd>or</span> <span id=t_idt>frameNum</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_slvCntrl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvCntrl_NextState</span>
+  <span id=t_idt>NextState_slvCntrl</span> &lt;= <span id=t_idt>CurrState_slvCntrl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_stallSent</span> &lt;= <span id=t_idt>stallSent</span>;
+  <span id=t_idt>next_NAKSent</span> &lt;= <span id=t_idt>NAKSent</span>;
+  <span id=t_idt>next_SOFRxed</span> &lt;= <span id=t_idt>SOFRxed</span>;
+  <span id=t_idt>next_PIDByte</span> &lt;= <span id=t_idt>PIDByte</span>;
+  <span id=t_idt>next_transDone</span> &lt;= <span id=t_idt>transDone</span>;
+  <span id=t_idt>next_clrEPRdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+  <span id=t_idt>next_endPMuxErrorsWEn</span> &lt;= <span id=t_idt>endPMuxErrorsWEn</span>;
+  <span id=t_idt>next_tempUSBEndPTransTypeReg</span> &lt;= <span id=t_idt>tempUSBEndPTransTypeReg</span>;
+  <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_idt>getPacketREn</span>;
+  <span id=t_idt>next_USBEndPTransTypeReg</span> &lt;= <span id=t_idt>USBEndPTransTypeReg</span>;
+  <span id=t_idt>next_USBEndPNakTransTypeReg</span> &lt;= <span id=t_idt>USBEndPNakTransTypeReg</span>;
+  <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+  <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketPID</span>;
+  <span id=t_idt>next_endpCRCTemp</span> &lt;= <span id=t_idt>endpCRCTemp</span>;
+  <span id=t_idt>next_addrEndPTemp</span> &lt;= <span id=t_idt>addrEndPTemp</span>;
+  <span id=t_idt>next_frameNum</span> &lt;= <span id=t_idt>frameNum</span>;
+  <span id=t_idt>next_USBAddress</span> &lt;= <span id=t_idt>USBAddress</span>;
+  <span id=t_idt>next_USBEndP</span> &lt;= <span id=t_idt>USBEndP</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_slvCntrl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>WAIT_RX1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_stallSent</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_NAKSent</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SOFRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> == `<span id=t_idt>RX_PACKET_START</span> &amp;&amp; 
+      <span id=t_idt>RxByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>TOKEN</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_WAIT_ADDR</span>;
+      <span id=t_idt>next_PIDByte</span> &lt;= <span id=t_idt>RxByte</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>FIN_SC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_transDone</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_clrEPRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_endPMuxErrorsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PID</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>PIDByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] == `<span id=t_idt>SETUP</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_GET_PKT</span>;
+      <span id=t_idt>next_tempUSBEndPTransTypeReg</span> &lt;= `<span id=t_idt>SC_SETUP_TRANS</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>PIDByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] == `<span id=t_idt>OUT</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_GET_PKT</span>;
+      <span id=t_idt>next_tempUSBEndPTransTypeReg</span> &lt;= `<span id=t_idt>SC_OUTDATA_TRANS</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>PIDByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] == `<span id=t_idt>IN</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_CHK_RDY</span>;
+      <span id=t_idt>next_tempUSBEndPTransTypeReg</span> &lt;= `<span id=t_idt>SC_IN_TRANS</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>PID_ERROR</span>;
+   `<span id=t_idt>PID_ERROR</span>:
+     <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>CHK_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_READY_BIT</span>] == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>FIN_SC</span>;
+      <span id=t_idt>next_transDone</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_clrEPRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBEndPTransTypeReg</span> &lt;= <span id=t_idt>tempUSBEndPTransTypeReg</span>;
+      <span id=t_idt>next_endPMuxErrorsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>NAKSent</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>FIN_SC</span>;
+      <span id=t_idt>next_USBEndPNakTransTypeReg</span> &lt;= <span id=t_idt>tempUSBEndPTransTypeReg</span>;
+      <span id=t_idt>next_endPMuxErrorsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>FIN_SC</span>;
+   `<span id=t_idt>SETUP_OUT_CHK</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_READY_BIT</span>] == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_SEND</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>NAK</span>;
+      <span id=t_idt>next_NAKSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_SEND_STALL_BIT</span>] == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_SEND</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>STALL</span>;
+      <span id=t_idt>next_stallSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_SEND</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>ACK</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_OUT_SEND</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_OUT_GET_PKT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> ((<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>CRCError</span> == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>bitStuffError</span> == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RxOverflow</span> == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RxTimeOut</span> == <span id=t_cns>1'b0</span>)) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_CHK</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_NAK_STALL</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_CHK_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_READY_BIT</span>] == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_NAK_STALL</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>NAK</span>;
+      <span id=t_idt>next_NAKSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_SEND_STALL_BIT</span>] == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_NAK_STALL</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>STALL</span>;
+      <span id=t_idt>next_stallSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_OUTDATA_SEQUENCE_BIT</span>] == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_DATA</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_DATA</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_DATA</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_GET_RESP</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_GET_RESP</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>START_S1</span>:
+     <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>GET_TOKEN_WAIT_CRC</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_WAIT_STOP</span>;
+      <span id=t_idt>next_endpCRCTemp</span> &lt;= <span id=t_idt>RxByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> != `<span id=t_idt>RX_PACKET_STREAM</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>GET_TOKEN_WAIT_ADDR</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_WAIT_CRC</span>;
+      <span id=t_idt>next_addrEndPTemp</span> &lt;= <span id=t_idt>RxByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> != `<span id=t_idt>RX_PACKET_STREAM</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>GET_TOKEN_WAIT_STOP</span>:
+     <span id=t_kwd>if</span> ((<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RxByte</span>[`<span id=t_idt>CRC_ERROR_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RxByte</span>[`<span id=t_idt>BIT_STUFF_ERROR_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RxByte</span> [`<span id=t_idt>RX_OVERFLOW_BIT</span>] == <span id=t_cns>1'b0</span>)) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_CHK_SOF</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>GET_TOKEN_CHK_SOF</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>PIDByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] == `<span id=t_idt>SOF</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+      <span id=t_idt>next_frameNum</span> &lt;= {<span id=t_idt>endpCRCTemp</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>],<span id=t_idt>addrEndPTemp</span>};
+      <span id=t_idt>next_SOFRxed</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_DELAY</span>;
+      <span id=t_idt>next_USBAddress</span> &lt;= <span id=t_idt>addrEndPTemp</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+      <span id=t_idt>next_USBEndP</span> &lt;= { <span id=t_idt>endpCRCTemp</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>], <span id=t_idt>addrEndPTemp</span>[<span id=t_cns>7</span>]};
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>GET_TOKEN_DELAY</span>:   <span id=t_com>// Insert delay to allow USBEndPControlReg to update</span>
+     <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_CHK_ADDR</span>;
+   `<span id=t_idt>GET_TOKEN_CHK_ADDR</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBEndP</span> &lt; `<span id=t_idt>NUM_OF_ENDPOINTS</span>  &amp;&amp;
+      <span id=t_idt>USBAddress</span> == <span id=t_idt>USBTgtAddress</span> &amp;&amp;
+      <span id=t_idt>SCGlobalEn</span> == <span id=t_cns>1'b1</span> &amp;&amp;
+      <span id=t_idt>USBEndPControlReg</span>[`<span id=t_idt>ENDPOINT_ENABLE_BIT</span>] == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_PID</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvCntrl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_slvCntrl</span> &lt;= `<span id=t_idt>START_S1</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_slvCntrl</span> &lt;= <span id=t_idt>NextState_slvCntrl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvCntrl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>tempUSBEndPTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>addrEndPTemp</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>endpCRCTemp</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>USBAddress</span> &lt;= <span id=t_cns>7'b0000000</span>;
+   <span id=t_idt>PIDByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>transDone</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_cns>4'b0</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>clrEPRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>USBEndPTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>USBEndPNakTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>NAKSent</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>stallSent</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SOFRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>endPMuxErrorsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>frameNum</span> &lt;= <span id=t_cns>11'b00000000000</span>;
+   <span id=t_idt>USBEndP</span> &lt;= <span id=t_cns>4'h0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>tempUSBEndPTransTypeReg</span> &lt;= <span id=t_idt>next_tempUSBEndPTransTypeReg</span>;
+   <span id=t_idt>addrEndPTemp</span> &lt;= <span id=t_idt>next_addrEndPTemp</span>;
+   <span id=t_idt>endpCRCTemp</span> &lt;= <span id=t_idt>next_endpCRCTemp</span>;
+   <span id=t_idt>USBAddress</span> &lt;= <span id=t_idt>next_USBAddress</span>;
+   <span id=t_idt>PIDByte</span> &lt;= <span id=t_idt>next_PIDByte</span>;
+   <span id=t_idt>transDone</span> &lt;= <span id=t_idt>next_transDone</span>;
+   <span id=t_idt>getPacketREn</span> &lt;= <span id=t_idt>next_getPacketREn</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_idt>next_sendPacketPID</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_idt>next_sendPacketWEn</span>;
+   <span id=t_idt>clrEPRdy</span> &lt;= <span id=t_idt>next_clrEPRdy</span>;
+   <span id=t_idt>USBEndPTransTypeReg</span> &lt;= <span id=t_idt>next_USBEndPTransTypeReg</span>;
+   <span id=t_idt>USBEndPNakTransTypeReg</span> &lt;= <span id=t_idt>next_USBEndPNakTransTypeReg</span>;
+   <span id=t_idt>NAKSent</span> &lt;= <span id=t_idt>next_NAKSent</span>;
+   <span id=t_idt>stallSent</span> &lt;= <span id=t_idt>next_stallSent</span>;
+   <span id=t_idt>SOFRxed</span> &lt;= <span id=t_idt>next_SOFRxed</span>;
+   <span id=t_idt>endPMuxErrorsWEn</span> &lt;= <span id=t_idt>next_endPMuxErrorsWEn</span>;
+   <span id=t_idt>frameNum</span> &lt;= <span id=t_idt>next_frameNum</span>;
+   <span id=t_idt>USBEndP</span> &lt;= <span id=t_idt>next_USBEndP</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_START.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_START.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar551.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar551.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar551.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 551 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller_SETUP_OUT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar551.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/aldec.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/aldec.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/aldec.htm	(revision 264)
@@ -0,0 +1,6 @@
+<html>
+<body bgcolor=blue background="./../images/logoback.bmp" leftmargin="0" topmargin="0" rightmargin="0"
+bottommargin="0" marhinheight=0 marginwidth=0 bgproperties="">
+<a href="http://www.aldec.com" target="_blank"><img hspace="0" vspace="0" src="./../images/logo.gif" alt="ALDEC logo" width="231" height="51" align="left" border="0"></a>
+</body>
+</html>
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/aldec.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.htm	(revision 264)
@@ -0,0 +1,17 @@
+<html>
+<style>
+body    { font-size: 12px }
+#tree   { font-size: 12px }
+#folder { cursor: hand }
+a { color: #000080; text-decoration: none }'
+</style>
+<body background="./../images/aldec.gif" bgproperties="fixed">
+
+<script language="JavaScript">
+<!--
+parent.FirstCreateTree ();
+//-->
+</script>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/settings.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/settings.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/settings.htm	(revision 264)
@@ -0,0 +1,29 @@
+<html>
+<script language="JavaScript">
+function XNotify(){}
+function LoadExp(){window.parent.frames["Map"].window.location.href="./map_e.htm";}
+function LoadColl(){window.parent.frames["Map"].window.location.href="./map_c.htm";}
+if(!document.all){
+	document.captureEvents(Event.CLICK | Event.ONLOAD);
+	document.images["COLL"].onclick = LoadColl;
+	document.images["EXP"].onclick = LoadExp;
+	document.onload = XNotify;
+}
+</script>
+
+<body leftmargin="4" topmargin="2" rightmargin="0" bottommargin="2" marhinheight="0" marginwidth="0" 
+bgcolor="white" background="./../images/aldec.gif"
+onLoad="XNotify()"
+>
+<table align="left" border="0" cellspacing="0" cellpadding="0" valign="center" align="center" height="100%">
+ <tr>
+  <td>
+	<img onClick="LoadColl()" name="COLL" src="./../images/set/coll.gif" alt="Load collapsed tree" width="18" height="16"></a>
+  </td>
+  <td>
+	<img onClick="LoadExp()" name="EXP"  src="./../images/set/exp.gif" alt="Load expanded tree" width="18" height="16">
+  </td>
+ </tr>
+</table>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/settings.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.db_info
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.db_info	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.db_info	(revision 264)
@@ -0,0 +1,3 @@
+Quartus_Version = Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
+Version_Index = 53250
+Creation_Time = Sat Oct 02 05:36:22 2004

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.db_info
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qws
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qws	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qws	(revision 264)
@@ -0,0 +1,23 @@
+[ProjectWorkspace]
+ptn_Child1=Frames
+ptn_Child2=Workmode
+ptn_Child3=ActionPoints
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
+[ProjectWorkspace.Frames.ChildFrames]
+ptn_Child1=Document-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
+DocPathName=../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
+InCompileMode=True
+InSimulateMode=False
+InFirmwareMode=False
+WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPGBAAAAAANBAAAAAACGCAAAAAGHBAAAAA
+IsActiveChildFrame=True
+ptn_Child1=StateMap
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
+AFC_IN_REPORT=False
+[ProjectWorkspace.Workmode]
+CurrentWorkmode=0

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qws
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifoBI.v	(revision 264)
@@ -0,0 +1,126 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: TxFifoBI.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:51  sfielding
+// Created
+//
+//
+
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+  address, writeEn, strobe_i,
+  clk, rst, fifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoWEn,
+  fifoFull,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoWEn;
+input fifoFull;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoWEn;
+wire fifoFull;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoFull or numElementsInFifo)
+begin
+  case (address)
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00;
+  endcase
+end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoWEn <= 1'b1;
+  else
+    fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/busInterface/wishBoneBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/busInterface/wishBoneBI.v	(revision 264)
@@ -0,0 +1,254 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBI.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: wishBoneBI.v,v 1.2 2004-12-18 14:36:08 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:51  sfielding
+// Created
+//
+//
+
+`include "wishBoneBus_h.v"
+
+ 
+module wishBoneBI (
+  address, dataIn, dataOut, writeEn, 
+  strobe_i,
+  ack_o,
+  clk, rst,
+  hostControlSel, 
+  hostRxFifoSel, hostTxFifoSel,
+  slaveControlSel,
+  slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, 
+  slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, 
+  hostSlaveMuxSel,
+  dataFromHostControl,
+  dataFromHostRxFifo,
+  dataFromHostTxFifo,
+  dataFromSlaveControl,
+  dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+  dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+  dataFromHostSlaveMux
+   );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+  dataFromHostControl or
+  dataFromHostRxFifo or
+  dataFromHostTxFifo or
+  dataFromSlaveControl or
+  dataFromEP0RxFifo or 
+  dataFromEP1RxFifo or
+  dataFromEP2RxFifo or
+  dataFromEP3RxFifo or
+  dataFromHostSlaveMux or 
+  dataFromEP0TxFifo or
+  dataFromEP1TxFifo or
+  dataFromEP2TxFifo or
+  dataFromEP3TxFifo)
+begin
+  hostControlSel <= 1'b0;
+  hostRxFifoSel <= 1'b0;
+  hostTxFifoSel <= 1'b0;
+  slaveControlSel <= 1'b0;
+  slaveEP0RxFifoSel <= 1'b0;
+  slaveEP0TxFifoSel <= 1'b0;
+  slaveEP1RxFifoSel <= 1'b0;
+  slaveEP1TxFifoSel <= 1'b0;
+  slaveEP2RxFifoSel <= 1'b0;
+  slaveEP2TxFifoSel <= 1'b0;
+  slaveEP3RxFifoSel <= 1'b0;
+  slaveEP3TxFifoSel <= 1'b0;
+  hostSlaveMuxSel <= 1'b0;
+  case (address & `ADDRESS_DECODE_MASK)
+    `HCREG_BASE : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HCREG_BASE_PLUS_0X10 : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HOST_RX_FIFO_BASE : begin
+      hostRxFifoSel <= 1'b1;
+      dataOut <= dataFromHostRxFifo;
+    end
+    `HOST_TX_FIFO_BASE : begin
+      hostTxFifoSel <= 1'b1;
+      dataOut <= dataFromHostTxFifo;
+    end
+    `SCREG_BASE : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `SCREG_BASE_PLUS_0X10 : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `EP0_RX_FIFO_BASE : begin
+      slaveEP0RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0RxFifo;
+    end
+    `EP0_TX_FIFO_BASE : begin
+      slaveEP0TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0TxFifo;
+    end
+    `EP1_RX_FIFO_BASE : begin
+      slaveEP1RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1RxFifo;
+    end
+    `EP1_TX_FIFO_BASE : begin
+      slaveEP1TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1TxFifo;
+    end
+    `EP2_RX_FIFO_BASE : begin
+      slaveEP2RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2RxFifo;
+    end
+    `EP2_TX_FIFO_BASE : begin
+      slaveEP2TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2TxFifo;
+    end
+    `EP3_RX_FIFO_BASE : begin
+      slaveEP3RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3RxFifo;
+    end
+    `EP3_TX_FIFO_BASE : begin
+      slaveEP3TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3TxFifo;
+    end
+    `HOST_SLAVE_CONTROL_BASE : begin
+      hostSlaveMuxSel <= 1'b1; 
+      dataOut <= dataFromHostSlaveMux;
+    end
+    default: 
+      dataOut <= 8'h00;
+  endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+  ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+  ack_immediate <= strobe_i;
+end 
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+  if (writeEn == 1'b0 &&
+      (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+  begin
+    ack_o <= ack_delayed;
+  end
+  else
+  begin
+    ack_o <= ack_immediate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.asf	(revision 264)
@@ -0,0 +1,287 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=259
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// getpacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: getpacket.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 33
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 58
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 112
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 245
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 251
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "getPkt"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: getPacket"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 35 34 0 TEXT "Conditions" | 122408,97630 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141270,86456 141068,79285
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141010,72814 6500 6500
+L 32 33 0 TEXT "State Labels" | 141010,72814 1 0 0 "PROC_PKT"
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+W 41 6 0 11 40 BEZIER "Transitions" | 96829,146625 92570,132664 92057,131084 90299,121915\
+                                      88541,112746 87971,105860 87641,93102 87312,80344\
+                                      87761,70127 92565,59363 97370,48599 95270,45542\
+                                      101102,30966
+A 42 41 16 TEXT "Actions" | 81060,99034 1 0 0 "RXTimeOut <= 1'b1;"
+C 43 41 0 TEXT "Conditions" | 74897,110510 1 0 0 "SIERxTimeOut == 1'b1"
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+                                         190292,107515 191648,100057 191987,92429 192326,84802\
+                                         192326,61750 188540,53162 184755,44574 169613,33274\
+                                         159556,30336 149499,27398 125714,27614 113171,27388
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 50 46 0 Builtin Exit | 180308,72140
+I 49 46 0 Builtin Entry | 47660,248640
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+W 59 46 0 49 54 BEZIER "Transitions" | 52133,248640 63746,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nNAKRxed <= RXDataIn[`NAK_RXED_BIT];\nstallRxed <= RXDataIn[`STALL_RXED_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 87 72 0 75 80 BEZIER "Transitions" | 37733,254940 43032,249077 61954,258197 67253,252334
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176799,72082 177196,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177616,25344 184028,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n  RXPktStatus = { \n  dataSequence, ACKRxed, \n  stallRxed, NAKRxed,\n  RXTimeOut, RXOverflow, \n  bitStuffError, CRCError};\nend"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+                                           57686,214631 75382,223396 84426,228258
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_SETUP_OUT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_SETUP_OUT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar376.html
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar376.html	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar376.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 376 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller_GET_TOKEN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/slaveController/slavecontroller.asf/toolbar376.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/wrapper/usbHostSlave.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/wrapper/usbHostSlave.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/wrapper/usbHostSlave.v/index.htm	(revision 264)
@@ -0,0 +1,528 @@
+<html>
+<head>
+<title>usbHostSlave.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbHostSlave.v                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////   Top level module</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:45 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>usbHostSlave</span>(
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>,
+  <span id=t_idt>address_i</span>, 
+  <span id=t_idt>data_i</span>, 
+  <span id=t_idt>data_o</span>, 
+  <span id=t_idt>writeEn</span>, 
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>ack_o</span>,
+  <span id=t_idt>hostSOFSentIntOut</span>, 
+  <span id=t_idt>hostConnEventIntOut</span>, 
+  <span id=t_idt>hostResumeIntOut</span>, 
+  <span id=t_idt>hostTransDoneIntOut</span>,
+  <span id=t_idt>slaveNAKSentIntOut</span>,
+  <span id=t_idt>slaveSOFRxedIntOut</span>, 
+  <span id=t_idt>slaveResetEventIntOut</span>, 
+  <span id=t_idt>slaveResumeIntOut</span>, 
+  <span id=t_idt>slaveTransDoneIntOut</span>,
+  <span id=t_idt>USBWireDataIn</span>,
+  <span id=t_idt>USBWireDataInTick</span>,
+  <span id=t_idt>USBWireDataOut</span>,
+  <span id=t_idt>USBWireDataOutTick</span>,
+  <span id=t_idt>USBWireCtrlOut</span>
+   );
+  <span id=t_kwd>parameter</span> <span id=t_idt>HOST_FIFO_DEPTH</span> = <span id=t_cns>64</span>; <span id=t_com>//HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>HOST_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP0_FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP0_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP1_FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP1_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP2_FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP2_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP3_FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP3_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>address_i</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data_i</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data_o</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>output</span> <span id=t_idt>ack_o</span>;
+<span id=t_kwd>output</span> <span id=t_idt>hostSOFSentIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>hostConnEventIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>hostResumeIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>hostTransDoneIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>slaveSOFRxedIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>slaveResetEventIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>slaveResumeIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>slaveTransDoneIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>slaveNAKSentIntOut</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireDataOutTick</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireDataInTick</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireCtrlOut</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>address_i</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data_i</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data_o</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>ack_o</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSOFSentIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostConnEventIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostResumeIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostTransDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveSOFRxedIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>slaveResetEventIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>slaveResumeIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>slaveTransDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveNAKSentIntOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataOutTick</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataInTick</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireCtrlOut</span>;
+
+<span id=t_com>//internal wiring</span>
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControlSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostRxFifoSel</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostTxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSlaveMuxSel</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostControl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromSlaveControl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostRxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostTxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostSlaveMux</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostTxFifoRE</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>hostTxFifoData</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostTxFifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostRxFifoWE</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>hostRxFifoData</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostRxFifoFull</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataFromSIE</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RxDataOutWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateFromHost</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateFromSlave</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityFromHost</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityFromSlave</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnFromHost</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnFromSlave</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortTxRdy</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromHost</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromSlave</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromHost</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromSlave</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetected</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnToSIE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>noActivityTimeOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3Full</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>slaveRxFifoData</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP0RxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP1RxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP2RxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP3RxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP0TxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP1TxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP2TxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP3TxFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP0RxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP1RxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP2RxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP3RxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP0TxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP1TxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP2TxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP3TxFifoSel</span>;
+
+<span id=t_idt>usbHostControl</span> <span id=t_idt>u_usbHostControl</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>TxFifoRE</span>(<span id=t_idt>hostTxFifoRE</span>), 
+  .<span id=t_idt>TxFifoData</span>(<span id=t_idt>hostTxFifoData</span>), 
+  .<span id=t_idt>TxFifoEmpty</span>(<span id=t_idt>hostTxFifoEmpty</span>),
+  .<span id=t_idt>RxFifoWE</span>(<span id=t_idt>hostRxFifoWE</span>), 
+  .<span id=t_idt>RxFifoData</span>(<span id=t_idt>hostRxFifoData</span>), 
+  .<span id=t_idt>RxFifoFull</span>(<span id=t_idt>hostRxFifoFull</span>),
+  .<span id=t_idt>RxByteStatus</span>(<span id=t_idt>RxCtrlOut</span>), 
+  .<span id=t_idt>RxData</span>(<span id=t_idt>RxDataFromSIE</span>), 
+  .<span id=t_idt>RxDataValid</span>(<span id=t_idt>RxDataOutWEn</span>),
+  .<span id=t_idt>SIERxTimeOut</span>(<span id=t_idt>noActivityTimeOut</span>),
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedBitRateFromHost</span>), 
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>fullSpeedPolarityFromHost</span>),
+  .<span id=t_idt>HCTxPortEn</span>(<span id=t_idt>SIEPortWEnFromHost</span>), 
+  .<span id=t_idt>HCTxPortRdy</span>(<span id=t_idt>SIEPortTxRdy</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>SIEPortDataInFromHost</span>), 
+  .<span id=t_idt>HCTxPortCtrl</span>(<span id=t_idt>SIEPortCtrlInFromHost</span>),
+  .<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectState</span>), 
+  .<span id=t_idt>resumeDetectedIn</span>(<span id=t_idt>resumeDetected</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>]),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromHostControl</span>), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>),
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>SOFSentIntOut</span>(<span id=t_idt>hostSOFSentIntOut</span>), 
+  .<span id=t_idt>connEventIntOut</span>(<span id=t_idt>hostConnEventIntOut</span>), 
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>hostResumeIntOut</span>), 
+  .<span id=t_idt>transDoneIntOut</span>(<span id=t_idt>hostTransDoneIntOut</span>),
+  .<span id=t_idt>hostControlSelect</span>(<span id=t_idt>hostControlSel</span>) );
+  
+
+<span id=t_idt>usbSlaveControl</span> <span id=t_idt>u_usbSlaveControl</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>RxByteStatus</span>(<span id=t_idt>RxCtrlOut</span>), 
+  .<span id=t_idt>RxData</span>(<span id=t_idt>RxDataFromSIE</span>), 
+  .<span id=t_idt>RxDataValid</span>(<span id=t_idt>RxDataOutWEn</span>),
+  .<span id=t_idt>SIERxTimeOut</span>(<span id=t_idt>noActivityTimeOut</span>), 
+  .<span id=t_idt>RxFifoData</span>(<span id=t_idt>slaveRxFifoData</span>),
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedBitRateFromSlave</span>), 
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>fullSpeedPolarityFromSlave</span>),
+  .<span id=t_idt>SCTxPortEn</span>(<span id=t_idt>SIEPortWEnFromSlave</span>), 
+  .<span id=t_idt>SCTxPortRdy</span>(<span id=t_idt>SIEPortTxRdy</span>),
+  .<span id=t_idt>SCTxPortData</span>(<span id=t_idt>SIEPortDataInFromSlave</span>), 
+  .<span id=t_idt>SCTxPortCtrl</span>(<span id=t_idt>SIEPortCtrlInFromSlave</span>),
+  .<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectState</span>), 
+  .<span id=t_idt>resumeDetectedIn</span>(<span id=t_idt>resumeDetected</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>]),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromSlaveControl</span>), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>),
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>SOFRxedIntOut</span>(<span id=t_idt>slaveSOFRxedIntOut</span>), 
+  .<span id=t_idt>resetEventIntOut</span>(<span id=t_idt>slaveResetEventIntOut</span>), 
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>slaveResumeIntOut</span>), 
+  .<span id=t_idt>transDoneIntOut</span>(<span id=t_idt>slaveTransDoneIntOut</span>),
+  .<span id=t_idt>NAKSentIntOut</span>(<span id=t_idt>slaveNAKSentIntOut</span>),
+  .<span id=t_idt>slaveControlSelect</span>(<span id=t_idt>slaveControlSel</span>),
+  .<span id=t_idt>TxFifoEP0REn</span>(<span id=t_idt>TxFifoEP0REn</span>),
+  .<span id=t_idt>TxFifoEP1REn</span>(<span id=t_idt>TxFifoEP1REn</span>),
+  .<span id=t_idt>TxFifoEP2REn</span>(<span id=t_idt>TxFifoEP2REn</span>),
+  .<span id=t_idt>TxFifoEP3REn</span>(<span id=t_idt>TxFifoEP3REn</span>),
+  .<span id=t_idt>TxFifoEP0Data</span>(<span id=t_idt>TxFifoEP0Data</span>),
+  .<span id=t_idt>TxFifoEP1Data</span>(<span id=t_idt>TxFifoEP1Data</span>),
+  .<span id=t_idt>TxFifoEP2Data</span>(<span id=t_idt>TxFifoEP2Data</span>),
+  .<span id=t_idt>TxFifoEP3Data</span>(<span id=t_idt>TxFifoEP3Data</span>),
+  .<span id=t_idt>TxFifoEP0Empty</span>(<span id=t_idt>TxFifoEP0Empty</span>),
+  .<span id=t_idt>TxFifoEP1Empty</span>(<span id=t_idt>TxFifoEP1Empty</span>),
+  .<span id=t_idt>TxFifoEP2Empty</span>(<span id=t_idt>TxFifoEP2Empty</span>),
+  .<span id=t_idt>TxFifoEP3Empty</span>(<span id=t_idt>TxFifoEP3Empty</span>),
+  .<span id=t_idt>RxFifoEP0WEn</span>(<span id=t_idt>RxFifoEP0WEn</span>),
+  .<span id=t_idt>RxFifoEP1WEn</span>(<span id=t_idt>RxFifoEP1WEn</span>),
+  .<span id=t_idt>RxFifoEP2WEn</span>(<span id=t_idt>RxFifoEP2WEn</span>),
+  .<span id=t_idt>RxFifoEP3WEn</span>(<span id=t_idt>RxFifoEP3WEn</span>),
+  .<span id=t_idt>RxFifoEP0Full</span>(<span id=t_idt>RxFifoEP0Full</span>),
+  .<span id=t_idt>RxFifoEP1Full</span>(<span id=t_idt>RxFifoEP1Full</span>),
+  .<span id=t_idt>RxFifoEP2Full</span>(<span id=t_idt>RxFifoEP2Full</span>),
+  .<span id=t_idt>RxFifoEP3Full</span>(<span id=t_idt>RxFifoEP3Full</span>)
+  );
+
+<span id=t_idt>wishBoneBI</span> <span id=t_idt>u_wishBoneBI</span> (
+  .<span id=t_idt>address</span>(<span id=t_idt>address_i</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>data_o</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>ack_o</span>(<span id=t_idt>ack_o</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>hostControlSel</span>(<span id=t_idt>hostControlSel</span>), 
+  .<span id=t_idt>hostRxFifoSel</span>(<span id=t_idt>hostRxFifoSel</span>), 
+  .<span id=t_idt>hostTxFifoSel</span>(<span id=t_idt>hostTxFifoSel</span>),
+  .<span id=t_idt>slaveControlSel</span>(<span id=t_idt>slaveControlSel</span>),
+  .<span id=t_idt>slaveEP0RxFifoSel</span>(<span id=t_idt>slaveEP0RxFifoSel</span>), 
+  .<span id=t_idt>slaveEP1RxFifoSel</span>(<span id=t_idt>slaveEP1RxFifoSel</span>), 
+  .<span id=t_idt>slaveEP2RxFifoSel</span>(<span id=t_idt>slaveEP2RxFifoSel</span>), 
+  .<span id=t_idt>slaveEP3RxFifoSel</span>(<span id=t_idt>slaveEP3RxFifoSel</span>), 
+  .<span id=t_idt>slaveEP0TxFifoSel</span>(<span id=t_idt>slaveEP0TxFifoSel</span>), 
+  .<span id=t_idt>slaveEP1TxFifoSel</span>(<span id=t_idt>slaveEP1TxFifoSel</span>), 
+  .<span id=t_idt>slaveEP2TxFifoSel</span>(<span id=t_idt>slaveEP2TxFifoSel</span>), 
+  .<span id=t_idt>slaveEP3TxFifoSel</span>(<span id=t_idt>slaveEP3TxFifoSel</span>), 
+  .<span id=t_idt>hostSlaveMuxSel</span>(<span id=t_idt>hostSlaveMuxSel</span>),
+  .<span id=t_idt>dataFromHostControl</span>(<span id=t_idt>dataFromHostControl</span>),
+  .<span id=t_idt>dataFromHostRxFifo</span>(<span id=t_idt>dataFromHostRxFifo</span>),
+  .<span id=t_idt>dataFromHostTxFifo</span>(<span id=t_idt>dataFromHostTxFifo</span>),
+  .<span id=t_idt>dataFromSlaveControl</span>(<span id=t_idt>dataFromSlaveControl</span>),
+  .<span id=t_idt>dataFromEP0RxFifo</span>(<span id=t_idt>dataFromEP0RxFifo</span>), 
+  .<span id=t_idt>dataFromEP1RxFifo</span>(<span id=t_idt>dataFromEP1RxFifo</span>), 
+  .<span id=t_idt>dataFromEP2RxFifo</span>(<span id=t_idt>dataFromEP2RxFifo</span>), 
+  .<span id=t_idt>dataFromEP3RxFifo</span>(<span id=t_idt>dataFromEP3RxFifo</span>),
+  .<span id=t_idt>dataFromEP0TxFifo</span>(<span id=t_idt>dataFromEP0TxFifo</span>), 
+  .<span id=t_idt>dataFromEP1TxFifo</span>(<span id=t_idt>dataFromEP1TxFifo</span>), 
+  .<span id=t_idt>dataFromEP2TxFifo</span>(<span id=t_idt>dataFromEP2TxFifo</span>), 
+  .<span id=t_idt>dataFromEP3TxFifo</span>(<span id=t_idt>dataFromEP3TxFifo</span>),
+  .<span id=t_idt>dataFromHostSlaveMux</span>(<span id=t_idt>dataFromHostSlaveMux</span>)
+   );
+
+<span id=t_idt>hostSlaveMux</span> <span id=t_idt>u_hostSlaveMux</span>(
+  .<span id=t_idt>SIEPortCtrlInToSIE</span>(<span id=t_idt>SIEPortCtrlInToSIE</span>),
+  .<span id=t_idt>SIEPortCtrlInFromHost</span>(<span id=t_idt>SIEPortCtrlInFromHost</span>),
+  .<span id=t_idt>SIEPortCtrlInFromSlave</span>(<span id=t_idt>SIEPortCtrlInFromSlave</span>),
+  .<span id=t_idt>SIEPortDataInToSIE</span>(<span id=t_idt>SIEPortDataInToSIE</span>), 
+  .<span id=t_idt>SIEPortDataInFromHost</span>(<span id=t_idt>SIEPortDataInFromHost</span>), 
+  .<span id=t_idt>SIEPortDataInFromSlave</span>(<span id=t_idt>SIEPortDataInFromSlave</span>), 
+  .<span id=t_idt>SIEPortWEnToSIE</span>(<span id=t_idt>SIEPortWEnToSIE</span>), 
+  .<span id=t_idt>SIEPortWEnFromHost</span>(<span id=t_idt>SIEPortWEnFromHost</span>), 
+  .<span id=t_idt>SIEPortWEnFromSlave</span>(<span id=t_idt>SIEPortWEnFromSlave</span>), 
+  .<span id=t_idt>fullSpeedPolarityToSIE</span>(<span id=t_idt>fullSpeedPolarityToSIE</span>),
+  .<span id=t_idt>fullSpeedPolarityFromHost</span>(<span id=t_idt>fullSpeedPolarityFromHost</span>),
+  .<span id=t_idt>fullSpeedPolarityFromSlave</span>(<span id=t_idt>fullSpeedPolarityFromSlave</span>),
+  .<span id=t_idt>fullSpeedBitRateToSIE</span>(<span id=t_idt>fullSpeedBitRateToSIE</span>),
+  .<span id=t_idt>fullSpeedBitRateFromHost</span>(<span id=t_idt>fullSpeedBitRateFromHost</span>),
+  .<span id=t_idt>fullSpeedBitRateFromSlave</span>(<span id=t_idt>fullSpeedBitRateFromSlave</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataFromHostSlaveMux</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>),
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>hostSlaveMuxSel</span>(<span id=t_idt>hostSlaveMuxSel</span>)  );
+
+<span id=t_idt>usbSerialInterfaceEngine</span> <span id=t_idt>u_usbSerialInterfaceEngine</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>USBWireDataIn</span>(<span id=t_idt>USBWireDataIn</span>),
+  .<span id=t_idt>USBWireDataOut</span>(<span id=t_idt>USBWireDataOut</span>),
+  .<span id=t_idt>USBWireDataInTick</span>(<span id=t_idt>USBWireDataInTick</span>),
+  .<span id=t_idt>USBWireDataOutTick</span>(<span id=t_idt>USBWireDataOutTick</span>),
+  .<span id=t_idt>USBWireCtrlOut</span>(<span id=t_idt>USBWireCtrlOut</span>),
+  .<span id=t_idt>connectState</span>(<span id=t_idt>connectState</span>),
+  .<span id=t_idt>resumeDetected</span>(<span id=t_idt>resumeDetected</span>),
+  .<span id=t_idt>RxCtrlOut</span>(<span id=t_idt>RxCtrlOut</span>), 
+  .<span id=t_idt>RxDataOutWEn</span>(<span id=t_idt>RxDataOutWEn</span>), 
+  .<span id=t_idt>RxDataOut</span>(<span id=t_idt>RxDataFromSIE</span>), 
+  .<span id=t_idt>SIEPortCtrlIn</span>(<span id=t_idt>SIEPortCtrlInToSIE</span>),
+  .<span id=t_idt>SIEPortDataIn</span>(<span id=t_idt>SIEPortDataInToSIE</span>), 
+  .<span id=t_idt>SIEPortTxRdy</span>(<span id=t_idt>SIEPortTxRdy</span>), 
+  .<span id=t_idt>SIEPortWEn</span>(<span id=t_idt>SIEPortWEnToSIE</span>), 
+  .<span id=t_idt>fullSpeedPolarity</span>(<span id=t_idt>fullSpeedPolarityToSIE</span>),
+  .<span id=t_idt>fullSpeedBitRate</span>(<span id=t_idt>fullSpeedBitRateToSIE</span>),
+  .<span id=t_idt>noActivityTimeOut</span>(<span id=t_idt>noActivityTimeOut</span>)
+);
+
+<span id=t_com>//---Host fifos</span>
+<span id=t_idt>TxFifo</span> #(<span id=t_idt>HOST_FIFO_DEPTH</span>, <span id=t_idt>HOST_FIFO_ADDR_WIDTH</span>) <span id=t_idt>HostTxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>hostTxFifoRE</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>hostTxFifoEmpty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>hostTxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromHostTxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>hostTxFifoData</span>) );
+
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>HOST_FIFO_DEPTH</span>, <span id=t_idt>HOST_FIFO_ADDR_WIDTH</span>) <span id=t_idt>HostRxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>hostRxFifoWE</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>hostRxFifoFull</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>hostRxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromHostRxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>hostRxFifoData</span>)  );
+
+<span id=t_com>//---Slave fifos</span>
+
+<span id=t_idt>TxFifo</span> #(<span id=t_idt>EP0_FIFO_DEPTH</span>, <span id=t_idt>EP0_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP0TxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>TxFifoEP0REn</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEP0Empty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP0TxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP0TxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>TxFifoEP0Data</span>) );
+
+<span id=t_idt>TxFifo</span> #(<span id=t_idt>EP1_FIFO_DEPTH</span>, <span id=t_idt>EP1_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP1TxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>TxFifoEP1REn</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEP1Empty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP1TxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP1TxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>TxFifoEP1Data</span>) );
+
+  <span id=t_idt>TxFifo</span> #(<span id=t_idt>EP2_FIFO_DEPTH</span>, <span id=t_idt>EP2_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP2TxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>TxFifoEP2REn</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEP2Empty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP2TxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP2TxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>TxFifoEP2Data</span>) );
+
+  <span id=t_idt>TxFifo</span> #(<span id=t_idt>EP3_FIFO_DEPTH</span>, <span id=t_idt>EP3_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP3TxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>TxFifoEP3REn</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEP3Empty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP3TxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP3TxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>TxFifoEP3Data</span>) );
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>EP0_FIFO_DEPTH</span>, <span id=t_idt>EP0_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP0RxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>RxFifoEP0WEn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>RxFifoEP0Full</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP0RxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP0RxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>slaveRxFifoData</span>)  );
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>EP1_FIFO_DEPTH</span>, <span id=t_idt>EP1_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP1RxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>RxFifoEP1WEn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>RxFifoEP1Full</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP1RxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP1RxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>slaveRxFifoData</span>)  );
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>EP2_FIFO_DEPTH</span>, <span id=t_idt>EP2_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP2RxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>RxFifoEP2WEn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>RxFifoEP2Full</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP2RxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP2RxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>slaveRxFifoData</span>)  );
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>EP3_FIFO_DEPTH</span>, <span id=t_idt>EP3_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP3RxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>RxFifoEP3WEn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>RxFifoEP3Full</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP3RxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP3RxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>slaveRxFifoData</span>)  );
+
+<span id=t_kwd>endmodule</span>
+
+  
+  
+
+
+
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/src/wrapper/usbHostSlave.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/is.js
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/is.js	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/is.js	(revision 264)
@@ -0,0 +1,3 @@
+
+var nn = (document.layers) ? 1:0;
+var ie = (document.all) ? 1:0;

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/is.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/noexport.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/noexport.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/noexport.htm	(revision 264)
@@ -0,0 +1 @@
+Appropriate file was not exported
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/noexport.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/cmp_state.ini
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/cmp_state.ini	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/cmp_state.ini	(revision 264)
@@ -0,0 +1 @@
+35
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/cmp_state.ini
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Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qsf
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qsf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qsf	(revision 264)
@@ -0,0 +1,93 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+# support information,  device programming or simulation file,  and any other
+# associated  documentation or information  provided by  Altera  or a partner
+# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+# other  use  of such  megafunction  design,  netlist,  support  information,
+# device programming or simulation file,  or any other  related documentation
+# or information  is prohibited  for  any  other purpose,  including, but not
+# limited to  modification,  reverse engineering,  de-compiling, or use  with
+# any other  silicon devices,  unless such use is  explicitly  licensed under
+# a separate agreement with  Altera  or a megafunction partner.  Title to the
+# intellectual property,  including patents,  copyrights,  trademarks,  trade
+# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+# support  information,  device programming or simulation file,  or any other
+# related documentation or information provided by  Altera  or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+# The default values for assignments are stored in the file
+#		usbHostSlave_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.1 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "05:36:22  OCTOBER 02, 2004"
+set_global_assignment -name LAST_QUARTUS_VERSION "4.1 SP2"
+set_global_assignment -name VERILOG_FILE ../../RTL/wrapper/usbHostSlave.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/USBSlaveControlBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/endpMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/fifoMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/sctxportarbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slavecontroller.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveDirectcontrol.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveGetpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveRxStatusMonitor.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveSendpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/usbSlaveControl.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/writeUSBWireData.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/lineControlUpdate.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/processRxBit.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/processRxByte.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/processTxByte.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/readUSBWireData.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/siereceiver.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/SIETransmitter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/updateCRC5.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/updateCRC16.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/usbTxWireArbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostSlaveMux/hostSlaveMuxBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostSlaveMux/hostSlaveMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/USBHostControlBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/directcontrol.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/getpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/hctxportarbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/hostcontroller.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/rxStatusMonitor.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sendpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sendpacketarbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sendpacketcheckpreamble.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sofcontroller.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/softransmit.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/speedCtrlMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/usbHostControl.v
+set_global_assignment -name VERILOG_FILE ../../RTL/busInterface/wishBoneBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/TxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/fifoMem.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/fifoRTL.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/RxFifo.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/RxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/simFifoMem.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/TxFifo.v
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name TOP_LEVEL_ENTITY usbHostSlave
+set_global_assignment -name USER_LIBRARIES "c:\\projects\\usbhostslaveforoc\\rtl\\include/"
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP1C20F400C6

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/usbHostSlave.qsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifo.v	(revision 264)
@@ -0,0 +1,131 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo write access via bus interface, fifo read access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: TxFifo.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:51  sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module TxFifo(
+  clk, 
+  rst, 
+  fifoREn, 
+  fifoEmpty,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataOut ); 
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoREn; 
+output fifoEmpty;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire clk; 
+wire rst; 
+wire fifoREn; 
+wire fifoEmpty;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(busDataIn), 
+  .dataOut(fifoDataOut), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+TxfifoBI u_TxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoWEn(fifoWEn),
+  .fifoFull(fifoFull),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/simFifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/simFifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/simFifoMem.v	(revision 264)
@@ -0,0 +1,92 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// simFifoMem.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: simFifoMem.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:51  sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module simFifoMem(  addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge clk) begin
+  dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge clk) begin
+  if (writeEn == 1'b1)
+    buffer[addrIn] <= dataIn;
+end                  
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/simFifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.v	(revision 264)
@@ -0,0 +1,208 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// directControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: directcontrol.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+  NextState_drctCntl <= CurrState_drctCntl;
+  // Set default values for outputs and signals
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_drctCntl)  // synopsys parallel_case full_case
+    `START_DC:
+    begin
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_drctCntl <= `CHK_DRCT_CNTL;
+        next_HCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {6'b000000, directControlLineState};
+        next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_HCTxPortReq <= 1'b0;
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_drctCntl <= `START_DC;
+  else
+    CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.v	(revision 264)
@@ -0,0 +1,242 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hctxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+input   [7:0]SOFCntlCntl;
+input   [7:0]SOFCntlData;
+input   SOFCntlReq;
+input   SOFCntlWEn;
+output  directCntlGnt;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortWEnable;
+output  sendPacketGnt;
+output  SOFCntlGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+reg     HCTxPortWEnable, next_HCTxPortWEnable;
+wire    rst;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+wire    [7:0]SOFCntlCntl;
+wire    [7:0]SOFCntlData;
+reg     SOFCntlGnt, next_SOFCntlGnt;
+wire    SOFCntlReq;
+wire    SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg  [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+  NextState_HCTxArb = CurrState_HCTxArb;
+  // Set default values for outputs and signals
+  next_SOFCntlGnt <= SOFCntlGnt;
+  next_sendPacketGnt <= sendPacketGnt;
+  next_directCntlGnt <= directCntlGnt;
+  next_muxCntl <= muxCntl;
+  case (CurrState_HCTxArb)  // synopsys parallel_case full_case
+    `START_HARB:
+    begin
+      NextState_HCTxArb = `WAIT_REQ;
+    end
+    `WAIT_REQ:
+    begin
+      if (SOFCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb = `SEND_SOF;
+        next_SOFCntlGnt <= 1'b1;
+        next_muxCntl <= `SOF_CTRL_MUX;
+      end
+      else if (sendPacketReq == 1'b1)
+      begin
+        NextState_HCTxArb = `SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxCntl <= `SEND_PACKET_MUX;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb = `DIRECT_CONTROL;
+        next_directCntlGnt <= 1'b1;
+        next_muxCntl <= `DIRECT_CTRL_MUX;
+      end
+    end
+    `SEND_SOF:
+    begin
+      if (SOFCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_SOFCntlGnt <= 1'b0;
+      end
+    end
+    `SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `DIRECT_CONTROL:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_HCTxArb = `START_HARB;
+  else
+    CurrState_HCTxArb = NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFCntlGnt = 1'b0;
+    sendPacketGnt = 1'b0;
+    directCntlGnt = 1'b0;
+    muxCntl = 2'b00;
+  end
+  else 
+  begin
+    SOFCntlGnt = next_SOFCntlGnt;
+    sendPacketGnt = next_sendPacketGnt;
+    directCntlGnt = next_directCntlGnt;
+    muxCntl = next_muxCntl;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/bdetools.js
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/bdetools.js	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/bdetools.js	(revision 264)
@@ -0,0 +1,467 @@
+var zoo = 100;
+var pzoo = 100;
+var zoom_inc = 2; //or 4
+var SCHEM = "DDT"
+var ViewX=w;
+var ViewY=h;
+var DEBUG_MODE = 1;
+var koef=2/(4400/w);
+//----------------------------------------------------------------------------
+IRoot = RootProject + "images/bde/";
+OV = "over.gif";
+OD = "down.gif";
+//----------------------------------------------------------------------------
+function CodeView(){
+window.parent.location = SchemCode;
+}
+//----------------------------------------------------------------------------
+function GotoPage(){
+	if(PageNext==-1){
+		alert("no page");
+		return;
+	}
+window.parent.location = "./content"+PageNext+".html"
+}
+//----------------------------------------------------------------------------
+function fubclick(lnk){
+	if(lnk!="")
+		window.parent.parent.location = lnk;
+}
+//----------------------------------------------------------------------------
+function DUMP() { 
+	var dump_msg;
+	dump_msg= "w.........."+w+"\n";
+	dump_msg+="h.........."+h+"\n";
+	dump_msg+="zoo........"+zoo+"\n";
+	dump_msg+="pzoo......."+pzoo+"\n";
+	dump_msg+="zoo_inc...."+zoom_inc+"\n";
+	dump_msg+="schem......"+SCHEM+"\n";
+	dump_msg+="viewx......"+ViewX+"\n";
+	dump_msg+="viewy......"+ViewY+"\n";
+	dump_msg+="pagex......"+PageX+"\n";
+	dump_msg+="pagey......"+PageY+"\n";
+	dump_msg+="IE........."+ie+"\n";
+	dump_msg+="NN........."+nn+"\n";
+	alert(dump_msg);
+}
+function alertd(msg) {
+	if(DEBUG_MODE==1)
+		alert(msg)
+}
+//----------------------------------------------------------------------------
+var MyImage;
+var MyDoc;
+var MyWindow;
+//----------------------------------------------------------------------------
+function Init(){
+MyImage = window.parent.frames["xschem"].window.document.images[SCHEM];
+MyImage.src = SchemImage.src;
+MyDoc = window.parent.frames["xschem"].window.document;
+MyWindow =  window.parent.frames["xschem"].window;
+//zoomfull();
+//�������� - � ��, �᫨ ��࠭�� �� ����㦥��?
+//alert("init")
+}
+//----------------------------------------------------------------------------
+function ZRefresh(){
+	ViewX = w*zoo/100;
+	ViewY = h*zoo/100;
+
+	if(ViewX<=0 || ViewY<=0 || ViewX==NaN || ViewY==NaN){
+		alertd("Z-Error: " + ViewX + "##" + ViewY + "##" + zoo + "##" + pzoo);
+		DUMP();
+		ViewX=w;
+		ViewX=h;
+		zoo=100;
+		pzoo=100;		
+	}
+
+//	if ((ViewX>(w/koef)) || (ViewY>(h/koef))){
+//		ViewX=w/koef;
+//		ViewY=h/koef;
+//	}
+
+	MyImage.width  = ViewX;
+	MyImage.height = ViewY;
+
+	if(!ie&&!nn) //NN6
+		MyImage.src = SchemImage.src;
+	if(ie){
+		window.top.resizeBy(1, 1);  
+		window.top.resizeBy(-1, -1);
+	}
+}
+function zoomin(){
+	pzoo=zoo;
+	zoo*=zoom_inc;
+	ZRefresh();
+}
+function zoomout(){
+	if(zoo<=zoom_inc) return;
+	pzoo=zoo;
+	zoo/=zoom_inc;
+	ZRefresh();
+}
+function zoomfit(){	
+	pw=w;ph=h;
+	var cw;var ch;
+	if(ie || nn){
+		if(!MyDoc.body.clientWidth) {
+
+			if (self.screen) { // for NN4 and IE4 
+				cw = screen.width/1.5 ; // What can I do for Opera
+				ch = screen.height/1.5; // What can I do for Opera
+			} else if (self.java) { // for NN3 with enabled Java 
+				var jkit = java.awt.Toolkit.getDefaultToolkit(); 
+				var scrsize = jkit.getScreenSize(); 
+				cw = scrsize.width; 
+				ch = scrsize.height; 
+			} else
+				{
+					cw = w;
+					ch = h
+				} 
+		} 
+
+		else //FOR TRUE IE!!! with clientWidth
+		{	
+			cw=MyDoc.body.clientWidth;
+			ch=MyDoc.body.clientHeight;
+
+			if (Math.round(ViewY)>ch) ch=ch+16;
+			if (Math.round(ViewX)>cw) cw=cw+16;
+			
+		}
+	} else { //for TRUE NN :-) cheak It!!!
+		//alertd("nn"); //NN6 use it		
+		cw=MyWindow.innerWidth*95/100;
+		ch=MyWindow.innerHeight*95/100;
+		//alertd("cw"+cw);
+		//alertd(""ch);
+	}
+
+	fw=100*(cw/pw);
+	fh=100*(ch/ph);
+	xzoo=fh;
+	if(fw<fh)
+		xzoo=fw;
+	if(xzoo==zoo)
+		return;
+	pzoo=zoo;
+	zoo=xzoo;
+	ZRefresh();
+}
+function zoomfull(){
+	pzoo=zoo;
+	zoo=100;
+	ZRefresh();
+}
+function zoomprev(){
+	tmp=zoo;
+	zoo=pzoo;
+	pzoo=tmp;
+	ZRefresh();
+}
+//----------------------------------------------------------------------------
+// Buttons of ToolBar
+//----------------------------------------------------------------------------
+BT_TITL = 0
+BT_ZMIN = 1
+BT_ZOUT = 2
+BT_ZFIT = 3
+BT_FULL = 4
+BT_PREV = 5
+BT_CODE = 6
+BT_PAGE = 7
+BT_PMOD = 8
+BT_ZMOD = 9
+BT_SMOD =10
+BT_OBJV =11
+BT_POPP =12 
+BT_PRNT =13
+BT_NEWW =14
+BT_SYSB =15
+//----------------------------------------------------------------------------
+NRM = 0;
+OVR = 1;
+DWN = 2;
+MES = 3;
+//----------------------------------------------------------------------------
+BT_NUMBER = 16;
+//----------------------------------------------------------------------------
+IMRES = new Array()//0..15 images is here
+Present = new Array(1,1,1,0,1, 1,0,0,0,0, 0,0,0,0,1, 1)//{1/0} boolean of visibility
+//----------------------------------------------------------------------------
+function mClick(i){
+	switch(i)
+	{
+		case BT_TITL: return;
+		case BT_ZMIN: zoomin();return;
+		case BT_ZOUT: zoomout();return;
+		case BT_ZFIT: zoomfit();return;
+		case BT_FULL: zoomfull();return;
+		case BT_PREV: zoomprev();return;
+		case BT_CODE: CodeView();return;
+		case BT_PAGE: GotoPage();return;
+		case BT_PMOD: Grosser(window.top);//Grosser();
+						window.top.resizeBy(1, 1);window.resizeBy(-1, -1); //!!!
+					  return;
+		case BT_ZMOD: return;
+		case BT_SMOD: view_source();return;
+		case BT_OBJV: DUMP();return;
+		case BT_SYSB: if (ie) {window.parent.close();void(0);}
+				if (!ie) {
+if (window.parent.parent.parent.document.title=="") {window.parent.close();void(0);}}
+					  return;
+		case BT_NEWW: fullScreen2(window.parent.location);
+						//window.parent.frames["xschem"].window.document.images[SCHEM].src = SchemImage.src;
+						return;
+		case BT_PRNT: printit();return;
+		case BT_POPP: alert(":-(");return;
+	}
+}
+//----------------------------------------------------------------------------
+function mOver(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][OVR].src;
+	SetStatus(IMRES[i][MES]);
+}
+//----------------------------------------------------------------------------
+function mOut(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][NRM].src;
+	SetStatus("");
+}
+//----------------------------------------------------------------------------
+function mDown(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][DWN].src;
+	SetStatus(IMRES[i][MES]);
+}
+//----------------------------------------------------------------------------
+function mUp(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][OVR].src;
+}
+//----------------------------------------------------------------------------
+function GetBod(i)
+	{
+	switch(i)
+	{	case BT_TITL: return "bar"
+		case BT_ZMIN: return "zoomin"
+		case BT_ZOUT: return "zoomout"
+		case BT_ZFIT: return "fit"
+		case BT_FULL: return "full"
+		case BT_CODE: return "code"
+		case BT_PREV: return "prev"
+		case BT_PAGE: return "goto"
+		case BT_PMOD: return "panmode"
+		case BT_ZMOD: return "zoommode"
+		case BT_SMOD: return "selectmode"
+		case BT_OBJV: return "tbl"
+		case BT_SYSB: return "frame"
+		case BT_NEWW: return "newwindow"
+		case BT_PRNT: return "print"
+		case BT_POPP: return "pop"
+	}
+	return "blank"
+}
+//----------------------------------------------------------------------------
+function GetFile(i, mode)
+	{
+	var bod = GetBod(i)
+	var end; 
+	switch(mode)
+	{	case NRM: end=".gif";break;
+		case OVR: end=OV;break;
+		case DWN: end=OD;
+	}
+	return IRoot + bod + end; 
+}
+//----------------------------------------------------------------------------
+function GetIMessage(i){
+	switch(i)
+	{
+		case BT_ZMIN: return "Zooms in view"
+		case BT_ZOUT: return "Zooms out view"
+		case BT_ZFIT: return "Zooms to fit"
+		case BT_FULL: return "Displays full page"
+		case BT_CODE: return "View generated code"
+		case BT_PREV: return "Displays previously visible area"
+		case BT_PAGE: return "Go to page"
+		case BT_PMOD: return "Enter panning mode"
+		case BT_ZMOD: return "Enter zoom mode"
+		case BT_SMOD: return "Enter select mode"
+		case BT_OBJV: return "Show Objects Window"
+		case BT_NEWW: return "Open in new window"
+		case BT_SYSB: return "Close newly opened window"
+		case BT_PRNT: return "Print"
+		case BT_POPP: return "Enters an upper hierarchical level"
+	}
+	return ""
+}
+//----------------------------------------------------------------------------
+for(i=0;i<BT_NUMBER;i++){
+	IMRES[i] = new Array(new Image(),new Image(),new Image(),"");
+}
+//----------------------------------------------------------------------------
+for(i=0;i<BT_NUMBER;i++){
+	IMRES[i][NRM].src = GetFile(i,NRM);
+	IMRES[i][OVR].src = GetFile(i,OVR);
+	IMRES[i][DWN].src = GetFile(i,DWN);
+	IMRES[i][MES]     = GetIMessage(i);
+//	IMRES[i][HNT]     = GetIHint(i);
+}
+//----------------------------------------------------------------------------
+function GetToolBar(){
+	var tools;
+	var open = '<table align="left" border="0" cellspacing="0" cellpadding="0" valign="center" align="center"> <tr bgcolor="silver" background="silver" bordercolordark="silver" >';
+	var close = '</tr></table>';
+
+	var std0 = '<td ><img hspace="0" vspace="0" border="0" align="absmiddle" ';
+	var std1= 'width=24 height=22 ';
+	var std2 = '></td>';
+
+	tools = open;
+	for(i=0;i<BT_NUMBER;i++){
+		if(Present[i]){
+			tools+=std0;
+			if(i!=BT_SYSB && i!=BT_TITL)
+				tools+=std1;
+			//tools+='src='+ GetINorm(i) + ' ';
+			tools+='src="'+ IMRES[i][NRM].src + '" ';
+			tools+=	'onClick="mClick('    + i + ')" ';
+			tools+=	'onMouseDown="mDown(' + i + ')" ';
+			tools+=	'onMouseUp="mUp(' + i + ')" ';
+			tools+=	'onMouseOver="mOver(' + i + ')" ';
+			tools+=	'onMouseOut="mOut('   + i + ')" ';	//	tools+='name="btn_' + i +'" '
+			tools+=	'name="btn_' + i +'" ';
+			tools+= 'alt="'+GetIMessage(i)+'" ';
+			tools+=std2;								
+		}
+	}
+	tools += close;
+
+	return tools;
+}
+//----------------------------------------------------------------------------
+var NIL = -1;
+//----------------------------------------------------------------------------
+function InRect(x,y,left,top,right,bottom) {
+	if(x>=left && x<=right && y>=top  && y<=bottom)
+		return 1;
+	return 0;	
+}
+//----------------------------------------------------------------------------
+function GetSender(x,y) {
+	for(i=0;i<FUBSNUMBER;i++) {
+		var left  = FUB[i][0];
+		var top   = FUB[i][1];
+		var right = FUB[i][2];
+		var bottom= FUB[i][3];
+
+	factor = PageX / ViewX;
+
+	xx = x*factor;
+	yy = y*factor;
+
+		if(InRect(xx,yy,left,top,right,bottom))
+			return i;
+	}
+	return NIL;
+}
+//----------------------------------------------------------------------------
+function Mapper(MouseX,MouseY) {
+	var SENDER = GetSender(MouseX,MouseY);
+	if(SENDER != NIL){
+		FUB[SENDER][4]();		
+	}
+}
+//----------------------------------------------------------------------------
+function MapperOver(MouseX,MouseY) {
+	var SENDER = GetSender(MouseX,MouseY);
+	if(SENDER != NIL){
+		FUB[SENDER][5]();
+		SetCursor("hand");
+	}
+	else {
+		SetStatus("");
+		SetCursor("default");
+	}
+	
+}
+//----------------------------------------------------------------------------
+function SetStatus(status){
+	if(window.top.status!=status){
+		window.top.status=status;
+		}
+}
+//----------------------------------------------------------------------------
+function SetCursor(cursor){
+	if(ie){
+		if(MyImage.style.cursor!=cursor)
+			MyImage.style.cursor=cursor;
+	} else {
+		; 
+	}
+}
+//----------------------------------------------------------------------------
+function Grosser(Who) { //in Opera - MDI - some bugs :-( but Ok . IE - nok. NN6 - ok
+	//window.moveTo(0,0);
+//	window.resizeTo(screen.availWidth,screen.availHeight);
+	Who.moveTo(0,0);
+	Who.resizeTo(screen.availWidth,screen.availHeight);
+}
+//----------------------------------------------------------------------------
+function fullScreen2(theURL) {
+	window.open(theURL, '', 'fullscreen=yes,scrollbars=yes,status=yes,resizable=yes,location=yes');
+}
+//----------------------------------------------------------------------------
+function boom(n){
+	if (window.top.moveBy)
+	{
+		for (i = 10; i > 0; i--){
+			for (j = n; j > 0; j--){
+				window.top.moveBy(0,i);
+				window.top.moveBy(i,0);
+				window.top.moveBy(0,-i);
+				window.top.moveBy(-i,0);
+			}//for
+		}//for
+	}//if
+}
+//----------------------------------------------------------------------------
+function view_source(){ //Opera - nok; IE - ok. NN6 - ok.
+MyWindow.location = "view-source:" + MyWindow.location.href;
+} 
+//----------------------------------------------------------------------------
+function printit(){
+	var browser_name = navigator.appName;
+	if (browser_name == "Netscape") {
+    	MyWindow.print() ;
+	} else {
+    	var WebBrowser = '<object id="WebBrowser1" width=0 height=0 classid="clsid:8856F961-340A-11D0-A96B-00C04FD705A2"></object>';
+	    document.body.insertAdjacentHTML('beforeEnd', WebBrowser);
+    	WebBrowser1.ExecWB(6, 2);
+	}
+}
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/bdetools.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.js
===================================================================
--- common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.js	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.js	(revision 264)
@@ -0,0 +1,249 @@
+
+// styles definition
+
+document.writeln ('<style>');
+document.writeln ('body    { font-size: 12px }');
+document.writeln ('#tree   { font-size: 12px }');
+document.writeln ('#folder { cursor: hand }');
+document.writeln ('a { color: #000080; text-decoration: none }');
+document.writeln ('</style>');
+
+// paths
+
+if ((ie) || (nn))
+{
+	var TreePath = "./images/tree/";
+	var ExtPath = "./images/ext/";
+	var DocPath = "./../src/";
+}
+if ((!ie) && (!nn))
+{
+	var TreePath = "./../images/tree/";
+	var ExtPath = "./../images/ext/";
+	var DocPath = "./../src/";
+}
+
+
+// preloading images
+
+Empty = new Image ();
+
+Join = new Image ();
+JoinBottom = new Image ();
+JoinTop = new Image ();
+JoinLeft = new Image ();
+
+Line = new Image ();
+
+Minus = new Image ();
+MinusBottom = new Image ();
+MinusOnly = new Image ();
+MinusTop = new Image ();
+
+Plus = new Image ();
+PlusBottom = new Image ();
+PlusOnly = new Image ();
+PlusTop = new Image ();
+
+FolderOpened = new Image ();
+FolderClosed = new Image ();
+
+Project = new Image ();
+
+VHD = new Image ();VHDL = new Image ();//VHDL Source cod
+V = new Image (); //Verilog Source cod
+EDN = new Image (); //edif...
+BDE = new Image ();
+AWF = new Image ();
+ASF = new Image (); //"State diagram"
+LST = new Image ();
+TXT = new Image ();
+PL = new Image ();
+TCL = new Image ();
+DO = new Image ();
+CPP = new Image ();
+SDF = new Image (); //"SDF File"
+
+XNF = new Image (); //"XNF Netlist"
+VLS = new Image (); //"ViewLogic Schematic"
+VTB = new Image (); //"VHDL Test bench"  || "Verilog Test bench"
+HTM = new Image ();HTML = new Image ();   //"HTML Document"
+BAS = new Image ();
+UND = new Image (); //undefined        || "External File"
+
+CONF = new Image (); //"Configuration file"
+DRW = new Image (); //"Drawing" ????
+SYMB = new Image (); //"Symbol Sheet" ????
+
+ACP = new Image (); //Active-CAD Project
+AHW = new Image (); //Active-HDL Workspace
+
+///////////////////////////////////////////
+Empty.src = TreePath + "empty.gif";
+
+Join.src = TreePath + "join.gif";
+JoinBottom.src = TreePath + "join_b.gif";
+JoinTop.src = TreePath + "join_t.gif";
+JoinLeft.src = TreePath + "join_l.gif";
+
+Line.src = TreePath + "line.gif";
+
+Minus.src = TreePath + "minus.gif";
+MinusBottom.src = TreePath + "minus_b.gif";
+MinusOnly.src = TreePath + "minus_o.gif";
+MinusTop.src = TreePath + "minus_t.gif";
+
+Plus.src = TreePath + "plus.gif";
+PlusBottom.src = TreePath + "plus_b.gif";
+PlusOnly.src = TreePath + "plus_o.gif";
+
+FolderOpened.src = TreePath + "folder_o.gif";
+FolderClosed.src = TreePath + "folder_c.gif";
+///////////////////////////////////////////
+Project.src = TreePath + "project.gif";
+///////////////////////////////////////////
+VHD.src = ExtPath + "vhd.gif";
+V.src = ExtPath + "v.gif";
+EDN.src = ExtPath + "edn.gif";
+BDE.src = ExtPath + "bde.gif";
+AWF.src = ExtPath + "awf.gif";
+ASF.src = ExtPath + "asf.gif";
+LST.src = ExtPath + "lst.gif";
+TXT.src = ExtPath + "txt.gif";
+PL.src = ExtPath + "pl.gif";
+TCL.src = ExtPath + "tcl.gif";
+DO.src = ExtPath + "do.gif";
+CPP.src = ExtPath + "cpp.gif";
+SDF.src = ExtPath + "sdf.gif";
+
+XNF.src = ExtPath + "xnf.gif";
+VLS.src = ExtPath + "vls.gif"; 
+VTB.src = ExtPath + "vtb.gif"; 
+HTM.src = ExtPath + "htm.gif"; HTML.src = HTM.src;
+BAS.src = ExtPath + "bas.gif"; 
+UND.src = ExtPath + "und.gif"; 
+
+CONF.src = ExtPath + "conf.gif"; 
+DRW.src = ExtPath + "drw.gif"; 
+SYMB.src = ExtPath + "symb.gif"; 
+
+ACP.src = ExtPath + "acp.gif"; 
+AHW.src = ExtPath + "ahw.gif"; 
+
+// working with tree
+
+function BeginTree ()
+ {
+  return '<table width="95%" cellspacing="0" cellpadding="0" border="0"><tbody align="left" valign="middle">';
+ }
+
+function EndTree ()
+ {
+  return '</table>';
+ }
+
+function FirstCreateTree()
+{
+  window.frames["Map"].document.writeln(DrawMapTree());
+}
+
+function CreateTree ()
+ {
+  if (!ie)
+  {
+  window.frames["Map"].document.open();
+  window.frames["Map"].document.writeln("<html>");
+  window.frames["Map"].document.writeln ('<style>');
+  window.frames["Map"].document.writeln ('body    { font-size: 12px }');
+  window.frames["Map"].document.writeln ('#tree   { font-size: 12px }');
+  window.frames["Map"].document.writeln ('#folder { cursor: hand }');
+  window.frames["Map"].document.writeln ('a { color: #000080; text-decoration: none }');
+  window.frames["Map"].document.writeln ('</style>');
+  window.frames["Map"].document.writeln("<body background=\"./../images/aldec.gif\" bgproperties=\"fixed\">");
+  window.frames["Map"].document.writeln("<script language=\"JavaScript\">");
+  window.frames["Map"].document.writeln("<!--");
+  for(i=0;i<Expanded.length;++i)
+    window.frames["Map"].document.writeln("parent.Expanded["+i+"]="+Expanded[i]+";");  
+  window.frames["Map"].document.writeln("//-->");
+  window.frames["Map"].document.writeln("</script>");
+  window.frames["Map"].document.writeln(DrawMapTree());
+  window.frames["Map"].document.writeln("</body>");
+  window.frames["Map"].document.writeln("</html>");
+  window.frames["Map"].document.close();
+  }
+  else
+    window.frames["Map"].document.body.innerHTML = DrawMapTree ();
+ }
+
+ function CollapseIt ()
+ {
+  for(i=0;i<Expanded.length;++i)
+   Expanded[i]=false;  
+  CreateTree();
+ }
+
+ function ExpandIt ()
+ {
+  for(i=0;i<Expanded.length;++i)
+   Expanded[i]=true;  
+  CreateTree();
+ }
+
+ function NormalIt ()
+ {
+  for(i=0;i<Expanded.length;++i)
+   Expanded[i]=false;
+  Expanded[0]=true;
+  CreateTree();
+ }
+
+// working with group
+
+function Invert (Number)
+ {
+   Expanded[Number] = ! Expanded[Number];
+   CreateTree ();
+ }
+
+function BR ()
+ {
+  return '<tr><td id=tree><nobr>';
+ }
+
+function ER ()
+ {
+  return '</nobr></td></tr>';
+ }
+
+// working with elements
+
+function Ver (ImgName,Number)
+ {
+  if (Number != -1)
+    return '<a href="#"  onClick="parent.Invert('+Number+');"><img border=0 src="' + ImgName.src + '" width=18 height=20 align=left hspace=0 vspace=0></a>';
+  else
+  return '<img src="' + ImgName.src + '" width=18 height=20 align=left hspace=0 vspace=0>';
+ }
+
+function Ext (ImgName)
+ {
+  return '<img src="' + ImgName.src + '" width=18 height=16 align=left hspace=0 vspace=0>';
+ }
+
+function Tit (Name, URL, Type)
+ {
+  if (Type != "folder")
+   {
+    var URL_doc = DocPath + URL;
+    if ((Type != "project")&&(Type != "HTM"))
+     URL_doc += "/index.htm";
+    if (Type=="project")
+    return ' <a href=' + "./../info/index.htm"+ ' class=k target="Information">' + Name + '</a>';
+    
+    if ((Type!="project")&&(URL==""))
+     return '<font color="#888888"> '+Name;
+    else
+     return ' <a href=' + URL_doc + ' class=k target="Information">' + Name + '</a>';
+   }
+  return Name;
+ }

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/html/struct/map.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.asf	(revision 264)
@@ -0,0 +1,243 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=225
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sendpacket.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
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+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 41
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
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+END
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+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/"
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+I 12 6 0 Builtin Reset | 74872,202290
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: sendPacket"
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "sndPkt"
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP\n/0/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "WAIT_ENABLE\n/1/"
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+W 30 25 0 28 26 BEZIER "Transitions" | 52150,256695 56357,246454 59660,235429 67946,223821
+I 29 25 0 Builtin Exit | 144780,121920
+I 28 25 0 Builtin Entry | 48013,256695
+L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/"
+S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+C 23 22 0 TEXT "Conditions" | 114645,116706 1 0 0 "HCTxPortGnt == 1'b1"
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 113134,104869 113443,100466
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500
+L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+S 47 6 36864 ELLIPSE "States" | 115848,16910 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP\n/5/"
+S 45 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,46294 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,46294 1 0 0 "DATA0_DATA1"
+S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500
+L 42 43 0 TEXT "State Labels" | 116148,48718 1 0 0 "SEND_SOF"
+S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500
+L 40 41 0 TEXT "State Labels" | 61608,50536 1 0 0 "OUT_IN_SETUP"
+W 39 25 0 33 29 BEZIER "Transitions" | 78151,174526 94720,161687 125355,134759 141924,121920
+A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 37 34 16 TEXT "Actions" | 66378,203896 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= PIDNotPID;\nHCTxPortCntl <= `TX_PACKET_START;"
+C 36 34 0 TEXT "Conditions" | 74012,211530 1 0 0 "HCTxPortRdy == 1'b1"
+W 34 25 0 26 33 BEZIER "Transitions" | 71729,211913 72078,205195 72736,192521 73085,185803
+S 33 25 20480 ELLIPSE "States" | 73797,179351 6500 6500
+L 32 33 0 TEXT "State Labels" | 73797,179351 1 0 0 "FIN\n/4/"
+H 58 43 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,5152 212900,250284
+H 51 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 50 6 8193 21 45 BEZIER "Transitions" | 119411,90353 134284,80236 162142,60327 177015,50210
+W 49 6 8194 21 43 BEZIER "Transitions" | 114327,87507 114704,79202 115453,63508 115830,55203
+W 48 6 8195 21 41 BEZIER "Transitions" | 108751,90198 97879,81365 77125,63914 66253,55081
+C 79 48 0 TEXT "Conditions" | 70608,88862 1 0 0 "PID == `OUT || \nPID == `IN || \nPID == `SETUP"
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nHCTxPortReq <= 1'b0;"
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888
+W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311
+W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500
+L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
+S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
+I 84 51 0 Builtin Entry | 48374,241112
+I 83 51 0 Builtin Exit | 161275,73621
+W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
+C 81 50 0 TEXT "Conditions" | 136066,86256 1 0 0 "PID == `DATA0 || PID == `DATA1"
+C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
+S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
+L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
+W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
+A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+I 110 58 0 Builtin Exit | 176204,35771
+I 111 58 0 Builtin Entry | 69864,225148
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1;	 \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
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+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+                                          48213,88528 42471,75064 41184,67490 39897,59917\
+                                          40491,43087 47668,36800 54846,30514 82962,22198\
+                                          91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+                                          200128,135446 205472,144130 205681,151728 205890,159327\
+                                          201380,181037 194241,189595 187102,198154 163054,210680\
+                                          152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// directControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: directcontrol.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 78
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 127
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "Labels" | 187300,263800 1 0 0 "clk"
+W 14 6 0 13 9 BEZIER "Transitions" | 48900,215400 60300,214600 83007,213291 94407,212491
+I 13 6 0 Builtin Reset | 48900,215400
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_DC\n/0/"
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "drctCntl"
+F 6 0 671089152 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+A 5 0 1 TEXT "Actions" | 17700,253700 1 0 0 "// diagram ACTION"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: directControl"
+C 28 27 0 TEXT "Conditions" | 80136,160617 1 0 0 "directControlEn == 1'b1"
+W 27 6 8193 11 78 BEZIER "Transitions" | 99393,170493 94693,161093 75357,144887 70657,135487
+W 26 6 0 9 11 BEZIER "Transitions" | 100525,205718 101125,199618 101292,188766 101892,182666
+I 21 0 2 Builtin InPort | 57252,239123 "" ""
+L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn"
+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 181500,257400 "" ""
+L 17 18 0 TEXT "Labels" | 187500,257400 1 0 0 "rst"
+I 16 0 3 Builtin InPort | 181300,263800 "" ""
+W 51 6 8194 11 127 BEZIER "Transitions" | 108159,173005 122851,164817 139855,136277 144754,128309
+H 79 78 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 78 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 68590,129326 6500 6500
+L 77 78 0 TEXT "State Labels" | 68590,129326 1 0 0 "DRCT_CNTL"
+W 95 79 0 102 93 BEZIER "Transitions" | 65496,102474 65896,97574 67230,81067 67630,76167
+A 94 93 4 TEXT "Actions" | 87021,72145 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 93 79 16384 ELLIPSE "States" | 68621,69745 6500 6500
+W 92 79 8194 93 102 BEZIER "Transitions" | 62907,72842 59107,76242 50421,81945 48421,85645\
+                                           46421,89345 46021,97345 47471,100295 48921,103245\
+                                           55748,105011 58848,106911
+L 91 90 0 TEXT "State Labels" | 62621,146145 1 0 0 "WAIT_GNT\n/2/"
+S 90 79 12288 ELLIPSE "States" | 62621,146145 6500 6500
+W 88 79 4096 124 90 BEZIER "Transitions" | 105569,175900 100869,166500 70569,161175 65869,151775
+L 103 102 0 TEXT "State Labels" | 65021,108945 1 0 0 "WAIT_RDY\n/4/"
+S 102 79 20480 ELLIPSE "States" | 65021,108945 6500 6500
+C 100 99 0 TEXT "Conditions" | 62221,136545 1 0 0 "HCTxPortGnt == 1'b1"
+W 99 79 0 90 102 BEZIER "Transitions" | 62834,139649 63234,133449 64005,121613 64405,115413
+L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/"
+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1"
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
+L 126 127 0 TEXT "State Labels" | 147819,122579 1 0 0 "IDLE"
+W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\
+                                       47285,153175 50048,167625 56316,171290 62585,174956\
+                                       84856,175714 96012,175820
+I 124 79 0 Builtin Entry | 109800,175900
+I 122 79 0 Builtin Exit | 138103,36586
+S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
+S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
+C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "HCTxPortGnt == 1'b1"
+W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
+H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "HCTxPortWEn"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]"
+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "HCTxPortCntl[7:0]"
+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+                                        171826,160150 159742,169266 150997,171704 142252,174142\
+                                        120424,175336 108976,175654
+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "HCTxPortReq <= 1'b1;"
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "HCTxPortGnt"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "HCTxPortRdy"
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;"
+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.asf	(revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hctxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: hctxportarbiter.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,543100 1 0 0 "Module: HCTxPortArbiter"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "HCTxArb"
+S 8 6 0 ELLIPSE "States" | 225591,395370 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_HARB\n/0/"
+S 10 6 4096 ELLIPSE "States" | 224972,365039 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "WAIT_REQ\n/1/"
+S 12 6 8192 ELLIPSE "States" | 191859,293613 6500 6500
+L 13 12 0 TEXT "State Labels" | 191859,293613 1 0 0 "SEND_SOF\n/2/"
+S 14 6 12288 ELLIPSE "States" | 269063,296392 6500 6500
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SEND_PACKET\n/3/"
+I 16 6 0 Builtin Reset | 178237,395710
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210052,391894 219337,393602
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 19 6 2 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 20 6 1 10 12 BEZIER "Transitions" | 219884,360995 214322,355742 203672,314353 193976,299756
+C 21 20 0 TEXT "Conditions" | 185611,358255 1 0 0 "SOFCntlReq == 1'b1"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxCntl <= `SEND_PACKET_MUX;"
+A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;"
+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
+C 26 17 0 TEXT "Conditions" | 201742,391978 1 0 0 "rst"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+                                      288786,359372 287077,371461 282417,376909 277757,382357\
+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+W 28 6 0 12 10 BEZIER "Transitions" | 186560,297376 167155,311353 168429,333163 167686,340659\
+                                      166944,348155 168507,364217 173450,370590 178394,376963\
+                                      186275,384997 193806,383684 201338,382371 213515,373400\
+                                      220004,369229
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n  `SOF_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= SOFCntlWEn;\n    HCTxPortData <= SOFCntlData;\n    HCTxPortCntl <= SOFCntlCntl;\n  end\n  `DIRECT_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= directCntlWEn;\n    HCTxPortData <= directCntlData;\n    HCTxPortCntl <= directCntlCntl;\n  end\n  `SEND_PACKET_MUX :\n  begin  \n    HCTxPortWEnable <= sendPacketWEn;\n    HCTxPortData <= sendPacketData;\n    HCTxPortCntl <= sendPacketCntl;\n  end\n  default :\n  begin  \n    HCTxPortWEnable <= 1'b0;\n    HCTxPortData <= 8'h00;\n    HCTxPortCntl <= 8'h00;\n  end\nendcase	\nend"
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+I 89 0 130 Builtin Signal | 141050,528812 "" ""
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286404,388600 275724,388298\
+                                      265045,387996 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.asf	(revision 264)
@@ -0,0 +1,150 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=153
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketcheckpreamble\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sendpacketcheckpreamble.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 32
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+A 45 44 16 TEXT "Actions" | 74811,210616 1 0 0 "fullSpeedBitRate <= 1'b1;\nfullSpeedPolarity <= 1'b1;\ngrabLineControl <= 1'b1;"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 68 37 BEZIER "Transitions" | 95534,53084 101453,45264 180021,53114 185941,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 93181,145786 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 55 60 BEZIER "Transitions" | 89225,146684 89301,143318 91477,99456 91230,95807
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 59 56 16 TEXT "Actions" | 87075,172050 1 0 0 "sendPacketWEn <= 1'b0;"
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88382,164186 88295,159636
+S 55 33 20480 ELLIPSE "States" | 88650,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88650,153150 1 0 0 "WAIT_RDY2\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "WAIT_RDY3\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+A 66 65 16 TEXT "Actions" | 90202,77286 1 0 0 "sendPacketWEn <= 1'b0;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+A 64 62 16 TEXT "Actions" | 78524,125856 1 0 0 "fullSpeedBitRate <= 1'b1;"
+A 72 39 16 TEXT "Actions" | 141267,52580 1 0 0 "grabLineControl <= 1'b0;"
+C 73 39 0 TEXT "Conditions" | 97529,56755 1 0 0 "sendPacketRdy == 1'b1"
+L 74 75 0 TEXT "Labels" | 35624,223586 1 0 0 "grabLineControl"
+I 75 0 2 Builtin OutPort | 29624,223586 "" ""
+L 76 77 0 TEXT "Labels" | 37072,218796 1 0 0 "fullSpeedPolarity"
+I 77 0 2 Builtin OutPort | 29360,218796 "" ""
+L 78 79 0 TEXT "Labels" | 35397,214093 1 0 0 "fullSpeedBitRate"
+I 79 0 2 Builtin OutPort | 29397,214093 "" ""
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+                                        94907,51569 61918,50756 52575,52503 43232,54250\
+                                        38843,62050 37706,72734 36569,83418 36406,118357\
+                                        40062,129609 43718,140862 58507,150938 67687,153172\
+                                        76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 95904,234688 "" ""
+L 150 151 0 TEXT "Labels" | 101904,234688 1 0 0 "preAmbleEnable"
+K 149 75 0 TEXT "Comments" | 60868,223364 1 0 0 "mux select"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nfullSpeedBitRate <= 1'b0;\nfullSpeedPolarity <= 1'b0;\ngrabLineControl <= 1'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/rxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/rxStatusMonitor.v	(revision 264)
@@ -0,0 +1,102 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// rxStatusMonitor.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: rxStatusMonitor.v,v 1.2 2004-12-18 14:36:10 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:53  sfielding
+// Created
+//
+//
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      connectionEventOut <= 1'b1;
+    else
+      connectionEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.v	(revision 264)
@@ -0,0 +1,183 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketarbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sendpacketarbiter.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input   clk;
+input   [3:0]HC_PID;
+input   HC_SP_WEn;
+input   HCTxReq;
+input   rst;
+input   SOF_SP_WEn;
+input   SOFTxReq;
+output  HCTxGnt;
+output  [3:0]sendPacketPID;
+output  sendPacketWEnable;
+output  SOFTxGnt;
+
+wire    clk;
+wire    [3:0]HC_PID;
+wire    HC_SP_WEn;
+reg     HCTxGnt, next_HCTxGnt;
+wire    HCTxReq;
+wire    rst;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+reg     sendPacketWEnable, next_sendPacketWEnable;
+wire    SOF_SP_WEn;
+reg     SOFTxGnt, next_SOFTxGnt;
+wire    SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC  == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+  NextState_sendPktArb <= CurrState_sendPktArb;
+  // Set default values for outputs and signals
+  next_HCTxGnt <= HCTxGnt;
+  next_SOFTxGnt <= SOFTxGnt;
+  next_muxSOFNotHC <= muxSOFNotHC;
+  case (CurrState_sendPktArb)  // synopsys parallel_case full_case
+    `HC_ACT:
+    begin
+      if (HCTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_HCTxGnt <= 1'b0;
+      end
+    end
+    `SOF_ACT:
+    begin
+      if (SOFTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_SOFTxGnt <= 1'b0;
+      end
+    end
+    `SARB_WAIT_REQ:
+    begin
+      if (SOFTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `SOF_ACT;
+        next_SOFTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b1;
+      end
+      else if (HCTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `HC_ACT;
+        next_HCTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_sendPktArb <= `SARB_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktArb <= `START_SARB;
+  else
+    CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxGnt <= 1'b0;
+    SOFTxGnt <= 1'b0;
+    muxSOFNotHC <= 1'b0;
+  end
+  else 
+  begin
+    HCTxGnt <= next_HCTxGnt;
+    SOFTxGnt <= next_SOFTxGnt;
+    muxSOFNotHC <= next_muxSOFNotHC;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.asf	(revision 264)
@@ -0,0 +1,285 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=432
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hostController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: hostcontroller.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
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+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+I 96 6 0 Builtin Reset | 67359,192312
+A 368 362 4 TEXT "Actions" | 121320,126002 1 0 0 "sendPacketWEn <= 1'b0;"
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+I 411 59 0 Builtin Exit | 100924,12876
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+                                          134254,207065 123583,209376 117848,210301
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+W 167 59 1 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+I 215 66 0 Builtin Entry | 50996,240683
+I 216 66 0 Builtin Exit | 120308,37514
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 231 220 4 TEXT "Actions" | 102966,127564 1 0 0 "sendPacketWEn <= 1'b0;"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.v	(revision 264)
@@ -0,0 +1,184 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sofcontroller
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sofcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input   clk;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+input   SOFEnable;
+input   SOFTimerClr;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [15:0]SOFTimer;
+
+wire    clk;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+wire    SOFEnable;
+reg     [15:0]SOFTimer, next_SOFTimer;
+wire    SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+  NextState_sofCntl <= CurrState_sofCntl;
+  // Set default values for outputs and signals
+  next_SOFTimer <= SOFTimer;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_sofCntl)  // synopsys parallel_case full_case
+    `START_SC:
+    begin
+      NextState_sofCntl <= `WAIT_SOF_EN;
+    end
+    `WAIT_SOF_EN:
+    begin
+      if (SOFEnable == 1'b1)
+      begin
+        NextState_sofCntl <= `SC_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `WAIT_SEND_RESUME:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sofCntl <= `CLR_WEN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_RESUME_START;
+      end
+    end
+    `INC_TIMER:
+    begin
+      next_HCTxPortReq <= 1'b0;
+      if (SOFTimerClr == 1'b1)
+      next_SOFTimer <= 16'h0000;
+      else
+      next_SOFTimer <= SOFTimer + 1'b1;
+      if (SOFEnable == 1'b0)
+      begin
+        NextState_sofCntl <= `WAIT_SOF_EN;
+        next_SOFTimer <= 16'h0000;
+      end
+    end
+    `SC_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sofCntl <= `WAIT_SEND_RESUME;
+      end
+    end
+    `CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sofCntl <= `INC_TIMER;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sofCntl <= `START_SC;
+  else
+    CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFTimer <= 16'h0000;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SOFTimer <= next_SOFTimer;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.project.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_01_alpha/syn/Altera/db/usbHostSlave.project.hdb
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifo.v	(revision 264)
@@ -0,0 +1,133 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo read access via bus interface, fifo write access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: RxFifo.v,v 1.2 2004-12-18 14:36:05 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:51  sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module RxFifo(
+  clk, 
+  rst, 
+  fifoWEn, 
+  fifoFull,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataIn  );
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk; 
+wire rst; 
+wire fifoWEn; 
+wire fifoFull;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(fifoDataIn), 
+  .dataOut(dataFromFifoToBus), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+RxfifoBI u_RxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .fifoDataIn(dataFromFifoToBus),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoREn(fifoREn),
+  .fifoEmpty(fifoEmpty),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoMem.v	(revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMem.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores/usbhostslave/>               ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoMem.v,v 1.2 2004-12-18 14:36:06 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:51  sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+
+module fifoMem(  addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+  // Generic synchronous dual-port RAM interface
+  .rclk(clk), 
+  .rrst(1'b0), 
+  .rce(1'b1), 
+  .oe(readEn), 
+  .raddr(addrOut), 
+  .do(dataOut),
+  .wclk(clk), 
+  .wrst(1'b0), 
+  .wce(1'b1),
+  .we(writeEn), 
+  .waddr(addrIn), 
+  .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_simFifoMem (
+  .addrIn(addrIn),
+  .addrOut(addrOut),
+  .clk(clk),
+  .dataIn(dataIn),
+  .writeEn(writeEn),
+  .readEn(readEn),
+  .dataOut(dataOut));  
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/buffers/fifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/USBHostControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/USBHostControlBI.v	(revision 264)
@@ -0,0 +1,267 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBHostControlBI.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: USBHostControlBI.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:56  sfielding
+// Created
+//
+//
+
+`include "usbHostControl_h.v"
+ 
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+  SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+  TxTransTypeReg, TxSOFEnableReg,
+  TxAddrReg, TxEndPReg, frameNumIn, 
+  RxPktStatusIn, RxPIDIn,
+  connectStateIn,
+  SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+  hostControlSelect,
+  clrTransReq,
+  preambleEn,
+  SOFSync,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  transReq
+  );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output transReq;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg transReq;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//sync write demux
+always @(posedge clk)
+begin
+  clrSOFReq <= 1'b0;
+  clrConnEvtReq <= 1'b0;
+  clrResInReq <= 1'b0;
+  clrTransDoneReq <= 1'b0;
+  setTransReq <= 1'b0;
+  if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+  begin
+    case (address)
+      `TX_CONTROL_REG : begin
+        preambleEn <= dataIn[2];
+        SOFSync <= dataIn[1];
+        setTransReq <= dataIn[0];
+      end
+      `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
+      `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+      `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[0];
+      `TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
+      `TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
+      `INTERRUPT_STATUS_REG :  begin
+        clrSOFReq <= dataIn[3];
+        clrConnEvtReq <= dataIn[2];
+        clrResInReq <= dataIn[1];
+        clrTransDoneReq <= dataIn[0];
+      end
+      `INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[3:0];
+    endcase
+  end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+  if (SOFSentIn == 1'b1)
+    SOFSentInt <= 1'b1;
+  else if (clrSOFReq == 1'b1)
+    SOFSentInt <= 1'b0;
+    
+  if (connEventIn == 1'b1)
+    connEventInt <= 1'b1;
+  else if (clrConnEvtReq == 1'b1)
+    connEventInt <= 1'b0;
+    
+  if (resumeIntIn == 1'b1)
+    resumeInt <= 1'b1;
+  else if (clrResInReq == 1'b1)
+    resumeInt <= 1'b0;  
+
+  if (transDoneIn == 1'b1)
+    transDoneInt <= 1'b1;
+  else if (clrTransDoneReq == 1'b1)
+    transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end  
+  
+//transaction request set/clear
+always @(posedge clk)
+begin
+  if (setTransReq == 1'b1)
+    transReq <= 1'b1;
+  else if (clrTransReq == 1'b1)
+    transReq <= 1'b0;
+end  
+  
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+  TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+  fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+  
+// async read mux
+always @(address or
+  TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+  TxAddrReg or TxEndPReg or frameNumIn or 
+  SOFSentInt or connEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+  preambleEn or SOFSync or transReq)
+begin
+  case (address)
+      `TX_CONTROL_REG : dataOut <= {5'b00000, preambleEn, SOFSync, transReq} ;
+      `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
+      `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+      `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
+      `TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
+      `TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
+      `FRAME_NUM_MSB_REG : dataOut <= frameNumIn[10:3];
+      `FRAME_NUM_LSB_REG : dataOut <= {5'b00000, frameNumIn[2:0]};
+      `INTERRUPT_STATUS_REG :  dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+      `INTERRUPT_MASK_REG  : dataOut <= {4'h0, interruptMaskReg};
+      `RX_STATUS_REG  : dataOut <= RxPktStatusIn;
+      `RX_PID_REG  : dataOut <= {4'b0000, RxPIDIn};
+      `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.asf	(revision 264)
@@ -0,0 +1,98 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=73
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// softransmit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: softransmit.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
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+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+A 67 51 16 TEXT "Actions" | 33349,35565 1 0 0 "sendPacketArbiterReq <= 1'b0;"
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+                                         105450,47318 105450,38252 107207,34228 108965,30205\
+                                         115846,23167 119361,19652
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMux.v	(revision 264)
@@ -0,0 +1,171 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostSlaveMux.v,v 1.2 2004-12-18 14:36:12 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:56  sfielding
+// Created
+//
+//
+
+module hostSlaveMux (
+  SIEPortCtrlInToSIE,
+  SIEPortCtrlInFromHost,
+  SIEPortCtrlInFromSlave,
+  SIEPortDataInToSIE, 
+  SIEPortDataInFromHost, 
+  SIEPortDataInFromSlave, 
+  SIEPortWEnToSIE, 
+  SIEPortWEnFromHost, 
+  SIEPortWEnFromSlave, 
+  fullSpeedPolarityToSIE,
+  fullSpeedPolarityFromHost,
+  fullSpeedPolarityFromSlave,
+  fullSpeedBitRateToSIE,
+  fullSpeedBitRateFromHost,
+  fullSpeedBitRateFromSlave,
+  dataIn, 
+  dataOut, 
+  writeEn,
+  strobe_i,
+  clk, 
+  rst,
+  hostSlaveMuxSel  );
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE; 
+input [7:0] SIEPortDataInFromHost; 
+input [7:0] SIEPortDataInFromSlave; 
+output SIEPortWEnToSIE; 
+input SIEPortWEnFromHost; 
+input SIEPortWEnFromSlave; 
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE; 
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+reg SIEPortWEnToSIE; 
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+  SIEPortCtrlInFromHost or
+  SIEPortCtrlInFromSlave or
+  SIEPortDataInFromHost or 
+  SIEPortDataInFromSlave or 
+  SIEPortWEnFromHost or 
+  SIEPortWEnFromSlave or 
+  fullSpeedPolarityFromHost or
+  fullSpeedPolarityFromSlave or
+  fullSpeedBitRateFromHost or
+  fullSpeedBitRateFromSlave)
+begin
+  if (hostMode == 1'b1) 
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+    SIEPortDataInToSIE <=  SIEPortDataInFromHost;
+    SIEPortWEnToSIE <= SIEPortWEnFromHost;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+  end
+  else
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+    SIEPortDataInToSIE <=  SIEPortDataInFromSlave;
+    SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+  end
+end      
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(dataIn), 
+  .dataOut(dataOut), 
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .hostMode(hostMode), 
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSerialInterfaceEngine_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSerialInterfaceEngine_h.v	(revision 264)
@@ -0,0 +1,100 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v                                
+//
+// $Id: usbSerialInterfaceEngine_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:57  sfielding
+// Created
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate
+`define OVER_SAMPLE_RATE 4
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 6
+`define RESUME_WAIT_TIME 10
+`define RESUME_WAIT_TIME_MINUS1 9
+`define RESUME_LEN 20
+`define CONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd20
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates 
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.v	(revision 264)
@@ -0,0 +1,768 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIETransmitter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: SIETransmitter.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteRdy;
+input   rst;
+input   [7:0]SIEPortCtrlIn;
+input   [7:0]SIEPortDataIn;
+input   SIEPortWEn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processTxByteWEn;
+output  rstCRC;
+output  SIEPortTxRdy;
+output  [7:0]TxByteOut;
+output  [7:0]TxByteOutCtrl;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+wire    processTxByteRdy;
+reg     processTxByteWEn, next_processTxByteWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]SIEPortCtrlIn;
+wire    [7:0]SIEPortDataIn;
+reg     SIEPortTxRdy, next_SIEPortTxRdy;
+wire    SIEPortWEn;
+reg     [7:0]TxByteOut, next_TxByteOut;
+reg     [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [4:0]i, next_i;
+reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg  [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define RES_ST_CHK_FIN 6'b000000
+`define IDLE_CHK_FIN 6'b000001
+`define DIR_CTL_CHK_FIN 6'b000010
+`define PKT_ST_CHK_PID 6'b000011
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
+`define PKT_ST_SPCL_PKT_SENT 6'b000101
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
+`define PKT_ST_TKN_PID_PKT_SENT 6'b000111
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b001000
+`define PKT_ST_DATA_PID_PKT_SENT 6'b001001
+`define PKT_ST_HS_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_S1 6'b001110
+`define RES_ST_S3 6'b001111
+`define RES_ST_S4 6'b010000
+`define RES_ST_S5 6'b010001
+`define RES_ST_S6 6'b010010
+`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
+`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
+`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
+`define START_SIETX 6'b010110
+`define STX_CHK_ST 6'b010111
+`define STX_WAIT_BYTE 6'b011000
+`define IDLE_STX_WAIT_GNT 6'b011001
+`define IDLE_STX_WAIT_RDY 6'b011010
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b011100
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011101
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
+`define DIR_CTL_WAIT_GNT 6'b100001
+`define RES_ST_WAIT_GNT 6'b100010
+`define PKT_ST_HS_WAIT_RDY 6'b100011
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100100
+`define PKT_ST_SPCL_WAIT_RDY 6'b100101
+`define RES_ST_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100111
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b101001
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b101010
+`define DIR_CTL_WAIT_RDY 6'b101011
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
+`define PKT_ST_WAIT_RDY_PKT 6'b101110
+`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
+`define PKT_ST_WAIT_RDY_WIRE 6'b110000
+`define PKT_ST_WAIT_GNT 6'b110001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b110010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b110011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110100
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or KBit or CRC5Result or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
+begin
+  NextState_SIETx <= CurrState_SIETx;
+  // Set default values for outputs and signals
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_USBWireReq <= USBWireReq;
+  next_processTxByteWEn <= processTxByteWEn;
+  next_rstCRC <= rstCRC;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_TxByteOut <= TxByteOut;
+  next_TxByteOutCtrl <= TxByteOutCtrl;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_SIEPortTxRdy <= SIEPortTxRdy;
+  next_SIEPortData <= SIEPortData;
+  next_SIEPortCtrl <= SIEPortCtrl;
+  case (CurrState_SIETx)  // synopsys parallel_case full_case
+    `START_SIETX:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_TxByteOut <= 8'h00;
+      next_TxByteOutCtrl <= 8'h00;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_SIEPortTxRdy <= 1'b0;
+      next_SIEPortData <= 8'h00;
+      next_SIEPortCtrl <= 8'h00;
+      next_i <= 5'h0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `STX_CHK_ST:
+    begin
+      if (SIEPortCtrl == `TX_PACKET_START)
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_IDLE)
+      begin
+        NextState_SIETx <= `IDLE_STX_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_RESUME_START)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+        next_i <= 5'h0;
+      end
+    end
+    `STX_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `STX_CHK_ST;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `DIR_CTL_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_i <= i + 1'b1;
+      if (i == 5'h7)
+      begin
+        NextState_SIETx <= `STX_WAIT_BYTE;
+        next_USBWireReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+      end
+    end
+    `DIR_CTL_WAIT_GNT:
+    begin
+      next_i <= 5'h0;
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+      end
+    end
+    `DIR_CTL_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_CHK_FIN;
+        next_USBWireData <= SIEPortData[1:0];
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `IDLE_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_i <= i + 1'b1;
+      if (i == 5'h7)
+      begin
+        NextState_SIETx <= `STX_WAIT_BYTE;
+        next_USBWireReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_SIETx <= `IDLE_STX_WAIT_RDY;
+      end
+    end
+    `IDLE_STX_WAIT_GNT:
+    begin
+      next_i <= 5'h0;
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `IDLE_STX_WAIT_RDY;
+      end
+    end
+    `IDLE_STX_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `IDLE_CHK_FIN;
+        next_USBWireData <= 2'b00;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `PKT_ST_CHK_PID:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      if (SIEPortData[1:0] == `HANDSHAKE)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `TOKEN)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `SPECIAL)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `DATA)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+      end
+    end
+    `PKT_ST_WAIT_RDY_PKT:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_CHK_PID;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= `SYNC_BYTE;
+        next_TxByteOutCtrl <= `DATA_START;
+      end
+    end
+    `PKT_ST_WAIT_RDY_WIRE:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+        //actively drive the first J bit
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `PKT_ST_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_WIRE;
+      end
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT2:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY1:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[7:0];
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY2:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[15:8];
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_DATA_DATA_CHK_STOP:
+    begin
+      if (SIEPortCtrl == `TX_PACKET_STOP)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+      end
+    end
+    `PKT_ST_DATA_DATA_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_DATA_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC16En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+    end
+    `PKT_ST_DATA_DATA_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_RDY:
+    begin
+      next_CRC16En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+      end
+    end
+    `PKT_ST_DATA_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `PKT_ST_HS_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_HS_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_SPCL_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
+    end
+    `PKT_ST_SPCL_SEND_IDLE1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `PKT_ST_SPCL_SEND_IDLE2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `PKT_ST_SPCL_SEND_IDLE3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_SPCL_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_SPCL_WAIT_WIRE:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_BYTE1_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_CRC_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_CRC_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+    end
+    `PKT_ST_TKN_CRC_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `RES_ST_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (i == `RESUME_LEN)
+      begin
+        NextState_SIETx <= `RES_ST_S1;
+      end
+      else
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_RDY;
+      end
+    end
+    `RES_ST_S1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_S3;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_S3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_S4;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_S4:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_S5;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_S5:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_S6;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_S6:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `RES_ST_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_RDY;
+      end
+    end
+    `RES_ST_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_CHK_FIN;
+        next_USBWireData <= KBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+        next_i <= i + 1'b1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SIETx <= `START_SIETX;
+  else
+    CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    USBWireWEn <= 1'b0;
+    USBWireReq <= 1'b0;
+    processTxByteWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    TxByteOut <= 8'h00;
+    TxByteOutCtrl <= 8'h00;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    SIEPortTxRdy <= 1'b0;
+    i <= 5'h0;
+    SIEPortData <= 8'h00;
+    SIEPortCtrl <= 8'h00;
+  end
+  else 
+  begin
+    USBWireWEn <= next_USBWireWEn;
+    USBWireReq <= next_USBWireReq;
+    processTxByteWEn <= next_processTxByteWEn;
+    rstCRC <= next_rstCRC;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    TxByteOut <= next_TxByteOut;
+    TxByteOutCtrl <= next_TxByteOutCtrl;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    SIEPortTxRdy <= next_SIEPortTxRdy;
+    i <= next_i;
+    SIEPortData <= next_SIEPortData;
+    SIEPortCtrl <= next_SIEPortCtrl;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.v	(revision 264)
@@ -0,0 +1,401 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// getpacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: getpacket.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
+input   clk;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  [7:0]RXPktStatus;
+
+wire    clk;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+reg     [7:0]RXPktStatus;
+wire    [7:0]RXStreamStatusIn;
+wire    SIERxTimeOut;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
+begin
+  NextState_getPkt <= CurrState_getPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  case (CurrState_getPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      if (SIERxTimeOut == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_getPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_getPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_getPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+        next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_getPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (RXFifoFull == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_getPkt <= `START_GP;
+  else
+    CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RxPID <= 4'h0;
+    RXOverflow <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXByteOld <= 8'h00;
+    RXTimeOut <= 1'b0;
+  end
+  else 
+  begin
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RxPID <= next_RxPID;
+    RXOverflow <= next_RXOverflow;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXByteOld <= next_RXByteOld;
+    RXTimeOut <= next_RXTimeOut;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.v	(revision 264)
@@ -0,0 +1,426 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostcontroller.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input   clk;
+input   getPacketRdy;
+input   rst;
+input   [7:0]RXStatus;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   transReq;
+input   [1:0]transType;
+output  clearTXReq;
+output  getPacketREn;
+output  sendPacketArbiterReq;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  transDone;
+
+reg     clearTXReq, next_clearTXReq;
+wire    clk;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+wire    rst;
+wire    [7:0]RXStatus;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     transDone, next_transDone;
+wire    transReq;
+wire    [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 5'b00000
+`define TX_REQ 5'b00001
+`define CHK_TYPE 5'b00010
+`define FLAG 5'b00011
+`define IN_WAIT_DATA_RXED 5'b00100
+`define IN_CHK_FOR_ERROR 5'b00101
+`define IN_CLR_SP_WEN2 5'b00110
+`define SETUP_CLR_SP_WEN1 5'b00111
+`define SETUP_CLR_SP_WEN2 5'b01000
+`define FIN 5'b01001
+`define WAIT_GNT 5'b01010
+`define SETUP_WAIT_PKT_RXED 5'b01011
+`define IN_WAIT_IN_SENT 5'b01100
+`define OUT0_WAIT_RX_DATA 5'b01101
+`define OUT0_WAIT_DATA0_SENT 5'b01110
+`define OUT0_WAIT_OUT_SENT 5'b01111
+`define SETUP_HC_WAIT_RDY 5'b10000
+`define IN_WAIT_SP_RDY1 5'b10001
+`define IN_WAIT_SP_RDY2 5'b10010
+`define OUT0_WAIT_SP_RDY1 5'b10011
+`define SETUP_WAIT_SETUP_SENT 5'b10100
+`define SETUP_WAIT_DATA_SENT 5'b10101
+`define IN_CLR_SP_WEN1 5'b10110
+`define IN_WAIT_ACK_SENT 5'b10111
+`define OUT0_CLR_WEN1 5'b11000
+`define OUT0_CLR_WEN2 5'b11001
+`define OUT1_WAIT_RX_DATA 5'b11010
+`define OUT1_WAIT_OUT_SENT 5'b11011
+`define OUT1_WAIT_DATA1_SENT 5'b11100
+`define OUT1_WAIT_SP_RDY1 5'b11101
+`define OUT1_CLR_WEN1 5'b11110
+`define OUT1_CLR_WEN2 5'b11111
+
+reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+  NextState_hstCntrl <= CurrState_hstCntrl;
+  // Set default values for outputs and signals
+  next_transDone <= transDone;
+  next_clearTXReq <= clearTXReq;
+  next_getPacketREn <= getPacketREn;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketPID <= sendPacketPID;
+  next_sendPacketWEn <= sendPacketWEn;
+  case (CurrState_hstCntrl)  // synopsys parallel_case full_case
+    `START_HC:
+    begin
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `TX_REQ:
+    begin
+      if (transReq == 1'b1)
+      begin
+        NextState_hstCntrl <= `WAIT_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `CHK_TYPE:
+    begin
+      if (transType == `OUTDATA0_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+      end
+      else if (transType == `IN_TRANS)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+      end
+      else if (transType == `SETUP_TRANS)
+      begin
+        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+      end
+      else if (transType == `OUTDATA1_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+      end
+    end
+    `FLAG:
+    begin
+      next_transDone <= 1'b1;
+      next_clearTXReq <= 1'b1;
+      next_sendPacketArbiterReq <= 1'b0;
+      NextState_hstCntrl <= `FIN;
+    end
+    `FIN:
+    begin
+      next_transDone <= 1'b0;
+      next_clearTXReq <= 1'b0;
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `WAIT_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1)
+      begin
+        NextState_hstCntrl <= `CHK_TYPE;
+      end
+    end
+    `SETUP_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+    end
+    `SETUP_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+    end
+    `SETUP_WAIT_PKT_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `SETUP_HC_WAIT_RDY:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `SETUP;
+      end
+    end
+    `SETUP_WAIT_SETUP_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `SETUP_WAIT_DATA_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_DATA_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+      end
+    end
+    `IN_CHK_FOR_ERROR:
+    begin
+      if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+      end
+      else
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `IN_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+    end
+    `IN_WAIT_IN_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `IN;
+      end
+    end
+    `IN_WAIT_SP_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `IN_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+    end
+    `IN_WAIT_ACK_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_DATA0_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `OUT0_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `OUT0_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT0_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+    end
+    `OUT0_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+    end
+    `OUT1_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT1_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `OUT1_WAIT_DATA1_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `OUT1_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT1_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+    end
+    `OUT1_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_hstCntrl <= `START_HC;
+  else
+    CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    transDone <= 1'b0;
+    clearTXReq <= 1'b0;
+    getPacketREn <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketPID <= 4'b0;
+    sendPacketWEn <= 1'b0;
+  end
+  else 
+  begin
+    transDone <= next_transDone;
+    clearTXReq <= next_clearTXReq;
+    getPacketREn <= next_getPacketREn;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketPID <= next_sendPacketPID;
+    sendPacketWEn <= next_sendPacketWEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketarbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sendpacketarbiter.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
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+END
+OBJECTS
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+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "SOF_ACT\n/1/"
+S 11 6 8192 ELLIPSE "States" | 128339,87513 6500 6500
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+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_SARB\n/3/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "sendPktArb"
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+L 40 41 0 TEXT "Labels" | 42274,157869 1 0 0 "HCTxGnt"
+I 41 0 2 Builtin OutPort | 36274,157869 "" ""
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+L 44 45 0 TEXT "Labels" | 168661,153684 1 0 0 "sendPacketPID[3:0]"
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+L 50 51 0 TEXT "Labels" | 44527,153081 1 0 0 "HCTxReq"
+I 51 0 2 Builtin InPort | 38527,153081 "" ""
+L 52 53 0 TEXT "Labels" | 44410,162874 1 0 0 "HC_PID[3:0]"
+I 53 0 130 Builtin InPort | 38410,162874 "" ""
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
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+                                      151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 184576,32757 1 0 0 "HCTxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)  \nbegin\n  if (muxSOFNotHC  == 1'b1)  \n  begin\n    sendPacketWEnable <= SOF_SP_WEn;\n    sendPacketPID <= `SOF;\n  end\n  else\n  begin\n    sendPacketWEnable <= HC_SP_WEn;\n    sendPacketPID <= HC_PID;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "SOFTxGnt <= 1'b0;"
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+                                      89642,107471 97173,106158 104705,104845 116882,95874\
+                                      123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "HCTxGnt <= 1'b0;"
+I 85 0 2 Builtin InPort | 38222,167883 "" ""
+L 86 85 0 TEXT "Labels" | 44222,167883 1 0 0 "HC_SP_WEn"
+I 89 0 2 Builtin InPort | 92234,162554 "" ""
+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sofcontroller\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sofcontroller.asf,v 1.3 2004-12-31 14:40:41 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+END
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+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/speedCtrlMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/speedCtrlMux.v	(revision 264)
@@ -0,0 +1,85 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// speedCtrlMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: speedCtrlMux.v,v 1.2 2004-12-18 14:36:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:55  sfielding
+// Created
+//
+//
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input   directCtrlRate;
+input   directCtrlPol;
+input   sendPacketRate;
+input   sendPacketPol;
+input   sendPacketSel;
+output  fullSpeedRate;
+output  fullSpeedPol;
+
+wire   directCtrlRate;
+wire   directCtrlPol;
+wire   sendPacketRate;
+wire   sendPacketPol;
+wire   sendPacketSel;
+reg   fullSpeedRate;
+reg   fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+  if (sendPacketSel == 1'b1) 
+  begin
+  fullSpeedRate <= sendPacketRate;
+  fullSpeedPol <= sendPacketPol;
+  end
+  else
+  begin
+  fullSpeedRate <= directCtrlRate;
+  fullSpeedPol <= directCtrlPol;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.v	(revision 264)
@@ -0,0 +1,355 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sendpacket.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   [3:0]PID;
+input   rst;
+input   sendPacketWEn;
+input   [6:0]TxAddr;
+input   [3:0]TxEndP;
+output  fifoReadEn;
+output  [10:0]frameNum;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+reg     [10:0]frameNum, next_frameNum;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    [3:0]PID;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+wire    [6:0]TxAddr;
+wire    [3:0]TxEndP;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+  NextState_sndPkt <= CurrState_sndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  next_frameNum <= frameNum;
+  case (CurrState_sndPkt)  // synopsys parallel_case full_case
+    `START_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+    end
+    `WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_sndPkt <= `SP_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `SP_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_HCTxPortReq <= 1'b0;
+    end
+    `SEND_PID_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= PIDNotPID;
+        next_HCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SEND_PID_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+      end
+      else if (PID == `SOF)
+      begin
+        NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+      end
+      else if (PID == `OUT || 
+        PID == `IN || 
+        PID == `SETUP)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sndPkt <= `FIN_SP;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY1:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY2:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `OUT_IN_SETUP_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+    end
+    `SEND_SOF_FIN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_frameNum <= frameNum + 1'b1;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `SEND_SOF_WAIT_RDY3:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= frameNum[7:0];
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_WAIT_RDY4:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_FIN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+    end
+    `DATA0_DATA1_READ_FIFO:
+    begin
+      next_HCTxPortWEn <= 1'b1;
+      next_HCTxPortData <= fifoData;
+      next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+    end
+    `DATA0_DATA1_WAIT_READ_FIFO:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `DATA0_DATA1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+      end
+    end
+    `DATA0_DATA1_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `DATA0_DATA1_TERM_BYTE:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `DATA0_DATA1_CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+    end
+    `DATA0_DATA1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sndPkt <= `START_SP;
+  else
+    CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    HCTxPortData <= 8'h00;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+    frameNum <= 11'h000;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+    frameNum <= next_frameNum;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.v	(revision 264)
@@ -0,0 +1,234 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketcheckpreamble
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sendpacketcheckpreamble.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   preAmbleEnable;
+input   rst;
+input   [3:0]sendPacketCPPID;
+input   sendPacketCPWEn;
+input   sendPacketRdy;
+output  fullSpeedBitRate;
+output  fullSpeedPolarity;
+output  grabLineControl;    // mux select
+output  sendPacketCPReady;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+
+wire    clk;
+reg     fullSpeedBitRate, next_fullSpeedBitRate;
+reg     fullSpeedPolarity, next_fullSpeedPolarity;
+reg     grabLineControl, next_grabLineControl;
+wire    preAmbleEnable;
+wire    rst;
+wire    [3:0]sendPacketCPPID;
+reg     sendPacketCPReady, next_sendPacketCPReady;
+wire    sendPacketCPWEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_WAIT_RDY2 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_WAIT_RDY3 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
+begin
+  NextState_sendPktCP <= CurrState_sendPktCP;
+  // Set default values for outputs and signals
+  next_sendPacketCPReady <= sendPacketCPReady;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  next_fullSpeedBitRate <= fullSpeedBitRate;
+  next_fullSpeedPolarity <= fullSpeedPolarity;
+  next_grabLineControl <= grabLineControl;
+  case (CurrState_sendPktCP)  // synopsys parallel_case full_case
+    `SPC_WAIT_EN:
+    begin
+      if (sendPacketCPWEn == 1'b1)
+      begin
+        NextState_sendPktCP <= `CHK_PREAM;
+        next_sendPacketCPReady <= 1'b0;
+      end
+    end
+    `START_SPC:
+    begin
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `CHK_PREAM:
+    begin
+      if (preAmbleEnable == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+      end
+    end
+    `READY:
+    begin
+      next_sendPacketCPReady <= 1'b1;
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `PREAM_PKT_SND_PREAM:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= `PREAMBLE;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+      next_sendPacketWEn <= 1'b0;
+    end
+    `PREAM_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+        next_fullSpeedBitRate <= 1'b1;
+        next_fullSpeedPolarity <= 1'b1;
+        next_grabLineControl <= 1'b1;
+      end
+    end
+    `PREAM_PKT_WAIT_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+        next_fullSpeedBitRate <= 1'b1;
+      end
+    end
+    `PREAM_PKT_SND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+      next_sendPacketWEn <= 1'b0;
+    end
+    `PREAM_PKT_WAIT_RDY3:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `READY;
+        next_grabLineControl <= 1'b0;
+      end
+    end
+    `REG_PKT_SEND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+    end
+    `REG_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `REG_PKT_SEND_PID;
+      end
+    end
+    `REG_PKT_WAIT_RDY:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `READY;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktCP <= `START_SPC;
+  else
+    CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketCPReady <= 1'b1;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    fullSpeedBitRate <= 1'b0;
+    fullSpeedPolarity <= 1'b0;
+    grabLineControl <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketCPReady <= next_sendPacketCPReady;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+    fullSpeedBitRate <= next_fullSpeedBitRate;
+    fullSpeedPolarity <= next_fullSpeedPolarity;
+    grabLineControl <= next_grabLineControl;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.v	(revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// softransmit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: softransmit.v,v 1.3 2004-12-31 14:40:41 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input   clk;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   SOFEnable;    // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input   SOFSyncEn;
+input   [15:0]SOFTimer;
+output  sendPacketArbiterReq;
+output  sendPacketWEn;
+output  SOFSent;    // single cycle pulse
+output  SOFTimerClr;    // Single cycle pulse
+
+wire    clk;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+wire    SOFEnable;
+reg     SOFSent, next_SOFSent;
+wire    SOFSyncEn;
+wire    [15:0]SOFTimer;
+reg     SOFTimerClr, next_SOFTimerClr;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+  NextState_SOFTx <= CurrState_SOFTx;
+  // Set default values for outputs and signals
+  next_SOFSent <= SOFSent;
+  next_SOFTimerClr <= SOFTimerClr;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketWEn <= sendPacketWEn;
+  case (CurrState_SOFTx)  // synopsys parallel_case full_case
+    `START_STX:
+    begin
+      NextState_SOFTx <= `WAIT_SOF_NEAR;
+    end
+    `WAIT_SOF_NEAR:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+        (SOFSyncEn == 1'b1 &&
+        SOFEnable == 1'b1))
+      begin
+        NextState_SOFTx <= `WAIT_SP_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `WAIT_SP_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+      begin
+        NextState_SOFTx <= `WAIT_SOF_NOW;
+      end
+    end
+    `WAIT_SOF_NOW:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_sendPacketWEn <= 1'b1;
+        next_SOFTimerClr <= 1'b1;
+        next_SOFSent <= 1'b1;
+      end
+      else if (SOFEnable == 1'b0)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_SOFTimerClr <= 1'b1;
+      end
+    end
+    `SOF_FIN:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      next_SOFTimerClr <= 1'b0;
+      next_SOFSent <= 1'b0;
+      NextState_SOFTx <= `WAIT_SOF_NEAR;
+      next_sendPacketArbiterReq <= 1'b0;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SOFTx <= `START_STX;
+  else
+    CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFSent <= 1'b0;
+    SOFTimerClr <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketWEn <= 1'b0;
+  end
+  else 
+  begin
+    SOFSent <= next_SOFSent;
+    SOFTimerClr <= next_SOFTimerClr;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketWEn <= next_sendPacketWEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMuxBI.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostSlaveMuxBI.v,v 1.2 2004-12-18 14:36:12 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:56  sfielding
+// Created
+//
+//
+
+ module hostSlaveMuxBI (dataIn, dataOut, writeEn, strobe_i, clk, rst,
+  hostMode, hostSlaveMuxSel);
+
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+
+//internal wire and regs
+
+//sync write demux
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+    hostMode <= 1'b0;
+  else begin
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1)
+      hostMode <= dataIn[0];
+  end
+end
+
+
+// async read mux
+always @(hostMode)
+begin
+  dataOut <= {7'h0, hostMode};
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSlaveControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSlaveControl_h.v	(revision 264)
@@ -0,0 +1,88 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v                                           
+//
+// $Id: usbSlaveControl_h.v,v 1.3 2004-12-31 14:40:42 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:57  sfielding
+// Created
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants 
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices 
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices 
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices 
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+//SCMasterControlegIndices 
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices 
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes 
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts 
+`define SC_RX_PACKET_TOUT 18
+       
+`endif //usbSlaveControl_h_vdefined  

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/usbHostControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/usbHostControl.v	(revision 264)
@@ -0,0 +1,406 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostControl.v,v 1.2 2004-12-18 14:36:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:56  sfielding
+// Created
+//
+//
+module usbHostControl(
+  clk, rst,
+  //sendPacket
+  TxFifoRE, TxFifoData, TxFifoEmpty,
+  //getPacket
+  RxFifoWE, RxFifoData, RxFifoFull,
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //HCTxPortArbiter
+  HCTxPortEn, HCTxPortRdy,
+  HCTxPortData, HCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFSentIntOut, 
+  connEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  hostControlSelect
+    );
+
+input clk, rst;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [3:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut; 
+output connEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+input hostControlSelect;
+
+wire clk;
+wire rst;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut; 
+wire connEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire sendPacketCPFSRate;
+wire sendPacketCPFSPol;
+wire sendPacketCPGrabLine;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire directCtrlRate;
+wire directCtrlPol;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI 
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .SOFSentIntOut(SOFSentIntOut), 
+  .connEventIntOut(connEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .TxTransTypeReg(transType), 
+  .TxSOFEnableReg(SOFEnable),
+  .TxAddrReg(TxAddr), 
+  .TxEndPReg(TxEndP), 
+  .frameNumIn(frameNum), 
+  .RxPktStatusIn(RxPktStatus), 
+  .RxPIDIn(RxPID),
+  .connectStateIn(connectStateOut),
+  .SOFSentIn(SOFSent), 
+  .connEventIn(connectionEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .hostControlSelect(hostControlSelect),
+  .clrTransReq(clrTxReq),
+  .preambleEn(preAmbleEnable),
+  .SOFSync(SOFSyncEn),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(directCtrlPol), 
+  .fullSpeedRate(directCtrlRate),
+  .transReq(transReq)
+  
+  );
+
+
+hostcontroller u_hostController
+  (.RXStatus(RxPktStatus), 
+  .clearTXReq(clrTxReq),
+  .clk(clk),
+  .getPacketREn(getPacketREn),
+  .getPacketRdy(getPacketRdy),
+  .rst(rst),
+  .sendPacketArbiterGnt(HCTxGnt),
+  .sendPacketArbiterReq(HCTxReq),
+  .sendPacketPID(HC_PID),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(HC_SP_WEn),
+  .transDone(transDone),
+  .transReq(transReq),
+  .transType(transType) );
+
+SOFController u_SOFController
+  (.HCTxPortCntl(SOFCntlCntl),
+  .HCTxPortData(SOFCntlData),
+  .HCTxPortGnt(SOFCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(SOFCntlReq),
+  .HCTxPortWEn(SOFCntlWEn),
+  .SOFEnable(SOFEnable),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(clk),
+  .rst(rst) ); 
+
+SOFTransmit u_SOFTransmit
+  (.SOFEnable(SOFEnable),
+  .SOFSent(SOFSent),
+  .SOFSyncEn(SOFSyncEn),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(clk),
+  .rst(rst),
+  .sendPacketArbiterGnt(SOFTxGnt),
+  .sendPacketArbiterReq(SOFTxReq),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(SOF_SP_WEn) );  
+
+
+sendPacketArbiter u_sendPacketArbiter
+  (.HCTxGnt(HCTxGnt),
+  .HCTxReq(HCTxReq),
+  .HC_PID(HC_PID),
+  .HC_SP_WEn(HC_SP_WEn),
+  .SOFTxGnt(SOFTxGnt),
+  .SOFTxReq(SOFTxReq),
+  .SOF_SP_WEn(SOF_SP_WEn),
+  .clk(clk),
+  .rst(rst),
+  .sendPacketPID(sendPacketCPPIDIn),
+  .sendPacketWEnable(sendPacketCPWEnIn) );    
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+  (.sendPacketCPPID(sendPacketCPPIDIn),
+  .clk(clk),
+  .fullSpeedBitRate(sendPacketCPFSRate),
+  .fullSpeedPolarity(sendPacketCPFSPol),
+  .grabLineControl(sendPacketCPGrabLine),
+  .preAmbleEnable(preAmbleEnable),
+  .rst(rst),
+  .sendPacketCPReady(sendPacketCPReadyOut),
+  .sendPacketCPWEn(sendPacketCPWEnIn),
+  .sendPacketPID(sendPacketCPPIDOut),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+  (.HCTxPortCntl(sendPacketCntl),
+  .HCTxPortData(sendPacketData),
+  .HCTxPortGnt(sendPacketGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(sendPacketReq),
+  .HCTxPortWEn(sendPacketWEn),
+  .PID(sendPacketCPPIDOut),
+  .TxAddr(TxAddr),
+  .TxEndP(TxEndP),
+  .clk(clk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .frameNum(frameNum),
+  .rst(rst),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut) );
+  
+directControl u_directControl
+  (.HCTxPortCntl(directCntlCntl),
+  .HCTxPortData(directCntlData),
+  .HCTxPortGnt(directCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(directCntlReq),
+  .HCTxPortWEn(directCntlWEn),
+  .clk(clk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rst) ); 
+
+HCTxPortArbiter u_HCTxPortArbiter
+  (.HCTxPortCntl(HCTxPortCtrl),
+  .HCTxPortData(HCTxPortData),
+  .HCTxPortWEnable(HCTxPortEn),
+  .SOFCntlCntl(SOFCntlCntl),
+  .SOFCntlData(SOFCntlData),
+  .SOFCntlGnt(SOFCntlGnt),
+  .SOFCntlReq(SOFCntlReq),
+  .SOFCntlWEn(SOFCntlWEn),
+  .clk(clk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rst),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+getPacket u_getPacket
+  (.RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXPktStatus(RxPktStatus),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .clk(clk),
+  .getPacketEn(getPacketREn),
+  .rst(rst) ); 
+
+speedCtrlMux u_speedCtrlMux
+  (.directCtrlRate(directCtrlRate),
+  .directCtrlPol(directCtrlPol),
+  .sendPacketRate(sendPacketCPFSRate),
+  .sendPacketPol(sendPacketCPFSPol),
+  .sendPacketSel(sendPacketCPGrabLine),
+  .fullSpeedRate(fullSpeedRate),
+  .fullSpeedPol(fullSpeedPol) );
+
+rxStatusMonitor  u_rxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .connectionEventOut(connectionEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(clk),
+  .rst(rst)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbHostControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbHostControl_h.v	(revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v                                          
+// $Id: usbHostControl_h.v,v 1.3 2004-12-31 14:40:42 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:57  sfielding
+// Created
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+ 
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants 
+//`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval
+`define SOF_TX_TIME 16'hbb80     //Correct SOF interval for 48MHz clock
+//`define SOF_TX_MARGIN 2 
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+       
+//Host RXStatusRegIndices 
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined 

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.asf	(revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processRxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: processRxByte.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+OBJECTS
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+S 286 50 73728 ELLIPSE "States" | 54701,94283 6500 6500
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+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "CHK_ST\n/0/"
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
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+A 295 293 4 TEXT "Actions" | 114075,218259 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC16Result != 16'hb001)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    RxDataOut <= RxByte;\n    RxCtrlOut <= `RX_PACKET_STREAM;\n    CRCData <= RxByte;\n    CRC16En <= 1'b1;\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 294 293 0 TEXT "State Labels" | 79792,157415 1 0 0 "CHK_STRM\n/12/"
+S 293 50 77824 ELLIPSE "States" | 79792,157415 6500 6500
+I 292 50 0 Builtin Entry | 33692,252435
+I 291 50 0 Builtin Exit | 90483,62922
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+W 288 50 0 293 286 BEZIER "Transitions" | 76852,151619 72082,138383 61585,113663 56815,100427
+S 16 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115714,123462 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 18 17 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 109233,155402 6500 6500
+L 19 18 0 TEXT "State Labels" | 109233,155402 1 0 0 "FIRST_BYTE"
+I 20 17 0 Builtin Entry | 45216,248076
+I 21 17 0 Builtin Exit | 89220,92674
+S 24 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115892,94696 6500 6500
+L 25 24 0 TEXT "State Labels" | 115892,94696 1 0 0 "HSHAKE"
+A 296 0 1 TEXT "Actions" | 13933,264927 1 0 0 "always @\n(next_CRCError or next_bitStuffError or\n next_RxOverflow or next_NAKRxed or \n next_stallRxed or next_ACKRxed or \n next_dataSequence)\nbegin	\n  RxStatus <= \n  {1'b0, next_dataSequence, \n  next_ACKRxed, \n  next_stallRxed, next_NAKRxed, \n  next_RxOverflow, \n  next_bitStuffError, next_CRCError };\nend"
+L 297 298 0 TEXT "Labels" | 82848,260279 1 0 0 "RxDataOut[7:0]"
+I 298 0 130 Builtin OutPort | 76848,260279 "" ""
+L 299 300 0 TEXT "Labels" | 82848,255265 1 0 0 "RxCtrlOut[7:0]"
+I 300 0 130 Builtin OutPort | 76848,255265 "" ""
+L 301 302 0 TEXT "Labels" | 82139,250245 1 0 0 "RxDataOutWEn"
+I 302 0 2 Builtin OutPort | 76139,250245 "" ""
+L 303 304 0 TEXT "Labels" | 84462,243195 1 0 0 "RxByteIn[7:0]"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 17144,15700 201644,263700
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+W 36 41 0 38 371 BEZIER "Transitions" | 34704,258592 38731,254357 47806,246433 31745,235718
+I 37 41 0 Builtin Exit | 85286,98575
+I 38 41 0 Builtin Entry | 30541,258592
+L 39 40 0 TEXT "State Labels" | 74595,193068 1 0 0 "CHK_STRM\n/9/"
+S 40 41 65536 ELLIPSE "States" | 74595,193068 6500 6500
+S 42 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118750,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 118750,36808 1 0 0 "DATA"
+I 304 0 130 Builtin InPort | 78462,243195 "" ""
+L 305 306 0 TEXT "Labels" | 84465,238172 1 0 0 "RxCtrlIn[7:0]"
+I 306 0 130 Builtin InPort | 78465,238172 "" ""
+L 307 308 0 TEXT "Labels" | 85176,232428 1 0 0 "processRxDataInWEn"
+I 308 0 2 Builtin InPort | 78462,232428 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
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+                                      43934,98582 46882,94562 55190,93624 63498,92686\
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+                                      109579,93150
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+                                      44470,65484 48490,63876 56999,63474 65508,63072\
+                                      95524,63072 103095,63072 110666,63072 111053,63134\
+                                      111187,63134
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+                                      45676,39220 48892,34396 57535,33391 66178,32386\
+                                      96662,35330 112340,35732
+C 55 51 0 TEXT "Conditions" | 43455,121392 1 0 0 "RXByteStMachCurrState == `CHECK_PID_ST"
+C 56 52 0 TEXT "Conditions" | 45596,90880 1 0 0 "RXByteStMachCurrState == `HS_BYTE_ST"
+C 57 53 0 TEXT "Conditions" | 45420,58426 1 0 0 "RXByteStMachCurrState == `TOKEN_BYTE_ST"
+C 58 54 0 TEXT "Conditions" | 46403,31524 1 0 0 "RXByteStMachCurrState == `DATA_BYTE_ST"
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "WAIT_BYTE\n/2/"
+S 63 6 24576 ELLIPSE "States" | 112744,173179 6500 6500
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 324 0 130 Builtin InPort | 126267,236303 "" ""
+L 325 326 0 TEXT "Labels" | 175074,265120 1 0 0 "bitStuffError"
+I 326 0 2 Builtin Signal | 172074,265120 "" ""
+L 327 328 0 TEXT "Labels" | 175074,260836 1 0 0 "RxOverflow"
+I 328 0 2 Builtin Signal | 172074,260836 "" ""
+L 329 330 0 TEXT "Labels" | 175074,256552 1 0 0 "RxTimeOut"
+I 330 0 2 Builtin Signal | 172074,256552 "" ""
+L 331 332 0 TEXT "Labels" | 174717,252268 1 0 0 "NAKRxed"
+I 332 0 2 Builtin Signal | 171717,252268 "" ""
+L 333 334 0 TEXT "Labels" | 175074,247627 1 0 0 "stallRxed"
+I 334 0 2 Builtin Signal | 172074,247627 "" ""
+L 335 336 0 TEXT "Labels" | 175074,243343 1 0 0 "ACKRxed"
+W 64 6 0 9 63 BEZIER "Transitions" | 48012,197411 59579,195797 95649,181504 106856,175930
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59763,178747 47927,176730
+C 66 65 0 TEXT "Conditions" | 62843,168563 1 0 0 "processRxDataInWEn == 1'b1"
+W 68 6 0 16 357 BEZIER "Transitions" | 120926,119581 130781,111751 152663,94796 162518,86966
+W 69 6 0 24 357 BEZIER "Transitions" | 122281,93503 131596,91478 152599,87697 161914,85672
+W 71 6 0 33 357 BEZIER "Transitions" | 123360,67490 132540,71405 152828,79824 162008,83739
+W 72 6 0 42 357 BEZIER "Transitions" | 123133,41607 132448,51732 153635,72170 162950,82295
+L 74 75 0 TEXT "State Labels" | 65748,212778 1 0 0 "DO_CHK\n/5/"
+S 75 17 45056 ELLIPSE "States" | 65748,212778 6500 6500
+W 76 17 8194 75 18 BEZIER "Transitions" | 69849,207737 75657,200807 99461,167483 105269,160553
+A 78 65 16 TEXT "Actions" | 51039,182627 1 0 0 "RxByte <= RxByteIn;\nRxCtrl <= RxCtrlIn;\nprocessRxByteRdy <= 1'b0;"
+I 336 0 2 Builtin Signal | 172074,243343 "" ""
+L 337 338 0 TEXT "Labels" | 175074,238702 1 0 0 "dataSequence"
+I 338 0 2 Builtin Signal | 172074,238702 "" ""
+L 341 342 0 TEXT "Labels" | 174929,216623 1 0 0 "RxByte[7:0]"
+I 342 0 130 Builtin Signal | 171929,216623 "" ""
+L 343 344 0 TEXT "Labels" | 175286,221621 1 0 0 "RxCtrl[7:0]"
+I 344 0 130 Builtin Signal | 172286,221621 "" ""
+L 345 346 0 TEXT "Labels" | 119382,216211 1 0 0 "RXByteStMachCurrState[2:0]"
+I 346 0 130 Builtin Signal | 116382,216211 "" ""
+A 349 9 4 TEXT "Actions" | 143783,207627 1 0 0 "RxByte <= 8'h00;\nRxCtrl <= 8'h00;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nRxTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxDataOut <= 8'h00;\nRxCtrlOut <= 8'h00;\nRxDataOutWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nRXDataByteCnt <= 10'h00;\nprocessRxByteRdy <= 1'b1;"
+W 351 6 0 357 63 BEZIER "Transitions" | 165899,88318 165621,91424 166582,101426 164321,105232\
+                                        162060,109038 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 135270,157360\
+                                        132480,162850 129690,168340 122852,170455 118982,171355
+L 339 340 0 TEXT "Labels" | 175498,229252 1 0 0 "RxStatus[7:0]"
+I 340 0 128 Builtin Signal | 172498,229252 "" ""
+W 361 358 0 359 360 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+I 360 358 0 Builtin Exit | 129540,111760
+I 359 358 0 Builtin Entry | 86360,167640
+H 358 357 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 357 6 81940 ELLIPSE "Junction" | 165320,84870 3500 3500
+L 356 357 0 TEXT "State Labels" | 165320,84870 1 0 0 "J1"
+W 82 17 4097 75 21 BEZIER "Transitions" | 63199,206800 60009,197085 40708,156469 41288,147696\
+                                          41868,138924 51896,113272 59871,108777 67846,104282\
+                                          74724,97474 86324,92674
+W 81 17 0 20 75 BEZIER "Transitions" | 49379,248076 53439,241189 58262,225186 62322,218299
+L 352 353 0 TEXT "Labels" | 175356,234668 1 0 0 "CRCError"
+I 353 0 2 Builtin Signal | 172356,234668 "" ""
+L 354 355 0 TEXT "Labels" | 80612,216204 1 0 0 "RXDataByteCnt[9:0]"
+I 355 0 130 Builtin Signal | 77612,216204 "" ""
+L 366 367 0 TEXT "Labels" | 80453,221558 1 0 0 "Signal1"
+I 367 0 2 Builtin Signal | 77453,221558 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+L 381 382 0 TEXT "Labels" | 84990,227664 1 0 0 "processRxByteRdy"
+L 368 369 0 TEXT "Labels" | 132404,226868 1 0 0 "CRC5UpdateRdy"
+I 369 0 2 Builtin InPort | 126404,226868 "" ""
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
+W 372 41 0 371 40 BEZIER "Transitions" | 35330,224745 46935,215765 58540,206785 70145,197805
+C 373 372 0 TEXT "Conditions" | 40381,225556 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 374 375 0 TEXT "Labels" | 132404,222116 1 0 0 "CRC16UpdateRdy"
+I 375 0 2 Builtin InPort | 126404,222116 "" ""
+L 376 377 0 TEXT "State Labels" | 76540,228660 1 0 0 "WAIT_CRC\n/14/"
+S 377 50 90112 ELLIPSE "States" | 76540,228660 6500 6500
+W 378 50 0 292 377 BEZIER "Transitions" | 37855,252435 46562,247168 62458,237581 71165,232314
+W 379 50 0 377 293 BEZIER "Transitions" | 76802,222169 77769,207119 78297,178932 79264,163882
+C 380 379 0 TEXT "Conditions" | 39560,213610 1 0 0 "CRC16UpdateRdy == 1'b1"
+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC5Result != 5'h6)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    if (RXDataByteCnt > 10'h2) \n    begin\n      RxOverflow <= 1'b1;\n      RxDataOut <= RxStatus;\n      RxCtrlOut <= `RX_PACKET_STOP;\n      RXByteStMachCurrState <= `IDLE_BYTE_ST;\n    end\n    else \n    begin\n      RxDataOut <= RxByte;\n      RxCtrlOut <= `RX_PACKET_STREAM;\n      CRCData <= RxByte;\n      CRC5_8Bit <= 1'b1;\n      CRC5En <= 1'b1;\n    end\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+I 220 217 0 Builtin Entry | 86360,167640
+I 221 217 0 Builtin Exit | 136710,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+I 227 224 0 Builtin Entry | 86360,167640
+I 228 224 0 Builtin Exit | 129540,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n  RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n  RXByteStMachCurrState = `IDLE_BYTE_ST;"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n  RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n  `SPECIAL:                              //Special PID.\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  `TOKEN:                                //Token PID\n  begin\n    RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\n  `HANDSHAKE:                            //Handshake PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        ACKRxed <= 1'b1;\n      2'b10:\n        NAKRxed <= 1'b1;\n      2'b11:\n        stallRxed <= 1'b1;\n      default:\n      begin\n        $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n      end\n    endcase\n    RXByteStMachCurrState <= `HS_BYTE_ST;\n  end\n  `DATA:                                  //Data PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        dataSequence <= 1'b0;\n      2'b10:\n        dataSequence <= 1'b1;\n      default:\n        $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n    endcase\n    RXByteStMachCurrState <= `DATA_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\nendcase"
+I 252 248 0 Builtin Entry | 35384,229000
+I 253 248 0 Builtin Exit | 78564,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+                                          110499,87996 110355,80840 110355,80474
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n  RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+I 260 32 0 Builtin Exit | 110355,78302
+I 259 32 0 Builtin Entry | 66351,233704
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+                                        89364,102368 89220,95212 89220,94846
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/readUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/readUSBWireData.v	(revision 264)
@@ -0,0 +1,203 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// readUSBWireData.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: readUSBWireData.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:01  sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
+input   [1:0] RxBitsIn;
+output  RxDataInTick;
+input   SIERxRdyIn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+input   disableWireRead;
+output  [1:0] RxBitsOut;
+output  SIERxWEn;
+
+wire   [1:0] RxBitsIn;
+reg    RxDataInTick;
+wire   SIERxRdyIn;
+wire   clk;
+wire   fullSpeedRate;
+wire   rst;
+reg    [1:0] RxBitsOut;
+reg    SIERxWEn;
+
+// local registers
+reg  [1:0]buffer0;
+reg  [1:0]buffer1;
+reg  [1:0]buffer2;
+reg  [1:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg  [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 2'b00;
+    buffer1 <= 2'b00;
+    buffer2 <= 2'b00;
+    buffer3 <= 2'b00;
+    RxDataInTick <= 1'b0;
+  end
+  else begin
+    RxBitsInReg <= RxBitsIn;      //sync to local clock to avoid metastability issues
+    incBufferCnt <= 1'b0;         //default value
+    oldRxBitsIn <= RxBitsInReg;
+    if (oldRxBitsIn != RxBitsInReg)  //if edge detected then
+      i <= 5'b00000;              //reset the counter
+    else
+      i <= i + 1'b1;
+    if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+    begin
+      RxDataInTick <= !RxDataInTick;
+      if (disableWireRead != 1'b1)  //do not read wire data when transmitter is active
+      begin
+        incBufferCnt <= 1'b1;
+        bufferInIndex <= bufferInIndex + 1'b1;
+        case (bufferInIndex)
+          2'b00 : buffer0 <= RxBitsInReg;
+          2'b01 : buffer1 <= RxBitsInReg;
+          2'b10 : buffer2 <= RxBitsInReg;
+          2'b11 : buffer3 <= RxBitsInReg;
+        endcase
+      end
+    end
+  end
+end
+
+        
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    decBufferCnt <= 1'b0;
+    bufferOutIndex <= 2'b00;
+    RxBitsOut <= 2'b00;
+    SIERxWEn <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+  end
+  else begin
+    case (bufferOutStMachCurrState)
+      `WAIT_BUFFER_NOT_EMPTY:
+      begin
+        if (bufferCnt != 3'b000)
+          bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+      end
+      `WAIT_SIE_RX_READY:
+      begin
+        if (SIERxRdyIn == 1'b1)
+        begin 
+          SIERxWEn <= 1'b1;
+          bufferOutStMachCurrState <= `SIE_RX_WRITE;
+          decBufferCnt <= 1'b1;
+          bufferOutIndex <= bufferOutIndex + 1'b1;
+          case (bufferOutIndex)
+            2'b00 :  RxBitsOut <= buffer0;
+            2'b01 : RxBitsOut <= buffer1;
+            2'b10 : RxBitsOut <= buffer2;
+            2'b11 : RxBitsOut <= buffer3;
+          endcase
+        end
+      end
+      `SIE_RX_WRITE:
+      begin
+        SIERxWEn <= 1'b0;
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+      end
+    endcase
+  end
+end
+
+      
+
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC5.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC5.v	(revision 264)
@@ -0,0 +1,120 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC5.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: updateCRC5.v,v 1.2 2004-12-18 14:36:16 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:04  sfielding
+// Created
+//
+//
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   CRC5_8BitIn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [4:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   CRC5_8BitIn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 5'h1f;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0) begin
+      if (CRCEn == 1'b1) begin
+        ready <= 1'b0;
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        if (CRC5_8BitIn == 1'b1) begin
+          loopEnd <= 4'h7; 
+        end
+        else begin
+          loopEnd <= 4'h2;
+        end
+      end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[4:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == loopEnd) begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v	(revision 264)
@@ -0,0 +1,311 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// writeUSBWireData.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: writeUSBWireData.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:05  sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL  3'b100
+
+module writeUSBWireData (
+  TxBitsIn, 
+  TxBitsOut,
+   TxDataOutTick,
+  TxCtrlIn, 
+  TxCtrlOut, 
+  USBWireRdy,
+  USBWireWEn, 
+  disableWireReadOut, 
+  fullSpeedRate, 
+  clk, 
+  rst,
+  noActivityTimeOut );
+  
+input   [1:0] TxBitsIn;
+input   TxCtrlIn;
+input   USBWireWEn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+output  [1:0] TxBitsOut;
+output TxDataOutTick;
+output  TxCtrlOut;
+output  USBWireRdy;
+output  disableWireReadOut;
+output noActivityTimeOut;
+
+wire    [1:0] TxBitsIn;
+reg     [1:0] TxBitsOut;
+reg     TxDataOutTick;
+wire    TxCtrlIn;
+reg     TxCtrlOut;
+reg     USBWireRdy;
+wire    USBWireWEn;
+wire    clk;
+wire    fullSpeedRate;
+wire    rst;
+reg  disableWireReadOut;
+reg noActivityTimeOut;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+reg [15:0] timeOutCnt;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else
+  begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+//buffer input state machine 
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+     incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    USBWireRdy <= 1'b0;
+    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+  end
+  else begin
+    case (bufferInStMachCurrState)
+      `WAIT_BUFFER_NOT_FULL:
+      begin
+        if (bufferCnt != `BUFFER_FULL)  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+      end
+      `WAIT_WRITE_REQ:
+      begin
+        if (USBWireWEn == 1'b1)
+        begin
+          incBufferCnt <= 1'b1;
+          USBWireRdy <= 1'b0;
+          bufferInIndex <= bufferInIndex + 1'b1;
+          case (bufferInIndex)
+            2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+            2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+            2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+            2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+          endcase
+          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+        end
+      end
+      `CLR_INC_BUFFER_CNT:
+      begin
+        incBufferCnt <= 1'b0;
+        if (bufferCnt != (`BUFFER_FULL - 1'b1) )  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+        else begin
+          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+        end
+      end
+    endcase
+  end
+end
+        
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    fullSpeedTick <= 1'b0;
+    lowSpeedTick <= 1'b0;
+  end
+  else
+  begin
+    i <= i + 1'b1;
+    if (i[1:0] == 2'b00)
+      fullSpeedTick <= 1'b1;
+    else
+      fullSpeedTick <= 1'b0; 
+    if (i == 5'b00000)
+      lowSpeedTick <= 1'b1;
+    else
+      lowSpeedTick <= 1'b0;
+  end
+end
+
+//buffer output state machine
+//After reset, waits for the output buffer to become full.
+//Once the buffer is full then it is constantly emptied at either
+//the full or low speed rate with no under run protection
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferOutIndex <= 2'b00;
+    decBufferCnt <= 1'b0;
+    TxBitsOut <= 2'b00;
+    TxCtrlOut <= `TRI_STATE;
+    TxDataOutTick <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_BUFFER_FULL;
+  end
+  else
+  begin
+    case (bufferOutStMachCurrState)
+      `WAIT_BUFFER_FULL:
+      begin
+        if (bufferCnt == `BUFFER_FULL)
+          bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+      end
+      `WAIT_LINE_WRITE:
+      begin
+        if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+        begin
+          TxDataOutTick <= !TxDataOutTick;
+          bufferOutStMachCurrState <= `LINE_WRITE;
+          decBufferCnt <= 1'b1;
+          bufferOutIndex <= bufferOutIndex + 1'b1;
+          case (bufferOutIndex)
+            2'b00 :
+          begin 
+            TxBitsOut <= buffer0[2:1];
+            TxCtrlOut <= buffer0[0];
+          end
+          2'b01 : 
+          begin
+            TxBitsOut <= buffer1[2:1];
+            TxCtrlOut <= buffer1[0];
+          end
+          2'b10 : 
+          begin 
+            TxBitsOut <= buffer2[2:1];
+            TxCtrlOut <= buffer2[0];
+          end
+          2'b11 : 
+          begin
+            TxBitsOut <= buffer3[2:1];
+            TxCtrlOut <= buffer3[0];
+          end
+          endcase
+        end
+      end
+      `LINE_WRITE:
+      begin
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+      end
+    endcase
+  end
+end
+
+// control 'disableWireReadOut' 
+always @(TxCtrlOut)
+begin  
+  if (TxCtrlOut == `DRIVE)
+    disableWireReadOut <= 1'b1;
+  else
+    disableWireReadOut <= 1'b0;
+end
+
+//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks
+always @(posedge clk) begin
+  if (rst) begin
+    timeOutCnt <= 16'h0000;
+    noActivityTimeOut <= 1'b0;
+  end
+  else begin
+    if (TxCtrlOut == `DRIVE)
+      timeOutCnt <= 16'h0000;
+    else 
+      timeOutCnt <= timeOutCnt + 1'b1;
+    //if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
+    if (timeOutCnt == 16'h200)  //temporary fix
+      noActivityTimeOut <= 1'b1;
+    else
+      noActivityTimeOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbConstants_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbConstants_h.v	(revision 264)
@@ -0,0 +1,40 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v                                             
+//
+// $Id: usbConstants_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:57  sfielding
+// Created
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc 
+     
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined       
+

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/wishBoneBus_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/wishBoneBus_h.v	(revision 264)
@@ -0,0 +1,42 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v                                              
+// $Id: wishBoneBus_h.v,v 1.2 2004-12-18 14:36:13 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:57  sfielding
+// Created
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+ 
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v	(revision 264)
@@ -0,0 +1,85 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// lineControlUpdate.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: lineControlUpdate.v,v 1.2 2004-12-18 14:36:15 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:00:57  sfielding
+// Created
+//
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+    if (fullSpeedPolarity == 1'b1)
+  begin
+      JBit = `ONE_ZERO;
+      KBit = `ZERO_ONE;
+    end
+    else
+  begin
+      JBit = `ZERO_ONE;
+      KBit = `ONE_ZERO;
+    end
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.v	(revision 264)
@@ -0,0 +1,504 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processRxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: processRxByte.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   processRxDataInWEn;
+input   rst;
+input   [7:0]RxByteIn;
+input   [7:0]RxCtrlIn;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processRxByteRdy;
+output  rstCRC;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+output  RxDataOutWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+reg     processRxByteRdy, next_processRxByteRdy;
+wire    processRxDataInWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]RxByteIn;
+wire    [7:0]RxCtrlIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+reg     RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RxByte, next_RxByte;
+reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg  [7:0]RxCtrl, next_RxCtrl;
+reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg  [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+  NextState_prRxByte <= CurrState_prRxByte;
+  // Set default values for outputs and signals
+  next_RxByte <= RxByte;
+  next_RxCtrl <= RxCtrl;
+  next_RXByteStMachCurrState <= RXByteStMachCurrState;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RxOverflow <= RxOverflow;
+  next_RxTimeOut <= RxTimeOut;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_RxDataOut <= RxDataOut;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOutWEn <= RxDataOutWEn;
+  next_rstCRC <= rstCRC;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_RXDataByteCnt <= RXDataByteCnt;
+  next_processRxByteRdy <= processRxByteRdy;
+  case (CurrState_prRxByte)  // synopsys parallel_case full_case
+    `CHK_ST:
+    begin
+      if (RXByteStMachCurrState == `HS_BYTE_ST)
+      begin
+        NextState_prRxByte <= `HSHAKE_CHK;
+      end
+      else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+      begin
+        NextState_prRxByte <= `TOKEN_WAIT_CRC;
+      end
+      else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+      begin
+        NextState_prRxByte <= `DATA_WAIT_CRC;
+      end
+      else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+      begin
+        NextState_prRxByte <= `IDLE_CHK_START;
+      end
+      else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+      begin
+        NextState_prRxByte <= `CHK_SYNC_DO;
+      end
+      else if (RXByteStMachCurrState == `CHECK_PID_ST)
+      begin
+        NextState_prRxByte <= `CHK_PID_DO_CHK;
+      end
+    end
+    `START_PRBY:
+    begin
+      next_RxByte <= 8'h00;
+      next_RxCtrl <= 8'h00;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RxOverflow <= 1'b0;
+      next_RxTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_RxDataOut <= 8'h00;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOutWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_RXDataByteCnt <= 10'h00;
+      next_processRxByteRdy <= 1'b1;
+      NextState_prRxByte <= `WAIT_BYTE;
+    end
+    `WAIT_BYTE:
+    begin
+      if (processRxDataInWEn == 1'b1)
+      begin
+        NextState_prRxByte <= `CHK_ST;
+        next_RxByte <= RxByteIn;
+        next_RxCtrl <= RxCtrlIn;
+        next_processRxByteRdy <= 1'b0;
+      end
+    end
+    `HSHAKE_FIN:
+    begin
+      next_RxDataOutWEn <= 1'b0;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `HSHAKE_CHK:
+    begin
+      NextState_prRxByte <= `HSHAKE_FIN;
+      if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RxDataOutWEn <= 1'b1;
+    end
+    `CHK_PID_DO_CHK:
+    begin
+      if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+      begin
+        NextState_prRxByte <= `WAIT_BYTE;
+        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+        next_processRxByteRdy <= 1'b1;
+      end
+      else
+      begin
+        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+        next_CRCError <= 1'b0;
+        next_bitStuffError <= 1'b0;
+        next_RxOverflow <= 1'b0;
+        next_NAKRxed <= 1'b0;
+        next_stallRxed <= 1'b0;
+        next_ACKRxed <= 1'b0;
+        next_dataSequence <= 1'b0;
+        next_RxTimeOut <= 1'b0;
+        next_RXDataByteCnt <= 0;
+        next_RxDataOut <= RxByte;
+        next_RxCtrlOut <= `RX_PACKET_START;
+        next_RxDataOutWEn <= 1'b1;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `CHK_PID_FIRST_BYTE_PROC:
+    begin
+      next_rstCRC <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      case (RxByte[1:0] )
+      `SPECIAL:                              //Special PID.
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      `TOKEN:                                //Token PID
+      begin
+      next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      `HANDSHAKE:                            //Handshake PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_ACKRxed <= 1'b1;
+      2'b10:
+      next_NAKRxed <= 1'b1;
+      2'b11:
+      next_stallRxed <= 1'b1;
+      default:
+      begin
+      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+      end
+      endcase
+      next_RXByteStMachCurrState <= `HS_BYTE_ST;
+      end
+      `DATA:                                  //Data PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_dataSequence <= 1'b0;
+      2'b10:
+      next_dataSequence <= 1'b1;
+      default:
+      $display ("Invalid DATA PID detected in ProcessRXByte\n");
+      endcase
+      next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      endcase
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_FIN:
+    begin
+      next_CRC16En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC16Result != 16'hb001)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC16En <= 1'b1;
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `DATA_FIN;
+    end
+    `DATA_WAIT_CRC:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `DATA_CHK_STRM;
+      end
+    end
+    `TOKEN_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC5Result != 5'h6)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      if (RXDataByteCnt > 10'h2)
+      begin
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      else
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      end
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `TOKEN_FIN;
+    end
+    `TOKEN_FIN:
+    begin
+      next_CRC5En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `TOKEN_WAIT_CRC:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `TOKEN_CHK_STRM;
+      end
+    end
+    `CHK_SYNC_DO:
+    begin
+      if (RxByte == `SYNC_BYTE)
+      next_RXByteStMachCurrState <= `CHECK_PID_ST;
+      else
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `IDLE_CHK_START:
+    begin
+      if (RxCtrl == `DATA_START)
+      next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxByte <= `START_PRBY;
+  else
+    CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RxDataOut <= 8'h00;
+    RxCtrlOut <= 8'h00;
+    RxDataOutWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    processRxByteRdy <= 1'b1;
+    RxByte <= 8'h00;
+    RxCtrl <= 8'h00;
+    RXByteStMachCurrState <= `IDLE_BYTE_ST;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RxOverflow <= 1'b0;
+    RxTimeOut <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    RXDataByteCnt <= 10'h00;
+  end
+  else 
+  begin
+    RxDataOut <= next_RxDataOut;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOutWEn <= next_RxDataOutWEn;
+    rstCRC <= next_rstCRC;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    processRxByteRdy <= next_processRxByteRdy;
+    RxByte <= next_RxByte;
+    RxCtrl <= next_RxCtrl;
+    RXByteStMachCurrState <= next_RXByteStMachCurrState;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RxOverflow <= next_RxOverflow;
+    RxTimeOut <= next_RxTimeOut;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    RXDataByteCnt <= next_RXDataByteCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf	(revision 264)
@@ -0,0 +1,614 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=955
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIETransmitter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: SIETransmitter.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
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+W 555 458 0 543 534 BEZIER "Transitions" | 69825,102352 80940,102469 155253,103091 166368,103208
+A 554 534 4 TEXT "Actions" | 157773,116901 1 0 0 "USBWireWEn <= 1'b0;"
+C 553 549 0 TEXT "Conditions" | 134841,94437 1 0 0 "USBWireRdy == 1'b1"
+C 552 547 0 TEXT "Conditions" | 72597,69165 1 0 0 "USBWireRdy == 1'b1"
+A 550 549 16 TEXT "Actions" | 89913,93969 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 549 458 0 534 532 BEZIER "Transitions" | 166590,101641 155007,95674 81782,81027 70199,75060
+A 548 547 16 TEXT "Actions" | 109101,76185 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 547 458 0 532 530 BEZIER "Transitions" | 71250,71190 82482,70839 157007,69015 168239,68664
+L 544 543 0 TEXT "State Labels" | 63328,102539 1 0 0 "WAIT_WIRE\n/47/"
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "SIETx"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: SIETransmitter"
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "STX_CHK_ST\n/23/"
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+I 12 6 0 Builtin Reset | 22016,204762
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+L 15 16 0 TEXT "State Labels" | 115356,124706 1 0 0 "RES_ST"
+I 816 0 2 Builtin OutPort | 64372,260578 "" ""
+L 817 818 0 TEXT "Labels" | 72692,255938 1 0 0 "processTxByteRdy"
+I 818 0 2 Builtin InPort | 66692,255938 "" ""
+L 819 820 0 TEXT "Labels" | 70372,251298 1 0 0 "TxByteOut[7:0]"
+I 820 0 130 Builtin OutPort | 64372,251298 "" ""
+L 821 822 0 TEXT "Labels" | 70372,246658 1 0 0 "TxByteOutCtrl[7:0]"
+I 822 0 130 Builtin OutPort | 64372,246658 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+A 835 9 4 TEXT "Actions" | 153876,205564 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 5'h0;"
+W 574 458 0 567 543 BEZIER "Transitions" | 44298,153135 48358,141709 56556,119871 60616,108445
+A 563 530 4 TEXT "Actions" | 161517,83673 1 0 0 "USBWireWEn <= 1'b0;"
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+I 572 458 0 Builtin Entry | 44780,253519
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/5/"
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/37/"
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+A 562 532 4 TEXT "Actions" | 37965,60741 1 0 0 "USBWireWEn <= 1'b0;"
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+A 836 63 4 TEXT "Actions" | 101212,188184 1 0 0 "SIEPortTxRdy <= 1'b1;"
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+I 838 0 130 Builtin Signal | 71732,224652 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 840 0 130 Builtin Signal | 71500,220244 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[4:0]"
+I 844 0 130 Builtin Signal | 71500,215836 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+I 872 360 0 Builtin Exit | 188676,86316
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+                                      42326,129670 44202,125650 52711,124511 61220,123372\
+                                      92777,123293 108857,123025
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "STX_WAIT_BYTE\n/24/"
+S 63 6 0 ELLIPSE "States" | 112744,173179 6500 6500
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 324 0 130 Builtin InPort | 126267,236303 "" ""
+I 599 489 0 Builtin Entry | 81144,219546
+I 606 489 0 Builtin Exit | 138120,51311
+W 895 224 8194 891 897 BEZIER "Transitions" | 101794,119505 95833,118125 85494,117151 81290,118312\
+                                              77086,119473 72191,126878 71751,132901 71312,138925\
+                                              74451,155618 76866,160637 79282,165657 85808,169046\
+                                              89165,169297 92522,169548 98692,166980 102143,165788
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 5'h7"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/2/"
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 890 885 0 TEXT "State Labels" | 60832,129059 1 0 0 "CHK_FIN\n/1/"
+C 889 888 0 TEXT "Conditions" | 62558,122269 1 0 0 "i == 5'h7"
+W 888 217 8193 885 221 BEZIER "Transitions" | 60935,122562 61052,115893 61713,104679 61830,98010
+W 887 217 8194 885 883 BEZIER "Transitions" | 54752,126763 48791,125383 38452,124409 34248,125570\
+                                              30044,126731 25149,134136 24709,140159 24270,146183\
+                                              27409,162876 29824,167895 32240,172915 38766,176304\
+                                              42123,176555 45480,176806 51650,174238 55101,173046
+A 886 885 4 TEXT "Actions" | 76742,138579 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 885 217 0 ELLIPSE "States" | 60832,129059 6500 6500
+L 884 883 0 TEXT "State Labels" | 60901,170112 1 0 0 "STX_WAIT_RDY\n/26/"
+S 883 217 0 ELLIPSE "States" | 60901,170112 6500 6500
+C 882 880 0 TEXT "Conditions" | 61330,163577 1 0 0 "USBWireRdy == 1'b1"
+A 881 880 16 TEXT "Actions" | 49805,157344 1 0 0 "USBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 880 217 0 883 885 BEZIER "Transitions" | 60836,163644 60774,157457 60714,141730 60652,135543
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59299,174571 47927,176730
+C 66 65 0 TEXT "Conditions" | 67688,166172 1 0 0 "SIEPortWEn == 1'b1"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+A 78 65 16 TEXT "Actions" | 54348,179673 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+                                        161730,108850 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 135270,157360\
+                                        132480,162850 129690,168340 122852,170455 118982,171355
+L 608 609 0 TEXT "State Labels" | 111818,198264 1 0 0 "PID"
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111818,198264 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114123,147554 6500 6500
+I 909 224 0 Builtin Exit | 108872,88817
+I 908 224 0 Builtin Entry | 85162,237767
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/33/"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/43/"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+                                        43361,99065 46384,95576 54928,94878 63472,94181\
+                                        94207,96080 109784,96428
+I 363 360 0 Builtin Entry | 47792,257148
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 68542,191838 89078,185356 109614,178874
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 114123,147554 1 0 0 "BYTE1"
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112740,88546 6500 6500
+L 634 626 0 TEXT "State Labels" | 112740,88546 1 0 0 "CRC"
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 636 610 0 Builtin Entry | 71380,236621
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+W 927 360 0 933 929 BEZIER "Transitions" | 144010,222256 143885,215969 143879,198227 143754,191940
+C 924 922 0 TEXT "Conditions" | 97818,190135 1 0 0 "USBWireRdy == 1'b1"
+A 923 922 16 TEXT "Actions" | 93859,209922 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit;  \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 922 360 0 929 453 BEZIER "Transitions" | 138043,187612 109537,196045 81451,206574 52945,215007
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+A 920 888 16 TEXT "Actions" | 54464,112031 1 0 0 "USBWireReq <= 1'b0;"
+A 917 371 4 TEXT "Actions" | 71825,218040 1 0 0 "i <= 5'h0;"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 5'h0;"
+C 378 377 0 TEXT "Conditions" | 56860,208360 1 0 0 "USBWireGnt == 1'b1"
+W 377 217 0 371 883 BEZIER "Transitions" | 52975,210241 55849,199016 58723,187790 61597,176565
+A 374 373 16 TEXT "Actions" | 43761,237148 1 0 0 "USBWireReq <= 1'b1;"
+W 373 217 0 220 371 BEZIER "Transitions" | 41882,245025 44900,239618 46527,227520 49545,222113
+S 371 217 0 ELLIPSE "States" | 53178,216725 6500 6500
+L 370 371 0 TEXT "State Labels" | 53178,216725 1 0 0 "STX_WAIT_GNT\n/25/"
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/7/"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/40/"
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 645 610 0 Builtin Exit | 114540,97930
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+W 648 489 0 599 609 BEZIER "Transitions" | 84906,219546 91705,215743 99788,205923 106587,202120
+W 649 489 0 609 617 BEZIER "Transitions" | 111887,191768 112232,181972 113177,163821 113522,154025
+W 650 489 0 617 626 BEZIER "Transitions" | 113848,141065 113272,128964 113115,107129 112539,95028
+W 651 489 0 626 606 BEZIER "Transitions" | 115586,82704 120772,74867 130139,59148 135325,51311
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/29/"
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 913 912 0 Builtin Entry | 86360,167640
+I 914 912 0 Builtin Exit | 129540,111760
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+A 937 453 4 TEXT "Actions" | 60460,224205 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+L 934 933 0 TEXT "State Labels" | 144285,228746 1 0 0 "WAIT_GNT\n/49/"
+S 933 360 12288 ELLIPSE "States" | 144285,228746 6500 6500
+A 932 931 16 TEXT "Actions" | 105661,247407 1 0 0 "USBWireReq <= 1'b1;"
+W 931 360 0 363 933 BEZIER "Transitions" | 51554,257148 80200,248283 109429,239528 138075,230663
+L 930 929 0 TEXT "State Labels" | 144175,185833 1 0 0 "WAIT_RDY_WIRE\n/48/"
+S 929 360 8192 ELLIPSE "States" | 144175,185458 6500 6500
+C 928 927 0 TEXT "Conditions" | 145669,221771 1 0 0 "USBWireGnt == 1'b1"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/31/"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 663 624 0 Builtin Entry | 59190,254840
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+                                           104039,47385 110550,45085 113597,43935
+I 671 624 0 Builtin Exit | 116402,43935
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/50/"
+S 939 633 16384 ELLIPSE "States" | 39277,179580 6500 6500
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;	\ni <= i + 1'b1;"
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/0/"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/38/"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+A 414 413 16 TEXT "Actions" | 50880,235676 1 0 0 "USBWireReq <= 1'b1;\ni <= 5'h0;"
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/42/"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/27/"
+I 682 633 0 Builtin Exit | 119917,39891
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/51/"
+S 947 734 20480 ELLIPSE "States" | 160390,197270 6500 6500
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/52/"
+S 952 624 24576 ELLIPSE "States" | 35474,185224 6500 6500
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "S5\n/17/"
+S 430 17 0 ELLIPSE "States" | 61659,61312 6500 6500
+L 429 430 0 TEXT "State Labels" | 61659,61312 1 0 0 "S4\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "S3\n/15/"
+C 426 425 0 TEXT "Conditions" | 60723,121216 1 0 0 "i == `RESUME_LEN"
+W 425 17 0 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/34/"
+I 417 17 0 Builtin Entry | 44586,243455
+I 418 17 0 Builtin Exit | 145044,30588
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+W 422 17 8194 407 411 BEZIER "Transitions" | 53385,128518 47424,127138 37085,126164 32881,127325\
+                                             28677,128486 23782,135891 23342,141914 22903,147938\
+                                             26042,164631 28457,169650 30873,174670 37399,178059\
+                                             40756,178310 44113,178561 50283,175993 53734,174801
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "S1\n/14/"
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/30/"
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/6/"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/41/"
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 447 438 16 TEXT "Actions" | 92898,48208 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 106002,65992 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 445 436 16 TEXT "Actions" | 86814,83776 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 444 438 0 TEXT "Conditions" | 142974,49612 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 69498,58972 1 0 0 "USBWireRdy == 1'b1"
+C 442 436 0 TEXT "Conditions" | 131742,84244 1 0 0 "USBWireRdy == 1'b1"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+W 438 17 0 432 434 BEZIER "Transitions" | 165378,56758 153093,51025 79495,38601 67210,32868
+W 437 17 0 430 432 BEZIER "Transitions" | 68151,60997 79383,60646 153908,58822 165140,58471
+W 436 17 0 428 430 BEZIER "Transitions" | 163491,91448 151908,85481 78683,70834 67100,64867
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "S6\n/18/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/35/"
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/10/"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251308 41695,240089 71091,229875 69529,218656
+I 711 480 0 Builtin Entry | 43257,253243
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 713 480 0 Builtin Exit | 85376,122104
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 715 471 0 Builtin Exit | 140592,59380
+I 716 471 0 Builtin Entry | 83616,227615
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/46/"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 123646,30705 142249,30588
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34866,50548 1 0 0 "USBWireWEn <= 1'b0;"
+A 448 432 4 TEXT "Actions" | 158418,73480 1 0 0 "USBWireWEn <= 1'b0;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 731 727 0 Builtin Entry | 71380,236621
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/28/"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+I 738 727 0 Builtin Exit | 114540,97930
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/36/"
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+I 744 734 0 Builtin Exit | 116402,43935
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+I 750 734 0 Builtin Entry | 59190,254840
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/3/"
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 220 217 0 Builtin Entry | 38120,245025
+I 221 217 0 Builtin Exit | 61830,96075
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/32/"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+I 762 733 0 Builtin Exit | 119917,39891
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+                                           48829,42592 51359,37532 61605,36267 71852,35002\
+                                           109061,35775 128289,35775
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+                                           48196,74723 50474,70169 60657,69030 70840,67892\
+                                           108432,68626 127660,68626
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+                                           46931,109511 49715,104703 60024,103501 70334,102300\
+                                           108774,103037 128002,103037
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+                                           46299,139871 48829,136075 59202,135063 69575,134052\
+                                           106314,125693 125795,125567
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/8/"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/39/"
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/45/"
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+I 787 733 0 Builtin Entry | 62705,250796
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/4/"
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+                                              31250,150650 32250,89650 34750,72525 37250,55400\
+                                              46250,47900 56000,46150 65750,44400 95896,46012\
+                                              103573,44899 111250,43786 113107,43935 113607,43935
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+                                           128857,67252 162473,65260 171997,66691 181521,68123\
+                                           186003,75843 187123,97692 188244,119542 188244,199222\
+                                           184384,221196 180525,243170 165087,251388 155563,253628\
+                                           146039,255869 123379,256617 115100,254625 106821,252633\
+                                           98206,243956 92977,239599
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+S 530 458 0 ELLIPSE "States" | 174738,68697 6500 6500
+L 531 530 0 TEXT "State Labels" | 174738,68697 1 0 0 "SEND_IDLE3\n/21/"
+S 543 458 0 ELLIPSE "States" | 63328,102539 6500 6500
+I 540 458 0 Builtin Exit | 68103,43333
+L 535 534 0 TEXT "State Labels" | 172866,103329 1 0 0 "SEND_IDLE1\n/19/"
+S 534 458 0 ELLIPSE "States" | 172866,103329 6500 6500
+L 533 532 0 TEXT "State Labels" | 64758,71505 1 0 0 "SEND_IDLE2\n/20/"
+S 532 458 0 ELLIPSE "States" | 64758,71505 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/44/"
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.v	(revision 264)
@@ -0,0 +1,416 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processrxbit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: processRxBit.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut);
+input   clk;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processRxBitsWEn;
+input   processRxByteRdy;
+input   rst;
+input   [1:0]RxBitsIn;
+output  processRxBitRdy;
+output  processRxByteWEn;
+output  resumeDetected;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+
+wire    clk;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processRxBitRdy, next_processRxBitRdy;
+wire    processRxBitsWEn;
+wire    processRxByteRdy;
+reg     processRxByteWEn, next_processRxByteWEn;
+reg     resumeDetected, next_resumeDetected;
+wire    rst;
+wire    [1:0]RxBitsIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg  [1:0]oldRXBits, next_oldRXBits;
+reg  [3:0]resumeWaitCnt, next_resumeWaitCnt;
+reg  [3:0]RXBitCount, next_RXBitCount;
+reg  [1:0]RxBits, next_RxBits;
+reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg  [7:0]RXByte, next_RXByte;
+reg  [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+  NextState_prRxBit <= CurrState_prRxBit;
+  // Set default values for outputs and signals
+  next_processRxByteWEn <= processRxByteWEn;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOut <= RxDataOut;
+  next_resumeDetected <= resumeDetected;
+  next_RXBitStMachCurrState <= RXBitStMachCurrState;
+  next_RxBits <= RxBits;
+  next_RXSameBitCount <= RXSameBitCount;
+  next_RXBitCount <= RXBitCount;
+  next_oldRXBits <= oldRXBits;
+  next_RXByte <= RXByte;
+  next_bitStuffError <= bitStuffError;
+  next_resumeWaitCnt <= resumeWaitCnt;
+  next_processRxBitRdy <= processRxBitRdy;
+  case (CurrState_prRxBit)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOut <= 8'h00;
+      next_resumeDetected <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_RxBits <= 2'b00;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h0;
+      next_oldRXBits <= 2'b00;
+      next_RXByte <= 8'h00;
+      next_bitStuffError <= 1'b0;
+      next_resumeWaitCnt <= 4'h0;
+      next_processRxBitRdy <= 1'b1;
+      NextState_prRxBit <= `WAIT_BITS;
+    end
+    `WAIT_BITS:
+    begin
+      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+      begin
+        NextState_prRxBit <= `RES_RX_CHK;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+      begin
+        NextState_prRxBit <= `DATA_RX_CHK_SE0;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+      begin
+        NextState_prRxBit <= `IDLE_CHK_KBIT;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+      begin
+        NextState_prRxBit <= `RES_END_CHK1;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+    end
+    `IDLE_FIRST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+      next_RXSameBitCount <= 4'h1;
+      next_RXBitCount <= 4'h1;
+      next_oldRXBits <= RxBits;
+      //zero is always the first RZ data bit of a new packet
+      next_RXByte <= 8'h00;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `IDLE_CHK_KBIT:
+    begin
+      if (RxBits == KBit)
+      begin
+        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `IDLE_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `IDLE_FIRST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_START;
+        //start of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_LAST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_CHK_SE0:
+    begin
+      next_bitStuffError <= 1'b0;
+      if (RxBits == `SE0)
+      begin
+        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
+        begin
+        next_RXSameBitCount <= RXSameBitCount + 1'b1;
+        //inc 'RXSameBitCount'
+        if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error
+        next_bitStuffError <= 1'b1;
+        //flag 'bitStuffError'
+        else                                          //else no bit stuffing error
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != 4'h7) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= { 1'b1, RXByte[7:1]};
+        //RZ bit <= 1 (ie no change in 'RxBits')
+        end
+        end
+        else                                            //else current 'RxBits' are different from old 'RxBits'
+        begin
+        if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != 4'h7) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= {1'b0, RXByte[7:1]};
+        //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+        end
+        next_RXSameBitCount <= 4'h1;
+        //reset 'RXSameBitCount'
+        end
+        next_oldRXBits <= RxBits;
+      end
+    end
+    `DATA_RX_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_LAST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_STOP;
+        //end of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_DATA_DESTUFF:
+    begin
+      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+      end
+      else if (bitStuffError == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `DATA_RX_BYTE_SEND2:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_BYTE_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+        next_RXBitCount <= 4'h0;
+        next_RxDataOut <= RXByte;
+        next_RxCtrlOut <= `DATA_STREAM;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_ERROR_CHK_RES:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      if (RxBits == JBit)                           //if current bit is a JBit, then
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      //next state is idle
+      else                                          //else
+      begin
+      next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+      //check for resume
+      next_resumeWaitCnt <= 0;
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_ERROR_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `RES_RX_CHK:
+    begin
+      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      else
+      begin
+      next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+      //if we've waited long enough, then
+      if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
+      begin
+      next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+      next_resumeDetected <= 1'b1;
+      //report resume detected
+      end
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `RES_END_CHK1:
+    begin
+      if (RxBits != KBit)  //line must leave KBit state for the end of resume
+      begin
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_resumeDetected <= 1'b0;
+      //clear resume detected flag
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxBit <= `START;
+  else
+    CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processRxByteWEn <= 1'b0;
+    RxCtrlOut <= 8'h00;
+    RxDataOut <= 8'h00;
+    resumeDetected <= 1'b0;
+    processRxBitRdy <= 1'b1;
+    RXBitStMachCurrState <= `IDLE_BIT_ST;
+    RxBits <= 2'b00;
+    RXSameBitCount <= 4'h0;
+    RXBitCount <= 4'h0;
+    oldRXBits <= 2'b00;
+    RXByte <= 8'h00;
+    bitStuffError <= 1'b0;
+    resumeWaitCnt <= 4'h0;
+  end
+  else 
+  begin
+    processRxByteWEn <= next_processRxByteWEn;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOut <= next_RxDataOut;
+    resumeDetected <= next_resumeDetected;
+    processRxBitRdy <= next_processRxBitRdy;
+    RXBitStMachCurrState <= next_RXBitStMachCurrState;
+    RxBits <= next_RxBits;
+    RXSameBitCount <= next_RXSameBitCount;
+    RXBitCount <= next_RXBitCount;
+    oldRXBits <= next_oldRXBits;
+    RXByte <= next_RXByte;
+    bitStuffError <= next_bitStuffError;
+    resumeWaitCnt <= next_resumeWaitCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.v	(revision 264)
@@ -0,0 +1,358 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processTxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: processTxByte.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteWEn;
+input   rst;
+input   [7:0]TxByteCtrlIn;
+input   [7:0]TxByteIn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  processTxByteRdy;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processTxByteRdy, next_processTxByteRdy;
+wire    processTxByteWEn;
+wire    rst;
+wire    [7:0]TxByteCtrlIn;
+wire    [7:0]TxByteIn;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [3:0]i, next_i;
+reg  [7:0]TxByte, next_TxByte;
+reg  [7:0]TxByteCtrl, next_TxByteCtrl;
+reg  [1:0]TXLineState, next_TXLineState;
+reg  [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 4'b0000
+`define PTBY_WAIT_EN 4'b0001
+`define SEND_BYTE_UPDATE_BYTE 4'b0010
+`define SEND_BYTE_WAIT_RDY 4'b0011
+`define SEND_BYTE_CHK 4'b0100
+`define SEND_BYTE_BIT_STUFF 4'b0101
+`define SEND_BYTE_WAIT_RDY2 4'b0110
+`define SEND_BYTE_CHK_FIN 4'b0111
+`define PTBY_WAIT_GNT 4'b1000
+`define STOP_SND_SE0_2 4'b1001
+`define STOP_SND_SE0_1 4'b1010
+`define STOP_CHK 4'b1011
+`define STOP_SND_J 4'b1100
+`define STOP_SND_IDLE 4'b1101
+`define STOP_FIN 4'b1110
+
+reg [3:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
+begin
+  NextState_prcTxB <= CurrState_prcTxB;
+  // Set default values for outputs and signals
+  next_processTxByteRdy <= processTxByteRdy;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_USBWireReq <= USBWireReq;
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_TxByte <= TxByte;
+  next_TxByteCtrl <= TxByteCtrl;
+  next_TXLineState <= TXLineState;
+  next_TXOneCount <= TXOneCount;
+  case (CurrState_prcTxB)  // synopsys parallel_case full_case
+    `START_PTBY:
+    begin
+      next_processTxByteRdy <= 1'b0;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_i <= 4'h0;
+      next_TxByte <= 8'h00;
+      next_TxByteCtrl <= 8'h00;
+      next_TXLineState <= 2'b0;
+      next_TXOneCount <= 4'h0;
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `PTBY_WAIT_EN:
+    begin
+      next_processTxByteRdy <= 1'b1;
+      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_GNT;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TXOneCount <= 1;
+        next_TXLineState <= JBit;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (processTxByteWEn == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_i <= 4'h0;
+      end
+    end
+    `PTBY_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+        next_i <= 4'h0;
+      end
+    end
+    `SEND_BYTE_UPDATE_BYTE:
+    begin
+      next_i <= i + 1'b1;
+      next_TxByte <= {1'b0, TxByte[7:1] };
+      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
+      next_TXOneCount <= TXOneCount + 1'b1;
+      //increment 'TXOneCount'
+      else                                        //else this is a zero bit
+      begin
+      next_TXOneCount <= 4'h1;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      end
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+    end
+    `SEND_BYTE_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (TXOneCount == 4'h6)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+      end
+      else if (i != 4'h8)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+      else
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+    end
+    `SEND_BYTE_BIT_STUFF:
+    begin
+      next_TXOneCount <= 4'h1;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+    end
+    `SEND_BYTE_WAIT_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (i == 4'h8)
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+      else
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+    end
+    `STOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_J;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_SND_SE0_1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_CHK:
+    begin
+      if (TxByteCtrl == `DATA_STOP)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_1;
+      end
+      else
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_EN;
+      end
+    end
+    `STOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_IDLE;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_SND_IDLE:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `STOP_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      //release the wire
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prcTxB <= `START_PTBY;
+  else
+    CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processTxByteRdy <= 1'b0;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    USBWireReq <= 1'b0;
+    USBWireWEn <= 1'b0;
+    i <= 4'h0;
+    TxByte <= 8'h00;
+    TxByteCtrl <= 8'h00;
+    TXLineState <= 2'b0;
+    TXOneCount <= 4'h0;
+  end
+  else 
+  begin
+    processTxByteRdy <= next_processTxByteRdy;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    USBWireReq <= next_USBWireReq;
+    USBWireWEn <= next_USBWireWEn;
+    i <= next_i;
+    TxByte <= next_TxByte;
+    TxByteCtrl <= next_TxByteCtrl;
+    TXLineState <= next_TXLineState;
+    TXOneCount <= next_TXOneCount;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC16.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC16.v	(revision 264)
@@ -0,0 +1,113 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC16.v                                                ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: updateCRC16.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:04  sfielding
+// Created
+//
+//
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [15:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [15:0] CRCResult;
+reg    ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 16'hffff;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0)
+    begin
+      if (CRCEn == 1'b1) begin
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        ready <= 1'b0;
+    end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[15:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == 4'h7)
+      begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(revision 264)
@@ -0,0 +1,205 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbTxWireArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbTxWireArbiter.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input   clk;
+input   prcTxByteCtrl;
+input   [1:0]prcTxByteData;
+input   prcTxByteReq;
+input   prcTxByteWEn;
+input   rst;
+input   SIETxCtrl;
+input   [1:0]SIETxData;
+input   SIETxReq;
+input   SIETxWEn;
+input   USBWireRdyIn;
+output  prcTxByteGnt;
+output  SIETxGnt;
+output  [1:0]TxBits;
+output  TxCtl;
+output  USBWireRdyOut;
+output  USBWireWEn;
+
+wire    clk;
+wire    prcTxByteCtrl;
+wire    [1:0]prcTxByteData;
+reg     prcTxByteGnt, next_prcTxByteGnt;
+wire    prcTxByteReq;
+wire    prcTxByteWEn;
+wire    rst;
+wire    SIETxCtrl;
+wire    [1:0]SIETxData;
+reg     SIETxGnt, next_SIETxGnt;
+wire    SIETxReq;
+wire    SIETxWEn;
+reg     [1:0]TxBits, next_TxBits;
+reg     TxCtl, next_TxCtl;
+wire    USBWireRdyIn;
+reg     USBWireRdyOut, next_USBWireRdyOut;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)
+begin
+if (muxSIENotPTXB  == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+  NextState_txWireArb <= CurrState_txWireArb;
+  // Set default values for outputs and signals
+  next_prcTxByteGnt <= prcTxByteGnt;
+  next_SIETxGnt <= SIETxGnt;
+  next_muxSIENotPTXB <= muxSIENotPTXB;
+  case (CurrState_txWireArb)  // synopsys parallel_case full_case
+    `START_TARB:
+    begin
+      NextState_txWireArb <= `TARB_WAIT_REQ;
+    end
+    `TARB_WAIT_REQ:
+    begin
+      if (prcTxByteReq == 1'b1)
+      begin
+        NextState_txWireArb <= `PTXB_ACT;
+        next_prcTxByteGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b0;
+      end
+      else if (SIETxReq == 1'b1)
+      begin
+        NextState_txWireArb <= `SIE_TX_ACT;
+        next_SIETxGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b1;
+      end
+    end
+    `PTXB_ACT:
+    begin
+      if (prcTxByteReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_prcTxByteGnt <= 1'b0;
+      end
+    end
+    `SIE_TX_ACT:
+    begin
+      if (SIETxReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_SIETxGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_txWireArb <= `START_TARB;
+  else
+    CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    prcTxByteGnt <= 1'b0;
+    SIETxGnt <= 1'b0;
+    muxSIENotPTXB <= 1'b0;
+  end
+  else 
+  begin
+    prcTxByteGnt <= next_prcTxByteGnt;
+    SIETxGnt <= next_SIETxGnt;
+    muxSIENotPTXB <= next_muxSIENotPTXB;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/fifoMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/fifoMux.v	(revision 264)
@@ -0,0 +1,220 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoMux.v,v 1.2 2004-12-18 14:36:20 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:05  sfielding
+// Created
+//
+//
+
+module fifoMux (
+  currEndP,
+  //TxFifo
+  TxFifoREn,
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoData,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEmpty,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  //RxFifo
+  RxFifoWEn,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoFull,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+  //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+  //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+  TxFifoREn or
+  RxFifoWEn or
+  TxFifoEP0Data or
+  TxFifoEP1Data or
+  TxFifoEP2Data or
+  TxFifoEP3Data or
+  TxFifoEP0Empty or
+  TxFifoEP1Empty or
+  TxFifoEP2Empty or
+  TxFifoEP3Empty or
+  RxFifoEP0Full or
+  RxFifoEP1Full or
+  RxFifoEP2Full or
+  RxFifoEP3Full)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      TxFifoEP0REn <= TxFifoREn;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP0Data;
+      TxFifoEmpty <= TxFifoEP0Empty;
+      RxFifoEP0WEn <= RxFifoWEn;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP0Full;
+    end
+    2'b01: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= TxFifoREn;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP1Data;
+      TxFifoEmpty <= TxFifoEP1Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= RxFifoWEn;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP1Full;
+    end
+    2'b10: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= TxFifoREn;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP2Data;
+      TxFifoEmpty <= TxFifoEP2Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= RxFifoWEn;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP2Full;
+    end
+    2'b11: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= TxFifoREn;
+      TxFifoData <= TxFifoEP3Data;
+      TxFifoEmpty <= TxFifoEP3Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= RxFifoWEn;
+      RxFifoFull <= RxFifoEP3Full;
+    end
+  endcase  
+end      
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.asf	(revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SCTxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: sctxportarbiter.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
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+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
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+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SARB_SEND_PACKET\n/1/"
+S 14 6 4096 ELLIPSE "States" | 269063,296392 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 10 6 0 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_SARB\n/3/"
+S 8 6 12288 ELLIPSE "States" | 225591,395370 6500 6500
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "SCTxArb"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,543100 1 0 0 "Module: SCTxPortArbiter"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+                                      288786,359372 287077,371461 282417,376909 277757,382357\
+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+C 26 17 0 TEXT "Conditions" | 202073,391408 1 0 0 "rst"
+A 25 8 2 TEXT "Actions" | 234434,411387 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+W 19 6 4097 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210185,391478 219470,393186
+I 16 6 0 Builtin Reset | 178237,395710
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 43 42 0 TEXT "Labels" | 172566,462781 1 0 0 "SCTxPortRdyIn"
+I 42 0 2 Builtin InPort | 166566,462781 "" ""
+I 41 0 3 Builtin InPort | 190061,536582 "" ""
+L 40 39 0 TEXT "Labels" | 195447,542126 1 0 0 "rst"
+I 39 0 2 Builtin InPort | 189447,542126 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "SCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 61 41 0 TEXT "Labels" | 196061,536582 1 0 0 "clk"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "SCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n  SCTxPortRdyOut = SCTxPortRdyIn;\nend\n	  \nalways @(muxDCEn or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n  begin  \n    SCTxPortWEnable <= directCntlWEn;\n    SCTxPortData <= directCntlData;\n    SCTxPortCntl <= directCntlCntl;\n  end\nelse\n  begin  \n    SCTxPortWEnable <= sendPacketWEn;\n    SCTxPortData <= sendPacketData;\n    SCTxPortCntl <= sendPacketCntl;\n  end\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "SCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+L 65 64 0 TEXT "Labels" | 170048,467134 1 0 0 "SCTxPortRdyOut"
+I 64 0 2 Builtin OutPort | 164048,467134 "" ""
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+W 92 6 4098 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+S 91 6 8192 ELLIPSE "States" | 230314,289948 6500 6500
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "SARB_DC\n/2/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxDCEn"
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286142,395412 275462,395110\
+                                      264783,394808 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.asf	(revision 264)
@@ -0,0 +1,275 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=280
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveGetPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: slaveGetpacket.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
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+END
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+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: slaveGetPacket"
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+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+L 277 278 0 TEXT "State Labels" | 44712,168924 1 0 0 "DELAY\n/17/"
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+                                           58879,216350 75631,224113 84458,228187
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
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+                                         159556,30336 149499,27398 125714,27614 113171,27388
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+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+L 32 33 0 TEXT "State Labels" | 141266,72558 1 0 0 "PROC_PKT"
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+C 35 34 0 TEXT "Conditions" | 122487,97401 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
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+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
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+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+I 49 46 0 Builtin Entry | 47660,248640
+I 50 46 0 Builtin Exit | 180308,72140
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
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+I 75 72 0 Builtin Entry | 33260,254940
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177624,25344 184036,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176807,72082 177204,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.v	(revision 264)
@@ -0,0 +1,270 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveSendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveSendpacket.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   [3:0]PID;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   sendPacketWEn;
+output  fifoReadEn;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+wire    [3:0]PID;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: slvSndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
+begin
+  NextState_slvSndPkt <= CurrState_slvSndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvSndPkt)  // synopsys parallel_case full_case
+    `START_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+    end
+    `SP_WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP1_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `SP1_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_SCTxPortReq <= 1'b0;
+    end
+    `SP_NOT_DATA:
+    begin
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_SEND_PID_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= PIDNotPID;
+        next_SCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SP_SEND_PID_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_NOT_DATA;
+      end
+    end
+    `SP_D0_D1_READ_FIFO:
+    begin
+      next_SCTxPortWEn <= 1'b1;
+      next_SCTxPortData <= fifoData;
+      next_SCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+    end
+    `SP_D0_D1_WAIT_READ_FIFO:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `SP_D0_D1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+      end
+    end
+    `SP_D0_D1_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_D0_D1_TERM_BYTE:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `SP_D0_D1_CLR_WEN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+    end
+    `SP_D0_D1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvSndPkt <= `START_SP1;
+  else
+    CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    SCTxPortData <= 8'h00;
+    SCTxPortCntl <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlave.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlave.v	(revision 264)
@@ -0,0 +1,518 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlave.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostSlave.v,v 1.2 2004-12-18 14:36:23 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:11  sfielding
+// Created
+//
+//
+
+module usbHostSlave(
+  clk, 
+  rst,
+  address_i, 
+  data_i, 
+  data_o, 
+  writeEn, 
+  strobe_i,
+  ack_o,
+  hostSOFSentIntOut, 
+  hostConnEventIntOut, 
+  hostResumeIntOut, 
+  hostTransDoneIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+  USBWireDataIn,
+  USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+  USBWireCtrlOut
+   );
+  parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+  parameter HOST_FIFO_ADDR_WIDTH = 6;   
+  parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+  parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+  parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+  parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk;
+input rst;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input writeEn; 
+input strobe_i;
+output ack_o;
+output hostSOFSentIntOut; 
+output hostConnEventIntOut; 
+output hostResumeIntOut; 
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+
+wire clk;
+wire rst;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire writeEn; 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel; 
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE; 
+wire [7:0] hostTxFifoData; 
+wire hostTxFifoEmpty;
+wire hostRxFifoWE; 
+wire [7:0] hostRxFifoData; 
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost; 
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+
+usbHostControl u_usbHostControl(
+  .clk(clk), 
+  .rst(rst),
+  .TxFifoRE(hostTxFifoRE), 
+  .TxFifoData(hostTxFifoData), 
+  .TxFifoEmpty(hostTxFifoEmpty),
+  .RxFifoWE(hostRxFifoWE), 
+  .RxFifoData(hostRxFifoData), 
+  .RxFifoFull(hostRxFifoFull),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut),
+  .fullSpeedRate(fullSpeedBitRateFromHost), 
+  .fullSpeedPol(fullSpeedPolarityFromHost),
+  .HCTxPortEn(SIEPortWEnFromHost), 
+  .HCTxPortRdy(SIEPortTxRdy),
+  .HCTxPortData(SIEPortDataInFromHost), 
+  .HCTxPortCtrl(SIEPortCtrlInFromHost),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[3:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+  .SOFSentIntOut(hostSOFSentIntOut), 
+  .connEventIntOut(hostConnEventIntOut), 
+  .resumeIntOut(hostResumeIntOut), 
+  .transDoneIntOut(hostTransDoneIntOut),
+  .hostControlSelect(hostControlSel) );
+  
+
+usbSlaveControl u_usbSlaveControl(
+  .clk(clk), 
+  .rst(rst),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut), 
+  .RxFifoData(slaveRxFifoData),
+  .fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+  .SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+  .SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+  .SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk), 
+  .rst(rst),
+  .hostControlSel(hostControlSel), 
+  .hostRxFifoSel(hostRxFifoSel), 
+  .hostTxFifoSel(hostTxFifoSel),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(dataFromHostControl),
+  .dataFromHostRxFifo(dataFromHostRxFifo),
+  .dataFromHostTxFifo(dataFromHostTxFifo),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+   );
+
+hostSlaveMux u_hostSlaveMux(
+  .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+  .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+  .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+  .SIEPortDataInToSIE(SIEPortDataInToSIE), 
+  .SIEPortDataInFromHost(SIEPortDataInFromHost), 
+  .SIEPortDataInFromSlave(SIEPortDataInFromSlave), 
+  .SIEPortWEnToSIE(SIEPortWEnToSIE), 
+  .SIEPortWEnFromHost(SIEPortWEnFromHost), 
+  .SIEPortWEnFromSlave(SIEPortWEnFromSlave), 
+  .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+  .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+  .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+  .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+  .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+  .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux), 
+  .writeEn(writeEn),
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(clk), 
+  .rst(rst),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .connectState(connectState),
+  .resumeDetected(resumeDetected),
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataFromSIE), 
+  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+  .SIEPortDataIn(SIEPortDataInToSIE), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEnToSIE), 
+  .fullSpeedPolarity(fullSpeedPolarityToSIE),
+  .fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(hostTxFifoRE), 
+  .fifoEmpty(hostTxFifoEmpty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostTxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostTxFifo),
+  .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(hostRxFifoWE), 
+  .fifoFull(hostRxFifoFull),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostRxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostRxFifo),
+  .fifoDataIn(hostRxFifoData)  );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+  TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+  TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+endmodule
+
+  
+  
+
+
+
+

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\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifoBI.v	(revision 264)
@@ -0,0 +1,116 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+  address, writeEn, strobe_i,
+  clk, rst, fifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoWEn,
+  fifoFull,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoWEn;
+input fifoFull;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoWEn;
+wire fifoFull;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoFull or numElementsInFifo)
+begin
+  case (address)
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00;
+  endcase
+end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoWEn <= 1'b1;
+  else
+    fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.v	(revision 264)
@@ -0,0 +1,207 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveDirectControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveDirectcontrol.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+  NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+  // Set default values for outputs and signals
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvDrctCntl)  // synopsys parallel_case full_case
+    `START_SDC:
+    begin
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+        next_SCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= {6'b000000, directControlLineState};
+        next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      next_SCTxPortReq <= 1'b0;
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvDrctCntl <= `START_SDC;
+  else
+    CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SCTxPortCntl <= 8'h00;
+    SCTxPortData <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.asf	(revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveSendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: slaveSendpacket.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170187,37688 173773,37229
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "SCTxPortWEn"
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
+W 210 65 0 207 145 BEZIER "Transitions" | 169895,125680 176804,126013 188953,127552 193864,130465\
+                                          198775,133379 204604,144369 205686,152818 206768,161268\
+                                          205269,184079 201481,192903 197694,201727 184040,214216\
+                                          173218,217462 162396,220708 133810,221642 118992,221891
+W 209 65 0 136 207 BEZIER "Transitions" | 103712,132145 117531,130730 143304,126529 157123,125114
+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 76973,151815 1 0 0 "CLR_REN\n/13/"
+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/usbSlaveControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/usbSlaveControl.v	(revision 264)
@@ -0,0 +1,501 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSlaveControl.v,v 1.2 2004-12-18 14:36:21 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:10  sfielding
+// Created
+//
+//
+
+module usbSlaveControl(
+  clk, rst,
+  //getPacket
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut, RxFifoData,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //SCTxPortArbiter
+  SCTxPortEn, SCTxPortRdy,
+  SCTxPortData, SCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFRxedIntOut, 
+  resetEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  NAKSentIntOut,
+  slaveControlSelect,
+  //fifoMux
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+input clk, rst;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [4:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut; 
+output resetEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire clk;
+wire rst;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut; 
+wire resetEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed; 
+wire CRCError; 
+wire RXOverflow; 
+wire RXTimeOut; 
+wire bitStuffError; 
+wire dataSequence; 
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [3:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+
+USBSlaveControlBI u_USBSlaveControlBI
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .SOFRxedIntOut(SOFRxedIntOut), 
+  .resetEventIntOut(resetEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .NAKSentIntOut(NAKSentIntOut),
+  .endP0TransTypeReg(endP0TransTypeReg), 
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg), 
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg), 
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg), 
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .EP0StatusReg(endP0StatusReg),
+  .EP1StatusReg(endP1StatusReg),
+  .EP2StatusReg(endP2StatusReg),
+  .EP3StatusReg(endP3StatusReg),
+  .SCAddrReg(USBTgtAddress), 
+  .frameNum(frameNum),
+  .connectStateIn(connectStateOut),
+  .SOFRxedIn(SOFRxed), 
+  .resetEventIn(resetEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .NAKSentIn(NAKSent),
+  .slaveControlSelect(slaveControlSelect),
+  .clrEP0Ready(clrEP0Rdy), 
+  .clrEP1Ready(clrEP1Rdy), 
+  .clrEP2Ready(clrEP2Rdy), 
+  .clrEP3Ready(clrEP3Rdy),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .SCGlobalEn(SCGlobalEn)
+  );
+
+slavecontroller u_slavecontroller
+  (.CRCError(CRCError), 
+  .NAKSent(NAKSent), 
+  .RxByte(RxData), 
+  .RxDataWEn(RxDataValid), 
+  .RxOverflow(RXOverflow), 
+  .RxStatus(RxByteStatus), 
+  .RxTimeOut(RXTimeOut), 
+  .SCGlobalEn(SCGlobalEn), 
+  .SOFRxed(SOFRxed), 
+  .USBEndPControlReg(endPControlReg), 
+  .USBEndPNakTransTypeReg(transTypeNAK), 
+  .USBEndPTransTypeReg(transType), 
+  .USBEndP(currEndP), 
+  .USBTgtAddress(USBTgtAddress),
+  .bitStuffError(bitStuffError), 
+  .clk(clk), 
+  .clrEPRdy(clrEPRdy), 
+  .endPMuxErrorsWEn(endPMuxErrorsWEn), 
+  .frameNum(frameNum), 
+  .getPacketREn(getPacketREn), 
+  .getPacketRdy(getPacketRdy), 
+  .rst(rst), 
+  .sendPacketPID(slaveControllerPIDOut), 
+  .sendPacketRdy(slaveControllerReadyIn), 
+  .sendPacketWEn(slaveControllerWEnOut), 
+  .stallSent(stallSent), 
+  .transDone(transDone) 
+    );
+
+
+endpMux u_endpMux (
+  .clk(clk), 
+  .rst(rst),
+  .currEndP(currEndP),
+  .NAKSent(NAKSent),
+  .stallSent(stallSent),
+  .CRCError(CRCError),
+  .bitStuffError(bitStuffError),
+  .RxOverflow(RXOverflow),
+  .RxTimeOut(RXTimeOut),
+  .dataSequence(dataSequence),
+  .ACKRxed(ACKRxed),
+  .transType(transType),
+  .transTypeNAK(transTypeNAK),
+  .endPControlReg(endPControlReg),
+  .clrEPRdy(clrEPRdy),
+  .endPMuxErrorsWEn(endPMuxErrorsWEn),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .endP0StatusReg(endP0StatusReg),
+  .endP1StatusReg(endP1StatusReg),
+  .endP2StatusReg(endP2StatusReg),
+  .endP3StatusReg(endP3StatusReg),
+  .endP0TransTypeReg(endP0TransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg),
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .clrEP0Rdy(clrEP0Rdy),
+  .clrEP1Rdy(clrEP1Rdy),
+  .clrEP2Rdy(clrEP2Rdy),
+  .clrEP3Rdy(clrEP3Rdy)
+    );
+
+slaveSendPacket u_slaveSendPacket
+  (.PID(slaveControllerPIDOut), 
+  .SCTxPortCntl(sendPacketCntl),
+  .SCTxPortData(sendPacketData),
+  .SCTxPortGnt(sendPacketGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(sendPacketReq),
+  .SCTxPortWEn(sendPacketWEn),
+  .clk(clk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .rst(rst),
+  .sendPacketRdy(slaveControllerReadyIn),
+  .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+  (.SCTxPortCntl(directCntlCntl),
+  .SCTxPortData(directCntlData),
+  .SCTxPortGnt(directCntlGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(directCntlReq),
+  .SCTxPortWEn(directCntlWEn),
+  .clk(clk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rst) ); 
+
+SCTxPortArbiter u_SCTxPortArbiter
+  (.SCTxPortCntl(SCTxPortCtrl),
+  .SCTxPortData(SCTxPortData),
+  .SCTxPortRdyIn(SCTxPortRdy),
+  .SCTxPortRdyOut(SCTxPortArbRdyOut),
+  .SCTxPortWEnable(SCTxPortEn),
+  .clk(clk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rst),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+
+slaveGetPacket u_slaveGetPacket
+  (.ACKRxed(ACKRxed), 
+  .CRCError(CRCError), 
+  .RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .clk(clk),
+  .RXOverflow(RXOverflow), 
+  .RXTimeOut(RXTimeOut), 
+  .bitStuffError(bitStuffError), 
+  .dataSequence(dataSequence), 
+  .getPacketEn(getPacketREn),
+  .rst(rst) ); 
+
+slaveRxStatusMonitor  u_slaveRxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .resetEventOut(resetEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(clk),
+  .rst(rst)  );    
+  
+fifoMux u_fifoMux (
+  .currEndP(currEndP),
+  //TxFifo
+  .TxFifoREn(TxFifoRE),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoData(TxFifoData),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEmpty(TxFifoEmpty),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  //RxFifo
+  .RxFifoWEn(RxFifoWE),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoFull(RxFifoFull),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+    );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm	(revision 264)
@@ -0,0 +1,276 @@
+<html>
+<head>
+<title>USBHostControlBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBHostControlBI.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+ 
+<span id=t_kwd>module</span> <span id=t_idt>USBHostControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>SOFSentIntOut</span>, <span id=t_idt>connEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>TxTransTypeReg</span>, <span id=t_idt>TxSOFEnableReg</span>,
+  <span id=t_idt>TxAddrReg</span>, <span id=t_idt>TxEndPReg</span>, <span id=t_idt>frameNumIn</span>, 
+  <span id=t_idt>RxPktStatusIn</span>, <span id=t_idt>RxPIDIn</span>,
+  <span id=t_idt>connectStateIn</span>,
+  <span id=t_idt>SOFSentIn</span>, <span id=t_idt>connEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>,
+  <span id=t_idt>hostControlSelect</span>,
+  <span id=t_idt>clrTransReq</span>,
+  <span id=t_idt>preambleEn</span>,
+  <span id=t_idt>SOFSync</span>,
+  <span id=t_idt>TxLineState</span>,
+  <span id=t_idt>LineDirectControlEn</span>,
+  <span id=t_idt>fullSpeedPol</span>, 
+  <span id=t_idt>fullSpeedRate</span>,
+  <span id=t_idt>transReq</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>output</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transReq</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transReq</span>;
+
+<span id=t_com>//internal wire and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineControlReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrConnEvtReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>setTransReq</span>;
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResInReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>setTransReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>hostControlSelect</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>preambleEn</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>SOFSync</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>setTransReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>TxTransTypeReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>TxLineControlReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>TxSOFEnableReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>TxAddrReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>TxEndPReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_kwd>begin</span>
+        <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>clrResInReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>interruptMaskReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+   <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//interrupt control</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>SOFSentIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>connEventIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrConnEvtReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b0</span>;  
+
+  <span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//mask interrupts</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSentInt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>transDoneIntOut</span> &lt;= <span id=t_idt>transDoneInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>];
+  <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_idt>resumeInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>];
+  <span id=t_idt>connEventIntOut</span> &lt;= <span id=t_idt>connEventInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>CONNECTION_EVENT_BIT</span>];
+  <span id=t_idt>SOFSentIntOut</span> &lt;= <span id=t_idt>SOFSentInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_SENT_BIT</span>];
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//transaction request set/clear</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>setTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//break out control signals</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>TxLineState</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>TX_LINE_STATE_LSBIT</span>];
+  <span id=t_idt>LineDirectControlEn</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>DIRECT_CONTROL_BIT</span>];
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span>]; 
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span>];
+<span id=t_kwd>end</span>
+  
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxSOFEnableReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndPReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNumIn</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SOFSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span>
+  <span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>RxPktStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxPIDIn</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>preambleEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSync</span> <span id=t_kwd>or</span> <span id=t_idt>transReq</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>preambleEn</span>, <span id=t_idt>SOFSync</span>, <span id=t_idt>transReq</span>} ;
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>TxTransTypeReg</span>};
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>TxLineControlReg</span>};
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>TxSOFEnableReg</span>};
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxAddrReg</span>};
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>TxEndPReg</span>};
+     `<span id=t_idt>FRAME_NUM_MSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>frameNumIn</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>];
+     `<span id=t_idt>FRAME_NUM_LSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNumIn</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]};
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>SOFSentInt</span>, <span id=t_idt>connEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>};
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>interruptMaskReg</span>};
+     `<span id=t_idt>RX_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>RxPktStatusIn</span>;
+     `<span id=t_idt>RX_PID_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'b0000</span>, <span id=t_idt>RxPIDIn</span>};
+     `<span id=t_idt>RX_CONNECT_STATE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>};
+      <span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifo.v	(revision 264)
@@ -0,0 +1,121 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo write access via bus interface, fifo read access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module TxFifo(
+  clk, 
+  rst, 
+  fifoREn, 
+  fifoEmpty,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataOut ); 
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoREn; 
+output fifoEmpty;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire clk; 
+wire rst; 
+wire fifoREn; 
+wire fifoEmpty;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(busDataIn), 
+  .dataOut(fifoDataOut), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+TxfifoBI u_TxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoWEn(fifoWEn),
+  .fifoFull(fifoFull),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/simFifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/simFifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/simFifoMem.v	(revision 264)
@@ -0,0 +1,82 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// simFifoMem.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module simFifoMem(  addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge clk) begin
+  dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge clk) begin
+  if (writeEn == 1'b1)
+    buffer[addrIn] <= dataIn;
+end                  
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/simFifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.v	(revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// directControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+  NextState_drctCntl <= CurrState_drctCntl;
+  // Set default values for outputs and signals
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_drctCntl)  // synopsys parallel_case full_case
+    `START_DC:
+    begin
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_drctCntl <= `CHK_DRCT_CNTL;
+        next_HCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {6'b000000, directControlLineState};
+        next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_HCTxPortReq <= 1'b0;
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_drctCntl <= `START_DC;
+  else
+    CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.asf	(revision 264)
@@ -0,0 +1,313 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=256
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processrxbit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: processRxBit.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
+BUNDLES
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+END
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+OBJECTS
+L 15 16 0 TEXT "State Labels" | 116068,123104 1 0 0 "IDLE"
+W 13 6 0 12 9 BEZIER "Transitions" | 22728,190398 27224,190134 31822,186104 35786,184244
+I 12 6 0 Builtin Reset | 22728,190398
+S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
+L 8 9 0 TEXT "State Labels" | 42238,183458 1 0 0 "START\n/0/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 94226,265828 1 0 0 "Module: processRxBit"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,221539
+L 7 6 0 TEXT "Labels" | 23239,210942 1 0 0 "prRxBit"
+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
+S 24 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116801,94499 6500 6500
+W 23 17 0 18 21 BEZIER "Transitions" | 111741,134422 116780,127404 120535,103988 125575,96970
+I 21 17 0 Builtin Exit | 128380,96970
+I 20 17 0 Builtin Entry | 56736,212076
+L 19 18 0 TEXT "State Labels" | 107950,139700 1 0 0 "FIRST_BIT\n/1/"
+S 18 17 8192 ELLIPSE "States" | 107950,139700 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 16 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116068,123104 6500 6500
+L 43 42 0 TEXT "State Labels" | 119820,36808 1 0 0 "RES_END"
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+L 39 40 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK\n/9/"
+I 38 41 0 Builtin Entry | 86360,167640
+I 37 41 0 Builtin Exit | 129540,111760
+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
+W 35 41 0 40 37 BEZIER "Transitions" | 111741,134422 116780,127404 121695,118778 126735,111760
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+W 54 6 0 213 42 BEZIER "Transitions" | 42671,154227 43609,125551 43842,70308 45115,54764\
+                                       46388,39220 49604,34396 58247,33391 66890,32386\
+                                       97657,35973 113335,36375
+W 53 6 0 213 33 BEZIER "Transitions" | 42645,154234 43047,131722 42770,88800 43976,77142\
+                                       45182,65484 49202,63876 57711,63474 66220,63072\
+                                       96236,63072 103807,63072 111378,63072 111758,63165\
+                                       111892,63165
+W 52 6 0 213 24 BEZIER "Transitions" | 42699,154238 43235,140704 42636,114126 43641,106354\
+                                       44646,98582 47594,94562 55902,93624 64210,92686\
+                                       94494,92954 102132,93021 109770,93088 110325,93078\
+                                       110459,93078
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+                                       43038,129670 44914,125650 53423,124511 61932,123372\
+                                       93489,123426 109569,123158
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+W 76 17 4096 241 18 BEZIER "Transitions" | 130017,172236 121274,163054 112530,153872 103787,144690
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+A 73 18 4 TEXT "Actions" | 122746,145328 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h1;                          \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 68 6 0 16 219 BEZIER "Transitions" | 121312,119265 131167,111435 152206,96104 162061,88274
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+                                       188238,99472 188778,113512 186145,122422 183513,131332\
+                                       167904,143587 159264,149864 150624,156142 133542,158851\
+                                       125779,159931 118017,161011 123617,159646 119837,160051
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+A 80 76 16 TEXT "Actions" | 98161,161647 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+W 82 17 8194 75 21 BEZIER "Transitions" | 74719,170800 71529,161085 64380,142085 64960,133312\
+                                          65540,124540 74240,108880 82215,104385 90190,99890\
+                                          113975,98130 125575,96970
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+I 85 32 0 Builtin Entry | 37613,245373
+I 86 32 0 Builtin Exit | 178157,29567
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+I 105 101 0 Builtin Entry | 97220,125648
+I 106 101 0 Builtin Exit | 140400,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+                                        176540,156388 181096,131196 181431,113977 181766,96758\
+                                        182570,51409 180962,29567
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+                                            151482,86440 167580,47791 175352,29567
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+I 138 122 0 Builtin Entry | 32350,235287
+I 139 122 0 Builtin Exit | 103994,120181
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte;       \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit)                           //if current bit is a JBit, then\n  RXBitStMachCurrState <= `IDLE_BIT_ST;       //next state is idle\nelse                                          //else\nbegin\n  RXBitStMachCurrState <= `WAIT_RESUME_ST;    //check for resume\n  resumeWaitCnt <= 0;                          \nend"
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+I 154 129 0 Builtin Exit | 115081,122515
+I 155 129 0 Builtin Entry | 43437,237621
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+                                         145117,36964 157043,31068 161599,29627 166155,28187\
+                                         172203,29500 175352,29567
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+                                         107061,21822 137747,20482 148467,20415 159187,20348\
+                                         171381,21420 174463,22458 177545,23497 178090,26035\
+                                         178157,27576
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit)  //can only be a resume if line remains in Kbit state\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n  resumeWaitCnt <= resumeWaitCnt + 1'b1; \n  //if we've waited long enough, then\n  if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)\n  begin	\n    RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n    resumeDetected <= 1'b1;  //report resume detected\n  end\nend"
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+I 165 50 0 Builtin Exit | 139214,89780
+I 166 50 0 Builtin Entry | 96034,145660
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit)  //line must leave KBit state for the end of resume\nbegin\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\n  resumeDetected <= 1'b0;   //clear resume detected flag\nend"
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 4'h0;\nprocessRxBitRdy <= 1'b1;"
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+I 222 220 0 Builtin Exit | 129540,111760
+I 221 220 0 Builtin Entry | 86360,167640
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+I 216 214 0 Builtin Exit | 129540,111760
+I 215 214 0 Builtin Entry | 86360,167640
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[3:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+A 237 102 2 TEXT "Actions" | 35548,248222 1 0 0 "if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n  RXSameBitCount <= RXSameBitCount + 1'b1;  //inc 'RXSameBitCount'\n  if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error\n    bitStuffError <= 1'b1;                         //flag 'bitStuffError'\n  else                                          //else no bit stuffing error\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;                   //early indication of ready\n	end\n    RXByte <= { 1'b1, RXByte[7:1]};              //RZ bit = 1 (ie no change in 'RxBits')\n  end\nend\nelse                                            //else current 'RxBits' are different from old 'RxBits'\nbegin\n  if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;	               //early indication of ready\n	end\n    RXByte <= {1'b0, RXByte[7:1]};             //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n  end\n  RXSameBitCount <= 4'h1;                      //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+I 230 228 0 Builtin Exit | 129540,111760
+I 229 228 0 Builtin Entry | 86360,167640
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+C 244 76 0 TEXT "Conditions" | 125584,169201 1 0 0 "processRxByteRdy == 1'b1"
+C 243 242 0 TEXT "Conditions" | 86880,174058 1 0 0 "RxBits == KBit"
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 111780,177768 121508,177678
+S 241 17 86016 ELLIPSE "States" | 127967,178402 6500 6500
+L 240 241 0 TEXT "State Labels" | 127967,178402 1 0 0 "WAIT_PRB_RDY\n/12/"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.asf	(revision 264)
@@ -0,0 +1,218 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1000
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processTxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: processTxByte.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 874
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 887
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 994
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin InPort | 20959,250108 "" ""
+L 821 822 0 TEXT "Labels" | 26959,250108 1 0 0 "TxByteCtrlIn[7:0]"
+I 820 0 130 Builtin InPort | 20959,254515 "" ""
+L 819 820 0 TEXT "Labels" | 26959,254515 1 0 0 "TxByteIn[7:0]"
+I 818 0 2 Builtin OutPort | 18852,259388 "" ""
+L 817 818 0 TEXT "Labels" | 24852,259388 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin InPort | 20959,264028 "" ""
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+C 870 869 0 TEXT "Conditions" | 44743,165433 1 0 0 "processTxByteWEn == 1'b1"
+A 871 869 16 TEXT "Actions" | 40695,156023 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+L 873 874 0 TEXT "State Labels" | 48483,85161 1 0 0 "SEND_BYTE"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48483,85161 6500 6500
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 883 880 0 Builtin Entry | 38120,248040
+I 884 880 0 Builtin Exit | 178131,23271
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47391,100834 47973,91631
+W 897 6 0 874 887 BEZIER "Transitions" | 48237,78679 48703,71573 48867,58679 49333,51573
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+                                         25630,50244 23766,53274 22950,67894 22135,82515\
+                                         20737,137969 21261,153813 21785,169657 25281,177579\
+                                         27028,179792 28775,182006 32271,182938 33727,182355\
+                                         35183,181773 37321,179186 38486,177555
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1)                      //If this bit is 1, then\n  TXOneCount <= TXOneCount + 1'b1;          //increment 'TXOneCount'\nelse                                        //else this is a zero bit\nbegin\n  TXOneCount <= 4'h1;                            //reset 'TXOneCount'\n  if (TXLineState == JBit) \n    TXLineState <= KBit; //toggle the line state\n  else \n    TXLineState <= JBit;\nend"
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == 4'h6"
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h1;                                //reset 'TXOneCount'\nif (TXLineState == JBit) \n  TXLineState <= KBit;   //toggle the line state\nelse \n  TXLineState <= JBit;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+                                              113354,23912 154429,23527 174909,23271
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+                                              40522,42856 31562,47464 29098,65320 26634,83176\
+                                              25738,149992 26858,168968 27978,187944 33354,197032\
+                                              36938,198888 40522,200744 49226,198568 51498,198152\
+                                              53770,197736 54409,198230 54473,198230
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 1;       \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+W 940 6 0 936 874 BEZIER "Transitions" | 142661,111545 128565,105371 68178,94636 54082,88462
+C 941 940 0 TEXT "Conditions" | 111729,100310 1 0 0 "USBWireGnt == 1'b1"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+W 944 895 0 948 942 BEZIER "Transitions" | 72730,212275 73358,204982 73632,189078 74260,181785
+C 945 944 0 TEXT "Conditions" | 73971,211371 1 0 0 "USBWireRdy == 1'b1"
+A 946 942 4 TEXT "Actions" | 93534,178039 1 0 0 "USBWireWEn <= 1'b0;"
+A 947 944 16 TEXT "Actions" | 69416,202253 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+W 958 895 0 942 956 BEZIER "Transitions" | 75377,168841 76005,161548 76957,146611 77585,139318
+A 959 958 16 TEXT "Actions" | 72304,159240 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 960 956 4 TEXT "Actions" | 96752,135563 1 0 0 "USBWireWEn <= 1'b0;"
+C 961 958 0 TEXT "Conditions" | 76516,167828 1 0 0 "USBWireRdy == 1'b1"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+W 964 895 0 956 962 BEZIER "Transitions" | 78681,126377 79309,119084 79833,97641 80461,90348
+A 965 964 16 TEXT "Actions" | 75410,113723 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+A 966 962 4 TEXT "Actions" | 99640,86596 1 0 0 "USBWireWEn <= 1'b0;"
+C 967 964 0 TEXT "Conditions" | 79852,125749 1 0 0 "USBWireRdy == 1'b1"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+W 970 895 0 962 968 BEZIER "Transitions" | 81334,77407 81962,70114 82544,57872 83172,50579
+A 971 970 16 TEXT "Actions" | 77621,69378 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+C 973 970 0 TEXT "Conditions" | 81643,77033 1 0 0 "USBWireRdy == 1'b1"
+I 974 895 0 Builtin Exit | 97904,23272
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+                                           90132,26172 93257,24084 94765,23272
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+                                              104561,139388 153745,139620 168013,138576 182281,137532\
+                                              190169,133124 192141,121582 194113,110040 194113,68280\
+                                              192025,55114 189937,41948 185529,28723 181353,23271
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+                                              41124,121640 36948,124424 36020,132602 35092,140780\
+                                              35556,170708 38166,179350 40776,187992 50140,192687\
+                                              55128,195007
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+                                              30972,218732 29812,212468 29638,189094 29464,165720\
+                                              29928,78488 31900,55230 33872,31972 41296,26172\
+                                              49358,24664 57420,23156 82353,23388 94765,23272
+I 977 895 0 Builtin Entry | 34452,259216
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+A 979 9 4 TEXT "Actions" | 108416,207754 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;"
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 997 995 0 Builtin Exit | 129540,111760
+I 996 995 0 Builtin Entry | 86360,167640
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+L 815 816 0 TEXT "Labels" | 26959,264028 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.v	(revision 264)
@@ -0,0 +1,362 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIEReceiver
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: siereceiver.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, processRxBitRdyIn, processRxBitsWEn, rst, RxBitsOut, RxWireDataIn, RxWireDataWEn, SIERxRdyOut);
+input   clk;
+input   processRxBitRdyIn;
+input   rst;
+input   [1:0]RxWireDataIn;
+input   RxWireDataWEn;
+output  [1:0]connectState;
+output  processRxBitsWEn;
+output  [1:0]RxBitsOut;
+output  SIERxRdyOut;
+
+wire    clk;
+reg     [1:0]connectState, next_connectState;
+wire    processRxBitRdyIn;
+reg     processRxBitsWEn, next_processRxBitsWEn;
+wire    rst;
+reg     [1:0]RxBitsOut, next_RxBitsOut;
+wire    [1:0]RxWireDataIn;
+wire    RxWireDataWEn;
+reg     SIERxRdyOut, next_SIERxRdyOut;
+
+// diagram signals declarations
+reg  [1:0]RxBits, next_RxBits;
+reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg  [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define LS_CONN_PROC_RX_BITS 4'b0110
+`define FS_CONN_CHK_RX_BITS1 4'b0111
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b1000
+`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
+`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
+`define FS_CONN_PROC_RX_BITS1 4'b1100
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or processRxBitRdyIn or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or processRxBitsWEn or RxBitsOut or SIERxRdyOut or CurrState_rcvr)
+begin
+  NextState_rcvr <= CurrState_rcvr;
+  // Set default values for outputs and signals
+  next_RXWaitCount <= RXWaitCount;
+  next_connectState <= connectState;
+  next_RXStMachCurrState <= RXStMachCurrState;
+  next_processRxBitsWEn <= processRxBitsWEn;
+  next_RxBitsOut <= RxBitsOut;
+  next_RxBits <= RxBits;
+  next_SIERxRdyOut <= SIERxRdyOut;
+  case (CurrState_rcvr)  // synopsys parallel_case full_case
+    `WAIT_BIT:
+    begin
+      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+        next_SIERxRdyOut <= 1'b0;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+      begin
+        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+        next_RxBits <= RxWireDataIn;
+        next_SIERxRdyOut <= 1'b0;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+      begin
+        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+        next_SIERxRdyOut <= 1'b0;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+        next_SIERxRdyOut <= 1'b0;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+        next_SIERxRdyOut <= 1'b0;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+        next_RxBits <= RxWireDataIn;
+        next_SIERxRdyOut <= 1'b0;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+        next_RxBits <= RxWireDataIn;
+        next_SIERxRdyOut <= 1'b0;
+      end
+    end
+    `START_SRX:
+    begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_RXWaitCount <= 8'h00;
+      next_connectState <= `DISCONNECT;
+      next_RxBits <= 2'b00;
+      next_RxBitsOut <= 2'b00;
+      next_processRxBitsWEn <= 1'b0;
+      next_SIERxRdyOut <= 1'b1;
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `DISCNCT_CHK_RXBITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+        next_SIERxRdyOut <= 1'b1;
+      end
+      else if (RxBits == `ONE_ZERO)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+        next_SIERxRdyOut <= 1'b1;
+      end
+      else
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_SIERxRdyOut <= 1'b1;
+      end
+    end
+    `WAIT_FS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ONE_ZERO)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `FULL_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+      next_SIERxRdyOut <= 1'b1;
+    end
+    `WAIT_LS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `LOW_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+      next_SIERxRdyOut <= 1'b1;
+    end
+    `LS_CONN_CHK_RX_BITS:
+    begin
+      if (processRxBitRdyIn == 1'b1)
+      begin
+        NextState_rcvr <= `LS_CONN_PROC_RX_BITS;
+        if (RxBits == `SE0)
+        begin
+        next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+        next_RXWaitCount <= 0;
+        end
+        next_processRxBitsWEn <= 1'b1;
+        next_RxBitsOut <= RxBits;
+      end
+    end
+    `LS_CONN_PROC_RX_BITS:
+    begin
+      next_processRxBitsWEn <= 1'b0;
+      NextState_rcvr <= `WAIT_BIT;
+      next_SIERxRdyOut <= 1'b1;
+    end
+    `FS_CONN_CHK_RX_BITS1:
+    begin
+      if (processRxBitRdyIn == 1'b1)
+      begin
+        NextState_rcvr <= `FS_CONN_PROC_RX_BITS1;
+        if (RxBits == `SE0)
+        begin
+        next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+        next_RXWaitCount <= 0;
+        end
+        next_processRxBitsWEn <= 1'b1;
+        next_RxBitsOut <= RxBits;
+        next_SIERxRdyOut <= 1'b1;
+        //early indication of ready
+      end
+    end
+    `FS_CONN_PROC_RX_BITS1:
+    begin
+      next_processRxBitsWEn <= 1'b0;
+      NextState_rcvr <= `WAIT_BIT;
+      next_SIERxRdyOut <= 1'b1;
+    end
+    `WAIT_LS_DIS_CHK_RX_BITS:
+    begin
+      if (processRxBitRdyIn == 1'b1)
+      begin
+        NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS;
+        if (RxBits == `SE0)
+        begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+        if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+        begin
+        next_RXStMachCurrState <= `DISCONNECT_ST;
+        next_connectState <= `DISCONNECT;
+        end
+        end
+        else
+        begin
+        next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+        end
+        next_processRxBitsWEn <= 1'b1;
+      end
+    end
+    `WAIT_LS_DIS_PROC_RX_BITS:
+    begin
+      next_processRxBitsWEn <= 1'b0;
+      NextState_rcvr <= `WAIT_BIT;
+      next_SIERxRdyOut <= 1'b1;
+    end
+    `WAIT_FS_DIS_PROC_RX_BITS2:
+    begin
+      next_processRxBitsWEn <= 1'b0;
+      NextState_rcvr <= `WAIT_BIT;
+      next_SIERxRdyOut <= 1'b1;
+    end
+    `WAIT_FS_DIS_CHK_RX_BITS2:
+    begin
+      if (processRxBitRdyIn == 1'b1)
+      begin
+        NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2;
+        if (RxBits == `SE0)
+        begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+        if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+        begin
+        next_RXStMachCurrState <= `DISCONNECT_ST;
+        next_connectState <= `DISCONNECT;
+        end
+        end
+        else
+        begin
+        next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+        end
+        next_processRxBitsWEn <= 1'b1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_rcvr <= `START_SRX;
+  else
+    CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    connectState <= `DISCONNECT;
+    processRxBitsWEn <= 1'b0;
+    RxBitsOut <= 2'b00;
+    SIERxRdyOut <= 1'b1;
+    RXWaitCount <= 8'h00;
+    RXStMachCurrState <= `DISCONNECT_ST;
+    RxBits <= 2'b00;
+  end
+  else 
+  begin
+    connectState <= next_connectState;
+    processRxBitsWEn <= next_processRxBitsWEn;
+    RxBitsOut <= next_RxBitsOut;
+    SIERxRdyOut <= next_SIERxRdyOut;
+    RXWaitCount <= next_RXWaitCount;
+    RXStMachCurrState <= next_RXStMachCurrState;
+    RxBits <= next_RxBits;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(revision 264)
@@ -0,0 +1,105 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=128
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// usbTxWireArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: usbTxWireArbiter.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
+F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
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+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
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+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n  USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)  \nbegin\n  if (muxSIENotPTXB  == 1'b1)  \n  begin\n    USBWireWEn <= SIETxWEn;\n    TxBits <= SIETxData;\n    TxCtl <= SIETxCtrl;\n  end\n  else\n  begin\n    USBWireWEn <= prcTxByteWEn;\n    TxBits <= prcTxByteData;\n    TxCtl <= prcTxByteCtrl;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+                                      70311,70629 71874,86691 76817,93064 81761,99437\
+                                      89642,107471 97173,106158 104705,104845 116882,95874\
+                                      123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 153906,181456 "" ""
+L 110 111 0 TEXT "Labels" | 159906,181456 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 156447,157894 "" ""
+L 108 109 0 TEXT "Labels" | 162447,157894 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 156216,186076 "" ""
+L 106 107 0 TEXT "Labels" | 162216,186076 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 154368,153274 "" ""
+L 104 105 0 TEXT "Labels" | 160368,153274 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 130 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 155985,199705 "" ""
+L 122 123 0 TEXT "Labels" | 161985,199705 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 155985,195316 "" ""
+L 120 121 0 TEXT "Labels" | 161985,195316 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 155985,190696 "" ""
+L 118 119 0 TEXT "Labels" | 161985,190696 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 156447,171985 "" ""
+L 116 117 0 TEXT "Labels" | 162447,171985 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 156447,167596 "" ""
+L 114 115 0 TEXT "Labels" | 162447,167596 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 156447,162745 "" ""
+L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/endpMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/endpMux.v	(revision 264)
@@ -0,0 +1,268 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// endpMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: endpMux.v,v 1.2 2004-12-18 14:36:18 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:05  sfielding
+// Created
+//
+//
+
+`include "usbSlaveControl_h.v" 
+
+module endpMux (
+  clk, 
+  rst,
+  currEndP,
+  NAKSent,
+  stallSent,
+  CRCError,
+  bitStuffError,
+  RxOverflow,
+  RxTimeOut,
+  dataSequence,
+  ACKRxed,
+  transType,
+  transTypeNAK,
+  endPControlReg,
+  clrEPRdy,
+  endPMuxErrorsWEn,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  endP0StatusReg,
+  endP1StatusReg,
+  endP2StatusReg,
+  endP3StatusReg,
+  endP0TransTypeReg,
+  endP1TransTypeReg,
+  endP2TransTypeReg,
+  endP3TransTypeReg,
+  endP0NAKTransTypeReg,
+  endP1NAKTransTypeReg,
+  endP2NAKTransTypeReg,
+  endP3NAKTransTypeReg,
+  clrEP0Rdy,
+  clrEP1Rdy,
+  clrEP2Rdy,
+  clrEP3Rdy);
+
+
+input clk; 
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [3:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [3:0] endP0ControlReg;
+input [3:0] endP1ControlReg;
+input [3:0] endP2ControlReg;
+input [3:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk; 
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [3:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      endPControlReg <= endP0ControlReg;
+      clrEP0Rdy <= clrEPRdy;
+    end
+    2'b01: begin
+      endPControlReg <= endP1ControlReg;
+      clrEP1Rdy <= clrEPRdy;
+    end
+    2'b10: begin
+      endPControlReg <= endP2ControlReg;
+      clrEP2Rdy <= clrEPRdy;
+    end
+    2'b11: begin
+      endPControlReg <= endP3ControlReg;
+      clrEP3Rdy <= clrEPRdy;
+    end
+  endcase  
+end      
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+  if (rst) begin
+    endP0NAKTransTypeReg <= 2'b00;
+    endP1NAKTransTypeReg <= 2'b00;
+    endP2NAKTransTypeReg <= 2'b00;
+    endP3NAKTransTypeReg <= 2'b00;
+    endP0TransTypeReg <= 2'b00;
+    endP1TransTypeReg <= 2'b00;
+    endP2TransTypeReg <= 2'b00;
+    endP3TransTypeReg <= 2'b00;
+    endP0StatusReg <= 4'h0;
+    endP1StatusReg <= 4'h0;
+    endP2StatusReg <= 4'h0;
+    endP3StatusReg <= 4'h0;
+  end
+  else begin
+    if (endPMuxErrorsWEn == 1'b1) begin
+      if (NAKSent == 1'b1) begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0NAKTransTypeReg <= transTypeNAK;
+            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; 
+          end
+          2'b01: begin
+            endP1NAKTransTypeReg <= transTypeNAK;
+            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; 
+          end
+          2'b10: begin
+            endP2NAKTransTypeReg <= transTypeNAK;
+            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; 
+          end
+          2'b11: begin
+            endP3NAKTransTypeReg <= transTypeNAK;
+            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; 
+          end
+        endcase
+      end
+      else begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0TransTypeReg <= transType;
+            endP0StatusReg <= endPStatusCombine; 
+          end
+          2'b01: begin
+            endP1TransTypeReg <= transType;
+            endP1StatusReg <= endPStatusCombine; 
+          end
+          2'b10: begin
+            endP2TransTypeReg <= transType;
+            endP2StatusReg <= endPStatusCombine; 
+          end
+          2'b11: begin
+            endP3TransTypeReg <= transType;
+            endP3StatusReg <= endPStatusCombine; 
+          end
+        endcase
+      end
+    end
+  end
+end
+        
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveDirectControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: slaveDirectcontrol.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+END
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+                                        171826,160150 159742,169266 150997,171704 142252,174142\
+                                        120424,175336 108976,175654
+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "SCTxPortCntl[7:0]"
+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "SCTxPortData[7:0]"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "SCTxPortWEn"
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "SCTxPortRdy"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "SCTxPortGnt"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "SCTxPortReq"
+A 166 9 2 TEXT "Actions" | 121708,221292 1 0 0 "SCTxPortCntl <= 8'h00;\nSCTxPortData <= 8'h00;\nSCTxPortWEn <= 1'b0;   \nSCTxPortReq <= 1'b0;"
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "SCTxPortReq <= 1'b1;"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+I 179 0 130 Builtin InPort | 57352,247790 "" ""
+L 178 179 0 TEXT "Labels" | 63352,247790 1 0 0 "directControlLineState[1:0]"
+A 177 174 16 TEXT "Actions" | 102262,47300 1 0 0 "SCTxPortReq <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveRxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveRxStatusMonitor.v	(revision 264)
@@ -0,0 +1,103 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveRxStatusMonitor.v                                       ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveRxStatusMonitor.v,v 1.2 2004-12-18 14:36:20 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:09  sfielding
+// Created
+//
+//
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      resetEventOut <= 1'b1;
+    else
+      resetEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.v	(revision 264)
@@ -0,0 +1,478 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slavecontroller.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input   bitStuffError;
+input   clk;
+input   CRCError;
+input   getPacketRdy;
+input   rst;
+input   [7:0]RxByte;
+input   RxDataWEn;
+input   RxOverflow;
+input   [7:0]RxStatus;
+input   RxTimeOut;
+input   SCGlobalEn;
+input   sendPacketRdy;
+input   [3:0]USBEndPControlReg;
+input   [6:0]USBTgtAddress;
+output  clrEPRdy;
+output  endPMuxErrorsWEn;
+output  [10:0]frameNum;
+output  getPacketREn;
+output  NAKSent;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  SOFRxed;
+output  stallSent;
+output  transDone;
+output  [3:0]USBEndP;
+output  [1:0]USBEndPNakTransTypeReg;
+output  [1:0]USBEndPTransTypeReg;
+
+wire    bitStuffError;
+wire    clk;
+reg     clrEPRdy, next_clrEPRdy;
+wire    CRCError;
+reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg     [10:0]frameNum, next_frameNum;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+reg     NAKSent, next_NAKSent;
+wire    rst;
+wire    [7:0]RxByte;
+wire    RxDataWEn;
+wire    RxOverflow;
+wire    [7:0]RxStatus;
+wire    RxTimeOut;
+wire    SCGlobalEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     SOFRxed, next_SOFRxed;
+reg     stallSent, next_stallSent;
+reg     transDone, next_transDone;
+reg     [3:0]USBEndP, next_USBEndP;
+wire    [3:0]USBEndPControlReg;
+reg     [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg     [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire    [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg  [7:0]addrEndPTemp, next_addrEndPTemp;
+reg  [7:0]endpCRCTemp, next_endpCRCTemp;
+reg  [7:0]PIDByte, next_PIDByte;
+reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg  [6:0]USBAddress, next_USBAddress;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define IN_DATA 5'b01011
+`define IN_GET_RESP 5'b01100
+`define SETUP_OUT_CHK 5'b01101
+`define SETUP_OUT_SEND 5'b01110
+`define SETUP_OUT_GET_PKT 5'b01111
+`define START_S1 5'b10000
+`define GET_TOKEN_DELAY 5'b10001
+`define GET_TOKEN_CHK_ADDR 5'b10010
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)
+begin
+  NextState_slvCntrl <= CurrState_slvCntrl;
+  // Set default values for outputs and signals
+  next_stallSent <= stallSent;
+  next_NAKSent <= NAKSent;
+  next_SOFRxed <= SOFRxed;
+  next_PIDByte <= PIDByte;
+  next_transDone <= transDone;
+  next_clrEPRdy <= clrEPRdy;
+  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+  next_endpCRCTemp <= endpCRCTemp;
+  next_addrEndPTemp <= addrEndPTemp;
+  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+  next_frameNum <= frameNum;
+  next_USBAddress <= USBAddress;
+  next_USBEndP <= USBEndP;
+  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  next_getPacketREn <= getPacketREn;
+  case (CurrState_slvCntrl)  // synopsys parallel_case full_case
+    `WAIT_RX1:
+    begin
+      next_stallSent <= 1'b0;
+      next_NAKSent <= 1'b0;
+      next_SOFRxed <= 1'b0;
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_START && 
+        RxByte[1:0] == `TOKEN)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+        next_PIDByte <= RxByte;
+      end
+    end
+    `FIN_SC:
+    begin
+      next_transDone <= 1'b0;
+      next_clrEPRdy <= 1'b0;
+      next_endPMuxErrorsWEn <= 1'b0;
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_PID:
+    begin
+      if (PIDByte[3:0] == `SETUP)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if (PIDByte[3:0] == `OUT)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if (PIDByte[3:0] == `IN)
+      begin
+        NextState_slvCntrl <= `IN_CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `PID_ERROR;
+      end
+    end
+    `PID_ERROR:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_RDY:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_transDone <= 1'b1;
+        next_clrEPRdy <= 1'b1;
+        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else if (NAKSent == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+      end
+    end
+    `SETUP_OUT_CHK:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `SETUP_OUT_SEND:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `SETUP_OUT_GET_PKT:
+    begin
+      next_getPacketREn <= 1'b0;
+      if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+        bitStuffError == 1'b0 && 
+        RxOverflow == 1'b0 && 
+        RxTimeOut == 1'b0))
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_CHK;
+      end
+      else if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_NAK_STALL:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_CHK_RDY:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `IN_DATA:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_GET_RESP;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_GET_RESP:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `START_S1:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `GET_TOKEN_WAIT_CRC:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+        next_endpCRCTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_ADDR:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+        next_addrEndPTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_STOP:
+    begin
+      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+      end
+      else if (RxDataWEn == 1'b1)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_CHK_SOF:
+    begin
+      if (PIDByte[3:0] == `SOF)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+        next_SOFRxed <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_DELAY;
+        next_USBAddress <= addrEndPTemp[6:0];
+        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+      end
+    end
+    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndPControlReg to update
+    begin
+      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+    end
+    `GET_TOKEN_CHK_ADDR:
+    begin
+      if (USBEndP < `NUM_OF_ENDPOINTS  &&
+        USBAddress == USBTgtAddress &&
+        SCGlobalEn == 1'b1 &&
+        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_PID;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvCntrl <= `START_S1;
+  else
+    CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    stallSent <= 1'b0;
+    NAKSent <= 1'b0;
+    SOFRxed <= 1'b0;
+    transDone <= 1'b0;
+    clrEPRdy <= 1'b0;
+    endPMuxErrorsWEn <= 1'b0;
+    frameNum <= 11'b00000000000;
+    USBEndP <= 4'h0;
+    USBEndPTransTypeReg <= 2'b00;
+    USBEndPNakTransTypeReg <= 2'b00;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    getPacketREn <= 1'b0;
+    PIDByte <= 8'h00;
+    endpCRCTemp <= 8'h00;
+    addrEndPTemp <= 8'h00;
+    tempUSBEndPTransTypeReg <= 2'b00;
+    USBAddress <= 7'b0000000;
+  end
+  else 
+  begin
+    stallSent <= next_stallSent;
+    NAKSent <= next_NAKSent;
+    SOFRxed <= next_SOFRxed;
+    transDone <= next_transDone;
+    clrEPRdy <= next_clrEPRdy;
+    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+    frameNum <= next_frameNum;
+    USBEndP <= next_USBEndP;
+    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+    getPacketREn <= next_getPacketREn;
+    PIDByte <= next_PIDByte;
+    endpCRCTemp <= next_endpCRCTemp;
+    addrEndPTemp <= next_addrEndPTemp;
+    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+    USBAddress <= next_USBAddress;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.asf	(revision 264)
@@ -0,0 +1,280 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIEReceiver\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: siereceiver.asf,v 1.3 2004-12-31 14:40:43 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 23
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+GRID=OFF
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+END
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+END
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+END
+INSTHEADER 241
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 11 241 BEZIER "Transitions" | 54697,186192 54895,182331 55070,163352 55268,159491
+W 14 6 0 9 11 BEZIER "Transitions" | 53793,212320 54090,208657 54044,202830 54341,199167
+S 11 6 16384 ELLIPSE "States" | 54795,192690 6500 6500
+L 10 11 0 TEXT "State Labels" | 54795,192690 1 0 0 "WAIT_BIT\n/4/"
+S 9 6 20480 ELLIPSE "States" | 54004,218793 6500 6500
+L 8 9 0 TEXT "State Labels" | 54004,218793 1 0 0 "START_SRX\n/5/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: SIEReceiver"
+F 6 0 671089152 228 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14253,12655 205887,234211
+L 7 6 0 TEXT "Labels" | 17253,231211 1 0 0 "rcvr"
+S 23 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 143681,32406 6500 6500
+L 22 23 0 TEXT "State Labels" | 143681,32406 1 0 0 "DISCNCT"
+A 21 15 16 TEXT "Actions" | 50061,176470 1 0 0 "RxBits <= RxWireDataIn;\nSIERxRdyOut <= 1'b0;"
+C 19 15 0 TEXT "Conditions" | 55867,186045 1 0 0 "RxWireDataWEn == 1'b1"
+W 17 6 0 16 9 BEZIER "Transitions" | 25106,221421 30781,219421 43306,224917 48981,222917
+I 16 6 0 Builtin Reset | 25106,221421
+H 39 23 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 40 39 12288 ELLIPSE "States" | 64508,213851 6500 6500
+L 41 40 0 TEXT "State Labels" | 64508,213851 1 0 0 "CHK_RXBITS\n/3/"
+I 42 39 0 Builtin Entry | 42918,241791
+I 43 39 0 Builtin Exit | 147281,109121
+W 44 39 0 42 40 BEZIER "Transitions" | 47426,241791 52025,234967 56275,226064 60875,219240
+S 46 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 142838,49983 6500 6500
+L 47 46 0 TEXT "State Labels" | 142838,49983 1 0 0 "WAIT_FS_CONN"
+H 54 46 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 48 54 4096 53 50 BEZIER "Transitions" | 111761,134435 116730,128048 137142,101490 142112,94624
+W 49 54 0 51 53 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 50 54 0 Builtin Exit | 145248,94624
+I 51 54 0 Builtin Entry | 86360,167640
+L 52 53 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/0/"
+S 53 54 0 ELLIPSE "States" | 107950,139700 6500 6500
+H 63 55 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 55 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141452,68793 6500 6500
+L 56 55 0 TEXT "State Labels" | 141452,68793 1 0 0 "WAIT_LS_CONN"
+W 57 63 0 62 59 BEZIER "Transitions" | 111761,134435 116730,127570 121442,118626 126412,111760
+W 58 63 0 60 62 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 59 63 0 Builtin Exit | 129540,111760
+I 60 63 0 Builtin Entry | 86360,167640
+L 61 62 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/1/"
+S 62 63 4096 ELLIPSE "States" | 107950,139700 6500 6500
+H 72 64 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 64 6 36868 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 140066,86613 6500 6500
+L 65 64 0 TEXT "State Labels" | 140066,86613 1 0 0 "LS_CONN"
+W 67 72 0 69 71 BEZIER "Transitions" | 69044,194920 73643,188096 77893,179193 82493,172369
+I 68 72 0 Builtin Exit | 131860,37310
+I 69 72 0 Builtin Entry | 64536,194920
+L 70 71 0 TEXT "State Labels" | 86126,166980 1 0 0 "CHK_RX_BITS\n/2/"
+S 71 72 8192 ELLIPSE "States" | 86126,166980 6500 6500
+S 73 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 139274,106215 6500 6500
+L 74 73 0 TEXT "State Labels" | 139274,106215 1 0 0 "FS_CONN"
+H 81 73 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 90 82 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 82 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 137888,126411 6500 6500
+L 83 82 0 TEXT "State Labels" | 137888,126411 1 0 0 "WAIT_LS_DIS"
+S 91 6 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 136700,148244 6500 6500
+L 92 91 0 TEXT "State Labels" | 136700,148244 1 0 0 "WAIT_FS_DIS"
+H 99 91 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 129 39 8194 40 43 BEZIER "Transitions" | 67288,207977 90867,158271 120574,158827 144153,109121
+W 130 39 8193 40 43 BEZIER "Transitions" | 69252,218293 110985,257468 165540,129446 150409,109121
+C 131 129 0 TEXT "Conditions" | 55856,199298 1 0 0 "RxBits == `ONE_ZERO"
+C 132 130 0 TEXT "Conditions" | 98621,230429 1 0 0 "RxBits == `ZERO_ONE"
+A 133 130 16 TEXT "Actions" | 102033,204788 1 0 0 "RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+A 134 129 16 TEXT "Actions" | 41551,160050 1 0 0 "RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+W 138 6 0 241 91 BEZIER "Transitions" | 55726,152526 55825,150740 55689,148412 56830,147271\
+                                        57971,146130 62339,145137 65812,144988 69286,144839\
+                                        125497,147159 130261,147357
+W 139 6 0 241 82 BEZIER "Transitions" | 54775,152569 53765,144812 51800,131524 53198,127807\
+                                        54597,124090 58369,121813 62636,121465 66904,121118\
+                                        125138,124972 131490,125269
+W 140 6 0 241 73 BEZIER "Transitions" | 54816,152562 53725,141843 49733,121615 49138,115313\
+                                        48543,109011 48344,105238 49038,103700 49733,102162\
+                                        52773,100254 56507,99743 60241,99232 74292,101683\
+                                        79033,101771 83774,101859 131499,104027 132998,104525
+W 141 6 0 241 64 BEZIER "Transitions" | 54966,152543 53478,134579 47748,100673 48939,91443\
+                                        50130,82213 57873,81220 62984,81170 68095,81121\
+                                        127305,85134 133657,85531
+W 142 6 0 241 55 BEZIER "Transitions" | 55084,152531 53397,129108 47947,83900 50081,72287\
+                                        52215,60675 60863,63077 65955,63276 71048,63475\
+                                        83004,63522 85042,64000 87080,64479 134402,67217\
+                                        135100,67416
+W 143 6 0 241 46 BEZIER "Transitions" | 54918,152546 51842,126940 43778,76555 43182,62859\
+                                        42587,49163 46360,45589 52513,44944 58666,44299\
+                                        125961,48736 136382,49232
+W 159 6 0 23 235 BEZIER "Transitions" | 148132,37141 151647,41428 158891,48733 161548,55421\
+                                        164206,62109 167707,83613 169507,92702
+W 158 6 0 46 235 BEZIER "Transitions" | 146210,55537 151355,64540 163238,84117 168383,93120
+W 157 6 0 55 235 BEZIER "Transitions" | 145872,73557 150759,78444 162584,89003 167471,93890
+W 155 6 0 64 235 BEZIER "Transitions" | 146100,89028 150732,91430 162771,94113 166713,95483
+W 154 6 0 73 235 BEZIER "Transitions" | 145399,104041 150201,102669 162025,98607 166827,97235
+W 153 6 0 82 235 BEZIER "Transitions" | 142566,121900 148139,116412 162016,104012 167589,98524
+W 152 6 0 91 235 BEZIER "Transitions" | 140515,142982 147718,132349 161212,109811 168415,99178
+C 151 138 0 TEXT "Conditions" | 53061,140339 1 0 0 "RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST"
+C 150 139 0 TEXT "Conditions" | 52495,119006 1 0 0 "RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST"
+C 149 140 0 TEXT "Conditions" | 50344,99146 1 0 0 "RXStMachCurrState == `CONNECT_FULL_SPEED_ST"
+C 148 141 0 TEXT "Conditions" | 51096,80093 1 0 0 "RXStMachCurrState == `CONNECT_LOW_SPEED_ST"
+C 147 142 0 TEXT "Conditions" | 46355,62337 1 0 0 "RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST"
+C 146 143 0 TEXT "Conditions" | 46100,43512 1 0 0 "RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST"
+W 144 6 0 241 23 BEZIER "Transitions" | 54917,152544 50947,121578 41893,61271 41744,45441\
+                                        41595,29611 48940,28220 55540,28071 62140,27923\
+                                        127685,31371 137213,31768
+C 145 144 0 TEXT "Conditions" | 62881,26704 1 0 0 "RXStMachCurrState == `DISCONNECT_ST"
+W 161 39 8195 40 43 BEZIER "Transitions" | 58578,211192 49548,206204 31147,197012 26632,187509\
+                                           22117,178006 22117,149970 33211,139263 44305,128556\
+                                           88681,113764 103817,110238 118953,106712 136069,108777\
+                                           144153,109121
+W 160 6 0 235 11 BEZIER "Transitions" | 171556,99342 175414,111175 187017,133454 187960,147988\
+                                        188903,162522 181196,168609 172535,178212 163875,187816\
+                                        140506,197413 125270,198727 110035,200042 80303,196085\
+                                        61192,193841
+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `LOW_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+A 166 53 4 TEXT "Actions" | 101814,215348 1 0 0 "if (RxBits == `ONE_ZERO)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `FULL_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+L 167 168 0 TEXT "State Labels" | 102779,73959 1 0 0 "PROC_RX_BITS\n/6/"
+S 168 72 53248 ELLIPSE "States" | 102779,73959 6500 6500
+W 169 72 0 71 168 BEZIER "Transitions" | 86126,160480 86807,152989 100534,87755 101215,80264
+W 170 72 0 168 68 BEZIER "Transitions" | 106629,68724 112767,60967 122594,45067 128732,37310
+A 173 168 4 TEXT "Actions" | 121345,75637 1 0 0 "processRxBitsWEn <= 1'b0;"
+S 174 81 57344 ELLIPSE "States" | 85374,175380 6500 6500
+L 175 174 0 TEXT "State Labels" | 85374,175380 1 0 0 "CHK_RX_BITS1\n/7/"
+I 176 81 0 Builtin Entry | 63784,203320
+I 177 81 0 Builtin Exit | 137732,35774
+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+S 179 81 81920 ELLIPSE "States" | 108651,72423 6500 6500
+A 180 179 4 TEXT "Actions" | 127217,74101 1 0 0 "processRxBitsWEn <= 1'b0;"
+W 182 81 0 179 177 BEZIER "Transitions" | 112501,67188 118639,59431 128706,43531 134844,35774
+W 183 81 0 174 179 BEZIER "Transitions" | 85374,168880 86055,161389 106112,86141 106793,78650
+L 184 179 0 TEXT "State Labels" | 108651,72423 1 0 0 "PROC_RX_BITS1\n/12/"
+S 185 90 61440 ELLIPSE "States" | 81562,170615 6500 6500
+L 186 185 0 TEXT "State Labels" | 81562,170615 1 0 0 "CHK_RX_BITS\n/8/"
+I 187 90 0 Builtin Entry | 59972,198555
+I 188 90 0 Builtin Exit | 126468,30181
+W 189 90 0 187 185 BEZIER "Transitions" | 63495,198555 68094,191731 73329,182828 77929,176004
+S 190 90 65536 ELLIPSE "States" | 97387,66830 6500 6500
+A 191 190 4 TEXT "Actions" | 115953,68508 1 0 0 "processRxBitsWEn <= 1'b0;"
+W 193 90 0 190 188 BEZIER "Transitions" | 101237,61595 107375,53838 117590,37938 123728,30181
+W 194 90 0 185 190 BEZIER "Transitions" | 81562,164115 82243,156624 95324,80670 96005,73179
+L 195 190 0 TEXT "State Labels" | 97387,66830 1 0 0 "PROC_RX_BITS\n/9/"
+S 196 99 69632 ELLIPSE "States" | 91399,59215 6500 6500
+A 197 196 4 TEXT "Actions" | 109965,60893 1 0 0 "processRxBitsWEn <= 1'b0;"
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+I 199 99 0 Builtin Exit | 120480,22566
+I 200 99 0 Builtin Entry | 53777,190526
+S 201 99 73728 ELLIPSE "States" | 75367,162586 6500 6500
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/11/"
+L 203 196 0 TEXT "State Labels" | 91399,59215 1 0 0 "PROC_RX_BITS2\n/10/"
+W 204 99 0 201 196 BEZIER "Transitions" | 75367,156086 76048,148595 89316,73050 89997,65559
+W 205 99 0 196 199 BEZIER "Transitions" | 95249,53980 101387,46223 111486,30323 117624,22566
+I 221 0 2 Builtin OutPort | 129743,241655 "" ""
+L 220 221 0 TEXT "Labels" | 135743,241655 1 0 0 "processRxBitsWEn"
+I 219 0 130 Builtin Signal | 20132,253454 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 215 0 130 Builtin Signal | 20439,258880 "" ""
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+I 209 0 130 Builtin InPort | 77032,244882 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+I 233 0 130 Builtin Signal | 19714,243194 "" ""
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;\nRxBitsOut <= 2'b00;\nprocessRxBitsWEn <= 1'b0;\nSIERxRdyOut <= 1'b1;"
+I 225 0 130 Builtin OutPort | 129743,246614 "" ""
+L 224 225 0 TEXT "Labels" | 135743,246614 1 0 0 "RxBitsOut[1:0]"
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+S 235 6 77844 ELLIPSE "Junction" | 170150,96140 3500 3500
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 237 236 0 Builtin Entry | 86360,167640
+I 238 236 0 Builtin Exit | 129540,111760
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+A 255 194 16 TEXT "Actions" | 61406,142366 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend\nprocessRxBitsWEn <= 1'b1;"
+C 254 194 0 TEXT "Conditions" | 81005,160052 1 0 0 "processRxBitRdyIn == 1'b1"
+C 253 204 0 TEXT "Conditions" | 76690,153596 1 0 0 "processRxBitRdyIn == 1'b1"
+A 252 204 16 TEXT "Actions" | 57026,138798 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend\nprocessRxBitsWEn <= 1'b1;"
+A 250 160 16 TEXT "Actions" | 151210,187452 1 0 0 "SIERxRdyOut <= 1'b1;"
+I 249 0 2 Builtin OutPort | 74763,249425 "" ""
+L 248 249 0 TEXT "Labels" | 80763,249425 1 0 0 "SIERxRdyOut"
+I 247 0 2 Builtin InPort | 132223,251370 "" ""
+L 246 247 0 TEXT "Labels" | 138223,251370 1 0 0 "processRxBitRdyIn"
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+S 241 6 81940 ELLIPSE "Junction" | 55410,156008 3500 3500
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 243 242 0 Builtin Entry | 86360,167640
+I 244 242 0 Builtin Exit | 129540,111760
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+A 259 169 16 TEXT "Actions" | 64097,138640 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend\nprocessRxBitsWEn <= 1'b1;\nRxBitsOut <= RxBits;"
+A 258 183 16 TEXT "Actions" | 78587,143608 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend\nprocessRxBitsWEn <= 1'b1;\nRxBitsOut <= RxBits;\nSIERxRdyOut <= 1'b1; //early indication of ready"
+C 257 169 0 TEXT "Conditions" | 57276,154345 1 0 0 "processRxBitRdyIn == 1'b1"
+C 256 183 0 TEXT "Conditions" | 63784,161795 1 0 0 "processRxBitRdyIn == 1'b1"
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(revision 264)
@@ -0,0 +1,378 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine.v                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSerialInterfaceEngine.v,v 1.3 2004-12-31 14:40:43 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:04  sfielding
+// Created
+//
+//
+
+module usbSerialInterfaceEngine(
+  clk, rst,
+  //readUSBWireData
+  USBWireDataIn,
+  USBWireDataInTick,
+  //writeUSBWireData
+  USBWireDataOut,
+  USBWireCtrlOut,
+  USBWireDataOutTick,
+  //SIEReceiver
+  connectState,
+  //processRxBit
+  resumeDetected,
+  //processRxByte
+  RxCtrlOut, 
+  RxDataOutWEn, 
+  RxDataOut, 
+    //SIETransmitter
+  SIEPortCtrlIn,
+  SIEPortDataIn, 
+  SIEPortTxRdy, 
+  SIEPortWEn, 
+    //lineControlUpdate
+  fullSpeedPolarity,
+  fullSpeedBitRate,
+  noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut; 
+output RxDataOutWEn; 
+output [7:0] RxDataOut; 
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy; 
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut; 
+wire RxDataOutWEn; 
+wire [7:0] RxDataOut; 
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy; 
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire [1:0] RxBitsFromSIERxToPrRxBit;
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRxToSIERx;
+wire RxWireDataWEn;
+wire SIERxRdyOut;
+wire disableWireRead;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En; 
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En; 
+wire [4:0] RxCRC5Result; 
+wire RxCRC5_8Bit; 
+wire [7:0] RxCRCData; 
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En; 
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En; 
+wire [4:0] TxCRC5Result; 
+wire TxCRC5_8Bit; 
+wire [7:0] TxCRCData; 
+wire TxRstCRC; 
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy; 
+wire processTxByteWEn; 
+
+lineControlUpdate u_lineControlUpdate
+  (.fullSpeedPolarity(fullSpeedPolarity),
+  .fullSpeedBitRate(fullSpeedBitRate),
+  .JBit(JBit),
+  .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+  (.RxBitsOut(RxBitsFromSIERxToPrRxBit),
+  .RxWireDataIn(RxWireDataFromWireRxToSIERx), 
+  .RxWireDataWEn(RxWireDataWEn), 
+  .SIERxRdyOut(SIERxRdyOut), 
+  .clk(clk),
+  .connectState(connectState),
+  .processRxBitRdyIn(processRxBitRdy), 
+  .processRxBitsWEn(processRxBitsWEn), 
+  .rst(rst) );
+  
+processRxBit u_processRxBit
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .RxBitsIn(RxBitsFromSIERxToPrRxBit), 
+  .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxDataOut(RxDataFromPrcRxBitToPrcRxByte), 
+  .clk(clk), 
+  .processRxBitRdy(processRxBitRdy), 
+  .processRxBitsWEn(processRxBitsWEn), 
+  .processRxByteWEn(processRxByteWEn), 
+  .resumeDetected(resumeDetected), 
+  .rst(rst),
+  .processRxByteRdy(processRxByteRdy) );
+  
+processRxByte u_processRxByte
+  (.CRC16En(RxCRC16En), 
+  .CRC16Result(RxCRC16Result), 
+  .CRC16UpdateRdy(RxCRC16UpdateRdy),
+  .CRC5En(RxCRC5En), 
+  .CRC5Result(RxCRC5Result), 
+  .CRC5_8Bit(RxCRC5_8Bit),
+  .CRC5UpdateRdy(RxCRC5UpdateRdy),
+  .CRCData(RxCRCData), 
+  .RxByteIn(RxDataFromPrcRxBitToPrcRxByte), 
+  .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataOut), 
+  .clk(clk), 
+  .processRxDataInWEn(processRxByteWEn), 
+  .rst(rst), 
+  .rstCRC(RxRstCRC),
+  .processRxByteRdy(processRxByteRdy) ); 
+  
+  
+updateCRC5 RxUpdateCRC5
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC5Result), 
+  .CRCEn(RxCRC5En), 
+  .CRC5_8BitIn(RxCRC5_8Bit), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 RxUpdateCRC16
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC16Result), 
+  .CRCEn(RxCRC16En), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+SIETransmitter u_SIETransmitter
+  (.CRC16En(TxCRC16En), 
+  .CRC16Result(TxCRC16Result), 
+  .CRC5En(TxCRC5En), 
+  .CRC5Result(TxCRC5Result), 
+  .CRC5_8Bit(TxCRC5_8Bit), 
+  .CRCData(TxCRCData),
+  .CRC5UpdateRdy(TxCRC5UpdateRdy),
+  .CRC16UpdateRdy(TxCRC16UpdateRdy),
+  .JBit(JBit), 
+  .KBit(KBit), 
+  .SIEPortCtrlIn(SIEPortCtrlIn),
+  .SIEPortDataIn(SIEPortDataIn), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEn), 
+  .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteOut(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(SIETxCtrl), 
+  .USBWireData(SIETxData), 
+  .USBWireGnt(SIETxGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(SIETxReq), 
+  .USBWireWEn(SIETxWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst), 
+  .rstCRC(TxRstCRC) );    
+
+updateCRC5 TxUpdateCRC5
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC5Result), 
+  .CRCEn(TxCRC5En), 
+  .CRC5_8BitIn(TxCRC5_8Bit), 
+  .dataIn(TxCRCData),
+  .ready(TxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 TxUpdateCRC16
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC16Result), 
+  .CRCEn(TxCRC16En), 
+  .dataIn(TxCRCData), 
+  .ready(TxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+
+processTxByte u_processTxByte
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteIn(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(prcTxByteCtrl), 
+  .USBWireData(prcTxByteData), 
+  .USBWireGnt(prcTxByteGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(prcTxByteReq), 
+  .USBWireWEn(prcTxByteWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst) ); 
+  
+USBTxWireArbiter u_USBTxWireArbiter
+  (.SIETxCtrl(SIETxCtrl), 
+  .SIETxData(SIETxData), 
+  .SIETxGnt(SIETxGnt), 
+  .SIETxReq(SIETxReq), 
+  .SIETxWEn(SIETxWEn), 
+  .TxBits(TxBitsFromArbToWire), 
+  .TxCtl(TxCtrlFromArbToWire), 
+  .USBWireRdyIn(USBWireRdy), 
+  .USBWireRdyOut(USBWireReadyFromTxArb), 
+  .USBWireWEn(USBWireWEn),
+  .clk(clk), 
+  .prcTxByteCtrl(prcTxByteCtrl), 
+  .prcTxByteData(prcTxByteData), 
+  .prcTxByteGnt(prcTxByteGnt), 
+  .prcTxByteReq(prcTxByteReq), 
+  .prcTxByteWEn(prcTxByteWEn), 
+  .rst(rst) ); 
+  
+writeUSBWireData u_writeUSBWireData
+  (.TxBitsIn(TxBitsFromArbToWire), 
+  .TxBitsOut(USBWireDataOut), 
+  .TxDataOutTick(USBWireDataOutTick),
+  .TxCtrlIn(TxCtrlFromArbToWire), 
+  .TxCtrlOut(USBWireCtrlOut), 
+  .USBWireRdy(USBWireRdy), 
+  .USBWireWEn(USBWireWEn),
+  .disableWireReadOut(disableWireRead),
+  .fullSpeedRate(fullSpeedBitRate), 
+  .clk(clk),
+  .rst(rst),
+  .noActivityTimeOut(noActivityTimeOut) );  
+  
+readUSBWireData u_readUSBWireData
+  (.RxBitsIn(USBWireDataIn), 
+  .RxDataInTick(USBWireDataInTick),
+  .RxBitsOut(RxWireDataFromWireRxToSIERx), 
+  .SIERxRdyIn(SIERxRdyOut), 
+  .SIERxWEn(RxWireDataWEn), 
+  .fullSpeedRate(fullSpeedBitRate), 
+  .disableWireRead(disableWireRead),
+  .clk(clk),
+  .rst(rst) );
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/USBSlaveControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/USBSlaveControlBI.v	(revision 264)
@@ -0,0 +1,397 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBSlaveControlBI.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: USBSlaveControlBI.v,v 1.2 2004-12-18 14:36:17 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1  2004/10/11 04:01:10  sfielding
+// Created
+//
+//
+
+`include "usbSlaveControl_h.v"
+ 
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+  SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+  endP0TransTypeReg, endP0NAKTransTypeReg,
+  endP1TransTypeReg, endP1NAKTransTypeReg,
+  endP2TransTypeReg, endP2NAKTransTypeReg,
+  endP3TransTypeReg, endP3NAKTransTypeReg,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  EP0StatusReg,
+  EP1StatusReg,
+  EP2StatusReg,
+  EP3StatusReg,
+  SCAddrReg, frameNum,
+  connectStateIn,
+  SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+  slaveControlSelect,
+  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  SCGlobalEn
+  );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg; 
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg; 
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg; 
+input [1:0] endP3NAKTransTypeReg;
+output [3:0] endP0ControlReg;
+output [3:0] endP1ControlReg;
+output [3:0] endP2ControlReg;
+output [3:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg; 
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg; 
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg; 
+wire [1:0] endP3NAKTransTypeReg;
+reg [3:0] endP0ControlReg;
+reg [3:0] endP1ControlReg;
+reg [3:0] endP2ControlReg;
+reg [3:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+
+//sync write demux
+always @(posedge clk)
+begin
+  clrNAKReq <= 1'b0;
+  clrSOFReq <= 1'b0;
+  clrResetReq <= 1'b0;
+  clrResInReq <= 1'b0;
+  clrTransDoneReq <= 1'b0;
+  EP0SetReady <= 1'b0;
+  EP1SetReady <= 1'b0;
+  EP2SetReady <= 1'b0;
+  EP3SetReady <= 1'b0;
+  if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+  begin
+    case (address)
+      `EP0_CTRL_REG : begin
+        EP0SendStall <= dataIn[3];
+        EP0DataSequence <= dataIn[2];
+        EP0SetReady <= dataIn[1];
+        EP0Enable <= dataIn[0];
+      end
+      `EP1_CTRL_REG : begin
+        EP1SendStall <= dataIn[3];
+        EP1DataSequence <= dataIn[2];
+        EP1SetReady <= dataIn[1];
+        EP1Enable <= dataIn[0];
+      end
+      `EP2_CTRL_REG : begin
+        EP2SendStall <= dataIn[3];
+        EP2DataSequence <= dataIn[2];
+        EP2SetReady <= dataIn[1];
+        EP2Enable <= dataIn[0];
+      end
+      `EP3_CTRL_REG : begin
+        EP3SendStall <= dataIn[3];
+        EP3DataSequence <= dataIn[2];
+        EP3SetReady <= dataIn[1];
+        EP3Enable <= dataIn[0];
+      end
+      `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+      `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+      `SC_INTERRUPT_STATUS_REG : begin
+        clrNAKReq <= dataIn[4];
+        clrSOFReq <= dataIn[3];
+        clrResetReq <= dataIn[2];
+        clrResInReq <= dataIn[1];
+        clrTransDoneReq <= dataIn[0];
+      end
+      `SC_INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[4:0];
+    endcase
+  end
+end
+
+//interrupt control 
+always @(posedge clk)
+begin
+  if (NAKSentIn == 1'b1)
+    NAKSentInt <= 1'b1;
+  else if (clrNAKReq == 1'b1)
+    NAKSentInt <= 1'b0; 
+    
+  if (SOFRxedIn == 1'b1)
+    SOFRxedInt <= 1'b1;
+  else if (clrSOFReq == 1'b1)
+    SOFRxedInt <= 1'b0;
+    
+  if (resetEventIn == 1'b1)
+    resetEventInt <= 1'b1;
+  else if (clrResetReq == 1'b1)
+    resetEventInt <= 1'b0;
+    
+  if (resumeIntIn == 1'b1)
+    resumeInt <= 1'b1;
+  else if (clrResInReq == 1'b1)
+    resumeInt <= 1'b0;  
+
+  if (transDoneIn == 1'b1)
+    transDoneInt <= 1'b1;
+  else if (clrTransDoneReq == 1'b1)
+    transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end  
+
+//end point ready, set/clear
+always @(posedge clk)
+begin
+  if (EP0SetReady == 1'b1)
+    EP0Ready <= 1'b1;
+  else if (clrEP0Ready == 1'b1)
+    EP0Ready <= 1'b0;
+    
+  if (EP1SetReady == 1'b1)
+    EP1Ready <= 1'b1;
+  else if (clrEP1Ready == 1'b1)
+    EP1Ready <= 1'b0;
+    
+  if (EP2SetReady == 1'b1)
+    EP2Ready <= 1'b1;
+  else if (clrEP2Ready == 1'b1)
+    EP2Ready <= 1'b0;
+    
+  if (EP3SetReady == 1'b1)
+    EP3Ready <= 1'b1;
+  else if (clrEP3Ready == 1'b1)
+    EP3Ready <= 1'b0;
+end  
+  
+//break out control signals
+always @(SCControlReg) begin
+  SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+  TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+  fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals 
+always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable) 
+begin
+  endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+  endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+  endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+  endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+      
+      
+      // async read mux
+always @(address or
+  EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+  EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
+  endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
+  endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or 
+  endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
+  SCControlReg or connectStateIn or
+  NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or SCAddrReg or frameNum)
+begin
+  case (address)
+      `EP0_CTRL_REG : dataOut <= endP0ControlReg;
+      `EP0_STS_REG : dataOut <= EP0StatusReg;
+      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
+      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
+      `EP1_CTRL_REG : dataOut <= endP1ControlReg;
+      `EP1_STS_REG :  dataOut <= EP1StatusReg;
+      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
+      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
+      `EP2_CTRL_REG : dataOut <= endP2ControlReg;
+      `EP2_STS_REG :  dataOut <= EP2StatusReg;
+      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
+      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
+      `EP3_CTRL_REG : dataOut <= endP3ControlReg;
+      `EP3_STS_REG :  dataOut <= EP3StatusReg;
+      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
+      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
+      `SC_CONTROL_REG : dataOut <= SCControlReg;
+      `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn}; 
+      `SC_INTERRUPT_STATUS_REG :  dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+      `SC_INTERRUPT_MASK_REG  : dataOut <= {3'b000, interruptMaskReg};
+      `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+      `SC_FRAME_NUM_MSP : dataOut <= frameNum[10:3];
+      `SC_FRAME_NUM_LSP : dataOut <= {5'b00000, frameNum[2:0]};
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.v	(revision 264)
@@ -0,0 +1,203 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SCTxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: sctxportarbiter.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   SCTxPortRdyIn;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  directCntlGnt;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortRdyOut;
+output  SCTxPortWEnable;
+output  sendPacketGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortRdyIn;
+reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg     SCTxPortWEnable, next_SCTxPortWEnable;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+  NextState_SCTxArb <= CurrState_SCTxArb;
+  // Set default values for outputs and signals
+  next_sendPacketGnt <= sendPacketGnt;
+  next_muxDCEn <= muxDCEn;
+  next_directCntlGnt <= directCntlGnt;
+  case (CurrState_SCTxArb)  // synopsys parallel_case full_case
+    `SARB1_WAIT_REQ:
+    begin
+      if (sendPacketReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxDCEn <= 1'b0;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_DC;
+        next_directCntlGnt <= 1'b1;
+        next_muxDCEn <= 1'b1;
+      end
+    end
+    `SARB_SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `SARB_DC:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_SCTxArb <= `SARB1_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SCTxArb <= `START_SARB;
+  else
+    CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketGnt <= 1'b0;
+    directCntlGnt <= 1'b0;
+    muxDCEn <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketGnt <= next_sendPacketGnt;
+    directCntlGnt <= next_directCntlGnt;
+    muxDCEn <= next_muxDCEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.v	(revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveGetPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveGetpacket.v,v 1.3 2004-12-31 14:40:44 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
+input   clk;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  ACKRxed;
+output  bitStuffError;
+output  CRCError;
+output  dataSequence;
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXOverflow;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  RXTimeOut;
+
+reg     ACKRxed, next_ACKRxed;
+reg     bitStuffError, next_bitStuffError;
+wire    clk;
+reg     CRCError, next_CRCError;
+reg     dataSequence, next_dataSequence;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXOverflow, next_RXOverflow;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+wire    [7:0]RXStreamStatusIn;
+reg     RXTimeOut, next_RXTimeOut;
+wire    SIERxTimeOut;
+
+// diagram signals declarations
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
+begin
+  NextState_slvGetPkt <= CurrState_slvGetPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  case (CurrState_slvGetPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_slvGetPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_slvGetPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (RXFifoFull == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvGetPkt <= `START_GP;
+  else
+    CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXOverflow <= 1'b0;
+    ACKRxed <= 1'b0;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RXTimeOut <= 1'b0;
+    RxPID <= 4'h0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    RXByteOld <= 8'h00;
+  end
+  else 
+  begin
+    RXOverflow <= next_RXOverflow;
+    ACKRxed <= next_ACKRxed;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RXTimeOut <= next_RXTimeOut;
+    RxPID <= next_RxPID;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    RXByteOld <= next_RXByteOld;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.asf	(revision 264)
@@ -0,0 +1,358 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=789
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n// $Id: slavecontroller.asf,v 1.3 2004-12-31 14:40:44 sfielding Exp $\n//\n// CVS Revision History\n//\n// $Log: not supported by cvs2svn $\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 376
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+END
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+END
+INSTHEADER 15
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 554 551 0 TEXT "State Labels" | 63527,72146 1 0 0 "SETUP_OUT"
+S 551 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63527,72146 6500 6500
+H 559 551 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3275 212900,251275
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+                                       30330,86104 25492,143212 35905,156667 46318,170122\
+                                       96612,168665 117496,167729
+A 548 546 16 TEXT "Actions" | 104043,25328 1 0 0 "USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+C 547 546 0 TEXT "Conditions" | 180628,44450 1 0 0 "NAKSent == 1'b1"
+W 546 6 8194 531 81 BEZIER "Transitions" | 193355,54360 193121,48042 196557,33707 194740,28964\
+                                           192923,24221 173766,19421 163644,19865 153522,20309\
+                                           122483,20608 111915,23020 101347,25432 81761,37919\
+                                           69710,37919
+C 285 97 0 TEXT "Conditions" | 99944,129593 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 190399,213982 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 182869,214288 "" ""
+L 272 271 0 TEXT "Labels" | 186628,209022 1 0 0 "getPacketREn"
+S 15 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "slvCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,252232 1 0 0 "Module: slavecontroller"
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+I 588 589 0 Builtin Entry | 89368,239805
+I 587 589 0 Builtin Exit | 192962,45432
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+C 607 601 0 TEXT "Conditions" | 114440,220845 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 606 589 0 588 605 BEZIER "Transitions" | 89368,237478 89903,233730 89797,226993 90332,223245
+S 605 589 53248 ELLIPSE "States" | 91340,216824 6500 6500
+L 604 605 0 TEXT "State Labels" | 91340,216824 1 0 0 "CHK_RDY\n/10/"
+A 603 596 4 TEXT "Actions" | 174409,172080 1 0 0 "sendPacketWEn <= 1'b0;"
+W 601 589 8193 605 596 BEZIER "Transitions" | 97839,216722 109714,216534 162558,220059 167812,183210
+W 600 589 8192 596 587 BEZIER "Transitions" | 168405,170293 203966,131503 199503,89144 196184,45432
+A 599 601 16 TEXT "Actions" | 124386,212388 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+C 598 600 0 TEXT "Conditions" | 159138,161356 1 0 0 "sendPacketRdy == 1'b1"
+L 597 596 0 TEXT "State Labels" | 169718,177574 1 0 0 "NAK_STALL\n/9/"
+S 596 589 49152 ELLIPSE "States" | 168684,176772 6500 6500
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+I 620 618 0 Builtin Exit | 144780,101600
+I 619 618 0 Builtin Entry | 96520,152400
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+A 615 612 16 TEXT "Actions" | 110702,185120 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 614 612 0 TEXT "Conditions" | 69153,194735 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+W 613 589 8195 605 617 BEZIER "Transitions" | 86536,212447 76974,203420 61686,186612 53042,177585
+W 612 589 8194 605 596 BEZIER "Transitions" | 91984,210359 90899,202871 142592,172810 163035,179986
+L 639 640 0 TEXT "State Labels" | 125814,48840 1 0 0 "GET_RESP\n/12/"
+A 638 631 16 TEXT "Actions" | 118603,107061 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+A 637 630 16 TEXT "Actions" | 36344,101376 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+C 636 630 0 TEXT "Conditions" | 29568,129096 1 0 0 "USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+W 631 589 8194 617 629 BEZIER "Transitions" | 54075,173680 59927,171524 83885,163128 122946,146882\
+                                              162008,130636 145376,121704 139603,106244 133831,90784\
+                                              72380,75586 70378,71274
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+                                              37884,87516 41041,76736 44198,65956 54978,65340\
+                                              57981,65109 60984,64878 60379,64505 60995,64351
+S 629 589 61440 ELLIPSE "States" | 67392,65502 6500 6500
+L 628 629 0 TEXT "State Labels" | 67392,65502 1 0 0 "DATA\n/11/"
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/13/"
+S 654 559 69632 ELLIPSE "States" | 92422,152802 6500 6500
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+C 652 651 0 TEXT "Conditions" | 124856,135409 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+I 650 559 0 Builtin Exit | 194044,45058
+I 649 559 0 Builtin Entry | 37971,243103
+C 647 646 0 TEXT "Conditions" | 140247,52755 1 0 0 "getPacketRdy == 1'b1"
+W 646 589 0 640 587 BEZIER "Transitions" | 132288,49411 139757,47794 182271,47049 189740,45432
+A 645 640 4 TEXT "Actions" | 108652,38924 1 0 0 "getPacketREn <= 1'b0;"
+A 644 641 16 TEXT "Actions" | 75293,54584 1 0 0 "getPacketREn <= 1'b1;"
+C 643 641 0 TEXT "Conditions" | 73811,60869 1 0 0 "sendPacketRdy == 1'b1"
+A 642 629 4 TEXT "Actions" | 76076,71808 1 0 0 "sendPacketWEn <= 1'b0;"
+W 641 589 0 629 640 BEZIER "Transitions" | 73191,62566 81815,59948 110822,52759 119446,50141
+S 640 589 65536 ELLIPSE "States" | 125814,48840 6500 6500
+I 381 377 0 Builtin Exit | 206487,14249
+I 380 377 0 Builtin Entry | 48940,236580
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 376 6 94212 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+I 96 722 0 Builtin Reset | 76296,129336
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/14/"
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+S 656 559 73728 ELLIPSE "States" | 109789,85208 5889 6500
+I 399 377 0 Builtin Link | 54419,17564
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+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
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+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
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+                                              36935,95064 38880,77714 40826,60365 38327,20823\
+                                              54419,15564
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+                                              46511,172964 33727,90292 34975,71611 36223,52930\
+                                              35724,34993 37785,28932 39847,22872 46307,16188\
+                                              54419,15564
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+I 701 699 0 Builtin Exit | 144780,101600
+I 700 699 0 Builtin Entry | 96520,152400
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 698 559 81940 ELLIPSE "Junction" | 117000,209824 3500 3500
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+W 696 559 8194 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+                                              200304,203038 205920,186346 207441,167119 208962,147892\
+                                              209430,87676 208962,71608 208494,55540 206154,51484\
+                                              204438,50041 202722,48598 199528,45916 197266,45058
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+                                              39220,148925 36609,140943 36571,133460 36533,125977\
+                                              38989,104026 47738,97617 56488,91209 87662,87731\
+                                              103933,85889
+C 693 692 0 TEXT "Conditions" | 108065,184348 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 692 559 8193 698 654 BEZIER "Transitions" | 115978,206479 112866,179807 96893,185826 93781,159154
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+S 690 559 77824 ELLIPSE "States" | 98991,238090 6500 6500
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/15/"
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+                                              69948,104476 47394,95074 43302,84878 39210,74682\
+                                              42917,24960 54419,15564
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+I 423 421 0 Builtin Exit | 144780,101600
+I 422 421 0 Builtin Entry | 96520,152400
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+                                           108160,233400 112640,227800 113920,224400 115200,221000\
+                                           116013,213096 116333,209096
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+I 727 722 0 Builtin Exit | 144780,101600
+I 726 722 0 Builtin Entry | 96520,152400
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;"
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/16/"
+S 723 722 90112 ELLIPSE "States" | 120650,127000 6500 6500
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/18/"
+S 462 377 102400 ELLIPSE "States" | 94684,51331 6500 6500
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[3:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+C 468 457 0 TEXT "Conditions" | 76387,38022 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS  &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+                                              46860,73975 46530,57145 47396,48771 48262,40398\
+                                              52522,23896 54419,15564
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+K 788 786 0 TEXT "Comments" | 118800,50912 1 0 0 "Insert delay to allow USBEndPControlReg to update"
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+S 786 377 98304 ELLIPSE "States" | 123152,53144 6500 6500
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/17/"
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+                                            105236,81091 81842,75191 69908,73378
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+                                            60717,97705 62441,84600 62616,78575
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+                                              53866,34676 56339,23332 57169,17564
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+                                           209214,43082 209522,23062 208983,17094 208444,11127\
+                                           205980,7277 191773,6353 177567,5429 123205,5583\
+                                           106804,9317 90403,13052 79161,27836 75696,31763\
+                                           72231,35690 70888,36159 69579,36621
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+C 535 532 0 TEXT "Conditions" | 73577,60437 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1"
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlaveWrap.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlaveWrap.v	(revision 264)
@@ -0,0 +1,205 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlaveWrap.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. Enable connection to Avalon bus
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostSlaveWrap.v,v 1.1 2004-12-18 14:57:10 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+//
+
+module usbHostSlaveWrap(
+  clk, 
+  reset,
+  address, 
+  writedata, 
+  readdata, 
+  write, 
+  read,
+  waitrequest,
+  chipselect,
+  irq,
+  USBWireVPI,
+  USBWireVMI,
+  USBWireDataInTick,
+  USBWireVPO,
+  USBWireVMO,
+  USBWireDataOutTick,
+  USBWireOutEn_n,
+  USBFullSpeed,
+  DPlusPullUp,
+  DMinusPullUp
+   );
+
+input clk;
+input reset;
+input [7:0] address; 
+input [7:0] writedata; 
+output [7:0] readdata; 
+input write; 
+input read;
+output waitrequest;
+input chipselect;
+output irq;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+output DPlusPullUp;
+output DMinusPullUp;
+
+wire clk;
+wire reset;
+wire [7:0] address; 
+wire [7:0] writedata; 
+wire [7:0] readdata; 
+wire write; 
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+wire DPlusPullUp;
+wire DMinusPullUp;
+
+//internal wiring 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+             hostResumeIntOut | hostTransDoneIntOut |
+             slaveSOFRxedIntOut | slaveResetEventIntOut |
+             slaveResumeIntOut | slaveTransDoneIntOut |
+             slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut; 
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+assign USBFullSpeed = 1'b1;
+assign DPlusPullUp = 1'b1;
+assign DMinusPullUp = 1'bz;
+
+//Parameters declaration: 
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+  .clk(clk),
+  .rst(reset),
+  .address_i(address),
+  .data_i(writedata),
+  .data_o(readdata),
+  .writeEn(write),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut));
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifo.v	(revision 264)
@@ -0,0 +1,123 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo read access via bus interface, fifo write access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module RxFifo(
+  clk, 
+  rst, 
+  fifoWEn, 
+  fifoFull,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataIn  );
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk; 
+wire rst; 
+wire fifoWEn; 
+wire fifoFull;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(fifoDataIn), 
+  .dataOut(dataFromFifoToBus), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+RxfifoBI u_RxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .fifoDataIn(dataFromFifoToBus),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoREn(fifoREn),
+  .fifoEmpty(fifoEmpty),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoMem.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMem.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores/usbhostslave/>               ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMem(  addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+  // Generic synchronous dual-port RAM interface
+  .rclk(clk), 
+  .rrst(1'b0), 
+  .rce(1'b1), 
+  .oe(readEn), 
+  .raddr(addrOut), 
+  .do(dataOut),
+  .wclk(clk), 
+  .wrst(1'b0), 
+  .wce(1'b1),
+  .we(writeEn), 
+  .waddr(addrIn), 
+  .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_simFifoMem (
+  .addrIn(addrIn),
+  .addrOut(addrOut),
+  .clk(clk),
+  .dataIn(dataIn),
+  .writeEn(writeEn),
+  .readEn(readEn),
+  .dataOut(dataOut));  
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/USBHostControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/USBHostControlBI.v	(revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBHostControlBI.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbHostControl_h.v"
+ 
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+  SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+  TxTransTypeReg, TxSOFEnableReg,
+  TxAddrReg, TxEndPReg, frameNumIn, 
+  RxPktStatusIn, RxPIDIn,
+  connectStateIn,
+  SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+  hostControlSelect,
+  clrTransReq,
+  preambleEn,
+  SOFSync,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  transReq
+  );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output transReq;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg transReq;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//sync write demux
+always @(posedge clk)
+begin
+  clrSOFReq <= 1'b0;
+  clrConnEvtReq <= 1'b0;
+  clrResInReq <= 1'b0;
+  clrTransDoneReq <= 1'b0;
+  setTransReq <= 1'b0;
+  if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+  begin
+    case (address)
+      `TX_CONTROL_REG : begin
+        preambleEn <= dataIn[2];
+        SOFSync <= dataIn[1];
+        setTransReq <= dataIn[0];
+      end
+      `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
+      `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+      `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[0];
+      `TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
+      `TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
+      `INTERRUPT_STATUS_REG :  begin
+        clrSOFReq <= dataIn[3];
+        clrConnEvtReq <= dataIn[2];
+        clrResInReq <= dataIn[1];
+        clrTransDoneReq <= dataIn[0];
+      end
+      `INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[3:0];
+    endcase
+  end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+  if (SOFSentIn == 1'b1)
+    SOFSentInt <= 1'b1;
+  else if (clrSOFReq == 1'b1)
+    SOFSentInt <= 1'b0;
+    
+  if (connEventIn == 1'b1)
+    connEventInt <= 1'b1;
+  else if (clrConnEvtReq == 1'b1)
+    connEventInt <= 1'b0;
+    
+  if (resumeIntIn == 1'b1)
+    resumeInt <= 1'b1;
+  else if (clrResInReq == 1'b1)
+    resumeInt <= 1'b0;  
+
+  if (transDoneIn == 1'b1)
+    transDoneInt <= 1'b1;
+  else if (clrTransDoneReq == 1'b1)
+    transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end  
+  
+//transaction request set/clear
+always @(posedge clk)
+begin
+  if (setTransReq == 1'b1)
+    transReq <= 1'b1;
+  else if (clrTransReq == 1'b1)
+    transReq <= 1'b0;
+end  
+  
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+  TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+  fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+  
+// async read mux
+always @(address or
+  TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+  TxAddrReg or TxEndPReg or frameNumIn or 
+  SOFSentInt or connEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+  preambleEn or SOFSync or transReq)
+begin
+  case (address)
+      `TX_CONTROL_REG : dataOut <= {5'b00000, preambleEn, SOFSync, transReq} ;
+      `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
+      `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+      `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
+      `TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
+      `TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
+      `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumIn[10:8]};
+      `FRAME_NUM_LSB_REG : dataOut <= frameNumIn[7:0];
+      `INTERRUPT_STATUS_REG :  dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+      `INTERRUPT_MASK_REG  : dataOut <= {4'h0, interruptMaskReg};
+      `RX_STATUS_REG  : dataOut <= RxPktStatusIn;
+      `RX_PID_REG  : dataOut <= {4'b0000, RxPIDIn};
+      `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.v	(revision 264)
@@ -0,0 +1,397 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// getpacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
+input   clk;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  [7:0]RXPktStatus;
+
+wire    clk;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+reg     [7:0]RXPktStatus;
+wire    [7:0]RXStreamStatusIn;
+wire    SIERxTimeOut;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
+begin
+  NextState_getPkt <= CurrState_getPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  case (CurrState_getPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      if (SIERxTimeOut == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_getPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_getPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_getPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+        next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_getPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (RXFifoFull == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_getPkt <= `START_GP;
+  else
+    CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RxPID <= 4'h0;
+    RXOverflow <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXByteOld <= 8'h00;
+    RXTimeOut <= 1'b0;
+  end
+  else 
+  begin
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RxPID <= next_RxPID;
+    RXOverflow <= next_RXOverflow;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXByteOld <= next_RXByteOld;
+    RXTimeOut <= next_RXTimeOut;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.v	(revision 264)
@@ -0,0 +1,242 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hctxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+input   [7:0]SOFCntlCntl;
+input   [7:0]SOFCntlData;
+input   SOFCntlReq;
+input   SOFCntlWEn;
+output  directCntlGnt;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortWEnable;
+output  sendPacketGnt;
+output  SOFCntlGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+reg     HCTxPortWEnable, next_HCTxPortWEnable;
+wire    rst;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+wire    [7:0]SOFCntlCntl;
+wire    [7:0]SOFCntlData;
+reg     SOFCntlGnt, next_SOFCntlGnt;
+wire    SOFCntlReq;
+wire    SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg  [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+  NextState_HCTxArb = CurrState_HCTxArb;
+  // Set default values for outputs and signals
+  next_SOFCntlGnt <= SOFCntlGnt;
+  next_sendPacketGnt <= sendPacketGnt;
+  next_directCntlGnt <= directCntlGnt;
+  next_muxCntl <= muxCntl;
+  case (CurrState_HCTxArb)  // synopsys parallel_case full_case
+    `START_HARB:
+    begin
+      NextState_HCTxArb = `WAIT_REQ;
+    end
+    `WAIT_REQ:
+    begin
+      if (SOFCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb = `SEND_SOF;
+        next_SOFCntlGnt <= 1'b1;
+        next_muxCntl <= `SOF_CTRL_MUX;
+      end
+      else if (sendPacketReq == 1'b1)
+      begin
+        NextState_HCTxArb = `SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxCntl <= `SEND_PACKET_MUX;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb = `DIRECT_CONTROL;
+        next_directCntlGnt <= 1'b1;
+        next_muxCntl <= `DIRECT_CTRL_MUX;
+      end
+    end
+    `SEND_SOF:
+    begin
+      if (SOFCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_SOFCntlGnt <= 1'b0;
+      end
+    end
+    `SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `DIRECT_CONTROL:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_HCTxArb = `START_HARB;
+  else
+    CurrState_HCTxArb = NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFCntlGnt = 1'b0;
+    sendPacketGnt = 1'b0;
+    directCntlGnt = 1'b0;
+    muxCntl = 2'b00;
+  end
+  else 
+  begin
+    SOFCntlGnt = next_SOFCntlGnt;
+    sendPacketGnt = next_sendPacketGnt;
+    directCntlGnt = next_directCntlGnt;
+    muxCntl = next_muxCntl;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_04_alpha/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_04_alpha/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifoBI.v	(revision 264)
@@ -0,0 +1,124 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+  address, 
+  writeEn, 
+  strobe_i,
+  clk, 
+  rst, 
+  fifoSelect,
+  fifoDataIn,
+  busDataIn, 
+  busDataOut,
+  fifoREn,
+  fifoEmpty,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoREn;
+input fifoEmpty;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoREn;
+wire fifoEmpty;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)
+begin
+  case (address)
+      `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00; 
+  endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b0 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoREn <= 1'b1;
+  else
+    fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoRTL.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoRTL.v	(revision 264)
@@ -0,0 +1,139 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoRTL.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+////  User must check full and empty flags before accessing fifo
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input rst;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoWEn;
+input fifoREn;
+output fifoFull;
+output fifoEmpty;
+input forceEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire clk;
+wire rst;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg  [15:0]numElementsInFifo;
+
+
+// local registers
+reg  [ADDR_WIDTH-1:0]bufferInIndex;
+reg  [ADDR_WIDTH-1:0]bufferOutIndex;
+reg  [ADDR_WIDTH:0]bufferCnt;
+reg  fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || forceEmpty == 1'b1)
+  begin
+    bufferCnt <= 0;
+    fifoFull <= 1'b0;
+    fifoEmpty <= 1'b1;
+    bufferInIndex <= 0;
+    bufferOutIndex <= 0;
+    fifoREnDelayed <= 1'b0;
+  end
+    else
+    begin
+      if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        dataOut <= dataFromMem;
+      end
+      fifoREnDelayed <= fifoREn;
+      if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
+        bufferCnt <= bufferCnt + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end 
+      else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferCnt <= bufferCnt - 1;
+        bufferOutIndex <= bufferOutIndex + 1;
+      end
+      else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferOutIndex <= bufferOutIndex + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end
+      if (bufferCnt[ADDR_WIDTH] == 1'b1)
+        fifoFull <= 1'b1;
+      else
+        fifoFull <= 1'b0;
+      if (|bufferCnt == 1'b0) 
+        fifoEmpty <= 1'b1;
+      else
+        fifoEmpty <= 1'b0;
+    end
+end
+
+//pad bufferCnt with leading zeroes
+always @(bufferCnt) begin
+  numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
+end
+
+fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_fifoMem (
+  .addrIn(bufferInIndex),
+  .addrOut(bufferOutIndex),
+  .clk(clk),
+  .dataIn(dataIn),
+  .writeEn(fifoWEn),
+  .readEn(fifoREn),
+  .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// directControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+END
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+I 13 6 0 Builtin Reset | 48900,215400
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
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+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
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+                                           55748,105011 58848,106911
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+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1"
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
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+                                       47285,153175 50048,167625 56316,171290 62585,174956\
+                                       84856,175714 96012,175820
+I 124 79 0 Builtin Entry | 109800,175900
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+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
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+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]"
+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
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+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
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+                                        120424,175336 108976,175654
+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
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+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
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+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
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+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.asf	(revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hctxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
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+W 28 6 0 12 10 BEZIER "Transitions" | 186560,297376 167155,311353 168429,333163 167686,340659\
+                                      166944,348155 168507,364217 173450,370590 178394,376963\
+                                      186275,384997 193806,383684 201338,382371 213515,373400\
+                                      220004,369229
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n  `SOF_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= SOFCntlWEn;\n    HCTxPortData <= SOFCntlData;\n    HCTxPortCntl <= SOFCntlCntl;\n  end\n  `DIRECT_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= directCntlWEn;\n    HCTxPortData <= directCntlData;\n    HCTxPortCntl <= directCntlCntl;\n  end\n  `SEND_PACKET_MUX :\n  begin  \n    HCTxPortWEnable <= sendPacketWEn;\n    HCTxPortData <= sendPacketData;\n    HCTxPortCntl <= sendPacketCntl;\n  end\n  default :\n  begin  \n    HCTxPortWEnable <= 1'b0;\n    HCTxPortData <= 8'h00;\n    HCTxPortCntl <= 8'h00;\n  end\nendcase	\nend"
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
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+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
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+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
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+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
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+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+I 89 0 130 Builtin Signal | 141050,528812 "" ""
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286404,388600 275724,388298\
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+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/rxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/rxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// rxStatusMonitor.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      connectionEventOut <= 1'b1;
+    else
+      connectionEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.v	(revision 264)
@@ -0,0 +1,177 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketarbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input   clk;
+input   [3:0]HC_PID;
+input   HC_SP_WEn;
+input   HCTxReq;
+input   rst;
+input   SOF_SP_WEn;
+input   SOFTxReq;
+output  HCTxGnt;
+output  [3:0]sendPacketPID;
+output  sendPacketWEnable;
+output  SOFTxGnt;
+
+wire    clk;
+wire    [3:0]HC_PID;
+wire    HC_SP_WEn;
+reg     HCTxGnt, next_HCTxGnt;
+wire    HCTxReq;
+wire    rst;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+reg     sendPacketWEnable, next_sendPacketWEnable;
+wire    SOF_SP_WEn;
+reg     SOFTxGnt, next_SOFTxGnt;
+wire    SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC  == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+  NextState_sendPktArb <= CurrState_sendPktArb;
+  // Set default values for outputs and signals
+  next_HCTxGnt <= HCTxGnt;
+  next_SOFTxGnt <= SOFTxGnt;
+  next_muxSOFNotHC <= muxSOFNotHC;
+  case (CurrState_sendPktArb)  // synopsys parallel_case full_case
+    `HC_ACT:
+    begin
+      if (HCTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_HCTxGnt <= 1'b0;
+      end
+    end
+    `SOF_ACT:
+    begin
+      if (SOFTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_SOFTxGnt <= 1'b0;
+      end
+    end
+    `SARB_WAIT_REQ:
+    begin
+      if (SOFTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `SOF_ACT;
+        next_SOFTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b1;
+      end
+      else if (HCTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `HC_ACT;
+        next_HCTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_sendPktArb <= `SARB_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktArb <= `START_SARB;
+  else
+    CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxGnt <= 1'b0;
+    SOFTxGnt <= 1'b0;
+    muxSOFNotHC <= 1'b0;
+  end
+  else 
+  begin
+    HCTxGnt <= next_HCTxGnt;
+    SOFTxGnt <= next_SOFTxGnt;
+    muxSOFNotHC <= next_muxSOFNotHC;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.asf	(revision 264)
@@ -0,0 +1,243 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=225
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
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+L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+S 47 6 36864 ELLIPSE "States" | 115848,16910 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP\n/5/"
+S 45 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,46294 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,46294 1 0 0 "DATA0_DATA1"
+S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500
+L 42 43 0 TEXT "State Labels" | 116148,48718 1 0 0 "SEND_SOF"
+S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500
+L 40 41 0 TEXT "State Labels" | 61608,50536 1 0 0 "OUT_IN_SETUP"
+W 39 25 0 33 29 BEZIER "Transitions" | 78151,174526 94720,161687 125355,134759 141924,121920
+A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 37 34 16 TEXT "Actions" | 66378,203896 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= PIDNotPID;\nHCTxPortCntl <= `TX_PACKET_START;"
+C 36 34 0 TEXT "Conditions" | 74012,211530 1 0 0 "HCTxPortRdy == 1'b1"
+W 34 25 0 26 33 BEZIER "Transitions" | 71729,211913 72078,205195 72736,192521 73085,185803
+S 33 25 20480 ELLIPSE "States" | 73797,179351 6500 6500
+L 32 33 0 TEXT "State Labels" | 73797,179351 1 0 0 "FIN\n/4/"
+H 58 43 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,5152 212900,250284
+H 51 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 50 6 8193 21 45 BEZIER "Transitions" | 119411,90353 134284,80236 162142,60327 177015,50210
+W 49 6 8194 21 43 BEZIER "Transitions" | 114327,87507 114704,79202 115453,63508 115830,55203
+W 48 6 8195 21 41 BEZIER "Transitions" | 108751,90198 97879,81365 77125,63914 66253,55081
+C 79 48 0 TEXT "Conditions" | 70608,88862 1 0 0 "PID == `OUT || \nPID == `IN || \nPID == `SETUP"
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nHCTxPortReq <= 1'b0;"
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888
+W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311
+W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500
+L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
+S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
+I 84 51 0 Builtin Entry | 48374,241112
+I 83 51 0 Builtin Exit | 161275,73621
+W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
+C 81 50 0 TEXT "Conditions" | 136066,86256 1 0 0 "PID == `DATA0 || PID == `DATA1"
+C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
+S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
+L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
+W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
+A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+I 110 58 0 Builtin Exit | 176204,35771
+I 111 58 0 Builtin Entry | 69864,225148
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1;	 \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+                                          48213,88528 42471,75064 41184,67490 39897,59917\
+                                          40491,43087 47668,36800 54846,30514 82962,22198\
+                                          91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+                                          200128,135446 205472,144130 205681,151728 205890,159327\
+                                          201380,181037 194241,189595 187102,198154 163054,210680\
+                                          152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.asf	(revision 264)
@@ -0,0 +1,150 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=153
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketcheckpreamble\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 32
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+A 45 44 16 TEXT "Actions" | 74811,210616 1 0 0 "fullSpeedBitRate <= 1'b1;\nfullSpeedPolarity <= 1'b1;\ngrabLineControl <= 1'b1;"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 68 37 BEZIER "Transitions" | 95534,53084 101453,45264 180021,53114 185941,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 93181,145786 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 55 60 BEZIER "Transitions" | 89225,146684 89301,143318 91477,99456 91230,95807
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 59 56 16 TEXT "Actions" | 87075,172050 1 0 0 "sendPacketWEn <= 1'b0;"
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88382,164186 88295,159636
+S 55 33 20480 ELLIPSE "States" | 88650,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88650,153150 1 0 0 "WAIT_RDY2\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "WAIT_RDY3\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+A 66 65 16 TEXT "Actions" | 90202,77286 1 0 0 "sendPacketWEn <= 1'b0;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+A 64 62 16 TEXT "Actions" | 78524,125856 1 0 0 "fullSpeedBitRate <= 1'b1;"
+A 72 39 16 TEXT "Actions" | 141267,52580 1 0 0 "grabLineControl <= 1'b0;"
+C 73 39 0 TEXT "Conditions" | 97529,56755 1 0 0 "sendPacketRdy == 1'b1"
+L 74 75 0 TEXT "Labels" | 35624,223586 1 0 0 "grabLineControl"
+I 75 0 2 Builtin OutPort | 29624,223586 "" ""
+L 76 77 0 TEXT "Labels" | 37072,218796 1 0 0 "fullSpeedPolarity"
+I 77 0 2 Builtin OutPort | 29360,218796 "" ""
+L 78 79 0 TEXT "Labels" | 35397,214093 1 0 0 "fullSpeedBitRate"
+I 79 0 2 Builtin OutPort | 29397,214093 "" ""
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+                                        94907,51569 61918,50756 52575,52503 43232,54250\
+                                        38843,62050 37706,72734 36569,83418 36406,118357\
+                                        40062,129609 43718,140862 58507,150938 67687,153172\
+                                        76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 95904,234688 "" ""
+L 150 151 0 TEXT "Labels" | 101904,234688 1 0 0 "preAmbleEnable"
+K 149 75 0 TEXT "Comments" | 60868,223364 1 0 0 "mux select"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nfullSpeedBitRate <= 1'b0;\nfullSpeedPolarity <= 1'b0;\ngrabLineControl <= 1'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.asf	(revision 264)
@@ -0,0 +1,98 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=73
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// softransmit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+F 6 0 671089152 54 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+                                     119442,151760 119430,151725 119430,151571
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+I 16 6 0 Builtin Reset | 76112,190530
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;"
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+W 51 6 0 26 11 BEZIER "Transitions" | 117404,14128 103585,14128 76675,12449 68441,16586\
+                                      60208,20724 54912,37274 53629,49148 52346,61023\
+                                      52495,91978 54333,104221 56172,116465 66907,131666\
+                                      73940,137333 80974,143001 92272,144264 98160,144352\
+                                      104049,144440 109926,143957 113732,143626
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+A 67 51 16 TEXT "Actions" | 33349,35565 1 0 0 "sendPacketArbiterReq <= 1'b0;"
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+                                         105450,47318 105450,38252 107207,34228 108965,30205\
+                                         115846,23167 119361,19652
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMux.v	(revision 264)
@@ -0,0 +1,168 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module hostSlaveMux (
+  SIEPortCtrlInToSIE,
+  SIEPortCtrlInFromHost,
+  SIEPortCtrlInFromSlave,
+  SIEPortDataInToSIE, 
+  SIEPortDataInFromHost, 
+  SIEPortDataInFromSlave, 
+  SIEPortWEnToSIE, 
+  SIEPortWEnFromHost, 
+  SIEPortWEnFromSlave, 
+  fullSpeedPolarityToSIE,
+  fullSpeedPolarityFromHost,
+  fullSpeedPolarityFromSlave,
+  fullSpeedBitRateToSIE,
+  fullSpeedBitRateFromHost,
+  fullSpeedBitRateFromSlave,
+  dataIn, 
+  dataOut,
+  address,
+  writeEn,
+  strobe_i,
+  clk, 
+  rst,
+  hostSlaveMuxSel  );
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE; 
+input [7:0] SIEPortDataInFromHost; 
+input [7:0] SIEPortDataInFromSlave; 
+output SIEPortWEnToSIE; 
+input SIEPortWEnFromHost; 
+input SIEPortWEnFromSlave; 
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE; 
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+reg SIEPortWEnToSIE; 
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+  SIEPortCtrlInFromHost or
+  SIEPortCtrlInFromSlave or
+  SIEPortDataInFromHost or 
+  SIEPortDataInFromSlave or 
+  SIEPortWEnFromHost or 
+  SIEPortWEnFromSlave or 
+  fullSpeedPolarityFromHost or
+  fullSpeedPolarityFromSlave or
+  fullSpeedBitRateFromHost or
+  fullSpeedBitRateFromSlave)
+begin
+  if (hostMode == 1'b1) 
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+    SIEPortDataInToSIE <=  SIEPortDataInFromHost;
+    SIEPortWEnToSIE <= SIEPortWEnFromHost;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+  end
+  else
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+    SIEPortDataInToSIE <=  SIEPortDataInFromSlave;
+    SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+  end
+end      
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(dataIn), 
+  .dataOut(dataOut),
+  .address(address),
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .hostMode(hostMode), 
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostSlave_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostSlave_h.v	(revision 264)
@@ -0,0 +1,18 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+//             control reads and writes to USB flash dongle 
+`define USBHOSTSLAVE_VERSION_NUM 8'h06
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostSlave_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf	(revision 264)
@@ -0,0 +1,572 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=957
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIETransmitter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 16
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+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 213
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+INSTHEADER 359
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+INSTHEADER 455
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+INSTHEADER 609
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+END
+INSTHEADER 717
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+END
+INSTHEADER 911
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin OutPort | 64372,246658 "" ""
+L 821 822 0 TEXT "Labels" | 70372,246658 1 0 0 "TxByteOutCtrl[7:0]"
+I 820 0 130 Builtin OutPort | 64372,251298 "" ""
+L 819 820 0 TEXT "Labels" | 70372,251298 1 0 0 "TxByteOut[7:0]"
+I 818 0 2 Builtin InPort | 66692,255938 "" ""
+L 817 818 0 TEXT "Labels" | 72692,255938 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin OutPort | 64372,260578 "" ""
+L 15 16 0 TEXT "State Labels" | 115356,124706 1 0 0 "RES_ST"
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "STX_CHK_ST\n/23/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: SIETransmitter"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "SIETx"
+L 544 543 0 TEXT "State Labels" | 63328,102539 1 0 0 "WAIT_WIRE\n/45/"
+W 547 458 0 532 530 BEZIER "Transitions" | 71250,71190 82482,70839 157007,69015 168239,68664
+A 548 547 16 TEXT "Actions" | 109101,76185 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 549 458 0 534 532 BEZIER "Transitions" | 166590,101641 155007,95674 81782,81027 70199,75060
+A 550 549 16 TEXT "Actions" | 89913,93969 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+C 552 547 0 TEXT "Conditions" | 72597,69165 1 0 0 "USBWireRdy == 1'b1"
+C 553 549 0 TEXT "Conditions" | 134841,94437 1 0 0 "USBWireRdy == 1'b1"
+A 554 534 4 TEXT "Actions" | 157773,116901 1 0 0 "USBWireWEn <= 1'b0;"
+W 555 458 0 543 534 BEZIER "Transitions" | 69825,102352 80940,102469 155253,103091 166368,103208
+A 556 555 16 TEXT "Actions" | 112553,111735 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+C 557 555 0 TEXT "Conditions" | 72988,107460 1 0 0 "USBWireRdy == 1'b1"
+W 545 458 0 530 540 BEZIER "Transitions" | 168710,66267 156425,60534 83183,49066 70898,43333
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_SIETX\n/22/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 71500,215836 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[4:0]"
+I 840 0 130 Builtin Signal | 71500,220244 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 838 0 130 Builtin Signal | 71732,224652 "" ""
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+A 836 63 4 TEXT "Actions" | 101212,188184 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,123104 6500 6500
+A 562 532 4 TEXT "Actions" | 37965,60741 1 0 0 "USBWireWEn <= 1'b0;"
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/35/"
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/9/"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+I 572 458 0 Builtin Entry | 44780,253519
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+A 563 530 4 TEXT "Actions" | 161517,83673 1 0 0 "USBWireWEn <= 1'b0;"
+W 574 458 0 567 543 BEZIER "Transitions" | 44298,153135 48358,141709 56556,119871 60616,108445
+A 835 9 4 TEXT "Actions" | 153876,205564 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 5'h0;"
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 606 489 0 Builtin Exit | 138120,51311
+I 599 489 0 Builtin Entry | 81144,219546
+I 324 0 130 Builtin InPort | 126267,236303 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+S 63 6 0 ELLIPSE "States" | 112744,173179 6500 6500
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "STX_WAIT_BYTE\n/24/"
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+                                      42326,129670 44202,125650 52711,124511 61220,123372\
+                                      92777,123293 108857,123025
+I 872 360 0 Builtin Exit | 188676,86316
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114123,147554 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111818,198264 6500 6500
+L 608 609 0 TEXT "State Labels" | 111818,198264 1 0 0 "PID"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+                                        161730,108850 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 135270,157360\
+                                        132480,162850 129690,168340 122852,170455 118982,171355
+A 78 65 16 TEXT "Actions" | 54348,179673 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+C 66 65 0 TEXT "Conditions" | 67688,166172 1 0 0 "SIEPortWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59299,174571 47927,176730
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/1/"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 5'h7"
+W 895 224 8194 891 897 BEZIER "Transitions" | 101794,119505 95833,118125 85494,117151 81290,118312\
+                                              77086,119473 72191,126878 71751,132901 71312,138925\
+                                              74451,155618 76866,160637 79282,165657 85808,169046\
+                                              89165,169297 92522,169548 98692,166980 102143,165788
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 636 610 0 Builtin Entry | 71380,236621
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 634 626 0 TEXT "State Labels" | 112740,88546 1 0 0 "CRC"
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112740,88546 6500 6500
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 114123,147554 1 0 0 "BYTE1"
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 68542,191838 89078,185356 109614,178874
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 363 360 0 Builtin Entry | 26888,244668
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+                                        43361,99065 46384,95576 54928,94878 63472,94181\
+                                        94207,96080 109784,96428
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/39/"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/32/"
+I 908 224 0 Builtin Entry | 85162,237767
+I 909 224 0 Builtin Exit | 108872,88817
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+I 914 912 0 Builtin Exit | 129540,111760
+I 913 912 0 Builtin Entry | 86360,167640
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/27/"
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+W 651 489 0 626 606 BEZIER "Transitions" | 115586,82704 120772,74867 130139,59148 135325,51311
+W 650 489 0 617 626 BEZIER "Transitions" | 113848,141065 113272,128964 113115,107129 112539,95028
+W 649 489 0 609 617 BEZIER "Transitions" | 111887,191768 112232,181972 113177,163821 113522,154025
+W 648 489 0 599 609 BEZIER "Transitions" | 84906,219546 91705,215743 99788,205923 106587,202120
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+I 645 610 0 Builtin Exit | 114540,97930
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/33/"
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/10/"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 5'h0;"
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+S 939 633 8192 ELLIPSE "States" | 39277,179580 6500 6500
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/46/"
+I 671 624 0 Builtin Exit | 116402,43935
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+                                           104039,47385 110550,45085 113597,43935
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+I 663 624 0 Builtin Entry | 59190,254840
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/29/"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+W 956 360 0 363 453 BEZIER "Transitions" | 30788,244668 34532,239130 40619,228589 44363,223051
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+S 952 624 16384 ELLIPSE "States" | 35474,185224 6500 6500
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/48/"
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+S 947 734 12288 ELLIPSE "States" | 160390,197270 6500 6500
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/47/"
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+I 682 633 0 Builtin Exit | 119917,39891
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/26/"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/38/"
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+A 414 413 16 TEXT "Actions" | 50880,235676 1 0 0 "USBWireReq <= 1'b1;\ni <= 5'h0;"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/40/"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/0/"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;	\ni <= i + 1'b1;"
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/37/"
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/5/"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/30/"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "S1\n/14/"
+W 422 17 8194 407 411 BEZIER "Transitions" | 53385,128518 47424,127138 37085,126164 32881,127325\
+                                             28677,128486 23782,135891 23342,141914 22903,147938\
+                                             26042,164631 28457,169650 30873,174670 37399,178059\
+                                             40756,178310 44113,178561 50283,175993 53734,174801
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+I 418 17 0 Builtin Exit | 145044,30588
+I 417 17 0 Builtin Entry | 44586,243455
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/31/"
+W 425 17 0 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+C 426 425 0 TEXT "Conditions" | 60723,121216 1 0 0 "i == `RESUME_LEN"
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "S3\n/15/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 429 430 0 TEXT "State Labels" | 61659,61312 1 0 0 "S4\n/16/"
+S 430 17 0 ELLIPSE "States" | 61659,61312 6500 6500
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "S5\n/17/"
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+I 716 471 0 Builtin Entry | 83616,227615
+I 715 471 0 Builtin Exit | 140592,59380
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 713 480 0 Builtin Exit | 85376,122104
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 711 480 0 Builtin Entry | 43257,253243
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251308 41695,240089 71091,229875 69529,218656
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/6/"
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/36/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "S6\n/18/"
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+W 436 17 0 428 430 BEZIER "Transitions" | 163491,91448 151908,85481 78683,70834 67100,64867
+W 437 17 0 430 432 BEZIER "Transitions" | 68151,60997 79383,60646 153908,58822 165140,58471
+W 438 17 0 432 434 BEZIER "Transitions" | 165378,56758 153093,51025 79495,38601 67210,32868
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+C 442 436 0 TEXT "Conditions" | 131742,84244 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 69498,58972 1 0 0 "USBWireRdy == 1'b1"
+C 444 438 0 TEXT "Conditions" | 142974,49612 1 0 0 "USBWireRdy == 1'b1"
+A 445 436 16 TEXT "Actions" | 86814,83776 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 106002,65992 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 447 438 16 TEXT "Actions" | 92898,48208 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/25/"
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 731 727 0 Builtin Entry | 71380,236621
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+A 448 432 4 TEXT "Actions" | 158418,73480 1 0 0 "USBWireWEn <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34866,50548 1 0 0 "USBWireWEn <= 1'b0;"
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 123646,30705 142249,30588
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/44/"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 750 734 0 Builtin Entry | 59190,254840
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+I 744 734 0 Builtin Exit | 116402,43935
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/8/"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/34/"
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 738 727 0 Builtin Exit | 114540,97930
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+I 762 733 0 Builtin Exit | 119917,39891
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/28/"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+S 216 6 0 ELLIPSE "States" | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE\n/4/"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/2/"
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/43/"
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/41/"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/7/"
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+                                           46299,139871 48829,136075 59202,135063 69575,134052\
+                                           106314,125693 125795,125567
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+                                           46931,109511 49715,104703 60024,103501 70334,102300\
+                                           108774,103037 128002,103037
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+                                           48196,74723 50474,70169 60657,69030 70840,67892\
+                                           108432,68626 127660,68626
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+                                           48829,42592 51359,37532 61605,36267 71852,35002\
+                                           109061,35775 128289,35775
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+                                           128857,67252 162473,65260 171997,66691 181521,68123\
+                                           186003,75843 187123,97692 188244,119542 188244,199222\
+                                           184384,221196 180525,243170 165087,251388 155563,253628\
+                                           146039,255869 123379,256617 115100,254625 106821,252633\
+                                           98206,243956 92977,239599
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+                                              31250,150650 32250,89650 34750,72525 37250,55400\
+                                              46250,47900 56000,46150 65750,44400 95896,46012\
+                                              103573,44899 111250,43786 113107,43935 113607,43935
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/3/"
+I 787 733 0 Builtin Entry | 62705,250796
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/42/"
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+S 532 458 0 ELLIPSE "States" | 64758,71505 6500 6500
+L 533 532 0 TEXT "State Labels" | 64758,71505 1 0 0 "SEND_IDLE2\n/20/"
+S 534 458 0 ELLIPSE "States" | 172866,103329 6500 6500
+L 535 534 0 TEXT "State Labels" | 172866,103329 1 0 0 "SEND_IDLE1\n/19/"
+I 540 458 0 Builtin Exit | 68103,43333
+S 543 458 0 ELLIPSE "States" | 63328,102539 6500 6500
+L 531 530 0 TEXT "State Labels" | 174738,68697 1 0 0 "SEND_IDLE3\n/21/"
+S 530 458 0 ELLIPSE "States" | 174738,68697 6500 6500
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.v	(revision 264)
@@ -0,0 +1,410 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processrxbit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut);
+input   clk;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processRxBitsWEn;
+input   processRxByteRdy;
+input   rst;
+input   [1:0]RxBitsIn;
+output  processRxBitRdy;
+output  processRxByteWEn;
+output  resumeDetected;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+
+wire    clk;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processRxBitRdy, next_processRxBitRdy;
+wire    processRxBitsWEn;
+wire    processRxByteRdy;
+reg     processRxByteWEn, next_processRxByteWEn;
+reg     resumeDetected, next_resumeDetected;
+wire    rst;
+wire    [1:0]RxBitsIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg  [1:0]oldRXBits, next_oldRXBits;
+reg  [3:0]resumeWaitCnt, next_resumeWaitCnt;
+reg  [3:0]RXBitCount, next_RXBitCount;
+reg  [1:0]RxBits, next_RxBits;
+reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg  [7:0]RXByte, next_RXByte;
+reg  [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+  NextState_prRxBit <= CurrState_prRxBit;
+  // Set default values for outputs and signals
+  next_processRxByteWEn <= processRxByteWEn;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOut <= RxDataOut;
+  next_resumeDetected <= resumeDetected;
+  next_RXBitStMachCurrState <= RXBitStMachCurrState;
+  next_RxBits <= RxBits;
+  next_RXSameBitCount <= RXSameBitCount;
+  next_RXBitCount <= RXBitCount;
+  next_oldRXBits <= oldRXBits;
+  next_RXByte <= RXByte;
+  next_bitStuffError <= bitStuffError;
+  next_resumeWaitCnt <= resumeWaitCnt;
+  next_processRxBitRdy <= processRxBitRdy;
+  case (CurrState_prRxBit)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOut <= 8'h00;
+      next_resumeDetected <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_RxBits <= 2'b00;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h0;
+      next_oldRXBits <= 2'b00;
+      next_RXByte <= 8'h00;
+      next_bitStuffError <= 1'b0;
+      next_resumeWaitCnt <= 4'h0;
+      next_processRxBitRdy <= 1'b1;
+      NextState_prRxBit <= `WAIT_BITS;
+    end
+    `WAIT_BITS:
+    begin
+      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+      begin
+        NextState_prRxBit <= `DATA_RX_CHK_SE0;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+      begin
+        NextState_prRxBit <= `RES_RX_CHK;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+      begin
+        NextState_prRxBit <= `RES_END_CHK1;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+      begin
+        NextState_prRxBit <= `IDLE_CHK_KBIT;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+    end
+    `IDLE_FIRST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h1;
+      next_oldRXBits <= RxBits;
+      //zero is always the first RZ data bit of a new packet
+      next_RXByte <= 8'h00;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `IDLE_CHK_KBIT:
+    begin
+      if (RxBits == KBit)
+      begin
+        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `IDLE_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `IDLE_FIRST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_START;
+        //start of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_LAST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_CHK_SE0:
+    begin
+      next_bitStuffError <= 1'b0;
+      if (RxBits == `SE0)
+      begin
+        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
+        begin
+        next_RXSameBitCount <= RXSameBitCount + 1'b1;
+        //inc 'RXSameBitCount'
+        if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+        next_bitStuffError <= 1'b1;
+        //flag 'bitStuffError'
+        else                                          //else no bit stuffing error
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= { 1'b1, RXByte[7:1]};
+        //RZ bit <= 1 (ie no change in 'RxBits')
+        end
+        end
+        else                                            //else current 'RxBits' are different from old 'RxBits'
+        begin
+        if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != 4'h7) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= {1'b0, RXByte[7:1]};
+        //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+        end
+        next_RXSameBitCount <= 4'h0;
+        //reset 'RXSameBitCount'
+        end
+        next_oldRXBits <= RxBits;
+      end
+    end
+    `DATA_RX_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_LAST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_STOP;
+        //end of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_DATA_DESTUFF:
+    begin
+      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+      end
+      else if (bitStuffError == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `DATA_RX_BYTE_SEND2:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_BYTE_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+        next_RXBitCount <= 4'h0;
+        next_RxDataOut <= RXByte;
+        next_RxCtrlOut <= `DATA_STREAM;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_ERROR_CHK_RES:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      if (RxBits == JBit)                           //if current bit is a JBit, then
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      //next state is idle
+      else                                          //else
+      begin
+      next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+      //check for resume
+      next_resumeWaitCnt <= 0;
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_ERROR_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `RES_RX_CHK:
+    begin
+      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      else
+      begin
+      next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+      //if we've waited long enough, then
+      if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
+      begin
+      next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+      next_resumeDetected <= 1'b1;
+      //report resume detected
+      end
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `RES_END_CHK1:
+    begin
+      if (RxBits != KBit)  //line must leave KBit state for the end of resume
+      begin
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_resumeDetected <= 1'b0;
+      //clear resume detected flag
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxBit <= `START;
+  else
+    CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processRxByteWEn <= 1'b0;
+    RxCtrlOut <= 8'h00;
+    RxDataOut <= 8'h00;
+    resumeDetected <= 1'b0;
+    processRxBitRdy <= 1'b1;
+    RXBitStMachCurrState <= `IDLE_BIT_ST;
+    RxBits <= 2'b00;
+    RXSameBitCount <= 4'h0;
+    RXBitCount <= 4'h0;
+    oldRXBits <= 2'b00;
+    RXByte <= 8'h00;
+    bitStuffError <= 1'b0;
+    resumeWaitCnt <= 4'h0;
+  end
+  else 
+  begin
+    processRxByteWEn <= next_processRxByteWEn;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOut <= next_RxDataOut;
+    resumeDetected <= next_resumeDetected;
+    processRxBitRdy <= next_processRxBitRdy;
+    RXBitStMachCurrState <= next_RXBitStMachCurrState;
+    RxBits <= next_RxBits;
+    RXSameBitCount <= next_RXSameBitCount;
+    RXBitCount <= next_RXBitCount;
+    oldRXBits <= next_oldRXBits;
+    RXByte <= next_RXByte;
+    bitStuffError <= next_bitStuffError;
+    resumeWaitCnt <= next_resumeWaitCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.v	(revision 264)
@@ -0,0 +1,431 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processTxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, fullSpeedRate, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   fullSpeedRate;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteWEn;
+input   rst;
+input   [7:0]TxByteCtrlIn;
+input   [7:0]TxByteIn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  processTxByteRdy;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+wire    fullSpeedRate;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processTxByteRdy, next_processTxByteRdy;
+wire    processTxByteWEn;
+wire    rst;
+wire    [7:0]TxByteCtrlIn;
+wire    [7:0]TxByteIn;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [3:0]i, next_i;
+reg  [7:0]TxByte, next_TxByte;
+reg  [7:0]TxByteCtrl, next_TxByteCtrl;
+reg  [1:0]TXLineState, next_TXLineState;
+reg  [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+
+reg [4:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
+begin
+  NextState_prcTxB <= CurrState_prcTxB;
+  // Set default values for outputs and signals
+  next_processTxByteRdy <= processTxByteRdy;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_USBWireReq <= USBWireReq;
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_TxByte <= TxByte;
+  next_TxByteCtrl <= TxByteCtrl;
+  next_TXLineState <= TXLineState;
+  next_TXOneCount <= TXOneCount;
+  case (CurrState_prcTxB)  // synopsys parallel_case full_case
+    `START_PTBY:
+    begin
+      next_processTxByteRdy <= 1'b0;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_i <= 4'h0;
+      next_TxByte <= 8'h00;
+      next_TxByteCtrl <= 8'h00;
+      next_TXLineState <= 2'b0;
+      next_TXOneCount <= 4'h0;
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `PTBY_WAIT_EN:
+    begin
+      next_processTxByteRdy <= 1'b1;
+      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_GNT;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TXOneCount <= 4'h0;
+        next_TXLineState <= JBit;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (processTxByteWEn == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_i <= 4'h0;
+      end
+    end
+    `PTBY_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_prcTxB <= `WAIT_RDY_WIRE;
+      end
+    end
+    `WAIT_RDY_WIRE:
+    begin
+      if ((USBWireRdy == 1'b1) && (fullSpeedRate == 1'b0))
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE1;
+      end
+      else if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `WAIT_RDY_PKT;
+        //actively drive the first J bit
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `WAIT_RDY_PKT:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `SEND_BYTE_UPDATE_BYTE:
+    begin
+      next_i <= i + 1'b1;
+      next_TxByte <= {1'b0, TxByte[7:1] };
+      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
+      next_TXOneCount <= TXOneCount + 1'b1;
+      //increment 'TXOneCount'
+      else                                        //else this is a zero bit
+      begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      end
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+    end
+    `SEND_BYTE_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (TXOneCount == `MAX_CONSEC_SAME_BITS)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+      end
+      else if (i != 4'h8)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+      else
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+    end
+    `SEND_BYTE_BIT_STUFF:
+    begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+    end
+    `SEND_BYTE_WAIT_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (i == 4'h8)
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+      else
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+    end
+    `STOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_J;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_SND_SE0_1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_CHK:
+    begin
+      if (TxByteCtrl == `DATA_STOP)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_1;
+      end
+      else
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_EN;
+      end
+    end
+    `STOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_IDLE;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_SND_IDLE:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `STOP_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      //release the wire
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `LS_START_SND_IDLE3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_J1;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_SND_J1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_FIN;
+        //Drive the first JBit
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `LS_START_SND_IDLE1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_SND_IDLE2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE3;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prcTxB <= `START_PTBY;
+  else
+    CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processTxByteRdy <= 1'b0;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    USBWireReq <= 1'b0;
+    USBWireWEn <= 1'b0;
+    i <= 4'h0;
+    TxByte <= 8'h00;
+    TxByteCtrl <= 8'h00;
+    TXLineState <= 2'b0;
+    TXOneCount <= 4'h0;
+  end
+  else 
+  begin
+    processTxByteRdy <= next_processTxByteRdy;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    USBWireReq <= next_USBWireReq;
+    USBWireWEn <= next_USBWireWEn;
+    i <= next_i;
+    TxByte <= next_TxByte;
+    TxByteCtrl <= next_TxByteCtrl;
+    TXLineState <= next_TXLineState;
+    TXOneCount <= next_TXOneCount;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC16.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC16.v	(revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC16.v                                                ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [15:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [15:0] CRCResult;
+reg    ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 16'hffff;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0)
+    begin
+      if (CRCEn == 1'b1) begin
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        ready <= 1'b0;
+    end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[15:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == 4'h7)
+      begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.v	(revision 264)
@@ -0,0 +1,418 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input   clk;
+input   getPacketRdy;
+input   rst;
+input   [7:0]RXStatus;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   transReq;
+input   [1:0]transType;
+output  clearTXReq;
+output  getPacketREn;
+output  sendPacketArbiterReq;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  transDone;
+
+reg     clearTXReq, next_clearTXReq;
+wire    clk;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+wire    rst;
+wire    [7:0]RXStatus;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     transDone, next_transDone;
+wire    transReq;
+wire    [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 5'b00000
+`define TX_REQ 5'b00001
+`define CHK_TYPE 5'b00010
+`define FLAG 5'b00011
+`define IN_WAIT_DATA_RXED 5'b00100
+`define IN_CHK_FOR_ERROR 5'b00101
+`define IN_CLR_SP_WEN2 5'b00110
+`define SETUP_CLR_SP_WEN1 5'b00111
+`define SETUP_CLR_SP_WEN2 5'b01000
+`define FIN 5'b01001
+`define WAIT_GNT 5'b01010
+`define SETUP_WAIT_PKT_RXED 5'b01011
+`define IN_WAIT_IN_SENT 5'b01100
+`define OUT0_WAIT_RX_DATA 5'b01101
+`define OUT0_WAIT_DATA0_SENT 5'b01110
+`define OUT0_WAIT_OUT_SENT 5'b01111
+`define SETUP_HC_WAIT_RDY 5'b10000
+`define IN_WAIT_SP_RDY1 5'b10001
+`define IN_WAIT_SP_RDY2 5'b10010
+`define OUT0_WAIT_SP_RDY1 5'b10011
+`define SETUP_WAIT_SETUP_SENT 5'b10100
+`define SETUP_WAIT_DATA_SENT 5'b10101
+`define IN_CLR_SP_WEN1 5'b10110
+`define IN_WAIT_ACK_SENT 5'b10111
+`define OUT0_CLR_WEN1 5'b11000
+`define OUT0_CLR_WEN2 5'b11001
+`define OUT1_WAIT_RX_DATA 5'b11010
+`define OUT1_WAIT_OUT_SENT 5'b11011
+`define OUT1_WAIT_DATA1_SENT 5'b11100
+`define OUT1_WAIT_SP_RDY1 5'b11101
+`define OUT1_CLR_WEN1 5'b11110
+`define OUT1_CLR_WEN2 5'b11111
+
+reg [4:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+  NextState_hstCntrl <= CurrState_hstCntrl;
+  // Set default values for outputs and signals
+  next_transDone <= transDone;
+  next_clearTXReq <= clearTXReq;
+  next_getPacketREn <= getPacketREn;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketPID <= sendPacketPID;
+  next_sendPacketWEn <= sendPacketWEn;
+  case (CurrState_hstCntrl)  // synopsys parallel_case full_case
+    `START_HC:
+    begin
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `TX_REQ:
+    begin
+      if (transReq == 1'b1)
+      begin
+        NextState_hstCntrl <= `WAIT_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `CHK_TYPE:
+    begin
+      if (transType == `IN_TRANS)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+      end
+      else if (transType == `OUTDATA0_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+      end
+      else if (transType == `OUTDATA1_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+      end
+      else if (transType == `SETUP_TRANS)
+      begin
+        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+      end
+    end
+    `FLAG:
+    begin
+      next_transDone <= 1'b1;
+      next_clearTXReq <= 1'b1;
+      next_sendPacketArbiterReq <= 1'b0;
+      NextState_hstCntrl <= `FIN;
+    end
+    `FIN:
+    begin
+      next_transDone <= 1'b0;
+      next_clearTXReq <= 1'b0;
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `WAIT_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1)
+      begin
+        NextState_hstCntrl <= `CHK_TYPE;
+      end
+    end
+    `SETUP_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+    end
+    `SETUP_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+    end
+    `SETUP_WAIT_PKT_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `SETUP_HC_WAIT_RDY:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `SETUP;
+      end
+    end
+    `SETUP_WAIT_SETUP_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `SETUP_WAIT_DATA_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_DATA_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+      end
+    end
+    `IN_CHK_FOR_ERROR:
+    begin
+      if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+      end
+      else
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `IN_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+    end
+    `IN_WAIT_IN_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `IN;
+      end
+    end
+    `IN_WAIT_SP_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `IN_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+    end
+    `IN_WAIT_ACK_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_DATA0_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `OUT0_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `OUT0_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT0_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+    end
+    `OUT0_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+    end
+    `OUT1_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT1_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `OUT1_WAIT_DATA1_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `OUT1_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT1_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+    end
+    `OUT1_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_hstCntrl <= `START_HC;
+  else
+    CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    transDone <= 1'b0;
+    clearTXReq <= 1'b0;
+    getPacketREn <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketPID <= 4'b0;
+    sendPacketWEn <= 1'b0;
+  end
+  else 
+  begin
+    transDone <= next_transDone;
+    clearTXReq <= next_clearTXReq;
+    getPacketREn <= next_getPacketREn;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketPID <= next_sendPacketPID;
+    sendPacketWEn <= next_sendPacketWEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketarbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
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+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)  \nbegin\n  if (muxSOFNotHC  == 1'b1)  \n  begin\n    sendPacketWEnable <= SOF_SP_WEn;\n    sendPacketPID <= `SOF;\n  end\n  else\n  begin\n    sendPacketWEnable <= HC_SP_WEn;\n    sendPacketPID <= HC_PID;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
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+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sofcontroller\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+END
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+L 43 42 0 TEXT "Labels" | 87638,244416 1 0 0 "HCTxPortWEn"
+I 44 0 130 Builtin OutPort | 81915,250446 "" ""
+L 45 44 0 TEXT "Labels" | 87915,250446 1 0 0 "HCTxPortData[7:0]"
+I 46 0 130 Builtin OutPort | 81312,256878 "" ""
+L 47 46 0 TEXT "Labels" | 87312,256878 1 0 0 "HCTxPortCntl[7:0]"
+I 60 0 2 Builtin InPort | 23316,251905 "" ""
+L 59 60 0 TEXT "Labels" | 29316,251905 1 0 0 "SOFTimerClr"
+A 48 9 2 TEXT "Actions" | 121328,217354 1 0 0 "SOFTimer <= 16'h0000;\nHCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+L 49 50 0 TEXT "State Labels" | 162077,151882 1 0 0 "SC_WAIT_GNT\n/4/"
+S 50 6 16384 ELLIPSE "States" | 162077,151882 6500 6500
+W 51 6 0 50 21 BEZIER "Transitions" | 155785,150253 143926,148645 122475,143375 110616,144581
+C 52 51 0 TEXT "Conditions" | 129444,145489 1 0 0 "HCTxPortGnt == 1'b1"
+A 53 22 16 TEXT "Actions" | 118898,162608 1 0 0 "HCTxPortReq <= 1'b1;"
+A 54 33 16 TEXT "Actions" | 41502,87168 1 0 0 "SOFTimer <= 16'h0000;"
+L 55 56 0 TEXT "Labels" | 139062,239200 1 0 0 "HCTxPortReq"
+I 56 0 2 Builtin OutPort | 133062,239200 "" ""
+L 57 58 0 TEXT "Labels" | 141474,244024 1 0 0 "HCTxPortGnt"
+I 58 0 2 Builtin InPort | 135474,244024 "" ""
+L 61 62 0 TEXT "State Labels" | 118352,95112 1 0 0 "CLR_WEN\n/5/"
+S 62 6 20480 ELLIPSE "States" | 118352,95112 6500 6500
+A 63 62 4 TEXT "Actions" | 137072,99272 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 64 6 0 62 24 BEZIER "Transitions" | 116496,88885 114624,81865 110713,68112 108841,61092
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/speedCtrlMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/speedCtrlMux.v	(revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// speedCtrlMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input   directCtrlRate;
+input   directCtrlPol;
+input   sendPacketRate;
+input   sendPacketPol;
+input   sendPacketSel;
+output  fullSpeedRate;
+output  fullSpeedPol;
+
+wire   directCtrlRate;
+wire   directCtrlPol;
+wire   sendPacketRate;
+wire   sendPacketPol;
+wire   sendPacketSel;
+reg   fullSpeedRate;
+reg   fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+  if (sendPacketSel == 1'b1) 
+  begin
+  fullSpeedRate <= sendPacketRate;
+  fullSpeedPol <= sendPacketPol;
+  end
+  else
+  begin
+  fullSpeedRate <= directCtrlRate;
+  fullSpeedPol <= directCtrlPol;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbConstants_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbConstants_h.v	(revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v                                             
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc 
+     
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined       
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSlaveControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSlaveControl_h.v	(revision 264)
@@ -0,0 +1,80 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v                                           
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants 
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices 
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices 
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices 
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+//SCMasterControlegIndices 
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices 
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes 
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts 
+`define SC_RX_PACKET_TOUT 18
+       
+`endif //usbSlaveControl_h_vdefined  

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v	(revision 264)
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// lineControlUpdate.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+    if (fullSpeedPolarity == 1'b1)
+  begin
+      JBit = `ONE_ZERO;
+      KBit = `ZERO_ONE;
+    end
+    else
+  begin
+      JBit = `ZERO_ONE;
+      KBit = `ONE_ZERO;
+    end
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.v	(revision 264)
@@ -0,0 +1,498 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processRxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   processRxDataInWEn;
+input   rst;
+input   [7:0]RxByteIn;
+input   [7:0]RxCtrlIn;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processRxByteRdy;
+output  rstCRC;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+output  RxDataOutWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+reg     processRxByteRdy, next_processRxByteRdy;
+wire    processRxDataInWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]RxByteIn;
+wire    [7:0]RxCtrlIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+reg     RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RxByte, next_RxByte;
+reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg  [7:0]RxCtrl, next_RxCtrl;
+reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg  [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+  NextState_prRxByte <= CurrState_prRxByte;
+  // Set default values for outputs and signals
+  next_RxByte <= RxByte;
+  next_RxCtrl <= RxCtrl;
+  next_RXByteStMachCurrState <= RXByteStMachCurrState;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RxOverflow <= RxOverflow;
+  next_RxTimeOut <= RxTimeOut;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_RxDataOut <= RxDataOut;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOutWEn <= RxDataOutWEn;
+  next_rstCRC <= rstCRC;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_RXDataByteCnt <= RXDataByteCnt;
+  next_processRxByteRdy <= processRxByteRdy;
+  case (CurrState_prRxByte)  // synopsys parallel_case full_case
+    `CHK_ST:
+    begin
+      if (RXByteStMachCurrState == `HS_BYTE_ST)
+      begin
+        NextState_prRxByte <= `HSHAKE_CHK;
+      end
+      else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+      begin
+        NextState_prRxByte <= `TOKEN_WAIT_CRC;
+      end
+      else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+      begin
+        NextState_prRxByte <= `DATA_WAIT_CRC;
+      end
+      else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+      begin
+        NextState_prRxByte <= `IDLE_CHK_START;
+      end
+      else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+      begin
+        NextState_prRxByte <= `CHK_SYNC_DO;
+      end
+      else if (RXByteStMachCurrState == `CHECK_PID_ST)
+      begin
+        NextState_prRxByte <= `CHK_PID_DO_CHK;
+      end
+    end
+    `START_PRBY:
+    begin
+      next_RxByte <= 8'h00;
+      next_RxCtrl <= 8'h00;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RxOverflow <= 1'b0;
+      next_RxTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_RxDataOut <= 8'h00;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOutWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_RXDataByteCnt <= 10'h00;
+      next_processRxByteRdy <= 1'b1;
+      NextState_prRxByte <= `WAIT_BYTE;
+    end
+    `WAIT_BYTE:
+    begin
+      if (processRxDataInWEn == 1'b1)
+      begin
+        NextState_prRxByte <= `CHK_ST;
+        next_RxByte <= RxByteIn;
+        next_RxCtrl <= RxCtrlIn;
+        next_processRxByteRdy <= 1'b0;
+      end
+    end
+    `HSHAKE_FIN:
+    begin
+      next_RxDataOutWEn <= 1'b0;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `HSHAKE_CHK:
+    begin
+      NextState_prRxByte <= `HSHAKE_FIN;
+      if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RxDataOutWEn <= 1'b1;
+    end
+    `CHK_PID_DO_CHK:
+    begin
+      if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+      begin
+        NextState_prRxByte <= `WAIT_BYTE;
+        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+        next_processRxByteRdy <= 1'b1;
+      end
+      else
+      begin
+        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+        next_CRCError <= 1'b0;
+        next_bitStuffError <= 1'b0;
+        next_RxOverflow <= 1'b0;
+        next_NAKRxed <= 1'b0;
+        next_stallRxed <= 1'b0;
+        next_ACKRxed <= 1'b0;
+        next_dataSequence <= 1'b0;
+        next_RxTimeOut <= 1'b0;
+        next_RXDataByteCnt <= 0;
+        next_RxDataOut <= RxByte;
+        next_RxCtrlOut <= `RX_PACKET_START;
+        next_RxDataOutWEn <= 1'b1;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `CHK_PID_FIRST_BYTE_PROC:
+    begin
+      next_rstCRC <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      case (RxByte[1:0] )
+      `SPECIAL:                              //Special PID.
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      `TOKEN:                                //Token PID
+      begin
+      next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      `HANDSHAKE:                            //Handshake PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_ACKRxed <= 1'b1;
+      2'b10:
+      next_NAKRxed <= 1'b1;
+      2'b11:
+      next_stallRxed <= 1'b1;
+      default:
+      begin
+      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+      end
+      endcase
+      next_RXByteStMachCurrState <= `HS_BYTE_ST;
+      end
+      `DATA:                                  //Data PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_dataSequence <= 1'b0;
+      2'b10:
+      next_dataSequence <= 1'b1;
+      default:
+      $display ("Invalid DATA PID detected in ProcessRXByte\n");
+      endcase
+      next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      endcase
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_FIN:
+    begin
+      next_CRC16En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC16Result != 16'hb001)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC16En <= 1'b1;
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `DATA_FIN;
+    end
+    `DATA_WAIT_CRC:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `DATA_CHK_STRM;
+      end
+    end
+    `TOKEN_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC5Result != 5'h6)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      if (RXDataByteCnt > 10'h2)
+      begin
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      else
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      end
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `TOKEN_FIN;
+    end
+    `TOKEN_FIN:
+    begin
+      next_CRC5En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `TOKEN_WAIT_CRC:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `TOKEN_CHK_STRM;
+      end
+    end
+    `CHK_SYNC_DO:
+    begin
+      if (RxByte == `SYNC_BYTE)
+      next_RXByteStMachCurrState <= `CHECK_PID_ST;
+      else
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `IDLE_CHK_START:
+    begin
+      if (RxCtrl == `DATA_START)
+      next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxByte <= `START_PRBY;
+  else
+    CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RxDataOut <= 8'h00;
+    RxCtrlOut <= 8'h00;
+    RxDataOutWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    processRxByteRdy <= 1'b1;
+    RxByte <= 8'h00;
+    RxCtrl <= 8'h00;
+    RXByteStMachCurrState <= `IDLE_BYTE_ST;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RxOverflow <= 1'b0;
+    RxTimeOut <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    RXDataByteCnt <= 10'h00;
+  end
+  else 
+  begin
+    RxDataOut <= next_RxDataOut;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOutWEn <= next_RxDataOutWEn;
+    rstCRC <= next_rstCRC;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    processRxByteRdy <= next_processRxByteRdy;
+    RxByte <= next_RxByte;
+    RxCtrl <= next_RxCtrl;
+    RXByteStMachCurrState <= next_RXByteStMachCurrState;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RxOverflow <= next_RxOverflow;
+    RxTimeOut <= next_RxTimeOut;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    RXDataByteCnt <= next_RXDataByteCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.asf	(revision 264)
@@ -0,0 +1,251 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIEReceiver\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+W 158 6 0 46 235 BEZIER "Transitions" | 146210,55537 151355,64540 163238,84117 168383,93120
+W 159 6 0 23 235 BEZIER "Transitions" | 148132,37141 151647,41428 158891,48733 161548,55421\
+                                        164206,62109 167707,83613 169507,92702
+L 175 174 0 TEXT "State Labels" | 85374,175380 1 0 0 "CHK_RX_BITS1\n/6/"
+S 174 81 53248 ELLIPSE "States" | 85374,175380 6500 6500
+W 169 72 0 71 68 BEZIER "Transitions" | 86442,160488 87123,152997 131179,46721 131860,39230
+A 166 53 4 TEXT "Actions" | 101814,215348 1 0 0 "if (RxBits == `ONE_ZERO)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `FULL_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `LOW_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+W 160 6 0 235 11 BEZIER "Transitions" | 171556,99342 175414,111175 187017,133454 187960,147988\
+                                        188903,162522 181196,168609 172535,178212 163875,187816\
+                                        140506,197413 125270,198727 110035,200042 80303,196085\
+                                        61192,193841
+W 161 39 8195 40 43 BEZIER "Transitions" | 58578,211192 49548,206204 31147,197012 26632,187509\
+                                           22117,178006 22117,149970 33211,139263 44305,128556\
+                                           88681,113764 103817,110238 118953,106712 136069,108777\
+                                           144153,109121
+W 189 90 0 187 185 BEZIER "Transitions" | 63495,198555 68094,191731 73329,182828 77929,176004
+I 188 90 0 Builtin Exit | 126468,30181
+I 187 90 0 Builtin Entry | 59972,198555
+L 186 185 0 TEXT "State Labels" | 81562,170615 1 0 0 "CHK_RX_BITS\n/7/"
+S 185 90 57344 ELLIPSE "States" | 81562,170615 6500 6500
+W 183 81 0 174 177 BEZIER "Transitions" | 85690,168888 83487,163706 122612,52505 134843,35774
+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+I 177 81 0 Builtin Exit | 137732,35774
+I 176 81 0 Builtin Entry | 63784,203320
+W 204 99 0 201 199 BEZIER "Transitions" | 75683,156094 76364,148603 119799,31977 120480,24486
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/8/"
+S 201 99 61440 ELLIPSE "States" | 75367,162586 6500 6500
+I 200 99 0 Builtin Entry | 53777,190526
+I 199 99 0 Builtin Exit | 120480,22566
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+W 194 90 0 185 188 BEZIER "Transitions" | 81878,164123 82559,156632 125787,39592 126468,32101
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 209 0 130 Builtin InPort | 77032,244882 "" ""
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+I 215 0 130 Builtin Signal | 20439,258880 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 219 0 130 Builtin Signal | 20132,253454 "" ""
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+I 238 236 0 Builtin Exit | 129540,111760
+I 237 236 0 Builtin Entry | 86360,167640
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 235 6 65556 ELLIPSE "Junction" | 170150,96140 3500 3500
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;"
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+I 233 0 130 Builtin Signal | 19714,243194 "" ""
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+I 244 242 0 Builtin Exit | 129540,111760
+I 243 242 0 Builtin Entry | 86360,167640
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 241 6 69652 ELLIPSE "Junction" | 55410,156008 3500 3500
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+A 252 204 16 TEXT "Actions" | 71150,119778 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend"
+A 255 194 16 TEXT "Actions" | 77086,121516 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+A 258 183 16 TEXT "Actions" | 76648,132819 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+A 259 169 16 TEXT "Actions" | 77229,121214 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(revision 264)
@@ -0,0 +1,199 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbTxWireArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input   clk;
+input   prcTxByteCtrl;
+input   [1:0]prcTxByteData;
+input   prcTxByteReq;
+input   prcTxByteWEn;
+input   rst;
+input   SIETxCtrl;
+input   [1:0]SIETxData;
+input   SIETxReq;
+input   SIETxWEn;
+input   USBWireRdyIn;
+output  prcTxByteGnt;
+output  SIETxGnt;
+output  [1:0]TxBits;
+output  TxCtl;
+output  USBWireRdyOut;
+output  USBWireWEn;
+
+wire    clk;
+wire    prcTxByteCtrl;
+wire    [1:0]prcTxByteData;
+reg     prcTxByteGnt, next_prcTxByteGnt;
+wire    prcTxByteReq;
+wire    prcTxByteWEn;
+wire    rst;
+wire    SIETxCtrl;
+wire    [1:0]SIETxData;
+reg     SIETxGnt, next_SIETxGnt;
+wire    SIETxReq;
+wire    SIETxWEn;
+reg     [1:0]TxBits, next_TxBits;
+reg     TxCtl, next_TxCtl;
+wire    USBWireRdyIn;
+reg     USBWireRdyOut, next_USBWireRdyOut;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)
+begin
+if (muxSIENotPTXB  == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+  NextState_txWireArb <= CurrState_txWireArb;
+  // Set default values for outputs and signals
+  next_prcTxByteGnt <= prcTxByteGnt;
+  next_SIETxGnt <= SIETxGnt;
+  next_muxSIENotPTXB <= muxSIENotPTXB;
+  case (CurrState_txWireArb)  // synopsys parallel_case full_case
+    `START_TARB:
+    begin
+      NextState_txWireArb <= `TARB_WAIT_REQ;
+    end
+    `TARB_WAIT_REQ:
+    begin
+      if (prcTxByteReq == 1'b1)
+      begin
+        NextState_txWireArb <= `PTXB_ACT;
+        next_prcTxByteGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b0;
+      end
+      else if (SIETxReq == 1'b1)
+      begin
+        NextState_txWireArb <= `SIE_TX_ACT;
+        next_SIETxGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b1;
+      end
+    end
+    `PTXB_ACT:
+    begin
+      if (prcTxByteReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_prcTxByteGnt <= 1'b0;
+      end
+    end
+    `SIE_TX_ACT:
+    begin
+      if (SIETxReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_SIETxGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_txWireArb <= `START_TARB;
+  else
+    CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    prcTxByteGnt <= 1'b0;
+    SIETxGnt <= 1'b0;
+    muxSIENotPTXB <= 1'b0;
+  end
+  else 
+  begin
+    prcTxByteGnt <= next_prcTxByteGnt;
+    SIETxGnt <= next_SIETxGnt;
+    muxSIENotPTXB <= next_muxSIENotPTXB;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.v	(revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sofcontroller
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input   clk;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+input   SOFEnable;
+input   SOFTimerClr;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [15:0]SOFTimer;
+
+wire    clk;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+wire    SOFEnable;
+reg     [15:0]SOFTimer, next_SOFTimer;
+wire    SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+  NextState_sofCntl <= CurrState_sofCntl;
+  // Set default values for outputs and signals
+  next_SOFTimer <= SOFTimer;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_sofCntl)  // synopsys parallel_case full_case
+    `START_SC:
+    begin
+      NextState_sofCntl <= `WAIT_SOF_EN;
+    end
+    `WAIT_SOF_EN:
+    begin
+      if (SOFEnable == 1'b1)
+      begin
+        NextState_sofCntl <= `SC_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `WAIT_SEND_RESUME:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sofCntl <= `CLR_WEN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_RESUME_START;
+      end
+    end
+    `INC_TIMER:
+    begin
+      next_HCTxPortReq <= 1'b0;
+      if (SOFTimerClr == 1'b1)
+      next_SOFTimer <= 16'h0000;
+      else
+      next_SOFTimer <= SOFTimer + 1'b1;
+      if (SOFEnable == 1'b0)
+      begin
+        NextState_sofCntl <= `WAIT_SOF_EN;
+        next_SOFTimer <= 16'h0000;
+      end
+    end
+    `SC_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sofCntl <= `WAIT_SEND_RESUME;
+      end
+    end
+    `CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sofCntl <= `INC_TIMER;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sofCntl <= `START_SC;
+  else
+    CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFTimer <= 16'h0000;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SOFTimer <= next_SOFTimer;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/usbHostControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/usbHostControl.v	(revision 264)
@@ -0,0 +1,399 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostControl(
+  clk, rst,
+  //sendPacket
+  TxFifoRE, TxFifoData, TxFifoEmpty,
+  //getPacket
+  RxFifoWE, RxFifoData, RxFifoFull,
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //HCTxPortArbiter
+  HCTxPortEn, HCTxPortRdy,
+  HCTxPortData, HCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFSentIntOut, 
+  connEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  hostControlSelect
+    );
+
+input clk, rst;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [3:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut; 
+output connEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+input hostControlSelect;
+
+wire clk;
+wire rst;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut; 
+wire connEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire sendPacketCPFSRate;
+wire sendPacketCPFSPol;
+wire sendPacketCPGrabLine;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire directCtrlRate;
+wire directCtrlPol;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI 
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .SOFSentIntOut(SOFSentIntOut), 
+  .connEventIntOut(connEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .TxTransTypeReg(transType), 
+  .TxSOFEnableReg(SOFEnable),
+  .TxAddrReg(TxAddr), 
+  .TxEndPReg(TxEndP), 
+  .frameNumIn(frameNum), 
+  .RxPktStatusIn(RxPktStatus), 
+  .RxPIDIn(RxPID),
+  .connectStateIn(connectStateOut),
+  .SOFSentIn(SOFSent), 
+  .connEventIn(connectionEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .hostControlSelect(hostControlSelect),
+  .clrTransReq(clrTxReq),
+  .preambleEn(preAmbleEnable),
+  .SOFSync(SOFSyncEn),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(directCtrlPol), 
+  .fullSpeedRate(directCtrlRate),
+  .transReq(transReq)
+  
+  );
+
+
+hostcontroller u_hostController
+  (.RXStatus(RxPktStatus), 
+  .clearTXReq(clrTxReq),
+  .clk(clk),
+  .getPacketREn(getPacketREn),
+  .getPacketRdy(getPacketRdy),
+  .rst(rst),
+  .sendPacketArbiterGnt(HCTxGnt),
+  .sendPacketArbiterReq(HCTxReq),
+  .sendPacketPID(HC_PID),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(HC_SP_WEn),
+  .transDone(transDone),
+  .transReq(transReq),
+  .transType(transType) );
+
+SOFController u_SOFController
+  (.HCTxPortCntl(SOFCntlCntl),
+  .HCTxPortData(SOFCntlData),
+  .HCTxPortGnt(SOFCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(SOFCntlReq),
+  .HCTxPortWEn(SOFCntlWEn),
+  .SOFEnable(SOFEnable),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(clk),
+  .rst(rst) ); 
+
+SOFTransmit u_SOFTransmit
+  (.SOFEnable(SOFEnable),
+  .SOFSent(SOFSent),
+  .SOFSyncEn(SOFSyncEn),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(clk),
+  .rst(rst),
+  .sendPacketArbiterGnt(SOFTxGnt),
+  .sendPacketArbiterReq(SOFTxReq),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(SOF_SP_WEn) );  
+
+
+sendPacketArbiter u_sendPacketArbiter
+  (.HCTxGnt(HCTxGnt),
+  .HCTxReq(HCTxReq),
+  .HC_PID(HC_PID),
+  .HC_SP_WEn(HC_SP_WEn),
+  .SOFTxGnt(SOFTxGnt),
+  .SOFTxReq(SOFTxReq),
+  .SOF_SP_WEn(SOF_SP_WEn),
+  .clk(clk),
+  .rst(rst),
+  .sendPacketPID(sendPacketCPPIDIn),
+  .sendPacketWEnable(sendPacketCPWEnIn) );    
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+  (.sendPacketCPPID(sendPacketCPPIDIn),
+  .clk(clk),
+  .fullSpeedBitRate(sendPacketCPFSRate),
+  .fullSpeedPolarity(sendPacketCPFSPol),
+  .grabLineControl(sendPacketCPGrabLine),
+  .preAmbleEnable(preAmbleEnable),
+  .rst(rst),
+  .sendPacketCPReady(sendPacketCPReadyOut),
+  .sendPacketCPWEn(sendPacketCPWEnIn),
+  .sendPacketPID(sendPacketCPPIDOut),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+  (.HCTxPortCntl(sendPacketCntl),
+  .HCTxPortData(sendPacketData),
+  .HCTxPortGnt(sendPacketGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(sendPacketReq),
+  .HCTxPortWEn(sendPacketWEn),
+  .PID(sendPacketCPPIDOut),
+  .TxAddr(TxAddr),
+  .TxEndP(TxEndP),
+  .clk(clk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .frameNum(frameNum),
+  .rst(rst),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut) );
+  
+directControl u_directControl
+  (.HCTxPortCntl(directCntlCntl),
+  .HCTxPortData(directCntlData),
+  .HCTxPortGnt(directCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(directCntlReq),
+  .HCTxPortWEn(directCntlWEn),
+  .clk(clk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rst) ); 
+
+HCTxPortArbiter u_HCTxPortArbiter
+  (.HCTxPortCntl(HCTxPortCtrl),
+  .HCTxPortData(HCTxPortData),
+  .HCTxPortWEnable(HCTxPortEn),
+  .SOFCntlCntl(SOFCntlCntl),
+  .SOFCntlData(SOFCntlData),
+  .SOFCntlGnt(SOFCntlGnt),
+  .SOFCntlReq(SOFCntlReq),
+  .SOFCntlWEn(SOFCntlWEn),
+  .clk(clk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rst),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+getPacket u_getPacket
+  (.RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXPktStatus(RxPktStatus),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .clk(clk),
+  .getPacketEn(getPacketREn),
+  .rst(rst) ); 
+
+speedCtrlMux u_speedCtrlMux
+  (.directCtrlRate(directCtrlRate),
+  .directCtrlPol(directCtrlPol),
+  .sendPacketRate(sendPacketCPFSRate),
+  .sendPacketPol(sendPacketCPFSPol),
+  .sendPacketSel(sendPacketCPGrabLine),
+  .fullSpeedRate(fullSpeedRate),
+  .fullSpeedPol(fullSpeedPol) );
+
+rxStatusMonitor  u_rxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .connectionEventOut(connectionEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(clk),
+  .rst(rst)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostControl_h.v	(revision 264)
@@ -0,0 +1,71 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v                                          
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+ 
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants 
+//`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval
+`define SOF_TX_TIME 16'hbb80     //Correct SOF interval for 48MHz clock
+//`define SOF_TX_MARGIN 2 
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+       
+//Host RXStatusRegIndices 
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined 

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/wishBoneBus_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/wishBoneBus_h.v	(revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+ 
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.asf	(revision 264)
@@ -0,0 +1,313 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=256
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processrxbit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+L 15 16 0 TEXT "State Labels" | 116068,123104 1 0 0 "IDLE"
+S 16 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116068,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 18 17 8192 ELLIPSE "States" | 107950,139700 6500 6500
+L 19 18 0 TEXT "State Labels" | 107950,139700 1 0 0 "FIRST_BIT\n/1/"
+I 20 17 0 Builtin Entry | 56736,212076
+I 21 17 0 Builtin Exit | 128380,96970
+W 23 17 0 18 21 BEZIER "Transitions" | 111741,134422 116780,127404 120535,103988 125575,96970
+S 24 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116801,94499 6500 6500
+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
+W 35 41 0 40 37 BEZIER "Transitions" | 111741,134422 116780,127404 121695,118778 126735,111760
+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
+I 37 41 0 Builtin Exit | 129540,111760
+I 38 41 0 Builtin Entry | 86360,167640
+L 39 40 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK\n/9/"
+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 119820,36808 1 0 0 "RES_END"
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 51 6 0 213 16 BEZIER "Transitions" | 42388,154240 42522,148478 41966,137442 42502,133556\
+                                       43038,129670 44914,125650 53423,124511 61932,123372\
+                                       93489,123426 109569,123158
+W 52 6 0 213 24 BEZIER "Transitions" | 42699,154238 43235,140704 42636,114126 43641,106354\
+                                       44646,98582 47594,94562 55902,93624 64210,92686\
+                                       94494,92954 102132,93021 109770,93088 110325,93078\
+                                       110459,93078
+W 53 6 0 213 33 BEZIER "Transitions" | 42645,154234 43047,131722 42770,88800 43976,77142\
+                                       45182,65484 49202,63876 57711,63474 66220,63072\
+                                       96236,63072 103807,63072 111378,63072 111758,63165\
+                                       111892,63165
+W 54 6 0 213 42 BEZIER "Transitions" | 42671,154227 43609,125551 43842,70308 45115,54764\
+                                       46388,39220 49604,34396 58247,33391 66890,32386\
+                                       97657,35973 113335,36375
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+                                       188238,99472 188778,113512 186145,122422 183513,131332\
+                                       167904,143587 159264,149864 150624,156142 133542,158851\
+                                       125779,159931 118017,161011 123617,159646 119837,160051
+W 68 6 0 16 219 BEZIER "Transitions" | 121312,119265 131167,111435 152206,96104 162061,88274
+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 122746,145328 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h0;                          \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+W 76 17 4096 241 18 BEZIER "Transitions" | 130017,172236 121274,163054 112530,153872 103787,144690
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
+W 82 17 8194 75 21 BEZIER "Transitions" | 74719,170800 71529,161085 64380,142085 64960,133312\
+                                          65540,124540 74240,108880 82215,104385 90190,99890\
+                                          113975,98130 125575,96970
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 98161,161647 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+                                            151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+                                        176540,156388 181096,131196 181431,113977 181766,96758\
+                                        182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit)                           //if current bit is a JBit, then\n  RXBitStMachCurrState <= `IDLE_BIT_ST;       //next state is idle\nelse                                          //else\nbegin\n  RXBitStMachCurrState <= `WAIT_RESUME_ST;    //check for resume\n  resumeWaitCnt <= 0;                          \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte;       \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit)  //line must leave KBit state for the end of resume\nbegin\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\n  resumeDetected <= 1'b0;   //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit)  //can only be a resume if line remains in Kbit state\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n  resumeWaitCnt <= resumeWaitCnt + 1'b1; \n  //if we've waited long enough, then\n  if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)\n  begin	\n    RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n    resumeDetected <= 1'b1;  //report resume detected\n  end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+                                         107061,21822 137747,20482 148467,20415 159187,20348\
+                                         171381,21420 174463,22458 177545,23497 178090,26035\
+                                         178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+                                         145117,36964 157043,31068 161599,29627 166155,28187\
+                                         172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 4'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[3:0]"
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 25628,249822 1 0 0 "if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n  RXSameBitCount <= RXSameBitCount + 1'b1;  //inc 'RXSameBitCount'\n  if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error\n    bitStuffError <= 1'b1;                         //flag 'bitStuffError'\n  else                                          //else no bit stuffing error\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin\n      processRxBitRdy <= 1'b1;                   //early indication of ready\n	end\n    RXByte <= { 1'b1, RXByte[7:1]};              //RZ bit = 1 (ie no change in 'RxBits')\n  end\nend\nelse                                            //else current 'RxBits' are different from old 'RxBits'\nbegin\n  if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;	               //early indication of ready\n	end\n    RXByte <= {1'b0, RXByte[7:1]};             //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n  end\n   RXSameBitCount <= 4'h0;                      //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 127967,178402 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 127967,178402 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 111780,177768 121508,177678
+C 243 242 0 TEXT "Conditions" | 86880,174058 1 0 0 "RxBits == KBit"
+C 244 76 0 TEXT "Conditions" | 125584,169201 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.asf	(revision 264)
@@ -0,0 +1,286 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1099
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processTxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 874
+PAGE 12700,12700 215900,279400
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+PAGE 12700,12700 215900,279400
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+GRID=OFF
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+END
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+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 1025
+PAGE 25400,25400 215900,279400
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+END
+INSTHEADER 1034
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 1098 1035 0 1095 1097 BEZIER "Transitions" | 108942,40143 114373,39761 124823,37993 130254,37611
+I 1097 1035 0 Builtin Exit | 133008,37611
+A 1096 1095 4 TEXT "Actions" | 110058,56736 1 0 0 "USBWireWEn <= 1'b0;"
+S 1095 1035 106496 ELLIPSE "States" | 102676,41870 6500 6500
+L 1094 1095 0 TEXT "State Labels" | 102676,41870 1 0 0 "FIN\n/21/"
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin InPort | 20959,250108 "" ""
+L 821 822 0 TEXT "Labels" | 26959,250108 1 0 0 "TxByteCtrlIn[7:0]"
+I 820 0 130 Builtin InPort | 20959,254515 "" ""
+L 819 820 0 TEXT "Labels" | 26959,254515 1 0 0 "TxByteIn[7:0]"
+I 818 0 2 Builtin OutPort | 18852,259388 "" ""
+L 817 818 0 TEXT "Labels" | 24852,259388 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin InPort | 20959,264028 "" ""
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+A 1088 1087 16 TEXT "Actions" | 79282,165145 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+C 1089 1087 0 TEXT "Conditions" | 44839,149287 1 0 0 "USBWireRdy == 1'b1"
+A 1090 1084 4 TEXT "Actions" | 60764,178497 1 0 0 "USBWireWEn <= 1'b0;"
+W 1091 6 1 1025 1034 BEZIER "Transitions" | 176852,45724 174332,42574 169925,36810 163940,34881\
+                                            157955,32952 139055,31533 132716,31415 126377,31297\
+                                            121929,32154 118701,32626
+C 1092 1091 0 TEXT "Conditions" | 145670,31298 1 0 0 "fullSpeedRate == 1'b0"
+W 1093 6 0 1034 874 BEZIER "Transitions" | 107126,38228 93109,49095 67229,69836 53212,80703
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+C 870 869 0 TEXT "Conditions" | 44743,165433 1 0 0 "processTxByteWEn == 1'b1"
+A 871 869 16 TEXT "Actions" | 40695,156023 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+L 873 874 0 TEXT "State Labels" | 48483,85161 1 0 0 "SEND_BYTE"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48483,85161 6500 6500
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 883 880 0 Builtin Entry | 38120,248040
+I 884 880 0 Builtin Exit | 178131,23271
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47391,100834 47973,91631
+W 897 6 0 874 887 BEZIER "Transitions" | 48237,78679 48703,71573 48867,58679 49333,51573
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+                                         25630,50244 23766,53274 22950,67894 22135,82515\
+                                         20737,137969 21261,153813 21785,169657 25281,177579\
+                                         27028,179792 28775,182006 32271,182938 33727,182355\
+                                         35183,181773 37321,179186 38486,177555
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1)                      //If this bit is 1, then\n  TXOneCount <= TXOneCount + 1'b1;          //increment 'TXOneCount'\nelse                                        //else this is a zero bit\nbegin\n  TXOneCount <= 4'h0;                            //reset 'TXOneCount'\n  if (TXLineState == JBit) \n    TXLineState <= KBit; //toggle the line state\n  else \n    TXLineState <= JBit;\nend"
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == `MAX_CONSEC_SAME_BITS"
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h0;                                //reset 'TXOneCount'\nif (TXLineState == JBit) \n  TXLineState <= KBit;   //toggle the line state\nelse \n  TXLineState <= JBit;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+                                              113354,23912 154429,23527 174909,23271
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+                                              40522,42856 31562,47464 29098,65320 26634,83176\
+                                              25738,149992 26858,168968 27978,187944 33354,197032\
+                                              36938,198888 40522,200744 49226,198568 51498,198152\
+                                              53770,197736 54409,198230 54473,198230
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 4'h0;       \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+W 940 6 0 936 1005 BEZIER "Transitions" | 152571,107755 158885,103151 166953,83129 172936,74254
+C 941 940 0 TEXT "Conditions" | 159104,107836 1 0 0 "USBWireGnt == 1'b1"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+W 944 895 0 948 942 BEZIER "Transitions" | 72730,212275 73358,204982 73632,189078 74260,181785
+C 945 944 0 TEXT "Conditions" | 73971,211371 1 0 0 "USBWireRdy == 1'b1"
+A 946 942 4 TEXT "Actions" | 93534,178039 1 0 0 "USBWireWEn <= 1'b0;"
+A 947 944 16 TEXT "Actions" | 69416,202253 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+W 958 895 0 942 956 BEZIER "Transitions" | 75377,168841 76005,161548 76957,146611 77585,139318
+A 959 958 16 TEXT "Actions" | 72304,159240 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 960 956 4 TEXT "Actions" | 96752,135563 1 0 0 "USBWireWEn <= 1'b0;"
+C 961 958 0 TEXT "Conditions" | 76516,167828 1 0 0 "USBWireRdy == 1'b1"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+W 964 895 0 956 962 BEZIER "Transitions" | 78681,126377 79309,119084 79833,97641 80461,90348
+A 965 964 16 TEXT "Actions" | 75410,113723 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+A 966 962 4 TEXT "Actions" | 99640,86596 1 0 0 "USBWireWEn <= 1'b0;"
+C 967 964 0 TEXT "Conditions" | 79852,125749 1 0 0 "USBWireRdy == 1'b1"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+W 970 895 0 962 968 BEZIER "Transitions" | 81334,77407 81962,70114 82544,57872 83172,50579
+A 971 970 16 TEXT "Actions" | 77621,69378 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+C 973 970 0 TEXT "Conditions" | 81643,77033 1 0 0 "USBWireRdy == 1'b1"
+I 974 895 0 Builtin Exit | 97904,23272
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+                                           90132,26172 93257,24084 94765,23272
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+                                              104561,139388 153745,139620 168013,138576 182281,137532\
+                                              190169,133124 192141,121582 194113,110040 194113,68280\
+                                              192025,55114 189937,41948 185529,28723 181353,23271
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+                                              41124,121640 36948,124424 36020,132602 35092,140780\
+                                              35556,170708 38166,179350 40776,187992 50140,192687\
+                                              55128,195007
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+                                              30972,218732 29812,212468 29638,189094 29464,165720\
+                                              29928,78488 31900,55230 33872,31972 41296,26172\
+                                              49358,24664 57420,23156 82353,23388 94765,23272
+I 977 895 0 Builtin Entry | 34452,259216
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+A 979 9 4 TEXT "Actions" | 108416,207754 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;"
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 997 995 0 Builtin Exit | 129540,111760
+I 996 995 0 Builtin Entry | 86360,167640
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+W 1000 6 2 1025 1011 BEZIER "Transitions" | 175446,48001 143324,42707 116663,67496 88157,75929
+A 1001 1000 16 TEXT "Actions" | 97876,75175 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit;  \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+S 1005 6 73728 ELLIPSE "States" | 178403,70739 6500 6500
+L 1006 1005 0 TEXT "State Labels" | 178403,71114 1 0 0 "WAIT_RDY_WIRE\n/15/"
+S 1011 6 77824 ELLIPSE "States" | 81933,77802 6500 6500
+A 1012 1011 4 TEXT "Actions" | 89664,97554 1 0 0 "USBWireWEn <= 1'b0;"
+L 1013 1011 0 TEXT "State Labels" | 81933,77802 1 0 0 "WAIT_RDY_PKT\n/16/"
+W 1020 6 0 1011 874 BEZIER "Transitions" | 75467,77142 69580,78790 60125,80492 54238,82140
+L 1021 1022 0 TEXT "Labels" | 130600,229120 1 0 0 "fullSpeedRate"
+I 1022 0 2 Builtin InPort | 124600,229120 "" ""
+H 1027 1025 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 1025 6 81940 ELLIPSE "Junction" | 178900,48560 3500 3500
+L 1026 1025 0 TEXT "State Labels" | 178900,48560 1 0 0 "J2"
+I 1028 1027 0 Builtin Entry | 86360,167640
+I 1029 1027 0 Builtin Exit | 129540,111760
+W 1030 1027 0 1028 1029 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+W 1031 6 0 1005 1025 BEZIER "Transitions" | 178252,64280 178492,60600 178502,55716 178742,52036
+C 1032 1031 0 TEXT "Conditions" | 160740,61840 1 0 0 "USBWireRdy == 1'b1"
+L 1033 1034 0 TEXT "State Labels" | 112501,34575 1 0 0 "LS_START"
+S 1034 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112501,34575 6500 6500
+H 1035 1034 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 1046 1035 90112 ELLIPSE "States" | 118913,145067 6500 6500
+L 1047 1046 0 TEXT "State Labels" | 118913,145067 1 0 0 "SND_IDLE3\n/17/"
+W 1060 1035 0 1068 1095 BEZIER "Transitions" | 119595,89987 115301,85752 96726,74583 101803,48306
+C 1061 1060 0 TEXT "Conditions" | 120455,89906 1 0 0 "USBWireRdy == 1'b1"
+A 1064 1060 16 TEXT "Actions" | 103427,83175 1 0 0 "//Drive the first JBit\nUSBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+W 1066 1035 0 1046 1068 BEZIER "Transitions" | 119437,138596 120065,131303 120589,109860 121217,102567
+C 1067 1066 0 TEXT "Conditions" | 120608,137968 1 0 0 "USBWireRdy == 1'b1"
+S 1068 1035 94208 ELLIPSE "States" | 121801,96100 6500 6500
+A 1069 1068 4 TEXT "Actions" | 140396,98815 1 0 0 "USBWireWEn <= 1'b0;"
+A 1070 1066 16 TEXT "Actions" | 116166,125942 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+L 1071 1068 0 TEXT "State Labels" | 121801,96100 1 0 0 "SND_J1\n/18/"
+L 815 816 0 TEXT "Labels" | 26959,264028 1 0 0 "processTxByteWEn"
+A 1073 1046 4 TEXT "Actions" | 137508,147782 1 0 0 "USBWireWEn <= 1'b0;"
+I 1075 1035 0 Builtin Entry | 75208,271435
+S 1077 1035 98304 ELLIPSE "States" | 59497,220774 6500 6500
+L 1078 1077 0 TEXT "State Labels" | 59497,220774 1 0 0 "SND_IDLE1\n/19/"
+W 1079 1035 0 1075 1077 BEZIER "Transitions" | 75208,269307 75836,262014 61041,234231 58933,227242
+W 1080 1035 0 1077 1084 BEZIER "Transitions" | 60047,214302 60675,207009 52849,177084 50437,170095
+A 1081 1080 16 TEXT "Actions" | 52141,196692 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+C 1082 1080 0 TEXT "Conditions" | 60959,213403 1 0 0 "USBWireRdy == 1'b1"
+S 1084 1035 102400 ELLIPSE "States" | 50985,163622 6500 6500
+L 1085 1084 0 TEXT "State Labels" | 50985,163622 1 0 0 "SND_IDLE2\n/20/"
+W 1087 1035 0 1084 1046 BEZIER "Transitions" | 51535,157150 52163,149857 101582,150816 115890,150819
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.v	(revision 264)
@@ -0,0 +1,276 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIEReceiver
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
+input   clk;
+input   rst;
+input   [1:0]RxWireDataIn;
+input   RxWireDataWEn;
+output  [1:0]connectState;
+
+wire    clk;
+reg     [1:0]connectState, next_connectState;
+wire    rst;
+wire    [1:0]RxWireDataIn;
+wire    RxWireDataWEn;
+
+// diagram signals declarations
+reg  [1:0]RxBits, next_RxBits;
+reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg  [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
+begin
+  NextState_rcvr <= CurrState_rcvr;
+  // Set default values for outputs and signals
+  next_RXWaitCount <= RXWaitCount;
+  next_connectState <= connectState;
+  next_RXStMachCurrState <= RXStMachCurrState;
+  next_RxBits <= RxBits;
+  case (CurrState_rcvr)  // synopsys parallel_case full_case
+    `WAIT_BIT:
+    begin
+      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+      begin
+        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+      begin
+        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+    end
+    `START_SRX:
+    begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_RXWaitCount <= 8'h00;
+      next_connectState <= `DISCONNECT;
+      next_RxBits <= 2'b00;
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `DISCNCT_CHK_RXBITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else if (RxBits == `ONE_ZERO)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+      end
+    end
+    `WAIT_FS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ONE_ZERO)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `FULL_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `WAIT_LS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `LOW_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `LS_CONN_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+      next_RXWaitCount <= 0;
+      end
+    end
+    `FS_CONN_CHK_RX_BITS1:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+      next_RXWaitCount <= 0;
+      end
+    end
+    `WAIT_LS_DIS_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_connectState <= `DISCONNECT;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+    end
+    `WAIT_FS_DIS_CHK_RX_BITS2:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_connectState <= `DISCONNECT;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_rcvr <= `START_SRX;
+  else
+    CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    connectState <= `DISCONNECT;
+    RXWaitCount <= 8'h00;
+    RXStMachCurrState <= `DISCONNECT_ST;
+    RxBits <= 2'b00;
+  end
+  else 
+  begin
+    connectState <= next_connectState;
+    RXWaitCount <= next_RXWaitCount;
+    RXStMachCurrState <= next_RXStMachCurrState;
+    RxBits <= next_RxBits;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(revision 264)
@@ -0,0 +1,105 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=128
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// usbTxWireArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
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+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
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+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
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+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
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+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
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+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n  USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)  \nbegin\n  if (muxSIENotPTXB  == 1'b1)  \n  begin\n    USBWireWEn <= SIETxWEn;\n    TxBits <= SIETxData;\n    TxCtl <= SIETxCtrl;\n  end\n  else\n  begin\n    USBWireWEn <= prcTxByteWEn;\n    TxBits <= prcTxByteData;\n    TxCtl <= prcTxByteCtrl;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
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+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
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+I 113 0 130 Builtin InPort | 156447,162745 "" ""
+L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/busInterface/wishBoneBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/busInterface/wishBoneBI.v	(revision 264)
@@ -0,0 +1,246 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBI.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "wishBoneBus_h.v"
+
+ 
+module wishBoneBI (
+  address, dataIn, dataOut, writeEn, 
+  strobe_i,
+  ack_o,
+  clk, rst,
+  hostControlSel, 
+  hostRxFifoSel, hostTxFifoSel,
+  slaveControlSel,
+  slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, 
+  slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, 
+  hostSlaveMuxSel,
+  dataFromHostControl,
+  dataFromHostRxFifo,
+  dataFromHostTxFifo,
+  dataFromSlaveControl,
+  dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+  dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+  dataFromHostSlaveMux
+   );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+  dataFromHostControl or
+  dataFromHostRxFifo or
+  dataFromHostTxFifo or
+  dataFromSlaveControl or
+  dataFromEP0RxFifo or 
+  dataFromEP1RxFifo or
+  dataFromEP2RxFifo or
+  dataFromEP3RxFifo or
+  dataFromHostSlaveMux or 
+  dataFromEP0TxFifo or
+  dataFromEP1TxFifo or
+  dataFromEP2TxFifo or
+  dataFromEP3TxFifo)
+begin
+  hostControlSel <= 1'b0;
+  hostRxFifoSel <= 1'b0;
+  hostTxFifoSel <= 1'b0;
+  slaveControlSel <= 1'b0;
+  slaveEP0RxFifoSel <= 1'b0;
+  slaveEP0TxFifoSel <= 1'b0;
+  slaveEP1RxFifoSel <= 1'b0;
+  slaveEP1TxFifoSel <= 1'b0;
+  slaveEP2RxFifoSel <= 1'b0;
+  slaveEP2TxFifoSel <= 1'b0;
+  slaveEP3RxFifoSel <= 1'b0;
+  slaveEP3TxFifoSel <= 1'b0;
+  hostSlaveMuxSel <= 1'b0;
+  case (address & `ADDRESS_DECODE_MASK)
+    `HCREG_BASE : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HCREG_BASE_PLUS_0X10 : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HOST_RX_FIFO_BASE : begin
+      hostRxFifoSel <= 1'b1;
+      dataOut <= dataFromHostRxFifo;
+    end
+    `HOST_TX_FIFO_BASE : begin
+      hostTxFifoSel <= 1'b1;
+      dataOut <= dataFromHostTxFifo;
+    end
+    `SCREG_BASE : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `SCREG_BASE_PLUS_0X10 : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `EP0_RX_FIFO_BASE : begin
+      slaveEP0RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0RxFifo;
+    end
+    `EP0_TX_FIFO_BASE : begin
+      slaveEP0TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0TxFifo;
+    end
+    `EP1_RX_FIFO_BASE : begin
+      slaveEP1RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1RxFifo;
+    end
+    `EP1_TX_FIFO_BASE : begin
+      slaveEP1TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1TxFifo;
+    end
+    `EP2_RX_FIFO_BASE : begin
+      slaveEP2RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2RxFifo;
+    end
+    `EP2_TX_FIFO_BASE : begin
+      slaveEP2TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2TxFifo;
+    end
+    `EP3_RX_FIFO_BASE : begin
+      slaveEP3RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3RxFifo;
+    end
+    `EP3_TX_FIFO_BASE : begin
+      slaveEP3TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3TxFifo;
+    end
+    `HOST_SLAVE_CONTROL_BASE : begin
+      hostSlaveMuxSel <= 1'b1; 
+      dataOut <= dataFromHostSlaveMux;
+    end
+    default: 
+      dataOut <= 8'h00;
+  endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+  ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+  ack_immediate <= strobe_i;
+end 
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+  if (writeEn == 1'b0 &&
+      (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+  begin
+    ack_o <= ack_delayed;
+  end
+  else
+  begin
+    ack_o <= ack_immediate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.asf	(revision 264)
@@ -0,0 +1,287 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=259
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// getpacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
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+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 33
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+END
+INSTHEADER 251
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "getPkt"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: getPacket"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
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+A 42 41 16 TEXT "Actions" | 81060,99034 1 0 0 "RXTimeOut <= 1'b1;"
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+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
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+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
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+I 123 120 0 Builtin Entry | 33260,254940
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+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176799,72082 177196,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177616,25344 184028,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n  RXPktStatus = { \n  dataSequence, ACKRxed, \n  stallRxed, NAKRxed,\n  RXTimeOut, RXOverflow, \n  bitStuffError, CRCError};\nend"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+                                           57686,214631 75382,223396 84426,228258
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.asf	(revision 264)
@@ -0,0 +1,283 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=432
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hostController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 47
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 49
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 51
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+A 302 83 16 TEXT "Actions" | 136700,161820 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+                                        170250,145750 137550,145450 128737,144962 119925,144475\
+                                        117963,142662 116688,141837
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+A 334 332 16 TEXT "Actions" | 87236,105298 1 0 0 "getPacketREn <= 1'b1;"
+C 333 332 0 TEXT "Conditions" | 48120,123470 1 0 0 "sendPacketRdy == 1'b1"
+W 332 66 0 220 331 BEZIER "Transitions" | 82714,126587 85717,114267 91541,91328 94544,79008
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+I 55 52 0 Builtin Entry | 88756,239499
+I 56 52 0 Builtin Exit | 155694,46048
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+C 321 320 0 TEXT "Conditions" | 124852,185328 1 0 0 "sendPacketRdy == 1'b1"
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+                                          110726,37400 115182,37514 117348,37514
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+I 366 73 0 Builtin Entry | 66816,246531
+I 365 73 0 Builtin Exit | 138662,35952
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+                                          129080,35838 133536,35952 135702,35952
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 95 6 0 294 41 BEZIER "Transitions" | 117484,22592 114800,20099 105581,15162 96803,16522\
+                                       88026,17883 53248,36150 43780,48625 34312,61101\
+                                       33772,117285 37441,132224 41110,147164 52980,154980\
+                                       61012,157537 69044,160095 94076,164012 106263,166770
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+I 96 6 0 Builtin Reset | 67359,192312
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+W 371 59 2 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+                                          40160,89849 37728,77233 37462,69633 37196,62033\
+                                          38564,44249 44378,36953 50192,29657 72080,18257\
+                                          79528,15331 86976,12405 94012,13028 97964,12876
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+I 411 59 0 Builtin Exit | 100924,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+                                          134254,207065 123583,209376 117848,210301
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+W 167 59 1 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+I 216 66 0 Builtin Exit | 120308,37514
+I 215 66 0 Builtin Entry | 50996,240683
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.v	(revision 264)
@@ -0,0 +1,349 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   [3:0]PID;
+input   rst;
+input   sendPacketWEn;
+input   [6:0]TxAddr;
+input   [3:0]TxEndP;
+output  fifoReadEn;
+output  [10:0]frameNum;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+reg     [10:0]frameNum, next_frameNum;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    [3:0]PID;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+wire    [6:0]TxAddr;
+wire    [3:0]TxEndP;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+  NextState_sndPkt <= CurrState_sndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  next_frameNum <= frameNum;
+  case (CurrState_sndPkt)  // synopsys parallel_case full_case
+    `START_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+    end
+    `WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_sndPkt <= `SP_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `SP_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_HCTxPortReq <= 1'b0;
+    end
+    `SEND_PID_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= PIDNotPID;
+        next_HCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SEND_PID_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+      end
+      else if (PID == `SOF)
+      begin
+        NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+      end
+      else if (PID == `OUT || 
+        PID == `IN || 
+        PID == `SETUP)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sndPkt <= `FIN_SP;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY1:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY2:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `OUT_IN_SETUP_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+    end
+    `SEND_SOF_FIN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_frameNum <= frameNum + 1'b1;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `SEND_SOF_WAIT_RDY3:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= frameNum[7:0];
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_WAIT_RDY4:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_FIN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+    end
+    `DATA0_DATA1_READ_FIFO:
+    begin
+      next_HCTxPortWEn <= 1'b1;
+      next_HCTxPortData <= fifoData;
+      next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+    end
+    `DATA0_DATA1_WAIT_READ_FIFO:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `DATA0_DATA1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+      end
+    end
+    `DATA0_DATA1_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `DATA0_DATA1_TERM_BYTE:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `DATA0_DATA1_CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+    end
+    `DATA0_DATA1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sndPkt <= `START_SP;
+  else
+    CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    HCTxPortData <= 8'h00;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+    frameNum <= 11'h000;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+    frameNum <= next_frameNum;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.v	(revision 264)
@@ -0,0 +1,228 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketcheckpreamble
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   preAmbleEnable;
+input   rst;
+input   [3:0]sendPacketCPPID;
+input   sendPacketCPWEn;
+input   sendPacketRdy;
+output  fullSpeedBitRate;
+output  fullSpeedPolarity;
+output  grabLineControl;    // mux select
+output  sendPacketCPReady;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+
+wire    clk;
+reg     fullSpeedBitRate, next_fullSpeedBitRate;
+reg     fullSpeedPolarity, next_fullSpeedPolarity;
+reg     grabLineControl, next_grabLineControl;
+wire    preAmbleEnable;
+wire    rst;
+wire    [3:0]sendPacketCPPID;
+reg     sendPacketCPReady, next_sendPacketCPReady;
+wire    sendPacketCPWEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_WAIT_RDY2 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_WAIT_RDY3 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
+begin
+  NextState_sendPktCP <= CurrState_sendPktCP;
+  // Set default values for outputs and signals
+  next_sendPacketCPReady <= sendPacketCPReady;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  next_fullSpeedBitRate <= fullSpeedBitRate;
+  next_fullSpeedPolarity <= fullSpeedPolarity;
+  next_grabLineControl <= grabLineControl;
+  case (CurrState_sendPktCP)  // synopsys parallel_case full_case
+    `SPC_WAIT_EN:
+    begin
+      if (sendPacketCPWEn == 1'b1)
+      begin
+        NextState_sendPktCP <= `CHK_PREAM;
+        next_sendPacketCPReady <= 1'b0;
+      end
+    end
+    `START_SPC:
+    begin
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `CHK_PREAM:
+    begin
+      if (preAmbleEnable == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+      end
+    end
+    `READY:
+    begin
+      next_sendPacketCPReady <= 1'b1;
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `PREAM_PKT_SND_PREAM:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= `PREAMBLE;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+      next_sendPacketWEn <= 1'b0;
+    end
+    `PREAM_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+        next_fullSpeedBitRate <= 1'b1;
+        next_fullSpeedPolarity <= 1'b1;
+        next_grabLineControl <= 1'b1;
+      end
+    end
+    `PREAM_PKT_WAIT_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+        next_fullSpeedBitRate <= 1'b1;
+      end
+    end
+    `PREAM_PKT_SND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+      next_sendPacketWEn <= 1'b0;
+    end
+    `PREAM_PKT_WAIT_RDY3:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `READY;
+        next_grabLineControl <= 1'b0;
+      end
+    end
+    `REG_PKT_SEND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+    end
+    `REG_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `REG_PKT_SEND_PID;
+      end
+    end
+    `REG_PKT_WAIT_RDY:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `READY;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktCP <= `START_SPC;
+  else
+    CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketCPReady <= 1'b1;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    fullSpeedBitRate <= 1'b0;
+    fullSpeedPolarity <= 1'b0;
+    grabLineControl <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketCPReady <= next_sendPacketCPReady;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+    fullSpeedBitRate <= next_fullSpeedBitRate;
+    fullSpeedPolarity <= next_fullSpeedPolarity;
+    grabLineControl <= next_grabLineControl;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.v	(revision 264)
@@ -0,0 +1,172 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// softransmit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input   clk;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   SOFEnable;    // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input   SOFSyncEn;
+input   [15:0]SOFTimer;
+output  sendPacketArbiterReq;
+output  sendPacketWEn;
+output  SOFSent;    // single cycle pulse
+output  SOFTimerClr;    // Single cycle pulse
+
+wire    clk;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+wire    SOFEnable;
+reg     SOFSent, next_SOFSent;
+wire    SOFSyncEn;
+wire    [15:0]SOFTimer;
+reg     SOFTimerClr, next_SOFTimerClr;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+  NextState_SOFTx <= CurrState_SOFTx;
+  // Set default values for outputs and signals
+  next_SOFSent <= SOFSent;
+  next_SOFTimerClr <= SOFTimerClr;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketWEn <= sendPacketWEn;
+  case (CurrState_SOFTx)  // synopsys parallel_case full_case
+    `START_STX:
+    begin
+      NextState_SOFTx <= `WAIT_SOF_NEAR;
+    end
+    `WAIT_SOF_NEAR:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+        (SOFSyncEn == 1'b1 &&
+        SOFEnable == 1'b1))
+      begin
+        NextState_SOFTx <= `WAIT_SP_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `WAIT_SP_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+      begin
+        NextState_SOFTx <= `WAIT_SOF_NOW;
+      end
+    end
+    `WAIT_SOF_NOW:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_sendPacketWEn <= 1'b1;
+        next_SOFTimerClr <= 1'b1;
+        next_SOFSent <= 1'b1;
+      end
+      else if (SOFEnable == 1'b0)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_SOFTimerClr <= 1'b1;
+      end
+    end
+    `SOF_FIN:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      next_SOFTimerClr <= 1'b0;
+      next_SOFSent <= 1'b0;
+      NextState_SOFTx <= `WAIT_SOF_NEAR;
+      next_sendPacketArbiterReq <= 1'b0;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SOFTx <= `START_STX;
+  else
+    CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFSent <= 1'b0;
+    SOFTimerClr <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketWEn <= 1'b0;
+  end
+  else 
+  begin
+    SOFSent <= next_SOFSent;
+    SOFTimerClr <= next_SOFTimerClr;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketWEn <= next_sendPacketWEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v	(revision 264)
@@ -0,0 +1,94 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMuxBI.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbHostSlave_h.v"
+
+ module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, clk, rst,
+  hostMode, hostSlaveMuxSel);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+
+//internal wire and regs
+
+//sync write demux
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+    hostMode <= 1'b0;
+  else begin
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+      hostMode <= dataIn[0];
+  end
+end
+
+
+// async read mux
+always @(address or hostMode)
+begin
+  case (address)
+    `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+    `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+  endcase
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSerialInterfaceEngine_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSerialInterfaceEngine_h.v	(revision 264)
@@ -0,0 +1,94 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v                                
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+`define RESUME_WAIT_TIME 10
+`define RESUME_WAIT_TIME_MINUS1 9
+`define RESUME_LEN 20
+`define CONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd20
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates 
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.v	(revision 264)
@@ -0,0 +1,708 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIETransmitter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteRdy;
+input   rst;
+input   [7:0]SIEPortCtrlIn;
+input   [7:0]SIEPortDataIn;
+input   SIEPortWEn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processTxByteWEn;
+output  rstCRC;
+output  SIEPortTxRdy;
+output  [7:0]TxByteOut;
+output  [7:0]TxByteOutCtrl;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+wire    processTxByteRdy;
+reg     processTxByteWEn, next_processTxByteWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]SIEPortCtrlIn;
+wire    [7:0]SIEPortDataIn;
+reg     SIEPortTxRdy, next_SIEPortTxRdy;
+wire    SIEPortWEn;
+reg     [7:0]TxByteOut, next_TxByteOut;
+reg     [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [4:0]i, next_i;
+reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg  [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define RES_ST_CHK_FIN 6'b000000
+`define DIR_CTL_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b000101
+`define PKT_ST_HS_PKT_SENT 6'b000110
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000111
+`define PKT_ST_DATA_PID_PKT_SENT 6'b001000
+`define PKT_ST_SPCL_PKT_SENT 6'b001001
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_S1 6'b001110
+`define RES_ST_S3 6'b001111
+`define RES_ST_S4 6'b010000
+`define RES_ST_S5 6'b010001
+`define RES_ST_S6 6'b010010
+`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
+`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
+`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
+`define START_SIETX 6'b010110
+`define STX_CHK_ST 6'b010111
+`define STX_WAIT_BYTE 6'b011000
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b011001
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b011010
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011011
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011100
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011101
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
+`define RES_ST_WAIT_GNT 6'b011111
+`define DIR_CTL_WAIT_GNT 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
+`define PKT_ST_SPCL_WAIT_RDY 6'b100011
+`define PKT_ST_HS_WAIT_RDY 6'b100100
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100101
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100110
+`define DIR_CTL_WAIT_RDY 6'b100111
+`define RES_ST_WAIT_RDY 6'b101000
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b101001
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101010
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101011
+`define PKT_ST_WAIT_RDY_PKT 6'b101100
+`define PKT_ST_SPCL_WAIT_WIRE 6'b101101
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101110
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101111
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110000
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or SIEPortData or SIEPortCtrl or USBWireRdy or JBit or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireData or USBWireCtrl or TxByteOut or TxByteOutCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
+begin
+  NextState_SIETx <= CurrState_SIETx;
+  // Set default values for outputs and signals
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_USBWireReq <= USBWireReq;
+  next_processTxByteWEn <= processTxByteWEn;
+  next_rstCRC <= rstCRC;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_TxByteOut <= TxByteOut;
+  next_TxByteOutCtrl <= TxByteOutCtrl;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_SIEPortTxRdy <= SIEPortTxRdy;
+  next_SIEPortData <= SIEPortData;
+  next_SIEPortCtrl <= SIEPortCtrl;
+  case (CurrState_SIETx)  // synopsys parallel_case full_case
+    `IDLE:
+    begin
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `START_SIETX:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_TxByteOut <= 8'h00;
+      next_TxByteOutCtrl <= 8'h00;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_SIEPortTxRdy <= 1'b0;
+      next_SIEPortData <= 8'h00;
+      next_SIEPortCtrl <= 8'h00;
+      next_i <= 5'h0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `STX_CHK_ST:
+    begin
+      if (SIEPortCtrl == `TX_PACKET_START)
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+      end
+      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_IDLE)
+      begin
+        NextState_SIETx <= `IDLE;
+      end
+      else if (SIEPortCtrl == `TX_RESUME_START)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+        next_i <= 5'h0;
+      end
+    end
+    `STX_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `STX_CHK_ST;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `DIR_CTL_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_i <= i + 1'b1;
+      if (i == 5'h7)
+      begin
+        NextState_SIETx <= `STX_WAIT_BYTE;
+        next_USBWireReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+      end
+    end
+    `DIR_CTL_WAIT_GNT:
+    begin
+      next_i <= 5'h0;
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+      end
+    end
+    `DIR_CTL_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_CHK_FIN;
+        next_USBWireData <= SIEPortData[1:0];
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `PKT_ST_CHK_PID:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      if (SIEPortData[1:0] == `TOKEN)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `HANDSHAKE)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `DATA)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `SPECIAL)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+      end
+    end
+    `PKT_ST_WAIT_RDY_PKT:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_CHK_PID;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= `SYNC_BYTE;
+        next_TxByteOutCtrl <= `DATA_START;
+      end
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT2:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY1:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[7:0];
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY2:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[15:8];
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_DATA_DATA_CHK_STOP:
+    begin
+      if (SIEPortCtrl == `TX_PACKET_STOP)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+      end
+    end
+    `PKT_ST_DATA_DATA_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_DATA_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC16En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+    end
+    `PKT_ST_DATA_DATA_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_RDY:
+    begin
+      next_CRC16En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+      end
+    end
+    `PKT_ST_DATA_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `PKT_ST_HS_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_HS_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_SPCL_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
+    end
+    `PKT_ST_SPCL_SEND_IDLE1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `PKT_ST_SPCL_SEND_IDLE2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `PKT_ST_SPCL_SEND_IDLE3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_SPCL_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_SPCL_WAIT_WIRE:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_BYTE1_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_CRC_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_CRC_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+    end
+    `PKT_ST_TKN_CRC_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `RES_ST_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (i == `RESUME_LEN)
+      begin
+        NextState_SIETx <= `RES_ST_S1;
+      end
+      else
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_RDY;
+      end
+    end
+    `RES_ST_S1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_S3;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_S3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_S4;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_S4:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_S5;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_S5:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_S6;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_S6:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `RES_ST_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_RDY;
+      end
+    end
+    `RES_ST_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_CHK_FIN;
+        next_USBWireData <= KBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+        next_i <= i + 1'b1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SIETx <= `START_SIETX;
+  else
+    CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    USBWireWEn <= 1'b0;
+    USBWireReq <= 1'b0;
+    processTxByteWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    TxByteOut <= 8'h00;
+    TxByteOutCtrl <= 8'h00;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    SIEPortTxRdy <= 1'b0;
+    i <= 5'h0;
+    SIEPortData <= 8'h00;
+    SIEPortCtrl <= 8'h00;
+  end
+  else 
+  begin
+    USBWireWEn <= next_USBWireWEn;
+    USBWireReq <= next_USBWireReq;
+    processTxByteWEn <= next_processTxByteWEn;
+    rstCRC <= next_rstCRC;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    TxByteOut <= next_TxByteOut;
+    TxByteOutCtrl <= next_TxByteOutCtrl;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    SIEPortTxRdy <= next_SIEPortTxRdy;
+    i <= next_i;
+    SIEPortData <= next_SIEPortData;
+    SIEPortCtrl <= next_SIEPortCtrl;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.asf	(revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processRxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+W 72 6 0 42 357 BEZIER "Transitions" | 123133,41607 132448,51732 153635,72170 162950,82295
+L 74 75 0 TEXT "State Labels" | 65748,212778 1 0 0 "DO_CHK\n/5/"
+S 75 17 45056 ELLIPSE "States" | 65748,212778 6500 6500
+W 76 17 8194 75 18 BEZIER "Transitions" | 69849,207737 75657,200807 99461,167483 105269,160553
+A 78 65 16 TEXT "Actions" | 51039,182627 1 0 0 "RxByte <= RxByteIn;\nRxCtrl <= RxCtrlIn;\nprocessRxByteRdy <= 1'b0;"
+I 336 0 2 Builtin Signal | 172074,243343 "" ""
+L 337 338 0 TEXT "Labels" | 175074,238702 1 0 0 "dataSequence"
+I 338 0 2 Builtin Signal | 172074,238702 "" ""
+L 341 342 0 TEXT "Labels" | 174929,216623 1 0 0 "RxByte[7:0]"
+I 342 0 130 Builtin Signal | 171929,216623 "" ""
+L 343 344 0 TEXT "Labels" | 175286,221621 1 0 0 "RxCtrl[7:0]"
+I 344 0 130 Builtin Signal | 172286,221621 "" ""
+L 345 346 0 TEXT "Labels" | 119382,216211 1 0 0 "RXByteStMachCurrState[2:0]"
+I 346 0 130 Builtin Signal | 116382,216211 "" ""
+A 349 9 4 TEXT "Actions" | 143783,207627 1 0 0 "RxByte <= 8'h00;\nRxCtrl <= 8'h00;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nRxTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxDataOut <= 8'h00;\nRxCtrlOut <= 8'h00;\nRxDataOutWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nRXDataByteCnt <= 10'h00;\nprocessRxByteRdy <= 1'b1;"
+W 351 6 0 357 63 BEZIER "Transitions" | 165899,88318 165621,91424 166582,101426 164321,105232\
+                                        162060,109038 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 135270,157360\
+                                        132480,162850 129690,168340 122852,170455 118982,171355
+L 339 340 0 TEXT "Labels" | 175498,229252 1 0 0 "RxStatus[7:0]"
+I 340 0 128 Builtin Signal | 172498,229252 "" ""
+W 361 358 0 359 360 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+I 360 358 0 Builtin Exit | 129540,111760
+I 359 358 0 Builtin Entry | 86360,167640
+H 358 357 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 357 6 81940 ELLIPSE "Junction" | 165320,84870 3500 3500
+L 356 357 0 TEXT "State Labels" | 165320,84870 1 0 0 "J1"
+W 82 17 4097 75 21 BEZIER "Transitions" | 63199,206800 60009,197085 40708,156469 41288,147696\
+                                          41868,138924 51896,113272 59871,108777 67846,104282\
+                                          74724,97474 86324,92674
+W 81 17 0 20 75 BEZIER "Transitions" | 49379,248076 53439,241189 58262,225186 62322,218299
+L 352 353 0 TEXT "Labels" | 175356,234668 1 0 0 "CRCError"
+I 353 0 2 Builtin Signal | 172356,234668 "" ""
+L 354 355 0 TEXT "Labels" | 80612,216204 1 0 0 "RXDataByteCnt[9:0]"
+I 355 0 130 Builtin Signal | 77612,216204 "" ""
+L 366 367 0 TEXT "Labels" | 80453,221558 1 0 0 "Signal1"
+I 367 0 2 Builtin Signal | 77453,221558 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+L 381 382 0 TEXT "Labels" | 84990,227664 1 0 0 "processRxByteRdy"
+L 368 369 0 TEXT "Labels" | 132404,226868 1 0 0 "CRC5UpdateRdy"
+I 369 0 2 Builtin InPort | 126404,226868 "" ""
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
+W 372 41 0 371 40 BEZIER "Transitions" | 35330,224745 46935,215765 58540,206785 70145,197805
+C 373 372 0 TEXT "Conditions" | 40381,225556 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 374 375 0 TEXT "Labels" | 132404,222116 1 0 0 "CRC16UpdateRdy"
+I 375 0 2 Builtin InPort | 126404,222116 "" ""
+L 376 377 0 TEXT "State Labels" | 76540,228660 1 0 0 "WAIT_CRC\n/14/"
+S 377 50 90112 ELLIPSE "States" | 76540,228660 6500 6500
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+W 379 50 0 377 293 BEZIER "Transitions" | 76802,222169 77769,207119 78297,178932 79264,163882
+C 380 379 0 TEXT "Conditions" | 39560,213610 1 0 0 "CRC16UpdateRdy == 1'b1"
+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC5Result != 5'h6)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    if (RXDataByteCnt > 10'h2) \n    begin\n      RxOverflow <= 1'b1;\n      RxDataOut <= RxStatus;\n      RxCtrlOut <= `RX_PACKET_STOP;\n      RXByteStMachCurrState <= `IDLE_BYTE_ST;\n    end\n    else \n    begin\n      RxDataOut <= RxByte;\n      RxCtrlOut <= `RX_PACKET_STREAM;\n      CRCData <= RxByte;\n      CRC5_8Bit <= 1'b1;\n      CRC5En <= 1'b1;\n    end\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+I 220 217 0 Builtin Entry | 86360,167640
+I 221 217 0 Builtin Exit | 136710,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+I 227 224 0 Builtin Entry | 86360,167640
+I 228 224 0 Builtin Exit | 129540,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n  RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n  RXByteStMachCurrState = `IDLE_BYTE_ST;"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n  RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n  `SPECIAL:                              //Special PID.\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  `TOKEN:                                //Token PID\n  begin\n    RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\n  `HANDSHAKE:                            //Handshake PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        ACKRxed <= 1'b1;\n      2'b10:\n        NAKRxed <= 1'b1;\n      2'b11:\n        stallRxed <= 1'b1;\n      default:\n      begin\n        $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n      end\n    endcase\n    RXByteStMachCurrState <= `HS_BYTE_ST;\n  end\n  `DATA:                                  //Data PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        dataSequence <= 1'b0;\n      2'b10:\n        dataSequence <= 1'b1;\n      default:\n        $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n    endcase\n    RXByteStMachCurrState <= `DATA_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\nendcase"
+I 252 248 0 Builtin Entry | 35384,229000
+I 253 248 0 Builtin Exit | 78564,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+                                          110499,87996 110355,80840 110355,80474
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n  RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+I 260 32 0 Builtin Exit | 110355,78302
+I 259 32 0 Builtin Entry | 66351,233704
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+                                        89364,102368 89220,95212 89220,94846
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/readUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/readUSBWireData.v	(revision 264)
@@ -0,0 +1,222 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// readUSBWireData.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut);
+input   [1:0] RxBitsIn;
+output  RxDataInTick;
+input   SIERxRdyIn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+input   TxWireActiveDrive;
+output  [1:0] RxBitsOut;
+output  SIERxWEn;
+output noActivityTimeOut;
+
+wire   [1:0] RxBitsIn;
+reg    RxDataInTick;
+wire   SIERxRdyIn;
+wire   clk;
+wire   fullSpeedRate;
+wire   rst;
+reg    [1:0] RxBitsOut;
+reg    SIERxWEn;
+reg    noActivityTimeOut;
+
+// local registers
+reg  [1:0]buffer0;
+reg  [1:0]buffer1;
+reg  [1:0]buffer2;
+reg  [1:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg  [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg RxWireActive;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 2'b00;
+    buffer1 <= 2'b00;
+    buffer2 <= 2'b00;
+    buffer3 <= 2'b00;
+    RxDataInTick <= 1'b0;
+    RxWireActive <= 1'b0;
+  end
+  else begin
+    RxBitsInReg <= RxBitsIn;      //sync to local clock to avoid metastability issues
+    incBufferCnt <= 1'b0;         //default value
+    oldRxBitsIn <= RxBitsInReg;
+    if (oldRxBitsIn != RxBitsInReg) begin  //if edge detected then
+      i <= 5'b00000;              //reset the counter
+      RxWireActive <= 1'b1;       // flag receive activity
+    end
+    else begin
+      i <= i + 1'b1;
+      RxWireActive <= 1'b0;
+    end
+    if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+    begin
+      RxDataInTick <= !RxDataInTick;
+      if (TxWireActiveDrive != 1'b1)  //do not read wire data when transmitter is active
+      begin
+        incBufferCnt <= 1'b1;
+        bufferInIndex <= bufferInIndex + 1'b1;
+        case (bufferInIndex)
+          2'b00 : buffer0 <= RxBitsInReg;
+          2'b01 : buffer1 <= RxBitsInReg;
+          2'b10 : buffer2 <= RxBitsInReg;
+          2'b11 : buffer3 <= RxBitsInReg;
+        endcase
+      end
+    end
+  end
+end
+
+        
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    decBufferCnt <= 1'b0;
+    bufferOutIndex <= 2'b00;
+    RxBitsOut <= 2'b00;
+    SIERxWEn <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+  end
+  else begin
+    case (bufferOutStMachCurrState)
+      `WAIT_BUFFER_NOT_EMPTY:
+      begin
+        if (bufferCnt != 3'b000)
+          bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+      end
+      `WAIT_SIE_RX_READY:
+      begin
+        if (SIERxRdyIn == 1'b1)
+        begin 
+          SIERxWEn <= 1'b1;
+          bufferOutStMachCurrState <= `SIE_RX_WRITE;
+          decBufferCnt <= 1'b1;
+          bufferOutIndex <= bufferOutIndex + 1'b1;
+          case (bufferOutIndex)
+            2'b00 :  RxBitsOut <= buffer0;
+            2'b01 : RxBitsOut <= buffer1;
+            2'b10 : RxBitsOut <= buffer2;
+            2'b11 : RxBitsOut <= buffer3;
+          endcase
+        end
+      end
+      `SIE_RX_WRITE:
+      begin
+        SIERxWEn <= 1'b0;
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+      end
+    endcase
+  end
+end
+
+//generate time out flag if no tx or rx activity
+always @(posedge clk) begin
+  if (rst) begin
+    timeOutCnt <= 16'h0000;
+    noActivityTimeOut <= 1'b0;
+  end
+  else begin
+    if (TxWireActiveDrive == 1'b1 || RxWireActive == 1'b1)
+      timeOutCnt <= 16'h0000;
+    else 
+      timeOutCnt <= timeOutCnt + 1'b1;
+    //if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
+    if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+          || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
+    //if (timeOutCnt == 16'h200)  //temporary hack
+      noActivityTimeOut <= 1'b1;
+    else
+      noActivityTimeOut <= 1'b0;
+  end
+end
+      
+
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC5.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC5.v	(revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC5.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   CRC5_8BitIn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [4:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   CRC5_8BitIn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 5'h1f;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0) begin
+      if (CRCEn == 1'b1) begin
+        ready <= 1'b0;
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        if (CRC5_8BitIn == 1'b1) begin
+          loopEnd <= 4'h7; 
+        end
+        else begin
+          loopEnd <= 4'h2;
+        end
+      end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[4:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == loopEnd) begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v	(revision 264)
@@ -0,0 +1,281 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// writeUSBWireData.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL  3'b100
+
+module writeUSBWireData (
+  TxBitsIn, 
+  TxBitsOut,
+   TxDataOutTick,
+  TxCtrlIn, 
+  TxCtrlOut, 
+  USBWireRdy,
+  USBWireWEn, 
+  TxWireActiveDrive, 
+  fullSpeedRate, 
+  clk, 
+  rst
+   );
+  
+input   [1:0] TxBitsIn;
+input   TxCtrlIn;
+input   USBWireWEn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+output  [1:0] TxBitsOut;
+output TxDataOutTick;
+output  TxCtrlOut;
+output  USBWireRdy;
+output  TxWireActiveDrive;
+
+wire    [1:0] TxBitsIn;
+reg     [1:0] TxBitsOut;
+reg     TxDataOutTick;
+wire    TxCtrlIn;
+reg     TxCtrlOut;
+reg     USBWireRdy;
+wire    USBWireWEn;
+wire    clk;
+wire    fullSpeedRate;
+wire    rst;
+reg     TxWireActiveDrive;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else
+  begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+//buffer input state machine 
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+     incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    USBWireRdy <= 1'b0;
+    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+  end
+  else begin
+    case (bufferInStMachCurrState)
+      `WAIT_BUFFER_NOT_FULL:
+      begin
+        if (bufferCnt != `BUFFER_FULL)  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+      end
+      `WAIT_WRITE_REQ:
+      begin
+        if (USBWireWEn == 1'b1)
+        begin
+          incBufferCnt <= 1'b1;
+          USBWireRdy <= 1'b0;
+          bufferInIndex <= bufferInIndex + 1'b1;
+          case (bufferInIndex)
+            2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+            2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+            2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+            2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+          endcase
+          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+        end
+      end
+      `CLR_INC_BUFFER_CNT:
+      begin
+        incBufferCnt <= 1'b0;
+        if (bufferCnt != (`BUFFER_FULL - 1'b1) )  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+        else begin
+          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+        end
+      end
+    endcase
+  end
+end
+        
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    fullSpeedTick <= 1'b0;
+    lowSpeedTick <= 1'b0;
+  end
+  else
+  begin
+    i <= i + 1'b1;
+    if (i[1:0] == 2'b00)
+      fullSpeedTick <= 1'b1;
+    else
+      fullSpeedTick <= 1'b0; 
+    if (i == 5'b00000)
+      lowSpeedTick <= 1'b1;
+    else
+      lowSpeedTick <= 1'b0;
+  end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferOutIndex <= 2'b00;
+    decBufferCnt <= 1'b0;
+    TxBitsOut <= 2'b00;
+    TxCtrlOut <= `TRI_STATE;
+    TxDataOutTick <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+  end
+  else
+  begin
+    case (bufferOutStMachCurrState)
+      `WAIT_LINE_WRITE:
+      begin
+        if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+        begin
+          TxDataOutTick <= !TxDataOutTick;
+          if (bufferCnt == 0) begin
+            TxBitsOut <= 2'b00;
+            TxCtrlOut <= `TRI_STATE;
+          end
+          else begin
+            bufferOutStMachCurrState <= `LINE_WRITE;
+            decBufferCnt <= 1'b1;
+            bufferOutIndex <= bufferOutIndex + 1'b1;
+            case (bufferOutIndex)
+              2'b00 :
+            begin 
+              TxBitsOut <= buffer0[2:1];
+              TxCtrlOut <= buffer0[0];
+            end
+            2'b01 : 
+            begin
+              TxBitsOut <= buffer1[2:1];
+              TxCtrlOut <= buffer1[0];
+            end
+            2'b10 : 
+            begin 
+              TxBitsOut <= buffer2[2:1];
+              TxCtrlOut <= buffer2[0];
+            end
+            2'b11 : 
+            begin
+              TxBitsOut <= buffer3[2:1];
+              TxCtrlOut <= buffer3[0];
+            end
+            endcase
+          end
+        end
+      end
+      `LINE_WRITE:
+      begin
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+      end
+    endcase
+  end
+end
+
+// control 'TxWireActiveDrive' 
+always @(TxCtrlOut)
+begin  
+  if (TxCtrlOut == `DRIVE)
+    TxWireActiveDrive <= 1'b1;
+  else
+    TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/fifoMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/fifoMux.v	(revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMux (
+  currEndP,
+  //TxFifo
+  TxFifoREn,
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoData,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEmpty,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  //RxFifo
+  RxFifoWEn,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoFull,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+  //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+  //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+  TxFifoREn or
+  RxFifoWEn or
+  TxFifoEP0Data or
+  TxFifoEP1Data or
+  TxFifoEP2Data or
+  TxFifoEP3Data or
+  TxFifoEP0Empty or
+  TxFifoEP1Empty or
+  TxFifoEP2Empty or
+  TxFifoEP3Empty or
+  RxFifoEP0Full or
+  RxFifoEP1Full or
+  RxFifoEP2Full or
+  RxFifoEP3Full)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      TxFifoEP0REn <= TxFifoREn;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP0Data;
+      TxFifoEmpty <= TxFifoEP0Empty;
+      RxFifoEP0WEn <= RxFifoWEn;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP0Full;
+    end
+    2'b01: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= TxFifoREn;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP1Data;
+      TxFifoEmpty <= TxFifoEP1Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= RxFifoWEn;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP1Full;
+    end
+    2'b10: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= TxFifoREn;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP2Data;
+      TxFifoEmpty <= TxFifoEP2Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= RxFifoWEn;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP2Full;
+    end
+    2'b11: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= TxFifoREn;
+      TxFifoData <= TxFifoEP3Data;
+      TxFifoEmpty <= TxFifoEP3Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= RxFifoWEn;
+      RxFifoFull <= RxFifoEP3Full;
+    end
+  endcase  
+end      
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.v	(revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveDirectControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+  NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+  // Set default values for outputs and signals
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvDrctCntl)  // synopsys parallel_case full_case
+    `START_SDC:
+    begin
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+        next_SCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= {6'b000000, directControlLineState};
+        next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      next_SCTxPortReq <= 1'b0;
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvDrctCntl <= `START_SDC;
+  else
+    CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SCTxPortCntl <= 8'h00;
+    SCTxPortData <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.asf	(revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveSendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
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+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP1_WAIT_GNT\n/2/"
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+I 12 6 0 Builtin Reset | 74872,202290
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: slaveSendPacket"
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP1\n/0/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "SP_WAIT_ENABLE\n/1/"
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+W 30 25 0 28 26 BEZIER "Transitions" | 53779,230379 60054,220138 63123,209223 69341,197615
+I 29 25 0 Builtin Exit | 146004,95604
+I 28 25 0 Builtin Entry | 49237,230379
+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
+S 26 25 16384 ELLIPSE "States" | 72734,192072 6500 6500
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 29624,2084 214124,250084
+C 23 22 0 TEXT "Conditions" | 114630,116691 1 0 0 "SCTxPortGnt == 1'b1"
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 112951,104607 113260,100204
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113767,93734 6500 6500
+L 20 21 0 TEXT "State Labels" | 113767,93734 1 0 0 "SP_SEND_PID"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nSCTxPortReq <= 1'b1;"
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+S 47 6 28672 ELLIPSE "States" | 115848,16910 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
+S 45 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,45960 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,45960 1 0 0 "SP_D0_D1"
+W 39 25 0 33 29 BEZIER "Transitions" | 79375,148210 95944,135371 126275,108443 142844,95604
+A 38 33 4 TEXT "Actions" | 93627,154331 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
+C 36 34 0 TEXT "Conditions" | 75236,185214 1 0 0 "SCTxPortRdy == 1'b1"
+W 34 25 0 26 33 BEZIER "Transitions" | 72953,185597 73302,178879 73960,166205 74309,159487
+S 33 25 20480 ELLIPSE "States" | 75021,153035 6500 6500
+L 32 33 0 TEXT "State Labels" | 75021,153035 1 0 0 "FIN\n/4/"
+W 50 6 8193 21 45 BEZIER "Transitions" | 119169,90120 134042,80003 162156,60011 177029,49894
+W 48 6 8194 21 205 BEZIER "Transitions" | 108645,89734 97773,80901 77133,63853 66261,55020
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+W 74 6 0 205 47 BEZIER "Transitions" | 67096,47093 78647,41129 99521,27639 110324,20335
+W 73 6 0 45 47 BEZIER "Transitions" | 176581,42697 162161,37714 135904,25306 121888,19311
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 126 65 0 Builtin Entry | 68162,237252
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 72704,237252 77515,245311 99394,235265 108723,227500
+S 136 65 32768 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1;	 \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170187,37688 173773,37229
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "SCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+L 211 212 0 TEXT "State Labels" | 76973,151815 1 0 0 "CLR_REN\n/13/"
+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 209 65 0 136 207 BEZIER "Transitions" | 103712,132145 117531,130730 143304,126529 157123,125114
+W 210 65 0 207 145 BEZIER "Transitions" | 169895,125680 176804,126013 188953,127552 193864,130465\
+                                          198775,133379 204604,144369 205686,152818 206768,161268\
+                                          205269,184079 201481,192903 197694,201727 184040,214216\
+                                          173218,217462 162396,220708 133810,221642 118992,221891
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/usbSlaveControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/usbSlaveControl.v	(revision 264)
@@ -0,0 +1,493 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSlaveControl(
+  clk, rst,
+  //getPacket
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut, RxFifoData,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //SCTxPortArbiter
+  SCTxPortEn, SCTxPortRdy,
+  SCTxPortData, SCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFRxedIntOut, 
+  resetEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  NAKSentIntOut,
+  slaveControlSelect,
+  //fifoMux
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+input clk, rst;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [4:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut; 
+output resetEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire clk;
+wire rst;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut; 
+wire resetEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed; 
+wire CRCError; 
+wire RXOverflow; 
+wire RXTimeOut; 
+wire bitStuffError; 
+wire dataSequence; 
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [3:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+
+USBSlaveControlBI u_USBSlaveControlBI
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .SOFRxedIntOut(SOFRxedIntOut), 
+  .resetEventIntOut(resetEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .NAKSentIntOut(NAKSentIntOut),
+  .endP0TransTypeReg(endP0TransTypeReg), 
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg), 
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg), 
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg), 
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .EP0StatusReg(endP0StatusReg),
+  .EP1StatusReg(endP1StatusReg),
+  .EP2StatusReg(endP2StatusReg),
+  .EP3StatusReg(endP3StatusReg),
+  .SCAddrReg(USBTgtAddress), 
+  .frameNum(frameNum),
+  .connectStateIn(connectStateOut),
+  .SOFRxedIn(SOFRxed), 
+  .resetEventIn(resetEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .NAKSentIn(NAKSent),
+  .slaveControlSelect(slaveControlSelect),
+  .clrEP0Ready(clrEP0Rdy), 
+  .clrEP1Ready(clrEP1Rdy), 
+  .clrEP2Ready(clrEP2Rdy), 
+  .clrEP3Ready(clrEP3Rdy),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .SCGlobalEn(SCGlobalEn)
+  );
+
+slavecontroller u_slavecontroller
+  (.CRCError(CRCError), 
+  .NAKSent(NAKSent), 
+  .RxByte(RxData), 
+  .RxDataWEn(RxDataValid), 
+  .RxOverflow(RXOverflow), 
+  .RxStatus(RxByteStatus), 
+  .RxTimeOut(RXTimeOut), 
+  .SCGlobalEn(SCGlobalEn), 
+  .SOFRxed(SOFRxed), 
+  .USBEndPControlReg(endPControlReg), 
+  .USBEndPNakTransTypeReg(transTypeNAK), 
+  .USBEndPTransTypeReg(transType), 
+  .USBEndP(currEndP), 
+  .USBTgtAddress(USBTgtAddress),
+  .bitStuffError(bitStuffError), 
+  .clk(clk), 
+  .clrEPRdy(clrEPRdy), 
+  .endPMuxErrorsWEn(endPMuxErrorsWEn), 
+  .frameNum(frameNum), 
+  .getPacketREn(getPacketREn), 
+  .getPacketRdy(getPacketRdy), 
+  .rst(rst), 
+  .sendPacketPID(slaveControllerPIDOut), 
+  .sendPacketRdy(slaveControllerReadyIn), 
+  .sendPacketWEn(slaveControllerWEnOut), 
+  .stallSent(stallSent), 
+  .transDone(transDone) 
+    );
+
+
+endpMux u_endpMux (
+  .clk(clk), 
+  .rst(rst),
+  .currEndP(currEndP),
+  .NAKSent(NAKSent),
+  .stallSent(stallSent),
+  .CRCError(CRCError),
+  .bitStuffError(bitStuffError),
+  .RxOverflow(RXOverflow),
+  .RxTimeOut(RXTimeOut),
+  .dataSequence(dataSequence),
+  .ACKRxed(ACKRxed),
+  .transType(transType),
+  .transTypeNAK(transTypeNAK),
+  .endPControlReg(endPControlReg),
+  .clrEPRdy(clrEPRdy),
+  .endPMuxErrorsWEn(endPMuxErrorsWEn),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .endP0StatusReg(endP0StatusReg),
+  .endP1StatusReg(endP1StatusReg),
+  .endP2StatusReg(endP2StatusReg),
+  .endP3StatusReg(endP3StatusReg),
+  .endP0TransTypeReg(endP0TransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg),
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .clrEP0Rdy(clrEP0Rdy),
+  .clrEP1Rdy(clrEP1Rdy),
+  .clrEP2Rdy(clrEP2Rdy),
+  .clrEP3Rdy(clrEP3Rdy)
+    );
+
+slaveSendPacket u_slaveSendPacket
+  (.PID(slaveControllerPIDOut), 
+  .SCTxPortCntl(sendPacketCntl),
+  .SCTxPortData(sendPacketData),
+  .SCTxPortGnt(sendPacketGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(sendPacketReq),
+  .SCTxPortWEn(sendPacketWEn),
+  .clk(clk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .rst(rst),
+  .sendPacketRdy(slaveControllerReadyIn),
+  .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+  (.SCTxPortCntl(directCntlCntl),
+  .SCTxPortData(directCntlData),
+  .SCTxPortGnt(directCntlGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(directCntlReq),
+  .SCTxPortWEn(directCntlWEn),
+  .clk(clk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rst) ); 
+
+SCTxPortArbiter u_SCTxPortArbiter
+  (.SCTxPortCntl(SCTxPortCtrl),
+  .SCTxPortData(SCTxPortData),
+  .SCTxPortRdyIn(SCTxPortRdy),
+  .SCTxPortRdyOut(SCTxPortArbRdyOut),
+  .SCTxPortWEnable(SCTxPortEn),
+  .clk(clk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rst),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+
+slaveGetPacket u_slaveGetPacket
+  (.ACKRxed(ACKRxed), 
+  .CRCError(CRCError), 
+  .RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .clk(clk),
+  .RXOverflow(RXOverflow), 
+  .RXTimeOut(RXTimeOut), 
+  .bitStuffError(bitStuffError), 
+  .dataSequence(dataSequence), 
+  .getPacketEn(getPacketREn),
+  .rst(rst) ); 
+
+slaveRxStatusMonitor  u_slaveRxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .resetEventOut(resetEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(clk),
+  .rst(rst)  );    
+  
+fifoMux u_fifoMux (
+  .currEndP(currEndP),
+  //TxFifo
+  .TxFifoREn(TxFifoRE),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoData(TxFifoData),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEmpty(TxFifoEmpty),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  //RxFifo
+  .RxFifoWEn(RxFifoWE),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoFull(RxFifoFull),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+    );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/endpMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/endpMux.v	(revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// endpMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSlaveControl_h.v" 
+
+module endpMux (
+  clk, 
+  rst,
+  currEndP,
+  NAKSent,
+  stallSent,
+  CRCError,
+  bitStuffError,
+  RxOverflow,
+  RxTimeOut,
+  dataSequence,
+  ACKRxed,
+  transType,
+  transTypeNAK,
+  endPControlReg,
+  clrEPRdy,
+  endPMuxErrorsWEn,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  endP0StatusReg,
+  endP1StatusReg,
+  endP2StatusReg,
+  endP3StatusReg,
+  endP0TransTypeReg,
+  endP1TransTypeReg,
+  endP2TransTypeReg,
+  endP3TransTypeReg,
+  endP0NAKTransTypeReg,
+  endP1NAKTransTypeReg,
+  endP2NAKTransTypeReg,
+  endP3NAKTransTypeReg,
+  clrEP0Rdy,
+  clrEP1Rdy,
+  clrEP2Rdy,
+  clrEP3Rdy);
+
+
+input clk; 
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [3:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [3:0] endP0ControlReg;
+input [3:0] endP1ControlReg;
+input [3:0] endP2ControlReg;
+input [3:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk; 
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [3:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      endPControlReg <= endP0ControlReg;
+      clrEP0Rdy <= clrEPRdy;
+    end
+    2'b01: begin
+      endPControlReg <= endP1ControlReg;
+      clrEP1Rdy <= clrEPRdy;
+    end
+    2'b10: begin
+      endPControlReg <= endP2ControlReg;
+      clrEP2Rdy <= clrEPRdy;
+    end
+    2'b11: begin
+      endPControlReg <= endP3ControlReg;
+      clrEP3Rdy <= clrEPRdy;
+    end
+  endcase  
+end      
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+  if (rst) begin
+    endP0NAKTransTypeReg <= 2'b00;
+    endP1NAKTransTypeReg <= 2'b00;
+    endP2NAKTransTypeReg <= 2'b00;
+    endP3NAKTransTypeReg <= 2'b00;
+    endP0TransTypeReg <= 2'b00;
+    endP1TransTypeReg <= 2'b00;
+    endP2TransTypeReg <= 2'b00;
+    endP3TransTypeReg <= 2'b00;
+    endP0StatusReg <= 4'h0;
+    endP1StatusReg <= 4'h0;
+    endP2StatusReg <= 4'h0;
+    endP3StatusReg <= 4'h0;
+  end
+  else begin
+    if (endPMuxErrorsWEn == 1'b1) begin
+      if (NAKSent == 1'b1) begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0NAKTransTypeReg <= transTypeNAK;
+            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; 
+          end
+          2'b01: begin
+            endP1NAKTransTypeReg <= transTypeNAK;
+            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; 
+          end
+          2'b10: begin
+            endP2NAKTransTypeReg <= transTypeNAK;
+            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; 
+          end
+          2'b11: begin
+            endP3NAKTransTypeReg <= transTypeNAK;
+            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; 
+          end
+        endcase
+      end
+      else begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0TransTypeReg <= transType;
+            endP0StatusReg <= endPStatusCombine; 
+          end
+          2'b01: begin
+            endP1TransTypeReg <= transType;
+            endP1StatusReg <= endPStatusCombine; 
+          end
+          2'b10: begin
+            endP2TransTypeReg <= transType;
+            endP2StatusReg <= endPStatusCombine; 
+          end
+          2'b11: begin
+            endP3TransTypeReg <= transType;
+            endP3StatusReg <= endPStatusCombine; 
+          end
+        endcase
+      end
+    end
+  end
+end
+        
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveDirectControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= {6'b000000, directControlLineState}; \nSCTxPortCntl <= `TX_DIRECT_CONTROL;"
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+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= 8'h00; \nSCTxPortCntl <= `TX_IDLE;"
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+L 178 179 0 TEXT "Labels" | 63352,247790 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,247790 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveRxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveRxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveRxStatusMonitor.v                                       ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      resetEventOut <= 1'b1;
+    else
+      resetEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.v	(revision 264)
@@ -0,0 +1,472 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input   bitStuffError;
+input   clk;
+input   CRCError;
+input   getPacketRdy;
+input   rst;
+input   [7:0]RxByte;
+input   RxDataWEn;
+input   RxOverflow;
+input   [7:0]RxStatus;
+input   RxTimeOut;
+input   SCGlobalEn;
+input   sendPacketRdy;
+input   [3:0]USBEndPControlReg;
+input   [6:0]USBTgtAddress;
+output  clrEPRdy;
+output  endPMuxErrorsWEn;
+output  [10:0]frameNum;
+output  getPacketREn;
+output  NAKSent;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  SOFRxed;
+output  stallSent;
+output  transDone;
+output  [3:0]USBEndP;
+output  [1:0]USBEndPNakTransTypeReg;
+output  [1:0]USBEndPTransTypeReg;
+
+wire    bitStuffError;
+wire    clk;
+reg     clrEPRdy, next_clrEPRdy;
+wire    CRCError;
+reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg     [10:0]frameNum, next_frameNum;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+reg     NAKSent, next_NAKSent;
+wire    rst;
+wire    [7:0]RxByte;
+wire    RxDataWEn;
+wire    RxOverflow;
+wire    [7:0]RxStatus;
+wire    RxTimeOut;
+wire    SCGlobalEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     SOFRxed, next_SOFRxed;
+reg     stallSent, next_stallSent;
+reg     transDone, next_transDone;
+reg     [3:0]USBEndP, next_USBEndP;
+wire    [3:0]USBEndPControlReg;
+reg     [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg     [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire    [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg  [7:0]addrEndPTemp, next_addrEndPTemp;
+reg  [7:0]endpCRCTemp, next_endpCRCTemp;
+reg  [7:0]PIDByte, next_PIDByte;
+reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg  [6:0]USBAddress, next_USBAddress;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define IN_DATA 5'b01011
+`define IN_GET_RESP 5'b01100
+`define SETUP_OUT_CHK 5'b01101
+`define SETUP_OUT_SEND 5'b01110
+`define SETUP_OUT_GET_PKT 5'b01111
+`define START_S1 5'b10000
+`define GET_TOKEN_DELAY 5'b10001
+`define GET_TOKEN_CHK_ADDR 5'b10010
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)
+begin
+  NextState_slvCntrl <= CurrState_slvCntrl;
+  // Set default values for outputs and signals
+  next_stallSent <= stallSent;
+  next_NAKSent <= NAKSent;
+  next_SOFRxed <= SOFRxed;
+  next_PIDByte <= PIDByte;
+  next_transDone <= transDone;
+  next_clrEPRdy <= clrEPRdy;
+  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+  next_endpCRCTemp <= endpCRCTemp;
+  next_addrEndPTemp <= addrEndPTemp;
+  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+  next_frameNum <= frameNum;
+  next_USBAddress <= USBAddress;
+  next_USBEndP <= USBEndP;
+  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  next_getPacketREn <= getPacketREn;
+  case (CurrState_slvCntrl)  // synopsys parallel_case full_case
+    `WAIT_RX1:
+    begin
+      next_stallSent <= 1'b0;
+      next_NAKSent <= 1'b0;
+      next_SOFRxed <= 1'b0;
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_START && 
+        RxByte[1:0] == `TOKEN)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+        next_PIDByte <= RxByte;
+      end
+    end
+    `FIN_SC:
+    begin
+      next_transDone <= 1'b0;
+      next_clrEPRdy <= 1'b0;
+      next_endPMuxErrorsWEn <= 1'b0;
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_PID:
+    begin
+      if (PIDByte[3:0] == `SETUP)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if (PIDByte[3:0] == `OUT)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if (PIDByte[3:0] == `IN)
+      begin
+        NextState_slvCntrl <= `IN_CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `PID_ERROR;
+      end
+    end
+    `PID_ERROR:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_RDY:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_transDone <= 1'b1;
+        next_clrEPRdy <= 1'b1;
+        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else if (NAKSent == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+      end
+    end
+    `SETUP_OUT_CHK:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `SETUP_OUT_SEND:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `SETUP_OUT_GET_PKT:
+    begin
+      next_getPacketREn <= 1'b0;
+      if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+        bitStuffError == 1'b0 && 
+        RxOverflow == 1'b0 && 
+        RxTimeOut == 1'b0))
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_CHK;
+      end
+      else if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_NAK_STALL:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_CHK_RDY:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `IN_DATA:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_GET_RESP;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_GET_RESP:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `START_S1:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `GET_TOKEN_WAIT_CRC:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+        next_endpCRCTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_ADDR:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+        next_addrEndPTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_STOP:
+    begin
+      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+      end
+      else if (RxDataWEn == 1'b1)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_CHK_SOF:
+    begin
+      if (PIDByte[3:0] == `SOF)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+        next_SOFRxed <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_DELAY;
+        next_USBAddress <= addrEndPTemp[6:0];
+        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+      end
+    end
+    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndPControlReg to update
+    begin
+      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+    end
+    `GET_TOKEN_CHK_ADDR:
+    begin
+      if (USBEndP < `NUM_OF_ENDPOINTS  &&
+        USBAddress == USBTgtAddress &&
+        SCGlobalEn == 1'b1 &&
+        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_PID;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvCntrl <= `START_S1;
+  else
+    CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    stallSent <= 1'b0;
+    NAKSent <= 1'b0;
+    SOFRxed <= 1'b0;
+    transDone <= 1'b0;
+    clrEPRdy <= 1'b0;
+    endPMuxErrorsWEn <= 1'b0;
+    frameNum <= 11'b00000000000;
+    USBEndP <= 4'h0;
+    USBEndPTransTypeReg <= 2'b00;
+    USBEndPNakTransTypeReg <= 2'b00;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    getPacketREn <= 1'b0;
+    PIDByte <= 8'h00;
+    endpCRCTemp <= 8'h00;
+    addrEndPTemp <= 8'h00;
+    tempUSBEndPTransTypeReg <= 2'b00;
+    USBAddress <= 7'b0000000;
+  end
+  else 
+  begin
+    stallSent <= next_stallSent;
+    NAKSent <= next_NAKSent;
+    SOFRxed <= next_SOFRxed;
+    transDone <= next_transDone;
+    clrEPRdy <= next_clrEPRdy;
+    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+    frameNum <= next_frameNum;
+    USBEndP <= next_USBEndP;
+    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+    getPacketREn <= next_getPacketREn;
+    PIDByte <= next_PIDByte;
+    endpCRCTemp <= next_endpCRCTemp;
+    addrEndPTemp <= next_addrEndPTemp;
+    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+    USBAddress <= next_USBAddress;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(revision 264)
@@ -0,0 +1,370 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine.v                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSerialInterfaceEngine(
+  clk, rst,
+  //readUSBWireData
+  USBWireDataIn,
+  USBWireDataInTick,
+  //writeUSBWireData
+  USBWireDataOut,
+  USBWireCtrlOut,
+  USBWireDataOutTick,
+  //SIEReceiver
+  connectState,
+  //processRxBit
+  resumeDetected,
+  //processRxByte
+  RxCtrlOut, 
+  RxDataOutWEn, 
+  RxDataOut, 
+    //SIETransmitter
+  SIEPortCtrlIn,
+  SIEPortDataIn, 
+  SIEPortTxRdy, 
+  SIEPortWEn, 
+    //lineControlUpdate
+  fullSpeedPolarity,
+  fullSpeedBitRate,
+  noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut; 
+output RxDataOutWEn; 
+output [7:0] RxDataOut; 
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy; 
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut; 
+wire RxDataOutWEn; 
+wire [7:0] RxDataOut; 
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy; 
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En; 
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En; 
+wire [4:0] RxCRC5Result; 
+wire RxCRC5_8Bit; 
+wire [7:0] RxCRCData; 
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En; 
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En; 
+wire [4:0] TxCRC5Result; 
+wire TxCRC5_8Bit; 
+wire [7:0] TxCRCData; 
+wire TxRstCRC; 
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy; 
+wire processTxByteWEn; 
+
+lineControlUpdate u_lineControlUpdate
+  (.fullSpeedPolarity(fullSpeedPolarity),
+  .fullSpeedBitRate(fullSpeedBitRate),
+  .JBit(JBit),
+  .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+  (
+  .RxWireDataIn(RxWireDataFromWireRx), 
+  .RxWireDataWEn(RxWireDataWEn), 
+  .clk(clk),
+  .connectState(connectState),
+  .rst(rst) );
+
+  
+processRxBit u_processRxBit
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .RxBitsIn(RxWireDataFromWireRx), 
+  .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxDataOut(RxDataFromPrcRxBitToPrcRxByte), 
+  .clk(clk), 
+  .processRxBitRdy(processRxBitRdy), 
+  .processRxBitsWEn(RxWireDataWEn), 
+  .processRxByteWEn(processRxByteWEn), 
+  .resumeDetected(resumeDetected), 
+  .rst(rst),
+  .processRxByteRdy(processRxByteRdy) );
+  
+processRxByte u_processRxByte
+  (.CRC16En(RxCRC16En), 
+  .CRC16Result(RxCRC16Result), 
+  .CRC16UpdateRdy(RxCRC16UpdateRdy),
+  .CRC5En(RxCRC5En), 
+  .CRC5Result(RxCRC5Result), 
+  .CRC5_8Bit(RxCRC5_8Bit),
+  .CRC5UpdateRdy(RxCRC5UpdateRdy),
+  .CRCData(RxCRCData), 
+  .RxByteIn(RxDataFromPrcRxBitToPrcRxByte), 
+  .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataOut), 
+  .clk(clk), 
+  .processRxDataInWEn(processRxByteWEn), 
+  .rst(rst), 
+  .rstCRC(RxRstCRC),
+  .processRxByteRdy(processRxByteRdy) ); 
+  
+  
+updateCRC5 RxUpdateCRC5
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC5Result), 
+  .CRCEn(RxCRC5En), 
+  .CRC5_8BitIn(RxCRC5_8Bit), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 RxUpdateCRC16
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC16Result), 
+  .CRCEn(RxCRC16En), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+SIETransmitter u_SIETransmitter
+  (.CRC16En(TxCRC16En), 
+  .CRC16Result(TxCRC16Result), 
+  .CRC5En(TxCRC5En), 
+  .CRC5Result(TxCRC5Result), 
+  .CRC5_8Bit(TxCRC5_8Bit), 
+  .CRCData(TxCRCData),
+  .CRC5UpdateRdy(TxCRC5UpdateRdy),
+  .CRC16UpdateRdy(TxCRC16UpdateRdy),
+  .JBit(JBit), 
+  .KBit(KBit), 
+  .SIEPortCtrlIn(SIEPortCtrlIn),
+  .SIEPortDataIn(SIEPortDataIn), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEn), 
+  .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteOut(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(SIETxCtrl), 
+  .USBWireData(SIETxData), 
+  .USBWireGnt(SIETxGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(SIETxReq), 
+  .USBWireWEn(SIETxWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst), 
+  .rstCRC(TxRstCRC) );    
+
+updateCRC5 TxUpdateCRC5
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC5Result), 
+  .CRCEn(TxCRC5En), 
+  .CRC5_8BitIn(TxCRC5_8Bit), 
+  .dataIn(TxCRCData),
+  .ready(TxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 TxUpdateCRC16
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC16Result), 
+  .CRCEn(TxCRC16En), 
+  .dataIn(TxCRCData), 
+  .ready(TxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+
+processTxByte u_processTxByte
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteIn(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(prcTxByteCtrl), 
+  .USBWireData(prcTxByteData), 
+  .USBWireGnt(prcTxByteGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(prcTxByteReq), 
+  .USBWireWEn(prcTxByteWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst),
+  .fullSpeedRate(fullSpeedBitRate) ); 
+  
+USBTxWireArbiter u_USBTxWireArbiter
+  (.SIETxCtrl(SIETxCtrl), 
+  .SIETxData(SIETxData), 
+  .SIETxGnt(SIETxGnt), 
+  .SIETxReq(SIETxReq), 
+  .SIETxWEn(SIETxWEn), 
+  .TxBits(TxBitsFromArbToWire), 
+  .TxCtl(TxCtrlFromArbToWire), 
+  .USBWireRdyIn(USBWireRdy), 
+  .USBWireRdyOut(USBWireReadyFromTxArb), 
+  .USBWireWEn(USBWireWEn),
+  .clk(clk), 
+  .prcTxByteCtrl(prcTxByteCtrl), 
+  .prcTxByteData(prcTxByteData), 
+  .prcTxByteGnt(prcTxByteGnt), 
+  .prcTxByteReq(prcTxByteReq), 
+  .prcTxByteWEn(prcTxByteWEn), 
+  .rst(rst) ); 
+  
+writeUSBWireData u_writeUSBWireData
+  (.TxBitsIn(TxBitsFromArbToWire), 
+  .TxBitsOut(USBWireDataOut), 
+  .TxDataOutTick(USBWireDataOutTick),
+  .TxCtrlIn(TxCtrlFromArbToWire), 
+  .TxCtrlOut(USBWireCtrlOut), 
+  .USBWireRdy(USBWireRdy), 
+  .USBWireWEn(USBWireWEn),
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .fullSpeedRate(fullSpeedBitRate), 
+  .clk(clk),
+  .rst(rst)
+   );  
+
+  
+  
+readUSBWireData u_readUSBWireData
+  (.RxBitsIn(USBWireDataIn), 
+  .RxDataInTick(USBWireDataInTick),
+  .RxBitsOut(RxWireDataFromWireRx), 
+  .SIERxRdyIn(processRxBitRdy), 
+  .SIERxWEn(RxWireDataWEn), 
+  .fullSpeedRate(fullSpeedBitRate), 
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .clk(clk),
+  .rst(rst),
+  .noActivityTimeOut(noActivityTimeOut));
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/USBSlaveControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/USBSlaveControlBI.v	(revision 264)
@@ -0,0 +1,390 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBSlaveControlBI.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbSlaveControl_h.v"
+ 
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+  SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+  endP0TransTypeReg, endP0NAKTransTypeReg,
+  endP1TransTypeReg, endP1NAKTransTypeReg,
+  endP2TransTypeReg, endP2NAKTransTypeReg,
+  endP3TransTypeReg, endP3NAKTransTypeReg,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  EP0StatusReg,
+  EP1StatusReg,
+  EP2StatusReg,
+  EP3StatusReg,
+  SCAddrReg, frameNum,
+  connectStateIn,
+  SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+  slaveControlSelect,
+  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  SCGlobalEn
+  );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg; 
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg; 
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg; 
+input [1:0] endP3NAKTransTypeReg;
+output [3:0] endP0ControlReg;
+output [3:0] endP1ControlReg;
+output [3:0] endP2ControlReg;
+output [3:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg; 
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg; 
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg; 
+wire [1:0] endP3NAKTransTypeReg;
+reg [3:0] endP0ControlReg;
+reg [3:0] endP1ControlReg;
+reg [3:0] endP2ControlReg;
+reg [3:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+
+//sync write demux
+always @(posedge clk)
+begin
+  clrNAKReq <= 1'b0;
+  clrSOFReq <= 1'b0;
+  clrResetReq <= 1'b0;
+  clrResInReq <= 1'b0;
+  clrTransDoneReq <= 1'b0;
+  EP0SetReady <= 1'b0;
+  EP1SetReady <= 1'b0;
+  EP2SetReady <= 1'b0;
+  EP3SetReady <= 1'b0;
+  if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+  begin
+    case (address)
+      `EP0_CTRL_REG : begin
+        EP0SendStall <= dataIn[3];
+        EP0DataSequence <= dataIn[2];
+        EP0SetReady <= dataIn[1];
+        EP0Enable <= dataIn[0];
+      end
+      `EP1_CTRL_REG : begin
+        EP1SendStall <= dataIn[3];
+        EP1DataSequence <= dataIn[2];
+        EP1SetReady <= dataIn[1];
+        EP1Enable <= dataIn[0];
+      end
+      `EP2_CTRL_REG : begin
+        EP2SendStall <= dataIn[3];
+        EP2DataSequence <= dataIn[2];
+        EP2SetReady <= dataIn[1];
+        EP2Enable <= dataIn[0];
+      end
+      `EP3_CTRL_REG : begin
+        EP3SendStall <= dataIn[3];
+        EP3DataSequence <= dataIn[2];
+        EP3SetReady <= dataIn[1];
+        EP3Enable <= dataIn[0];
+      end
+      `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+      `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+      `SC_INTERRUPT_STATUS_REG : begin
+        clrNAKReq <= dataIn[4];
+        clrSOFReq <= dataIn[3];
+        clrResetReq <= dataIn[2];
+        clrResInReq <= dataIn[1];
+        clrTransDoneReq <= dataIn[0];
+      end
+      `SC_INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[4:0];
+    endcase
+  end
+end
+
+//interrupt control 
+always @(posedge clk)
+begin
+  if (NAKSentIn == 1'b1)
+    NAKSentInt <= 1'b1;
+  else if (clrNAKReq == 1'b1)
+    NAKSentInt <= 1'b0; 
+    
+  if (SOFRxedIn == 1'b1)
+    SOFRxedInt <= 1'b1;
+  else if (clrSOFReq == 1'b1)
+    SOFRxedInt <= 1'b0;
+    
+  if (resetEventIn == 1'b1)
+    resetEventInt <= 1'b1;
+  else if (clrResetReq == 1'b1)
+    resetEventInt <= 1'b0;
+    
+  if (resumeIntIn == 1'b1)
+    resumeInt <= 1'b1;
+  else if (clrResInReq == 1'b1)
+    resumeInt <= 1'b0;  
+
+  if (transDoneIn == 1'b1)
+    transDoneInt <= 1'b1;
+  else if (clrTransDoneReq == 1'b1)
+    transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end  
+
+//end point ready, set/clear
+always @(posedge clk)
+begin
+  if (EP0SetReady == 1'b1)
+    EP0Ready <= 1'b1;
+  else if (clrEP0Ready == 1'b1)
+    EP0Ready <= 1'b0;
+    
+  if (EP1SetReady == 1'b1)
+    EP1Ready <= 1'b1;
+  else if (clrEP1Ready == 1'b1)
+    EP1Ready <= 1'b0;
+    
+  if (EP2SetReady == 1'b1)
+    EP2Ready <= 1'b1;
+  else if (clrEP2Ready == 1'b1)
+    EP2Ready <= 1'b0;
+    
+  if (EP3SetReady == 1'b1)
+    EP3Ready <= 1'b1;
+  else if (clrEP3Ready == 1'b1)
+    EP3Ready <= 1'b0;
+end  
+  
+//break out control signals
+always @(SCControlReg) begin
+  SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+  TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+  fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals 
+always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable) 
+begin
+  endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+  endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+  endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+  endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+      
+      
+      // async read mux
+always @(address or
+  EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+  EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
+  endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
+  endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or 
+  endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
+  SCControlReg or connectStateIn or
+  NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or SCAddrReg or frameNum)
+begin
+  case (address)
+      `EP0_CTRL_REG : dataOut <= endP0ControlReg;
+      `EP0_STS_REG : dataOut <= EP0StatusReg;
+      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
+      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
+      `EP1_CTRL_REG : dataOut <= endP1ControlReg;
+      `EP1_STS_REG :  dataOut <= EP1StatusReg;
+      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
+      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
+      `EP2_CTRL_REG : dataOut <= endP2ControlReg;
+      `EP2_STS_REG :  dataOut <= EP2StatusReg;
+      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
+      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
+      `EP3_CTRL_REG : dataOut <= endP3ControlReg;
+      `EP3_STS_REG :  dataOut <= EP3StatusReg;
+      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
+      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
+      `SC_CONTROL_REG : dataOut <= SCControlReg;
+      `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn}; 
+      `SC_INTERRUPT_STATUS_REG :  dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+      `SC_INTERRUPT_MASK_REG  : dataOut <= {3'b000, interruptMaskReg};
+      `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+      `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNum[10:8]};
+      `SC_FRAME_NUM_LSP : dataOut <= frameNum[7:0];
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.v	(revision 264)
@@ -0,0 +1,197 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SCTxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   SCTxPortRdyIn;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  directCntlGnt;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortRdyOut;
+output  SCTxPortWEnable;
+output  sendPacketGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortRdyIn;
+reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg     SCTxPortWEnable, next_SCTxPortWEnable;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+  NextState_SCTxArb <= CurrState_SCTxArb;
+  // Set default values for outputs and signals
+  next_sendPacketGnt <= sendPacketGnt;
+  next_muxDCEn <= muxDCEn;
+  next_directCntlGnt <= directCntlGnt;
+  case (CurrState_SCTxArb)  // synopsys parallel_case full_case
+    `SARB1_WAIT_REQ:
+    begin
+      if (sendPacketReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxDCEn <= 1'b0;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_DC;
+        next_directCntlGnt <= 1'b1;
+        next_muxDCEn <= 1'b1;
+      end
+    end
+    `SARB_SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `SARB_DC:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_SCTxArb <= `SARB1_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SCTxArb <= `START_SARB;
+  else
+    CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketGnt <= 1'b0;
+    directCntlGnt <= 1'b0;
+    muxDCEn <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketGnt <= next_sendPacketGnt;
+    directCntlGnt <= next_directCntlGnt;
+    muxDCEn <= next_muxDCEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.v	(revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveGetPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
+input   clk;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  ACKRxed;
+output  bitStuffError;
+output  CRCError;
+output  dataSequence;
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXOverflow;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  RXTimeOut;
+
+reg     ACKRxed, next_ACKRxed;
+reg     bitStuffError, next_bitStuffError;
+wire    clk;
+reg     CRCError, next_CRCError;
+reg     dataSequence, next_dataSequence;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXOverflow, next_RXOverflow;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+wire    [7:0]RXStreamStatusIn;
+reg     RXTimeOut, next_RXTimeOut;
+wire    SIERxTimeOut;
+
+// diagram signals declarations
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
+begin
+  NextState_slvGetPkt <= CurrState_slvGetPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  case (CurrState_slvGetPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (SIERxTimeOut == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_slvGetPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_slvGetPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (RXFifoFull == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvGetPkt <= `START_GP;
+  else
+    CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXOverflow <= 1'b0;
+    ACKRxed <= 1'b0;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RXTimeOut <= 1'b0;
+    RxPID <= 4'h0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    RXByteOld <= 8'h00;
+  end
+  else 
+  begin
+    RXOverflow <= next_RXOverflow;
+    ACKRxed <= next_ACKRxed;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RXTimeOut <= next_RXTimeOut;
+    RxPID <= next_RxPID;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    RXByteOld <= next_RXByteOld;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.asf	(revision 264)
@@ -0,0 +1,358 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=790
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
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+A 599 601 16 TEXT "Actions" | 124386,212388 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 600 589 8192 596 587 BEZIER "Transitions" | 168405,170293 203966,131503 199503,89144 196184,45432
+W 601 589 8193 605 596 BEZIER "Transitions" | 97839,216722 109714,216534 162558,220059 167812,183210
+A 603 596 4 TEXT "Actions" | 174409,172080 1 0 0 "sendPacketWEn <= 1'b0;"
+L 604 605 0 TEXT "State Labels" | 91340,216824 1 0 0 "CHK_RDY\n/10/"
+S 605 589 53248 ELLIPSE "States" | 91340,216824 6500 6500
+W 606 589 0 588 605 BEZIER "Transitions" | 89368,237478 89903,233730 89797,226993 90332,223245
+C 607 601 0 TEXT "Conditions" | 114440,220845 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 612 589 8194 605 596 BEZIER "Transitions" | 91984,210359 90899,202871 142592,172810 163035,179986
+W 613 589 8195 605 617 BEZIER "Transitions" | 86536,212447 76974,203420 61686,186612 53042,177585
+C 614 612 0 TEXT "Conditions" | 69153,194735 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 615 612 16 TEXT "Actions" | 110702,185120 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 619 618 0 Builtin Entry | 96520,152400
+I 620 618 0 Builtin Exit | 144780,101600
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+L 628 629 0 TEXT "State Labels" | 67392,65502 1 0 0 "DATA\n/11/"
+S 629 589 61440 ELLIPSE "States" | 67392,65502 6500 6500
+W 630 589 8193 617 629 BEZIER "Transitions" | 48383,172368 44995,170520 39116,166056 37345,163515\
+                                              35574,160974 35266,154506 35651,142263 36036,130020\
+                                              37884,87516 41041,76736 44198,65956 54978,65340\
+                                              57981,65109 60984,64878 60379,64505 60995,64351
+W 631 589 8194 617 629 BEZIER "Transitions" | 54075,173680 59927,171524 83885,163128 122946,146882\
+                                              162008,130636 145376,121704 139603,106244 133831,90784\
+                                              72380,75586 70378,71274
+C 636 630 0 TEXT "Conditions" | 29568,129096 1 0 0 "USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+A 637 630 16 TEXT "Actions" | 36344,101376 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 638 631 16 TEXT "Actions" | 118603,107061 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+L 639 640 0 TEXT "State Labels" | 125814,48840 1 0 0 "GET_RESP\n/12/"
+I 96 722 0 Builtin Reset | 76296,129336
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+S 376 6 94212 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 380 377 0 Builtin Entry | 48940,236580
+I 381 377 0 Builtin Exit | 206487,14249
+S 640 589 65536 ELLIPSE "States" | 125814,48840 6500 6500
+W 641 589 0 629 640 BEZIER "Transitions" | 73191,62566 81815,59948 110822,52759 119446,50141
+A 642 629 4 TEXT "Actions" | 76076,71808 1 0 0 "sendPacketWEn <= 1'b0;"
+C 643 641 0 TEXT "Conditions" | 73811,60869 1 0 0 "sendPacketRdy == 1'b1"
+A 644 641 16 TEXT "Actions" | 75293,54584 1 0 0 "getPacketREn <= 1'b1;"
+A 645 640 4 TEXT "Actions" | 108652,38924 1 0 0 "getPacketREn <= 1'b0;"
+W 646 589 0 640 587 BEZIER "Transitions" | 132288,49411 139757,47794 182271,47049 189740,45432
+C 647 646 0 TEXT "Conditions" | 140247,52755 1 0 0 "getPacketRdy == 1'b1"
+I 649 559 0 Builtin Entry | 37971,243103
+I 650 559 0 Builtin Exit | 194044,45058
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+C 652 651 0 TEXT "Conditions" | 124856,135409 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+S 654 559 69632 ELLIPSE "States" | 92422,152802 6500 6500
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/13/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+I 399 377 0 Builtin Link | 54419,17564
+S 656 559 73728 ELLIPSE "States" | 109789,85208 5889 6500
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/14/"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+                                              46511,172964 33727,90292 34975,71611 36223,52930\
+                                              35724,34993 37785,28932 39847,22872 46307,16188\
+                                              54419,15564
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+                                              60053,165183 57484,160822 55722,148570 53960,136319\
+                                              36935,95064 38880,77714 40826,60365 38327,20823\
+                                              54419,15564
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+                                           108160,233400 112640,227800 113920,224400 115200,221000\
+                                           116013,213096 116333,209096
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 422 421 0 Builtin Entry | 96520,152400
+I 423 421 0 Builtin Exit | 144780,101600
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+                                              69948,104476 47394,95074 43302,84878 39210,74682\
+                                              42917,24960 54419,15564
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/15/"
+S 690 559 77824 ELLIPSE "States" | 98991,238090 6500 6500
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+W 692 559 8193 698 654 BEZIER "Transitions" | 115978,206479 112866,179807 96893,185826 93781,159154
+C 693 692 0 TEXT "Conditions" | 108065,184348 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+                                              39220,148925 36609,140943 36571,133460 36533,125977\
+                                              38989,104026 47738,97617 56488,91209 87662,87731\
+                                              103933,85889
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 696 559 8194 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+                                              200304,203038 205920,186346 207441,167119 208962,147892\
+                                              209430,87676 208962,71608 208494,55540 206154,51484\
+                                              204438,50041 202722,48598 199528,45916 197266,45058
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+S 698 559 81940 ELLIPSE "Junction" | 117000,209824 3500 3500
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 700 699 0 Builtin Entry | 96520,152400
+I 701 699 0 Builtin Exit | 144780,101600
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+S 462 377 102400 ELLIPSE "States" | 94684,51331 6500 6500
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/18/"
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 723 722 90112 ELLIPSE "States" | 120650,127000 6500 6500
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/16/"
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;"
+I 726 722 0 Builtin Entry | 96520,152400
+I 727 722 0 Builtin Exit | 144780,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+C 468 457 0 TEXT "Conditions" | 76387,38022 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS  &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[3:0]"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+                                              46860,73975 46530,57145 47396,48771 48262,40398\
+                                              52522,23896 54419,15564
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+                                           209214,43082 209522,23062 208983,17094 208444,11127\
+                                           205980,7277 191773,6353 177567,5429 123205,5583\
+                                           106804,9317 90403,13052 79161,27836 75696,31763\
+                                           72231,35690 70888,36159 69579,36621
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+                                              53866,34676 56339,23332 57169,17564
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+                                            60717,97705 62441,84600 62616,78575
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+                                            105236,81091 81842,75191 69908,73378
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/17/"
+S 786 377 98304 ELLIPSE "States" | 123152,53144 6500 6500
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+K 788 786 0 TEXT "Comments" | 118800,50912 1 0 0 "Insert delay to allow USBEndPControlReg to update"
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+C 535 532 0 TEXT "Conditions" | 73577,60437 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1"
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlaveWrap.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlaveWrap.v	(revision 264)
@@ -0,0 +1,191 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlaveWrap.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. Enable connection to Altera Avalon bus
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module usbHostSlaveWrap(
+  clk, 
+  reset,
+  address, 
+  writedata, 
+  readdata, 
+  write, 
+  read,
+  waitrequest,
+  chipselect,
+  irq,
+  USBWireVPI,
+  USBWireVMI,
+  USBWireDataInTick,
+  USBWireVPO,
+  USBWireVMO,
+  USBWireDataOutTick,
+  USBWireOutEn_n,
+  USBFullSpeed
+   );
+
+input clk;
+input reset;
+input [7:0] address; 
+input [7:0] writedata; 
+output [7:0] readdata; 
+input write; 
+input read;
+output waitrequest;
+input chipselect;
+output irq;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+
+wire clk;
+wire reset;
+wire [7:0] address; 
+wire [7:0] writedata; 
+wire [7:0] readdata; 
+wire write; 
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+
+//internal wiring 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+             hostResumeIntOut | hostTransDoneIntOut |
+             slaveSOFRxedIntOut | slaveResetEventIntOut |
+             slaveResumeIntOut | slaveTransDoneIntOut |
+             slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut; 
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+//Parameters declaration: 
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+  .clk(clk),
+  .rst(reset),
+  .address_i(address),
+  .data_i(writedata),
+  .data_o(readdata),
+  .writeEn(write),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/doc/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/doc/README.txt	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/doc/README.txt	(revision 264)
@@ -0,0 +1,24 @@
+USBHostSlave has been successfully compiled using Quartus 4.1 with Servive Pack 2
+USBHostSlave has been tested in a SystemC simulation, and on a Altera Nios development kit Cyclone edition.
+
+For those who wish to use a pre-configured Quartus project, I have included two files;
+usbhostslaveQuartusProj.qar   - Quartus project archive
+usbHostSlaveNiosIDEProj.zip   - NIOS IDE project zip file. You can use NIOS IDE File>>import to open the file
+
+
+If you wish to replicate the hardware setup, then you will need to replace
+the standard 50MHz oscillator with a 48MHz oscillator (Digikey XC280-ND),
+and you will need a add a Santa Cruz daughter card with two USB transceivers.
+
+If there is enough interest, I will consider producing a Santa Cruz daughter card
+with the hardware required to support this core. 
+Please email me at sfielding@base2designs.com if you are interested in this option.
+
+
+Release notes:
+Version 6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+            control reads and writes to USB flash dongle 
+
+ 
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/doc/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifo.v	(revision 264)
@@ -0,0 +1,123 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo read access via bus interface, fifo write access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module RxFifo(
+  clk, 
+  rst, 
+  fifoWEn, 
+  fifoFull,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataIn  );
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk; 
+wire rst; 
+wire fifoWEn; 
+wire fifoFull;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(fifoDataIn), 
+  .dataOut(dataFromFifoToBus), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+RxfifoBI u_RxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .fifoDataIn(dataFromFifoToBus),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoREn(fifoREn),
+  .fifoEmpty(fifoEmpty),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoMem.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMem.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores/usbhostslave/>               ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMem(  addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+  // Generic synchronous dual-port RAM interface
+  .rclk(clk), 
+  .rrst(1'b0), 
+  .rce(1'b1), 
+  .oe(readEn), 
+  .raddr(addrOut), 
+  .do(dataOut),
+  .wclk(clk), 
+  .wrst(1'b0), 
+  .wce(1'b1),
+  .we(writeEn), 
+  .waddr(addrIn), 
+  .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_simFifoMem (
+  .addrIn(addrIn),
+  .addrOut(addrOut),
+  .clk(clk),
+  .dataIn(dataIn),
+  .writeEn(writeEn),
+  .readEn(readEn),
+  .dataOut(dataOut));  
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/USBHostControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/USBHostControlBI.v	(revision 264)
@@ -0,0 +1,290 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBHostControlBI.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbHostControl_h.v"
+ 
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+  SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+  TxTransTypeReg, TxSOFEnableReg,
+  TxAddrReg, TxEndPReg, frameNumIn, 
+  RxPktStatusIn, RxPIDIn,
+  connectStateIn,
+  SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+  hostControlSelect,
+  clrTransReq,
+  preambleEn,
+  SOFSync,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  transReq,
+  isoEn
+  );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output transReq;
+output isoEn;     //enable isochronous mode
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg transReq;
+reg isoEn;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//sync write demux
+always @(posedge clk)
+begin
+  if (rst == 1'b1) begin
+    isoEn <= 1'b0;
+    preambleEn <= 1'b0;
+    SOFSync <= 1'b0;
+    TxTransTypeReg <= 2'b00;
+    TxLineControlReg <= 5'h00;
+    TxSOFEnableReg <= 1'b0;
+    TxAddrReg <= 7'h00;
+    TxEndPReg <= 4'h0;
+    interruptMaskReg <= 4'h0;
+  end
+  else begin
+    clrSOFReq <= 1'b0;
+    clrConnEvtReq <= 1'b0;
+    clrResInReq <= 1'b0;
+    clrTransDoneReq <= 1'b0;
+    setTransReq <= 1'b0;
+    if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+    begin
+      case (address)
+        `TX_CONTROL_REG : begin
+          isoEn <= dataIn[`ISO_ENABLE_BIT];
+          preambleEn <= dataIn[`PREAMBLE_ENABLE_BIT];
+          SOFSync <= dataIn[`SOF_SYNC_BIT];
+          setTransReq <= dataIn[`TRANS_REQ_BIT];
+        end
+        `TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
+        `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+        `TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[`SOF_EN_BIT];
+        `TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
+        `TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
+        `INTERRUPT_STATUS_REG :  begin
+          clrSOFReq <= dataIn[`SOF_SENT_BIT];
+          clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
+          clrResInReq <= dataIn[`RESUME_INT_BIT];
+          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+        end
+        `INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[3:0];
+      endcase
+    end 
+  end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+  if (rst == 1'b1) begin
+    SOFSentInt <= 1'b0;
+    connEventInt <= 1'b0;
+    resumeInt <= 1'b0;
+    transDoneInt <= 1'b0;
+  end
+  else begin
+    if (SOFSentIn == 1'b1)
+      SOFSentInt <= 1'b1;
+    else if (clrSOFReq == 1'b1)
+      SOFSentInt <= 1'b0;
+    
+    if (connEventIn == 1'b1)
+      connEventInt <= 1'b1;
+    else if (clrConnEvtReq == 1'b1)
+      connEventInt <= 1'b0;
+    
+    if (resumeIntIn == 1'b1)
+      resumeInt <= 1'b1;
+    else if (clrResInReq == 1'b1)
+      resumeInt <= 1'b0;  
+
+    if (transDoneIn == 1'b1)
+      transDoneInt <= 1'b1;
+    else if (clrTransDoneReq == 1'b1)
+      transDoneInt <= 1'b0;
+  end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end  
+  
+//transaction request set/clear
+always @(posedge clk)
+begin
+  if (rst == 1'b1) begin
+    transReq <= 1'b0;
+  end
+  else begin
+    if (setTransReq == 1'b1)
+      transReq <= 1'b1;
+    else if (clrTransReq == 1'b1)
+      transReq <= 1'b0;
+  end
+end  
+  
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+  TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+  fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+  
+// async read mux
+always @(address or
+  TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+  TxAddrReg or TxEndPReg or frameNumIn or 
+  SOFSentInt or connEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+  preambleEn or SOFSync or transReq or isoEn)
+begin
+  case (address)
+      `TX_CONTROL_REG : dataOut <= {4'b0000, isoEn, preambleEn, SOFSync, transReq} ;
+      `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
+      `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+      `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
+      `TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
+      `TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
+      `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumIn[10:8]};
+      `FRAME_NUM_LSB_REG : dataOut <= frameNumIn[7:0];
+      `INTERRUPT_STATUS_REG :  dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+      `INTERRUPT_MASK_REG  : dataOut <= {4'h0, interruptMaskReg};
+      `RX_STATUS_REG  : dataOut <= RxPktStatusIn;
+      `RX_PID_REG  : dataOut <= {4'b0000, RxPIDIn};
+      `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.v	(revision 264)
@@ -0,0 +1,397 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// getpacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
+input   clk;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  [7:0]RXPktStatus;
+
+wire    clk;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+reg     [7:0]RXPktStatus;
+wire    [7:0]RXStreamStatusIn;
+wire    SIERxTimeOut;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
+begin
+  NextState_getPkt <= CurrState_getPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  case (CurrState_getPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      if (SIERxTimeOut == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_getPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_getPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_getPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+        next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_getPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (RXFifoFull == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_getPkt <= `START_GP;
+  else
+    CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RxPID <= 4'h0;
+    RXOverflow <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXByteOld <= 8'h00;
+    RXTimeOut <= 1'b0;
+  end
+  else 
+  begin
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RxPID <= next_RxPID;
+    RXOverflow <= next_RXOverflow;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXByteOld <= next_RXByteOld;
+    RXTimeOut <= next_RXTimeOut;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.v	(revision 264)
@@ -0,0 +1,436 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, isoEn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input   clk;
+input   getPacketRdy;
+input   isoEn;
+input   rst;
+input   [7:0]RXStatus;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   transReq;
+input   [1:0]transType;
+output  clearTXReq;
+output  getPacketREn;
+output  sendPacketArbiterReq;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  transDone;
+
+reg     clearTXReq, next_clearTXReq;
+wire    clk;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+wire    isoEn;
+wire    rst;
+wire    [7:0]RXStatus;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     transDone, next_transDone;
+wire    transReq;
+wire    [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 6'b000000
+`define TX_REQ 6'b000001
+`define CHK_TYPE 6'b000010
+`define FLAG 6'b000011
+`define IN_WAIT_DATA_RXED 6'b000100
+`define IN_CHK_FOR_ERROR 6'b000101
+`define IN_CLR_SP_WEN2 6'b000110
+`define SETUP_CLR_SP_WEN1 6'b000111
+`define SETUP_CLR_SP_WEN2 6'b001000
+`define FIN 6'b001001
+`define WAIT_GNT 6'b001010
+`define SETUP_WAIT_PKT_RXED 6'b001011
+`define IN_WAIT_IN_SENT 6'b001100
+`define OUT0_WAIT_RX_DATA 6'b001101
+`define OUT0_WAIT_DATA0_SENT 6'b001110
+`define OUT0_WAIT_OUT_SENT 6'b001111
+`define SETUP_HC_WAIT_RDY 6'b010000
+`define IN_WAIT_SP_RDY1 6'b010001
+`define IN_WAIT_SP_RDY2 6'b010010
+`define OUT0_WAIT_SP_RDY1 6'b010011
+`define SETUP_WAIT_SETUP_SENT 6'b010100
+`define SETUP_WAIT_DATA_SENT 6'b010101
+`define IN_CLR_SP_WEN1 6'b010110
+`define IN_WAIT_ACK_SENT 6'b010111
+`define OUT0_CLR_WEN1 6'b011000
+`define OUT0_CLR_WEN2 6'b011001
+`define OUT1_WAIT_RX_DATA 6'b011010
+`define OUT1_WAIT_OUT_SENT 6'b011011
+`define OUT1_WAIT_DATA1_SENT 6'b011100
+`define OUT1_WAIT_SP_RDY1 6'b011101
+`define OUT1_CLR_WEN1 6'b011110
+`define OUT1_CLR_WEN2 6'b011111
+`define OUT0_CHK_ISO 6'b100000
+
+reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or isoEn or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+  NextState_hstCntrl <= CurrState_hstCntrl;
+  // Set default values for outputs and signals
+  next_transDone <= transDone;
+  next_clearTXReq <= clearTXReq;
+  next_getPacketREn <= getPacketREn;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketPID <= sendPacketPID;
+  next_sendPacketWEn <= sendPacketWEn;
+  case (CurrState_hstCntrl)  // synopsys parallel_case full_case
+    `START_HC:
+    begin
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `TX_REQ:
+    begin
+      if (transReq == 1'b1)
+      begin
+        NextState_hstCntrl <= `WAIT_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `CHK_TYPE:
+    begin
+      if (transType == `OUTDATA0_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+      end
+      else if (transType == `IN_TRANS)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+      end
+      else if (transType == `SETUP_TRANS)
+      begin
+        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+      end
+      else if (transType == `OUTDATA1_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+      end
+    end
+    `FLAG:
+    begin
+      next_transDone <= 1'b1;
+      next_clearTXReq <= 1'b1;
+      next_sendPacketArbiterReq <= 1'b0;
+      NextState_hstCntrl <= `FIN;
+    end
+    `FIN:
+    begin
+      next_transDone <= 1'b0;
+      next_clearTXReq <= 1'b0;
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `WAIT_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1)
+      begin
+        NextState_hstCntrl <= `CHK_TYPE;
+      end
+    end
+    `SETUP_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+    end
+    `SETUP_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+    end
+    `SETUP_WAIT_PKT_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `SETUP_HC_WAIT_RDY:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `SETUP;
+      end
+    end
+    `SETUP_WAIT_SETUP_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `SETUP_WAIT_DATA_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_DATA_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+      end
+    end
+    `IN_CHK_FOR_ERROR:
+    begin
+      if (isoEn == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+      else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+      end
+      else
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `IN_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+    end
+    `IN_WAIT_IN_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `IN;
+      end
+    end
+    `IN_WAIT_SP_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `IN_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+    end
+    `IN_WAIT_ACK_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_DATA0_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CHK_ISO;
+      end
+    end
+    `OUT0_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `OUT0_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT0_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+    end
+    `OUT0_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+    end
+    `OUT0_CHK_ISO:
+    begin
+      if (isoEn == 1'b0)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+      else
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT1_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT1_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `OUT1_WAIT_DATA1_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `OUT1_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT1_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+    end
+    `OUT1_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_hstCntrl <= `START_HC;
+  else
+    CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    transDone <= 1'b0;
+    clearTXReq <= 1'b0;
+    getPacketREn <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketPID <= 4'b0;
+    sendPacketWEn <= 1'b0;
+  end
+  else 
+  begin
+    transDone <= next_transDone;
+    clearTXReq <= next_clearTXReq;
+    getPacketREn <= next_getPacketREn;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketPID <= next_sendPacketPID;
+    sendPacketWEn <= next_sendPacketWEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketarbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
+INSTHEADER 1
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
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+I 53 0 130 Builtin InPort | 38410,162874 "" ""
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+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)  \nbegin\n  if (muxSOFNotHC  == 1'b1)  \n  begin\n    sendPacketWEnable <= SOF_SP_WEn;\n    sendPacketPID <= `SOF;\n  end\n  else\n  begin\n    sendPacketWEnable <= HC_SP_WEn;\n    sendPacketPID <= HC_PID;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
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+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.asf	(revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SCTxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SARB_SEND_PACKET\n/1/"
+S 14 6 4096 ELLIPSE "States" | 269063,296392 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 10 6 0 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_SARB\n/3/"
+S 8 6 12288 ELLIPSE "States" | 225591,395370 6500 6500
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "SCTxArb"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,543100 1 0 0 "Module: SCTxPortArbiter"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+                                      288786,359372 287077,371461 282417,376909 277757,382357\
+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+C 26 17 0 TEXT "Conditions" | 202073,391408 1 0 0 "rst"
+A 25 8 2 TEXT "Actions" | 234434,411387 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+W 19 6 4097 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210185,391478 219470,393186
+I 16 6 0 Builtin Reset | 178237,395710
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 43 42 0 TEXT "Labels" | 172566,462781 1 0 0 "SCTxPortRdyIn"
+I 42 0 2 Builtin InPort | 166566,462781 "" ""
+I 41 0 3 Builtin InPort | 190061,536582 "" ""
+L 40 39 0 TEXT "Labels" | 195447,542126 1 0 0 "rst"
+I 39 0 2 Builtin InPort | 189447,542126 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "SCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 61 41 0 TEXT "Labels" | 196061,536582 1 0 0 "clk"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "SCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n  SCTxPortRdyOut = SCTxPortRdyIn;\nend\n	  \nalways @(muxDCEn or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n  begin  \n    SCTxPortWEnable <= directCntlWEn;\n    SCTxPortData <= directCntlData;\n    SCTxPortCntl <= directCntlCntl;\n  end\nelse\n  begin  \n    SCTxPortWEnable <= sendPacketWEn;\n    SCTxPortData <= sendPacketData;\n    SCTxPortCntl <= sendPacketCntl;\n  end\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "SCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+L 65 64 0 TEXT "Labels" | 170048,467134 1 0 0 "SCTxPortRdyOut"
+I 64 0 2 Builtin OutPort | 164048,467134 "" ""
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+W 92 6 4098 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+S 91 6 8192 ELLIPSE "States" | 230314,289948 6500 6500
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "SARB_DC\n/2/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxDCEn"
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286142,395412 275462,395110\
+                                      264783,394808 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.asf	(revision 264)
@@ -0,0 +1,277 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=284
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveGetPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 33
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 58
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 112
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 245
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 251
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: slaveGetPacket"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "slvGetPkt"
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+L 277 278 0 TEXT "State Labels" | 44712,168924 1 0 0 "DELAY\n/17/"
+S 278 120 90112 ELLIPSE "States" | 44712,168924 6500 6500
+W 279 120 0 278 137 BEZIER "Transitions" | 45244,175402 46602,184714 48694,202964 53786,209657\
+                                           58879,216350 75631,224113 84458,228187
+W 281 6 0 11 40 BEZIER "Transitions" | 103032,141659 103834,114294 105382,61467 106184,34102
+C 282 281 0 TEXT "Conditions" | 78641,126629 1 0 0 "SIERxTimeOut == 1'b1"
+A 283 281 16 TEXT "Actions" | 79925,116036 1 0 0 "RXTimeOut <= 1'b1;"
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+                                         190292,107515 191648,100057 191987,92429 192326,84802\
+                                         192326,61750 188540,53162 184755,44574 169613,33274\
+                                         159556,30336 149499,27398 125714,27614 113171,27388
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+L 32 33 0 TEXT "State Labels" | 141266,72558 1 0 0 "PROC_PKT"
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141266,72558 6500 6500
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141572,86202 141370,79031
+C 35 34 0 TEXT "Conditions" | 122487,97401 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 59 46 0 49 54 BEZIER "Transitions" | 52122,248640 63735,242665 85368,230107 96981,224132
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+I 49 46 0 Builtin Entry | 47660,248640
+I 50 46 0 Builtin Exit | 180308,72140
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+I 76 72 0 Builtin Exit | 187140,27160
+I 75 72 0 Builtin Entry | 33260,254940
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177624,25344 184036,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176807,72082 177204,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.v	(revision 264)
@@ -0,0 +1,265 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveSendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   [3:0]PID;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   sendPacketWEn;
+output  fifoReadEn;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+wire    [3:0]PID;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: slvSndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
+begin
+  NextState_slvSndPkt <= CurrState_slvSndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvSndPkt)  // synopsys parallel_case full_case
+    `START_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+    end
+    `SP_WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP1_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `SP1_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_SCTxPortReq <= 1'b0;
+    end
+    `SP_NOT_DATA:
+    begin
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_SEND_PID_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= PIDNotPID;
+        next_SCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SP_SEND_PID_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_NOT_DATA;
+      end
+    end
+    `SP_D0_D1_READ_FIFO:
+    begin
+      next_SCTxPortWEn <= 1'b1;
+      next_SCTxPortData <= fifoData;
+      next_SCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+    end
+    `SP_D0_D1_WAIT_READ_FIFO:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `SP_D0_D1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+      end
+    end
+    `SP_D0_D1_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_D0_D1_TERM_BYTE:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `SP_D0_D1_CLR_WEN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+    end
+    `SP_D0_D1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvSndPkt <= `START_SP1;
+  else
+    CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    SCTxPortData <= 8'h00;
+    SCTxPortCntl <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlave.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlave.v	(revision 264)
@@ -0,0 +1,516 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlave.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostSlave(
+  clk, 
+  rst,
+  address_i, 
+  data_i, 
+  data_o, 
+  writeEn, 
+  strobe_i,
+  ack_o,
+  hostSOFSentIntOut, 
+  hostConnEventIntOut, 
+  hostResumeIntOut, 
+  hostTransDoneIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+  USBWireDataIn,
+  USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+  USBWireCtrlOut,
+  USBFullSpeed
+   );
+  parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+  parameter HOST_FIFO_ADDR_WIDTH = 6;   
+  parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+  parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+  parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+  parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk;
+input rst;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input writeEn; 
+input strobe_i;
+output ack_o;
+output hostSOFSentIntOut; 
+output hostConnEventIntOut; 
+output hostResumeIntOut; 
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+
+wire clk;
+wire rst;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire writeEn; 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel; 
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE; 
+wire [7:0] hostTxFifoData; 
+wire hostTxFifoEmpty;
+wire hostRxFifoWE; 
+wire [7:0] hostRxFifoData; 
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost; 
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+
+assign USBFullSpeed = fullSpeedBitRateToSIE;  
+
+usbHostControl u_usbHostControl(
+  .clk(clk), 
+  .rst(rst),
+  .TxFifoRE(hostTxFifoRE), 
+  .TxFifoData(hostTxFifoData), 
+  .TxFifoEmpty(hostTxFifoEmpty),
+  .RxFifoWE(hostRxFifoWE), 
+  .RxFifoData(hostRxFifoData), 
+  .RxFifoFull(hostRxFifoFull),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut),
+  .fullSpeedRate(fullSpeedBitRateFromHost), 
+  .fullSpeedPol(fullSpeedPolarityFromHost),
+  .HCTxPortEn(SIEPortWEnFromHost), 
+  .HCTxPortRdy(SIEPortTxRdy),
+  .HCTxPortData(SIEPortDataInFromHost), 
+  .HCTxPortCtrl(SIEPortCtrlInFromHost),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[3:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+  .SOFSentIntOut(hostSOFSentIntOut), 
+  .connEventIntOut(hostConnEventIntOut), 
+  .resumeIntOut(hostResumeIntOut), 
+  .transDoneIntOut(hostTransDoneIntOut),
+  .hostControlSelect(hostControlSel) );
+  
+
+usbSlaveControl u_usbSlaveControl(
+  .clk(clk), 
+  .rst(rst),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut), 
+  .RxFifoData(slaveRxFifoData),
+  .fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+  .SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+  .SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+  .SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk), 
+  .rst(rst),
+  .hostControlSel(hostControlSel), 
+  .hostRxFifoSel(hostRxFifoSel), 
+  .hostTxFifoSel(hostTxFifoSel),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(dataFromHostControl),
+  .dataFromHostRxFifo(dataFromHostRxFifo),
+  .dataFromHostTxFifo(dataFromHostTxFifo),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+   );
+
+hostSlaveMux u_hostSlaveMux(
+  .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+  .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+  .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+  .SIEPortDataInToSIE(SIEPortDataInToSIE), 
+  .SIEPortDataInFromHost(SIEPortDataInFromHost), 
+  .SIEPortDataInFromSlave(SIEPortDataInFromSlave), 
+  .SIEPortWEnToSIE(SIEPortWEnToSIE), 
+  .SIEPortWEnFromHost(SIEPortWEnFromHost), 
+  .SIEPortWEnFromSlave(SIEPortWEnFromSlave), 
+  .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+  .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+  .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+  .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+  .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+  .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux),
+  .address(address_i[0]),
+  .writeEn(writeEn),
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(clk), 
+  .rst(rst),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .connectState(connectState),
+  .resumeDetected(resumeDetected),
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataFromSIE), 
+  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+  .SIEPortDataIn(SIEPortDataInToSIE), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEnToSIE), 
+  .fullSpeedPolarity(fullSpeedPolarityToSIE),
+  .fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(hostTxFifoRE), 
+  .fifoEmpty(hostTxFifoEmpty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostTxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostTxFifo),
+  .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(hostRxFifoWE), 
+  .fifoFull(hostRxFifoFull),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostRxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostRxFifo),
+  .fifoDataIn(hostRxFifoData)  );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+  TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+  TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm	(revision 264)
@@ -0,0 +1,276 @@
+<html>
+<head>
+<title>USBHostControlBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBHostControlBI.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+ 
+<span id=t_kwd>module</span> <span id=t_idt>USBHostControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>SOFSentIntOut</span>, <span id=t_idt>connEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>TxTransTypeReg</span>, <span id=t_idt>TxSOFEnableReg</span>,
+  <span id=t_idt>TxAddrReg</span>, <span id=t_idt>TxEndPReg</span>, <span id=t_idt>frameNumIn</span>, 
+  <span id=t_idt>RxPktStatusIn</span>, <span id=t_idt>RxPIDIn</span>,
+  <span id=t_idt>connectStateIn</span>,
+  <span id=t_idt>SOFSentIn</span>, <span id=t_idt>connEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>,
+  <span id=t_idt>hostControlSelect</span>,
+  <span id=t_idt>clrTransReq</span>,
+  <span id=t_idt>preambleEn</span>,
+  <span id=t_idt>SOFSync</span>,
+  <span id=t_idt>TxLineState</span>,
+  <span id=t_idt>LineDirectControlEn</span>,
+  <span id=t_idt>fullSpeedPol</span>, 
+  <span id=t_idt>fullSpeedRate</span>,
+  <span id=t_idt>transReq</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>output</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transReq</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transReq</span>;
+
+<span id=t_com>//internal wire and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineControlReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrConnEvtReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>setTransReq</span>;
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResInReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>setTransReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>hostControlSelect</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>preambleEn</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>SOFSync</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>setTransReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>TxTransTypeReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>TxLineControlReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>TxSOFEnableReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>TxAddrReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>TxEndPReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_kwd>begin</span>
+        <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>clrResInReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>interruptMaskReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+   <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//interrupt control</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>SOFSentIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>connEventIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrConnEvtReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b0</span>;  
+
+  <span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//mask interrupts</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSentInt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>transDoneIntOut</span> &lt;= <span id=t_idt>transDoneInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>];
+  <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_idt>resumeInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>];
+  <span id=t_idt>connEventIntOut</span> &lt;= <span id=t_idt>connEventInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>CONNECTION_EVENT_BIT</span>];
+  <span id=t_idt>SOFSentIntOut</span> &lt;= <span id=t_idt>SOFSentInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_SENT_BIT</span>];
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//transaction request set/clear</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>setTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//break out control signals</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>TxLineState</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>TX_LINE_STATE_LSBIT</span>];
+  <span id=t_idt>LineDirectControlEn</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>DIRECT_CONTROL_BIT</span>];
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span>]; 
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span>];
+<span id=t_kwd>end</span>
+  
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxSOFEnableReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndPReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNumIn</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SOFSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span>
+  <span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>RxPktStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxPIDIn</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>preambleEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSync</span> <span id=t_kwd>or</span> <span id=t_idt>transReq</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>preambleEn</span>, <span id=t_idt>SOFSync</span>, <span id=t_idt>transReq</span>} ;
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>TxTransTypeReg</span>};
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>TxLineControlReg</span>};
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>TxSOFEnableReg</span>};
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxAddrReg</span>};
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>TxEndPReg</span>};
+     `<span id=t_idt>FRAME_NUM_MSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>frameNumIn</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>];
+     `<span id=t_idt>FRAME_NUM_LSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNumIn</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]};
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>SOFSentInt</span>, <span id=t_idt>connEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>};
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>interruptMaskReg</span>};
+     `<span id=t_idt>RX_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>RxPktStatusIn</span>;
+     `<span id=t_idt>RX_PID_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'b0000</span>, <span id=t_idt>RxPIDIn</span>};
+     `<span id=t_idt>RX_CONNECT_STATE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>};
+      <span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifo.v	(revision 264)
@@ -0,0 +1,121 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo write access via bus interface, fifo read access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module TxFifo(
+  clk, 
+  rst, 
+  fifoREn, 
+  fifoEmpty,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataOut ); 
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoREn; 
+output fifoEmpty;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire clk; 
+wire rst; 
+wire fifoREn; 
+wire fifoEmpty;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(busDataIn), 
+  .dataOut(fifoDataOut), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+TxfifoBI u_TxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoWEn(fifoWEn),
+  .fifoFull(fifoFull),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/simFifoMem.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/simFifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/simFifoMem.v	(revision 264)
@@ -0,0 +1,82 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// simFifoMem.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module simFifoMem(  addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge clk) begin
+  dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge clk) begin
+  if (writeEn == 1'b1)
+    buffer[addrIn] <= dataIn;
+end                  
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/simFifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.v	(revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// directControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+  NextState_drctCntl <= CurrState_drctCntl;
+  // Set default values for outputs and signals
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_drctCntl)  // synopsys parallel_case full_case
+    `START_DC:
+    begin
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_drctCntl <= `CHK_DRCT_CNTL;
+        next_HCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {6'b000000, directControlLineState};
+        next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_HCTxPortReq <= 1'b0;
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_drctCntl <= `START_DC;
+  else
+    CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.v	(revision 264)
@@ -0,0 +1,242 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hctxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+input   [7:0]SOFCntlCntl;
+input   [7:0]SOFCntlData;
+input   SOFCntlReq;
+input   SOFCntlWEn;
+output  directCntlGnt;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortWEnable;
+output  sendPacketGnt;
+output  SOFCntlGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+reg     HCTxPortWEnable, next_HCTxPortWEnable;
+wire    rst;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+wire    [7:0]SOFCntlCntl;
+wire    [7:0]SOFCntlData;
+reg     SOFCntlGnt, next_SOFCntlGnt;
+wire    SOFCntlReq;
+wire    SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg  [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+  NextState_HCTxArb = CurrState_HCTxArb;
+  // Set default values for outputs and signals
+  next_SOFCntlGnt <= SOFCntlGnt;
+  next_sendPacketGnt <= sendPacketGnt;
+  next_directCntlGnt <= directCntlGnt;
+  next_muxCntl <= muxCntl;
+  case (CurrState_HCTxArb)  // synopsys parallel_case full_case
+    `START_HARB:
+    begin
+      NextState_HCTxArb = `WAIT_REQ;
+    end
+    `WAIT_REQ:
+    begin
+      if (SOFCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb = `SEND_SOF;
+        next_SOFCntlGnt <= 1'b1;
+        next_muxCntl <= `SOF_CTRL_MUX;
+      end
+      else if (sendPacketReq == 1'b1)
+      begin
+        NextState_HCTxArb = `SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxCntl <= `SEND_PACKET_MUX;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb = `DIRECT_CONTROL;
+        next_directCntlGnt <= 1'b1;
+        next_muxCntl <= `DIRECT_CTRL_MUX;
+      end
+    end
+    `SEND_SOF:
+    begin
+      if (SOFCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_SOFCntlGnt <= 1'b0;
+      end
+    end
+    `SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `DIRECT_CONTROL:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_HCTxArb = `START_HARB;
+  else
+    CurrState_HCTxArb = NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFCntlGnt = 1'b0;
+    sendPacketGnt = 1'b0;
+    directCntlGnt = 1'b0;
+    muxCntl = 2'b00;
+  end
+  else 
+  begin
+    SOFCntlGnt = next_SOFCntlGnt;
+    sendPacketGnt = next_sendPacketGnt;
+    directCntlGnt = next_directCntlGnt;
+    muxCntl = next_muxCntl;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.asf	(revision 264)
@@ -0,0 +1,285 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=260
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
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+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
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+PAGE 25400,25400 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/"
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+I 12 6 0 Builtin Reset | 74872,202290
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: sendPacket"
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "sndPkt"
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP\n/0/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "WAIT_ENABLE\n/1/"
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+W 30 25 0 28 26 BEZIER "Transitions" | 52150,256695 56357,246454 59660,235429 67946,223821
+I 29 25 0 Builtin Exit | 144780,121920
+I 28 25 0 Builtin Entry | 48013,256695
+L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/"
+S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+C 23 22 0 TEXT "Conditions" | 129137,121283 1 0 0 "HCTxPortGnt == 1'b1"
+W 22 6 0 16 227 BEZIER "Transitions" | 115535,117920 120401,115274 154207,112243 162751,111806
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500
+L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+S 47 6 36864 ELLIPSE "States" | 115848,16910 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP\n/5/"
+S 45 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,46294 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,46294 1 0 0 "DATA0_DATA1"
+S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500
+L 42 43 0 TEXT "State Labels" | 116148,48718 1 0 0 "SEND_SOF"
+S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500
+L 40 41 0 TEXT "State Labels" | 61608,50536 1 0 0 "OUT_IN_SETUP"
+W 39 25 0 33 29 BEZIER "Transitions" | 78151,174526 94720,161687 125355,134759 141924,121920
+A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 37 34 16 TEXT "Actions" | 66378,203896 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= PIDNotPID;\nHCTxPortCntl <= `TX_PACKET_START;"
+C 36 34 0 TEXT "Conditions" | 74012,211530 1 0 0 "HCTxPortRdy == 1'b1"
+W 34 25 0 26 33 BEZIER "Transitions" | 71729,211913 72078,205195 72736,192521 73085,185803
+S 33 25 20480 ELLIPSE "States" | 73797,179351 6500 6500
+L 32 33 0 TEXT "State Labels" | 73797,179351 1 0 0 "FIN\n/4/"
+H 58 43 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,5152 212900,250284
+H 51 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 50 6 8193 21 45 BEZIER "Transitions" | 119411,90353 134284,80236 162142,60327 177015,50210
+W 49 6 8194 21 43 BEZIER "Transitions" | 114327,87507 114704,79202 115453,63508 115830,55203
+W 48 6 8195 21 41 BEZIER "Transitions" | 108751,90198 97879,81365 77125,63914 66253,55081
+C 79 48 0 TEXT "Conditions" | 70608,88862 1 0 0 "PID == `OUT || \nPID == `IN || \nPID == `SETUP"
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nHCTxPortReq <= 1'b0;"
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888
+W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311
+W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500
+L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
+S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
+I 84 51 0 Builtin Entry | 48374,241112
+I 83 51 0 Builtin Exit | 161275,73621
+W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
+C 81 50 0 TEXT "Conditions" | 135398,83918 1 0 0 "PID == `DATA0 || PID == `DATA1"
+C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
+S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
+L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
+W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
+A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+I 110 58 0 Builtin Exit | 176204,35771
+I 111 58 0 Builtin Entry | 69864,225148
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1;	 \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127618,200894 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+                                          48213,88528 42471,75064 41184,67490 39897,59917\
+                                          40491,43087 47668,36800 54846,30514 82962,22198\
+                                          91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+                                          200128,135446 205472,144130 205681,151728 205890,159327\
+                                          201380,181037 194241,189595 187102,198154 163054,210680\
+                                          152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
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+W 259 241 0 253 251 BEZIER "Transitions" | 90715,166299 107284,153460 137919,126532 154488,113693
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sofcontroller\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: SOFController"
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+A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n  SOFTimer <= 16'h0000;\nelse\n  SOFTimer <= SOFTimer + 1'b1;"
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+L 49 50 0 TEXT "State Labels" | 162077,151882 1 0 0 "SC_WAIT_GNT\n/4/"
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+W 64 6 0 62 24 BEZIER "Transitions" | 116496,88885 114624,81865 110713,68112 108841,61092
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/speedCtrlMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/speedCtrlMux.v	(revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// speedCtrlMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input   directCtrlRate;
+input   directCtrlPol;
+input   sendPacketRate;
+input   sendPacketPol;
+input   sendPacketSel;
+output  fullSpeedRate;
+output  fullSpeedPol;
+
+wire   directCtrlRate;
+wire   directCtrlPol;
+wire   sendPacketRate;
+wire   sendPacketPol;
+wire   sendPacketSel;
+reg   fullSpeedRate;
+reg   fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+  if (sendPacketSel == 1'b1) 
+  begin
+  fullSpeedRate <= sendPacketRate;
+  fullSpeedPol <= sendPacketPol;
+  end
+  else
+  begin
+  fullSpeedRate <= directCtrlRate;
+  fullSpeedPol <= directCtrlPol;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbConstants_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbConstants_h.v	(revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v                                             
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc 
+     
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined       
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifoBI.v	(revision 264)
@@ -0,0 +1,116 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+  address, writeEn, strobe_i,
+  clk, rst, fifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoWEn,
+  fifoFull,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoWEn;
+input fifoFull;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoWEn;
+wire fifoFull;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoFull or numElementsInFifo)
+begin
+  case (address)
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00;
+  endcase
+end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoWEn <= 1'b1;
+  else
+    fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/busInterface/wishBoneBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/busInterface/wishBoneBI.v	(revision 264)
@@ -0,0 +1,246 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBI.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "wishBoneBus_h.v"
+
+ 
+module wishBoneBI (
+  address, dataIn, dataOut, writeEn, 
+  strobe_i,
+  ack_o,
+  clk, rst,
+  hostControlSel, 
+  hostRxFifoSel, hostTxFifoSel,
+  slaveControlSel,
+  slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, 
+  slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, 
+  hostSlaveMuxSel,
+  dataFromHostControl,
+  dataFromHostRxFifo,
+  dataFromHostTxFifo,
+  dataFromSlaveControl,
+  dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+  dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+  dataFromHostSlaveMux
+   );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+  dataFromHostControl or
+  dataFromHostRxFifo or
+  dataFromHostTxFifo or
+  dataFromSlaveControl or
+  dataFromEP0RxFifo or 
+  dataFromEP1RxFifo or
+  dataFromEP2RxFifo or
+  dataFromEP3RxFifo or
+  dataFromHostSlaveMux or 
+  dataFromEP0TxFifo or
+  dataFromEP1TxFifo or
+  dataFromEP2TxFifo or
+  dataFromEP3TxFifo)
+begin
+  hostControlSel <= 1'b0;
+  hostRxFifoSel <= 1'b0;
+  hostTxFifoSel <= 1'b0;
+  slaveControlSel <= 1'b0;
+  slaveEP0RxFifoSel <= 1'b0;
+  slaveEP0TxFifoSel <= 1'b0;
+  slaveEP1RxFifoSel <= 1'b0;
+  slaveEP1TxFifoSel <= 1'b0;
+  slaveEP2RxFifoSel <= 1'b0;
+  slaveEP2TxFifoSel <= 1'b0;
+  slaveEP3RxFifoSel <= 1'b0;
+  slaveEP3TxFifoSel <= 1'b0;
+  hostSlaveMuxSel <= 1'b0;
+  case (address & `ADDRESS_DECODE_MASK)
+    `HCREG_BASE : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HCREG_BASE_PLUS_0X10 : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HOST_RX_FIFO_BASE : begin
+      hostRxFifoSel <= 1'b1;
+      dataOut <= dataFromHostRxFifo;
+    end
+    `HOST_TX_FIFO_BASE : begin
+      hostTxFifoSel <= 1'b1;
+      dataOut <= dataFromHostTxFifo;
+    end
+    `SCREG_BASE : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `SCREG_BASE_PLUS_0X10 : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `EP0_RX_FIFO_BASE : begin
+      slaveEP0RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0RxFifo;
+    end
+    `EP0_TX_FIFO_BASE : begin
+      slaveEP0TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0TxFifo;
+    end
+    `EP1_RX_FIFO_BASE : begin
+      slaveEP1RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1RxFifo;
+    end
+    `EP1_TX_FIFO_BASE : begin
+      slaveEP1TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1TxFifo;
+    end
+    `EP2_RX_FIFO_BASE : begin
+      slaveEP2RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2RxFifo;
+    end
+    `EP2_TX_FIFO_BASE : begin
+      slaveEP2TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2TxFifo;
+    end
+    `EP3_RX_FIFO_BASE : begin
+      slaveEP3RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3RxFifo;
+    end
+    `EP3_TX_FIFO_BASE : begin
+      slaveEP3TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3TxFifo;
+    end
+    `HOST_SLAVE_CONTROL_BASE : begin
+      hostSlaveMuxSel <= 1'b1; 
+      dataOut <= dataFromHostSlaveMux;
+    end
+    default: 
+      dataOut <= 8'h00;
+  endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+  ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+  ack_immediate <= strobe_i;
+end 
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+  if (writeEn == 1'b0 &&
+      (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+  begin
+    ack_o <= ack_delayed;
+  end
+  else
+  begin
+    ack_o <= ack_immediate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.asf	(revision 264)
@@ -0,0 +1,287 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=259
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// getpacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
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+UPPERLEFT 0,0
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+OBJECTS
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+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
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+                                              122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177616,25344 184028,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176799,72082 177196,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n  RXPktStatus = { \n  dataSequence, ACKRxed, \n  stallRxed, NAKRxed,\n  RXTimeOut, RXOverflow, \n  bitStuffError, CRCError};\nend"
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+                                           57686,214631 75382,223396 84426,228258
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.asf	(revision 264)
@@ -0,0 +1,298 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=445
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hostController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 47
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 49
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 51
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+A 302 83 16 TEXT "Actions" | 136700,161820 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;"
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+                                        170250,145750 137550,145450 128737,144962 119925,144475\
+                                        117963,142662 116688,141837
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+I 56 52 0 Builtin Exit | 155694,46048
+I 55 52 0 Builtin Entry | 88756,239499
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+W 332 66 0 220 435 BEZIER "Transitions" | 82899,126626 83372,118876 55983,116868 40261,109385
+C 333 332 0 TEXT "Conditions" | 54763,123556 1 0 0 "sendPacketRdy == 1'b1"
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+                                          110726,37400 115182,37514 117348,37514
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+W 95 6 0 294 41 BEZIER "Transitions" | 117484,22592 114800,20099 105581,15162 96803,16522\
+                                       88026,17883 53248,36150 43780,48625 34312,61101\
+                                       33772,117285 37441,132224 41110,147164 52980,154980\
+                                       61012,157537 69044,160095 94076,164012 106263,166770
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+                                          129080,35838 133536,35952 135702,35952
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+I 365 73 0 Builtin Exit | 138662,35952
+I 366 73 0 Builtin Entry | 66816,246531
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+W 371 59 3 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+                                          40160,89849 37728,77233 37462,69633 37196,62033\
+                                          38564,44249 44378,36953 50192,29657 72080,18257\
+                                          79528,15331 86976,12405 94012,13028 97964,12876
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+I 96 6 0 Builtin Reset | 67359,192312
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+I 411 59 0 Builtin Exit | 100924,12876
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+                                          134254,207065 123583,209376 117848,210301
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+C 444 320 0 TEXT "Conditions" | 127768,183900 1 0 0 "sendPacketRdy == 1'b1"
+C 442 441 0 TEXT "Conditions" | 70632,78432 1 0 0 "isoEn == 1'b1"
+W 441 59 1 152 411 BEZIER "Transitions" | 80207,97867 74663,87703 63240,68436 60930,60120\
+                                          58620,51804 60468,38868 64038,33660 67608,28452\
+                                          80040,20556 84492,18330 88944,16104 95212,13380\
+                                          97900,12876
+W 440 66 2 435 216 BEZIER "Transitions" | 37283,96930 37450,86034 36933,64502 39250,56716\
+                                          41567,48930 50502,39578 58559,36864 66617,34151\
+                                          89914,32647 97658,32793 105403,32939 113545,36471\
+                                          117386,37514
+C 439 436 0 TEXT "Conditions" | 45200,98446 1 0 0 "isoEn == 1'b0"
+A 437 436 16 TEXT "Actions" | 45964,81812 1 0 0 "getPacketREn <= 1'b1;"
+W 436 66 1 435 331 BEZIER "Transitions" | 43135,99848 51564,83991 80050,72911 89986,72452
+S 435 66 147456 ELLIPSE "States" | 37700,103412 6500 6500
+L 434 435 0 TEXT "State Labels" | 37700,103412 1 0 0 "CHK_ISO\n/32/"
+I 433 0 2 Builtin InPort | 150555,227440 "" ""
+L 432 433 0 TEXT "Labels" | 156555,227440 1 0 0 "isoEn"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+I 215 66 0 Builtin Entry | 50996,240683
+I 216 66 0 Builtin Exit | 120308,37514
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.v	(revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   fullSpeedPolarity;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   [3:0]PID;
+input   rst;
+input   sendPacketWEn;
+input   [6:0]TxAddr;
+input   [3:0]TxEndP;
+output  fifoReadEn;
+output  [10:0]frameNum;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+reg     [10:0]frameNum, next_frameNum;
+wire    fullSpeedPolarity;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    [3:0]PID;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+wire    [6:0]TxAddr;
+wire    [3:0]TxEndP;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+`define LS_EOP_WAIT_RDY 5'b10101
+`define LS_EOP_FIN 5'b10110
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or fullSpeedPolarity or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+  NextState_sndPkt <= CurrState_sndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  next_frameNum <= frameNum;
+  case (CurrState_sndPkt)  // synopsys parallel_case full_case
+    `START_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+    end
+    `WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_sndPkt <= `SP_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `SP_WAIT_GNT:
+    begin
+      if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
+      begin
+        NextState_sndPkt <= `LS_EOP_WAIT_RDY;
+      end
+      else if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_HCTxPortReq <= 1'b0;
+    end
+    `SEND_PID_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= PIDNotPID;
+        next_HCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SEND_PID_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+      end
+      else if (PID == `SOF)
+      begin
+        NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+      end
+      else if (PID == `OUT || 
+        PID == `IN || 
+        PID == `SETUP)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sndPkt <= `FIN_SP;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY1:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY2:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `OUT_IN_SETUP_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+    end
+    `SEND_SOF_FIN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_frameNum <= frameNum + 1'b1;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `SEND_SOF_WAIT_RDY3:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= frameNum[7:0];
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_WAIT_RDY4:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_FIN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+    end
+    `DATA0_DATA1_READ_FIFO:
+    begin
+      next_HCTxPortWEn <= 1'b1;
+      next_HCTxPortData <= fifoData;
+      next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+    end
+    `DATA0_DATA1_WAIT_READ_FIFO:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `DATA0_DATA1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+      end
+    end
+    `DATA0_DATA1_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `DATA0_DATA1_TERM_BYTE:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `DATA0_DATA1_CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+    end
+    `DATA0_DATA1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+    end
+    `LS_EOP_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `LS_EOP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
+      end
+    end
+    `LS_EOP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sndPkt <= `START_SP;
+  else
+    CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    HCTxPortData <= 8'h00;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+    frameNum <= 11'h000;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+    frameNum <= next_frameNum;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.v	(revision 264)
@@ -0,0 +1,218 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketcheckpreamble
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   preAmbleEnable;
+input   rst;
+input   [3:0]sendPacketCPPID;
+input   sendPacketCPWEn;
+input   sendPacketRdy;
+output  sendPacketCPReady;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+
+wire    clk;
+wire    preAmbleEnable;
+wire    rst;
+wire    [3:0]sendPacketCPPID;
+reg     sendPacketCPReady, next_sendPacketCPReady;
+wire    sendPacketCPWEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_PREAM_SENT 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_PID_SENT 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+`define PREAM_PKT_WAIT_RDY2 4'b1100
+`define PREAM_PKT_WAIT_RDY3 4'b1101
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
+begin
+  NextState_sendPktCP <= CurrState_sendPktCP;
+  // Set default values for outputs and signals
+  next_sendPacketCPReady <= sendPacketCPReady;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  case (CurrState_sendPktCP)  // synopsys parallel_case full_case
+    `SPC_WAIT_EN:
+    begin
+      if (sendPacketCPWEn == 1'b1)
+      begin
+        NextState_sendPktCP <= `CHK_PREAM;
+        next_sendPacketCPReady <= 1'b0;
+      end
+    end
+    `START_SPC:
+    begin
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `CHK_PREAM:
+    begin
+      if (preAmbleEnable == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+      end
+    end
+    `READY:
+    begin
+      next_sendPacketCPReady <= 1'b1;
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `PREAM_PKT_SND_PREAM:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= `PREAMBLE;
+      NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
+    end
+    `PREAM_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+      end
+    end
+    `PREAM_PKT_PREAM_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+    end
+    `PREAM_PKT_SND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
+    end
+    `PREAM_PKT_PID_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+    end
+    `PREAM_PKT_WAIT_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+      end
+    end
+    `PREAM_PKT_WAIT_RDY3:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `READY;
+      end
+    end
+    `REG_PKT_SEND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+    end
+    `REG_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `REG_PKT_SEND_PID;
+      end
+    end
+    `REG_PKT_WAIT_RDY:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `READY;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktCP <= `START_SPC;
+  else
+    CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketCPReady <= 1'b1;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+  end
+  else 
+  begin
+    sendPacketCPReady <= next_sendPacketCPReady;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.v	(revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// softransmit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input   clk;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   SOFEnable;    // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input   SOFSyncEn;
+input   [15:0]SOFTimer;
+output  sendPacketArbiterReq;
+output  sendPacketWEn;
+output  SOFSent;    // single cycle pulse
+output  SOFTimerClr;    // Single cycle pulse
+
+wire    clk;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+wire    SOFEnable;
+reg     SOFSent, next_SOFSent;
+wire    SOFSyncEn;
+wire    [15:0]SOFTimer;
+reg     SOFTimerClr, next_SOFTimerClr;
+
+// diagram signals declarations
+reg  [7:0]i, next_i;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+`define DLY_SOF_CHK1 3'b101
+`define DLY_SOF_CHK2 3'b110
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or i or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+  NextState_SOFTx <= CurrState_SOFTx;
+  // Set default values for outputs and signals
+  next_SOFSent <= SOFSent;
+  next_SOFTimerClr <= SOFTimerClr;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_i <= i;
+  case (CurrState_SOFTx)  // synopsys parallel_case full_case
+    `START_STX:
+    begin
+      NextState_SOFTx <= `WAIT_SOF_NEAR;
+    end
+    `WAIT_SOF_NEAR:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+        (SOFSyncEn == 1'b1 &&
+        SOFEnable == 1'b1))
+      begin
+        NextState_SOFTx <= `WAIT_SP_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `WAIT_SP_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+      begin
+        NextState_SOFTx <= `WAIT_SOF_NOW;
+      end
+    end
+    `WAIT_SOF_NOW:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_sendPacketWEn <= 1'b1;
+        next_SOFTimerClr <= 1'b1;
+        next_SOFSent <= 1'b1;
+      end
+      else if (SOFEnable == 1'b0)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_SOFTimerClr <= 1'b1;
+      end
+    end
+    `SOF_FIN:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      next_SOFTimerClr <= 1'b0;
+      next_SOFSent <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_SOFTx <= `DLY_SOF_CHK1;
+        next_i <= 8'h00;
+      end
+    end
+    `DLY_SOF_CHK1:
+    begin
+      next_i <= i + 1'b1;
+      if (i==8'hff)
+      begin
+        NextState_SOFTx <= `DLY_SOF_CHK2;
+        next_sendPacketArbiterReq <= 1'b0;
+        next_i <= 8'h00;
+      end
+    end
+    `DLY_SOF_CHK2:
+    begin
+      next_i <= i + 1'b1;
+      if (i==8'hff)
+      begin
+        NextState_SOFTx <= `WAIT_SOF_NEAR;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SOFTx <= `START_STX;
+  else
+    CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFSent <= 1'b0;
+    SOFTimerClr <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketWEn <= 1'b0;
+    i <= 8'h00;
+  end
+  else 
+  begin
+    SOFSent <= next_SOFSent;
+    SOFTimerClr <= next_SOFTimerClr;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketWEn <= next_sendPacketWEn;
+    i <= next_i;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v	(revision 264)
@@ -0,0 +1,94 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMuxBI.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbHostSlave_h.v"
+
+ module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, clk, rst,
+  hostMode, hostSlaveMuxSel);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+
+//internal wire and regs
+
+//sync write demux
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+    hostMode <= 1'b0;
+  else begin
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+      hostMode <= dataIn[0];
+  end
+end
+
+
+// async read mux
+always @(address or hostMode)
+begin
+  case (address)
+    `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+    `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+  endcase
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSerialInterfaceEngine_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSerialInterfaceEngine_h.v	(revision 264)
@@ -0,0 +1,103 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v                                
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+`define TX_LS_KEEP_ALIVE 8'h06
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+// RESUME_RX_WAIT_TIME defines the time period for resume detection
+// The resume counter is incremented at the bit rate, so
+// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
+// and 30 * 1/1.5MHz =  20uS at low speed, both of which are within the USB spec of 
+// 2.5uS <= resumeDetectTime <= 100uS
+`define RESUME_RX_WAIT_TIME 5'd29
+//`define RESUME_WAIT_TIME_MINUS1 9
+// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate 
+`define HOST_TX_RESUME_TIME 16'd30000  //Host sends resume for 30000 * 1/1.5MHz = 20mS
+//`define CONNECT_WAIT_TIME 8'd20
+`define CONNECT_WAIT_TIME 8'd120      //Device connect detected after 120 * 1/48MHz = 2.5uS
+//`define DISCONNECT_WAIT_TIME 8'd20   
+`define DISCONNECT_WAIT_TIME 8'd120   //Device disconnect detected after 120 * 1/48MHz = 2.5uS
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates 
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_06_alpha/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_06_alpha/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifoBI.v	(revision 264)
@@ -0,0 +1,124 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+  address, 
+  writeEn, 
+  strobe_i,
+  clk, 
+  rst, 
+  fifoSelect,
+  fifoDataIn,
+  busDataIn, 
+  busDataOut,
+  fifoREn,
+  fifoEmpty,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoREn;
+input fifoEmpty;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoREn;
+wire fifoEmpty;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)
+begin
+  case (address)
+      `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00; 
+  endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b0 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoREn <= 1'b1;
+  else
+    fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoRTL.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoRTL.v	(revision 264)
@@ -0,0 +1,139 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoRTL.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+////  User must check full and empty flags before accessing fifo
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input rst;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoWEn;
+input fifoREn;
+output fifoFull;
+output fifoEmpty;
+input forceEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire clk;
+wire rst;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg  [15:0]numElementsInFifo;
+
+
+// local registers
+reg  [ADDR_WIDTH-1:0]bufferInIndex;
+reg  [ADDR_WIDTH-1:0]bufferOutIndex;
+reg  [ADDR_WIDTH:0]bufferCnt;
+reg  fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || forceEmpty == 1'b1)
+  begin
+    bufferCnt <= 0;
+    fifoFull <= 1'b0;
+    fifoEmpty <= 1'b1;
+    bufferInIndex <= 0;
+    bufferOutIndex <= 0;
+    fifoREnDelayed <= 1'b0;
+  end
+    else
+    begin
+      if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        dataOut <= dataFromMem;
+      end
+      fifoREnDelayed <= fifoREn;
+      if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
+        bufferCnt <= bufferCnt + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end 
+      else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferCnt <= bufferCnt - 1;
+        bufferOutIndex <= bufferOutIndex + 1;
+      end
+      else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferOutIndex <= bufferOutIndex + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end
+      if (bufferCnt[ADDR_WIDTH] == 1'b1)
+        fifoFull <= 1'b1;
+      else
+        fifoFull <= 1'b0;
+      if (|bufferCnt == 1'b0) 
+        fifoEmpty <= 1'b1;
+      else
+        fifoEmpty <= 1'b0;
+    end
+end
+
+//pad bufferCnt with leading zeroes
+always @(bufferCnt) begin
+  numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
+end
+
+fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_fifoMem (
+  .addrIn(bufferInIndex),
+  .addrOut(bufferOutIndex),
+  .clk(clk),
+  .dataIn(dataIn),
+  .writeEn(fifoWEn),
+  .readEn(fifoREn),
+  .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// directControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\
+                                       47285,153175 50048,167625 56316,171290 62585,174956\
+                                       84856,175714 96012,175820
+I 124 79 0 Builtin Entry | 109800,175900
+I 122 79 0 Builtin Exit | 138103,36586
+S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
+S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
+C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "HCTxPortGnt == 1'b1"
+W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
+H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "HCTxPortWEn"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]"
+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "HCTxPortCntl[7:0]"
+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+                                        171826,160150 159742,169266 150997,171704 142252,174142\
+                                        120424,175336 108976,175654
+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "HCTxPortReq <= 1'b1;"
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "HCTxPortGnt"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "HCTxPortRdy"
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;"
+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.asf	(revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hctxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
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+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,543100 1 0 0 "Module: HCTxPortArbiter"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
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+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_HARB\n/0/"
+S 10 6 4096 ELLIPSE "States" | 224972,365039 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "WAIT_REQ\n/1/"
+S 12 6 8192 ELLIPSE "States" | 191859,293613 6500 6500
+L 13 12 0 TEXT "State Labels" | 191859,293613 1 0 0 "SEND_SOF\n/2/"
+S 14 6 12288 ELLIPSE "States" | 269063,296392 6500 6500
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SEND_PACKET\n/3/"
+I 16 6 0 Builtin Reset | 178237,395710
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210052,391894 219337,393602
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 19 6 2 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
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+C 21 20 0 TEXT "Conditions" | 185611,358255 1 0 0 "SOFCntlReq == 1'b1"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxCntl <= `SEND_PACKET_MUX;"
+A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;"
+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
+C 26 17 0 TEXT "Conditions" | 201742,391978 1 0 0 "rst"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+                                      288786,359372 287077,371461 282417,376909 277757,382357\
+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
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+                                      166944,348155 168507,364217 173450,370590 178394,376963\
+                                      186275,384997 193806,383684 201338,382371 213515,373400\
+                                      220004,369229
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n  `SOF_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= SOFCntlWEn;\n    HCTxPortData <= SOFCntlData;\n    HCTxPortCntl <= SOFCntlCntl;\n  end\n  `DIRECT_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= directCntlWEn;\n    HCTxPortData <= directCntlData;\n    HCTxPortCntl <= directCntlCntl;\n  end\n  `SEND_PACKET_MUX :\n  begin  \n    HCTxPortWEnable <= sendPacketWEn;\n    HCTxPortData <= sendPacketData;\n    HCTxPortCntl <= sendPacketCntl;\n  end\n  default :\n  begin  \n    HCTxPortWEnable <= 1'b0;\n    HCTxPortData <= 8'h00;\n    HCTxPortCntl <= 8'h00;\n  end\nendcase	\nend"
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+I 89 0 130 Builtin Signal | 141050,528812 "" ""
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286404,388600 275724,388298\
+                                      265045,387996 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/rxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/rxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// rxStatusMonitor.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      connectionEventOut <= 1'b1;
+    else
+      connectionEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.v	(revision 264)
@@ -0,0 +1,177 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketarbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input   clk;
+input   [3:0]HC_PID;
+input   HC_SP_WEn;
+input   HCTxReq;
+input   rst;
+input   SOF_SP_WEn;
+input   SOFTxReq;
+output  HCTxGnt;
+output  [3:0]sendPacketPID;
+output  sendPacketWEnable;
+output  SOFTxGnt;
+
+wire    clk;
+wire    [3:0]HC_PID;
+wire    HC_SP_WEn;
+reg     HCTxGnt, next_HCTxGnt;
+wire    HCTxReq;
+wire    rst;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+reg     sendPacketWEnable, next_sendPacketWEnable;
+wire    SOF_SP_WEn;
+reg     SOFTxGnt, next_SOFTxGnt;
+wire    SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC  == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+  NextState_sendPktArb <= CurrState_sendPktArb;
+  // Set default values for outputs and signals
+  next_HCTxGnt <= HCTxGnt;
+  next_SOFTxGnt <= SOFTxGnt;
+  next_muxSOFNotHC <= muxSOFNotHC;
+  case (CurrState_sendPktArb)  // synopsys parallel_case full_case
+    `HC_ACT:
+    begin
+      if (HCTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_HCTxGnt <= 1'b0;
+      end
+    end
+    `SOF_ACT:
+    begin
+      if (SOFTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_SOFTxGnt <= 1'b0;
+      end
+    end
+    `SARB_WAIT_REQ:
+    begin
+      if (SOFTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `SOF_ACT;
+        next_SOFTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b1;
+      end
+      else if (HCTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `HC_ACT;
+        next_HCTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_sendPktArb <= `SARB_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktArb <= `START_SARB;
+  else
+    CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxGnt <= 1'b0;
+    SOFTxGnt <= 1'b0;
+    muxSOFNotHC <= 1'b0;
+  end
+  else 
+  begin
+    HCTxGnt <= next_HCTxGnt;
+    SOFTxGnt <= next_SOFTxGnt;
+    muxSOFNotHC <= next_muxSOFNotHC;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.v	(revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sofcontroller
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input   clk;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+input   SOFEnable;
+input   SOFTimerClr;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [15:0]SOFTimer;
+
+wire    clk;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+wire    SOFEnable;
+reg     [15:0]SOFTimer, next_SOFTimer;
+wire    SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+  NextState_sofCntl <= CurrState_sofCntl;
+  // Set default values for outputs and signals
+  next_SOFTimer <= SOFTimer;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_sofCntl)  // synopsys parallel_case full_case
+    `START_SC:
+    begin
+      NextState_sofCntl <= `WAIT_SOF_EN;
+    end
+    `WAIT_SOF_EN:
+    begin
+      if (SOFEnable == 1'b1)
+      begin
+        NextState_sofCntl <= `SC_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `WAIT_SEND_RESUME:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sofCntl <= `CLR_WEN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_RESUME_START;
+      end
+    end
+    `INC_TIMER:
+    begin
+      next_HCTxPortReq <= 1'b0;
+      if (SOFTimerClr == 1'b1)
+      next_SOFTimer <= 16'h0000;
+      else
+      next_SOFTimer <= SOFTimer + 1'b1;
+      if (SOFEnable == 1'b0)
+      begin
+        NextState_sofCntl <= `WAIT_SOF_EN;
+        next_SOFTimer <= 16'h0000;
+      end
+    end
+    `SC_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sofCntl <= `WAIT_SEND_RESUME;
+      end
+    end
+    `CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sofCntl <= `INC_TIMER;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sofCntl <= `START_SC;
+  else
+    CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFTimer <= 16'h0000;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SOFTimer <= next_SOFTimer;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/usbHostControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/usbHostControl.v	(revision 264)
@@ -0,0 +1,386 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostControl(
+  clk, rst,
+  //sendPacket
+  TxFifoRE, TxFifoData, TxFifoEmpty,
+  //getPacket
+  RxFifoWE, RxFifoData, RxFifoFull,
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //HCTxPortArbiter
+  HCTxPortEn, HCTxPortRdy,
+  HCTxPortData, HCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFSentIntOut, 
+  connEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  hostControlSelect
+    );
+
+input clk, rst;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [3:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut; 
+output connEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+input hostControlSelect;
+
+wire clk;
+wire rst;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut; 
+wire connEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire isoEn;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI 
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .SOFSentIntOut(SOFSentIntOut), 
+  .connEventIntOut(connEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .TxTransTypeReg(transType), 
+  .TxSOFEnableReg(SOFEnable),
+  .TxAddrReg(TxAddr), 
+  .TxEndPReg(TxEndP), 
+  .frameNumIn(frameNum), 
+  .RxPktStatusIn(RxPktStatus), 
+  .RxPIDIn(RxPID),
+  .connectStateIn(connectStateOut),
+  .SOFSentIn(SOFSent), 
+  .connEventIn(connectionEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .hostControlSelect(hostControlSelect),
+  .clrTransReq(clrTxReq),
+  .preambleEn(preAmbleEnable),
+  .SOFSync(SOFSyncEn),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .transReq(transReq),
+  .isoEn(isoEn)
+  
+  );
+
+
+hostcontroller u_hostController
+  (.RXStatus(RxPktStatus), 
+  .clearTXReq(clrTxReq),
+  .clk(clk),
+  .getPacketREn(getPacketREn),
+  .getPacketRdy(getPacketRdy),
+  .rst(rst),
+  .sendPacketArbiterGnt(HCTxGnt),
+  .sendPacketArbiterReq(HCTxReq),
+  .sendPacketPID(HC_PID),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(HC_SP_WEn),
+  .transDone(transDone),
+  .transReq(transReq),
+  .transType(transType),
+  .isoEn(isoEn) );
+
+SOFController u_SOFController
+  (.HCTxPortCntl(SOFCntlCntl),
+  .HCTxPortData(SOFCntlData),
+  .HCTxPortGnt(SOFCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(SOFCntlReq),
+  .HCTxPortWEn(SOFCntlWEn),
+  .SOFEnable(SOFEnable),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(clk),
+  .rst(rst) ); 
+
+SOFTransmit u_SOFTransmit
+  (.SOFEnable(SOFEnable),
+  .SOFSent(SOFSent),
+  .SOFSyncEn(SOFSyncEn),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(clk),
+  .rst(rst),
+  .sendPacketArbiterGnt(SOFTxGnt),
+  .sendPacketArbiterReq(SOFTxReq),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(SOF_SP_WEn) );  
+
+
+sendPacketArbiter u_sendPacketArbiter
+  (.HCTxGnt(HCTxGnt),
+  .HCTxReq(HCTxReq),
+  .HC_PID(HC_PID),
+  .HC_SP_WEn(HC_SP_WEn),
+  .SOFTxGnt(SOFTxGnt),
+  .SOFTxReq(SOFTxReq),
+  .SOF_SP_WEn(SOF_SP_WEn),
+  .clk(clk),
+  .rst(rst),
+  .sendPacketPID(sendPacketCPPIDIn),
+  .sendPacketWEnable(sendPacketCPWEnIn) );    
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+  (.sendPacketCPPID(sendPacketCPPIDIn),
+  .clk(clk),
+  .preAmbleEnable(preAmbleEnable),
+  .rst(rst),
+  .sendPacketCPReady(sendPacketCPReadyOut),
+  .sendPacketCPWEn(sendPacketCPWEnIn),
+  .sendPacketPID(sendPacketCPPIDOut),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+  (.HCTxPortCntl(sendPacketCntl),
+  .HCTxPortData(sendPacketData),
+  .HCTxPortGnt(sendPacketGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(sendPacketReq),
+  .HCTxPortWEn(sendPacketWEn),
+  .PID(sendPacketCPPIDOut),
+  .TxAddr(TxAddr),
+  .TxEndP(TxEndP),
+  .clk(clk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .frameNum(frameNum),
+  .rst(rst),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut),
+  .fullSpeedPolarity(fullSpeedPol) );
+  
+directControl u_directControl
+  (.HCTxPortCntl(directCntlCntl),
+  .HCTxPortData(directCntlData),
+  .HCTxPortGnt(directCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(directCntlReq),
+  .HCTxPortWEn(directCntlWEn),
+  .clk(clk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rst) ); 
+
+HCTxPortArbiter u_HCTxPortArbiter
+  (.HCTxPortCntl(HCTxPortCtrl),
+  .HCTxPortData(HCTxPortData),
+  .HCTxPortWEnable(HCTxPortEn),
+  .SOFCntlCntl(SOFCntlCntl),
+  .SOFCntlData(SOFCntlData),
+  .SOFCntlGnt(SOFCntlGnt),
+  .SOFCntlReq(SOFCntlReq),
+  .SOFCntlWEn(SOFCntlWEn),
+  .clk(clk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rst),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+getPacket u_getPacket
+  (.RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXPktStatus(RxPktStatus),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .clk(clk),
+  .getPacketEn(getPacketREn),
+  .rst(rst) ); 
+
+rxStatusMonitor  u_rxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .connectionEventOut(connectionEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(clk),
+  .rst(rst)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostControl_h.v	(revision 264)
@@ -0,0 +1,73 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v                                          
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+`define ISO_ENABLE_BIT 3
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+ 
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants 
+//`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval   
+//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer 
+`define SOF_TX_TIME 16'hbb7d     //Correct SOF interval for 48MHz clock.
+//`define SOF_TX_MARGIN 2 
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+       
+//Host RXStatusRegIndices 
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined 

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/wishBoneBus_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/wishBoneBus_h.v	(revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+ 
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.asf	(revision 264)
@@ -0,0 +1,315 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=258
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processrxbit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
+BUNDLES
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
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+GRIDSIZE 5000,5000 10000,10000
+END
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+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 7 6 0 TEXT "Labels" | 23239,210942 1 0 0 "prRxBit"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,221539
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 94226,265828 1 0 0 "Module: processRxBit"
+L 8 9 0 TEXT "State Labels" | 42238,183458 1 0 0 "START\n/0/"
+S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
+I 12 6 0 Builtin Reset | 22728,190398
+W 13 6 0 12 9 BEZIER "Transitions" | 22728,190398 27224,190134 31822,186104 35786,184244
+L 15 16 0 TEXT "State Labels" | 116068,123104 1 0 0 "IDLE"
+S 16 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116068,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 18 17 8192 ELLIPSE "States" | 99337,112266 6500 6500
+L 19 18 0 TEXT "State Labels" | 99337,112266 1 0 0 "FIRST_BIT\n/1/"
+I 20 17 0 Builtin Entry | 56736,212076
+I 21 17 0 Builtin Exit | 146563,24238
+W 23 17 0 18 21 BEZIER "Transitions" | 103975,107713 107885,100636 103154,45547 143864,24443
+S 24 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116801,94499 6500 6500
+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
+W 35 41 0 40 37 BEZIER "Transitions" | 111741,134422 116780,127404 121695,118778 126735,111760
+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
+I 37 41 0 Builtin Exit | 129540,111760
+I 38 41 0 Builtin Entry | 86360,167640
+L 39 40 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK\n/9/"
+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 119820,36808 1 0 0 "RES_END"
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 51 6 0 213 16 BEZIER "Transitions" | 42388,154240 42522,148478 41966,137442 42502,133556\
+                                       43038,129670 44914,125650 53423,124511 61932,123372\
+                                       93489,123426 109569,123158
+W 52 6 0 213 24 BEZIER "Transitions" | 42699,154238 43235,140704 42636,114126 43641,106354\
+                                       44646,98582 47594,94562 55902,93624 64210,92686\
+                                       94494,92954 102132,93021 109770,93088 110325,93078\
+                                       110459,93078
+W 53 6 0 213 33 BEZIER "Transitions" | 42645,154234 43047,131722 42770,88800 43976,77142\
+                                       45182,65484 49202,63876 57711,63474 66220,63072\
+                                       96236,63072 103807,63072 111378,63072 111758,63165\
+                                       111892,63165
+W 54 6 0 213 42 BEZIER "Transitions" | 42671,154227 43609,125551 43842,70308 45115,54764\
+                                       46388,39220 49604,34396 58247,33391 66890,32386\
+                                       97657,35973 113335,36375
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+                                       188238,99472 188778,113512 186145,122422 183513,131332\
+                                       167904,143587 159264,149864 150624,156142 133542,158851\
+                                       125779,159931 118017,161011 123617,159646 119837,160051
+W 68 6 0 16 219 BEZIER "Transitions" | 121312,119265 131167,111435 152206,96104 162061,88274
+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 114133,117894 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h0;                          \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+W 76 17 4096 241 18 BEZIER "Transitions" | 152390,172884 131374,171355 101683,127861 94565,116677
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
+W 82 17 8194 75 21 BEZIER "Transitions" | 74719,170800 72243,162260 51221,151750 45574,140719\
+                                          39928,129688 39788,80170 47763,75675 55738,71180\
+                                          102436,61038 148189,26024
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 95824,146799 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+                                            151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+                                        176540,156388 181096,131196 181431,113977 181766,96758\
+                                        182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit)                           //if current bit is a JBit, then\n  RXBitStMachCurrState <= `IDLE_BIT_ST;       //next state is idle\nelse                                          //else\nbegin\n  RXBitStMachCurrState <= `WAIT_RESUME_ST;    //check for resume\n  resumeWaitCnt <= 5'h0;                          \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte;       \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit)  //line must leave KBit state for the end of resume\nbegin\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\n  resumeDetected <= 1'b0;   //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit)  //can only be a resume if line remains in Kbit state\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n  resumeWaitCnt <= resumeWaitCnt + 1'b1; \n  //if we've waited long enough, then\n  if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)\n  begin	\n    RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n    resumeDetected <= 1'b1;  //report resume detected\n  end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+                                         107061,21822 137747,20482 148467,20415 159187,20348\
+                                         171381,21420 174463,22458 177545,23497 178090,26035\
+                                         178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+                                         145117,36964 157043,31068 161599,29627 166155,28187\
+                                         172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 5'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[4:0]"
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 25628,249822 1 0 0 "if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n  RXSameBitCount <= RXSameBitCount + 1'b1;  //inc 'RXSameBitCount'\n  if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error\n    bitStuffError <= 1'b1;                         //flag 'bitStuffError'\n  else                                          //else no bit stuffing error\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin\n      processRxBitRdy <= 1'b1;                   //early indication of ready\n	end\n    RXByte <= { 1'b1, RXByte[7:1]};              //RZ bit = 1 (ie no change in 'RxBits')\n  end\nend\nelse                                            //else current 'RxBits' are different from old 'RxBits'\nbegin\n  if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;	               //early indication of ready\n	end\n    RXByte <= {1'b0, RXByte[7:1]};             //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n  end\n   RXSameBitCount <= 4'h0;                      //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 151892,179359 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 151892,179359 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 135677,178559 145432,178646
+C 243 242 0 TEXT "Conditions" | 82407,188660 1 0 0 "(RxBits == KBit) && (RxWireActive == 1'b1)"
+C 244 76 0 TEXT "Conditions" | 137618,163943 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+I 257 0 2 Builtin InPort | 150840,260800 "" ""
+L 256 257 0 TEXT "Labels" | 156840,260800 1 0 0 "RxWireActive"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.asf	(revision 264)
@@ -0,0 +1,311 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1126
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processTxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 874
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
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+GRIDSIZE 0,0 10000,10000
+END
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 1098 1035 0 1095 1097 BEZIER "Transitions" | 108942,40143 114373,39761 124823,37993 130254,37611
+I 1097 1035 0 Builtin Exit | 133008,37611
+A 1096 1095 4 TEXT "Actions" | 110058,56736 1 0 0 "USBWireWEn <= 1'b0;"
+S 1095 1035 106496 ELLIPSE "States" | 102676,41870 6500 6500
+L 1094 1095 0 TEXT "State Labels" | 102676,41870 1 0 0 "FIN\n/21/"
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin InPort | 123679,239194 "" ""
+L 821 822 0 TEXT "Labels" | 129679,239194 1 0 0 "TxByteCtrlIn[7:0]"
+I 820 0 130 Builtin InPort | 123679,243601 "" ""
+L 819 820 0 TEXT "Labels" | 129679,243601 1 0 0 "TxByteIn[7:0]"
+I 818 0 2 Builtin OutPort | 121572,248474 "" ""
+L 817 818 0 TEXT "Labels" | 127572,248474 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin InPort | 123679,253114 "" ""
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+A 1088 1087 16 TEXT "Actions" | 81756,164067 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+C 1089 1087 0 TEXT "Conditions" | 68348,136414 1 0 0 "USBWireRdy == 1'b1"
+A 1090 1084 4 TEXT "Actions" | 60764,178497 1 0 0 "USBWireWEn <= 1'b0;"
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+                                            157955,32952 139055,31533 132716,31415 126377,31297\
+                                            121929,32154 118701,32626
+C 1092 1091 0 TEXT "Conditions" | 145670,31298 1 0 0 "TxByteFullSpeedRate  == 1'b0"
+W 1093 6 0 1034 874 BEZIER "Transitions" | 107126,38228 93109,49095 67454,69717 53517,80692
+L 1099 1100 0 TEXT "State Labels" | 52016,132400 1 0 0 "W_RDY1\n/22/"
+S 1100 1035 110592 ELLIPSE "States" | 52016,132400 6500 6500
+W 1103 1035 0 1084 1100 BEZIER "Transitions" | 50775,157143 50927,152127 51227,143877 51379,138861
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 1104 1105 0 TEXT "State Labels" | 175744,133008 1 0 0 "W_RDY2\n/23/"
+S 1105 1035 114688 ELLIPSE "States" | 175744,133008 6500 6500
+L 1106 1107 0 TEXT "State Labels" | 180608,78592 1 0 0 "W_RDY3\n/24/"
+S 1107 1035 118784 ELLIPSE "States" | 180608,78592 6500 6500
+W 1108 1035 0 1046 1105 BEZIER "Transitions" | 125077,143006 136439,141182 157968,135884 169330,134060
+W 1109 1035 0 1068 1107 BEZIER "Transitions" | 127810,93623 140198,90963 162007,83161 174395,80501
+L 1110 1111 0 TEXT "State Labels" | 129359,218595 1 0 0 "W_RDY1\n/25/"
+S 1111 895 122880 ELLIPSE "States" | 129359,218595 6500 6500
+L 1112 1113 0 TEXT "State Labels" | 147977,176223 1 0 0 "W_RDY2\n/26/"
+S 1113 895 126976 ELLIPSE "States" | 147977,176223 6500 6500
+L 1114 1115 0 TEXT "State Labels" | 152471,133209 1 0 0 "W_RDY3\n/27/"
+S 1115 895 131072 ELLIPSE "States" | 152471,133209 6500 6500
+L 1116 1117 0 TEXT "State Labels" | 157607,86664 1 0 0 "W_RDY4\n/28/"
+S 1117 895 135168 ELLIPSE "States" | 157607,86664 6500 6500
+W 1118 895 0 948 1111 BEZIER "Transitions" | 78609,218255 90004,218415 111471,218138 122866,218298
+W 1119 895 0 942 1113 BEZIER "Transitions" | 81422,174858 96749,175660 126155,175178 141482,175980
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+W 1120 895 0 956 1115 BEZIER "Transitions" | 84631,133419 97918,132655 128828,133044 145972,133233
+W 1121 895 0 962 1117 BEZIER "Transitions" | 87535,83532 103906,84093 134787,85298 151158,85859
+L 1122 1123 0 TEXT "Labels" | 72332,217706 1 0 0 "TxByteFullSpeedRate"
+I 1123 0 2 Builtin Signal | 69653,217706 "" ""
+L 1124 1125 0 TEXT "Labels" | 23114,248843 1 0 0 "USBWireFullSpeedRate"
+I 1125 0 2 Builtin OutPort | 17114,248843 "" ""
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+C 870 869 0 TEXT "Conditions" | 45385,167359 1 0 0 "processTxByteWEn == 1'b1"
+A 871 869 16 TEXT "Actions" | 38769,162443 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;\nTxByteFullSpeedRate <= TxByteFullSpeedRateIn;\nUSBWireFullSpeedRate <= TxByteFullSpeedRateIn;"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+L 873 874 0 TEXT "State Labels" | 48799,85161 1 0 0 "SEND_BYTE"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48799,85161 6500 6500
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 883 880 0 Builtin Entry | 38120,248040
+I 884 880 0 Builtin Exit | 178131,23271
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+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47452,100861 48245,91628
+W 897 6 0 874 887 BEZIER "Transitions" | 48492,78681 48772,71498 48867,58679 49333,51573
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+                                         25630,50244 23766,53274 22950,67894 22135,82515\
+                                         20737,137969 21261,153813 21785,169657 25281,177579\
+                                         27028,179792 28775,182006 32271,182938 33727,182355\
+                                         35183,181773 37321,179186 38486,177555
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1)                      //If this bit is 1, then\n  TXOneCount <= TXOneCount + 1'b1;          //increment 'TXOneCount'\nelse                                        //else this is a zero bit\nbegin\n  TXOneCount <= 4'h0;                            //reset 'TXOneCount'\n  if (TXLineState == JBit) \n    TXLineState <= KBit; //toggle the line state\n  else \n    TXLineState <= JBit;\nend"
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == `MAX_CONSEC_SAME_BITS"
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h0;                                //reset 'TXOneCount'\nif (TXLineState == JBit) \n  TXLineState <= KBit;   //toggle the line state\nelse \n  TXLineState <= JBit;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+                                              113354,23912 154429,23527 174909,23271
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+                                              40522,42856 31562,47464 29098,65320 26634,83176\
+                                              25738,149992 26858,168968 27978,187944 33354,197032\
+                                              36938,198888 40522,200744 49226,198568 51498,198152\
+                                              53770,197736 54409,198230 54473,198230
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 4'h0;       \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+W 940 6 0 936 1005 BEZIER "Transitions" | 152571,107755 158885,103151 166953,83129 172936,74254
+C 941 940 0 TEXT "Conditions" | 159104,107836 1 0 0 "USBWireGnt == 1'b1"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+W 944 895 0 1111 942 BEZIER "Transitions" | 129757,212112 130385,204819 80759,192930 74325,181785
+C 945 944 0 TEXT "Conditions" | 128791,211803 1 0 0 "USBWireRdy == 1'b1"
+A 946 942 4 TEXT "Actions" | 92250,183175 1 0 0 "USBWireWEn <= 1'b0;"
+A 947 944 16 TEXT "Actions" | 109865,203040 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+W 958 895 0 1113 956 BEZIER "Transitions" | 148099,169766 148727,162473 88842,149177 77593,139316
+A 959 958 16 TEXT "Actions" | 127881,161233 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 960 956 4 TEXT "Actions" | 86480,140378 1 0 0 "USBWireWEn <= 1'b0;"
+C 961 958 0 TEXT "Conditions" | 146391,169184 1 0 0 "USBWireRdy == 1'b1"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+W 964 895 0 1115 962 BEZIER "Transitions" | 152792,126730 153420,119437 79847,97645 80475,90352
+A 965 964 16 TEXT "Actions" | 130933,116536 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+A 966 962 4 TEXT "Actions" | 90331,92695 1 0 0 "USBWireWEn <= 1'b0;"
+C 967 964 0 TEXT "Conditions" | 151835,126496 1 0 0 "USBWireRdy == 1'b1"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+W 970 895 0 1117 968 BEZIER "Transitions" | 157812,80182 158440,72889 82671,57884 83299,50591
+A 971 970 16 TEXT "Actions" | 138904,72921 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+C 973 970 0 TEXT "Conditions" | 155824,79891 1 0 0 "USBWireRdy == 1'b1"
+I 974 895 0 Builtin Exit | 97904,23272
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+                                           90132,26172 93257,24084 94765,23272
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+                                              104561,139388 153745,139620 168013,138576 182281,137532\
+                                              190169,133124 192141,121582 194113,110040 194113,68280\
+                                              192025,55114 189937,41948 185529,28723 181353,23271
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+                                              41124,121640 36948,124424 36020,132602 35092,140780\
+                                              35556,170708 38166,179350 40776,187992 50140,192687\
+                                              55128,195007
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+                                              30972,218732 29812,212468 29638,189094 29464,165720\
+                                              29928,78488 31900,55230 33872,31972 41296,26172\
+                                              49358,24664 57420,23156 82353,23388 94765,23272
+I 977 895 0 Builtin Entry | 34452,259216
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+A 979 9 4 TEXT "Actions" | 127034,208396 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;\nUSBWireFullSpeedRate <= 1'b0;\nTxByteFullSpeedRate <= 1'b0;"
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 997 995 0 Builtin Exit | 129540,111760
+I 996 995 0 Builtin Entry | 86360,167640
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+W 1000 6 2 1025 1011 BEZIER "Transitions" | 175446,48001 143324,42707 116663,67496 88157,75929
+A 1001 1000 16 TEXT "Actions" | 97876,75175 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit;  \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+S 1005 6 73728 ELLIPSE "States" | 178403,70739 6500 6500
+L 1006 1005 0 TEXT "State Labels" | 178403,71114 1 0 0 "WAIT_RDY_WIRE\n/15/"
+S 1011 6 77824 ELLIPSE "States" | 81933,77802 6500 6500
+A 1012 1011 4 TEXT "Actions" | 89664,97554 1 0 0 "USBWireWEn <= 1'b0;"
+L 1013 1011 0 TEXT "State Labels" | 81933,77802 1 0 0 "WAIT_RDY_PKT\n/16/"
+W 1020 6 0 1011 874 BEZIER "Transitions" | 75467,77142 69580,78790 60425,80424 54545,82123
+L 1021 1022 0 TEXT "Labels" | 129637,233935 1 0 0 "TxByteFullSpeedRateIn"
+I 1022 0 2 Builtin InPort | 123637,233935 "" ""
+H 1027 1025 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 1025 6 81940 ELLIPSE "Junction" | 178900,48560 3500 3500
+L 1026 1025 0 TEXT "State Labels" | 178900,48560 1 0 0 "J2"
+I 1028 1027 0 Builtin Entry | 86360,167640
+I 1029 1027 0 Builtin Exit | 129540,111760
+W 1030 1027 0 1028 1029 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+W 1031 6 0 1005 1025 BEZIER "Transitions" | 178252,64280 178492,60600 178502,55716 178742,52036
+C 1032 1031 0 TEXT "Conditions" | 160740,61840 1 0 0 "USBWireRdy == 1'b1"
+L 1033 1034 0 TEXT "State Labels" | 112501,34575 1 0 0 "LS_START"
+S 1034 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112501,34575 6500 6500
+H 1035 1034 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 1046 1035 90112 ELLIPSE "States" | 118913,145067 6500 6500
+L 1047 1046 0 TEXT "State Labels" | 118913,145067 1 0 0 "SND_IDLE3\n/17/"
+W 1060 1035 0 1107 1095 BEZIER "Transitions" | 176710,73393 172416,69158 96436,74541 101513,48264
+C 1061 1060 0 TEXT "Conditions" | 146295,70754 1 0 0 "USBWireRdy == 1'b1"
+A 1064 1060 16 TEXT "Actions" | 145913,63353 1 0 0 "//Drive the first JBit\nUSBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+W 1066 1035 0 1105 1068 BEZIER "Transitions" | 174692,126596 175320,119303 120603,109864 121231,102571
+C 1067 1066 0 TEXT "Conditions" | 172627,126718 1 0 0 "USBWireRdy == 1'b1"
+S 1068 1035 94208 ELLIPSE "States" | 121801,96100 6500 6500
+A 1069 1068 4 TEXT "Actions" | 140396,98815 1 0 0 "USBWireWEn <= 1'b0;"
+A 1070 1066 16 TEXT "Actions" | 152238,115920 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+L 1071 1068 0 TEXT "State Labels" | 121801,96100 1 0 0 "SND_J1\n/18/"
+L 815 816 0 TEXT "Labels" | 129679,253114 1 0 0 "processTxByteWEn"
+A 1073 1046 4 TEXT "Actions" | 137508,147782 1 0 0 "USBWireWEn <= 1'b0;"
+I 1075 1035 0 Builtin Entry | 75208,271435
+S 1077 1035 98304 ELLIPSE "States" | 59497,220774 6500 6500
+L 1078 1077 0 TEXT "State Labels" | 59497,220774 1 0 0 "SND_IDLE1\n/19/"
+W 1079 1035 0 1075 1077 BEZIER "Transitions" | 75208,269307 75836,262014 61041,234231 58933,227242
+W 1080 1035 0 1077 1084 BEZIER "Transitions" | 60047,214302 60675,207009 52849,177084 50437,170095
+A 1081 1080 16 TEXT "Actions" | 52141,196692 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+C 1082 1080 0 TEXT "Conditions" | 60959,213403 1 0 0 "USBWireRdy == 1'b1"
+S 1084 1035 102400 ELLIPSE "States" | 50985,163622 6500 6500
+L 1085 1084 0 TEXT "State Labels" | 50985,163622 1 0 0 "SND_IDLE2\n/20/"
+W 1087 1035 0 1100 1046 BEZIER "Transitions" | 56057,127311 71885,129746 98436,147110 112744,147113
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.v	(revision 264)
@@ -0,0 +1,276 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIEReceiver
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
+input   clk;
+input   rst;
+input   [1:0]RxWireDataIn;
+input   RxWireDataWEn;
+output  [1:0]connectState;
+
+wire    clk;
+reg     [1:0]connectState, next_connectState;
+wire    rst;
+wire    [1:0]RxWireDataIn;
+wire    RxWireDataWEn;
+
+// diagram signals declarations
+reg  [1:0]RxBits, next_RxBits;
+reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg  [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
+begin
+  NextState_rcvr <= CurrState_rcvr;
+  // Set default values for outputs and signals
+  next_RXWaitCount <= RXWaitCount;
+  next_connectState <= connectState;
+  next_RXStMachCurrState <= RXStMachCurrState;
+  next_RxBits <= RxBits;
+  case (CurrState_rcvr)  // synopsys parallel_case full_case
+    `WAIT_BIT:
+    begin
+      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+      begin
+        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+      begin
+        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+    end
+    `START_SRX:
+    begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_RXWaitCount <= 8'h00;
+      next_connectState <= `DISCONNECT;
+      next_RxBits <= 2'b00;
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `DISCNCT_CHK_RXBITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else if (RxBits == `ONE_ZERO)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+      end
+    end
+    `WAIT_FS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ONE_ZERO)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `FULL_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `WAIT_LS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `LOW_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `LS_CONN_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+      next_RXWaitCount <= 0;
+      end
+    end
+    `FS_CONN_CHK_RX_BITS1:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+      next_RXWaitCount <= 0;
+      end
+    end
+    `WAIT_LS_DIS_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_connectState <= `DISCONNECT;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+    end
+    `WAIT_FS_DIS_CHK_RX_BITS2:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_connectState <= `DISCONNECT;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_rcvr <= `START_SRX;
+  else
+    CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    connectState <= `DISCONNECT;
+    RXWaitCount <= 8'h00;
+    RXStMachCurrState <= `DISCONNECT_ST;
+    RxBits <= 2'b00;
+  end
+  else 
+  begin
+    connectState <= next_connectState;
+    RXWaitCount <= next_RXWaitCount;
+    RXStMachCurrState <= next_RXStMachCurrState;
+    RxBits <= next_RxBits;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSlaveControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSlaveControl_h.v	(revision 264)
@@ -0,0 +1,81 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v                                           
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants 
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices 
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices 
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices 
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+`define ENDPOINT_ISO_ENABLE_BIT 4
+//SCMasterControlegIndices 
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices 
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes 
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts 
+`define SC_RX_PACKET_TOUT 18
+       
+`endif //usbSlaveControl_h_vdefined  

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v	(revision 264)
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// lineControlUpdate.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+    if (fullSpeedPolarity == 1'b1)
+  begin
+      JBit = `ONE_ZERO;
+      KBit = `ZERO_ONE;
+    end
+    else
+  begin
+      JBit = `ZERO_ONE;
+      KBit = `ONE_ZERO;
+    end
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.v	(revision 264)
@@ -0,0 +1,498 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processRxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   processRxDataInWEn;
+input   rst;
+input   [7:0]RxByteIn;
+input   [7:0]RxCtrlIn;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processRxByteRdy;
+output  rstCRC;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+output  RxDataOutWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+reg     processRxByteRdy, next_processRxByteRdy;
+wire    processRxDataInWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]RxByteIn;
+wire    [7:0]RxCtrlIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+reg     RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RxByte, next_RxByte;
+reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg  [7:0]RxCtrl, next_RxCtrl;
+reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg  [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+  NextState_prRxByte <= CurrState_prRxByte;
+  // Set default values for outputs and signals
+  next_RxByte <= RxByte;
+  next_RxCtrl <= RxCtrl;
+  next_RXByteStMachCurrState <= RXByteStMachCurrState;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RxOverflow <= RxOverflow;
+  next_RxTimeOut <= RxTimeOut;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_RxDataOut <= RxDataOut;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOutWEn <= RxDataOutWEn;
+  next_rstCRC <= rstCRC;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_RXDataByteCnt <= RXDataByteCnt;
+  next_processRxByteRdy <= processRxByteRdy;
+  case (CurrState_prRxByte)  // synopsys parallel_case full_case
+    `CHK_ST:
+    begin
+      if (RXByteStMachCurrState == `HS_BYTE_ST)
+      begin
+        NextState_prRxByte <= `HSHAKE_CHK;
+      end
+      else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+      begin
+        NextState_prRxByte <= `TOKEN_WAIT_CRC;
+      end
+      else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+      begin
+        NextState_prRxByte <= `DATA_WAIT_CRC;
+      end
+      else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+      begin
+        NextState_prRxByte <= `IDLE_CHK_START;
+      end
+      else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+      begin
+        NextState_prRxByte <= `CHK_SYNC_DO;
+      end
+      else if (RXByteStMachCurrState == `CHECK_PID_ST)
+      begin
+        NextState_prRxByte <= `CHK_PID_DO_CHK;
+      end
+    end
+    `START_PRBY:
+    begin
+      next_RxByte <= 8'h00;
+      next_RxCtrl <= 8'h00;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RxOverflow <= 1'b0;
+      next_RxTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_RxDataOut <= 8'h00;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOutWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_RXDataByteCnt <= 10'h00;
+      next_processRxByteRdy <= 1'b1;
+      NextState_prRxByte <= `WAIT_BYTE;
+    end
+    `WAIT_BYTE:
+    begin
+      if (processRxDataInWEn == 1'b1)
+      begin
+        NextState_prRxByte <= `CHK_ST;
+        next_RxByte <= RxByteIn;
+        next_RxCtrl <= RxCtrlIn;
+        next_processRxByteRdy <= 1'b0;
+      end
+    end
+    `HSHAKE_FIN:
+    begin
+      next_RxDataOutWEn <= 1'b0;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `HSHAKE_CHK:
+    begin
+      NextState_prRxByte <= `HSHAKE_FIN;
+      if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RxDataOutWEn <= 1'b1;
+    end
+    `CHK_PID_DO_CHK:
+    begin
+      if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+      begin
+        NextState_prRxByte <= `WAIT_BYTE;
+        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+        next_processRxByteRdy <= 1'b1;
+      end
+      else
+      begin
+        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+        next_CRCError <= 1'b0;
+        next_bitStuffError <= 1'b0;
+        next_RxOverflow <= 1'b0;
+        next_NAKRxed <= 1'b0;
+        next_stallRxed <= 1'b0;
+        next_ACKRxed <= 1'b0;
+        next_dataSequence <= 1'b0;
+        next_RxTimeOut <= 1'b0;
+        next_RXDataByteCnt <= 0;
+        next_RxDataOut <= RxByte;
+        next_RxCtrlOut <= `RX_PACKET_START;
+        next_RxDataOutWEn <= 1'b1;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `CHK_PID_FIRST_BYTE_PROC:
+    begin
+      next_rstCRC <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      case (RxByte[1:0] )
+      `SPECIAL:                              //Special PID.
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      `TOKEN:                                //Token PID
+      begin
+      next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      `HANDSHAKE:                            //Handshake PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_ACKRxed <= 1'b1;
+      2'b10:
+      next_NAKRxed <= 1'b1;
+      2'b11:
+      next_stallRxed <= 1'b1;
+      default:
+      begin
+      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+      end
+      endcase
+      next_RXByteStMachCurrState <= `HS_BYTE_ST;
+      end
+      `DATA:                                  //Data PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_dataSequence <= 1'b0;
+      2'b10:
+      next_dataSequence <= 1'b1;
+      default:
+      $display ("Invalid DATA PID detected in ProcessRXByte\n");
+      endcase
+      next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      endcase
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_FIN:
+    begin
+      next_CRC16En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC16Result != 16'hb001)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC16En <= 1'b1;
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `DATA_FIN;
+    end
+    `DATA_WAIT_CRC:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `DATA_CHK_STRM;
+      end
+    end
+    `TOKEN_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC5Result != 5'h6)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      if (RXDataByteCnt > 10'h2)
+      begin
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      else
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      end
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `TOKEN_FIN;
+    end
+    `TOKEN_FIN:
+    begin
+      next_CRC5En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `TOKEN_WAIT_CRC:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `TOKEN_CHK_STRM;
+      end
+    end
+    `CHK_SYNC_DO:
+    begin
+      if (RxByte == `SYNC_BYTE)
+      next_RXByteStMachCurrState <= `CHECK_PID_ST;
+      else
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `IDLE_CHK_START:
+    begin
+      if (RxCtrl == `DATA_START)
+      next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxByte <= `START_PRBY;
+  else
+    CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RxDataOut <= 8'h00;
+    RxCtrlOut <= 8'h00;
+    RxDataOutWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    processRxByteRdy <= 1'b1;
+    RxByte <= 8'h00;
+    RxCtrl <= 8'h00;
+    RXByteStMachCurrState <= `IDLE_BYTE_ST;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RxOverflow <= 1'b0;
+    RxTimeOut <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    RXDataByteCnt <= 10'h00;
+  end
+  else 
+  begin
+    RxDataOut <= next_RxDataOut;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOutWEn <= next_RxDataOutWEn;
+    rstCRC <= next_rstCRC;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    processRxByteRdy <= next_processRxByteRdy;
+    RxByte <= next_RxByte;
+    RxCtrl <= next_RxCtrl;
+    RXByteStMachCurrState <= next_RXByteStMachCurrState;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RxOverflow <= next_RxOverflow;
+    RxTimeOut <= next_RxTimeOut;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    RXDataByteCnt <= next_RXDataByteCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.asf	(revision 264)
@@ -0,0 +1,251 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIEReceiver\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `LOW_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
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+W 183 81 0 174 177 BEZIER "Transitions" | 85690,168888 83487,163706 122612,52505 134843,35774
+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+I 177 81 0 Builtin Exit | 137732,35774
+I 176 81 0 Builtin Entry | 63784,203320
+W 204 99 0 201 199 BEZIER "Transitions" | 75683,156094 76364,148603 119799,31977 120480,24486
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/8/"
+S 201 99 61440 ELLIPSE "States" | 75367,162586 6500 6500
+I 200 99 0 Builtin Entry | 53777,190526
+I 199 99 0 Builtin Exit | 120480,22566
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+W 194 90 0 185 188 BEZIER "Transitions" | 81878,164123 82559,156632 125787,39592 126468,32101
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 209 0 130 Builtin InPort | 77032,244882 "" ""
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+I 215 0 130 Builtin Signal | 20439,258880 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 219 0 130 Builtin Signal | 20132,253454 "" ""
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+I 238 236 0 Builtin Exit | 129540,111760
+I 237 236 0 Builtin Entry | 86360,167640
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 235 6 65556 ELLIPSE "Junction" | 170150,96140 3500 3500
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;"
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+I 233 0 130 Builtin Signal | 19714,243194 "" ""
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+I 244 242 0 Builtin Exit | 129540,111760
+I 243 242 0 Builtin Entry | 86360,167640
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 241 6 69652 ELLIPSE "Junction" | 55410,156008 3500 3500
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+A 252 204 16 TEXT "Actions" | 71150,119778 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend"
+A 255 194 16 TEXT "Actions" | 77086,121516 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+A 258 183 16 TEXT "Actions" | 76648,132819 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+A 259 169 16 TEXT "Actions" | 77229,121214 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.asf	(revision 264)
@@ -0,0 +1,146 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=161
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketcheckpreamble\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 32
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 158 37 BEZIER "Transitions" | 116216,34379 122135,26559 180161,53114 186081,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 70466,115662 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 156 60 BEZIER "Transitions" | 58983,118146 59059,114780 91699,99435 91452,95786
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88319,164339 88052,159633
+S 55 33 20480 ELLIPSE "States" | 88319,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88319,153150 1 0 0 "PREAM_SENT\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "PID_SENT\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+C 73 39 0 TEXT "Conditions" | 145852,37243 1 0 0 "sendPacketRdy == 1'b1"
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+                                        94907,51569 61918,50756 52575,52503 43232,54250\
+                                        38843,62050 37706,72734 36569,83418 36406,118357\
+                                        40062,129609 43718,140862 58507,150938 67687,153172\
+                                        76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 34428,222262 "" ""
+L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;"
+A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;"
+L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/"
+S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500
+L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/"
+S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500
+W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011
+W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.asf	(revision 264)
@@ -0,0 +1,110 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=95
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// softransmit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+F 6 0 671089152 54 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+                                     119442,151760 119430,151725 119430,151571
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+I 16 6 0 Builtin Reset | 76112,190530
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;\ni <= 8'h00;"
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+A 76 75 16 TEXT "Actions" | 55404,31002 1 0 0 "i <= 8'h00;"
+W 75 6 0 26 74 BEZIER "Transitions" | 117387,14280 106719,14616 86172,13920 78234,17868\
+                                      70296,21816 59880,36936 57948,44622 56016,52308\
+                                      59778,66554 61122,74366
+S 74 6 20480 ELLIPSE "States" | 63408,80448 6500 6500
+L 73 74 0 TEXT "State Labels" | 63408,80448 1 0 0 "DLY_SOF_CHK1\n/5/"
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+                                         105450,47318 105450,38252 107207,34228 108965,30205\
+                                         115846,23167 119361,19652
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+L 78 79 0 TEXT "State Labels" | 54655,123733 1 0 0 "DLY_SOF_CHK2\n/6/"
+S 79 6 24576 ELLIPSE "States" | 54655,123733 6500 6500
+W 82 6 0 74 79 BEZIER "Transitions" | 61272,86583 60002,89345 56169,113512 55585,117302
+C 85 75 0 TEXT "Conditions" | 66368,14007 1 0 0 "sendPacketRdy == 1'b1"
+L 86 87 0 TEXT "Labels" | 50362,241979 1 0 0 "i[7:0]"
+I 87 0 130 Builtin Signal | 47362,241979 "" ""
+A 88 74 4 TEXT "Actions" | 81838,80970 1 0 0 "i <= i + 1'b1;"
+C 90 82 0 TEXT "Conditions" | 61793,96219 1 0 0 "i==8'hff"
+A 91 82 16 TEXT "Actions" | 49949,109037 1 0 0 "sendPacketArbiterReq <= 1'b0;\ni <= 8'h00;"
+W 92 6 0 79 11 BEZIER "Transitions" | 60486,126602 74574,130193 99716,139754 113804,143345
+A 93 79 4 TEXT "Actions" | 72777,123623 1 0 0 "i <= i + 1'b1;"
+C 94 92 0 TEXT "Conditions" | 68357,136883 1 0 0 "i==8'hff"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMux.v	(revision 264)
@@ -0,0 +1,168 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module hostSlaveMux (
+  SIEPortCtrlInToSIE,
+  SIEPortCtrlInFromHost,
+  SIEPortCtrlInFromSlave,
+  SIEPortDataInToSIE, 
+  SIEPortDataInFromHost, 
+  SIEPortDataInFromSlave, 
+  SIEPortWEnToSIE, 
+  SIEPortWEnFromHost, 
+  SIEPortWEnFromSlave, 
+  fullSpeedPolarityToSIE,
+  fullSpeedPolarityFromHost,
+  fullSpeedPolarityFromSlave,
+  fullSpeedBitRateToSIE,
+  fullSpeedBitRateFromHost,
+  fullSpeedBitRateFromSlave,
+  dataIn, 
+  dataOut,
+  address,
+  writeEn,
+  strobe_i,
+  clk, 
+  rst,
+  hostSlaveMuxSel  );
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE; 
+input [7:0] SIEPortDataInFromHost; 
+input [7:0] SIEPortDataInFromSlave; 
+output SIEPortWEnToSIE; 
+input SIEPortWEnFromHost; 
+input SIEPortWEnFromSlave; 
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE; 
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+reg SIEPortWEnToSIE; 
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+  SIEPortCtrlInFromHost or
+  SIEPortCtrlInFromSlave or
+  SIEPortDataInFromHost or 
+  SIEPortDataInFromSlave or 
+  SIEPortWEnFromHost or 
+  SIEPortWEnFromSlave or 
+  fullSpeedPolarityFromHost or
+  fullSpeedPolarityFromSlave or
+  fullSpeedBitRateFromHost or
+  fullSpeedBitRateFromSlave)
+begin
+  if (hostMode == 1'b1) 
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+    SIEPortDataInToSIE <=  SIEPortDataInFromHost;
+    SIEPortWEnToSIE <= SIEPortWEnFromHost;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+  end
+  else
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+    SIEPortDataInToSIE <=  SIEPortDataInFromSlave;
+    SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+  end
+end      
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(dataIn), 
+  .dataOut(dataOut),
+  .address(address),
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .hostMode(hostMode), 
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostSlave_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostSlave_h.v	(revision 264)
@@ -0,0 +1,28 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+//             control reads and writes to USB flash dongle
+// Version 7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect 
+//             time outs, added low speed EOP keep alive. The TX bit rate is now controlled by 
+//             SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+//             speed, and TX resume is always low speed.
+//             Fixed read clock recovery (readUSBWireData.v) issue which was resulting 
+//             in missing receive packets.
+//             Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+//             by adding kludged delay to softranmit. This needs to be fixed properly.
+//             This version has undergone limited testing
+//             with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+`define USBHOSTSLAVE_VERSION_NUM 8'h07
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/include/usbHostSlave_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf	(revision 264)
@@ -0,0 +1,638 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=1083
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIETransmitter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
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+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
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+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/10/"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+I 572 458 0 Builtin Entry | 44780,253519
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+W 574 458 0 567 540 BEZIER "Transitions" | 44528,153207 48588,141781 61374,54759 65434,43333
+A 835 9 4 TEXT "Actions" | 153876,207727 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 3'h0;\nresumeCnt <= 16'h0000;\nTxByteOutFullSpeedRate <= 1'b0;\nUSBWireFullSpeedRate <= 1'b0;"
+L 848 847 0 TEXT "Labels" | 130599,219647 1 0 0 "JBit[1:0]"
+L 319 320 0 TEXT "Labels" | 133337,226207 1 0 0 "fullSpeedRateIn"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 606 489 0 Builtin Exit | 101068,51939
+I 599 489 0 Builtin Entry | 29952,254306
+I 324 0 130 Builtin InPort | 126267,235982 "" ""
+L 323 324 0 TEXT "Labels" | 132267,235982 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin InPort | 127337,226207 "" ""
+S 63 6 0 ELLIPSE "States" | 138700,177505 6500 6500
+L 62 63 0 TEXT "State Labels" | 139687,176678 1 0 0 "STX_WAIT_BYTE\n/20/"
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+                                      42326,129670 44202,125650 52711,124511 61220,123372\
+                                      92777,123293 108857,123025
+I 872 360 0 Builtin Exit | 188676,86316
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 77071,148182 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 74766,198892 6500 6500
+L 608 609 0 TEXT "State Labels" | 74766,198892 1 0 0 "PID"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+                                        161730,108850 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 144540,155815\
+                                        141750,161305 138960,166795 141442,165439 137520,171118
+A 78 65 16 TEXT "Actions" | 53177,187164 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;\nTxByteOutFullSpeedRate <= fullSpeedRateIn;\nUSBWireFullSpeedRate <= fullSpeedRateIn;"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+C 66 65 0 TEXT "Conditions" | 70342,165567 1 0 0 "SIEPortWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 132240,176792 119927,171164 59299,174571 47927,176730
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/0/"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 3'h7"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 636 610 0 Builtin Entry | 71380,236621
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 634 626 0 TEXT "State Labels" | 75688,89174 1 0 0 "CRC"
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 75688,89174 6500 6500
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 77071,148182 1 0 0 "BYTE1"
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 80182,200322 122622,188930 134753,182668
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 363 360 0 Builtin Entry | 26888,244668
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+                                        43361,99065 46384,95576 54928,94878 63472,94181\
+                                        94207,96080 109784,96428
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/38/"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/29/"
+I 908 224 0 Builtin Entry | 85162,237767
+I 909 224 0 Builtin Exit | 108872,88817
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+I 914 912 0 Builtin Exit | 129540,111760
+I 913 912 0 Builtin Entry | 86360,167640
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/22/"
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+W 651 489 0 626 606 BEZIER "Transitions" | 78534,83332 83720,75495 93087,59776 98273,51939
+W 650 489 0 617 626 BEZIER "Transitions" | 76796,141693 76220,129592 76063,107757 75487,95656
+W 649 489 0 609 617 BEZIER "Transitions" | 74835,192396 75180,182600 76125,164449 76470,154653
+W 648 489 0 599 609 BEZIER "Transitions" | 33927,254306 41205,251054 71176,221478 73868,205326
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+I 645 610 0 Builtin Exit | 114540,97930
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/33/"
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 3'h0;"
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+S 939 633 8192 ELLIPSE "States" | 39277,179580 6500 6500
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/42/"
+I 671 624 0 Builtin Exit | 116402,43935
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+                                           104039,47385 110550,45085 113597,43935
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+I 663 624 0 Builtin Entry | 59190,254840
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/26/"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+W 956 360 0 363 1073 BEZIER "Transitions" | 30725,244668 34469,239130 89108,253575 97764,256633
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+S 952 624 16384 ELLIPSE "States" | 35474,185224 6500 6500
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/44/"
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+S 947 734 12288 ELLIPSE "States" | 160390,197270 6500 6500
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/43/"
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+I 682 633 0 Builtin Exit | 119917,39891
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/21/"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/36/"
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+A 414 413 16 TEXT "Actions" | 50560,239516 1 0 0 "USBWireReq <= 1'b1;\nresumeCnt  <= 16'h0000;\nUSBWireFullSpeedRate <= 1'b0; //resume always uses low speed timing"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/35/"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/1/"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;	\nresumeCnt  <= resumeCnt  + 1'b1;"
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+L 957 958 0 TEXT "State Labels" | 118124,69006 1 0 0 "TX_LS_EOP"
+S 958 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118124,67086 6500 6500
+W 959 6 0 11 958 BEZIER "Transitions" | 41589,169153 41990,145961 42609,100547 43291,87547\
+                                        43973,74547 45899,68928 54485,67524 63072,66120\
+                                        95424,66959 111633,66752
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/32/"
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/8/"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/25/"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "W_RDY1\n/24/"
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+I 418 17 0 Builtin Exit | 171923,20004
+I 417 17 0 Builtin Entry | 44586,243455
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/28/"
+W 425 17 1 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+C 426 425 0 TEXT "Conditions" | 62970,121537 1 0 0 "resumeCnt == `HOST_TX_RESUME_TIME"
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "SND_SE0_1\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 429 430 0 TEXT "State Labels" | 62301,61312 1 0 0 "SND_SE0_2\n/17/"
+S 430 17 0 ELLIPSE "States" | 62301,61312 6500 6500
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "SND_J_1\n/14/"
+C 960 959 0 TEXT "Conditions" | 51998,64924 1 0 0 "SIEPortCtrl == `TX_LS_KEEP_ALIVE"
+H 961 958 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 973 961 0 979 993 BEZIER "Transitions" | 70323,232853 70198,226566 70679,201498 70554,195211
+C 974 973 0 TEXT "Conditions" | 71910,232073 1 0 0 "USBWireGnt == 1'b1"
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+I 716 471 0 Builtin Entry | 83616,227615
+I 715 471 0 Builtin Exit | 140592,59380
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 713 480 0 Builtin Exit | 85376,122104
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 711 480 0 Builtin Entry | 43257,253243
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251031 41695,239812 59162,227406 68316,218108
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/7/"
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/30/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "SND_J_2\n/15/"
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+W 436 17 0 1026 430 BEZIER "Transitions" | 180912,80742 169329,74775 79549,70544 67972,64487
+W 437 17 0 1028 432 BEZIER "Transitions" | 51111,44834 62356,44473 153909,58971 165141,58620
+W 438 17 0 1030 434 BEZIER "Transitions" | 180827,34395 168542,28662 79732,38178 67447,32445
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+C 442 436 0 TEXT "Conditions" | 142323,77914 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 53546,46742 1 0 0 "USBWireRdy == 1'b1"
+C 444 438 0 TEXT "Conditions" | 151980,31125 1 0 0 "USBWireRdy == 1'b1"
+A 445 436 16 TEXT "Actions" | 93935,80043 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 94027,64120 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 447 438 16 TEXT "Actions" | 100527,44161 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 977 961 0 989 979 BEZIER "Transitions" | 59230,267637 62248,262230 65883,250383 66893,244725
+A 978 977 16 TEXT "Actions" | 61762,259858 1 0 0 "USBWireReq <= 1'b1;"
+S 979 961 24576 ELLIPSE "States" | 70526,239337 6500 6500
+S 982 961 28672 ELLIPSE "States" | 72541,157710 6500 6500
+L 983 982 0 TEXT "State Labels" | 72541,157710 1 0 0 "SND_SE0_2\n/46/"
+S 984 961 32768 ELLIPSE "States" | 180649,189534 6500 6500
+L 985 984 0 TEXT "State Labels" | 180649,189534 1 0 0 "SND_SE0_1\n/47/"
+L 988 979 0 TEXT "State Labels" | 70526,239337 1 0 0 "WAIT_GNT1\n/45/"
+I 989 961 0 Builtin Entry | 55468,267637
+I 990 961 0 Builtin Exit | 202744,115664
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/23/"
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 731 727 0 Builtin Entry | 71380,236621
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+A 448 432 4 TEXT "Actions" | 159702,69949 1 0 0 "USBWireWEn <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34545,73018 1 0 0 "USBWireWEn <= 1'b0;"
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 150428,26102 169066,20266
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/41/"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 993 961 36864 ELLIPSE "States" | 71111,188744 6500 6500
+L 994 993 0 TEXT "State Labels" | 71111,188744 1 0 0 "W_RDY1\n/48/"
+W 997 961 0 1018 1008 BEZIER "Transitions" | 102841,134185 114073,133834 169562,153024 180794,152673
+A 998 997 16 TEXT "Actions" | 129506,151946 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 999 961 0 1016 982 BEZIER "Transitions" | 191758,179211 180175,173244 89868,166719 78285,160752
+A 1000 999 16 TEXT "Actions" | 104380,176838 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1002 997 0 TEXT "Conditions" | 110626,136953 1 0 0 "USBWireRdy == 1'b1"
+C 1003 999 0 TEXT "Conditions" | 156382,176802 1 0 0 "USBWireRdy == 1'b1"
+A 1004 984 4 TEXT "Actions" | 165556,203106 1 0 0 "USBWireWEn <= 1'b0;"
+W 1005 961 0 993 984 BEZIER "Transitions" | 77608,188557 88723,188674 163036,189296 174151,189413
+A 1006 1005 16 TEXT "Actions" | 120336,197940 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1007 1005 0 TEXT "Conditions" | 80771,193665 1 0 0 "USBWireRdy == 1'b1"
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 750 734 0 Builtin Entry | 59190,254840
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+I 744 734 0 Builtin Exit | 116402,43935
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/6/"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/34/"
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 738 727 0 Builtin Exit | 114540,97930
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+S 1008 961 40960 ELLIPSE "States" | 187291,152508 6500 6500
+L 1009 1008 0 TEXT "State Labels" | 187291,152508 1 0 0 "SND_J\n/49/"
+W 1010 961 0 1008 990 BEZIER "Transitions" | 189673,146461 206752,122150 181346,115781 199949,115664
+A 1011 1008 4 TEXT "Actions" | 175523,169038 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 1012 982 4 TEXT "Actions" | 80404,154242 1 0 0 "USBWireWEn <= 1'b0;"
+W 1014 6 0 958 911 BEZIER "Transitions" | 124457,68547 133850,72702 151714,79462 161174,83437
+L 1015 1016 0 TEXT "State Labels" | 197328,182560 1 0 0 "W_RDY2\n/50/"
+S 1016 961 45056 ELLIPSE "States" | 197328,182560 6500 6500
+L 1017 1018 0 TEXT "State Labels" | 96400,133312 1 0 0 "W_RDY3\n/51/"
+S 1018 961 49152 ELLIPSE "States" | 96400,133312 6500 6500
+W 1019 961 0 984 1016 BEZIER "Transitions" | 186591,186901 188111,186673 190020,185744 191540,185516
+W 1020 961 0 982 1018 BEZIER "Transitions" | 76114,152281 80446,148557 87065,141183 91397,137459
+L 1021 1022 0 TEXT "State Labels" | 32738,152469 1 0 0 "DELAY\n/52/"
+S 1022 17 53248 ELLIPSE "States" | 32738,152469 6500 6500
+W 1023 17 2 407 1022 BEZIER "Transitions" | 52990,130254 48496,130815 40121,131043 37433,133209\
+                                            34745,135375 33783,142213 32901,145984
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+I 762 733 0 Builtin Exit | 119917,39891
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/27/"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+S 216 6 0 ELLIPSE "States" | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE\n/4/"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/2/"
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+W 1024 17 0 1022 411 BEZIER "Transitions" | 33384,158929 34668,162139 36269,168519 38877,170084\
+                                            41485,171649 49107,171706 53039,171626
+L 1025 1026 0 TEXT "State Labels" | 186818,83454 1 0 0 "W_RDY2\n/53/"
+S 1026 17 57344 ELLIPSE "States" | 186818,83454 6500 6500
+L 1027 1028 0 TEXT "State Labels" | 44615,44613 1 0 0 "W_RDY3\n/54/"
+S 1028 17 61440 ELLIPSE "States" | 44615,44613 6500 6500
+L 1029 1030 0 TEXT "State Labels" | 187139,35946 1 0 0 "W_RDY4\n/55/"
+S 1030 17 65536 ELLIPSE "States" | 187139,35946 6500 6500
+W 1031 17 0 428 1026 BEZIER "Transitions" | 175312,89747 176917,88865 179480,87397 181085,86515
+W 1032 17 0 430 1028 BEZIER "Transitions" | 56906,57687 55061,55440 50351,52066 48506,49819
+W 1033 17 0 432 1030 BEZIER "Transitions" | 175464,53250 177630,50201 181501,44488 183667,41439
+L 1034 1035 0 TEXT "State Labels" | 59060,143481 1 0 0 "DELAY\n/56/"
+S 1035 224 69632 ELLIPSE "States" | 59060,143481 6500 6500
+W 1036 224 2 891 1035 BEZIER "Transitions" | 101504,123089 91624,127529 74202,135226 64322,139666
+W 1037 224 0 1035 897 BEZIER "Transitions" | 64606,146870 74406,150350 91859,157715 101659,161195
+L 1038 1039 0 TEXT "Labels" | 74756,230822 1 0 0 "resumeCnt[15:0]"
+I 1039 0 130 Builtin Signal | 71756,230822 "" ""
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/40/"
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/37/"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/5/"
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+                                           46299,139871 48829,136075 59202,135063 69575,134052\
+                                           106314,125693 125795,125567
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+                                           46931,109511 49715,104703 60024,103501 70334,102300\
+                                           108774,103037 128002,103037
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+                                           48196,74723 50474,70169 60657,69030 70840,67892\
+                                           108432,68626 127660,68626
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+                                           48829,42592 51359,37532 61605,36267 71852,35002\
+                                           109061,35775 128289,35775
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+L 1040 1041 0 TEXT "Labels" | 70301,241139 1 0 0 "TxByteOutFullSpeedRate"
+I 1041 0 2 Builtin OutPort | 64301,241139 "" ""
+L 1042 1043 0 TEXT "Labels" | 27464,245142 1 0 0 "USBWireFullSpeedRate"
+I 1043 0 2 Builtin OutPort | 21464,245142 "" ""
+A 1046 451 16 TEXT "Actions" | 91713,26530 1 0 0 "USBWireFullSpeedRate <= fullSpeedRateIn;"
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+                                           128857,67252 162473,65260 171997,66691 181521,68123\
+                                           186003,75843 187123,97692 188244,119542 188244,199222\
+                                           184384,221196 180525,243170 165087,251388 155563,253628\
+                                           146039,255869 123379,256617 115100,254625 106821,252633\
+                                           98206,243956 92977,239599
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+                                              31250,150650 32250,89650 34750,72525 37250,55400\
+                                              46250,47900 56000,46150 65750,44400 95896,46012\
+                                              103573,44899 111250,43786 113107,43935 113607,43935
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/3/"
+I 787 733 0 Builtin Entry | 62705,250796
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+L 1071 1072 0 TEXT "Labels" | 130970,231188 1 0 0 "CRC16En"
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/39/"
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+I 540 458 0 Builtin Exit | 68103,43333
+I 1072 0 2 Builtin OutPort | 124970,231188 "" ""
+H 1075 1073 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 1073 360 73748 ELLIPSE "Junction" | 100383,254312 3500 3500
+L 1074 1073 0 TEXT "State Labels" | 100383,254312 1 0 0 "J3"
+I 1076 1075 0 Builtin Entry | 86360,167640
+I 1077 1075 0 Builtin Exit | 129540,111760
+W 1078 1075 0 1076 1077 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+W 1079 360 2 1073 453 BEZIER "Transitions" | 97595,252197 93012,236072 61888,222891 52340,220350
+W 1080 360 1 1073 453 BEZIER "Transitions" | 103127,252141 112392,249752 130361,224032 127627,220759\
+                                             124894,217487 107954,214253 97790,213829 87626,213406\
+                                             65074,215466 53216,216236
+C 1081 1080 0 TEXT "Conditions" | 102248,241873 1 0 0 "SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE"
+A 1082 1080 16 TEXT "Actions" | 95072,224240 1 0 0 "TxByteOutFullSpeedRate <= 1'b1; //SOF and PRE always at full speed"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.v	(revision 264)
@@ -0,0 +1,412 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processrxbit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive);
+input   clk;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processRxBitsWEn;
+input   processRxByteRdy;
+input   rst;
+input   [1:0]RxBitsIn;
+input   RxWireActive;
+output  processRxBitRdy;
+output  processRxByteWEn;
+output  resumeDetected;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+
+wire    clk;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processRxBitRdy, next_processRxBitRdy;
+wire    processRxBitsWEn;
+wire    processRxByteRdy;
+reg     processRxByteWEn, next_processRxByteWEn;
+reg     resumeDetected, next_resumeDetected;
+wire    rst;
+wire    [1:0]RxBitsIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+wire    RxWireActive;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg  [1:0]oldRXBits, next_oldRXBits;
+reg  [4:0]resumeWaitCnt, next_resumeWaitCnt;
+reg  [3:0]RXBitCount, next_RXBitCount;
+reg  [1:0]RxBits, next_RxBits;
+reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg  [7:0]RXByte, next_RXByte;
+reg  [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RxWireActive or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+  NextState_prRxBit <= CurrState_prRxBit;
+  // Set default values for outputs and signals
+  next_processRxByteWEn <= processRxByteWEn;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOut <= RxDataOut;
+  next_resumeDetected <= resumeDetected;
+  next_RXBitStMachCurrState <= RXBitStMachCurrState;
+  next_RxBits <= RxBits;
+  next_RXSameBitCount <= RXSameBitCount;
+  next_RXBitCount <= RXBitCount;
+  next_oldRXBits <= oldRXBits;
+  next_RXByte <= RXByte;
+  next_bitStuffError <= bitStuffError;
+  next_resumeWaitCnt <= resumeWaitCnt;
+  next_processRxBitRdy <= processRxBitRdy;
+  case (CurrState_prRxBit)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOut <= 8'h00;
+      next_resumeDetected <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_RxBits <= 2'b00;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h0;
+      next_oldRXBits <= 2'b00;
+      next_RXByte <= 8'h00;
+      next_bitStuffError <= 1'b0;
+      next_resumeWaitCnt <= 5'h0;
+      next_processRxBitRdy <= 1'b1;
+      NextState_prRxBit <= `WAIT_BITS;
+    end
+    `WAIT_BITS:
+    begin
+      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+      begin
+        NextState_prRxBit <= `DATA_RX_CHK_SE0;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+      begin
+        NextState_prRxBit <= `RES_RX_CHK;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+      begin
+        NextState_prRxBit <= `RES_END_CHK1;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+      begin
+        NextState_prRxBit <= `IDLE_CHK_KBIT;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+    end
+    `IDLE_FIRST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h1;
+      next_oldRXBits <= RxBits;
+      //zero is always the first RZ data bit of a new packet
+      next_RXByte <= 8'h00;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `IDLE_CHK_KBIT:
+    begin
+      if ((RxBits == KBit) && (RxWireActive == 1'b1))
+      begin
+        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `IDLE_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `IDLE_FIRST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_START;
+        //start of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_LAST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_CHK_SE0:
+    begin
+      next_bitStuffError <= 1'b0;
+      if (RxBits == `SE0)
+      begin
+        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
+        begin
+        next_RXSameBitCount <= RXSameBitCount + 1'b1;
+        //inc 'RXSameBitCount'
+        if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+        next_bitStuffError <= 1'b1;
+        //flag 'bitStuffError'
+        else                                          //else no bit stuffing error
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= { 1'b1, RXByte[7:1]};
+        //RZ bit <= 1 (ie no change in 'RxBits')
+        end
+        end
+        else                                            //else current 'RxBits' are different from old 'RxBits'
+        begin
+        if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != 4'h7) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= {1'b0, RXByte[7:1]};
+        //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+        end
+        next_RXSameBitCount <= 4'h0;
+        //reset 'RXSameBitCount'
+        end
+        next_oldRXBits <= RxBits;
+      end
+    end
+    `DATA_RX_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_LAST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_STOP;
+        //end of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_DATA_DESTUFF:
+    begin
+      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+      end
+      else if (bitStuffError == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `DATA_RX_BYTE_SEND2:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_BYTE_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+        next_RXBitCount <= 4'h0;
+        next_RxDataOut <= RXByte;
+        next_RxCtrlOut <= `DATA_STREAM;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_ERROR_CHK_RES:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      if (RxBits == JBit)                           //if current bit is a JBit, then
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      //next state is idle
+      else                                          //else
+      begin
+      next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+      //check for resume
+      next_resumeWaitCnt <= 5'h0;
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_ERROR_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `RES_RX_CHK:
+    begin
+      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      else
+      begin
+      next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+      //if we've waited long enough, then
+      if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
+      begin
+      next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+      next_resumeDetected <= 1'b1;
+      //report resume detected
+      end
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `RES_END_CHK1:
+    begin
+      if (RxBits != KBit)  //line must leave KBit state for the end of resume
+      begin
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_resumeDetected <= 1'b0;
+      //clear resume detected flag
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxBit <= `START;
+  else
+    CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processRxByteWEn <= 1'b0;
+    RxCtrlOut <= 8'h00;
+    RxDataOut <= 8'h00;
+    resumeDetected <= 1'b0;
+    processRxBitRdy <= 1'b1;
+    RXBitStMachCurrState <= `IDLE_BIT_ST;
+    RxBits <= 2'b00;
+    RXSameBitCount <= 4'h0;
+    RXBitCount <= 4'h0;
+    oldRXBits <= 2'b00;
+    RXByte <= 8'h00;
+    bitStuffError <= 1'b0;
+    resumeWaitCnt <= 5'h0;
+  end
+  else 
+  begin
+    processRxByteWEn <= next_processRxByteWEn;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOut <= next_RxDataOut;
+    resumeDetected <= next_resumeDetected;
+    processRxBitRdy <= next_processRxBitRdy;
+    RXBitStMachCurrState <= next_RXBitStMachCurrState;
+    RxBits <= next_RxBits;
+    RXSameBitCount <= next_RXSameBitCount;
+    RXBitCount <= next_RXBitCount;
+    oldRXBits <= next_oldRXBits;
+    RXByte <= next_RXByte;
+    bitStuffError <= next_bitStuffError;
+    resumeWaitCnt <= next_resumeWaitCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.v	(revision 264)
@@ -0,0 +1,481 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processTxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteWEn;
+input   rst;
+input   [7:0]TxByteCtrlIn;
+input   TxByteFullSpeedRateIn;
+input   [7:0]TxByteIn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  processTxByteRdy;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processTxByteRdy, next_processTxByteRdy;
+wire    processTxByteWEn;
+wire    rst;
+wire    [7:0]TxByteCtrlIn;
+wire    TxByteFullSpeedRateIn;
+wire    [7:0]TxByteIn;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [3:0]i, next_i;
+reg  [7:0]TxByte, next_TxByte;
+reg  [7:0]TxByteCtrl, next_TxByteCtrl;
+reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
+reg  [1:0]TXLineState, next_TXLineState;
+reg  [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+`define LS_START_W_RDY1 5'b10110
+`define LS_START_W_RDY2 5'b10111
+`define LS_START_W_RDY3 5'b11000
+`define STOP_W_RDY1 5'b11001
+`define STOP_W_RDY2 5'b11010
+`define STOP_W_RDY3 5'b11011
+`define STOP_W_RDY4 5'b11100
+
+reg [4:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)
+begin
+  NextState_prcTxB <= CurrState_prcTxB;
+  // Set default values for outputs and signals
+  next_processTxByteRdy <= processTxByteRdy;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_USBWireReq <= USBWireReq;
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_TxByte <= TxByte;
+  next_TxByteCtrl <= TxByteCtrl;
+  next_TXLineState <= TXLineState;
+  next_TXOneCount <= TXOneCount;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
+  case (CurrState_prcTxB)  // synopsys parallel_case full_case
+    `START_PTBY:
+    begin
+      next_processTxByteRdy <= 1'b0;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_i <= 4'h0;
+      next_TxByte <= 8'h00;
+      next_TxByteCtrl <= 8'h00;
+      next_TXLineState <= 2'b0;
+      next_TXOneCount <= 4'h0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      next_TxByteFullSpeedRate <= 1'b0;
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `PTBY_WAIT_EN:
+    begin
+      next_processTxByteRdy <= 1'b1;
+      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_GNT;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_TXOneCount <= 4'h0;
+        next_TXLineState <= JBit;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (processTxByteWEn == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_i <= 4'h0;
+      end
+    end
+    `PTBY_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_prcTxB <= `WAIT_RDY_WIRE;
+      end
+    end
+    `WAIT_RDY_WIRE:
+    begin
+      if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate  == 1'b0))
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE1;
+      end
+      else if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `WAIT_RDY_PKT;
+        //actively drive the first J bit
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `WAIT_RDY_PKT:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `SEND_BYTE_UPDATE_BYTE:
+    begin
+      next_i <= i + 1'b1;
+      next_TxByte <= {1'b0, TxByte[7:1] };
+      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
+      next_TXOneCount <= TXOneCount + 1'b1;
+      //increment 'TXOneCount'
+      else                                        //else this is a zero bit
+      begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      end
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+    end
+    `SEND_BYTE_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (TXOneCount == `MAX_CONSEC_SAME_BITS)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+      end
+      else if (i != 4'h8)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+      else
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+    end
+    `SEND_BYTE_BIT_STUFF:
+    begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+    end
+    `SEND_BYTE_WAIT_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (i == 4'h8)
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+      else
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+    end
+    `STOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY2;
+    end
+    `STOP_SND_SE0_1:
+    begin
+      NextState_prcTxB <= `STOP_W_RDY1;
+    end
+    `STOP_CHK:
+    begin
+      if (TxByteCtrl == `DATA_STOP)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_1;
+      end
+      else
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_EN;
+      end
+    end
+    `STOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY3;
+    end
+    `STOP_SND_IDLE:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY4;
+    end
+    `STOP_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      //release the wire
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `STOP_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_J;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_IDLE;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_W_RDY4:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_SND_IDLE3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY2;
+    end
+    `LS_START_SND_J1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY3;
+    end
+    `LS_START_SND_IDLE1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_SND_IDLE2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY1;
+    end
+    `LS_START_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `LS_START_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE3;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_J1;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_FIN;
+        //Drive the first JBit
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prcTxB <= `START_PTBY;
+  else
+    CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processTxByteRdy <= 1'b0;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    USBWireReq <= 1'b0;
+    USBWireWEn <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+    i <= 4'h0;
+    TxByte <= 8'h00;
+    TxByteCtrl <= 8'h00;
+    TXLineState <= 2'b0;
+    TXOneCount <= 4'h0;
+    TxByteFullSpeedRate <= 1'b0;
+  end
+  else 
+  begin
+    processTxByteRdy <= next_processTxByteRdy;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    USBWireReq <= next_USBWireReq;
+    USBWireWEn <= next_USBWireWEn;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+    i <= next_i;
+    TxByte <= next_TxByte;
+    TxByteCtrl <= next_TxByteCtrl;
+    TXLineState <= next_TXLineState;
+    TXOneCount <= next_TXOneCount;
+    TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC16.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC16.v	(revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC16.v                                                ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [15:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [15:0] CRCResult;
+reg    ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 16'hffff;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0)
+    begin
+      if (CRCEn == 1'b1) begin
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        ready <= 1'b0;
+    end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[15:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == 4'h7)
+      begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(revision 264)
@@ -0,0 +1,111 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=134
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// usbTxWireArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
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+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
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+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
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+A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
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+                                      189371,107780 182843,108050 176316,108321 158239,103840\
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+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n  USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or\nSIETxFSRate or prcTxByteFSRate)  \nbegin\n  if (muxSIENotPTXB  == 1'b1)  \n  begin\n    USBWireWEn <= SIETxWEn;\n    TxBits <= SIETxData;\n    TxCtl <= SIETxCtrl;\n    TxFSRate <= SIETxFSRate;\n  end\n  else\n  begin\n    USBWireWEn <= prcTxByteWEn;\n    TxBits <= prcTxByteData;\n    TxCtl <= prcTxByteCtrl;\n    TxFSRate <= prcTxByteFSRate;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
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+                                      89642,107471 97173,106158 104705,104845 116882,95874\
+                                      123371,91703
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+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
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+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 175137,200041 "" ""
+L 122 123 0 TEXT "Labels" | 181137,200041 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 175137,195652 "" ""
+L 120 121 0 TEXT "Labels" | 181137,195652 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 175137,191032 "" ""
+L 118 119 0 TEXT "Labels" | 181137,191032 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 140655,173329 "" ""
+L 116 117 0 TEXT "Labels" | 146655,173329 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 140655,168940 "" ""
+L 114 115 0 TEXT "Labels" | 146655,168940 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 140655,164089 "" ""
+L 112 113 0 TEXT "Labels" | 146655,164089 1 0 0 "SIETxData[1:0]"
+L 128 129 0 TEXT "Labels" | 146868,178208 1 0 0 "SIETxFSRate"
+I 129 0 2 Builtin InPort | 140868,178208 "" ""
+L 130 131 0 TEXT "Labels" | 181140,205088 1 0 0 "prcTxByteFSRate"
+I 131 0 2 Builtin InPort | 175140,205088 "" ""
+L 132 133 0 TEXT "Labels" | 148212,207440 1 0 0 "TxFSRate"
+I 133 0 2 Builtin OutPort | 142212,207440 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/endpMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/endpMux.v	(revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// endpMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSlaveControl_h.v" 
+
+module endpMux (
+  clk, 
+  rst,
+  currEndP,
+  NAKSent,
+  stallSent,
+  CRCError,
+  bitStuffError,
+  RxOverflow,
+  RxTimeOut,
+  dataSequence,
+  ACKRxed,
+  transType,
+  transTypeNAK,
+  endPControlReg,
+  clrEPRdy,
+  endPMuxErrorsWEn,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  endP0StatusReg,
+  endP1StatusReg,
+  endP2StatusReg,
+  endP3StatusReg,
+  endP0TransTypeReg,
+  endP1TransTypeReg,
+  endP2TransTypeReg,
+  endP3TransTypeReg,
+  endP0NAKTransTypeReg,
+  endP1NAKTransTypeReg,
+  endP2NAKTransTypeReg,
+  endP3NAKTransTypeReg,
+  clrEP0Rdy,
+  clrEP1Rdy,
+  clrEP2Rdy,
+  clrEP3Rdy);
+
+
+input clk; 
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [4:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [4:0] endP0ControlReg;
+input [4:0] endP1ControlReg;
+input [4:0] endP2ControlReg;
+input [4:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk; 
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [4:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      endPControlReg <= endP0ControlReg;
+      clrEP0Rdy <= clrEPRdy;
+    end
+    2'b01: begin
+      endPControlReg <= endP1ControlReg;
+      clrEP1Rdy <= clrEPRdy;
+    end
+    2'b10: begin
+      endPControlReg <= endP2ControlReg;
+      clrEP2Rdy <= clrEPRdy;
+    end
+    2'b11: begin
+      endPControlReg <= endP3ControlReg;
+      clrEP3Rdy <= clrEPRdy;
+    end
+  endcase  
+end      
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+  if (rst) begin
+    endP0NAKTransTypeReg <= 2'b00;
+    endP1NAKTransTypeReg <= 2'b00;
+    endP2NAKTransTypeReg <= 2'b00;
+    endP3NAKTransTypeReg <= 2'b00;
+    endP0TransTypeReg <= 2'b00;
+    endP1TransTypeReg <= 2'b00;
+    endP2TransTypeReg <= 2'b00;
+    endP3TransTypeReg <= 2'b00;
+    endP0StatusReg <= 4'h0;
+    endP1StatusReg <= 4'h0;
+    endP2StatusReg <= 4'h0;
+    endP3StatusReg <= 4'h0;
+  end
+  else begin
+    if (endPMuxErrorsWEn == 1'b1) begin
+      if (NAKSent == 1'b1) begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0NAKTransTypeReg <= transTypeNAK;
+            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; 
+          end
+          2'b01: begin
+            endP1NAKTransTypeReg <= transTypeNAK;
+            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; 
+          end
+          2'b10: begin
+            endP2NAKTransTypeReg <= transTypeNAK;
+            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; 
+          end
+          2'b11: begin
+            endP3NAKTransTypeReg <= transTypeNAK;
+            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; 
+          end
+        endcase
+      end
+      else begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0TransTypeReg <= transType;
+            endP0StatusReg <= endPStatusCombine; 
+          end
+          2'b01: begin
+            endP1TransTypeReg <= transType;
+            endP1StatusReg <= endPStatusCombine; 
+          end
+          2'b10: begin
+            endP2TransTypeReg <= transType;
+            endP2StatusReg <= endPStatusCombine; 
+          end
+          2'b11: begin
+            endP3TransTypeReg <= transType;
+            endP3StatusReg <= endPStatusCombine; 
+          end
+        endcase
+      end
+    end
+  end
+end
+        
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveDirectControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 78
+PAGE 12700,12700 215900,279400
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+END
+INSTHEADER 127
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
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+I 13 6 0 Builtin Reset | 48900,215400
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
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+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_SDC\n/0/"
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+I 179 0 130 Builtin InPort | 57352,247790 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(revision 264)
@@ -0,0 +1,391 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine.v                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSerialInterfaceEngine(
+  clk, rst,
+  //readUSBWireData
+  USBWireDataIn,
+  USBWireDataInTick,
+  //writeUSBWireData
+  USBWireDataOut,
+  USBWireCtrlOut,
+  USBWireDataOutTick,
+  //SIEReceiver
+  connectState,
+  //processRxBit
+  resumeDetected,
+  //processRxByte
+  RxCtrlOut, 
+  RxDataOutWEn, 
+  RxDataOut, 
+    //SIETransmitter
+  SIEPortCtrlIn,
+  SIEPortDataIn, 
+  SIEPortTxRdy, 
+  SIEPortWEn, 
+    //lineControlUpdate
+  fullSpeedPolarity,
+  fullSpeedBitRate,
+  noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut; 
+output RxDataOutWEn; 
+output [7:0] RxDataOut; 
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy; 
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut; 
+wire RxDataOutWEn; 
+wire [7:0] RxDataOut; 
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy; 
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En; 
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En; 
+wire [4:0] RxCRC5Result; 
+wire RxCRC5_8Bit; 
+wire [7:0] RxCRCData; 
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En; 
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En; 
+wire [4:0] TxCRC5Result; 
+wire TxCRC5_8Bit; 
+wire [7:0] TxCRCData; 
+wire TxRstCRC; 
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy; 
+wire processTxByteWEn; 
+
+wire SIEFsRate;
+wire TxFSRateFromSIETxToPrcTxByte;
+wire prcTxByteFSRate;
+wire FSRateFromArbiterToWire;
+
+wire RxWireActive;
+
+lineControlUpdate u_lineControlUpdate
+  (.fullSpeedPolarity(fullSpeedPolarity),
+  .fullSpeedBitRate(fullSpeedBitRate),
+  .JBit(JBit),
+  .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+  (
+  .RxWireDataIn(RxWireDataFromWireRx), 
+  .RxWireDataWEn(RxWireDataWEn), 
+  .clk(clk),
+  .connectState(connectState),
+  .rst(rst) );
+
+  
+processRxBit u_processRxBit
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .RxBitsIn(RxWireDataFromWireRx), 
+  .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxDataOut(RxDataFromPrcRxBitToPrcRxByte), 
+  .clk(clk), 
+  .processRxBitRdy(processRxBitRdy), 
+  .processRxBitsWEn(RxWireDataWEn), 
+  .processRxByteWEn(processRxByteWEn), 
+  .resumeDetected(resumeDetected), 
+  .rst(rst),
+  .processRxByteRdy(processRxByteRdy),
+  .RxWireActive(RxWireActive)
+  );
+  
+processRxByte u_processRxByte
+  (.CRC16En(RxCRC16En), 
+  .CRC16Result(RxCRC16Result), 
+  .CRC16UpdateRdy(RxCRC16UpdateRdy),
+  .CRC5En(RxCRC5En), 
+  .CRC5Result(RxCRC5Result), 
+  .CRC5_8Bit(RxCRC5_8Bit),
+  .CRC5UpdateRdy(RxCRC5UpdateRdy),
+  .CRCData(RxCRCData), 
+  .RxByteIn(RxDataFromPrcRxBitToPrcRxByte), 
+  .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataOut), 
+  .clk(clk), 
+  .processRxDataInWEn(processRxByteWEn), 
+  .rst(rst), 
+  .rstCRC(RxRstCRC),
+  .processRxByteRdy(processRxByteRdy) ); 
+  
+  
+updateCRC5 RxUpdateCRC5
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC5Result), 
+  .CRCEn(RxCRC5En), 
+  .CRC5_8BitIn(RxCRC5_8Bit), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 RxUpdateCRC16
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC16Result), 
+  .CRCEn(RxCRC16En), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+SIETransmitter u_SIETransmitter
+  (.CRC16En(TxCRC16En), 
+  .CRC16Result(TxCRC16Result), 
+  .CRC5En(TxCRC5En), 
+  .CRC5Result(TxCRC5Result), 
+  .CRC5_8Bit(TxCRC5_8Bit), 
+  .CRCData(TxCRCData),
+  .CRC5UpdateRdy(TxCRC5UpdateRdy),
+  .CRC16UpdateRdy(TxCRC16UpdateRdy),
+  .JBit(JBit), 
+  .KBit(KBit), 
+  .SIEPortCtrlIn(SIEPortCtrlIn),
+  .SIEPortDataIn(SIEPortDataIn), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEn), 
+  .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteOut(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(SIETxCtrl), 
+  .USBWireData(SIETxData), 
+  .USBWireGnt(SIETxGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(SIETxReq), 
+  .USBWireWEn(SIETxWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst), 
+  .rstCRC(TxRstCRC),
+  .USBWireFullSpeedRate(SIEFsRate),
+  .TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
+  .fullSpeedRateIn(fullSpeedBitRate)
+  );    
+
+updateCRC5 TxUpdateCRC5
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC5Result), 
+  .CRCEn(TxCRC5En), 
+  .CRC5_8BitIn(TxCRC5_8Bit), 
+  .dataIn(TxCRCData),
+  .ready(TxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 TxUpdateCRC16
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC16Result), 
+  .CRCEn(TxCRC16En), 
+  .dataIn(TxCRCData), 
+  .ready(TxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+
+processTxByte u_processTxByte
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteIn(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(prcTxByteCtrl), 
+  .USBWireData(prcTxByteData), 
+  .USBWireGnt(prcTxByteGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(prcTxByteReq), 
+  .USBWireWEn(prcTxByteWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst),
+  .USBWireFullSpeedRate(prcTxByteFSRate),
+  .TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
+  ); 
+  
+USBTxWireArbiter u_USBTxWireArbiter
+  (.SIETxCtrl(SIETxCtrl), 
+  .SIETxData(SIETxData), 
+  .SIETxGnt(SIETxGnt), 
+  .SIETxReq(SIETxReq), 
+  .SIETxWEn(SIETxWEn), 
+  .TxBits(TxBitsFromArbToWire), 
+  .TxCtl(TxCtrlFromArbToWire), 
+  .USBWireRdyIn(USBWireRdy), 
+  .USBWireRdyOut(USBWireReadyFromTxArb), 
+  .USBWireWEn(USBWireWEn),
+  .clk(clk), 
+  .prcTxByteCtrl(prcTxByteCtrl), 
+  .prcTxByteData(prcTxByteData), 
+  .prcTxByteGnt(prcTxByteGnt), 
+  .prcTxByteReq(prcTxByteReq), 
+  .prcTxByteWEn(prcTxByteWEn), 
+  .rst(rst),
+  .SIETxFSRate(SIEFsRate),
+  .prcTxByteFSRate(prcTxByteFSRate),
+  .TxFSRate(FSRateFromArbiterToWire)
+  ); 
+  
+writeUSBWireData u_writeUSBWireData
+  (.TxBitsIn(TxBitsFromArbToWire), 
+  .TxBitsOut(USBWireDataOut), 
+  .TxDataOutTick(USBWireDataOutTick),
+  .TxCtrlIn(TxCtrlFromArbToWire), 
+  .TxCtrlOut(USBWireCtrlOut), 
+  .USBWireRdy(USBWireRdy), 
+  .USBWireWEn(USBWireWEn),
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .fullSpeedRate(FSRateFromArbiterToWire), 
+  .clk(clk),
+  .rst(rst)
+   );  
+
+  
+  
+readUSBWireData u_readUSBWireData
+  (.RxBitsIn(USBWireDataIn), 
+  .RxDataInTick(USBWireDataInTick),
+  .RxBitsOut(RxWireDataFromWireRx), 
+  .SIERxRdyIn(processRxBitRdy), 
+  .SIERxWEn(RxWireDataWEn), 
+  .fullSpeedRate(fullSpeedBitRate), 
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .clk(clk),
+  .rst(rst),
+  .noActivityTimeOut(noActivityTimeOut),
+  .RxWireActive(RxWireActive)
+  );
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/USBSlaveControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/USBSlaveControlBI.v	(revision 264)
@@ -0,0 +1,438 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBSlaveControlBI.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////       
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbSlaveControl_h.v"
+ 
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+  SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+  endP0TransTypeReg, endP0NAKTransTypeReg,
+  endP1TransTypeReg, endP1NAKTransTypeReg,
+  endP2TransTypeReg, endP2NAKTransTypeReg,
+  endP3TransTypeReg, endP3NAKTransTypeReg,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  EP0StatusReg,
+  EP1StatusReg,
+  EP2StatusReg,
+  EP3StatusReg,
+  SCAddrReg, frameNum,
+  connectStateIn,
+  SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+  slaveControlSelect,
+  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  SCGlobalEn
+  );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg; 
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg; 
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg; 
+input [1:0] endP3NAKTransTypeReg;
+output [4:0] endP0ControlReg;
+output [4:0] endP1ControlReg;
+output [4:0] endP2ControlReg;
+output [4:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg; 
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg; 
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg; 
+wire [1:0] endP3NAKTransTypeReg;
+reg [4:0] endP0ControlReg;
+reg [4:0] endP1ControlReg;
+reg [4:0] endP2ControlReg;
+reg [4:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0IsoEn;
+reg EP1IsoEn;
+reg EP2IsoEn;
+reg EP3IsoEn;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+
+//sync write demux
+always @(posedge clk)
+begin   
+  if (rst == 1'b1) begin
+    EP0IsoEn <= 1'b0;
+    EP0SendStall <= 1'b0;
+    EP0DataSequence <= 1'b0;
+    EP0Enable <= 1'b0;
+    EP1IsoEn <= 1'b0;
+    EP1SendStall <= 1'b0;
+    EP1DataSequence <= 1'b0;
+    EP1Enable <= 1'b0;
+    EP2IsoEn <= 1'b0;
+    EP2SendStall <= 1'b0;
+    EP2DataSequence <= 1'b0;
+    EP2Enable <= 1'b0;
+    EP3IsoEn <= 1'b0;
+    EP3SendStall <= 1'b0;
+    EP3DataSequence <= 1'b0;
+    EP3Enable <= 1'b0;
+    SCControlReg <= 6'h00;
+    SCAddrReg <= 7'h00;
+    interruptMaskReg <= 5'h00;
+  end
+  else begin
+    clrNAKReq <= 1'b0;
+    clrSOFReq <= 1'b0;
+    clrResetReq <= 1'b0;
+    clrResInReq <= 1'b0;
+    clrTransDoneReq <= 1'b0;
+    EP0SetReady <= 1'b0;
+    EP1SetReady <= 1'b0;
+    EP2SetReady <= 1'b0;
+    EP3SetReady <= 1'b0;
+    if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+    begin
+      case (address)
+        `EP0_CTRL_REG : begin
+          EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP1_CTRL_REG : begin
+          EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP2_CTRL_REG : begin
+          EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP3_CTRL_REG : begin
+          EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+        `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+        `SC_INTERRUPT_STATUS_REG : begin
+          clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
+          clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
+          clrResetReq <= dataIn[`RESET_EVENT_BIT];
+          clrResInReq <= dataIn[`RESUME_INT_BIT];
+          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+        end
+        `SC_INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[4:0];
+      endcase
+    end
+  end
+end
+
+//interrupt control 
+always @(posedge clk)
+begin
+  if (rst == 1'b1) begin
+    NAKSentInt <= 1'b0;
+    SOFRxedInt <= 1'b0;
+    resetEventInt <= 1'b0;
+    resumeInt <= 1'b0;
+    transDoneInt <= 1'b0;
+  end
+  else begin
+    if (NAKSentIn == 1'b1)
+      NAKSentInt <= 1'b1;
+    else if (clrNAKReq == 1'b1)
+      NAKSentInt <= 1'b0; 
+    
+    if (SOFRxedIn == 1'b1)
+      SOFRxedInt <= 1'b1;
+    else if (clrSOFReq == 1'b1)
+      SOFRxedInt <= 1'b0;
+    
+    if (resetEventIn == 1'b1)
+      resetEventInt <= 1'b1;
+    else if (clrResetReq == 1'b1)
+      resetEventInt <= 1'b0;
+    
+    if (resumeIntIn == 1'b1)
+      resumeInt <= 1'b1;
+    else if (clrResInReq == 1'b1)
+      resumeInt <= 1'b0;  
+
+    if (transDoneIn == 1'b1)
+      transDoneInt <= 1'b1;
+    else if (clrTransDoneReq == 1'b1)
+      transDoneInt <= 1'b0;
+  end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end  
+
+//end point ready, set/clear
+always @(posedge clk)
+begin
+  if (rst == 1'b1) begin
+    EP0Ready <= 1'b0;
+    EP1Ready <= 1'b0;
+    EP2Ready <= 1'b0;
+    EP3Ready <= 1'b0;
+  end
+  else begin
+    if (EP0SetReady == 1'b1)
+      EP0Ready <= 1'b1;
+    else if (clrEP0Ready == 1'b1)
+      EP0Ready <= 1'b0;
+    
+    if (EP1SetReady == 1'b1)
+      EP1Ready <= 1'b1;
+    else if (clrEP1Ready == 1'b1)
+      EP1Ready <= 1'b0;
+    
+    if (EP2SetReady == 1'b1)
+      EP2Ready <= 1'b1;
+    else if (clrEP2Ready == 1'b1)
+      EP2Ready <= 1'b0;
+    
+    if (EP3SetReady == 1'b1)
+      EP3Ready <= 1'b1;
+    else if (clrEP3Ready == 1'b1)
+      EP3Ready <= 1'b0;
+  end
+end  
+  
+//break out control signals
+always @(SCControlReg) begin
+  SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+  TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+  fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals 
+always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable) 
+begin
+  endP0ControlReg <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+  endP1ControlReg <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+  endP2ControlReg <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+  endP3ControlReg <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+      
+      
+      // async read mux
+always @(address or
+  EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+  EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
+  endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
+  endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or 
+  endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
+  SCControlReg or connectStateIn or
+  NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or SCAddrReg or frameNum)
+begin
+  case (address)
+      `EP0_CTRL_REG : dataOut <= endP0ControlReg;
+      `EP0_STS_REG : dataOut <= EP0StatusReg;
+      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
+      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
+      `EP1_CTRL_REG : dataOut <= endP1ControlReg;
+      `EP1_STS_REG :  dataOut <= EP1StatusReg;
+      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
+      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
+      `EP2_CTRL_REG : dataOut <= endP2ControlReg;
+      `EP2_STS_REG :  dataOut <= EP2StatusReg;
+      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
+      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
+      `EP3_CTRL_REG : dataOut <= endP3ControlReg;
+      `EP3_STS_REG :  dataOut <= EP3StatusReg;
+      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
+      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
+      `SC_CONTROL_REG : dataOut <= SCControlReg;
+      `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn}; 
+      `SC_INTERRUPT_STATUS_REG :  dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+      `SC_INTERRUPT_MASK_REG  : dataOut <= {3'b000, interruptMaskReg};
+      `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+      `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNum[10:8]};
+      `SC_FRAME_NUM_LSP : dataOut <= frameNum[7:0];
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.v	(revision 264)
@@ -0,0 +1,197 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SCTxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   SCTxPortRdyIn;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  directCntlGnt;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortRdyOut;
+output  SCTxPortWEnable;
+output  sendPacketGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortRdyIn;
+reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg     SCTxPortWEnable, next_SCTxPortWEnable;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+  NextState_SCTxArb <= CurrState_SCTxArb;
+  // Set default values for outputs and signals
+  next_sendPacketGnt <= sendPacketGnt;
+  next_muxDCEn <= muxDCEn;
+  next_directCntlGnt <= directCntlGnt;
+  case (CurrState_SCTxArb)  // synopsys parallel_case full_case
+    `SARB1_WAIT_REQ:
+    begin
+      if (sendPacketReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxDCEn <= 1'b0;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_DC;
+        next_directCntlGnt <= 1'b1;
+        next_muxDCEn <= 1'b1;
+      end
+    end
+    `SARB_SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `SARB_DC:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_SCTxArb <= `SARB1_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SCTxArb <= `START_SARB;
+  else
+    CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketGnt <= 1'b0;
+    directCntlGnt <= 1'b0;
+    muxDCEn <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketGnt <= next_sendPacketGnt;
+    directCntlGnt <= next_directCntlGnt;
+    muxDCEn <= next_muxDCEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.v	(revision 264)
@@ -0,0 +1,787 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIETransmitter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   fullSpeedRateIn;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteRdy;
+input   rst;
+input   [7:0]SIEPortCtrlIn;
+input   [7:0]SIEPortDataIn;
+input   SIEPortWEn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processTxByteWEn;
+output  rstCRC;
+output  SIEPortTxRdy;
+output  [7:0]TxByteOut;
+output  [7:0]TxByteOutCtrl;
+output  TxByteOutFullSpeedRate;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+wire    fullSpeedRateIn;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+wire    processTxByteRdy;
+reg     processTxByteWEn, next_processTxByteWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]SIEPortCtrlIn;
+wire    [7:0]SIEPortDataIn;
+reg     SIEPortTxRdy, next_SIEPortTxRdy;
+wire    SIEPortWEn;
+reg     [7:0]TxByteOut, next_TxByteOut;
+reg     [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg     TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [2:0]i, next_i;
+reg  [15:0]resumeCnt, next_resumeCnt;
+reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg  [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define DIR_CTL_CHK_FIN 6'b000000
+`define RES_ST_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
+`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
+`define PKT_ST_HS_PKT_SENT 6'b000111
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
+`define PKT_ST_SPCL_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_SND_J_1 6'b001110
+`define RES_ST_SND_J_2 6'b001111
+`define RES_ST_SND_SE0_1 6'b010000
+`define RES_ST_SND_SE0_2 6'b010001
+`define START_SIETX 6'b010010
+`define STX_CHK_ST 6'b010011
+`define STX_WAIT_BYTE 6'b010100
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
+`define RES_ST_W_RDY1 6'b011000
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
+`define RES_ST_WAIT_GNT 6'b011100
+`define DIR_CTL_WAIT_GNT 6'b011101
+`define PKT_ST_HS_WAIT_RDY 6'b011110
+`define PKT_ST_SPCL_WAIT_RDY 6'b011111
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
+`define RES_ST_WAIT_RDY 6'b100011
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
+`define DIR_CTL_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
+`define PKT_ST_WAIT_RDY_PKT 6'b101001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
+`define TX_LS_EOP_WAIT_GNT1 6'b101101
+`define TX_LS_EOP_SND_SE0_2 6'b101110
+`define TX_LS_EOP_SND_SE0_1 6'b101111
+`define TX_LS_EOP_W_RDY1 6'b110000
+`define TX_LS_EOP_SND_J 6'b110001
+`define TX_LS_EOP_W_RDY2 6'b110010
+`define TX_LS_EOP_W_RDY3 6'b110011
+`define RES_ST_DELAY 6'b110100
+`define RES_ST_W_RDY2 6'b110101
+`define RES_ST_W_RDY3 6'b110110
+`define RES_ST_W_RDY4 6'b110111
+`define DIR_CTL_DELAY 6'b111000
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)
+begin
+  NextState_SIETx <= CurrState_SIETx;
+  // Set default values for outputs and signals
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_USBWireReq <= USBWireReq;
+  next_processTxByteWEn <= processTxByteWEn;
+  next_rstCRC <= rstCRC;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  next_TxByteOut <= TxByteOut;
+  next_TxByteOutCtrl <= TxByteOutCtrl;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_SIEPortTxRdy <= SIEPortTxRdy;
+  next_SIEPortData <= SIEPortData;
+  next_SIEPortCtrl <= SIEPortCtrl;
+  next_resumeCnt <= resumeCnt;
+  next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
+  case (CurrState_SIETx)  // synopsys parallel_case full_case
+    `IDLE:
+    begin
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `START_SIETX:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_TxByteOut <= 8'h00;
+      next_TxByteOutCtrl <= 8'h00;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_SIEPortTxRdy <= 1'b0;
+      next_SIEPortData <= 8'h00;
+      next_SIEPortCtrl <= 8'h00;
+      next_i <= 3'h0;
+      next_resumeCnt <= 16'h0000;
+      next_TxByteOutFullSpeedRate <= 1'b0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `STX_CHK_ST:
+    begin
+      if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+        next_TxByteOutFullSpeedRate <= 1'b1;
+        //SOF and PRE always at full speed
+      end
+      else if (SIEPortCtrl == `TX_PACKET_START)
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+      end
+      else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_IDLE)
+      begin
+        NextState_SIETx <= `IDLE;
+      end
+      else if (SIEPortCtrl == `TX_RESUME_START)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+        next_resumeCnt <= 16'h0000;
+        next_USBWireFullSpeedRate <= 1'b0;
+        //resume always uses low speed timing
+      end
+    end
+    `STX_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `STX_CHK_ST;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+        next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
+        next_USBWireFullSpeedRate <= fullSpeedRateIn;
+      end
+    end
+    `DIR_CTL_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_i <= i + 1'b1;
+      if (i == 3'h7)
+      begin
+        NextState_SIETx <= `STX_WAIT_BYTE;
+        next_USBWireReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_SIETx <= `DIR_CTL_DELAY;
+      end
+    end
+    `DIR_CTL_WAIT_GNT:
+    begin
+      next_i <= 3'h0;
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+      end
+    end
+    `DIR_CTL_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_CHK_FIN;
+        next_USBWireData <= SIEPortData[1:0];
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `DIR_CTL_DELAY:
+    begin
+      NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+    end
+    `PKT_ST_CHK_PID:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      if (SIEPortData[1:0] == `TOKEN)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `HANDSHAKE)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `DATA)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `SPECIAL)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+      end
+    end
+    `PKT_ST_WAIT_RDY_PKT:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_CHK_PID;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= `SYNC_BYTE;
+        next_TxByteOutCtrl <= `DATA_START;
+      end
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT2:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY1:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[7:0];
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY2:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[15:8];
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_DATA_DATA_CHK_STOP:
+    begin
+      if (SIEPortCtrl == `TX_PACKET_STOP)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+      end
+    end
+    `PKT_ST_DATA_DATA_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_DATA_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC16En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+    end
+    `PKT_ST_DATA_DATA_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_RDY:
+    begin
+      next_CRC16En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+      end
+    end
+    `PKT_ST_DATA_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `PKT_ST_HS_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_HS_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_SPCL_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_SPCL_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_BYTE1_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_CRC_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_CRC_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+    end
+    `PKT_ST_TKN_CRC_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `RES_ST_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (resumeCnt == `HOST_TX_RESUME_TIME)
+      begin
+        NextState_SIETx <= `RES_ST_W_RDY1;
+      end
+      else
+      begin
+        NextState_SIETx <= `RES_ST_DELAY;
+      end
+    end
+    `RES_ST_SND_J_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY4;
+    end
+    `RES_ST_SND_J_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+      next_USBWireFullSpeedRate <= fullSpeedRateIn;
+    end
+    `RES_ST_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY2;
+    end
+    `RES_ST_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY3;
+    end
+    `RES_ST_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_RDY;
+      end
+    end
+    `RES_ST_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_CHK_FIN;
+        next_USBWireData <= KBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+        next_resumeCnt <= resumeCnt  + 1'b1;
+      end
+    end
+    `RES_ST_DELAY:
+    begin
+      NextState_SIETx <= `RES_ST_WAIT_RDY;
+    end
+    `RES_ST_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_W_RDY4:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_2;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `TX_LS_EOP_WAIT_GNT1:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_W_RDY1;
+      end
+    end
+    `TX_LS_EOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY3;
+    end
+    `TX_LS_EOP_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY2;
+    end
+    `TX_LS_EOP_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `TX_LS_EOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `TX_LS_EOP_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `TX_LS_EOP_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_J;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SIETx <= `START_SIETX;
+  else
+    CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    USBWireWEn <= 1'b0;
+    USBWireReq <= 1'b0;
+    processTxByteWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+    TxByteOut <= 8'h00;
+    TxByteOutCtrl <= 8'h00;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    SIEPortTxRdy <= 1'b0;
+    TxByteOutFullSpeedRate <= 1'b0;
+    i <= 3'h0;
+    SIEPortData <= 8'h00;
+    SIEPortCtrl <= 8'h00;
+    resumeCnt <= 16'h0000;
+  end
+  else 
+  begin
+    USBWireWEn <= next_USBWireWEn;
+    USBWireReq <= next_USBWireReq;
+    processTxByteWEn <= next_processTxByteWEn;
+    rstCRC <= next_rstCRC;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+    TxByteOut <= next_TxByteOut;
+    TxByteOutCtrl <= next_TxByteOutCtrl;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    SIEPortTxRdy <= next_SIEPortTxRdy;
+    TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
+    i <= next_i;
+    SIEPortData <= next_SIEPortData;
+    SIEPortCtrl <= next_SIEPortCtrl;
+    resumeCnt <= next_resumeCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.asf	(revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processRxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+I 20 17 0 Builtin Entry | 45216,248076
+I 21 17 0 Builtin Exit | 89220,92674
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+L 25 24 0 TEXT "State Labels" | 115892,94696 1 0 0 "HSHAKE"
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+L 299 300 0 TEXT "Labels" | 82848,255265 1 0 0 "RxCtrlOut[7:0]"
+I 300 0 130 Builtin OutPort | 76848,255265 "" ""
+L 301 302 0 TEXT "Labels" | 82139,250245 1 0 0 "RxDataOutWEn"
+I 302 0 2 Builtin OutPort | 76139,250245 "" ""
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+S 42 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118750,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 118750,36808 1 0 0 "DATA"
+I 304 0 130 Builtin InPort | 78462,243195 "" ""
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+I 306 0 130 Builtin InPort | 78465,238172 "" ""
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+C 55 51 0 TEXT "Conditions" | 43455,121392 1 0 0 "RXByteStMachCurrState == `CHECK_PID_ST"
+C 56 52 0 TEXT "Conditions" | 45596,90880 1 0 0 "RXByteStMachCurrState == `HS_BYTE_ST"
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+S 357 6 81940 ELLIPSE "Junction" | 165320,84870 3500 3500
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+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC5Result != 5'h6)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    if (RXDataByteCnt > 10'h2) \n    begin\n      RxOverflow <= 1'b1;\n      RxDataOut <= RxStatus;\n      RxCtrlOut <= `RX_PACKET_STOP;\n      RXByteStMachCurrState <= `IDLE_BYTE_ST;\n    end\n    else \n    begin\n      RxDataOut <= RxByte;\n      RxCtrlOut <= `RX_PACKET_STREAM;\n      CRCData <= RxByte;\n      CRC5_8Bit <= 1'b1;\n      CRC5En <= 1'b1;\n    end\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
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+I 221 217 0 Builtin Exit | 136710,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+I 227 224 0 Builtin Entry | 86360,167640
+I 228 224 0 Builtin Exit | 129540,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n  RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n  RXByteStMachCurrState = `IDLE_BYTE_ST;"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n  RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n  `SPECIAL:                              //Special PID.\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  `TOKEN:                                //Token PID\n  begin\n    RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\n  `HANDSHAKE:                            //Handshake PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        ACKRxed <= 1'b1;\n      2'b10:\n        NAKRxed <= 1'b1;\n      2'b11:\n        stallRxed <= 1'b1;\n      default:\n      begin\n        $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n      end\n    endcase\n    RXByteStMachCurrState <= `HS_BYTE_ST;\n  end\n  `DATA:                                  //Data PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        dataSequence <= 1'b0;\n      2'b10:\n        dataSequence <= 1'b1;\n      default:\n        $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n    endcase\n    RXByteStMachCurrState <= `DATA_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\nendcase"
+I 252 248 0 Builtin Entry | 35384,229000
+I 253 248 0 Builtin Exit | 78564,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+                                          110499,87996 110355,80840 110355,80474
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n  RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+I 260 32 0 Builtin Exit | 110355,78302
+I 259 32 0 Builtin Entry | 66351,233704
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+                                        89364,102368 89220,95212 89220,94846
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/readUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/readUSBWireData.v	(revision 264)
@@ -0,0 +1,227 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// readUSBWireData.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive);
+input   [1:0] RxBitsIn;
+output  RxDataInTick;
+input   SIERxRdyIn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+input   TxWireActiveDrive;
+output  [1:0] RxBitsOut;
+output  SIERxWEn;
+output noActivityTimeOut;
+output RxWireActive;
+
+wire   [1:0] RxBitsIn;
+reg    RxDataInTick;
+wire   SIERxRdyIn;
+wire   clk;
+wire   fullSpeedRate;
+wire   rst;
+reg    [1:0] RxBitsOut;
+reg    SIERxWEn;
+reg    noActivityTimeOut;
+reg    RxWireActive;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg  [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg RxWireEdgeDetect;
+reg RxWireActiveReg1;
+reg RxWireActiveReg2;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    RxDataInTick <= 1'b0;
+    RxWireEdgeDetect <= 1'b0;
+    RxWireActiveReg1 <= 1'b0;
+    RxWireActiveReg2 <= 1'b0;
+  end
+  else begin
+    RxWireActiveReg2 <= RxWireActiveReg1; //Delay RxWireActiveReg1 until after i has been reset
+    RxBitsInReg <= RxBitsIn;      //sync incoming data to local clock to avoid metastability issues
+    incBufferCnt <= 1'b0;         //default value
+    oldRxBitsIn <= RxBitsInReg;
+    if ( (TxWireActiveDrive == 1'b0) && (oldRxBitsIn != RxBitsInReg)) begin  //if edge detected then
+      i <= 5'b00000;              //reset the counter
+      RxWireEdgeDetect <= 1'b1;       // flag receive activity 
+      RxWireActiveReg1 <= 1'b1;
+    end
+    else begin
+      i <= i + 1'b1;
+      RxWireEdgeDetect <= 1'b0;
+    end
+    if (noActivityTimeOut == 1'b1)
+      RxWireActiveReg1 <= 1'b0;
+    if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+    begin
+      RxDataInTick <= !RxDataInTick;
+      if (TxWireActiveDrive != 1'b1)  //do not read wire data when transmitter is active
+      begin
+        incBufferCnt <= 1'b1;
+        bufferInIndex <= bufferInIndex + 1'b1;
+        case (bufferInIndex)
+          2'b00 : buffer0 <= {RxWireActiveReg2, RxBitsInReg}; 
+          2'b01 : buffer1 <= {RxWireActiveReg2, RxBitsInReg};
+          2'b10 : buffer2 <= {RxWireActiveReg2, RxBitsInReg};
+          2'b11 : buffer3 <= {RxWireActiveReg2, RxBitsInReg};
+        endcase
+      end
+    end
+  end
+end
+
+        
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    decBufferCnt <= 1'b0;
+    bufferOutIndex <= 2'b00;
+    RxBitsOut <= 2'b00;
+    SIERxWEn <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+  end
+  else begin
+    case (bufferOutStMachCurrState)
+      `WAIT_BUFFER_NOT_EMPTY:
+      begin
+        if (bufferCnt != 3'b000)
+          bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+      end
+      `WAIT_SIE_RX_READY:
+      begin
+        if (SIERxRdyIn == 1'b1)
+        begin 
+          SIERxWEn <= 1'b1;
+          bufferOutStMachCurrState <= `SIE_RX_WRITE;
+          decBufferCnt <= 1'b1;
+          bufferOutIndex <= bufferOutIndex + 1'b1;
+          case (bufferOutIndex)
+            2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
+            2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
+            2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
+            2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
+          endcase
+        end
+      end
+      `SIE_RX_WRITE:
+      begin
+        SIERxWEn <= 1'b0;
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+      end
+    endcase
+  end
+end
+
+//generate time out flag if no tx or rx activity
+always @(posedge clk) begin
+  if (rst) begin
+    timeOutCnt <= 16'h0000;
+    noActivityTimeOut <= 1'b0;
+  end
+  else begin
+    if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1)
+      timeOutCnt <= 16'h0000;
+    else 
+      timeOutCnt <= timeOutCnt + 1'b1;
+    if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+          || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
+      noActivityTimeOut <= 1'b1;
+    else 
+      noActivityTimeOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC5.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC5.v	(revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC5.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   CRC5_8BitIn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [4:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   CRC5_8BitIn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 5'h1f;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0) begin
+      if (CRCEn == 1'b1) begin
+        ready <= 1'b0;
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        if (CRC5_8BitIn == 1'b1) begin
+          loopEnd <= 4'h7; 
+        end
+        else begin
+          loopEnd <= 4'h2;
+        end
+      end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[4:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == loopEnd) begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v	(revision 264)
@@ -0,0 +1,281 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// writeUSBWireData.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL  3'b100
+
+module writeUSBWireData (
+  TxBitsIn, 
+  TxBitsOut,
+   TxDataOutTick,
+  TxCtrlIn, 
+  TxCtrlOut, 
+  USBWireRdy,
+  USBWireWEn, 
+  TxWireActiveDrive, 
+  fullSpeedRate, 
+  clk, 
+  rst
+   );
+  
+input   [1:0] TxBitsIn;
+input   TxCtrlIn;
+input   USBWireWEn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+output  [1:0] TxBitsOut;
+output TxDataOutTick;
+output  TxCtrlOut;
+output  USBWireRdy;
+output  TxWireActiveDrive;
+
+wire    [1:0] TxBitsIn;
+reg     [1:0] TxBitsOut;
+reg     TxDataOutTick;
+wire    TxCtrlIn;
+reg     TxCtrlOut;
+reg     USBWireRdy;
+wire    USBWireWEn;
+wire    clk;
+wire    fullSpeedRate;
+wire    rst;
+reg     TxWireActiveDrive;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else
+  begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+//buffer input state machine 
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+     incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    USBWireRdy <= 1'b0;
+    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+  end
+  else begin
+    case (bufferInStMachCurrState)
+      `WAIT_BUFFER_NOT_FULL:
+      begin
+        if (bufferCnt != `BUFFER_FULL)  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+      end
+      `WAIT_WRITE_REQ:
+      begin
+        if (USBWireWEn == 1'b1)
+        begin
+          incBufferCnt <= 1'b1;
+          USBWireRdy <= 1'b0;
+          bufferInIndex <= bufferInIndex + 1'b1;
+          case (bufferInIndex)
+            2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+            2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+            2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+            2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+          endcase
+          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+        end
+      end
+      `CLR_INC_BUFFER_CNT:
+      begin
+        incBufferCnt <= 1'b0;
+        if (bufferCnt != (`BUFFER_FULL - 1'b1) )  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+        else begin
+          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+        end
+      end
+    endcase
+  end
+end
+        
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    fullSpeedTick <= 1'b0;
+    lowSpeedTick <= 1'b0;
+  end
+  else
+  begin
+    i <= i + 1'b1;
+    if (i[1:0] == 2'b00)
+      fullSpeedTick <= 1'b1;
+    else
+      fullSpeedTick <= 1'b0; 
+    if (i == 5'b00000)
+      lowSpeedTick <= 1'b1;
+    else
+      lowSpeedTick <= 1'b0;
+  end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferOutIndex <= 2'b00;
+    decBufferCnt <= 1'b0;
+    TxBitsOut <= 2'b00;
+    TxCtrlOut <= `TRI_STATE;
+    TxDataOutTick <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+  end
+  else
+  begin
+    case (bufferOutStMachCurrState)
+      `WAIT_LINE_WRITE:
+      begin
+        if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+        begin
+          TxDataOutTick <= !TxDataOutTick;
+          if (bufferCnt == 0) begin
+            TxBitsOut <= 2'b00;
+            TxCtrlOut <= `TRI_STATE;
+          end
+          else begin
+            bufferOutStMachCurrState <= `LINE_WRITE;
+            decBufferCnt <= 1'b1;
+            bufferOutIndex <= bufferOutIndex + 1'b1;
+            case (bufferOutIndex)
+              2'b00 :
+            begin 
+              TxBitsOut <= buffer0[2:1];
+              TxCtrlOut <= buffer0[0];
+            end
+            2'b01 : 
+            begin
+              TxBitsOut <= buffer1[2:1];
+              TxCtrlOut <= buffer1[0];
+            end
+            2'b10 : 
+            begin 
+              TxBitsOut <= buffer2[2:1];
+              TxCtrlOut <= buffer2[0];
+            end
+            2'b11 : 
+            begin
+              TxBitsOut <= buffer3[2:1];
+              TxCtrlOut <= buffer3[0];
+            end
+            endcase
+          end
+        end
+      end
+      `LINE_WRITE:
+      begin
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+      end
+    endcase
+  end
+end
+
+// control 'TxWireActiveDrive' 
+always @(TxCtrlOut)
+begin  
+  if (TxCtrlOut == `DRIVE)
+    TxWireActiveDrive <= 1'b1;
+  else
+    TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.asf	(revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SCTxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
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+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
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+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SARB_SEND_PACKET\n/1/"
+S 14 6 4096 ELLIPSE "States" | 269063,296392 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 10 6 0 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_SARB\n/3/"
+S 8 6 12288 ELLIPSE "States" | 225591,395370 6500 6500
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "SCTxArb"
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,543100 1 0 0 "Module: SCTxPortArbiter"
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+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
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+                                      248267,378971 241663,376577 234289,371557 230118,369008
+C 26 17 0 TEXT "Conditions" | 202073,391408 1 0 0 "rst"
+A 25 8 2 TEXT "Actions" | 234434,411387 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
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+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 43 42 0 TEXT "Labels" | 172566,462781 1 0 0 "SCTxPortRdyIn"
+I 42 0 2 Builtin InPort | 166566,462781 "" ""
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+L 40 39 0 TEXT "Labels" | 195447,542126 1 0 0 "rst"
+I 39 0 2 Builtin InPort | 189447,542126 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
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+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
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+L 61 41 0 TEXT "Labels" | 196061,536582 1 0 0 "clk"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "SCTxPortData[7:0]"
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+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n  SCTxPortRdyOut = SCTxPortRdyIn;\nend\n	  \nalways @(muxDCEn or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n  begin  \n    SCTxPortWEnable <= directCntlWEn;\n    SCTxPortData <= directCntlData;\n    SCTxPortCntl <= directCntlCntl;\n  end\nelse\n  begin  \n    SCTxPortWEnable <= sendPacketWEn;\n    SCTxPortData <= sendPacketData;\n    SCTxPortCntl <= sendPacketCntl;\n  end\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
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+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
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+I 64 0 2 Builtin OutPort | 164048,467134 "" ""
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+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "SARB_DC\n/2/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxDCEn"
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+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
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+I 80 0 2 Builtin InPort | 120331,452467 "" ""
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+                                      264783,394808 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveRxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveRxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveRxStatusMonitor.v                                       ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      resetEventOut <= 1'b1;
+    else
+      resetEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.v	(revision 264)
@@ -0,0 +1,507 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input   bitStuffError;
+input   clk;
+input   CRCError;
+input   getPacketRdy;
+input   rst;
+input   [7:0]RxByte;
+input   RxDataWEn;
+input   RxOverflow;
+input   [7:0]RxStatus;
+input   RxTimeOut;
+input   SCGlobalEn;
+input   sendPacketRdy;
+input   [4:0]USBEndPControlReg;
+input   [6:0]USBTgtAddress;
+output  clrEPRdy;
+output  endPMuxErrorsWEn;
+output  [10:0]frameNum;
+output  getPacketREn;
+output  NAKSent;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  SOFRxed;
+output  stallSent;
+output  transDone;
+output  [3:0]USBEndP;
+output  [1:0]USBEndPNakTransTypeReg;
+output  [1:0]USBEndPTransTypeReg;
+
+wire    bitStuffError;
+wire    clk;
+reg     clrEPRdy, next_clrEPRdy;
+wire    CRCError;
+reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg     [10:0]frameNum, next_frameNum;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+reg     NAKSent, next_NAKSent;
+wire    rst;
+wire    [7:0]RxByte;
+wire    RxDataWEn;
+wire    RxOverflow;
+wire    [7:0]RxStatus;
+wire    RxTimeOut;
+wire    SCGlobalEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     SOFRxed, next_SOFRxed;
+reg     stallSent, next_stallSent;
+reg     transDone, next_transDone;
+reg     [3:0]USBEndP, next_USBEndP;
+wire    [4:0]USBEndPControlReg;
+reg     [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg     [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire    [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg  [7:0]addrEndPTemp, next_addrEndPTemp;
+reg  [7:0]endpCRCTemp, next_endpCRCTemp;
+reg  [7:0]PIDByte, next_PIDByte;
+reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg  [6:0]USBAddress, next_USBAddress;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define SETUP_OUT_CHK 5'b01011
+`define SETUP_OUT_SEND 5'b01100
+`define SETUP_OUT_GET_PKT 5'b01101
+`define START_S1 5'b01110
+`define GET_TOKEN_DELAY 5'b01111
+`define GET_TOKEN_CHK_ADDR 5'b10000
+`define IN_RESP_GET_RESP 5'b10001
+`define IN_RESP_DATA 5'b10010
+`define IN_RESP_CHK_ISO 5'b10011
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlReg or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or CurrState_slvCntrl)
+begin
+  NextState_slvCntrl <= CurrState_slvCntrl;
+  // Set default values for outputs and signals
+  next_stallSent <= stallSent;
+  next_NAKSent <= NAKSent;
+  next_SOFRxed <= SOFRxed;
+  next_PIDByte <= PIDByte;
+  next_transDone <= transDone;
+  next_clrEPRdy <= clrEPRdy;
+  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+  next_endpCRCTemp <= endpCRCTemp;
+  next_addrEndPTemp <= addrEndPTemp;
+  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+  next_frameNum <= frameNum;
+  next_USBAddress <= USBAddress;
+  next_USBEndP <= USBEndP;
+  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  next_getPacketREn <= getPacketREn;
+  case (CurrState_slvCntrl)  // synopsys parallel_case full_case
+    `WAIT_RX1:
+    begin
+      next_stallSent <= 1'b0;
+      next_NAKSent <= 1'b0;
+      next_SOFRxed <= 1'b0;
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_START && 
+        RxByte[1:0] == `TOKEN)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+        next_PIDByte <= RxByte;
+      end
+    end
+    `FIN_SC:
+    begin
+      next_transDone <= 1'b0;
+      next_clrEPRdy <= 1'b0;
+      next_endPMuxErrorsWEn <= 1'b0;
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_PID:
+    begin
+      if (PIDByte[3:0] == `SETUP)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if (PIDByte[3:0] == `OUT)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `IN_CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else if (((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1))
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+      else if (PIDByte[3:0] == `IN)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `PID_ERROR;
+      end
+    end
+    `PID_ERROR:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_RDY:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_transDone <= 1'b1;
+        next_clrEPRdy <= 1'b1;
+        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else if (NAKSent == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+      end
+    end
+    `SETUP_OUT_CHK:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `SETUP_OUT_SEND:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `SETUP_OUT_GET_PKT:
+    begin
+      next_getPacketREn <= 1'b0;
+      if ((getPacketRdy == 1'b1) && (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+      else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+        bitStuffError == 1'b0 && 
+        RxOverflow == 1'b0 && 
+        RxTimeOut == 1'b0))
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_CHK;
+      end
+      else if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_NAK_STALL:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_CHK_RDY:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `IN_RESP_GET_RESP:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_RESP_DATA:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_RESP_CHK_ISO;
+      end
+    end
+    `IN_RESP_CHK_ISO:
+    begin
+      if (USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_GET_RESP;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `START_S1:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `GET_TOKEN_WAIT_CRC:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+        next_endpCRCTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_ADDR:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+        next_addrEndPTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_STOP:
+    begin
+      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+      end
+      else if (RxDataWEn == 1'b1)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_CHK_SOF:
+    begin
+      if (PIDByte[3:0] == `SOF)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+        next_SOFRxed <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_DELAY;
+        next_USBAddress <= addrEndPTemp[6:0];
+        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+      end
+    end
+    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndPControlReg to update
+    begin
+      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+    end
+    `GET_TOKEN_CHK_ADDR:
+    begin
+      if (USBEndP < `NUM_OF_ENDPOINTS  &&
+        USBAddress == USBTgtAddress &&
+        SCGlobalEn == 1'b1 &&
+        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_PID;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvCntrl <= `START_S1;
+  else
+    CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    stallSent <= 1'b0;
+    NAKSent <= 1'b0;
+    SOFRxed <= 1'b0;
+    transDone <= 1'b0;
+    clrEPRdy <= 1'b0;
+    endPMuxErrorsWEn <= 1'b0;
+    frameNum <= 11'b00000000000;
+    USBEndP <= 4'h0;
+    USBEndPTransTypeReg <= 2'b00;
+    USBEndPNakTransTypeReg <= 2'b00;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    getPacketREn <= 1'b0;
+    PIDByte <= 8'h00;
+    endpCRCTemp <= 8'h00;
+    addrEndPTemp <= 8'h00;
+    tempUSBEndPTransTypeReg <= 2'b00;
+    USBAddress <= 7'b0000000;
+  end
+  else 
+  begin
+    stallSent <= next_stallSent;
+    NAKSent <= next_NAKSent;
+    SOFRxed <= next_SOFRxed;
+    transDone <= next_transDone;
+    clrEPRdy <= next_clrEPRdy;
+    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+    frameNum <= next_frameNum;
+    USBEndP <= next_USBEndP;
+    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+    getPacketREn <= next_getPacketREn;
+    PIDByte <= next_PIDByte;
+    endpCRCTemp <= next_endpCRCTemp;
+    addrEndPTemp <= next_addrEndPTemp;
+    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+    USBAddress <= next_USBAddress;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.v	(revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveGetPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
+input   clk;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  ACKRxed;
+output  bitStuffError;
+output  CRCError;
+output  dataSequence;
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXOverflow;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  RXTimeOut;
+
+reg     ACKRxed, next_ACKRxed;
+reg     bitStuffError, next_bitStuffError;
+wire    clk;
+reg     CRCError, next_CRCError;
+reg     dataSequence, next_dataSequence;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXOverflow, next_RXOverflow;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+wire    [7:0]RXStreamStatusIn;
+reg     RXTimeOut, next_RXTimeOut;
+wire    SIERxTimeOut;
+
+// diagram signals declarations
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
+begin
+  NextState_slvGetPkt <= CurrState_slvGetPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  case (CurrState_slvGetPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (SIERxTimeOut == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_slvGetPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_slvGetPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (RXFifoFull == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvGetPkt <= `START_GP;
+  else
+    CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXOverflow <= 1'b0;
+    ACKRxed <= 1'b0;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RXTimeOut <= 1'b0;
+    RxPID <= 4'h0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    RXByteOld <= 8'h00;
+  end
+  else 
+  begin
+    RXOverflow <= next_RXOverflow;
+    ACKRxed <= next_ACKRxed;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RXTimeOut <= next_RXTimeOut;
+    RxPID <= next_RxPID;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    RXByteOld <= next_RXByteOld;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.asf	(revision 264)
@@ -0,0 +1,403 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=857
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
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+END
+OBJECTS
+C 831 830 0 TEXT "Conditions" | 112905,152704 1 0 0 "USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+W 830 821 1 847 832 BEZIER "Transitions" | 149052,177611 172803,163396 180803,116530 192775,92880
+A 829 828 16 TEXT "Actions" | 74668,133998 1 0 0 "getPacketREn <= 1'b1;"
+W 828 821 2 847 833 BEZIER "Transitions" | 143788,176826 110094,161523 73824,121282 61589,104841
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+S 820 589 102404 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 67420,66064 6500 6500
+L 819 820 0 TEXT "State Labels" | 67420,66064 1 0 0 "RESP"
+L 554 551 0 TEXT "State Labels" | 63527,72146 1 0 0 "SETUP_OUT"
+S 551 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63527,72146 6500 6500
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+                                       30330,86104 25492,143212 35905,156667 46318,170122\
+                                       96612,168665 117496,167729
+A 548 546 16 TEXT "Actions" | 104043,25328 1 0 0 "USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+C 547 546 0 TEXT "Conditions" | 180628,44450 1 0 0 "NAKSent == 1'b1"
+W 546 6 8194 531 81 BEZIER "Transitions" | 193355,54360 193121,48042 196557,33707 194740,28964\
+                                           192923,24221 173766,19421 163644,19865 153522,20309\
+                                           122483,20608 111915,23020 101347,25432 81761,37919\
+                                           69710,37919
+C 285 97 0 TEXT "Conditions" | 99944,129593 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 190399,213982 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 182869,214288 "" ""
+L 272 271 0 TEXT "Labels" | 186628,209022 1 0 0 "getPacketREn"
+S 15 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "slvCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,252232 1 0 0 "Module: slavecontroller"
+S 847 821 114688 ELLIPSE "States" | 145546,183083 6500 6500
+A 846 839 4 TEXT "Actions" | 65120,205455 1 0 0 "sendPacketWEn <= 1'b0;"
+C 845 844 0 TEXT "Conditions" | 79180,187273 1 0 0 "sendPacketRdy == 1'b1"
+W 844 821 0 839 847 BEZIER "Transitions" | 51640,188679 108408,173735 108918,187523 139645,180358
+A 843 833 4 TEXT "Actions" | 70674,110022 1 0 0 "getPacketREn <= 1'b0;"
+L 840 839 0 TEXT "State Labels" | 49830,194919 1 0 0 "DATA\n/18/"
+S 839 821 110592 ELLIPSE "States" | 49830,194919 6500 6500
+L 834 833 0 TEXT "State Labels" | 56676,100586 1 0 0 "GET_RESP\n/17/"
+S 833 821 106496 ELLIPSE "States" | 56676,100586 6500 6500
+I 832 821 0 Builtin Exit | 195662,92880
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+W 856 589 0 820 587 BEZIER "Transitions" | 73765,64656 103240,60314 160481,49774 189956,45432
+C 855 854 0 TEXT "Conditions" | 79768,96292 1 0 0 "getPacketRdy == 1'b1"
+W 854 821 0 833 832 BEZIER "Transitions" | 63119,99731 96001,98583 159828,94028 192710,92880
+C 853 852 0 TEXT "Conditions" | 112257,227462 1 0 0 "USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b0"
+W 852 589 1 800 605 BEZIER "Transitions" | 112033,243004 131211,241916 168722,239928 178018,237332\
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+I 850 821 0 Builtin Entry | 49920,240120
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+I 588 589 0 Builtin Entry | 205195,243792
+I 587 589 0 Builtin Exit | 192962,45432
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+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
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+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
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+L 604 605 0 TEXT "State Labels" | 101725,211799 1 0 0 "CHK_RDY\n/10/"
+A 603 596 4 TEXT "Actions" | 173404,104745 1 0 0 "sendPacketWEn <= 1'b0;"
+W 601 589 8193 605 596 BEZIER "Transitions" | 108219,211536 117760,212835 193154,194500 186733,113295
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+C 598 600 0 TEXT "Conditions" | 169310,83968 1 0 0 "sendPacketRdy == 1'b1"
+L 597 596 0 TEXT "State Labels" | 181443,115599 1 0 0 "NAK_STALL\n/9/"
+S 596 589 49152 ELLIPSE "States" | 180409,114797 6500 6500
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
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+I 619 618 0 Builtin Entry | 96520,152400
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+A 615 612 16 TEXT "Actions" | 138346,155279 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 614 612 0 TEXT "Conditions" | 70152,180662 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+W 613 589 8195 605 617 BEZIER "Transitions" | 96173,208420 81310,204985 61686,186612 53042,177585
+W 612 589 8194 605 596 BEZIER "Transitions" | 102126,205324 97268,194370 163866,132884 176477,119972
+A 638 631 16 TEXT "Actions" | 117990,107831 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+A 637 630 16 TEXT "Actions" | 47297,102245 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+C 636 630 0 TEXT "Conditions" | 35003,128975 1 0 0 "USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+W 631 589 8194 617 820 BEZIER "Transitions" | 54078,173688 59930,171532 83885,163128 122946,146882\
+                                              162008,130636 151291,117855 140238,106874 129185,95894\
+                                              77774,78896 71279,71294
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+                                              41052,159480 41752,153900 40959,141711 40167,129522\
+                                              46701,89176 50135,78506 53570,67837 54978,65340\
+                                              57981,65109 60984,64878 60458,64813 61074,64659
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/11/"
+S 654 559 61440 ELLIPSE "States" | 92422,152802 6500 6500
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+C 652 651 0 TEXT "Conditions" | 124856,135409 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+I 650 559 0 Builtin Exit | 194044,45058
+I 649 559 0 Builtin Entry | 37971,243103
+I 381 377 0 Builtin Exit | 206487,14249
+I 380 377 0 Builtin Entry | 48940,236580
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+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+I 96 722 0 Builtin Reset | 76296,129336
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/12/"
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+S 656 559 65536 ELLIPSE "States" | 109789,85208 5889 6500
+I 399 377 0 Builtin Link | 54419,17564
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+                                              60053,165183 57484,160822 55722,148570 53960,136319\
+                                              36935,95064 38880,77714 40826,60365 38327,20823\
+                                              54419,15564
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+                                              46511,172964 33727,90292 34975,71611 36223,52930\
+                                              35724,34993 37785,28932 39847,22872 46307,16188\
+                                              54419,15564
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+I 701 699 0 Builtin Exit | 144780,101600
+I 700 699 0 Builtin Entry | 96520,152400
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 698 559 73748 ELLIPSE "Junction" | 117000,209824 3500 3500
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+W 696 559 8195 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+                                              200304,203038 205920,186346 207441,167119 208962,147892\
+                                              209430,87676 208962,71608 208494,55540 206154,51484\
+                                              204438,50041 202722,48598 199528,45916 197266,45058
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+                                              39220,148925 36609,140943 36571,133460 36533,125977\
+                                              38989,104026 47738,97617 56488,91209 87662,87731\
+                                              103933,85889
+C 693 692 0 TEXT "Conditions" | 66756,183110 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 692 559 8194 698 654 BEZIER "Transitions" | 115978,206479 88070,190212 85643,190437 93781,159154
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+S 690 559 69632 ELLIPSE "States" | 98991,238090 6500 6500
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/13/"
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+                                              69948,104476 47394,95074 43302,84878 39210,74682\
+                                              42917,24960 54419,15564
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+I 423 421 0 Builtin Exit | 144780,101600
+I 422 421 0 Builtin Entry | 96520,152400
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+                                           108160,233400 112640,227800 113920,224400 115200,221000\
+                                           116013,213096 116333,209096
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+I 727 722 0 Builtin Exit | 144780,101600
+I 726 722 0 Builtin Entry | 96520,152400
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;"
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/14/"
+S 723 722 81920 ELLIPSE "States" | 120650,127000 6500 6500
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/16/"
+S 462 377 94208 ELLIPSE "States" | 94684,51331 6500 6500
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[4:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+C 468 457 0 TEXT "Conditions" | 76387,38022 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS  &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+                                              46860,73975 46530,57145 47396,48771 48262,40398\
+                                              52522,23896 54419,15564
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+C 791 790 0 TEXT "Conditions" | 102423,188540 1 0 0 "USBEndPControlReg [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+W 790 559 1 698 650 BEZIER "Transitions" | 120235,208489 139440,201809 176211,187874 186899,181444\
+                                           197587,175015 201929,162657 202973,147251 204017,131846\
+                                           203849,82580 202847,68719 201846,54859 198970,48147\
+                                           197050,45058
+K 788 786 0 TEXT "Comments" | 118800,50912 1 0 0 "Insert delay to allow USBEndPControlReg to update"
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+S 786 377 90112 ELLIPSE "States" | 123152,53144 6500 6500
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/15/"
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+                                            105236,81091 81842,75191 69908,73378
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+                                            60717,97705 62441,84600 62616,78575
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+                                              53866,34676 56339,23332 57169,17564
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+                                           209214,43082 209522,23062 208983,17094 208444,11127\
+                                           205980,7277 191773,6353 177567,5429 123205,5583\
+                                           106804,9317 90403,13052 79161,27836 75696,31763\
+                                           72231,35690 70888,36159 69579,36621
+C 812 807 0 TEXT "Conditions" | 65637,235739 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1"
+W 810 589 3 800 587 BEZIER "Transitions" | 105040,243281 73377,254491 34925,221320 34178,196665\
+                                           33432,172010 34721,79558 53522,54375 72324,29193\
+                                           153226,30396 173104,33029 192983,35662 193169,40577\
+                                           192962,43440
+W 807 589 2 800 617 BEZIER "Transitions" | 106097,240666 80398,219718 50449,190675 50573,178391
+I 804 805 0 Builtin Entry | 96520,152400
+I 803 805 0 Builtin Exit | 144780,101600
+W 802 805 0 804 803 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+L 801 800 0 TEXT "State Labels" | 108538,243174 1 0 0 "J4"
+S 800 589 98324 ELLIPSE "Junction" | 108538,243174 3500 3500
+H 805 800 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+C 535 532 0 TEXT "Conditions" | 73577,60437 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1"
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(revision 264)
@@ -0,0 +1,208 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbTxWireArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input   clk;
+input   prcTxByteCtrl;
+input   [1:0]prcTxByteData;
+input   prcTxByteFSRate;
+input   prcTxByteReq;
+input   prcTxByteWEn;
+input   rst;
+input   SIETxCtrl;
+input   [1:0]SIETxData;
+input   SIETxFSRate;
+input   SIETxReq;
+input   SIETxWEn;
+input   USBWireRdyIn;
+output  prcTxByteGnt;
+output  SIETxGnt;
+output  [1:0]TxBits;
+output  TxCtl;
+output  TxFSRate;
+output  USBWireRdyOut;
+output  USBWireWEn;
+
+wire    clk;
+wire    prcTxByteCtrl;
+wire    [1:0]prcTxByteData;
+wire    prcTxByteFSRate;
+reg     prcTxByteGnt, next_prcTxByteGnt;
+wire    prcTxByteReq;
+wire    prcTxByteWEn;
+wire    rst;
+wire    SIETxCtrl;
+wire    [1:0]SIETxData;
+wire    SIETxFSRate;
+reg     SIETxGnt, next_SIETxGnt;
+wire    SIETxReq;
+wire    SIETxWEn;
+reg     [1:0]TxBits, next_TxBits;
+reg     TxCtl, next_TxCtl;
+reg     TxFSRate, next_TxFSRate;
+wire    USBWireRdyIn;
+reg     USBWireRdyOut, next_USBWireRdyOut;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
+SIETxFSRate or prcTxByteFSRate)
+begin
+if (muxSIENotPTXB  == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+TxFSRate <= SIETxFSRate;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+TxFSRate <= prcTxByteFSRate;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+  NextState_txWireArb <= CurrState_txWireArb;
+  // Set default values for outputs and signals
+  next_prcTxByteGnt <= prcTxByteGnt;
+  next_SIETxGnt <= SIETxGnt;
+  next_muxSIENotPTXB <= muxSIENotPTXB;
+  case (CurrState_txWireArb)  // synopsys parallel_case full_case
+    `START_TARB:
+    begin
+      NextState_txWireArb <= `TARB_WAIT_REQ;
+    end
+    `TARB_WAIT_REQ:
+    begin
+      if (prcTxByteReq == 1'b1)
+      begin
+        NextState_txWireArb <= `PTXB_ACT;
+        next_prcTxByteGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b0;
+      end
+      else if (SIETxReq == 1'b1)
+      begin
+        NextState_txWireArb <= `SIE_TX_ACT;
+        next_SIETxGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b1;
+      end
+    end
+    `PTXB_ACT:
+    begin
+      if (prcTxByteReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_prcTxByteGnt <= 1'b0;
+      end
+    end
+    `SIE_TX_ACT:
+    begin
+      if (SIETxReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_SIETxGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_txWireArb <= `START_TARB;
+  else
+    CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    prcTxByteGnt <= 1'b0;
+    SIETxGnt <= 1'b0;
+    muxSIENotPTXB <= 1'b0;
+  end
+  else 
+  begin
+    prcTxByteGnt <= next_prcTxByteGnt;
+    SIETxGnt <= next_SIETxGnt;
+    muxSIENotPTXB <= next_muxSIENotPTXB;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/fifoMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/fifoMux.v	(revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMux (
+  currEndP,
+  //TxFifo
+  TxFifoREn,
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoData,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEmpty,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  //RxFifo
+  RxFifoWEn,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoFull,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+  //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+  //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+  TxFifoREn or
+  RxFifoWEn or
+  TxFifoEP0Data or
+  TxFifoEP1Data or
+  TxFifoEP2Data or
+  TxFifoEP3Data or
+  TxFifoEP0Empty or
+  TxFifoEP1Empty or
+  TxFifoEP2Empty or
+  TxFifoEP3Empty or
+  RxFifoEP0Full or
+  RxFifoEP1Full or
+  RxFifoEP2Full or
+  RxFifoEP3Full)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      TxFifoEP0REn <= TxFifoREn;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP0Data;
+      TxFifoEmpty <= TxFifoEP0Empty;
+      RxFifoEP0WEn <= RxFifoWEn;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP0Full;
+    end
+    2'b01: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= TxFifoREn;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP1Data;
+      TxFifoEmpty <= TxFifoEP1Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= RxFifoWEn;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP1Full;
+    end
+    2'b10: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= TxFifoREn;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP2Data;
+      TxFifoEmpty <= TxFifoEP2Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= RxFifoWEn;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP2Full;
+    end
+    2'b11: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= TxFifoREn;
+      TxFifoData <= TxFifoEP3Data;
+      TxFifoEmpty <= TxFifoEP3Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= RxFifoWEn;
+      RxFifoFull <= RxFifoEP3Full;
+    end
+  endcase  
+end      
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.v	(revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveDirectControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+  NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+  // Set default values for outputs and signals
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvDrctCntl)  // synopsys parallel_case full_case
+    `START_SDC:
+    begin
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+        next_SCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= {6'b000000, directControlLineState};
+        next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      next_SCTxPortReq <= 1'b0;
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvDrctCntl <= `START_SDC;
+  else
+    CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SCTxPortCntl <= 8'h00;
+    SCTxPortData <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.asf	(revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveSendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
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+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP1_WAIT_GNT\n/2/"
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+I 12 6 0 Builtin Reset | 74872,202290
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: slaveSendPacket"
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP1\n/0/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "SP_WAIT_ENABLE\n/1/"
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+W 30 25 0 28 26 BEZIER "Transitions" | 53779,230379 60054,220138 63123,209223 69341,197615
+I 29 25 0 Builtin Exit | 146004,95604
+I 28 25 0 Builtin Entry | 49237,230379
+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
+S 26 25 16384 ELLIPSE "States" | 72734,192072 6500 6500
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 29624,2084 214124,250084
+C 23 22 0 TEXT "Conditions" | 114630,116691 1 0 0 "SCTxPortGnt == 1'b1"
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 112951,104607 113260,100204
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113767,93734 6500 6500
+L 20 21 0 TEXT "State Labels" | 113767,93734 1 0 0 "SP_SEND_PID"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nSCTxPortReq <= 1'b1;"
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+S 47 6 28672 ELLIPSE "States" | 115848,16910 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
+S 45 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,45960 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,45960 1 0 0 "SP_D0_D1"
+W 39 25 0 33 29 BEZIER "Transitions" | 79375,148210 95944,135371 126275,108443 142844,95604
+A 38 33 4 TEXT "Actions" | 93627,154331 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
+C 36 34 0 TEXT "Conditions" | 75236,185214 1 0 0 "SCTxPortRdy == 1'b1"
+W 34 25 0 26 33 BEZIER "Transitions" | 72953,185597 73302,178879 73960,166205 74309,159487
+S 33 25 20480 ELLIPSE "States" | 75021,153035 6500 6500
+L 32 33 0 TEXT "State Labels" | 75021,153035 1 0 0 "FIN\n/4/"
+W 50 6 8193 21 45 BEZIER "Transitions" | 119169,90120 134042,80003 162156,60011 177029,49894
+W 48 6 8194 21 205 BEZIER "Transitions" | 108645,89734 97773,80901 77133,63853 66261,55020
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+W 74 6 0 205 47 BEZIER "Transitions" | 67096,47093 78647,41129 99521,27639 110324,20335
+W 73 6 0 45 47 BEZIER "Transitions" | 176581,42697 162161,37714 135904,25306 121888,19311
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 126 65 0 Builtin Entry | 68162,237252
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 72704,237252 77515,245311 99394,235265 108723,227500
+S 136 65 32768 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1;	 \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170187,37688 173773,37229
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "SCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+L 211 212 0 TEXT "State Labels" | 76973,151815 1 0 0 "CLR_REN\n/13/"
+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 209 65 0 136 207 BEZIER "Transitions" | 103712,132145 117531,130730 143304,126529 157123,125114
+W 210 65 0 207 145 BEZIER "Transitions" | 169895,125680 176804,126013 188953,127552 193864,130465\
+                                          198775,133379 204604,144369 205686,152818 206768,161268\
+                                          205269,184079 201481,192903 197694,201727 184040,214216\
+                                          173218,217462 162396,220708 133810,221642 118992,221891
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/usbSlaveControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/usbSlaveControl.v	(revision 264)
@@ -0,0 +1,493 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSlaveControl(
+  clk, rst,
+  //getPacket
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut, RxFifoData,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //SCTxPortArbiter
+  SCTxPortEn, SCTxPortRdy,
+  SCTxPortData, SCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFRxedIntOut, 
+  resetEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  NAKSentIntOut,
+  slaveControlSelect,
+  //fifoMux
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+input clk, rst;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [4:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut; 
+output resetEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire clk;
+wire rst;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut; 
+wire resetEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed; 
+wire CRCError; 
+wire RXOverflow; 
+wire RXTimeOut; 
+wire bitStuffError; 
+wire dataSequence; 
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [4:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+
+USBSlaveControlBI u_USBSlaveControlBI
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .SOFRxedIntOut(SOFRxedIntOut), 
+  .resetEventIntOut(resetEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .NAKSentIntOut(NAKSentIntOut),
+  .endP0TransTypeReg(endP0TransTypeReg), 
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg), 
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg), 
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg), 
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .EP0StatusReg(endP0StatusReg),
+  .EP1StatusReg(endP1StatusReg),
+  .EP2StatusReg(endP2StatusReg),
+  .EP3StatusReg(endP3StatusReg),
+  .SCAddrReg(USBTgtAddress), 
+  .frameNum(frameNum),
+  .connectStateIn(connectStateOut),
+  .SOFRxedIn(SOFRxed), 
+  .resetEventIn(resetEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .NAKSentIn(NAKSent),
+  .slaveControlSelect(slaveControlSelect),
+  .clrEP0Ready(clrEP0Rdy), 
+  .clrEP1Ready(clrEP1Rdy), 
+  .clrEP2Ready(clrEP2Rdy), 
+  .clrEP3Ready(clrEP3Rdy),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .SCGlobalEn(SCGlobalEn)
+  );
+
+slavecontroller u_slavecontroller
+  (.CRCError(CRCError), 
+  .NAKSent(NAKSent), 
+  .RxByte(RxData), 
+  .RxDataWEn(RxDataValid), 
+  .RxOverflow(RXOverflow), 
+  .RxStatus(RxByteStatus), 
+  .RxTimeOut(RXTimeOut), 
+  .SCGlobalEn(SCGlobalEn), 
+  .SOFRxed(SOFRxed), 
+  .USBEndPControlReg(endPControlReg), 
+  .USBEndPNakTransTypeReg(transTypeNAK), 
+  .USBEndPTransTypeReg(transType), 
+  .USBEndP(currEndP), 
+  .USBTgtAddress(USBTgtAddress),
+  .bitStuffError(bitStuffError), 
+  .clk(clk), 
+  .clrEPRdy(clrEPRdy), 
+  .endPMuxErrorsWEn(endPMuxErrorsWEn), 
+  .frameNum(frameNum), 
+  .getPacketREn(getPacketREn), 
+  .getPacketRdy(getPacketRdy), 
+  .rst(rst), 
+  .sendPacketPID(slaveControllerPIDOut), 
+  .sendPacketRdy(slaveControllerReadyIn), 
+  .sendPacketWEn(slaveControllerWEnOut), 
+  .stallSent(stallSent), 
+  .transDone(transDone) 
+    );
+
+
+endpMux u_endpMux (
+  .clk(clk), 
+  .rst(rst),
+  .currEndP(currEndP),
+  .NAKSent(NAKSent),
+  .stallSent(stallSent),
+  .CRCError(CRCError),
+  .bitStuffError(bitStuffError),
+  .RxOverflow(RXOverflow),
+  .RxTimeOut(RXTimeOut),
+  .dataSequence(dataSequence),
+  .ACKRxed(ACKRxed),
+  .transType(transType),
+  .transTypeNAK(transTypeNAK),
+  .endPControlReg(endPControlReg),
+  .clrEPRdy(clrEPRdy),
+  .endPMuxErrorsWEn(endPMuxErrorsWEn),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .endP0StatusReg(endP0StatusReg),
+  .endP1StatusReg(endP1StatusReg),
+  .endP2StatusReg(endP2StatusReg),
+  .endP3StatusReg(endP3StatusReg),
+  .endP0TransTypeReg(endP0TransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg),
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .clrEP0Rdy(clrEP0Rdy),
+  .clrEP1Rdy(clrEP1Rdy),
+  .clrEP2Rdy(clrEP2Rdy),
+  .clrEP3Rdy(clrEP3Rdy)
+    );
+
+slaveSendPacket u_slaveSendPacket
+  (.PID(slaveControllerPIDOut), 
+  .SCTxPortCntl(sendPacketCntl),
+  .SCTxPortData(sendPacketData),
+  .SCTxPortGnt(sendPacketGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(sendPacketReq),
+  .SCTxPortWEn(sendPacketWEn),
+  .clk(clk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .rst(rst),
+  .sendPacketRdy(slaveControllerReadyIn),
+  .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+  (.SCTxPortCntl(directCntlCntl),
+  .SCTxPortData(directCntlData),
+  .SCTxPortGnt(directCntlGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(directCntlReq),
+  .SCTxPortWEn(directCntlWEn),
+  .clk(clk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rst) ); 
+
+SCTxPortArbiter u_SCTxPortArbiter
+  (.SCTxPortCntl(SCTxPortCtrl),
+  .SCTxPortData(SCTxPortData),
+  .SCTxPortRdyIn(SCTxPortRdy),
+  .SCTxPortRdyOut(SCTxPortArbRdyOut),
+  .SCTxPortWEnable(SCTxPortEn),
+  .clk(clk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rst),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+
+slaveGetPacket u_slaveGetPacket
+  (.ACKRxed(ACKRxed), 
+  .CRCError(CRCError), 
+  .RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .clk(clk),
+  .RXOverflow(RXOverflow), 
+  .RXTimeOut(RXTimeOut), 
+  .bitStuffError(bitStuffError), 
+  .dataSequence(dataSequence), 
+  .getPacketEn(getPacketREn),
+  .rst(rst) ); 
+
+slaveRxStatusMonitor  u_slaveRxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .resetEventOut(resetEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(clk),
+  .rst(rst)  );    
+  
+fifoMux u_fifoMux (
+  .currEndP(currEndP),
+  //TxFifo
+  .TxFifoREn(TxFifoRE),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoData(TxFifoData),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEmpty(TxFifoEmpty),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  //RxFifo
+  .RxFifoWEn(RxFifoWE),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoFull(RxFifoFull),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+    );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/doc/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/doc/README.txt	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/doc/README.txt	(revision 264)
@@ -0,0 +1,24 @@
+USBHostSlave has been successfully compiled using Quartus 4.1 with Servive Pack 2
+USBHostSlave has been tested in a SystemC simulation, and on a Altera Nios development kit Cyclone edition.
+
+For those who wish to use a pre-configured Quartus project, I have included two files;
+usbhostslaveQuartusProj.qar   - Quartus project archive
+usbHostSlaveNiosIDEProj.zip   - NIOS IDE project zip file. You can use NIOS IDE File>>import to open the file
+
+
+If you wish to replicate the hardware setup, then you will need to replace
+the standard 50MHz oscillator with a 48MHz oscillator (Digikey XC280-ND),
+and you will need a add a Santa Cruz daughter card with two USB transceivers.
+
+If there is enough interest, I will consider producing a Santa Cruz daughter card
+with the hardware required to support this core. 
+Please email me at sfielding@base2designs.com if you are interested in this option.
+
+
+Release notes:
+Version 6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+            control reads and writes to USB flash dongle 
+
+ 
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/doc/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifo.v	(revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo read access via bus interface, fifo write access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module RxFifo(
+  busClk,
+  usbClk,
+  rstSyncToBusClk, 
+  rstSyncToUsbClk, 
+  fifoWEn, 
+  fifoFull,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataIn  );
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input busClk; 
+input usbClk; 
+input rstSyncToBusClk; 
+input rstSyncToUsbClk; 
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire busClk; 
+wire usbClk; 
+wire rstSyncToBusClk; 
+wire rstSyncToUsbClk; 
+wire fifoWEn; 
+wire fifoFull;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmptySyncToBusClk;
+wire forceEmptySyncToUsbClk;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;   //not used
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .wrClk(usbClk), 
+  .rdClk(busClk), 
+  .rstSyncToWrClk(rstSyncToUsbClk), 
+  .rstSyncToRdClk(rstSyncToBusClk), 
+  .dataIn(fifoDataIn), 
+  .dataOut(dataFromFifoToBus), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmptySyncToWrClk(forceEmptySyncToUsbClk), 
+  .forceEmptySyncToRdClk(forceEmptySyncToBusClk), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+RxfifoBI u_RxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .fifoSelect(busFifoSelect),
+  .fifoDataIn(dataFromFifoToBus),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoREn(fifoREn),
+  .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+  .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/dpMem_dc.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/dpMem_dc.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/dpMem_dc.v	(revision 264)
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// dpMem_dc.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Synchronous dual port memory with dual clocks
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module dpMem_dc(  addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input wrClk;
+input rdClk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire wrClk;
+wire rdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge rdClk) begin
+  dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge wrClk) begin
+  if (writeEn == 1'b1)
+    buffer[addrIn] <= dataIn;
+end                  
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/dpMem_dc.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// directControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/"
+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1"
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
+L 126 127 0 TEXT "State Labels" | 147819,122579 1 0 0 "IDLE"
+W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\
+                                       47285,153175 50048,167625 56316,171290 62585,174956\
+                                       84856,175714 96012,175820
+I 124 79 0 Builtin Entry | 109800,175900
+I 122 79 0 Builtin Exit | 138103,36586
+S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
+S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
+C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "HCTxPortGnt == 1'b1"
+W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
+H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "HCTxPortWEn"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]"
+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "HCTxPortCntl[7:0]"
+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+                                        171826,160150 159742,169266 150997,171704 142252,174142\
+                                        120424,175336 108976,175654
+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "HCTxPortReq <= 1'b1;"
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "HCTxPortGnt"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "HCTxPortRdy"
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;"
+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.asf	(revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hctxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,543100 1 0 0 "Module: HCTxPortArbiter"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "HCTxArb"
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+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_HARB\n/0/"
+S 10 6 4096 ELLIPSE "States" | 224972,365039 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "WAIT_REQ\n/1/"
+S 12 6 8192 ELLIPSE "States" | 191859,293613 6500 6500
+L 13 12 0 TEXT "State Labels" | 191859,293613 1 0 0 "SEND_SOF\n/2/"
+S 14 6 12288 ELLIPSE "States" | 269063,296392 6500 6500
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SEND_PACKET\n/3/"
+I 16 6 0 Builtin Reset | 178237,395710
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210052,391894 219337,393602
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 19 6 2 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 20 6 1 10 12 BEZIER "Transitions" | 219884,360995 214322,355742 203672,314353 193976,299756
+C 21 20 0 TEXT "Conditions" | 185611,358255 1 0 0 "SOFCntlReq == 1'b1"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxCntl <= `SEND_PACKET_MUX;"
+A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;"
+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
+C 26 17 0 TEXT "Conditions" | 201742,391978 1 0 0 "rst"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+                                      288786,359372 287077,371461 282417,376909 277757,382357\
+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+W 28 6 0 12 10 BEZIER "Transitions" | 186560,297376 167155,311353 168429,333163 167686,340659\
+                                      166944,348155 168507,364217 173450,370590 178394,376963\
+                                      186275,384997 193806,383684 201338,382371 213515,373400\
+                                      220004,369229
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n  `SOF_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= SOFCntlWEn;\n    HCTxPortData <= SOFCntlData;\n    HCTxPortCntl <= SOFCntlCntl;\n  end\n  `DIRECT_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= directCntlWEn;\n    HCTxPortData <= directCntlData;\n    HCTxPortCntl <= directCntlCntl;\n  end\n  `SEND_PACKET_MUX :\n  begin  \n    HCTxPortWEnable <= sendPacketWEn;\n    HCTxPortData <= sendPacketData;\n    HCTxPortCntl <= sendPacketCntl;\n  end\n  default :\n  begin  \n    HCTxPortWEnable <= 1'b0;\n    HCTxPortData <= 8'h00;\n    HCTxPortCntl <= 8'h00;\n  end\nendcase	\nend"
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+I 89 0 130 Builtin Signal | 141050,528812 "" ""
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286404,388600 275724,388298\
+                                      265045,387996 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/rxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/rxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// rxStatusMonitor.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      connectionEventOut <= 1'b1;
+    else
+      connectionEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.v	(revision 264)
@@ -0,0 +1,177 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketarbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input   clk;
+input   [3:0]HC_PID;
+input   HC_SP_WEn;
+input   HCTxReq;
+input   rst;
+input   SOF_SP_WEn;
+input   SOFTxReq;
+output  HCTxGnt;
+output  [3:0]sendPacketPID;
+output  sendPacketWEnable;
+output  SOFTxGnt;
+
+wire    clk;
+wire    [3:0]HC_PID;
+wire    HC_SP_WEn;
+reg     HCTxGnt, next_HCTxGnt;
+wire    HCTxReq;
+wire    rst;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+reg     sendPacketWEnable, next_sendPacketWEnable;
+wire    SOF_SP_WEn;
+reg     SOFTxGnt, next_SOFTxGnt;
+wire    SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC  == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+  NextState_sendPktArb <= CurrState_sendPktArb;
+  // Set default values for outputs and signals
+  next_HCTxGnt <= HCTxGnt;
+  next_SOFTxGnt <= SOFTxGnt;
+  next_muxSOFNotHC <= muxSOFNotHC;
+  case (CurrState_sendPktArb)  // synopsys parallel_case full_case
+    `HC_ACT:
+    begin
+      if (HCTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_HCTxGnt <= 1'b0;
+      end
+    end
+    `SOF_ACT:
+    begin
+      if (SOFTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_SOFTxGnt <= 1'b0;
+      end
+    end
+    `SARB_WAIT_REQ:
+    begin
+      if (SOFTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `SOF_ACT;
+        next_SOFTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b1;
+      end
+      else if (HCTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `HC_ACT;
+        next_HCTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_sendPktArb <= `SARB_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktArb <= `START_SARB;
+  else
+    CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxGnt <= 1'b0;
+    SOFTxGnt <= 1'b0;
+    muxSOFNotHC <= 1'b0;
+  end
+  else 
+  begin
+    HCTxGnt <= next_HCTxGnt;
+    SOFTxGnt <= next_SOFTxGnt;
+    muxSOFNotHC <= next_muxSOFNotHC;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlaveWrap.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlaveWrap.v	(revision 264)
@@ -0,0 +1,191 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlaveWrap.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. Enable connection to Altera Avalon bus
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module usbHostSlaveWrap(
+  clk, 
+  reset,
+  address, 
+  writedata, 
+  readdata, 
+  write, 
+  read,
+  waitrequest,
+  chipselect,
+  irq,
+  USBWireVPI,
+  USBWireVMI,
+  USBWireDataInTick,
+  USBWireVPO,
+  USBWireVMO,
+  USBWireDataOutTick,
+  USBWireOutEn_n,
+  USBFullSpeed
+   );
+
+input clk;
+input reset;
+input [7:0] address; 
+input [7:0] writedata; 
+output [7:0] readdata; 
+input write; 
+input read;
+output waitrequest;
+input chipselect;
+output irq;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+
+wire clk;
+wire reset;
+wire [7:0] address; 
+wire [7:0] writedata; 
+wire [7:0] readdata; 
+wire write; 
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+
+//internal wiring 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+             hostResumeIntOut | hostTransDoneIntOut |
+             slaveSOFRxedIntOut | slaveResetEventIntOut |
+             slaveResumeIntOut | slaveTransDoneIntOut |
+             slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut; 
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+//Parameters declaration: 
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+  .clk(clk),
+  .rst(reset),
+  .address_i(address),
+  .data_i(writedata),
+  .data_o(readdata),
+  .writeEn(write),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifoBI.v	(revision 264)
@@ -0,0 +1,146 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+  address, writeEn, strobe_i,
+  busClk, 
+  usbClk, 
+  rstSyncToBusClk, 
+  fifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoWEn,
+  forceEmptySyncToUsbClk,
+  forceEmptySyncToBusClk,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoWEn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+reg fifoWEn;
+reg forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg [5:0] forceEmptyShift;
+reg forceEmpty;
+reg forceEmptySyncToUsbClkFirst;
+
+//sync write
+always @(posedge busClk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+//generate 'forceEmptySyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) 
+    forceEmptyShift <= 6'b000000;
+  else begin
+    if (forceEmpty == 1'b1)
+      forceEmptyShift <= 6'b111111;
+    else
+      forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
+  end
+end
+assign forceEmptySyncToBusClk = forceEmptyShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+    forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
+    forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
+end
+
+
+
+// async read mux
+assign busDataOut = 8'h00;
+//always @(address or fifoFull or numElementsInFifo)
+//begin
+//  case (address)
+//      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+//      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+//      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+//      default: busDataOut <= 8'h00;
+//  endcase
+//end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoWEn <= 1'b1;
+  else
+    fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.asf	(revision 264)
@@ -0,0 +1,277 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=284
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveGetPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 35 34 0 TEXT "Conditions" | 122487,97401 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141572,86202 141370,79031
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141266,72558 6500 6500
+L 32 33 0 TEXT "State Labels" | 141266,72558 1 0 0 "PROC_PKT"
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+                                         190292,107515 191648,100057 191987,92429 192326,84802\
+                                         192326,61750 188540,53162 184755,44574 169613,33274\
+                                         159556,30336 149499,27398 125714,27614 113171,27388
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 50 46 0 Builtin Exit | 180308,72140
+I 49 46 0 Builtin Entry | 47660,248640
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+W 59 46 0 49 54 BEZIER "Transitions" | 52122,248640 63735,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176807,72082 177204,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177624,25344 184036,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+END

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.v	(revision 264)
@@ -0,0 +1,265 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveSendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   [3:0]PID;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   sendPacketWEn;
+output  fifoReadEn;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+wire    [3:0]PID;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: slvSndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
+begin
+  NextState_slvSndPkt <= CurrState_slvSndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvSndPkt)  // synopsys parallel_case full_case
+    `START_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+    end
+    `SP_WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP1_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `SP1_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_SCTxPortReq <= 1'b0;
+    end
+    `SP_NOT_DATA:
+    begin
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_SEND_PID_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= PIDNotPID;
+        next_SCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SP_SEND_PID_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_NOT_DATA;
+      end
+    end
+    `SP_D0_D1_READ_FIFO:
+    begin
+      next_SCTxPortWEn <= 1'b1;
+      next_SCTxPortData <= fifoData;
+      next_SCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+    end
+    `SP_D0_D1_WAIT_READ_FIFO:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `SP_D0_D1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+      end
+    end
+    `SP_D0_D1_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_D0_D1_TERM_BYTE:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `SP_D0_D1_CLR_WEN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+    end
+    `SP_D0_D1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvSndPkt <= `START_SP1;
+  else
+    CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    SCTxPortData <= 8'h00;
+    SCTxPortCntl <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlave.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlave.v	(revision 264)
@@ -0,0 +1,516 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlave.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostSlave(
+  clk, 
+  rst,
+  address_i, 
+  data_i, 
+  data_o, 
+  writeEn, 
+  strobe_i,
+  ack_o,
+  hostSOFSentIntOut, 
+  hostConnEventIntOut, 
+  hostResumeIntOut, 
+  hostTransDoneIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+  USBWireDataIn,
+  USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+  USBWireCtrlOut,
+  USBFullSpeed
+   );
+  parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+  parameter HOST_FIFO_ADDR_WIDTH = 6;   
+  parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+  parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+  parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+  parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk;
+input rst;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input writeEn; 
+input strobe_i;
+output ack_o;
+output hostSOFSentIntOut; 
+output hostConnEventIntOut; 
+output hostResumeIntOut; 
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+
+wire clk;
+wire rst;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire writeEn; 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel; 
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE; 
+wire [7:0] hostTxFifoData; 
+wire hostTxFifoEmpty;
+wire hostRxFifoWE; 
+wire [7:0] hostRxFifoData; 
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost; 
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+
+assign USBFullSpeed = fullSpeedBitRateToSIE;  
+
+usbHostControl u_usbHostControl(
+  .clk(clk), 
+  .rst(rst),
+  .TxFifoRE(hostTxFifoRE), 
+  .TxFifoData(hostTxFifoData), 
+  .TxFifoEmpty(hostTxFifoEmpty),
+  .RxFifoWE(hostRxFifoWE), 
+  .RxFifoData(hostRxFifoData), 
+  .RxFifoFull(hostRxFifoFull),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut),
+  .fullSpeedRate(fullSpeedBitRateFromHost), 
+  .fullSpeedPol(fullSpeedPolarityFromHost),
+  .HCTxPortEn(SIEPortWEnFromHost), 
+  .HCTxPortRdy(SIEPortTxRdy),
+  .HCTxPortData(SIEPortDataInFromHost), 
+  .HCTxPortCtrl(SIEPortCtrlInFromHost),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[3:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+  .SOFSentIntOut(hostSOFSentIntOut), 
+  .connEventIntOut(hostConnEventIntOut), 
+  .resumeIntOut(hostResumeIntOut), 
+  .transDoneIntOut(hostTransDoneIntOut),
+  .hostControlSelect(hostControlSel) );
+  
+
+usbSlaveControl u_usbSlaveControl(
+  .clk(clk), 
+  .rst(rst),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut), 
+  .RxFifoData(slaveRxFifoData),
+  .fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+  .SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+  .SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+  .SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk), 
+  .rst(rst),
+  .hostControlSel(hostControlSel), 
+  .hostRxFifoSel(hostRxFifoSel), 
+  .hostTxFifoSel(hostTxFifoSel),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(dataFromHostControl),
+  .dataFromHostRxFifo(dataFromHostRxFifo),
+  .dataFromHostTxFifo(dataFromHostTxFifo),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+   );
+
+hostSlaveMux u_hostSlaveMux(
+  .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+  .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+  .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+  .SIEPortDataInToSIE(SIEPortDataInToSIE), 
+  .SIEPortDataInFromHost(SIEPortDataInFromHost), 
+  .SIEPortDataInFromSlave(SIEPortDataInFromSlave), 
+  .SIEPortWEnToSIE(SIEPortWEnToSIE), 
+  .SIEPortWEnFromHost(SIEPortWEnFromHost), 
+  .SIEPortWEnFromSlave(SIEPortWEnFromSlave), 
+  .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+  .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+  .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+  .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+  .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+  .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux),
+  .address(address_i[0]),
+  .writeEn(writeEn),
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(clk), 
+  .rst(rst),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .connectState(connectState),
+  .resumeDetected(resumeDetected),
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataFromSIE), 
+  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+  .SIEPortDataIn(SIEPortDataInToSIE), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEnToSIE), 
+  .fullSpeedPolarity(fullSpeedPolarityToSIE),
+  .fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(hostTxFifoRE), 
+  .fifoEmpty(hostTxFifoEmpty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostTxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostTxFifo),
+  .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(hostRxFifoWE), 
+  .fifoFull(hostRxFifoFull),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostRxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostRxFifo),
+  .fifoDataIn(hostRxFifoData)  );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+  TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+  TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_00_07_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_00_07_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm	(revision 264)
@@ -0,0 +1,276 @@
+<html>
+<head>
+<title>USBHostControlBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBHostControlBI.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+ 
+<span id=t_kwd>module</span> <span id=t_idt>USBHostControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>SOFSentIntOut</span>, <span id=t_idt>connEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>TxTransTypeReg</span>, <span id=t_idt>TxSOFEnableReg</span>,
+  <span id=t_idt>TxAddrReg</span>, <span id=t_idt>TxEndPReg</span>, <span id=t_idt>frameNumIn</span>, 
+  <span id=t_idt>RxPktStatusIn</span>, <span id=t_idt>RxPIDIn</span>,
+  <span id=t_idt>connectStateIn</span>,
+  <span id=t_idt>SOFSentIn</span>, <span id=t_idt>connEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>,
+  <span id=t_idt>hostControlSelect</span>,
+  <span id=t_idt>clrTransReq</span>,
+  <span id=t_idt>preambleEn</span>,
+  <span id=t_idt>SOFSync</span>,
+  <span id=t_idt>TxLineState</span>,
+  <span id=t_idt>LineDirectControlEn</span>,
+  <span id=t_idt>fullSpeedPol</span>, 
+  <span id=t_idt>fullSpeedRate</span>,
+  <span id=t_idt>transReq</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>output</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transReq</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transReq</span>;
+
+<span id=t_com>//internal wire and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineControlReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrConnEvtReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>setTransReq</span>;
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResInReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>setTransReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>hostControlSelect</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>preambleEn</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>SOFSync</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>setTransReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>TxTransTypeReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>TxLineControlReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>TxSOFEnableReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>TxAddrReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>TxEndPReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_kwd>begin</span>
+        <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>clrResInReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>interruptMaskReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+   <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//interrupt control</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>SOFSentIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>connEventIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrConnEvtReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b0</span>;  
+
+  <span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//mask interrupts</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSentInt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>transDoneIntOut</span> &lt;= <span id=t_idt>transDoneInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>];
+  <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_idt>resumeInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>];
+  <span id=t_idt>connEventIntOut</span> &lt;= <span id=t_idt>connEventInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>CONNECTION_EVENT_BIT</span>];
+  <span id=t_idt>SOFSentIntOut</span> &lt;= <span id=t_idt>SOFSentInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_SENT_BIT</span>];
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//transaction request set/clear</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>setTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//break out control signals</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>TxLineState</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>TX_LINE_STATE_LSBIT</span>];
+  <span id=t_idt>LineDirectControlEn</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>DIRECT_CONTROL_BIT</span>];
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span>]; 
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span>];
+<span id=t_kwd>end</span>
+  
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxSOFEnableReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndPReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNumIn</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SOFSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span>
+  <span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>RxPktStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxPIDIn</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>preambleEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSync</span> <span id=t_kwd>or</span> <span id=t_idt>transReq</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>preambleEn</span>, <span id=t_idt>SOFSync</span>, <span id=t_idt>transReq</span>} ;
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>TxTransTypeReg</span>};
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>TxLineControlReg</span>};
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>TxSOFEnableReg</span>};
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxAddrReg</span>};
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>TxEndPReg</span>};
+     `<span id=t_idt>FRAME_NUM_MSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>frameNumIn</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>];
+     `<span id=t_idt>FRAME_NUM_LSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNumIn</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]};
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>SOFSentInt</span>, <span id=t_idt>connEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>};
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>interruptMaskReg</span>};
+     `<span id=t_idt>RX_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>RxPktStatusIn</span>;
+     `<span id=t_idt>RX_PID_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'b0000</span>, <span id=t_idt>RxPIDIn</span>};
+     `<span id=t_idt>RX_CONNECT_STATE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>};
+      <span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifo.v	(revision 264)
@@ -0,0 +1,132 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo write access via bus interface, fifo read access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module TxFifo(
+  busClk,
+  usbClk,
+  rstSyncToBusClk, 
+  rstSyncToUsbClk, 
+  fifoREn, 
+  fifoEmpty,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn,
+  busDataOut,
+  fifoDataOut ); 
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input busClk; 
+input usbClk; 
+input rstSyncToBusClk; 
+input rstSyncToUsbClk; 
+input fifoREn; 
+output fifoEmpty;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+output [7:0] fifoDataOut;
+
+wire busClk; 
+wire usbClk; 
+wire rstSyncToBusClk; 
+wire rstSyncToUsbClk; 
+wire fifoREn; 
+wire fifoEmpty;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .wrClk(busClk), 
+  .rdClk(usbClk), 
+  .rstSyncToWrClk(rstSyncToBusClk), 
+  .rstSyncToRdClk(rstSyncToUsbClk), 
+  .dataIn(busDataIn), 
+  .dataOut(fifoDataOut), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmptySyncToWrClk(forceEmptySyncToBusClk), 
+  .forceEmptySyncToRdClk(forceEmptySyncToUsbClk), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+TxfifoBI u_TxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .fifoSelect(busFifoSelect),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut), 
+  .fifoWEn(fifoWEn),
+  .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+  .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/busInterface/wishBoneBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/busInterface/wishBoneBI.v	(revision 264)
@@ -0,0 +1,246 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBI.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "wishBoneBus_h.v"
+
+ 
+module wishBoneBI (
+  address, dataIn, dataOut, writeEn, 
+  strobe_i,
+  ack_o,
+  clk, rst,
+  hostControlSel, 
+  hostRxFifoSel, hostTxFifoSel,
+  slaveControlSel,
+  slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, 
+  slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, 
+  hostSlaveMuxSel,
+  dataFromHostControl,
+  dataFromHostRxFifo,
+  dataFromHostTxFifo,
+  dataFromSlaveControl,
+  dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+  dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+  dataFromHostSlaveMux
+   );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+  dataFromHostControl or
+  dataFromHostRxFifo or
+  dataFromHostTxFifo or
+  dataFromSlaveControl or
+  dataFromEP0RxFifo or 
+  dataFromEP1RxFifo or
+  dataFromEP2RxFifo or
+  dataFromEP3RxFifo or
+  dataFromHostSlaveMux or 
+  dataFromEP0TxFifo or
+  dataFromEP1TxFifo or
+  dataFromEP2TxFifo or
+  dataFromEP3TxFifo)
+begin
+  hostControlSel <= 1'b0;
+  hostRxFifoSel <= 1'b0;
+  hostTxFifoSel <= 1'b0;
+  slaveControlSel <= 1'b0;
+  slaveEP0RxFifoSel <= 1'b0;
+  slaveEP0TxFifoSel <= 1'b0;
+  slaveEP1RxFifoSel <= 1'b0;
+  slaveEP1TxFifoSel <= 1'b0;
+  slaveEP2RxFifoSel <= 1'b0;
+  slaveEP2TxFifoSel <= 1'b0;
+  slaveEP3RxFifoSel <= 1'b0;
+  slaveEP3TxFifoSel <= 1'b0;
+  hostSlaveMuxSel <= 1'b0;
+  case (address & `ADDRESS_DECODE_MASK)
+    `HCREG_BASE : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HCREG_BASE_PLUS_0X10 : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HOST_RX_FIFO_BASE : begin
+      hostRxFifoSel <= 1'b1;
+      dataOut <= dataFromHostRxFifo;
+    end
+    `HOST_TX_FIFO_BASE : begin
+      hostTxFifoSel <= 1'b1;
+      dataOut <= dataFromHostTxFifo;
+    end
+    `SCREG_BASE : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `SCREG_BASE_PLUS_0X10 : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `EP0_RX_FIFO_BASE : begin
+      slaveEP0RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0RxFifo;
+    end
+    `EP0_TX_FIFO_BASE : begin
+      slaveEP0TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0TxFifo;
+    end
+    `EP1_RX_FIFO_BASE : begin
+      slaveEP1RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1RxFifo;
+    end
+    `EP1_TX_FIFO_BASE : begin
+      slaveEP1TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1TxFifo;
+    end
+    `EP2_RX_FIFO_BASE : begin
+      slaveEP2RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2RxFifo;
+    end
+    `EP2_TX_FIFO_BASE : begin
+      slaveEP2TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2TxFifo;
+    end
+    `EP3_RX_FIFO_BASE : begin
+      slaveEP3RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3RxFifo;
+    end
+    `EP3_TX_FIFO_BASE : begin
+      slaveEP3TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3TxFifo;
+    end
+    `HOST_SLAVE_CONTROL_BASE : begin
+      hostSlaveMuxSel <= 1'b1; 
+      dataOut <= dataFromHostSlaveMux;
+    end
+    default: 
+      dataOut <= 8'h00;
+  endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+  ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+  ack_immediate <= strobe_i;
+end 
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+  if (writeEn == 1'b0 &&
+      (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+  begin
+    ack_o <= ack_delayed;
+  end
+  else
+  begin
+    ack_o <= ack_immediate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.asf	(revision 264)
@@ -0,0 +1,287 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=259
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// getpacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 33
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
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+GRIDSIZE 0,0 10000,10000
+END
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+UPPERLEFT 0,0
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+UPPERLEFT 0,0
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+INSTHEADER 251
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
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+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "getPkt"
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+W 25 6 0 23 11 BEZIER "Transitions" | 103028,178064 102828,172064 102811,160604 102611,154604
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
+A 31 18 16 TEXT "Actions" | 117968,133698 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+                                         190292,107515 191648,100057 191987,92429 192326,84802\
+                                         192326,61750 188540,53162 184755,44574 169613,33274\
+                                         159556,30336 149499,27398 125714,27614 113171,27388
+C 43 41 0 TEXT "Conditions" | 74897,110510 1 0 0 "SIERxTimeOut == 1'b1"
+A 42 41 16 TEXT "Actions" | 81060,99034 1 0 0 "RXTimeOut <= 1'b1;"
+W 41 6 0 11 40 BEZIER "Transitions" | 96829,146625 92570,132664 92057,131084 90299,121915\
+                                      88541,112746 87971,105860 87641,93102 87312,80344\
+                                      87761,70127 92565,59363 97370,48599 95270,45542\
+                                      101102,30966
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+L 32 33 0 TEXT "State Labels" | 141010,72814 1 0 0 "PROC_PKT"
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141010,72814 6500 6500
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141270,86456 141068,79285
+C 35 34 0 TEXT "Conditions" | 122408,97630 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 59 46 0 49 54 BEZIER "Transitions" | 52133,248640 63746,242665 85368,230107 96981,224132
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+I 49 46 0 Builtin Entry | 47660,248640
+I 50 46 0 Builtin Exit | 180308,72140
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+I 76 72 0 Builtin Exit | 187140,27160
+I 75 72 0 Builtin Entry | 33260,254940
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nNAKRxed <= RXDataIn[`NAK_RXED_BIT];\nstallRxed <= RXDataIn[`STALL_RXED_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+W 87 72 0 75 80 BEZIER "Transitions" | 37733,254940 43032,249077 61954,258197 67253,252334
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177616,25344 184028,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176799,72082 177196,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n  RXPktStatus = { \n  dataSequence, ACKRxed, \n  stallRxed, NAKRxed,\n  RXTimeOut, RXOverflow, \n  bitStuffError, CRCError};\nend"
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+                                           57686,214631 75382,223396 84426,228258
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.asf	(revision 264)
@@ -0,0 +1,304 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=455
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hostController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 47
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 49
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 51
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+A 302 83 16 TEXT "Actions" | 127391,163104 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "clearTXReq <= 1'b0;\ntransDone <= 1'b0;\n//now wait for 'transReq' to clear"
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+                                        170250,145750 137550,145450 128737,144962 119925,144475\
+                                        117963,142662 116688,141837
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+I 56 52 0 Builtin Exit | 155694,46048
+I 55 52 0 Builtin Entry | 88756,239499
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+W 332 66 0 220 435 BEZIER "Transitions" | 82899,126626 83372,118876 55983,116868 40261,109385
+C 333 332 0 TEXT "Conditions" | 54763,123556 1 0 0 "sendPacketRdy == 1'b1"
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+                                          110726,37400 115182,37514 117348,37514
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+                                          129080,35838 133536,35952 135702,35952
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+I 365 73 0 Builtin Exit | 138662,35952
+I 366 73 0 Builtin Entry | 66816,246531
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+W 371 59 3 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+                                          40160,89849 37728,77233 37462,69633 37196,62033\
+                                          38564,44249 44378,36953 50192,29657 72080,18257\
+                                          79528,15331 86976,12405 94012,13028 97964,12876
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+I 96 6 0 Builtin Reset | 67359,192312
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+I 411 59 0 Builtin Exit | 100924,12876
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+                                          134254,207065 123583,209376 117848,210301
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+C 444 320 0 TEXT "Conditions" | 127768,183900 1 0 0 "sendPacketRdy == 1'b1"
+C 442 441 0 TEXT "Conditions" | 70632,78432 1 0 0 "isoEn == 1'b1"
+W 441 59 1 152 411 BEZIER "Transitions" | 80207,97867 74663,87703 63240,68436 60930,60120\
+                                          58620,51804 60468,38868 64038,33660 67608,28452\
+                                          80040,20556 84492,18330 88944,16104 95212,13380\
+                                          97900,12876
+W 440 66 2 435 216 BEZIER "Transitions" | 37283,96930 37450,86034 36933,64502 39250,56716\
+                                          41567,48930 50502,39578 58559,36864 66617,34151\
+                                          89914,32647 97658,32793 105403,32939 113545,36471\
+                                          117386,37514
+C 439 436 0 TEXT "Conditions" | 45200,98446 1 0 0 "isoEn == 1'b0"
+A 437 436 16 TEXT "Actions" | 45964,81812 1 0 0 "getPacketREn <= 1'b1;"
+W 436 66 1 435 331 BEZIER "Transitions" | 43135,99848 51564,83991 80050,72911 89986,72452
+S 435 66 147456 ELLIPSE "States" | 37700,103412 6500 6500
+L 434 435 0 TEXT "State Labels" | 37700,103412 1 0 0 "CHK_ISO\n/32/"
+I 433 0 2 Builtin InPort | 150555,227440 "" ""
+L 432 433 0 TEXT "Labels" | 156555,227440 1 0 0 "isoEn"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+L 445 446 0 TEXT "State Labels" | 91983,29847 1 0 0 "DEL1\n/33/"
+S 446 6 151552 ELLIPSE "States" | 91983,29847 6500 6500
+L 447 448 0 TEXT "State Labels" | 71118,38835 1 0 0 "DEL2\n/34/"
+S 448 6 155648 ELLIPSE "States" | 71118,38835 6500 6500
+W 451 6 0 294 446 BEZIER "Transitions" | 113064,28940 108490,29421 103055,29490 98481,29971
+W 452 6 0 446 448 BEZIER "Transitions" | 86012,32413 83123,33616 79949,35000 77060,36203
+W 454 6 0 448 41 BEZIER "Transitions" | 67046,43901 63355,51524 38215,83856 36770,94047\
+                                        35326,104238 36932,129759 42870,138987 48808,148215\
+                                        70958,159612 79745,162701 88532,165790 99731,166612\
+                                        106231,167093
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+I 215 66 0 Builtin Entry | 50996,240683
+I 216 66 0 Builtin Exit | 120308,37514
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.v	(revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   fullSpeedPolarity;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   [3:0]PID;
+input   rst;
+input   sendPacketWEn;
+input   [6:0]TxAddr;
+input   [3:0]TxEndP;
+output  fifoReadEn;
+output  [10:0]frameNum;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+reg     [10:0]frameNum, next_frameNum;
+wire    fullSpeedPolarity;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    [3:0]PID;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+wire    [6:0]TxAddr;
+wire    [3:0]TxEndP;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+`define LS_EOP_WAIT_RDY 5'b10101
+`define LS_EOP_FIN 5'b10110
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or fullSpeedPolarity or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+  NextState_sndPkt <= CurrState_sndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  next_frameNum <= frameNum;
+  case (CurrState_sndPkt)  // synopsys parallel_case full_case
+    `START_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+    end
+    `WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_sndPkt <= `SP_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `SP_WAIT_GNT:
+    begin
+      if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
+      begin
+        NextState_sndPkt <= `LS_EOP_WAIT_RDY;
+      end
+      else if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_HCTxPortReq <= 1'b0;
+    end
+    `SEND_PID_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= PIDNotPID;
+        next_HCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SEND_PID_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+      end
+      else if (PID == `SOF)
+      begin
+        NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+      end
+      else if (PID == `OUT || 
+        PID == `IN || 
+        PID == `SETUP)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sndPkt <= `FIN_SP;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY1:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY2:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `OUT_IN_SETUP_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+    end
+    `SEND_SOF_FIN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_frameNum <= frameNum + 1'b1;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `SEND_SOF_WAIT_RDY3:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= frameNum[7:0];
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_WAIT_RDY4:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_FIN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+    end
+    `DATA0_DATA1_READ_FIFO:
+    begin
+      next_HCTxPortWEn <= 1'b1;
+      next_HCTxPortData <= fifoData;
+      next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+    end
+    `DATA0_DATA1_WAIT_READ_FIFO:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `DATA0_DATA1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+      end
+    end
+    `DATA0_DATA1_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `DATA0_DATA1_TERM_BYTE:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `DATA0_DATA1_CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+    end
+    `DATA0_DATA1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+    end
+    `LS_EOP_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `LS_EOP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
+      end
+    end
+    `LS_EOP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sndPkt <= `START_SP;
+  else
+    CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    HCTxPortData <= 8'h00;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+    frameNum <= 11'h000;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+    frameNum <= next_frameNum;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.v	(revision 264)
@@ -0,0 +1,218 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketcheckpreamble
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   preAmbleEnable;
+input   rst;
+input   [3:0]sendPacketCPPID;
+input   sendPacketCPWEn;
+input   sendPacketRdy;
+output  sendPacketCPReady;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+
+wire    clk;
+wire    preAmbleEnable;
+wire    rst;
+wire    [3:0]sendPacketCPPID;
+reg     sendPacketCPReady, next_sendPacketCPReady;
+wire    sendPacketCPWEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_PREAM_SENT 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_PID_SENT 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+`define PREAM_PKT_WAIT_RDY2 4'b1100
+`define PREAM_PKT_WAIT_RDY3 4'b1101
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
+begin
+  NextState_sendPktCP <= CurrState_sendPktCP;
+  // Set default values for outputs and signals
+  next_sendPacketCPReady <= sendPacketCPReady;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  case (CurrState_sendPktCP)  // synopsys parallel_case full_case
+    `SPC_WAIT_EN:
+    begin
+      if (sendPacketCPWEn == 1'b1)
+      begin
+        NextState_sendPktCP <= `CHK_PREAM;
+        next_sendPacketCPReady <= 1'b0;
+      end
+    end
+    `START_SPC:
+    begin
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `CHK_PREAM:
+    begin
+      if (preAmbleEnable == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+      end
+    end
+    `READY:
+    begin
+      next_sendPacketCPReady <= 1'b1;
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `PREAM_PKT_SND_PREAM:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= `PREAMBLE;
+      NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
+    end
+    `PREAM_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+      end
+    end
+    `PREAM_PKT_PREAM_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+    end
+    `PREAM_PKT_SND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
+    end
+    `PREAM_PKT_PID_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+    end
+    `PREAM_PKT_WAIT_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+      end
+    end
+    `PREAM_PKT_WAIT_RDY3:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `READY;
+      end
+    end
+    `REG_PKT_SEND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+    end
+    `REG_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `REG_PKT_SEND_PID;
+      end
+    end
+    `REG_PKT_WAIT_RDY:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `READY;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktCP <= `START_SPC;
+  else
+    CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketCPReady <= 1'b1;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+  end
+  else 
+  begin
+    sendPacketCPReady <= next_sendPacketCPReady;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.v	(revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// softransmit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input   clk;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   SOFEnable;    // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input   SOFSyncEn;
+input   [15:0]SOFTimer;
+output  sendPacketArbiterReq;
+output  sendPacketWEn;
+output  SOFSent;    // single cycle pulse
+output  SOFTimerClr;    // Single cycle pulse
+
+wire    clk;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+wire    SOFEnable;
+reg     SOFSent, next_SOFSent;
+wire    SOFSyncEn;
+wire    [15:0]SOFTimer;
+reg     SOFTimerClr, next_SOFTimerClr;
+
+// diagram signals declarations
+reg  [7:0]i, next_i;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+`define DLY_SOF_CHK1 3'b101
+`define DLY_SOF_CHK2 3'b110
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or i or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+  NextState_SOFTx <= CurrState_SOFTx;
+  // Set default values for outputs and signals
+  next_SOFSent <= SOFSent;
+  next_SOFTimerClr <= SOFTimerClr;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_i <= i;
+  case (CurrState_SOFTx)  // synopsys parallel_case full_case
+    `START_STX:
+    begin
+      NextState_SOFTx <= `WAIT_SOF_NEAR;
+    end
+    `WAIT_SOF_NEAR:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+        (SOFSyncEn == 1'b1 &&
+        SOFEnable == 1'b1))
+      begin
+        NextState_SOFTx <= `WAIT_SP_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `WAIT_SP_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+      begin
+        NextState_SOFTx <= `WAIT_SOF_NOW;
+      end
+    end
+    `WAIT_SOF_NOW:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_sendPacketWEn <= 1'b1;
+        next_SOFTimerClr <= 1'b1;
+        next_SOFSent <= 1'b1;
+      end
+      else if (SOFEnable == 1'b0)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_SOFTimerClr <= 1'b1;
+      end
+    end
+    `SOF_FIN:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      next_SOFTimerClr <= 1'b0;
+      next_SOFSent <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_SOFTx <= `DLY_SOF_CHK1;
+        next_i <= 8'h00;
+      end
+    end
+    `DLY_SOF_CHK1:
+    begin
+      next_i <= i + 1'b1;
+      if (i==8'hff)
+      begin
+        NextState_SOFTx <= `DLY_SOF_CHK2;
+        next_sendPacketArbiterReq <= 1'b0;
+        next_i <= 8'h00;
+      end
+    end
+    `DLY_SOF_CHK2:
+    begin
+      next_i <= i + 1'b1;
+      if (i==8'hff)
+      begin
+        NextState_SOFTx <= `WAIT_SOF_NEAR;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SOFTx <= `START_STX;
+  else
+    CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFSent <= 1'b0;
+    SOFTimerClr <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketWEn <= 1'b0;
+    i <= 8'h00;
+  end
+  else 
+  begin
+    SOFSent <= next_SOFSent;
+    SOFTimerClr <= next_SOFTimerClr;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketWEn <= next_sendPacketWEn;
+    i <= next_i;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.v	(revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sofcontroller
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input   clk;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+input   SOFEnable;
+input   SOFTimerClr;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [15:0]SOFTimer;
+
+wire    clk;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+wire    SOFEnable;
+reg     [15:0]SOFTimer, next_SOFTimer;
+wire    SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+  NextState_sofCntl <= CurrState_sofCntl;
+  // Set default values for outputs and signals
+  next_SOFTimer <= SOFTimer;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_sofCntl)  // synopsys parallel_case full_case
+    `START_SC:
+    begin
+      NextState_sofCntl <= `WAIT_SOF_EN;
+    end
+    `WAIT_SOF_EN:
+    begin
+      if (SOFEnable == 1'b1)
+      begin
+        NextState_sofCntl <= `SC_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `WAIT_SEND_RESUME:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sofCntl <= `CLR_WEN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_RESUME_START;
+      end
+    end
+    `INC_TIMER:
+    begin
+      next_HCTxPortReq <= 1'b0;
+      if (SOFTimerClr == 1'b1)
+      next_SOFTimer <= 16'h0000;
+      else
+      next_SOFTimer <= SOFTimer + 1'b1;
+      if (SOFEnable == 1'b0)
+      begin
+        NextState_sofCntl <= `WAIT_SOF_EN;
+        next_SOFTimer <= 16'h0000;
+      end
+    end
+    `SC_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sofCntl <= `WAIT_SEND_RESUME;
+      end
+    end
+    `CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sofCntl <= `INC_TIMER;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sofCntl <= `START_SC;
+  else
+    CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFTimer <= 16'h0000;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SOFTimer <= next_SOFTimer;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/usbHostControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/usbHostControl.v	(revision 264)
@@ -0,0 +1,394 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostControl(
+  busClk, rstSyncToBusClk,
+  usbClk, rstSyncToUsbClk,
+  //sendPacket
+  TxFifoRE, TxFifoData, TxFifoEmpty,
+  //getPacket
+  RxFifoWE, RxFifoData, RxFifoFull,
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //HCTxPortArbiter
+  HCTxPortEn, HCTxPortRdy,
+  HCTxPortData, HCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFSentIntOut, 
+  connEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  hostControlSelect
+    );
+
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [3:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut; 
+output connEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+input hostControlSelect;
+
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut; 
+wire connEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire isoEn;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI 
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .SOFSentIntOut(SOFSentIntOut), 
+  .connEventIntOut(connEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .TxTransTypeReg(transType), 
+  .TxSOFEnableReg(SOFEnable),
+  .TxAddrReg(TxAddr), 
+  .TxEndPReg(TxEndP), 
+  .frameNumIn(frameNum), 
+  .RxPktStatusIn(RxPktStatus), 
+  .RxPIDIn(RxPID),
+  .connectStateIn(connectStateOut),
+  .SOFSentIn(SOFSent), 
+  .connEventIn(connectionEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .hostControlSelect(hostControlSelect),
+  .clrTransReq(clrTxReq),
+  .preambleEn(preAmbleEnable),
+  .SOFSync(SOFSyncEn),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .transReq(transReq),
+  .isoEn(isoEn),
+  .SOFTimer(SOFTimer)
+  );
+
+
+hostcontroller u_hostController
+  (.RXStatus(RxPktStatus), 
+  .clearTXReq(clrTxReq),
+  .clk(usbClk),
+  .getPacketREn(getPacketREn),
+  .getPacketRdy(getPacketRdy),
+  .rst(rstSyncToUsbClk),
+  .sendPacketArbiterGnt(HCTxGnt),
+  .sendPacketArbiterReq(HCTxReq),
+  .sendPacketPID(HC_PID),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(HC_SP_WEn),
+  .transDone(transDone),
+  .transReq(transReq),
+  .transType(transType),
+  .isoEn(isoEn) );
+
+SOFController u_SOFController
+  (.HCTxPortCntl(SOFCntlCntl),
+  .HCTxPortData(SOFCntlData),
+  .HCTxPortGnt(SOFCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(SOFCntlReq),
+  .HCTxPortWEn(SOFCntlWEn),
+  .SOFEnable(SOFEnable),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk) ); 
+
+SOFTransmit u_SOFTransmit
+  (.SOFEnable(SOFEnable),
+  .SOFSent(SOFSent),
+  .SOFSyncEn(SOFSyncEn),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk),
+  .sendPacketArbiterGnt(SOFTxGnt),
+  .sendPacketArbiterReq(SOFTxReq),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(SOF_SP_WEn) );  
+
+
+sendPacketArbiter u_sendPacketArbiter
+  (.HCTxGnt(HCTxGnt),
+  .HCTxReq(HCTxReq),
+  .HC_PID(HC_PID),
+  .HC_SP_WEn(HC_SP_WEn),
+  .SOFTxGnt(SOFTxGnt),
+  .SOFTxReq(SOFTxReq),
+  .SOF_SP_WEn(SOF_SP_WEn),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk),
+  .sendPacketPID(sendPacketCPPIDIn),
+  .sendPacketWEnable(sendPacketCPWEnIn) );    
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+  (.sendPacketCPPID(sendPacketCPPIDIn),
+  .clk(usbClk),
+  .preAmbleEnable(preAmbleEnable),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCPReady(sendPacketCPReadyOut),
+  .sendPacketCPWEn(sendPacketCPWEnIn),
+  .sendPacketPID(sendPacketCPPIDOut),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+  (.HCTxPortCntl(sendPacketCntl),
+  .HCTxPortData(sendPacketData),
+  .HCTxPortGnt(sendPacketGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(sendPacketReq),
+  .HCTxPortWEn(sendPacketWEn),
+  .PID(sendPacketCPPIDOut),
+  .TxAddr(TxAddr),
+  .TxEndP(TxEndP),
+  .clk(usbClk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .frameNum(frameNum),
+  .rst(rstSyncToUsbClk),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut),
+  .fullSpeedPolarity(fullSpeedPol) );
+  
+directControl u_directControl
+  (.HCTxPortCntl(directCntlCntl),
+  .HCTxPortData(directCntlData),
+  .HCTxPortGnt(directCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(directCntlReq),
+  .HCTxPortWEn(directCntlWEn),
+  .clk(usbClk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rstSyncToUsbClk) ); 
+
+HCTxPortArbiter u_HCTxPortArbiter
+  (.HCTxPortCntl(HCTxPortCtrl),
+  .HCTxPortData(HCTxPortData),
+  .HCTxPortWEnable(HCTxPortEn),
+  .SOFCntlCntl(SOFCntlCntl),
+  .SOFCntlData(SOFCntlData),
+  .SOFCntlGnt(SOFCntlGnt),
+  .SOFCntlReq(SOFCntlReq),
+  .SOFCntlWEn(SOFCntlWEn),
+  .clk(usbClk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+getPacket u_getPacket
+  (.RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXPktStatus(RxPktStatus),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .clk(usbClk),
+  .getPacketEn(getPacketREn),
+  .rst(rstSyncToUsbClk) ); 
+
+rxStatusMonitor  u_rxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .connectionEventOut(connectionEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostControl_h.v	(revision 264)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v                                          
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HOST_SOF_TIMER_MSB_REG 4'hf
+
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+`define ISO_ENABLE_BIT 3
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+ 
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants 
+//`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval   
+//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer 
+`define SOF_TX_TIME 16'hbb7d     //Correct SOF interval for 48MHz clock.
+//`define SOF_TX_MARGIN 2 
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+       
+//Host RXStatusRegIndices 
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined 

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/wishBoneBus_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/wishBoneBus_h.v	(revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+ 
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/USBHostControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/USBHostControlBI.v	(revision 264)
@@ -0,0 +1,380 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBHostControlBI.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbHostControl_h.v"
+ 
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+  TxTransTypeReg, TxSOFEnableReg,
+  TxAddrReg, TxEndPReg, frameNumIn, 
+  RxPktStatusIn, RxPIDIn,
+  connectStateIn,
+  SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+  hostControlSelect,
+  clrTransReq,
+  preambleEn,
+  SOFSync,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  transReq,
+  isoEn,
+  SOFTimer
+  );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output transReq;
+output isoEn;     //enable isochronous mode
+input [15:0] SOFTimer;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg transReq;
+reg isoEn;
+wire [15:0] SOFTimer;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [1:0] TxTransTypeRegSTB;
+reg TxSOFEnableRegSTB;
+reg [6:0] TxAddrRegSTB;
+reg [3:0] TxEndPRegSTB;
+reg preambleEnSTB;
+reg SOFSyncSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB; 
+reg fullSpeedRateSTB;
+reg transReqSTB;
+reg isoEnSTB;   
+reg [10:0] frameNumInSTB;
+reg [7:0] RxPktStatusInSTB;
+reg [3:0] RxPIDInSTB;
+reg [1:0] connectStateInSTB;
+reg SOFSentInSTB;
+reg connEventInSTB;
+reg resumeIntInSTB;
+reg transDoneInSTB;
+reg clrTransReqSTB;
+reg [15:0] SOFTimerSTB;
+
+  
+//sync write demux
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    isoEnSTB <= 1'b0;
+    preambleEnSTB <= 1'b0;
+    SOFSyncSTB <= 1'b0;
+    TxTransTypeRegSTB <= 2'b00;
+    TxLineControlReg <= 5'h00;
+    TxSOFEnableRegSTB <= 1'b0;
+    TxAddrRegSTB <= 7'h00;
+    TxEndPRegSTB <= 4'h0;
+    interruptMaskReg <= 4'h0;
+  end
+  else begin
+    clrSOFReq <= 1'b0;
+    clrConnEvtReq <= 1'b0;
+    clrResInReq <= 1'b0;
+    clrTransDoneReq <= 1'b0;
+    setTransReq <= 1'b0;
+    if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+    begin
+      case (address)
+        `TX_CONTROL_REG : begin
+          isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
+          preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
+          SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
+          setTransReq <= dataIn[`TRANS_REQ_BIT];
+        end
+        `TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
+        `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+        `TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
+        `TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
+        `TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
+        `INTERRUPT_STATUS_REG :  begin
+          clrSOFReq <= dataIn[`SOF_SENT_BIT];
+          clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
+          clrResInReq <= dataIn[`RESUME_INT_BIT];
+          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+        end
+        `INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[3:0];
+      endcase
+    end 
+  end
+end
+
+//interrupt control
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    SOFSentInt <= 1'b0;
+    connEventInt <= 1'b0;
+    resumeInt <= 1'b0;
+    transDoneInt <= 1'b0;
+  end
+  else begin
+    if (SOFSentInSTB == 1'b1)
+      SOFSentInt <= 1'b1;
+    else if (clrSOFReq == 1'b1)
+      SOFSentInt <= 1'b0;
+    
+    if (connEventInSTB == 1'b1)
+      connEventInt <= 1'b1;
+    else if (clrConnEvtReq == 1'b1)
+      connEventInt <= 1'b0;
+    
+    if (resumeIntInSTB == 1'b1)
+      resumeInt <= 1'b1;
+    else if (clrResInReq == 1'b1)
+      resumeInt <= 1'b0;  
+
+    if (transDoneInSTB == 1'b1)
+      transDoneInt <= 1'b1;
+    else if (clrTransDoneReq == 1'b1)
+      transDoneInt <= 1'b0;
+  end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end  
+  
+//transaction request set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'setTransReq' must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the transaction request is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'transReq' and sampling of related control signals.always @(posedge busClk)
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    transReqSTB <= 1'b0;
+  end
+  else begin
+    if (setTransReq == 1'b1)
+      transReqSTB <= 1'b1;
+    else if (clrTransReqSTB == 1'b1)
+      transReqSTB <= 1'b0;
+  end
+end  
+  
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+  TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+  LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+  fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+  
+// async read mux
+always @(address or
+  TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
+  TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or 
+  SOFSentInt or connEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
+  preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimer)
+begin
+  case (address)
+      `TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
+      `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
+      `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+      `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
+      `TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
+      `TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
+      `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
+      `FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
+      `INTERRUPT_STATUS_REG :  dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+      `INTERRUPT_MASK_REG  : dataOut <= {4'h0, interruptMaskReg};
+      `RX_STATUS_REG  : dataOut <= RxPktStatusInSTB;
+      `RX_PID_REG  : dataOut <= {4'b0000, RxPIDInSTB};
+      `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
+      `HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimer[15:8];
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+//re-sync from busClk to usbClk. 
+always @(posedge usbClk) begin
+  if (rstSyncToUsbClk == 1'b1) begin
+    isoEn <= 1'b0;
+    preambleEn <= 1'b0;
+    SOFSync <= 1'b0;
+    TxTransTypeReg <= 2'b00;
+    TxSOFEnableReg <= 1'b0;
+    TxAddrReg <= 7'h00;
+    TxEndPReg <= 4'h0;
+    TxLineState <= 2'b00;
+    LineDirectControlEn <= 1'b0;
+    fullSpeedPol <= 1'b0; 
+    fullSpeedRate <= 1'b0;
+    transReq <= 1'b0;
+  end
+  else begin
+    isoEn <= isoEnSTB;     
+    preambleEn <= preambleEnSTB;
+    SOFSync <= SOFSyncSTB;
+    TxTransTypeReg <= TxTransTypeRegSTB;
+    TxSOFEnableReg <= TxSOFEnableRegSTB;
+    TxAddrReg <= TxAddrRegSTB;
+    TxEndPReg <= TxEndPRegSTB;
+    TxLineState <= TxLineStateSTB;
+    LineDirectControlEn <= LineDirectControlEnSTB;
+    fullSpeedPol <= fullSpeedPolSTB; 
+    fullSpeedRate <= fullSpeedRateSTB;
+    transReq <= transReqSTB;
+  end
+end
+
+//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted 
+//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
+always @(posedge busClk) begin
+  frameNumInSTB <= frameNumIn;
+  RxPktStatusInSTB <= RxPktStatusIn;
+  RxPIDInSTB <= RxPIDIn;
+  connectStateInSTB <= connectStateIn;
+  SOFSentInSTB <= SOFSentIn;
+  connEventInSTB <= connEventIn;
+  resumeIntInSTB <= resumeIntIn;
+  transDoneInSTB <= transDoneIn;
+  clrTransReqSTB <= clrTransReq;
+  SOFTimerSTB <= SOFTimer;
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.v	(revision 264)
@@ -0,0 +1,397 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// getpacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut);
+input   clk;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  [7:0]RXPktStatus;
+
+wire    clk;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+reg     [7:0]RXPktStatus;
+wire    [7:0]RXStreamStatusIn;
+wire    SIERxTimeOut;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_getPkt)
+begin
+  NextState_getPkt <= CurrState_getPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  case (CurrState_getPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      if (SIERxTimeOut == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_getPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_getPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_getPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+        next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_getPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (RXFifoFull == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_getPkt <= `START_GP;
+  else
+    CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RxPID <= 4'h0;
+    RXOverflow <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXByteOld <= 8'h00;
+    RXTimeOut <= 1'b0;
+  end
+  else 
+  begin
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RxPID <= next_RxPID;
+    RXOverflow <= next_RXOverflow;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXByteOld <= next_RXByteOld;
+    RXTimeOut <= next_RXTimeOut;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.v	(revision 264)
@@ -0,0 +1,447 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, isoEn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input   clk;
+input   getPacketRdy;
+input   isoEn;
+input   rst;
+input   [7:0]RXStatus;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   transReq;
+input   [1:0]transType;
+output  clearTXReq;
+output  getPacketREn;
+output  sendPacketArbiterReq;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  transDone;
+
+reg     clearTXReq, next_clearTXReq;
+wire    clk;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+wire    isoEn;
+wire    rst;
+wire    [7:0]RXStatus;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     transDone, next_transDone;
+wire    transReq;
+wire    [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 6'b000000
+`define TX_REQ 6'b000001
+`define CHK_TYPE 6'b000010
+`define FLAG 6'b000011
+`define IN_WAIT_DATA_RXED 6'b000100
+`define IN_CHK_FOR_ERROR 6'b000101
+`define IN_CLR_SP_WEN2 6'b000110
+`define SETUP_CLR_SP_WEN1 6'b000111
+`define SETUP_CLR_SP_WEN2 6'b001000
+`define FIN 6'b001001
+`define WAIT_GNT 6'b001010
+`define SETUP_WAIT_PKT_RXED 6'b001011
+`define IN_WAIT_IN_SENT 6'b001100
+`define OUT0_WAIT_RX_DATA 6'b001101
+`define OUT0_WAIT_DATA0_SENT 6'b001110
+`define OUT0_WAIT_OUT_SENT 6'b001111
+`define SETUP_HC_WAIT_RDY 6'b010000
+`define IN_WAIT_SP_RDY1 6'b010001
+`define IN_WAIT_SP_RDY2 6'b010010
+`define OUT0_WAIT_SP_RDY1 6'b010011
+`define SETUP_WAIT_SETUP_SENT 6'b010100
+`define SETUP_WAIT_DATA_SENT 6'b010101
+`define IN_CLR_SP_WEN1 6'b010110
+`define IN_WAIT_ACK_SENT 6'b010111
+`define OUT0_CLR_WEN1 6'b011000
+`define OUT0_CLR_WEN2 6'b011001
+`define OUT1_WAIT_RX_DATA 6'b011010
+`define OUT1_WAIT_OUT_SENT 6'b011011
+`define OUT1_WAIT_DATA1_SENT 6'b011100
+`define OUT1_WAIT_SP_RDY1 6'b011101
+`define OUT1_CLR_WEN1 6'b011110
+`define OUT1_CLR_WEN2 6'b011111
+`define OUT0_CHK_ISO 6'b100000
+`define DEL1 6'b100001
+`define DEL2 6'b100010
+
+reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or isoEn or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+  NextState_hstCntrl <= CurrState_hstCntrl;
+  // Set default values for outputs and signals
+  next_transDone <= transDone;
+  next_clearTXReq <= clearTXReq;
+  next_getPacketREn <= getPacketREn;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketPID <= sendPacketPID;
+  next_sendPacketWEn <= sendPacketWEn;
+  case (CurrState_hstCntrl)  // synopsys parallel_case full_case
+    `START_HC:
+    begin
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `TX_REQ:
+    begin
+      if (transReq == 1'b1)
+      begin
+        NextState_hstCntrl <= `WAIT_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `CHK_TYPE:
+    begin
+      if (transType == `OUTDATA0_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+      end
+      else if (transType == `IN_TRANS)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+      end
+      else if (transType == `SETUP_TRANS)
+      begin
+        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+      end
+      else if (transType == `OUTDATA1_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+      end
+    end
+    `FLAG:
+    begin
+      next_transDone <= 1'b1;
+      next_clearTXReq <= 1'b1;
+      next_sendPacketArbiterReq <= 1'b0;
+      NextState_hstCntrl <= `FIN;
+    end
+    `FIN:
+    begin
+      next_clearTXReq <= 1'b0;
+      next_transDone <= 1'b0;
+      //now wait for 'transReq' to clear
+      NextState_hstCntrl <= `DEL1;
+    end
+    `WAIT_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1)
+      begin
+        NextState_hstCntrl <= `CHK_TYPE;
+      end
+    end
+    `DEL1:
+    begin
+      NextState_hstCntrl <= `DEL2;
+    end
+    `DEL2:
+    begin
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `SETUP_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+    end
+    `SETUP_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+    end
+    `SETUP_WAIT_PKT_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `SETUP_HC_WAIT_RDY:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `SETUP;
+      end
+    end
+    `SETUP_WAIT_SETUP_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `SETUP_WAIT_DATA_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_DATA_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+      end
+    end
+    `IN_CHK_FOR_ERROR:
+    begin
+      if (isoEn == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+      else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+      end
+      else
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `IN_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+    end
+    `IN_WAIT_IN_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `IN;
+      end
+    end
+    `IN_WAIT_SP_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `IN_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+    end
+    `IN_WAIT_ACK_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_DATA0_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CHK_ISO;
+      end
+    end
+    `OUT0_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `OUT0_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT0_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+    end
+    `OUT0_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+    end
+    `OUT0_CHK_ISO:
+    begin
+      if (isoEn == 1'b0)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+      else
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT1_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT1_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `OUT1_WAIT_DATA1_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `OUT1_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT1_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+    end
+    `OUT1_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_hstCntrl <= `START_HC;
+  else
+    CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    transDone <= 1'b0;
+    clearTXReq <= 1'b0;
+    getPacketREn <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketPID <= 4'b0;
+    sendPacketWEn <= 1'b0;
+  end
+  else 
+  begin
+    transDone <= next_transDone;
+    clearTXReq <= next_clearTXReq;
+    getPacketREn <= next_getPacketREn;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketPID <= next_sendPacketPID;
+    sendPacketWEn <= next_sendPacketWEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketarbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 0 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "HC_ACT\n/0/"
+S 13 6 4096 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "SOF_ACT\n/1/"
+S 11 6 8192 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "SARB_WAIT_REQ\n/2/"
+S 9 6 12288 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_SARB\n/3/"
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+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "HCTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b0;"
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+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "SOFTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b1;"
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+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
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+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)  \nbegin\n  if (muxSOFNotHC  == 1'b1)  \n  begin\n    sendPacketWEnable <= SOF_SP_WEn;\n    sendPacketPID <= `SOF;\n  end\n  else\n  begin\n    sendPacketWEnable <= HC_SP_WEn;\n    sendPacketPID <= HC_PID;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "SOFTxGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+                                      70311,70629 71874,86691 76817,93064 81761,99437\
+                                      89642,107471 97173,106158 104705,104845 116882,95874\
+                                      123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "HCTxGnt <= 1'b0;"
+I 85 0 2 Builtin InPort | 38222,167883 "" ""
+L 86 85 0 TEXT "Labels" | 44222,167883 1 0 0 "HC_SP_WEn"
+I 89 0 2 Builtin InPort | 92234,162554 "" ""
+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sofcontroller\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: SOFController"
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+L 10 11 0 TEXT "State Labels" | 102510,174880 1 0 0 "WAIT_SOF_EN\n/1/"
+S 11 6 4096 ELLIPSE "States" | 102510,174880 6500 6500
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+I 13 6 0 Builtin Reset | 56682,217090
+W 14 6 0 13 9 BEZIER "Transitions" | 56682,217090 66531,215181 85597,210696 95446,208787
+L 15 16 0 TEXT "Labels" | 186096,262516 1 0 0 "clk"
+I 16 0 3 Builtin InPort | 180096,262516 "" ""
+L 17 18 0 TEXT "Labels" | 185694,255682 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 179694,255682 "" ""
+C 19 14 0 TEXT "Conditions" | 80380,211899 1 0 0 "rst"
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+C 27 25 0 TEXT "Conditions" | 106980,134689 1 0 0 "HCTxPortRdy == 1'b1"
+A 29 25 16 TEXT "Actions" | 99582,127475 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_RESUME_START;"
+A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n  SOFTimer <= 16'h0000;\nelse\n  SOFTimer <= SOFTimer + 1'b1;"
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+                                      64755,81944 65727,99405 63767,113072 61807,126740\
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+                                      86530,192015 91053,190659 96125,183689 98738,180172
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+L 36 37 0 TEXT "Labels" | 26502,239200 1 0 0 "SOFTimer[15:0]"
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+I 39 0 2 Builtin InPort | 22914,244024 "" ""
+L 40 41 0 TEXT "Labels" | 90018,239200 1 0 0 "HCTxPortRdy"
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+I 44 0 130 Builtin OutPort | 81915,250446 "" ""
+L 45 44 0 TEXT "Labels" | 87915,250446 1 0 0 "HCTxPortData[7:0]"
+I 46 0 130 Builtin OutPort | 81312,256878 "" ""
+L 47 46 0 TEXT "Labels" | 87312,256878 1 0 0 "HCTxPortCntl[7:0]"
+I 60 0 2 Builtin InPort | 23316,251905 "" ""
+L 59 60 0 TEXT "Labels" | 29316,251905 1 0 0 "SOFTimerClr"
+A 48 9 2 TEXT "Actions" | 121328,217354 1 0 0 "SOFTimer <= 16'h0000;\nHCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+L 49 50 0 TEXT "State Labels" | 162077,151882 1 0 0 "SC_WAIT_GNT\n/4/"
+S 50 6 16384 ELLIPSE "States" | 162077,151882 6500 6500
+W 51 6 0 50 21 BEZIER "Transitions" | 155785,150253 143926,148645 122475,143375 110616,144581
+C 52 51 0 TEXT "Conditions" | 129444,145489 1 0 0 "HCTxPortGnt == 1'b1"
+A 53 22 16 TEXT "Actions" | 118898,162608 1 0 0 "HCTxPortReq <= 1'b1;"
+A 54 33 16 TEXT "Actions" | 41502,87168 1 0 0 "SOFTimer <= 16'h0000;"
+L 55 56 0 TEXT "Labels" | 139062,239200 1 0 0 "HCTxPortReq"
+I 56 0 2 Builtin OutPort | 133062,239200 "" ""
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+I 58 0 2 Builtin InPort | 135474,244024 "" ""
+L 61 62 0 TEXT "State Labels" | 118352,95112 1 0 0 "CLR_WEN\n/5/"
+S 62 6 20480 ELLIPSE "States" | 118352,95112 6500 6500
+A 63 62 4 TEXT "Actions" | 137072,99272 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 64 6 0 62 24 BEZIER "Transitions" | 116496,88885 114624,81865 110713,68112 108841,61092
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/speedCtrlMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/speedCtrlMux.v	(revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// speedCtrlMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input   directCtrlRate;
+input   directCtrlPol;
+input   sendPacketRate;
+input   sendPacketPol;
+input   sendPacketSel;
+output  fullSpeedRate;
+output  fullSpeedPol;
+
+wire   directCtrlRate;
+wire   directCtrlPol;
+wire   sendPacketRate;
+wire   sendPacketPol;
+wire   sendPacketSel;
+reg   fullSpeedRate;
+reg   fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+  if (sendPacketSel == 1'b1) 
+  begin
+  fullSpeedRate <= sendPacketRate;
+  fullSpeedPol <= sendPacketPol;
+  end
+  else
+  begin
+  fullSpeedRate <= directCtrlRate;
+  fullSpeedPol <= directCtrlPol;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbConstants_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbConstants_h.v	(revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v                                             
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc 
+     
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined       
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSlaveControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSlaveControl_h.v	(revision 264)
@@ -0,0 +1,81 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v                                           
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants 
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices 
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices 
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices 
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+`define ENDPOINT_ISO_ENABLE_BIT 4
+//SCMasterControlegIndices 
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices 
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes 
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts 
+`define SC_RX_PACKET_TOUT 18
+       
+`endif //usbSlaveControl_h_vdefined  

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMuxBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMuxBI.v	(revision 264)
@@ -0,0 +1,125 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMuxBI.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbHostSlave_h.v"
+
+module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
+  hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+wire rstFromWire;
+reg rstSyncToBusClkOut;
+reg rstSyncToUsbClkOut;
+
+//internal wire and regs
+reg [5:0] rstShift;
+reg rstFromBus;
+reg rstSyncToUsbClkFirst;
+
+//sync write demux
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClkOut == 1'b1)
+    hostMode <= 1'b0;
+  else begin
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+      hostMode <= dataIn[0];
+    end
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
+      rstFromBus <= 1'b1;
+    else
+      rstFromBus <= 1'b0;
+end
+
+// async read mux
+always @(address or hostMode)
+begin
+  case (address)
+    `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+    `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+  endcase
+end
+
+// reset control
+//generate 'rstSyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+  if (rstFromWire == 1'b1 || rstFromBus == 1'b1) 
+    rstShift <= 6'b111111;
+  else
+    rstShift <= {1'b0, rstShift[5:1]};
+end
+
+always @(rstShift)
+  rstSyncToBusClkOut <= rstShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+    rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
+    rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
+end
+
+endmodule

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSerialInterfaceEngine_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSerialInterfaceEngine_h.v	(revision 264)
@@ -0,0 +1,103 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v                                
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+`define TX_LS_KEEP_ALIVE 8'h06
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+// RESUME_RX_WAIT_TIME defines the time period for resume detection
+// The resume counter is incremented at the bit rate, so
+// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
+// and 30 * 1/1.5MHz =  20uS at low speed, both of which are within the USB spec of 
+// 2.5uS <= resumeDetectTime <= 100uS
+`define RESUME_RX_WAIT_TIME 5'd29
+//`define RESUME_WAIT_TIME_MINUS1 9
+// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate 
+`define HOST_TX_RESUME_TIME 16'd30000  //Host sends resume for 30000 * 1/1.5MHz = 20mS
+//`define CONNECT_WAIT_TIME 8'd20
+`define CONNECT_WAIT_TIME 8'd120      //Device connect detected after 120 * 1/48MHz = 2.5uS
+//`define DISCONNECT_WAIT_TIME 8'd20   
+`define DISCONNECT_WAIT_TIME 8'd120   //Device disconnect detected after 120 * 1/48MHz = 2.5uS
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates 
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_00_07_alpha/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_00_07_alpha/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifoBI.v	(revision 264)
@@ -0,0 +1,148 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+  address, 
+  writeEn, 
+  strobe_i,
+  busClk, 
+  usbClk, 
+  rstSyncToBusClk, 
+  fifoSelect,
+  fifoDataIn,
+  busDataIn, 
+  busDataOut,
+  fifoREn,
+  forceEmptySyncToUsbClk,
+  forceEmptySyncToBusClk,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoREn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoREn;
+reg forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg [5:0] forceEmptyShift;
+reg forceEmpty;
+reg forceEmptySyncToUsbClkFirst;
+
+//sync write
+always @(posedge busClk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+    address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+//generate 'forceEmptySyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) 
+    forceEmptyShift <= 6'b000000;
+  else begin
+    if (forceEmpty == 1'b1)
+      forceEmptyShift <= 6'b111111;
+    else
+      forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
+  end
+end
+assign forceEmptySyncToBusClk = forceEmptyShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+    forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
+    forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
+end
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo)
+begin
+  case (address)
+      `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00; 
+  endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b0 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoREn <= 1'b1;
+  else
+    fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/buffers/fifoRTL.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/buffers/fifoRTL.v	(revision 264)
@@ -0,0 +1,164 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoRTL.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized dual clock domain fifo. 
+////  fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn, 
+  dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty,
+  forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+
+// Two clock domains within this module
+// These ports are within 'wrClk' domain
+input wrClk;
+input rstSyncToWrClk;
+input [FIFO_WIDTH-1:0] dataIn;
+input fifoWEn;
+input forceEmptySyncToWrClk;
+output fifoFull;
+
+// These ports are within 'rdClk' domain
+input rdClk;
+input rstSyncToRdClk;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoREn;
+input forceEmptySyncToRdClk;
+output fifoEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire wrClk;
+wire rdClk;
+wire rstSyncToWrClk;
+wire rstSyncToRdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg  [15:0]numElementsInFifo;
+
+
+// local registers
+reg  [ADDR_WIDTH:0]bufferInIndex; 
+reg  [ADDR_WIDTH:0]bufferInIndexSyncToRdClk;
+reg  [ADDR_WIDTH:0]bufferOutIndex;
+reg  [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk;
+reg  [ADDR_WIDTH-1:0]bufferInIndexToMem;
+reg  [ADDR_WIDTH-1:0]bufferOutIndexToMem;
+reg  [ADDR_WIDTH:0]bufferCnt;
+reg  fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge wrClk)
+begin
+  bufferOutIndexSyncToWrClk <= bufferOutIndex;
+  if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1)
+  begin
+    fifoFull <= 1'b0;
+    bufferInIndex <= 0;
+  end
+    else
+    begin
+      if (fifoWEn == 1'b1) begin
+        bufferInIndex <= bufferInIndex + 1'b1;
+      end 
+      if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
+          (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
+        fifoFull <= 1'b1;
+      else
+        fifoFull <= 1'b0;
+    end
+end
+
+always @(bufferInIndexSyncToRdClk or bufferOutIndex) 
+  bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
+
+always @(posedge rdClk)
+begin
+  numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes
+  bufferInIndexSyncToRdClk <= bufferInIndex;
+  if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1)
+  begin
+    fifoEmpty <= 1'b1;
+    bufferOutIndex <= 0;
+    fifoREnDelayed <= 1'b0;
+  end
+    else
+    begin
+      fifoREnDelayed <= fifoREn;
+      if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        dataOut <= dataFromMem;
+        bufferOutIndex <= bufferOutIndex + 1'b1;
+      end
+      if (bufferInIndexSyncToRdClk == bufferOutIndex) 
+        fifoEmpty <= 1'b1;
+      else
+        fifoEmpty <= 1'b0;
+    end
+end
+
+
+always @(bufferInIndex or bufferOutIndex) begin
+  bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
+  bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
+end
+
+dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_dpMem_dc (
+  .addrIn(bufferInIndexToMem),
+  .addrOut(bufferOutIndexToMem),
+  .wrClk(wrClk),
+  .rdClk(rdClk),
+  .dataIn(dataIn),
+  .writeEn(fifoWEn),
+  .readEn(fifoREn),
+  .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.v	(revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// directControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+  NextState_drctCntl <= CurrState_drctCntl;
+  // Set default values for outputs and signals
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_drctCntl)  // synopsys parallel_case full_case
+    `START_DC:
+    begin
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_drctCntl <= `CHK_DRCT_CNTL;
+        next_HCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {6'b000000, directControlLineState};
+        next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_HCTxPortReq <= 1'b0;
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_drctCntl <= `START_DC;
+  else
+    CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.v	(revision 264)
@@ -0,0 +1,242 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hctxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hctxportarbiter.v,v 1.2 2004-12-18 14:36:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+input   [7:0]SOFCntlCntl;
+input   [7:0]SOFCntlData;
+input   SOFCntlReq;
+input   SOFCntlWEn;
+output  directCntlGnt;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortWEnable;
+output  sendPacketGnt;
+output  SOFCntlGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+reg     HCTxPortWEnable, next_HCTxPortWEnable;
+wire    rst;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+wire    [7:0]SOFCntlCntl;
+wire    [7:0]SOFCntlData;
+reg     SOFCntlGnt, next_SOFCntlGnt;
+wire    SOFCntlReq;
+wire    SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg  [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+  NextState_HCTxArb = CurrState_HCTxArb;
+  // Set default values for outputs and signals
+  next_SOFCntlGnt <= SOFCntlGnt;
+  next_sendPacketGnt <= sendPacketGnt;
+  next_directCntlGnt <= directCntlGnt;
+  next_muxCntl <= muxCntl;
+  case (CurrState_HCTxArb)  // synopsys parallel_case full_case
+    `START_HARB:
+    begin
+      NextState_HCTxArb = `WAIT_REQ;
+    end
+    `WAIT_REQ:
+    begin
+      if (SOFCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb = `SEND_SOF;
+        next_SOFCntlGnt <= 1'b1;
+        next_muxCntl <= `SOF_CTRL_MUX;
+      end
+      else if (sendPacketReq == 1'b1)
+      begin
+        NextState_HCTxArb = `SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxCntl <= `SEND_PACKET_MUX;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb = `DIRECT_CONTROL;
+        next_directCntlGnt <= 1'b1;
+        next_muxCntl <= `DIRECT_CTRL_MUX;
+      end
+    end
+    `SEND_SOF:
+    begin
+      if (SOFCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_SOFCntlGnt <= 1'b0;
+      end
+    end
+    `SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `DIRECT_CONTROL:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb = `WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_HCTxArb = `START_HARB;
+  else
+    CurrState_HCTxArb = NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFCntlGnt = 1'b0;
+    sendPacketGnt = 1'b0;
+    directCntlGnt = 1'b0;
+    muxCntl = 2'b00;
+  end
+  else 
+  begin
+    SOFCntlGnt = next_SOFCntlGnt;
+    sendPacketGnt = next_sendPacketGnt;
+    directCntlGnt = next_directCntlGnt;
+    muxCntl = next_muxCntl;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.asf	(revision 264)
@@ -0,0 +1,285 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=260
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
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+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+I 110 58 0 Builtin Exit | 176204,35771
+I 111 58 0 Builtin Entry | 69864,225148
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1;	 \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127618,200894 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+                                          48213,88528 42471,75064 41184,67490 39897,59917\
+                                          40491,43087 47668,36800 54846,30514 82962,22198\
+                                          91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+                                          200128,135446 205472,144130 205681,151728 205890,159327\
+                                          201380,181037 194241,189595 187102,198154 163054,210680\
+                                          152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+H 229 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 227 6 102420 ELLIPSE "Junction" | 165212,109319 3500 3500
+L 228 227 0 TEXT "State Labels" | 165212,109319 1 0 0 "J1"
+I 230 229 0 Builtin Entry | 86360,167640
+I 231 229 0 Builtin Exit | 129540,111760
+W 232 229 0 230 231 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+L 233 234 0 TEXT "Labels" | 162660,245408 1 0 0 "fullSpeedPolarity"
+I 234 0 2 Builtin InPort | 156660,245408 "" ""
+L 235 236 0 TEXT "State Labels" | 198623,87106 1 0 0 "LS_EOP"
+S 236 6 106500 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 198623,87106 6500 6500
+W 237 6 1 227 236 BEZIER "Transitions" | 168384,107842 175000,104995 188420,97278 193251,90764
+W 238 6 2 227 21 BEZIER "Transitions" | 161819,108462 150848,105699 131009,99230 120038,96467
+W 239 6 0 236 47 BEZIER "Transitions" | 199566,80679 201782,68823 204064,53250 203352,44331\
+                                        202640,35412 197280,23183 191376,19540 185472,15898\
+                                        167213,13552 158043,13342 148873,13133 131482,15160\
+                                        122270,15913
+C 240 237 0 TEXT "Conditions" | 144637,101038 1 0 0 "PID == `SOF && fullSpeedPolarity == 1'b0"
+H 241 236 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 248 241 110592 ELLIPSE "States" | 84074,210161 6500 6500
+L 249 248 0 TEXT "State Labels" | 84074,210864 1 0 0 "WAIT_RDY\n/21/"
+I 250 241 0 Builtin Entry | 60577,248468
+I 251 241 0 Builtin Exit | 157344,113693
+W 252 241 0 250 248 BEZIER "Transitions" | 64714,248468 68921,238227 72224,227202 80510,215594
+S 253 241 114688 ELLIPSE "States" | 86361,171124 6500 6500
+L 254 253 0 TEXT "State Labels" | 86361,171124 1 0 0 "FIN\n/22/"
+W 255 241 0 248 253 BEZIER "Transitions" | 84293,203686 84642,196968 85300,184294 85649,177576
+C 256 255 0 TEXT "Conditions" | 86576,203303 1 0 0 "HCTxPortRdy == 1'b1"
+A 257 255 16 TEXT "Actions" | 78942,195669 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_LS_KEEP_ALIVE;"
+A 258 253 4 TEXT "Actions" | 104967,172420 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 259 241 0 253 251 BEZIER "Transitions" | 90715,166299 107284,153460 137919,126532 154488,113693
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.asf	(revision 264)
@@ -0,0 +1,146 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=161
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketcheckpreamble\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 32
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 158 37 BEZIER "Transitions" | 116216,34379 122135,26559 180161,53114 186081,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 70466,115662 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 156 60 BEZIER "Transitions" | 58983,118146 59059,114780 91699,99435 91452,95786
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88319,164339 88052,159633
+S 55 33 20480 ELLIPSE "States" | 88319,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88319,153150 1 0 0 "PREAM_SENT\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "PID_SENT\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+C 73 39 0 TEXT "Conditions" | 145852,37243 1 0 0 "sendPacketRdy == 1'b1"
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+                                        94907,51569 61918,50756 52575,52503 43232,54250\
+                                        38843,62050 37706,72734 36569,83418 36406,118357\
+                                        40062,129609 43718,140862 58507,150938 67687,153172\
+                                        76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 34428,222262 "" ""
+L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;"
+A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;"
+L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/"
+S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500
+L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/"
+S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500
+W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011
+W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.asf	(revision 264)
@@ -0,0 +1,110 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=95
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// softransmit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+F 6 0 671089152 54 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 16 6 0 Builtin Reset | 76112,190530
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+                                     119442,151760 119430,151725 119430,151571
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
+W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429
+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;\ni <= 8'h00;"
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+S 79 6 24576 ELLIPSE "States" | 54655,123733 6500 6500
+L 78 79 0 TEXT "State Labels" | 54655,123733 1 0 0 "DLY_SOF_CHK2\n/6/"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+                                         105450,47318 105450,38252 107207,34228 108965,30205\
+                                         115846,23167 119361,19652
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+L 73 74 0 TEXT "State Labels" | 63408,80448 1 0 0 "DLY_SOF_CHK1\n/5/"
+S 74 6 20480 ELLIPSE "States" | 63408,80448 6500 6500
+W 75 6 0 26 74 BEZIER "Transitions" | 117387,14280 106719,14616 86172,13920 78234,17868\
+                                      70296,21816 59880,36936 57948,44622 56016,52308\
+                                      59778,66554 61122,74366
+A 76 75 16 TEXT "Actions" | 55404,31002 1 0 0 "i <= 8'h00;"
+C 94 92 0 TEXT "Conditions" | 68357,136883 1 0 0 "i==8'hff"
+A 93 79 4 TEXT "Actions" | 72777,123623 1 0 0 "i <= i + 1'b1;"
+W 92 6 0 79 11 BEZIER "Transitions" | 60486,126602 74574,130193 99716,139754 113804,143345
+A 91 82 16 TEXT "Actions" | 49949,109037 1 0 0 "sendPacketArbiterReq <= 1'b0;\ni <= 8'h00;"
+C 90 82 0 TEXT "Conditions" | 61793,96219 1 0 0 "i==8'hff"
+A 88 74 4 TEXT "Actions" | 81838,80970 1 0 0 "i <= i + 1'b1;"
+I 87 0 130 Builtin Signal | 47362,241979 "" ""
+L 86 87 0 TEXT "Labels" | 50362,241979 1 0 0 "i[7:0]"
+C 85 75 0 TEXT "Conditions" | 66368,14007 1 0 0 "sendPacketRdy == 1'b1"
+W 82 6 0 74 79 BEZIER "Transitions" | 61272,86583 60002,89345 56169,113512 55585,117302
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMux.v	(revision 264)
@@ -0,0 +1,185 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Controls the select line for the mux that enables the sharing
+//// of a single SerialInterfaceEgine between the hostController
+//// and slaveController
+//// Also a dumping area for any features common to host and slave 
+//// operation. That is reset control and version number report.
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module hostSlaveMux (
+  SIEPortCtrlInToSIE,
+  SIEPortCtrlInFromHost,
+  SIEPortCtrlInFromSlave,
+  SIEPortDataInToSIE, 
+  SIEPortDataInFromHost, 
+  SIEPortDataInFromSlave, 
+  SIEPortWEnToSIE, 
+  SIEPortWEnFromHost, 
+  SIEPortWEnFromSlave, 
+  fullSpeedPolarityToSIE,
+  fullSpeedPolarityFromHost,
+  fullSpeedPolarityFromSlave,
+  fullSpeedBitRateToSIE,
+  fullSpeedBitRateFromHost,
+  fullSpeedBitRateFromSlave,
+  dataIn, 
+  dataOut,
+  address,
+  writeEn,
+  strobe_i,
+  busClk, 
+  usbClk, 
+  hostSlaveMuxSel,
+  rstFromWire,
+  rstSyncToBusClkOut,
+  rstSyncToUsbClkOut
+);
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE; 
+input [7:0] SIEPortDataInFromHost; 
+input [7:0] SIEPortDataInFromSlave; 
+output SIEPortWEnToSIE; 
+input SIEPortWEnFromHost; 
+input SIEPortWEnFromSlave; 
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE; 
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+reg SIEPortWEnToSIE; 
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClkOut;
+wire rstSyncToUsbClkOut;
+wire rstFromWire;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+  SIEPortCtrlInFromHost or
+  SIEPortCtrlInFromSlave or
+  SIEPortDataInFromHost or 
+  SIEPortDataInFromSlave or 
+  SIEPortWEnFromHost or 
+  SIEPortWEnFromSlave or 
+  fullSpeedPolarityFromHost or
+  fullSpeedPolarityFromSlave or
+  fullSpeedBitRateFromHost or
+  fullSpeedBitRateFromSlave)
+begin
+  if (hostMode == 1'b1) 
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+    SIEPortDataInToSIE <=  SIEPortDataInFromHost;
+    SIEPortWEnToSIE <= SIEPortWEnFromHost;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+  end
+  else
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+    SIEPortDataInToSIE <=  SIEPortDataInFromSlave;
+    SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+  end
+end      
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(dataIn), 
+  .dataOut(dataOut),
+  .address(address),
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .hostMode(hostMode), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),  
+  .rstFromWire(rstFromWire),
+  .rstSyncToBusClkOut(rstSyncToBusClkOut),
+  .rstSyncToUsbClkOut(rstSyncToUsbClkOut) );
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostSlave_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostSlave_h.v	(revision 264)
@@ -0,0 +1,46 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+//             control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect 
+//             time outs, added low speed EOP keep alive. The TX bit rate is now controlled by 
+//             SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+//             speed, and TX resume is always low speed.
+//             Fixed read clock recovery (readUSBWireData.v) issue which was resulting 
+//             in missing receive packets.
+//             Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+//             by adding kludged delay to softranmit. This needs to be fixed properly.
+//             This version has undergone limited testing
+//             with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+//             with uClinux, and is known to work with a full speed USB flash stick.
+//             Moving Opencores project status from Beta to done.
+//             TODO: Test isochronous mode, and low speed mode using uClinux driver
+//                   Create a seperate clock domain for the bus interface
+//                   Add frame period adjustment capability
+//                   Add compilation flags for slave only and host only versions
+//                   Create data bus width options beyond 8-bit
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+//             Removed TX and RX fifo status registers, and removed 
+//             TX fifo data count register.
+//             Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG. 
+//             Fixed slave mode bug which caused receive fifo to be filled with 
+//             incoming data when the slave was responding with a NAK, and the 
+//             data should have been discarded.
+
+// Most significant nibble corresponds to major revision.
+// Least significant nibble corresponds to minor revision.
+`define USBHOSTSLAVE_VERSION_NUM 8'h10   
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/include/usbHostSlave_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.asf	(revision 264)
@@ -0,0 +1,638 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=1083
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIETransmitter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 16
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+INSTHEADER 609
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+INSTHEADER 626
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+END
+INSTHEADER 958
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+END
+INSTHEADER 1073
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin OutPort | 64372,246658 "" ""
+L 821 822 0 TEXT "Labels" | 70372,246658 1 0 0 "TxByteOutCtrl[7:0]"
+I 820 0 130 Builtin OutPort | 64372,251298 "" ""
+L 819 820 0 TEXT "Labels" | 70372,251298 1 0 0 "TxByteOut[7:0]"
+I 818 0 2 Builtin InPort | 66692,255938 "" ""
+L 817 818 0 TEXT "Labels" | 72692,255938 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin OutPort | 64372,260578 "" ""
+L 15 16 0 TEXT "State Labels" | 115356,124706 1 0 0 "RES_ST"
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "STX_CHK_ST\n/19/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: SIETransmitter"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,209519
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "SIETx"
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_SIETX\n/18/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 847 0 130 Builtin InPort | 124599,219647 "" ""
+I 846 0 130 Builtin InPort | 125108,215006 "" ""
+L 845 846 0 TEXT "Labels" | 131108,215006 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 71500,215836 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[2:0]"
+I 840 0 130 Builtin Signal | 71500,220244 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 838 0 130 Builtin Signal | 71732,224652 "" ""
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+A 836 63 4 TEXT "Actions" | 118825,194982 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,123104 6500 6500
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/31/"
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/10/"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+I 572 458 0 Builtin Entry | 44780,253519
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+W 574 458 0 567 540 BEZIER "Transitions" | 44528,153207 48588,141781 61374,54759 65434,43333
+A 835 9 4 TEXT "Actions" | 153876,207727 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 3'h0;\nresumeCnt <= 16'h0000;\nTxByteOutFullSpeedRate <= 1'b0;\nUSBWireFullSpeedRate <= 1'b0;"
+L 848 847 0 TEXT "Labels" | 130599,219647 1 0 0 "JBit[1:0]"
+L 319 320 0 TEXT "Labels" | 133337,226207 1 0 0 "fullSpeedRateIn"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 606 489 0 Builtin Exit | 101068,51939
+I 599 489 0 Builtin Entry | 29952,254306
+I 324 0 130 Builtin InPort | 126267,235982 "" ""
+L 323 324 0 TEXT "Labels" | 132267,235982 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin InPort | 127337,226207 "" ""
+S 63 6 0 ELLIPSE "States" | 138700,177505 6500 6500
+L 62 63 0 TEXT "State Labels" | 139687,176678 1 0 0 "STX_WAIT_BYTE\n/20/"
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+                                      42326,129670 44202,125650 52711,124511 61220,123372\
+                                      92777,123293 108857,123025
+I 872 360 0 Builtin Exit | 188676,86316
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 77071,148182 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 74766,198892 6500 6500
+L 608 609 0 TEXT "State Labels" | 74766,198892 1 0 0 "PID"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+                                        161730,108850 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 144540,155815\
+                                        141750,161305 138960,166795 141442,165439 137520,171118
+A 78 65 16 TEXT "Actions" | 53177,187164 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;\nTxByteOutFullSpeedRate <= fullSpeedRateIn;\nUSBWireFullSpeedRate <= fullSpeedRateIn;"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+C 66 65 0 TEXT "Conditions" | 70342,165567 1 0 0 "SIEPortWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 132240,176792 119927,171164 59299,174571 47927,176730
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/0/"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 3'h7"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 636 610 0 Builtin Entry | 71380,236621
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 634 626 0 TEXT "State Labels" | 75688,89174 1 0 0 "CRC"
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 75688,89174 6500 6500
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 77071,148182 1 0 0 "BYTE1"
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 80182,200322 122622,188930 134753,182668
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 363 360 0 Builtin Entry | 26888,244668
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+                                        43361,99065 46384,95576 54928,94878 63472,94181\
+                                        94207,96080 109784,96428
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/38/"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/29/"
+I 908 224 0 Builtin Entry | 85162,237767
+I 909 224 0 Builtin Exit | 108872,88817
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+I 914 912 0 Builtin Exit | 129540,111760
+I 913 912 0 Builtin Entry | 86360,167640
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/22/"
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+W 651 489 0 626 606 BEZIER "Transitions" | 78534,83332 83720,75495 93087,59776 98273,51939
+W 650 489 0 617 626 BEZIER "Transitions" | 76796,141693 76220,129592 76063,107757 75487,95656
+W 649 489 0 609 617 BEZIER "Transitions" | 74835,192396 75180,182600 76125,164449 76470,154653
+W 648 489 0 599 609 BEZIER "Transitions" | 33927,254306 41205,251054 71176,221478 73868,205326
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+I 645 610 0 Builtin Exit | 114540,97930
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/33/"
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 3'h0;"
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+S 939 633 8192 ELLIPSE "States" | 39277,179580 6500 6500
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/42/"
+I 671 624 0 Builtin Exit | 116402,43935
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+                                           104039,47385 110550,45085 113597,43935
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+I 663 624 0 Builtin Entry | 59190,254840
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/26/"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+W 956 360 0 363 1073 BEZIER "Transitions" | 30725,244668 34469,239130 89108,253575 97764,256633
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+S 952 624 16384 ELLIPSE "States" | 35474,185224 6500 6500
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/44/"
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+S 947 734 12288 ELLIPSE "States" | 160390,197270 6500 6500
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/43/"
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+I 682 633 0 Builtin Exit | 119917,39891
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/21/"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/36/"
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+A 414 413 16 TEXT "Actions" | 50560,239516 1 0 0 "USBWireReq <= 1'b1;\nresumeCnt  <= 16'h0000;\nUSBWireFullSpeedRate <= 1'b0; //resume always uses low speed timing"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/35/"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/1/"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;	\nresumeCnt  <= resumeCnt  + 1'b1;"
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+L 957 958 0 TEXT "State Labels" | 118124,69006 1 0 0 "TX_LS_EOP"
+S 958 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118124,67086 6500 6500
+W 959 6 0 11 958 BEZIER "Transitions" | 41589,169153 41990,145961 42609,100547 43291,87547\
+                                        43973,74547 45899,68928 54485,67524 63072,66120\
+                                        95424,66959 111633,66752
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/32/"
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/8/"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/25/"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "W_RDY1\n/24/"
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+I 418 17 0 Builtin Exit | 171923,20004
+I 417 17 0 Builtin Entry | 44586,243455
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/28/"
+W 425 17 1 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+C 426 425 0 TEXT "Conditions" | 62970,121537 1 0 0 "resumeCnt == `HOST_TX_RESUME_TIME"
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "SND_SE0_1\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 429 430 0 TEXT "State Labels" | 62301,61312 1 0 0 "SND_SE0_2\n/17/"
+S 430 17 0 ELLIPSE "States" | 62301,61312 6500 6500
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "SND_J_1\n/14/"
+C 960 959 0 TEXT "Conditions" | 51998,64924 1 0 0 "SIEPortCtrl == `TX_LS_KEEP_ALIVE"
+H 961 958 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 973 961 0 979 993 BEZIER "Transitions" | 70323,232853 70198,226566 70679,201498 70554,195211
+C 974 973 0 TEXT "Conditions" | 71910,232073 1 0 0 "USBWireGnt == 1'b1"
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+I 716 471 0 Builtin Entry | 83616,227615
+I 715 471 0 Builtin Exit | 140592,59380
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 713 480 0 Builtin Exit | 85376,122104
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 711 480 0 Builtin Entry | 43257,253243
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251031 41695,239812 59162,227406 68316,218108
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/7/"
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/30/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "SND_J_2\n/15/"
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+W 436 17 0 1026 430 BEZIER "Transitions" | 180912,80742 169329,74775 79549,70544 67972,64487
+W 437 17 0 1028 432 BEZIER "Transitions" | 51111,44834 62356,44473 153909,58971 165141,58620
+W 438 17 0 1030 434 BEZIER "Transitions" | 180827,34395 168542,28662 79732,38178 67447,32445
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+C 442 436 0 TEXT "Conditions" | 142323,77914 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 53546,46742 1 0 0 "USBWireRdy == 1'b1"
+C 444 438 0 TEXT "Conditions" | 151980,31125 1 0 0 "USBWireRdy == 1'b1"
+A 445 436 16 TEXT "Actions" | 93935,80043 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 94027,64120 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 447 438 16 TEXT "Actions" | 100527,44161 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 977 961 0 989 979 BEZIER "Transitions" | 59230,267637 62248,262230 65883,250383 66893,244725
+A 978 977 16 TEXT "Actions" | 61762,259858 1 0 0 "USBWireReq <= 1'b1;"
+S 979 961 24576 ELLIPSE "States" | 70526,239337 6500 6500
+S 982 961 28672 ELLIPSE "States" | 72541,157710 6500 6500
+L 983 982 0 TEXT "State Labels" | 72541,157710 1 0 0 "SND_SE0_2\n/46/"
+S 984 961 32768 ELLIPSE "States" | 180649,189534 6500 6500
+L 985 984 0 TEXT "State Labels" | 180649,189534 1 0 0 "SND_SE0_1\n/47/"
+L 988 979 0 TEXT "State Labels" | 70526,239337 1 0 0 "WAIT_GNT1\n/45/"
+I 989 961 0 Builtin Entry | 55468,267637
+I 990 961 0 Builtin Exit | 202744,115664
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/23/"
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 731 727 0 Builtin Entry | 71380,236621
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+A 448 432 4 TEXT "Actions" | 159702,69949 1 0 0 "USBWireWEn <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34545,73018 1 0 0 "USBWireWEn <= 1'b0;"
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 150428,26102 169066,20266
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/41/"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 993 961 36864 ELLIPSE "States" | 71111,188744 6500 6500
+L 994 993 0 TEXT "State Labels" | 71111,188744 1 0 0 "W_RDY1\n/48/"
+W 997 961 0 1018 1008 BEZIER "Transitions" | 102841,134185 114073,133834 169562,153024 180794,152673
+A 998 997 16 TEXT "Actions" | 129506,151946 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 999 961 0 1016 982 BEZIER "Transitions" | 191758,179211 180175,173244 89868,166719 78285,160752
+A 1000 999 16 TEXT "Actions" | 104380,176838 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1002 997 0 TEXT "Conditions" | 110626,136953 1 0 0 "USBWireRdy == 1'b1"
+C 1003 999 0 TEXT "Conditions" | 156382,176802 1 0 0 "USBWireRdy == 1'b1"
+A 1004 984 4 TEXT "Actions" | 165556,203106 1 0 0 "USBWireWEn <= 1'b0;"
+W 1005 961 0 993 984 BEZIER "Transitions" | 77608,188557 88723,188674 163036,189296 174151,189413
+A 1006 1005 16 TEXT "Actions" | 120336,197940 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1007 1005 0 TEXT "Conditions" | 80771,193665 1 0 0 "USBWireRdy == 1'b1"
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 750 734 0 Builtin Entry | 59190,254840
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+I 744 734 0 Builtin Exit | 116402,43935
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/6/"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/34/"
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 738 727 0 Builtin Exit | 114540,97930
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+S 1008 961 40960 ELLIPSE "States" | 187291,152508 6500 6500
+L 1009 1008 0 TEXT "State Labels" | 187291,152508 1 0 0 "SND_J\n/49/"
+W 1010 961 0 1008 990 BEZIER "Transitions" | 189673,146461 206752,122150 181346,115781 199949,115664
+A 1011 1008 4 TEXT "Actions" | 175523,169038 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 1012 982 4 TEXT "Actions" | 80404,154242 1 0 0 "USBWireWEn <= 1'b0;"
+W 1014 6 0 958 911 BEZIER "Transitions" | 124457,68547 133850,72702 151714,79462 161174,83437
+L 1015 1016 0 TEXT "State Labels" | 197328,182560 1 0 0 "W_RDY2\n/50/"
+S 1016 961 45056 ELLIPSE "States" | 197328,182560 6500 6500
+L 1017 1018 0 TEXT "State Labels" | 96400,133312 1 0 0 "W_RDY3\n/51/"
+S 1018 961 49152 ELLIPSE "States" | 96400,133312 6500 6500
+W 1019 961 0 984 1016 BEZIER "Transitions" | 186591,186901 188111,186673 190020,185744 191540,185516
+W 1020 961 0 982 1018 BEZIER "Transitions" | 76114,152281 80446,148557 87065,141183 91397,137459
+L 1021 1022 0 TEXT "State Labels" | 32738,152469 1 0 0 "DELAY\n/52/"
+S 1022 17 53248 ELLIPSE "States" | 32738,152469 6500 6500
+W 1023 17 2 407 1022 BEZIER "Transitions" | 52990,130254 48496,130815 40121,131043 37433,133209\
+                                            34745,135375 33783,142213 32901,145984
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+I 762 733 0 Builtin Exit | 119917,39891
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/27/"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+S 216 6 0 ELLIPSE "States" | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE\n/4/"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/2/"
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+W 1024 17 0 1022 411 BEZIER "Transitions" | 33384,158929 34668,162139 36269,168519 38877,170084\
+                                            41485,171649 49107,171706 53039,171626
+L 1025 1026 0 TEXT "State Labels" | 186818,83454 1 0 0 "W_RDY2\n/53/"
+S 1026 17 57344 ELLIPSE "States" | 186818,83454 6500 6500
+L 1027 1028 0 TEXT "State Labels" | 44615,44613 1 0 0 "W_RDY3\n/54/"
+S 1028 17 61440 ELLIPSE "States" | 44615,44613 6500 6500
+L 1029 1030 0 TEXT "State Labels" | 187139,35946 1 0 0 "W_RDY4\n/55/"
+S 1030 17 65536 ELLIPSE "States" | 187139,35946 6500 6500
+W 1031 17 0 428 1026 BEZIER "Transitions" | 175312,89747 176917,88865 179480,87397 181085,86515
+W 1032 17 0 430 1028 BEZIER "Transitions" | 56906,57687 55061,55440 50351,52066 48506,49819
+W 1033 17 0 432 1030 BEZIER "Transitions" | 175464,53250 177630,50201 181501,44488 183667,41439
+L 1034 1035 0 TEXT "State Labels" | 59060,143481 1 0 0 "DELAY\n/56/"
+S 1035 224 69632 ELLIPSE "States" | 59060,143481 6500 6500
+W 1036 224 2 891 1035 BEZIER "Transitions" | 101504,123089 91624,127529 74202,135226 64322,139666
+W 1037 224 0 1035 897 BEZIER "Transitions" | 64606,146870 74406,150350 91859,157715 101659,161195
+L 1038 1039 0 TEXT "Labels" | 74756,230822 1 0 0 "resumeCnt[15:0]"
+I 1039 0 130 Builtin Signal | 71756,230822 "" ""
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/40/"
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/37/"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/5/"
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+                                           46299,139871 48829,136075 59202,135063 69575,134052\
+                                           106314,125693 125795,125567
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+                                           46931,109511 49715,104703 60024,103501 70334,102300\
+                                           108774,103037 128002,103037
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+                                           48196,74723 50474,70169 60657,69030 70840,67892\
+                                           108432,68626 127660,68626
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+                                           48829,42592 51359,37532 61605,36267 71852,35002\
+                                           109061,35775 128289,35775
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+L 1040 1041 0 TEXT "Labels" | 70301,241139 1 0 0 "TxByteOutFullSpeedRate"
+I 1041 0 2 Builtin OutPort | 64301,241139 "" ""
+L 1042 1043 0 TEXT "Labels" | 27464,245142 1 0 0 "USBWireFullSpeedRate"
+I 1043 0 2 Builtin OutPort | 21464,245142 "" ""
+A 1046 451 16 TEXT "Actions" | 91713,26530 1 0 0 "USBWireFullSpeedRate <= fullSpeedRateIn;"
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+                                           128857,67252 162473,65260 171997,66691 181521,68123\
+                                           186003,75843 187123,97692 188244,119542 188244,199222\
+                                           184384,221196 180525,243170 165087,251388 155563,253628\
+                                           146039,255869 123379,256617 115100,254625 106821,252633\
+                                           98206,243956 92977,239599
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+                                              31250,150650 32250,89650 34750,72525 37250,55400\
+                                              46250,47900 56000,46150 65750,44400 95896,46012\
+                                              103573,44899 111250,43786 113107,43935 113607,43935
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/3/"
+I 787 733 0 Builtin Entry | 62705,250796
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+L 1071 1072 0 TEXT "Labels" | 130970,231188 1 0 0 "CRC16En"
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/39/"
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+I 540 458 0 Builtin Exit | 68103,43333
+I 1072 0 2 Builtin OutPort | 124970,231188 "" ""
+H 1075 1073 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 1073 360 73748 ELLIPSE "Junction" | 100383,254312 3500 3500
+L 1074 1073 0 TEXT "State Labels" | 100383,254312 1 0 0 "J3"
+I 1076 1075 0 Builtin Entry | 86360,167640
+I 1077 1075 0 Builtin Exit | 129540,111760
+W 1078 1075 0 1076 1077 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+W 1079 360 2 1073 453 BEZIER "Transitions" | 97595,252197 93012,236072 61888,222891 52340,220350
+W 1080 360 1 1073 453 BEZIER "Transitions" | 103127,252141 112392,249752 130361,224032 127627,220759\
+                                             124894,217487 107954,214253 97790,213829 87626,213406\
+                                             65074,215466 53216,216236
+C 1081 1080 0 TEXT "Conditions" | 102248,241873 1 0 0 "SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE"
+A 1082 1080 16 TEXT "Actions" | 95072,224240 1 0 0 "TxByteOutFullSpeedRate <= 1'b1; //SOF and PRE always at full speed"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.v	(revision 264)
@@ -0,0 +1,412 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processrxbit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive);
+input   clk;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processRxBitsWEn;
+input   processRxByteRdy;
+input   rst;
+input   [1:0]RxBitsIn;
+input   RxWireActive;
+output  processRxBitRdy;
+output  processRxByteWEn;
+output  resumeDetected;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+
+wire    clk;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processRxBitRdy, next_processRxBitRdy;
+wire    processRxBitsWEn;
+wire    processRxByteRdy;
+reg     processRxByteWEn, next_processRxByteWEn;
+reg     resumeDetected, next_resumeDetected;
+wire    rst;
+wire    [1:0]RxBitsIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+wire    RxWireActive;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg  [1:0]oldRXBits, next_oldRXBits;
+reg  [4:0]resumeWaitCnt, next_resumeWaitCnt;
+reg  [3:0]RXBitCount, next_RXBitCount;
+reg  [1:0]RxBits, next_RxBits;
+reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg  [7:0]RXByte, next_RXByte;
+reg  [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RxWireActive or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+  NextState_prRxBit <= CurrState_prRxBit;
+  // Set default values for outputs and signals
+  next_processRxByteWEn <= processRxByteWEn;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOut <= RxDataOut;
+  next_resumeDetected <= resumeDetected;
+  next_RXBitStMachCurrState <= RXBitStMachCurrState;
+  next_RxBits <= RxBits;
+  next_RXSameBitCount <= RXSameBitCount;
+  next_RXBitCount <= RXBitCount;
+  next_oldRXBits <= oldRXBits;
+  next_RXByte <= RXByte;
+  next_bitStuffError <= bitStuffError;
+  next_resumeWaitCnt <= resumeWaitCnt;
+  next_processRxBitRdy <= processRxBitRdy;
+  case (CurrState_prRxBit)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOut <= 8'h00;
+      next_resumeDetected <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_RxBits <= 2'b00;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h0;
+      next_oldRXBits <= 2'b00;
+      next_RXByte <= 8'h00;
+      next_bitStuffError <= 1'b0;
+      next_resumeWaitCnt <= 5'h0;
+      next_processRxBitRdy <= 1'b1;
+      NextState_prRxBit <= `WAIT_BITS;
+    end
+    `WAIT_BITS:
+    begin
+      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+      begin
+        NextState_prRxBit <= `DATA_RX_CHK_SE0;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+      begin
+        NextState_prRxBit <= `RES_RX_CHK;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+      begin
+        NextState_prRxBit <= `RES_END_CHK1;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+      begin
+        NextState_prRxBit <= `IDLE_CHK_KBIT;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+    end
+    `IDLE_FIRST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h1;
+      next_oldRXBits <= RxBits;
+      //zero is always the first RZ data bit of a new packet
+      next_RXByte <= 8'h00;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `IDLE_CHK_KBIT:
+    begin
+      if ((RxBits == KBit) && (RxWireActive == 1'b1))
+      begin
+        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `IDLE_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `IDLE_FIRST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_START;
+        //start of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_LAST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_CHK_SE0:
+    begin
+      next_bitStuffError <= 1'b0;
+      if (RxBits == `SE0)
+      begin
+        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
+        begin
+        next_RXSameBitCount <= RXSameBitCount + 1'b1;
+        //inc 'RXSameBitCount'
+        if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+        next_bitStuffError <= 1'b1;
+        //flag 'bitStuffError'
+        else                                          //else no bit stuffing error
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= { 1'b1, RXByte[7:1]};
+        //RZ bit <= 1 (ie no change in 'RxBits')
+        end
+        end
+        else                                            //else current 'RxBits' are different from old 'RxBits'
+        begin
+        if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != 4'h7) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= {1'b0, RXByte[7:1]};
+        //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+        end
+        next_RXSameBitCount <= 4'h0;
+        //reset 'RXSameBitCount'
+        end
+        next_oldRXBits <= RxBits;
+      end
+    end
+    `DATA_RX_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_LAST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_STOP;
+        //end of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_DATA_DESTUFF:
+    begin
+      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+      end
+      else if (bitStuffError == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `DATA_RX_BYTE_SEND2:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_BYTE_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+        next_RXBitCount <= 4'h0;
+        next_RxDataOut <= RXByte;
+        next_RxCtrlOut <= `DATA_STREAM;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_ERROR_CHK_RES:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      if (RxBits == JBit)                           //if current bit is a JBit, then
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      //next state is idle
+      else                                          //else
+      begin
+      next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+      //check for resume
+      next_resumeWaitCnt <= 5'h0;
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_ERROR_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `RES_RX_CHK:
+    begin
+      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      else
+      begin
+      next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+      //if we've waited long enough, then
+      if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
+      begin
+      next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+      next_resumeDetected <= 1'b1;
+      //report resume detected
+      end
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `RES_END_CHK1:
+    begin
+      if (RxBits != KBit)  //line must leave KBit state for the end of resume
+      begin
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_resumeDetected <= 1'b0;
+      //clear resume detected flag
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxBit <= `START;
+  else
+    CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processRxByteWEn <= 1'b0;
+    RxCtrlOut <= 8'h00;
+    RxDataOut <= 8'h00;
+    resumeDetected <= 1'b0;
+    processRxBitRdy <= 1'b1;
+    RXBitStMachCurrState <= `IDLE_BIT_ST;
+    RxBits <= 2'b00;
+    RXSameBitCount <= 4'h0;
+    RXBitCount <= 4'h0;
+    oldRXBits <= 2'b00;
+    RXByte <= 8'h00;
+    bitStuffError <= 1'b0;
+    resumeWaitCnt <= 5'h0;
+  end
+  else 
+  begin
+    processRxByteWEn <= next_processRxByteWEn;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOut <= next_RxDataOut;
+    resumeDetected <= next_resumeDetected;
+    processRxBitRdy <= next_processRxBitRdy;
+    RXBitStMachCurrState <= next_RXBitStMachCurrState;
+    RxBits <= next_RxBits;
+    RXSameBitCount <= next_RXSameBitCount;
+    RXBitCount <= next_RXBitCount;
+    oldRXBits <= next_oldRXBits;
+    RXByte <= next_RXByte;
+    bitStuffError <= next_bitStuffError;
+    resumeWaitCnt <= next_resumeWaitCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.v	(revision 264)
@@ -0,0 +1,481 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processTxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteWEn;
+input   rst;
+input   [7:0]TxByteCtrlIn;
+input   TxByteFullSpeedRateIn;
+input   [7:0]TxByteIn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  processTxByteRdy;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processTxByteRdy, next_processTxByteRdy;
+wire    processTxByteWEn;
+wire    rst;
+wire    [7:0]TxByteCtrlIn;
+wire    TxByteFullSpeedRateIn;
+wire    [7:0]TxByteIn;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [3:0]i, next_i;
+reg  [7:0]TxByte, next_TxByte;
+reg  [7:0]TxByteCtrl, next_TxByteCtrl;
+reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
+reg  [1:0]TXLineState, next_TXLineState;
+reg  [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+`define LS_START_W_RDY1 5'b10110
+`define LS_START_W_RDY2 5'b10111
+`define LS_START_W_RDY3 5'b11000
+`define STOP_W_RDY1 5'b11001
+`define STOP_W_RDY2 5'b11010
+`define STOP_W_RDY3 5'b11011
+`define STOP_W_RDY4 5'b11100
+
+reg [4:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)
+begin
+  NextState_prcTxB <= CurrState_prcTxB;
+  // Set default values for outputs and signals
+  next_processTxByteRdy <= processTxByteRdy;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_USBWireReq <= USBWireReq;
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_TxByte <= TxByte;
+  next_TxByteCtrl <= TxByteCtrl;
+  next_TXLineState <= TXLineState;
+  next_TXOneCount <= TXOneCount;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
+  case (CurrState_prcTxB)  // synopsys parallel_case full_case
+    `START_PTBY:
+    begin
+      next_processTxByteRdy <= 1'b0;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_i <= 4'h0;
+      next_TxByte <= 8'h00;
+      next_TxByteCtrl <= 8'h00;
+      next_TXLineState <= 2'b0;
+      next_TXOneCount <= 4'h0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      next_TxByteFullSpeedRate <= 1'b0;
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `PTBY_WAIT_EN:
+    begin
+      next_processTxByteRdy <= 1'b1;
+      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_GNT;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_TXOneCount <= 4'h0;
+        next_TXLineState <= JBit;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (processTxByteWEn == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_i <= 4'h0;
+      end
+    end
+    `PTBY_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_prcTxB <= `WAIT_RDY_WIRE;
+      end
+    end
+    `WAIT_RDY_WIRE:
+    begin
+      if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate  == 1'b0))
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE1;
+      end
+      else if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `WAIT_RDY_PKT;
+        //actively drive the first J bit
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `WAIT_RDY_PKT:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `SEND_BYTE_UPDATE_BYTE:
+    begin
+      next_i <= i + 1'b1;
+      next_TxByte <= {1'b0, TxByte[7:1] };
+      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
+      next_TXOneCount <= TXOneCount + 1'b1;
+      //increment 'TXOneCount'
+      else                                        //else this is a zero bit
+      begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      end
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+    end
+    `SEND_BYTE_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (TXOneCount == `MAX_CONSEC_SAME_BITS)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+      end
+      else if (i != 4'h8)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+      else
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+    end
+    `SEND_BYTE_BIT_STUFF:
+    begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+    end
+    `SEND_BYTE_WAIT_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (i == 4'h8)
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+      else
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+    end
+    `STOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY2;
+    end
+    `STOP_SND_SE0_1:
+    begin
+      NextState_prcTxB <= `STOP_W_RDY1;
+    end
+    `STOP_CHK:
+    begin
+      if (TxByteCtrl == `DATA_STOP)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_1;
+      end
+      else
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_EN;
+      end
+    end
+    `STOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY3;
+    end
+    `STOP_SND_IDLE:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY4;
+    end
+    `STOP_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      //release the wire
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `STOP_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_J;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_IDLE;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_W_RDY4:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_SND_IDLE3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY2;
+    end
+    `LS_START_SND_J1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY3;
+    end
+    `LS_START_SND_IDLE1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_SND_IDLE2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY1;
+    end
+    `LS_START_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `LS_START_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE3;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_J1;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_FIN;
+        //Drive the first JBit
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prcTxB <= `START_PTBY;
+  else
+    CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processTxByteRdy <= 1'b0;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    USBWireReq <= 1'b0;
+    USBWireWEn <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+    i <= 4'h0;
+    TxByte <= 8'h00;
+    TxByteCtrl <= 8'h00;
+    TXLineState <= 2'b0;
+    TXOneCount <= 4'h0;
+    TxByteFullSpeedRate <= 1'b0;
+  end
+  else 
+  begin
+    processTxByteRdy <= next_processTxByteRdy;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    USBWireReq <= next_USBWireReq;
+    USBWireWEn <= next_USBWireWEn;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+    i <= next_i;
+    TxByte <= next_TxByte;
+    TxByteCtrl <= next_TxByteCtrl;
+    TXLineState <= next_TXLineState;
+    TXOneCount <= next_TXOneCount;
+    TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC16.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC16.v	(revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC16.v                                                ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [15:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [15:0] CRCResult;
+reg    ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 16'hffff;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0)
+    begin
+      if (CRCEn == 1'b1) begin
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        ready <= 1'b0;
+    end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[15:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == 4'h7)
+      begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.asf	(revision 264)
@@ -0,0 +1,315 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=258
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processrxbit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+L 7 6 0 TEXT "Labels" | 23239,210942 1 0 0 "prRxBit"
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+S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
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+L 15 16 0 TEXT "State Labels" | 116068,123104 1 0 0 "IDLE"
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+I 20 17 0 Builtin Entry | 56736,212076
+I 21 17 0 Builtin Exit | 146563,24238
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+S 24 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116801,94499 6500 6500
+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
+W 35 41 0 40 37 BEZIER "Transitions" | 111741,134422 116780,127404 121695,118778 126735,111760
+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
+I 37 41 0 Builtin Exit | 129540,111760
+I 38 41 0 Builtin Entry | 86360,167640
+L 39 40 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK\n/9/"
+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 119820,36808 1 0 0 "RES_END"
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
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+                                       111892,63165
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+                                       46388,39220 49604,34396 58247,33391 66890,32386\
+                                       97657,35973 113335,36375
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+                                       188238,99472 188778,113512 186145,122422 183513,131332\
+                                       167904,143587 159264,149864 150624,156142 133542,158851\
+                                       125779,159931 118017,161011 123617,159646 119837,160051
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+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 114133,117894 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h0;                          \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+W 76 17 4096 241 18 BEZIER "Transitions" | 152390,172884 131374,171355 101683,127861 94565,116677
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
+W 82 17 8194 75 21 BEZIER "Transitions" | 74719,170800 72243,162260 51221,151750 45574,140719\
+                                          39928,129688 39788,80170 47763,75675 55738,71180\
+                                          102436,61038 148189,26024
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 95824,146799 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+                                            151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+                                        176540,156388 181096,131196 181431,113977 181766,96758\
+                                        182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit)                           //if current bit is a JBit, then\n  RXBitStMachCurrState <= `IDLE_BIT_ST;       //next state is idle\nelse                                          //else\nbegin\n  RXBitStMachCurrState <= `WAIT_RESUME_ST;    //check for resume\n  resumeWaitCnt <= 5'h0;                          \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte;       \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit)  //line must leave KBit state for the end of resume\nbegin\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\n  resumeDetected <= 1'b0;   //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit)  //can only be a resume if line remains in Kbit state\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n  resumeWaitCnt <= resumeWaitCnt + 1'b1; \n  //if we've waited long enough, then\n  if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)\n  begin	\n    RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n    resumeDetected <= 1'b1;  //report resume detected\n  end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+                                         107061,21822 137747,20482 148467,20415 159187,20348\
+                                         171381,21420 174463,22458 177545,23497 178090,26035\
+                                         178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+                                         145117,36964 157043,31068 161599,29627 166155,28187\
+                                         172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 5'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[4:0]"
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 25628,249822 1 0 0 "if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n  RXSameBitCount <= RXSameBitCount + 1'b1;  //inc 'RXSameBitCount'\n  if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error\n    bitStuffError <= 1'b1;                         //flag 'bitStuffError'\n  else                                          //else no bit stuffing error\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin\n      processRxBitRdy <= 1'b1;                   //early indication of ready\n	end\n    RXByte <= { 1'b1, RXByte[7:1]};              //RZ bit = 1 (ie no change in 'RxBits')\n  end\nend\nelse                                            //else current 'RxBits' are different from old 'RxBits'\nbegin\n  if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;	               //early indication of ready\n	end\n    RXByte <= {1'b0, RXByte[7:1]};             //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n  end\n   RXSameBitCount <= 4'h0;                      //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 151892,179359 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 151892,179359 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 135677,178559 145432,178646
+C 243 242 0 TEXT "Conditions" | 82407,188660 1 0 0 "(RxBits == KBit) && (RxWireActive == 1'b1)"
+C 244 76 0 TEXT "Conditions" | 137618,163943 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+I 257 0 2 Builtin InPort | 150840,260800 "" ""
+L 256 257 0 TEXT "Labels" | 156840,260800 1 0 0 "RxWireActive"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.asf	(revision 264)
@@ -0,0 +1,311 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1126
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processTxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
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+END
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+OBJECTS
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+S 1100 1035 110592 ELLIPSE "States" | 52016,132400 6500 6500
+L 1099 1100 0 TEXT "State Labels" | 52016,132400 1 0 0 "W_RDY1\n/22/"
+W 1093 6 0 1034 874 BEZIER "Transitions" | 107126,38228 93109,49095 67454,69717 53517,80692
+C 1092 1091 0 TEXT "Conditions" | 145670,31298 1 0 0 "TxByteFullSpeedRate  == 1'b0"
+W 1091 6 1 1025 1034 BEZIER "Transitions" | 176852,45724 174332,42574 169925,36810 163940,34881\
+                                            157955,32952 139055,31533 132716,31415 126377,31297\
+                                            121929,32154 118701,32626
+A 1090 1084 4 TEXT "Actions" | 60764,178497 1 0 0 "USBWireWEn <= 1'b0;"
+C 1089 1087 0 TEXT "Conditions" | 68348,136414 1 0 0 "USBWireRdy == 1'b1"
+A 1088 1087 16 TEXT "Actions" | 81756,164067 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 12 6 0 Builtin Reset | 22016,204762
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 816 0 2 Builtin InPort | 123679,253114 "" ""
+L 817 818 0 TEXT "Labels" | 127572,248474 1 0 0 "processTxByteRdy"
+I 818 0 2 Builtin OutPort | 121572,248474 "" ""
+L 819 820 0 TEXT "Labels" | 129679,243601 1 0 0 "TxByteIn[7:0]"
+I 820 0 130 Builtin InPort | 123679,243601 "" ""
+L 821 822 0 TEXT "Labels" | 129679,239194 1 0 0 "TxByteCtrlIn[7:0]"
+I 822 0 130 Builtin InPort | 123679,239194 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+L 1094 1095 0 TEXT "State Labels" | 102676,41870 1 0 0 "FIN\n/21/"
+S 1095 1035 106496 ELLIPSE "States" | 102676,41870 6500 6500
+A 1096 1095 4 TEXT "Actions" | 110058,56736 1 0 0 "USBWireWEn <= 1'b0;"
+I 1097 1035 0 Builtin Exit | 133008,37611
+W 1098 1035 0 1095 1097 BEZIER "Transitions" | 108942,40143 114373,39761 124823,37993 130254,37611
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+S 1117 895 135168 ELLIPSE "States" | 157607,86664 6500 6500
+L 1116 1117 0 TEXT "State Labels" | 157607,86664 1 0 0 "W_RDY4\n/28/"
+S 1115 895 131072 ELLIPSE "States" | 152471,133209 6500 6500
+L 1114 1115 0 TEXT "State Labels" | 152471,133209 1 0 0 "W_RDY3\n/27/"
+S 1113 895 126976 ELLIPSE "States" | 147977,176223 6500 6500
+L 1112 1113 0 TEXT "State Labels" | 147977,176223 1 0 0 "W_RDY2\n/26/"
+S 1111 895 122880 ELLIPSE "States" | 129359,218595 6500 6500
+L 1110 1111 0 TEXT "State Labels" | 129359,218595 1 0 0 "W_RDY1\n/25/"
+W 1109 1035 0 1068 1107 BEZIER "Transitions" | 127810,93623 140198,90963 162007,83161 174395,80501
+W 1108 1035 0 1046 1105 BEZIER "Transitions" | 125077,143006 136439,141182 157968,135884 169330,134060
+S 1107 1035 118784 ELLIPSE "States" | 180608,78592 6500 6500
+L 1106 1107 0 TEXT "State Labels" | 180608,78592 1 0 0 "W_RDY3\n/24/"
+S 1105 1035 114688 ELLIPSE "States" | 175744,133008 6500 6500
+L 1104 1105 0 TEXT "State Labels" | 175744,133008 1 0 0 "W_RDY2\n/23/"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 1125 0 2 Builtin OutPort | 17114,248843 "" ""
+L 1124 1125 0 TEXT "Labels" | 23114,248843 1 0 0 "USBWireFullSpeedRate"
+I 1123 0 2 Builtin Signal | 69653,217706 "" ""
+L 1122 1123 0 TEXT "Labels" | 72332,217706 1 0 0 "TxByteFullSpeedRate"
+W 1121 895 0 962 1117 BEZIER "Transitions" | 87535,83532 103906,84093 134787,85298 151158,85859
+W 1120 895 0 956 1115 BEZIER "Transitions" | 84631,133419 97918,132655 128828,133044 145972,133233
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48799,85161 6500 6500
+L 873 874 0 TEXT "State Labels" | 48799,85161 1 0 0 "SEND_BYTE"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+A 871 869 16 TEXT "Actions" | 38769,162443 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;\nTxByteFullSpeedRate <= TxByteFullSpeedRateIn;\nUSBWireFullSpeedRate <= TxByteFullSpeedRateIn;"
+C 870 869 0 TEXT "Conditions" | 45385,167359 1 0 0 "processTxByteWEn == 1'b1"
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+I 884 880 0 Builtin Exit | 178131,23271
+I 883 880 0 Builtin Entry | 38120,248040
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1)                      //If this bit is 1, then\n  TXOneCount <= TXOneCount + 1'b1;          //increment 'TXOneCount'\nelse                                        //else this is a zero bit\nbegin\n  TXOneCount <= 4'h0;                            //reset 'TXOneCount'\n  if (TXLineState == JBit) \n    TXLineState <= KBit; //toggle the line state\n  else \n    TXLineState <= JBit;\nend"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+                                         25630,50244 23766,53274 22950,67894 22135,82515\
+                                         20737,137969 21261,153813 21785,169657 25281,177579\
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+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47452,100861 48245,91628
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h0;                                //reset 'TXOneCount'\nif (TXLineState == JBit) \n  TXLineState <= KBit;   //toggle the line state\nelse \n  TXLineState <= JBit;"
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == `MAX_CONSEC_SAME_BITS"
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+C 941 940 0 TEXT "Conditions" | 159104,107836 1 0 0 "USBWireGnt == 1'b1"
+W 940 6 0 936 1005 BEZIER "Transitions" | 152571,107755 158885,103151 166953,83129 172936,74254
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 4'h0;       \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+                                              40522,42856 31562,47464 29098,65320 26634,83176\
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+                                              53770,197736 54409,198230 54473,198230
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+                                              113354,23912 154429,23527 174909,23271
+A 959 958 16 TEXT "Actions" | 127881,161233 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+W 958 895 0 1113 956 BEZIER "Transitions" | 148099,169766 148727,162473 88842,149177 77593,139316
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+A 947 944 16 TEXT "Actions" | 109865,203040 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 946 942 4 TEXT "Actions" | 92250,183175 1 0 0 "USBWireWEn <= 1'b0;"
+C 945 944 0 TEXT "Conditions" | 128791,211803 1 0 0 "USBWireRdy == 1'b1"
+W 944 895 0 1111 942 BEZIER "Transitions" | 129757,212112 130385,204819 80759,192930 74325,181785
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+                                           90132,26172 93257,24084 94765,23272
+I 974 895 0 Builtin Exit | 97904,23272
+C 973 970 0 TEXT "Conditions" | 155824,79891 1 0 0 "USBWireRdy == 1'b1"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+A 971 970 16 TEXT "Actions" | 138904,72921 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 970 895 0 1117 968 BEZIER "Transitions" | 157812,80182 158440,72889 82671,57884 83299,50591
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+C 967 964 0 TEXT "Conditions" | 151835,126496 1 0 0 "USBWireRdy == 1'b1"
+A 966 962 4 TEXT "Actions" | 90331,92695 1 0 0 "USBWireWEn <= 1'b0;"
+A 965 964 16 TEXT "Actions" | 130933,116536 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+W 964 895 0 1115 962 BEZIER "Transitions" | 152792,126730 153420,119437 79847,97645 80475,90352
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+C 961 958 0 TEXT "Conditions" | 146391,169184 1 0 0 "USBWireRdy == 1'b1"
+A 960 956 4 TEXT "Actions" | 86480,140378 1 0 0 "USBWireWEn <= 1'b0;"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+A 979 9 4 TEXT "Actions" | 127034,208396 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;\nUSBWireFullSpeedRate <= 1'b0;\nTxByteFullSpeedRate <= 1'b0;"
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+I 977 895 0 Builtin Entry | 34452,259216
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+                                              30972,218732 29812,212468 29638,189094 29464,165720\
+                                              29928,78488 31900,55230 33872,31972 41296,26172\
+                                              49358,24664 57420,23156 82353,23388 94765,23272
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+                                              41124,121640 36948,124424 36020,132602 35092,140780\
+                                              35556,170708 38166,179350 40776,187992 50140,192687\
+                                              55128,195007
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+                                              104561,139388 153745,139620 168013,138576 182281,137532\
+                                              190169,133124 192141,121582 194113,110040 194113,68280\
+                                              192025,55114 189937,41948 185529,28723 181353,23271
+L 1006 1005 0 TEXT "State Labels" | 178403,71114 1 0 0 "WAIT_RDY_WIRE\n/15/"
+S 1005 6 73728 ELLIPSE "States" | 178403,70739 6500 6500
+A 1001 1000 16 TEXT "Actions" | 97876,75175 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit;  \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 1000 6 2 1025 1011 BEZIER "Transitions" | 175446,48001 143324,42707 116663,67496 88157,75929
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 996 995 0 Builtin Entry | 86360,167640
+I 997 995 0 Builtin Exit | 129540,111760
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+I 1022 0 2 Builtin InPort | 123637,233935 "" ""
+L 1021 1022 0 TEXT "Labels" | 129637,233935 1 0 0 "TxByteFullSpeedRateIn"
+W 1020 6 0 1011 874 BEZIER "Transitions" | 75467,77142 69580,78790 60425,80424 54545,82123
+L 1013 1011 0 TEXT "State Labels" | 81933,77802 1 0 0 "WAIT_RDY_PKT\n/16/"
+A 1012 1011 4 TEXT "Actions" | 89664,97554 1 0 0 "USBWireWEn <= 1'b0;"
+S 1011 6 77824 ELLIPSE "States" | 81933,77802 6500 6500
+H 1035 1034 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 1034 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112501,34575 6500 6500
+L 1033 1034 0 TEXT "State Labels" | 112501,34575 1 0 0 "LS_START"
+C 1032 1031 0 TEXT "Conditions" | 160740,61840 1 0 0 "USBWireRdy == 1'b1"
+W 1031 6 0 1005 1025 BEZIER "Transitions" | 178252,64280 178492,60600 178502,55716 178742,52036
+W 1030 1027 0 1028 1029 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 1029 1027 0 Builtin Exit | 129540,111760
+I 1028 1027 0 Builtin Entry | 86360,167640
+L 1026 1025 0 TEXT "State Labels" | 178900,48560 1 0 0 "J2"
+S 1025 6 81940 ELLIPSE "Junction" | 178900,48560 3500 3500
+H 1027 1025 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 1047 1046 0 TEXT "State Labels" | 118913,145067 1 0 0 "SND_IDLE3\n/17/"
+S 1046 1035 90112 ELLIPSE "States" | 118913,145067 6500 6500
+L 1071 1068 0 TEXT "State Labels" | 121801,96100 1 0 0 "SND_J1\n/18/"
+A 1070 1066 16 TEXT "Actions" | 152238,115920 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 1069 1068 4 TEXT "Actions" | 140396,98815 1 0 0 "USBWireWEn <= 1'b0;"
+S 1068 1035 94208 ELLIPSE "States" | 121801,96100 6500 6500
+C 1067 1066 0 TEXT "Conditions" | 172627,126718 1 0 0 "USBWireRdy == 1'b1"
+W 1066 1035 0 1105 1068 BEZIER "Transitions" | 174692,126596 175320,119303 120603,109864 121231,102571
+A 1064 1060 16 TEXT "Actions" | 145913,63353 1 0 0 "//Drive the first JBit\nUSBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+C 1061 1060 0 TEXT "Conditions" | 146295,70754 1 0 0 "USBWireRdy == 1'b1"
+W 1060 1035 0 1107 1095 BEZIER "Transitions" | 176710,73393 172416,69158 96436,74541 101513,48264
+W 1087 1035 0 1100 1046 BEZIER "Transitions" | 56057,127311 71885,129746 98436,147110 112744,147113
+L 1085 1084 0 TEXT "State Labels" | 50985,163622 1 0 0 "SND_IDLE2\n/20/"
+S 1084 1035 102400 ELLIPSE "States" | 50985,163622 6500 6500
+C 1082 1080 0 TEXT "Conditions" | 60959,213403 1 0 0 "USBWireRdy == 1'b1"
+A 1081 1080 16 TEXT "Actions" | 52141,196692 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 1080 1035 0 1077 1084 BEZIER "Transitions" | 60047,214302 60675,207009 52849,177084 50437,170095
+W 1079 1035 0 1075 1077 BEZIER "Transitions" | 75208,269307 75836,262014 61041,234231 58933,227242
+L 1078 1077 0 TEXT "State Labels" | 59497,220774 1 0 0 "SND_IDLE1\n/19/"
+S 1077 1035 98304 ELLIPSE "States" | 59497,220774 6500 6500
+I 1075 1035 0 Builtin Entry | 75208,271435
+A 1073 1046 4 TEXT "Actions" | 137508,147782 1 0 0 "USBWireWEn <= 1'b0;"
+L 815 816 0 TEXT "Labels" | 129679,253114 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/lineControlUpdate.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/lineControlUpdate.v	(revision 264)
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// lineControlUpdate.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+    if (fullSpeedPolarity == 1'b1)
+  begin
+      JBit = `ONE_ZERO;
+      KBit = `ZERO_ONE;
+    end
+    else
+  begin
+      JBit = `ZERO_ONE;
+      KBit = `ONE_ZERO;
+    end
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.v	(revision 264)
@@ -0,0 +1,498 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processRxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   processRxDataInWEn;
+input   rst;
+input   [7:0]RxByteIn;
+input   [7:0]RxCtrlIn;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processRxByteRdy;
+output  rstCRC;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+output  RxDataOutWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+reg     processRxByteRdy, next_processRxByteRdy;
+wire    processRxDataInWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]RxByteIn;
+wire    [7:0]RxCtrlIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+reg     RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RxByte, next_RxByte;
+reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg  [7:0]RxCtrl, next_RxCtrl;
+reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg  [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+  NextState_prRxByte <= CurrState_prRxByte;
+  // Set default values for outputs and signals
+  next_RxByte <= RxByte;
+  next_RxCtrl <= RxCtrl;
+  next_RXByteStMachCurrState <= RXByteStMachCurrState;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RxOverflow <= RxOverflow;
+  next_RxTimeOut <= RxTimeOut;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_RxDataOut <= RxDataOut;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOutWEn <= RxDataOutWEn;
+  next_rstCRC <= rstCRC;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_RXDataByteCnt <= RXDataByteCnt;
+  next_processRxByteRdy <= processRxByteRdy;
+  case (CurrState_prRxByte)  // synopsys parallel_case full_case
+    `CHK_ST:
+    begin
+      if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+      begin
+        NextState_prRxByte <= `TOKEN_WAIT_CRC;
+      end
+      else if (RXByteStMachCurrState == `HS_BYTE_ST)
+      begin
+        NextState_prRxByte <= `HSHAKE_CHK;
+      end
+      else if (RXByteStMachCurrState == `CHECK_PID_ST)
+      begin
+        NextState_prRxByte <= `CHK_PID_DO_CHK;
+      end
+      else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+      begin
+        NextState_prRxByte <= `CHK_SYNC_DO;
+      end
+      else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+      begin
+        NextState_prRxByte <= `IDLE_CHK_START;
+      end
+      else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+      begin
+        NextState_prRxByte <= `DATA_WAIT_CRC;
+      end
+    end
+    `START_PRBY:
+    begin
+      next_RxByte <= 8'h00;
+      next_RxCtrl <= 8'h00;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RxOverflow <= 1'b0;
+      next_RxTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_RxDataOut <= 8'h00;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOutWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_RXDataByteCnt <= 10'h00;
+      next_processRxByteRdy <= 1'b1;
+      NextState_prRxByte <= `WAIT_BYTE;
+    end
+    `WAIT_BYTE:
+    begin
+      if (processRxDataInWEn == 1'b1)
+      begin
+        NextState_prRxByte <= `CHK_ST;
+        next_RxByte <= RxByteIn;
+        next_RxCtrl <= RxCtrlIn;
+        next_processRxByteRdy <= 1'b0;
+      end
+    end
+    `HSHAKE_FIN:
+    begin
+      next_RxDataOutWEn <= 1'b0;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `HSHAKE_CHK:
+    begin
+      NextState_prRxByte <= `HSHAKE_FIN;
+      if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RxDataOutWEn <= 1'b1;
+    end
+    `CHK_PID_DO_CHK:
+    begin
+      if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+      begin
+        NextState_prRxByte <= `WAIT_BYTE;
+        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+        next_processRxByteRdy <= 1'b1;
+      end
+      else
+      begin
+        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+        next_CRCError <= 1'b0;
+        next_bitStuffError <= 1'b0;
+        next_RxOverflow <= 1'b0;
+        next_NAKRxed <= 1'b0;
+        next_stallRxed <= 1'b0;
+        next_ACKRxed <= 1'b0;
+        next_dataSequence <= 1'b0;
+        next_RxTimeOut <= 1'b0;
+        next_RXDataByteCnt <= 0;
+        next_RxDataOut <= RxByte;
+        next_RxCtrlOut <= `RX_PACKET_START;
+        next_RxDataOutWEn <= 1'b1;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `CHK_PID_FIRST_BYTE_PROC:
+    begin
+      next_rstCRC <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      case (RxByte[1:0] )
+      `SPECIAL:                              //Special PID.
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      `TOKEN:                                //Token PID
+      begin
+      next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      `HANDSHAKE:                            //Handshake PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_ACKRxed <= 1'b1;
+      2'b10:
+      next_NAKRxed <= 1'b1;
+      2'b11:
+      next_stallRxed <= 1'b1;
+      default:
+      begin
+      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+      end
+      endcase
+      next_RXByteStMachCurrState <= `HS_BYTE_ST;
+      end
+      `DATA:                                  //Data PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_dataSequence <= 1'b0;
+      2'b10:
+      next_dataSequence <= 1'b1;
+      default:
+      $display ("Invalid DATA PID detected in ProcessRXByte\n");
+      endcase
+      next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      endcase
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_FIN:
+    begin
+      next_CRC16En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC16Result != 16'hb001)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC16En <= 1'b1;
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `DATA_FIN;
+    end
+    `DATA_WAIT_CRC:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `DATA_CHK_STRM;
+      end
+    end
+    `TOKEN_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC5Result != 5'h6)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      if (RXDataByteCnt > 10'h2)
+      begin
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      else
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      end
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `TOKEN_FIN;
+    end
+    `TOKEN_FIN:
+    begin
+      next_CRC5En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `TOKEN_WAIT_CRC:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `TOKEN_CHK_STRM;
+      end
+    end
+    `CHK_SYNC_DO:
+    begin
+      if (RxByte == `SYNC_BYTE)
+      next_RXByteStMachCurrState <= `CHECK_PID_ST;
+      else
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `IDLE_CHK_START:
+    begin
+      if (RxCtrl == `DATA_START)
+      next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxByte <= `START_PRBY;
+  else
+    CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RxDataOut <= 8'h00;
+    RxCtrlOut <= 8'h00;
+    RxDataOutWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    processRxByteRdy <= 1'b1;
+    RxByte <= 8'h00;
+    RxCtrl <= 8'h00;
+    RXByteStMachCurrState <= `IDLE_BYTE_ST;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RxOverflow <= 1'b0;
+    RxTimeOut <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    RXDataByteCnt <= 10'h00;
+  end
+  else 
+  begin
+    RxDataOut <= next_RxDataOut;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOutWEn <= next_RxDataOutWEn;
+    rstCRC <= next_rstCRC;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    processRxByteRdy <= next_processRxByteRdy;
+    RxByte <= next_RxByte;
+    RxCtrl <= next_RxCtrl;
+    RXByteStMachCurrState <= next_RXByteStMachCurrState;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RxOverflow <= next_RxOverflow;
+    RxTimeOut <= next_RxTimeOut;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    RXDataByteCnt <= next_RXDataByteCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.asf	(revision 264)
@@ -0,0 +1,251 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIEReceiver\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+                                        127685,31371 137213,31768
+C 145 144 0 TEXT "Conditions" | 62881,26704 1 0 0 "RXStMachCurrState == `DISCONNECT_ST"
+W 161 39 8195 40 43 BEZIER "Transitions" | 58578,211192 49548,206204 31147,197012 26632,187509\
+                                           22117,178006 22117,149970 33211,139263 44305,128556\
+                                           88681,113764 103817,110238 118953,106712 136069,108777\
+                                           144153,109121
+W 160 6 0 235 11 BEZIER "Transitions" | 171556,99342 175414,111175 187017,133454 187960,147988\
+                                        188903,162522 181196,168609 172535,178212 163875,187816\
+                                        140506,197413 125270,198727 110035,200042 80303,196085\
+                                        61192,193841
+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `LOW_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+A 166 53 4 TEXT "Actions" | 101814,215348 1 0 0 "if (RxBits == `ONE_ZERO)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `FULL_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+W 169 72 0 71 68 BEZIER "Transitions" | 86442,160488 87123,152997 131179,46721 131860,39230
+S 174 81 53248 ELLIPSE "States" | 85374,175380 6500 6500
+L 175 174 0 TEXT "State Labels" | 85374,175380 1 0 0 "CHK_RX_BITS1\n/6/"
+I 176 81 0 Builtin Entry | 63784,203320
+I 177 81 0 Builtin Exit | 137732,35774
+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+W 183 81 0 174 177 BEZIER "Transitions" | 85690,168888 83487,163706 122612,52505 134843,35774
+S 185 90 57344 ELLIPSE "States" | 81562,170615 6500 6500
+L 186 185 0 TEXT "State Labels" | 81562,170615 1 0 0 "CHK_RX_BITS\n/7/"
+I 187 90 0 Builtin Entry | 59972,198555
+I 188 90 0 Builtin Exit | 126468,30181
+W 189 90 0 187 185 BEZIER "Transitions" | 63495,198555 68094,191731 73329,182828 77929,176004
+W 194 90 0 185 188 BEZIER "Transitions" | 81878,164123 82559,156632 125787,39592 126468,32101
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+I 199 99 0 Builtin Exit | 120480,22566
+I 200 99 0 Builtin Entry | 53777,190526
+S 201 99 61440 ELLIPSE "States" | 75367,162586 6500 6500
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/8/"
+W 204 99 0 201 199 BEZIER "Transitions" | 75683,156094 76364,148603 119799,31977 120480,24486
+I 219 0 130 Builtin Signal | 20132,253454 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 215 0 130 Builtin Signal | 20439,258880 "" ""
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+I 209 0 130 Builtin InPort | 77032,244882 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+I 233 0 130 Builtin Signal | 19714,243194 "" ""
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;"
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+S 235 6 65556 ELLIPSE "Junction" | 170150,96140 3500 3500
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 237 236 0 Builtin Entry | 86360,167640
+I 238 236 0 Builtin Exit | 129540,111760
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+A 255 194 16 TEXT "Actions" | 77086,121516 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend"
+A 252 204 16 TEXT "Actions" | 71150,119778 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend"
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+S 241 6 69652 ELLIPSE "Junction" | 55410,156008 3500 3500
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 243 242 0 Builtin Entry | 86360,167640
+I 244 242 0 Builtin Exit | 129540,111760
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+A 259 169 16 TEXT "Actions" | 77229,121214 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+A 258 183 16 TEXT "Actions" | 76648,132819 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(revision 264)
@@ -0,0 +1,391 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine.v                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSerialInterfaceEngine(
+  clk, rst,
+  //readUSBWireData
+  USBWireDataIn,
+  USBWireDataInTick,
+  //writeUSBWireData
+  USBWireDataOut,
+  USBWireCtrlOut,
+  USBWireDataOutTick,
+  //SIEReceiver
+  connectState,
+  //processRxBit
+  resumeDetected,
+  //processRxByte
+  RxCtrlOut, 
+  RxDataOutWEn, 
+  RxDataOut, 
+    //SIETransmitter
+  SIEPortCtrlIn,
+  SIEPortDataIn, 
+  SIEPortTxRdy, 
+  SIEPortWEn, 
+    //lineControlUpdate
+  fullSpeedPolarity,
+  fullSpeedBitRate,
+  noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut; 
+output RxDataOutWEn; 
+output [7:0] RxDataOut; 
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy; 
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut; 
+wire RxDataOutWEn; 
+wire [7:0] RxDataOut; 
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy; 
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En; 
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En; 
+wire [4:0] RxCRC5Result; 
+wire RxCRC5_8Bit; 
+wire [7:0] RxCRCData; 
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En; 
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En; 
+wire [4:0] TxCRC5Result; 
+wire TxCRC5_8Bit; 
+wire [7:0] TxCRCData; 
+wire TxRstCRC; 
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy; 
+wire processTxByteWEn; 
+
+wire SIEFsRate;
+wire TxFSRateFromSIETxToPrcTxByte;
+wire prcTxByteFSRate;
+wire FSRateFromArbiterToWire;
+
+wire RxWireActive;
+
+lineControlUpdate u_lineControlUpdate
+  (.fullSpeedPolarity(fullSpeedPolarity),
+  .fullSpeedBitRate(fullSpeedBitRate),
+  .JBit(JBit),
+  .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+  (
+  .RxWireDataIn(RxWireDataFromWireRx), 
+  .RxWireDataWEn(RxWireDataWEn), 
+  .clk(clk),
+  .connectState(connectState),
+  .rst(rst) );
+
+  
+processRxBit u_processRxBit
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .RxBitsIn(RxWireDataFromWireRx), 
+  .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxDataOut(RxDataFromPrcRxBitToPrcRxByte), 
+  .clk(clk), 
+  .processRxBitRdy(processRxBitRdy), 
+  .processRxBitsWEn(RxWireDataWEn), 
+  .processRxByteWEn(processRxByteWEn), 
+  .resumeDetected(resumeDetected), 
+  .rst(rst),
+  .processRxByteRdy(processRxByteRdy),
+  .RxWireActive(RxWireActive)
+  );
+  
+processRxByte u_processRxByte
+  (.CRC16En(RxCRC16En), 
+  .CRC16Result(RxCRC16Result), 
+  .CRC16UpdateRdy(RxCRC16UpdateRdy),
+  .CRC5En(RxCRC5En), 
+  .CRC5Result(RxCRC5Result), 
+  .CRC5_8Bit(RxCRC5_8Bit),
+  .CRC5UpdateRdy(RxCRC5UpdateRdy),
+  .CRCData(RxCRCData), 
+  .RxByteIn(RxDataFromPrcRxBitToPrcRxByte), 
+  .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataOut), 
+  .clk(clk), 
+  .processRxDataInWEn(processRxByteWEn), 
+  .rst(rst), 
+  .rstCRC(RxRstCRC),
+  .processRxByteRdy(processRxByteRdy) ); 
+  
+  
+updateCRC5 RxUpdateCRC5
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC5Result), 
+  .CRCEn(RxCRC5En), 
+  .CRC5_8BitIn(RxCRC5_8Bit), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 RxUpdateCRC16
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC16Result), 
+  .CRCEn(RxCRC16En), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+SIETransmitter u_SIETransmitter
+  (.CRC16En(TxCRC16En), 
+  .CRC16Result(TxCRC16Result), 
+  .CRC5En(TxCRC5En), 
+  .CRC5Result(TxCRC5Result), 
+  .CRC5_8Bit(TxCRC5_8Bit), 
+  .CRCData(TxCRCData),
+  .CRC5UpdateRdy(TxCRC5UpdateRdy),
+  .CRC16UpdateRdy(TxCRC16UpdateRdy),
+  .JBit(JBit), 
+  .KBit(KBit), 
+  .SIEPortCtrlIn(SIEPortCtrlIn),
+  .SIEPortDataIn(SIEPortDataIn), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEn), 
+  .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteOut(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(SIETxCtrl), 
+  .USBWireData(SIETxData), 
+  .USBWireGnt(SIETxGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(SIETxReq), 
+  .USBWireWEn(SIETxWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst), 
+  .rstCRC(TxRstCRC),
+  .USBWireFullSpeedRate(SIEFsRate),
+  .TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
+  .fullSpeedRateIn(fullSpeedBitRate)
+  );    
+
+updateCRC5 TxUpdateCRC5
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC5Result), 
+  .CRCEn(TxCRC5En), 
+  .CRC5_8BitIn(TxCRC5_8Bit), 
+  .dataIn(TxCRCData),
+  .ready(TxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 TxUpdateCRC16
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC16Result), 
+  .CRCEn(TxCRC16En), 
+  .dataIn(TxCRCData), 
+  .ready(TxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+
+processTxByte u_processTxByte
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteIn(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(prcTxByteCtrl), 
+  .USBWireData(prcTxByteData), 
+  .USBWireGnt(prcTxByteGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(prcTxByteReq), 
+  .USBWireWEn(prcTxByteWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst),
+  .USBWireFullSpeedRate(prcTxByteFSRate),
+  .TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
+  ); 
+  
+USBTxWireArbiter u_USBTxWireArbiter
+  (.SIETxCtrl(SIETxCtrl), 
+  .SIETxData(SIETxData), 
+  .SIETxGnt(SIETxGnt), 
+  .SIETxReq(SIETxReq), 
+  .SIETxWEn(SIETxWEn), 
+  .TxBits(TxBitsFromArbToWire), 
+  .TxCtl(TxCtrlFromArbToWire), 
+  .USBWireRdyIn(USBWireRdy), 
+  .USBWireRdyOut(USBWireReadyFromTxArb), 
+  .USBWireWEn(USBWireWEn),
+  .clk(clk), 
+  .prcTxByteCtrl(prcTxByteCtrl), 
+  .prcTxByteData(prcTxByteData), 
+  .prcTxByteGnt(prcTxByteGnt), 
+  .prcTxByteReq(prcTxByteReq), 
+  .prcTxByteWEn(prcTxByteWEn), 
+  .rst(rst),
+  .SIETxFSRate(SIEFsRate),
+  .prcTxByteFSRate(prcTxByteFSRate),
+  .TxFSRate(FSRateFromArbiterToWire)
+  ); 
+  
+writeUSBWireData u_writeUSBWireData
+  (.TxBitsIn(TxBitsFromArbToWire), 
+  .TxBitsOut(USBWireDataOut), 
+  .TxDataOutTick(USBWireDataOutTick),
+  .TxCtrlIn(TxCtrlFromArbToWire), 
+  .TxCtrlOut(USBWireCtrlOut), 
+  .USBWireRdy(USBWireRdy), 
+  .USBWireWEn(USBWireWEn),
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .fullSpeedRate(FSRateFromArbiterToWire), 
+  .clk(clk),
+  .rst(rst)
+   );  
+
+  
+  
+readUSBWireData u_readUSBWireData
+  (.RxBitsIn(USBWireDataIn), 
+  .RxDataInTick(USBWireDataInTick),
+  .RxBitsOut(RxWireDataFromWireRx), 
+  .SIERxRdyIn(processRxBitRdy), 
+  .SIERxWEn(RxWireDataWEn), 
+  .fullSpeedRate(fullSpeedBitRate), 
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .clk(clk),
+  .rst(rst),
+  .noActivityTimeOut(noActivityTimeOut),
+  .RxWireActive(RxWireActive)
+  );
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/USBSlaveControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/USBSlaveControlBI.v	(revision 264)
@@ -0,0 +1,527 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBSlaveControlBI.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////       
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbSlaveControl_h.v"
+ 
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+  endP0TransTypeReg, endP0NAKTransTypeReg,
+  endP1TransTypeReg, endP1NAKTransTypeReg,
+  endP2TransTypeReg, endP2NAKTransTypeReg,
+  endP3TransTypeReg, endP3NAKTransTypeReg,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  EP0StatusReg,
+  EP1StatusReg,
+  EP2StatusReg,
+  EP3StatusReg,
+  SCAddrReg, frameNum,
+  connectStateIn,
+  SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+  slaveControlSelect,
+  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  SCGlobalEn
+  );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg; 
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg; 
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg; 
+input [1:0] endP3NAKTransTypeReg;
+output [4:0] endP0ControlReg;
+output [4:0] endP1ControlReg;
+output [4:0] endP2ControlReg;
+output [4:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg; 
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg; 
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg; 
+wire [1:0] endP3NAKTransTypeReg;
+reg [4:0] endP0ControlReg;
+reg [4:0] endP1ControlReg;
+reg [4:0] endP2ControlReg;
+reg [4:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0IsoEn;
+reg EP1IsoEn;
+reg EP2IsoEn;
+reg EP3IsoEn;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [4:0] endP0ControlRegSTB;
+reg [4:0] endP1ControlRegSTB;
+reg [4:0] endP2ControlRegSTB;
+reg [4:0] endP3ControlRegSTB;
+reg NAKSentInSTB;
+reg SOFRxedInSTB;
+reg resetEventInSTB;
+reg resumeIntInSTB;
+reg transDoneInSTB;
+reg clrEP0ReadySTB;
+reg clrEP1ReadySTB;
+reg clrEP2ReadySTB;
+reg clrEP3ReadySTB;
+reg SCGlobalEnSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB; 
+reg fullSpeedRateSTB;
+reg [7:0] EP0StatusRegSTB;
+reg [7:0] EP1StatusRegSTB;
+reg [7:0] EP2StatusRegSTB;
+reg [7:0] EP3StatusRegSTB;
+reg [1:0] endP0TransTypeRegSTB;
+reg [1:0] endP0NAKTransTypeRegSTB;
+reg [1:0] endP1TransTypeRegSTB; 
+reg [1:0] endP1NAKTransTypeRegSTB;
+reg [1:0] endP2TransTypeRegSTB; 
+reg [1:0] endP2NAKTransTypeRegSTB;
+reg [1:0] endP3TransTypeRegSTB; 
+reg [1:0] endP3NAKTransTypeRegSTB;
+reg [10:0] frameNumSTB;
+
+  
+//sync write demux
+always @(posedge busClk)
+begin   
+  if (rstSyncToBusClk == 1'b1) begin
+    EP0IsoEn <= 1'b0;
+    EP0SendStall <= 1'b0;
+    EP0DataSequence <= 1'b0;
+    EP0Enable <= 1'b0;
+    EP1IsoEn <= 1'b0;
+    EP1SendStall <= 1'b0;
+    EP1DataSequence <= 1'b0;
+    EP1Enable <= 1'b0;
+    EP2IsoEn <= 1'b0;
+    EP2SendStall <= 1'b0;
+    EP2DataSequence <= 1'b0;
+    EP2Enable <= 1'b0;
+    EP3IsoEn <= 1'b0;
+    EP3SendStall <= 1'b0;
+    EP3DataSequence <= 1'b0;
+    EP3Enable <= 1'b0;
+    SCControlReg <= 6'h00;
+    SCAddrReg <= 7'h00;
+    interruptMaskReg <= 5'h00;
+  end
+  else begin
+    clrNAKReq <= 1'b0;
+    clrSOFReq <= 1'b0;
+    clrResetReq <= 1'b0;
+    clrResInReq <= 1'b0;
+    clrTransDoneReq <= 1'b0;
+    EP0SetReady <= 1'b0;
+    EP1SetReady <= 1'b0;
+    EP2SetReady <= 1'b0;
+    EP3SetReady <= 1'b0;
+    if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+    begin
+      case (address)
+        `EP0_CTRL_REG : begin
+          EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP1_CTRL_REG : begin
+          EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP2_CTRL_REG : begin
+          EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP3_CTRL_REG : begin
+          EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+        `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+        `SC_INTERRUPT_STATUS_REG : begin
+          clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
+          clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
+          clrResetReq <= dataIn[`RESET_EVENT_BIT];
+          clrResInReq <= dataIn[`RESUME_INT_BIT];
+          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+        end
+        `SC_INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[4:0];
+      endcase
+    end
+  end
+end
+
+//interrupt control 
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    NAKSentInt <= 1'b0;
+    SOFRxedInt <= 1'b0;
+    resetEventInt <= 1'b0;
+    resumeInt <= 1'b0;
+    transDoneInt <= 1'b0;
+  end
+  else begin
+    if (NAKSentInSTB == 1'b1)
+      NAKSentInt <= 1'b1;
+    else if (clrNAKReq == 1'b1)
+      NAKSentInt <= 1'b0; 
+    
+    if (SOFRxedInSTB == 1'b1)
+      SOFRxedInt <= 1'b1;
+    else if (clrSOFReq == 1'b1)
+      SOFRxedInt <= 1'b0;
+    
+    if (resetEventInSTB == 1'b1)
+      resetEventInt <= 1'b1;
+    else if (clrResetReq == 1'b1)
+      resetEventInt <= 1'b0;
+    
+    if (resumeIntInSTB == 1'b1)
+      resumeInt <= 1'b1;
+    else if (clrResInReq == 1'b1)
+      resumeInt <= 1'b0;  
+
+    if (transDoneInSTB == 1'b1)
+      transDoneInt <= 1'b1;
+    else if (clrTransDoneReq == 1'b1)
+      transDoneInt <= 1'b0;
+  end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end  
+
+//end point ready, set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'EP0SetReady' etc must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the ready is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'EP0Ready' and sampling of related control signals.always @(posedge busClk)
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    EP0Ready <= 1'b0;
+    EP1Ready <= 1'b0;
+    EP2Ready <= 1'b0;
+    EP3Ready <= 1'b0;
+  end
+  else begin
+    if (EP0SetReady == 1'b1)
+      EP0Ready <= 1'b1;
+    else if (clrEP0ReadySTB == 1'b1)
+      EP0Ready <= 1'b0;
+    
+    if (EP1SetReady == 1'b1)
+      EP1Ready <= 1'b1;
+    else if (clrEP1ReadySTB == 1'b1)
+      EP1Ready <= 1'b0;
+    
+    if (EP2SetReady == 1'b1)
+      EP2Ready <= 1'b1;
+    else if (clrEP2ReadySTB == 1'b1)
+      EP2Ready <= 1'b0;
+    
+    if (EP3SetReady == 1'b1)
+      EP3Ready <= 1'b1;
+    else if (clrEP3ReadySTB == 1'b1)
+      EP3Ready <= 1'b0;
+  end
+end  
+  
+//break out control signals
+always @(SCControlReg) begin
+  SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+  TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+  LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+  fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals 
+always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable) 
+begin
+  endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+  endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+  endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+  endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+      
+      
+// async read mux
+// FIX ME
+// Not sure why 'EP0SendStall' etc are in sensitivity list. May be related to
+// some translation bug
+always @(address or
+  EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+  EP0StatusRegSTB or EP1StatusRegSTB or EP2StatusRegSTB or EP3StatusRegSTB or
+  endP0ControlRegSTB or endP1ControlRegSTB or endP2ControlRegSTB or endP3ControlRegSTB or
+  endP0NAKTransTypeRegSTB or endP1NAKTransTypeRegSTB or endP2NAKTransTypeRegSTB or endP3NAKTransTypeRegSTB or 
+  endP0TransTypeRegSTB or endP1TransTypeRegSTB or endP2TransTypeRegSTB or endP3TransTypeRegSTB or
+  SCControlReg or connectStateIn or
+  NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or SCAddrReg or frameNumSTB)
+begin
+  case (address)
+      `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
+      `EP0_STS_REG : dataOut <= EP0StatusRegSTB;
+      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
+      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
+      `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
+      `EP1_STS_REG :  dataOut <= EP1StatusRegSTB;
+      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
+      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
+      `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
+      `EP2_STS_REG :  dataOut <= EP2StatusRegSTB;
+      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
+      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
+      `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
+      `EP3_STS_REG :  dataOut <= EP3StatusRegSTB;
+      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
+      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
+      `SC_CONTROL_REG : dataOut <= SCControlReg;
+      `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn}; 
+      `SC_INTERRUPT_STATUS_REG :  dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+      `SC_INTERRUPT_MASK_REG  : dataOut <= {3'b000, interruptMaskReg};
+      `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+      `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
+      `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+//re-sync from busClk to usbClk. 
+always @(posedge usbClk) begin
+  endP0ControlReg <= endP0ControlRegSTB;
+  endP1ControlReg <= endP1ControlRegSTB;
+  endP2ControlReg <= endP2ControlRegSTB;
+  endP3ControlReg <= endP3ControlRegSTB;
+  SCGlobalEn <= SCGlobalEnSTB;
+  TxLineState <= TxLineStateSTB;
+  LineDirectControlEn <= LineDirectControlEnSTB;
+  fullSpeedPol <= fullSpeedPolSTB; 
+  fullSpeedRate <= fullSpeedRateSTB;
+end
+
+//re-sync from usbClk to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc are only asserted 
+//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
+always @(posedge busClk) begin
+  NAKSentInSTB <= NAKSentIn;
+  SOFRxedInSTB <= SOFRxedIn;
+  resetEventInSTB <= resetEventIn;
+  resumeIntInSTB <= resumeIntIn;
+  transDoneInSTB <= transDoneIn;
+  clrEP0ReadySTB <= clrEP0Ready;
+  clrEP1ReadySTB <= clrEP1Ready;
+  clrEP2ReadySTB <= clrEP2Ready;
+  clrEP3ReadySTB <= clrEP3Ready;
+  EP0StatusRegSTB <= EP0StatusReg;
+  EP1StatusRegSTB <= EP1StatusReg;
+  EP2StatusRegSTB <= EP2StatusReg;
+  EP3StatusRegSTB <= EP3StatusReg;
+  endP0TransTypeRegSTB <= endP0TransTypeReg;
+  endP1TransTypeRegSTB <= endP1TransTypeReg;
+  endP2TransTypeRegSTB <= endP2TransTypeReg;
+  endP3TransTypeRegSTB <= endP3TransTypeReg;
+  endP0NAKTransTypeRegSTB <= endP0NAKTransTypeReg;
+  endP1NAKTransTypeRegSTB <= endP1NAKTransTypeReg;
+  endP2NAKTransTypeRegSTB <= endP2NAKTransTypeReg;
+  endP3NAKTransTypeRegSTB <= endP3NAKTransTypeReg;
+  frameNumSTB <= frameNum;
+end
+
+endmodule

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.v	(revision 264)
@@ -0,0 +1,197 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SCTxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   SCTxPortRdyIn;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  directCntlGnt;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortRdyOut;
+output  SCTxPortWEnable;
+output  sendPacketGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortRdyIn;
+reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg     SCTxPortWEnable, next_SCTxPortWEnable;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+  NextState_SCTxArb <= CurrState_SCTxArb;
+  // Set default values for outputs and signals
+  next_sendPacketGnt <= sendPacketGnt;
+  next_muxDCEn <= muxDCEn;
+  next_directCntlGnt <= directCntlGnt;
+  case (CurrState_SCTxArb)  // synopsys parallel_case full_case
+    `SARB1_WAIT_REQ:
+    begin
+      if (sendPacketReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxDCEn <= 1'b0;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_DC;
+        next_directCntlGnt <= 1'b1;
+        next_muxDCEn <= 1'b1;
+      end
+    end
+    `SARB_SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `SARB_DC:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_SCTxArb <= `SARB1_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SCTxArb <= `START_SARB;
+  else
+    CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketGnt <= 1'b0;
+    directCntlGnt <= 1'b0;
+    muxDCEn <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketGnt <= next_sendPacketGnt;
+    directCntlGnt <= next_directCntlGnt;
+    muxDCEn <= next_muxDCEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.v	(revision 264)
@@ -0,0 +1,383 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveGetPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut);
+input   clk;
+input   endPointReady;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  ACKRxed;
+output  bitStuffError;
+output  CRCError;
+output  dataSequence;
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXOverflow;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  RXTimeOut;
+
+reg     ACKRxed, next_ACKRxed;
+reg     bitStuffError, next_bitStuffError;
+wire    clk;
+reg     CRCError, next_CRCError;
+reg     dataSequence, next_dataSequence;
+wire    endPointReady;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXOverflow, next_RXOverflow;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+wire    [7:0]RXStreamStatusIn;
+reg     RXTimeOut, next_RXTimeOut;
+wire    SIERxTimeOut;
+
+// diagram signals declarations
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or CurrState_slvGetPkt)
+begin
+  NextState_slvGetPkt <= CurrState_slvGetPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  case (CurrState_slvGetPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (SIERxTimeOut == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_slvGetPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_slvGetPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (endPointReady == 1'b0)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
+      end
+      else if (RXFifoFull == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+    `PROC_PKT_DATA_LOOP_EP_N_RDY:    // Discard data
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvGetPkt <= `START_GP;
+  else
+    CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXOverflow <= 1'b0;
+    ACKRxed <= 1'b0;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RXTimeOut <= 1'b0;
+    RxPID <= 4'h0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    RXByteOld <= 8'h00;
+  end
+  else 
+  begin
+    RXOverflow <= next_RXOverflow;
+    ACKRxed <= next_ACKRxed;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RXTimeOut <= next_RXTimeOut;
+    RxPID <= next_RxPID;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    RXByteOld <= next_RXByteOld;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.v	(revision 264)
@@ -0,0 +1,787 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIETransmitter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   fullSpeedRateIn;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteRdy;
+input   rst;
+input   [7:0]SIEPortCtrlIn;
+input   [7:0]SIEPortDataIn;
+input   SIEPortWEn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processTxByteWEn;
+output  rstCRC;
+output  SIEPortTxRdy;
+output  [7:0]TxByteOut;
+output  [7:0]TxByteOutCtrl;
+output  TxByteOutFullSpeedRate;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+wire    fullSpeedRateIn;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+wire    processTxByteRdy;
+reg     processTxByteWEn, next_processTxByteWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]SIEPortCtrlIn;
+wire    [7:0]SIEPortDataIn;
+reg     SIEPortTxRdy, next_SIEPortTxRdy;
+wire    SIEPortWEn;
+reg     [7:0]TxByteOut, next_TxByteOut;
+reg     [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg     TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [2:0]i, next_i;
+reg  [15:0]resumeCnt, next_resumeCnt;
+reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg  [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define DIR_CTL_CHK_FIN 6'b000000
+`define RES_ST_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
+`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
+`define PKT_ST_HS_PKT_SENT 6'b000111
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
+`define PKT_ST_SPCL_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_SND_J_1 6'b001110
+`define RES_ST_SND_J_2 6'b001111
+`define RES_ST_SND_SE0_1 6'b010000
+`define RES_ST_SND_SE0_2 6'b010001
+`define START_SIETX 6'b010010
+`define STX_CHK_ST 6'b010011
+`define STX_WAIT_BYTE 6'b010100
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
+`define RES_ST_W_RDY1 6'b011000
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
+`define RES_ST_WAIT_GNT 6'b011100
+`define DIR_CTL_WAIT_GNT 6'b011101
+`define PKT_ST_HS_WAIT_RDY 6'b011110
+`define PKT_ST_SPCL_WAIT_RDY 6'b011111
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
+`define RES_ST_WAIT_RDY 6'b100011
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
+`define DIR_CTL_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
+`define PKT_ST_WAIT_RDY_PKT 6'b101001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
+`define TX_LS_EOP_WAIT_GNT1 6'b101101
+`define TX_LS_EOP_SND_SE0_2 6'b101110
+`define TX_LS_EOP_SND_SE0_1 6'b101111
+`define TX_LS_EOP_W_RDY1 6'b110000
+`define TX_LS_EOP_SND_J 6'b110001
+`define TX_LS_EOP_W_RDY2 6'b110010
+`define TX_LS_EOP_W_RDY3 6'b110011
+`define RES_ST_DELAY 6'b110100
+`define RES_ST_W_RDY2 6'b110101
+`define RES_ST_W_RDY3 6'b110110
+`define RES_ST_W_RDY4 6'b110111
+`define DIR_CTL_DELAY 6'b111000
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)
+begin
+  NextState_SIETx <= CurrState_SIETx;
+  // Set default values for outputs and signals
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_USBWireReq <= USBWireReq;
+  next_processTxByteWEn <= processTxByteWEn;
+  next_rstCRC <= rstCRC;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  next_TxByteOut <= TxByteOut;
+  next_TxByteOutCtrl <= TxByteOutCtrl;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_SIEPortTxRdy <= SIEPortTxRdy;
+  next_SIEPortData <= SIEPortData;
+  next_SIEPortCtrl <= SIEPortCtrl;
+  next_resumeCnt <= resumeCnt;
+  next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
+  case (CurrState_SIETx)  // synopsys parallel_case full_case
+    `IDLE:
+    begin
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `START_SIETX:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_TxByteOut <= 8'h00;
+      next_TxByteOutCtrl <= 8'h00;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_SIEPortTxRdy <= 1'b0;
+      next_SIEPortData <= 8'h00;
+      next_SIEPortCtrl <= 8'h00;
+      next_i <= 3'h0;
+      next_resumeCnt <= 16'h0000;
+      next_TxByteOutFullSpeedRate <= 1'b0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `STX_CHK_ST:
+    begin
+      if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+        next_TxByteOutFullSpeedRate <= 1'b1;
+        //SOF and PRE always at full speed
+      end
+      else if (SIEPortCtrl == `TX_PACKET_START)
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+      end
+      else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_IDLE)
+      begin
+        NextState_SIETx <= `IDLE;
+      end
+      else if (SIEPortCtrl == `TX_RESUME_START)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+        next_resumeCnt <= 16'h0000;
+        next_USBWireFullSpeedRate <= 1'b0;
+        //resume always uses low speed timing
+      end
+    end
+    `STX_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `STX_CHK_ST;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+        next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
+        next_USBWireFullSpeedRate <= fullSpeedRateIn;
+      end
+    end
+    `DIR_CTL_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_i <= i + 1'b1;
+      if (i == 3'h7)
+      begin
+        NextState_SIETx <= `STX_WAIT_BYTE;
+        next_USBWireReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_SIETx <= `DIR_CTL_DELAY;
+      end
+    end
+    `DIR_CTL_WAIT_GNT:
+    begin
+      next_i <= 3'h0;
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+      end
+    end
+    `DIR_CTL_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_CHK_FIN;
+        next_USBWireData <= SIEPortData[1:0];
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `DIR_CTL_DELAY:
+    begin
+      NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+    end
+    `PKT_ST_CHK_PID:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      if (SIEPortData[1:0] == `TOKEN)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `HANDSHAKE)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `DATA)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `SPECIAL)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+      end
+    end
+    `PKT_ST_WAIT_RDY_PKT:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_CHK_PID;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= `SYNC_BYTE;
+        next_TxByteOutCtrl <= `DATA_START;
+      end
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT2:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY1:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[7:0];
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY2:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[15:8];
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_DATA_DATA_CHK_STOP:
+    begin
+      if (SIEPortCtrl == `TX_PACKET_STOP)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+      end
+    end
+    `PKT_ST_DATA_DATA_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_DATA_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC16En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+    end
+    `PKT_ST_DATA_DATA_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_RDY:
+    begin
+      next_CRC16En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+      end
+    end
+    `PKT_ST_DATA_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `PKT_ST_HS_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_HS_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_SPCL_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_SPCL_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_BYTE1_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_CRC_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_CRC_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+    end
+    `PKT_ST_TKN_CRC_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `RES_ST_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (resumeCnt == `HOST_TX_RESUME_TIME)
+      begin
+        NextState_SIETx <= `RES_ST_W_RDY1;
+      end
+      else
+      begin
+        NextState_SIETx <= `RES_ST_DELAY;
+      end
+    end
+    `RES_ST_SND_J_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY4;
+    end
+    `RES_ST_SND_J_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+      next_USBWireFullSpeedRate <= fullSpeedRateIn;
+    end
+    `RES_ST_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY2;
+    end
+    `RES_ST_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY3;
+    end
+    `RES_ST_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_RDY;
+      end
+    end
+    `RES_ST_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_CHK_FIN;
+        next_USBWireData <= KBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+        next_resumeCnt <= resumeCnt  + 1'b1;
+      end
+    end
+    `RES_ST_DELAY:
+    begin
+      NextState_SIETx <= `RES_ST_WAIT_RDY;
+    end
+    `RES_ST_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_W_RDY4:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_2;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `TX_LS_EOP_WAIT_GNT1:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_W_RDY1;
+      end
+    end
+    `TX_LS_EOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY3;
+    end
+    `TX_LS_EOP_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY2;
+    end
+    `TX_LS_EOP_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `TX_LS_EOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `TX_LS_EOP_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `TX_LS_EOP_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_J;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SIETx <= `START_SIETX;
+  else
+    CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    USBWireWEn <= 1'b0;
+    USBWireReq <= 1'b0;
+    processTxByteWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+    TxByteOut <= 8'h00;
+    TxByteOutCtrl <= 8'h00;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    SIEPortTxRdy <= 1'b0;
+    TxByteOutFullSpeedRate <= 1'b0;
+    i <= 3'h0;
+    SIEPortData <= 8'h00;
+    SIEPortCtrl <= 8'h00;
+    resumeCnt <= 16'h0000;
+  end
+  else 
+  begin
+    USBWireWEn <= next_USBWireWEn;
+    USBWireReq <= next_USBWireReq;
+    processTxByteWEn <= next_processTxByteWEn;
+    rstCRC <= next_rstCRC;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+    TxByteOut <= next_TxByteOut;
+    TxByteOutCtrl <= next_TxByteOutCtrl;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    SIEPortTxRdy <= next_SIEPortTxRdy;
+    TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
+    i <= next_i;
+    SIEPortData <= next_SIEPortData;
+    SIEPortCtrl <= next_SIEPortCtrl;
+    resumeCnt <= next_resumeCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.asf	(revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processRxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC5Result != 5'h6)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    if (RXDataByteCnt > 10'h2) \n    begin\n      RxOverflow <= 1'b1;\n      RxDataOut <= RxStatus;\n      RxCtrlOut <= `RX_PACKET_STOP;\n      RXByteStMachCurrState <= `IDLE_BYTE_ST;\n    end\n    else \n    begin\n      RxDataOut <= RxByte;\n      RxCtrlOut <= `RX_PACKET_STREAM;\n      CRCData <= RxByte;\n      CRC5_8Bit <= 1'b1;\n      CRC5En <= 1'b1;\n    end\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+I 221 217 0 Builtin Exit | 136710,89055
+I 220 217 0 Builtin Entry | 86360,167640
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+I 228 224 0 Builtin Exit | 129540,111760
+I 227 224 0 Builtin Entry | 86360,167640
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+I 253 248 0 Builtin Exit | 78564,173120
+I 252 248 0 Builtin Entry | 35384,229000
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n  `SPECIAL:                              //Special PID.\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  `TOKEN:                                //Token PID\n  begin\n    RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\n  `HANDSHAKE:                            //Handshake PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        ACKRxed <= 1'b1;\n      2'b10:\n        NAKRxed <= 1'b1;\n      2'b11:\n        stallRxed <= 1'b1;\n      default:\n      begin\n        $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n      end\n    endcase\n    RXByteStMachCurrState <= `HS_BYTE_ST;\n  end\n  `DATA:                                  //Data PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        dataSequence <= 1'b0;\n      2'b10:\n        dataSequence <= 1'b1;\n      default:\n        $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n    endcase\n    RXByteStMachCurrState <= `DATA_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\nendcase"
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n  RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n  RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n  RXByteStMachCurrState = `IDLE_BYTE_ST;"
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+                                        89364,102368 89220,95212 89220,94846
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+I 259 32 0 Builtin Entry | 66351,233704
+I 260 32 0 Builtin Exit | 110355,78302
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n  RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+                                          110499,87996 110355,80840 110355,80474
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/readUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/readUSBWireData.v	(revision 264)
@@ -0,0 +1,227 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// readUSBWireData.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive);
+input   [1:0] RxBitsIn;
+output  RxDataInTick;
+input   SIERxRdyIn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+input   TxWireActiveDrive;
+output  [1:0] RxBitsOut;
+output  SIERxWEn;
+output noActivityTimeOut;
+output RxWireActive;
+
+wire   [1:0] RxBitsIn;
+reg    RxDataInTick;
+wire   SIERxRdyIn;
+wire   clk;
+wire   fullSpeedRate;
+wire   rst;
+reg    [1:0] RxBitsOut;
+reg    SIERxWEn;
+reg    noActivityTimeOut;
+reg    RxWireActive;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg  [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg RxWireEdgeDetect;
+reg RxWireActiveReg1;
+reg RxWireActiveReg2;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    RxDataInTick <= 1'b0;
+    RxWireEdgeDetect <= 1'b0;
+    RxWireActiveReg1 <= 1'b0;
+    RxWireActiveReg2 <= 1'b0;
+  end
+  else begin
+    RxWireActiveReg2 <= RxWireActiveReg1; //Delay RxWireActiveReg1 until after i has been reset
+    RxBitsInReg <= RxBitsIn;      //sync incoming data to local clock to avoid metastability issues
+    incBufferCnt <= 1'b0;         //default value
+    oldRxBitsIn <= RxBitsInReg;
+    if ( (TxWireActiveDrive == 1'b0) && (oldRxBitsIn != RxBitsInReg)) begin  //if edge detected then
+      i <= 5'b00000;              //reset the counter
+      RxWireEdgeDetect <= 1'b1;       // flag receive activity 
+      RxWireActiveReg1 <= 1'b1;
+    end
+    else begin
+      i <= i + 1'b1;
+      RxWireEdgeDetect <= 1'b0;
+    end
+    if (noActivityTimeOut == 1'b1)
+      RxWireActiveReg1 <= 1'b0;
+    if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b01) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+    begin
+      RxDataInTick <= !RxDataInTick;
+      if (TxWireActiveDrive != 1'b1)  //do not read wire data when transmitter is active
+      begin
+        incBufferCnt <= 1'b1;
+        bufferInIndex <= bufferInIndex + 1'b1;
+        case (bufferInIndex)
+          2'b00 : buffer0 <= {RxWireActiveReg2, RxBitsInReg}; 
+          2'b01 : buffer1 <= {RxWireActiveReg2, RxBitsInReg};
+          2'b10 : buffer2 <= {RxWireActiveReg2, RxBitsInReg};
+          2'b11 : buffer3 <= {RxWireActiveReg2, RxBitsInReg};
+        endcase
+      end
+    end
+  end
+end
+
+        
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    decBufferCnt <= 1'b0;
+    bufferOutIndex <= 2'b00;
+    RxBitsOut <= 2'b00;
+    SIERxWEn <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+  end
+  else begin
+    case (bufferOutStMachCurrState)
+      `WAIT_BUFFER_NOT_EMPTY:
+      begin
+        if (bufferCnt != 3'b000)
+          bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+      end
+      `WAIT_SIE_RX_READY:
+      begin
+        if (SIERxRdyIn == 1'b1)
+        begin 
+          SIERxWEn <= 1'b1;
+          bufferOutStMachCurrState <= `SIE_RX_WRITE;
+          decBufferCnt <= 1'b1;
+          bufferOutIndex <= bufferOutIndex + 1'b1;
+          case (bufferOutIndex)
+            2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
+            2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
+            2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
+            2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
+          endcase
+        end
+      end
+      `SIE_RX_WRITE:
+      begin
+        SIERxWEn <= 1'b0;
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+      end
+    endcase
+  end
+end
+
+//generate time out flag if no tx or rx activity
+always @(posedge clk) begin
+  if (rst) begin
+    timeOutCnt <= 16'h0000;
+    noActivityTimeOut <= 1'b0;
+  end
+  else begin
+    if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1)
+      timeOutCnt <= 16'h0000;
+    else 
+      timeOutCnt <= timeOutCnt + 1'b1;
+    if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+          || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
+      noActivityTimeOut <= 1'b1;
+    else 
+      noActivityTimeOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC5.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC5.v	(revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC5.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   CRC5_8BitIn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [4:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   CRC5_8BitIn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 5'h1f;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0) begin
+      if (CRCEn == 1'b1) begin
+        ready <= 1'b0;
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        if (CRC5_8BitIn == 1'b1) begin
+          loopEnd <= 4'h7; 
+        end
+        else begin
+          loopEnd <= 4'h2;
+        end
+      end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[4:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == loopEnd) begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/writeUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/writeUSBWireData.v	(revision 264)
@@ -0,0 +1,281 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// writeUSBWireData.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL  3'b100
+
+module writeUSBWireData (
+  TxBitsIn, 
+  TxBitsOut,
+   TxDataOutTick,
+  TxCtrlIn, 
+  TxCtrlOut, 
+  USBWireRdy,
+  USBWireWEn, 
+  TxWireActiveDrive, 
+  fullSpeedRate, 
+  clk, 
+  rst
+   );
+  
+input   [1:0] TxBitsIn;
+input   TxCtrlIn;
+input   USBWireWEn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+output  [1:0] TxBitsOut;
+output TxDataOutTick;
+output  TxCtrlOut;
+output  USBWireRdy;
+output  TxWireActiveDrive;
+
+wire    [1:0] TxBitsIn;
+reg     [1:0] TxBitsOut;
+reg     TxDataOutTick;
+wire    TxCtrlIn;
+reg     TxCtrlOut;
+reg     USBWireRdy;
+wire    USBWireWEn;
+wire    clk;
+wire    fullSpeedRate;
+wire    rst;
+reg     TxWireActiveDrive;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else
+  begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+//buffer input state machine 
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+     incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    USBWireRdy <= 1'b0;
+    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+  end
+  else begin
+    case (bufferInStMachCurrState)
+      `WAIT_BUFFER_NOT_FULL:
+      begin
+        if (bufferCnt != `BUFFER_FULL)  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+      end
+      `WAIT_WRITE_REQ:
+      begin
+        if (USBWireWEn == 1'b1)
+        begin
+          incBufferCnt <= 1'b1;
+          USBWireRdy <= 1'b0;
+          bufferInIndex <= bufferInIndex + 1'b1;
+          case (bufferInIndex)
+            2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+            2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+            2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+            2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+          endcase
+          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+        end
+      end
+      `CLR_INC_BUFFER_CNT:
+      begin
+        incBufferCnt <= 1'b0;
+        if (bufferCnt != (`BUFFER_FULL - 1'b1) )  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+        else begin
+          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+        end
+      end
+    endcase
+  end
+end
+        
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    fullSpeedTick <= 1'b0;
+    lowSpeedTick <= 1'b0;
+  end
+  else
+  begin
+    i <= i + 1'b1;
+    if (i[1:0] == 2'b00)
+      fullSpeedTick <= 1'b1;
+    else
+      fullSpeedTick <= 1'b0; 
+    if (i == 5'b00000)
+      lowSpeedTick <= 1'b1;
+    else
+      lowSpeedTick <= 1'b0;
+  end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferOutIndex <= 2'b00;
+    decBufferCnt <= 1'b0;
+    TxBitsOut <= 2'b00;
+    TxCtrlOut <= `TRI_STATE;
+    TxDataOutTick <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+  end
+  else
+  begin
+    case (bufferOutStMachCurrState)
+      `WAIT_LINE_WRITE:
+      begin
+        if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+        begin
+          TxDataOutTick <= !TxDataOutTick;
+          if (bufferCnt == 0) begin
+            TxBitsOut <= 2'b00;
+            TxCtrlOut <= `TRI_STATE;
+          end
+          else begin
+            bufferOutStMachCurrState <= `LINE_WRITE;
+            decBufferCnt <= 1'b1;
+            bufferOutIndex <= bufferOutIndex + 1'b1;
+            case (bufferOutIndex)
+              2'b00 :
+            begin 
+              TxBitsOut <= buffer0[2:1];
+              TxCtrlOut <= buffer0[0];
+            end
+            2'b01 : 
+            begin
+              TxBitsOut <= buffer1[2:1];
+              TxCtrlOut <= buffer1[0];
+            end
+            2'b10 : 
+            begin 
+              TxBitsOut <= buffer2[2:1];
+              TxCtrlOut <= buffer2[0];
+            end
+            2'b11 : 
+            begin
+              TxBitsOut <= buffer3[2:1];
+              TxCtrlOut <= buffer3[0];
+            end
+            endcase
+          end
+        end
+      end
+      `LINE_WRITE:
+      begin
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+      end
+    endcase
+  end
+end
+
+// control 'TxWireActiveDrive' 
+always @(TxCtrlOut)
+begin  
+  if (TxCtrlOut == `DRIVE)
+    TxWireActiveDrive <= 1'b1;
+  else
+    TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.asf	(revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SCTxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SARB_SEND_PACKET\n/1/"
+S 14 6 4096 ELLIPSE "States" | 269063,296392 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 10 6 0 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_SARB\n/3/"
+S 8 6 12288 ELLIPSE "States" | 225591,395370 6500 6500
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "SCTxArb"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,543100 1 0 0 "Module: SCTxPortArbiter"
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+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
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+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+C 26 17 0 TEXT "Conditions" | 202073,391408 1 0 0 "rst"
+A 25 8 2 TEXT "Actions" | 234434,411387 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
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+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
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+L 43 42 0 TEXT "Labels" | 172566,462781 1 0 0 "SCTxPortRdyIn"
+I 42 0 2 Builtin InPort | 166566,462781 "" ""
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+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
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+L 61 41 0 TEXT "Labels" | 196061,536582 1 0 0 "clk"
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+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n  SCTxPortRdyOut = SCTxPortRdyIn;\nend\n	  \nalways @(muxDCEn or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n  begin  \n    SCTxPortWEnable <= directCntlWEn;\n    SCTxPortData <= directCntlData;\n    SCTxPortCntl <= directCntlCntl;\n  end\nelse\n  begin  \n    SCTxPortWEnable <= sendPacketWEn;\n    SCTxPortData <= sendPacketData;\n    SCTxPortCntl <= sendPacketCntl;\n  end\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
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+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxDCEn"
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+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
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+I 80 0 2 Builtin InPort | 120331,452467 "" ""
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+                                      264783,394808 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.v	(revision 264)
@@ -0,0 +1,276 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIEReceiver
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
+input   clk;
+input   rst;
+input   [1:0]RxWireDataIn;
+input   RxWireDataWEn;
+output  [1:0]connectState;
+
+wire    clk;
+reg     [1:0]connectState, next_connectState;
+wire    rst;
+wire    [1:0]RxWireDataIn;
+wire    RxWireDataWEn;
+
+// diagram signals declarations
+reg  [1:0]RxBits, next_RxBits;
+reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg  [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
+begin
+  NextState_rcvr <= CurrState_rcvr;
+  // Set default values for outputs and signals
+  next_RXWaitCount <= RXWaitCount;
+  next_connectState <= connectState;
+  next_RXStMachCurrState <= RXStMachCurrState;
+  next_RxBits <= RxBits;
+  case (CurrState_rcvr)  // synopsys parallel_case full_case
+    `WAIT_BIT:
+    begin
+      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+      begin
+        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+      begin
+        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+        next_RxBits <= RxWireDataIn;
+      end
+    end
+    `START_SRX:
+    begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_RXWaitCount <= 8'h00;
+      next_connectState <= `DISCONNECT;
+      next_RxBits <= 2'b00;
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `DISCNCT_CHK_RXBITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else if (RxBits == `ONE_ZERO)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+      end
+    end
+    `WAIT_FS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ONE_ZERO)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `FULL_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `WAIT_LS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `LOW_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `LS_CONN_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+      next_RXWaitCount <= 0;
+      end
+    end
+    `FS_CONN_CHK_RX_BITS1:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+      next_RXWaitCount <= 0;
+      end
+    end
+    `WAIT_LS_DIS_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_connectState <= `DISCONNECT;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+    end
+    `WAIT_FS_DIS_CHK_RX_BITS2:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_connectState <= `DISCONNECT;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_rcvr <= `START_SRX;
+  else
+    CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    connectState <= `DISCONNECT;
+    RXWaitCount <= 8'h00;
+    RXStMachCurrState <= `DISCONNECT_ST;
+    RxBits <= 2'b00;
+  end
+  else 
+  begin
+    connectState <= next_connectState;
+    RXWaitCount <= next_RXWaitCount;
+    RXStMachCurrState <= next_RXStMachCurrState;
+    RxBits <= next_RxBits;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(revision 264)
@@ -0,0 +1,111 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=134
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// usbTxWireArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
+F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
+W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
+W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
+W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+C 62 21 0 TEXT "Conditions" | 105671,125880 1 0 0 "rst"
+W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
+                                      200193,83454 202194,93721 199799,97969 197405,102218\
+                                      189371,107780 182843,108050 176316,108321 158239,103840\
+                                      151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n  USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or\nSIETxFSRate or prcTxByteFSRate)  \nbegin\n  if (muxSIENotPTXB  == 1'b1)  \n  begin\n    USBWireWEn <= SIETxWEn;\n    TxBits <= SIETxData;\n    TxCtl <= SIETxCtrl;\n    TxFSRate <= SIETxFSRate;\n  end\n  else\n  begin\n    USBWireWEn <= prcTxByteWEn;\n    TxBits <= prcTxByteData;\n    TxCtl <= prcTxByteCtrl;\n    TxFSRate <= prcTxByteFSRate;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+                                      70311,70629 71874,86691 76817,93064 81761,99437\
+                                      89642,107471 97173,106158 104705,104845 116882,95874\
+                                      123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 173058,181792 "" ""
+L 110 111 0 TEXT "Labels" | 179058,181792 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 140655,159238 "" ""
+L 108 109 0 TEXT "Labels" | 146655,159238 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 175368,186412 "" ""
+L 106 107 0 TEXT "Labels" | 181368,186412 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 138576,154618 "" ""
+L 104 105 0 TEXT "Labels" | 144576,154618 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 130 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 175137,200041 "" ""
+L 122 123 0 TEXT "Labels" | 181137,200041 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 175137,195652 "" ""
+L 120 121 0 TEXT "Labels" | 181137,195652 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 175137,191032 "" ""
+L 118 119 0 TEXT "Labels" | 181137,191032 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 140655,173329 "" ""
+L 116 117 0 TEXT "Labels" | 146655,173329 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 140655,168940 "" ""
+L 114 115 0 TEXT "Labels" | 146655,168940 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 140655,164089 "" ""
+L 112 113 0 TEXT "Labels" | 146655,164089 1 0 0 "SIETxData[1:0]"
+L 128 129 0 TEXT "Labels" | 146868,178208 1 0 0 "SIETxFSRate"
+I 129 0 2 Builtin InPort | 140868,178208 "" ""
+L 130 131 0 TEXT "Labels" | 181140,205088 1 0 0 "prcTxByteFSRate"
+I 131 0 2 Builtin InPort | 175140,205088 "" ""
+L 132 133 0 TEXT "Labels" | 148212,207440 1 0 0 "TxFSRate"
+I 133 0 2 Builtin OutPort | 142212,207440 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/endpMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/endpMux.v	(revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// endpMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSlaveControl_h.v" 
+
+module endpMux (
+  clk, 
+  rst,
+  currEndP,
+  NAKSent,
+  stallSent,
+  CRCError,
+  bitStuffError,
+  RxOverflow,
+  RxTimeOut,
+  dataSequence,
+  ACKRxed,
+  transType,
+  transTypeNAK,
+  endPControlReg,
+  clrEPRdy,
+  endPMuxErrorsWEn,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  endP0StatusReg,
+  endP1StatusReg,
+  endP2StatusReg,
+  endP3StatusReg,
+  endP0TransTypeReg,
+  endP1TransTypeReg,
+  endP2TransTypeReg,
+  endP3TransTypeReg,
+  endP0NAKTransTypeReg,
+  endP1NAKTransTypeReg,
+  endP2NAKTransTypeReg,
+  endP3NAKTransTypeReg,
+  clrEP0Rdy,
+  clrEP1Rdy,
+  clrEP2Rdy,
+  clrEP3Rdy);
+
+
+input clk; 
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [4:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [4:0] endP0ControlReg;
+input [4:0] endP1ControlReg;
+input [4:0] endP2ControlReg;
+input [4:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk; 
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [4:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      endPControlReg <= endP0ControlReg;
+      clrEP0Rdy <= clrEPRdy;
+    end
+    2'b01: begin
+      endPControlReg <= endP1ControlReg;
+      clrEP1Rdy <= clrEPRdy;
+    end
+    2'b10: begin
+      endPControlReg <= endP2ControlReg;
+      clrEP2Rdy <= clrEPRdy;
+    end
+    2'b11: begin
+      endPControlReg <= endP3ControlReg;
+      clrEP3Rdy <= clrEPRdy;
+    end
+  endcase  
+end      
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+  if (rst) begin
+    endP0NAKTransTypeReg <= 2'b00;
+    endP1NAKTransTypeReg <= 2'b00;
+    endP2NAKTransTypeReg <= 2'b00;
+    endP3NAKTransTypeReg <= 2'b00;
+    endP0TransTypeReg <= 2'b00;
+    endP1TransTypeReg <= 2'b00;
+    endP2TransTypeReg <= 2'b00;
+    endP3TransTypeReg <= 2'b00;
+    endP0StatusReg <= 4'h0;
+    endP1StatusReg <= 4'h0;
+    endP2StatusReg <= 4'h0;
+    endP3StatusReg <= 4'h0;
+  end
+  else begin
+    if (endPMuxErrorsWEn == 1'b1) begin
+      if (NAKSent == 1'b1) begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0NAKTransTypeReg <= transTypeNAK;
+            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; 
+          end
+          2'b01: begin
+            endP1NAKTransTypeReg <= transTypeNAK;
+            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; 
+          end
+          2'b10: begin
+            endP2NAKTransTypeReg <= transTypeNAK;
+            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; 
+          end
+          2'b11: begin
+            endP3NAKTransTypeReg <= transTypeNAK;
+            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; 
+          end
+        endcase
+      end
+      else begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0TransTypeReg <= transType;
+            endP0StatusReg <= endPStatusCombine; 
+          end
+          2'b01: begin
+            endP1TransTypeReg <= transType;
+            endP1StatusReg <= endPStatusCombine; 
+          end
+          2'b10: begin
+            endP2TransTypeReg <= transType;
+            endP2StatusReg <= endPStatusCombine; 
+          end
+          2'b11: begin
+            endP3TransTypeReg <= transType;
+            endP3StatusReg <= endPStatusCombine; 
+          end
+        endcase
+      end
+    end
+  end
+end
+        
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveDirectControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= {6'b000000, directControlLineState}; \nSCTxPortCntl <= `TX_DIRECT_CONTROL;"
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+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= 8'h00; \nSCTxPortCntl <= `TX_IDLE;"
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+L 178 179 0 TEXT "Labels" | 63352,247790 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,247790 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveRxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveRxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveRxStatusMonitor.v                                       ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      resetEventOut <= 1'b1;
+    else
+      resetEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.v	(revision 264)
@@ -0,0 +1,518 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input   bitStuffError;
+input   clk;
+input   CRCError;
+input   getPacketRdy;
+input   rst;
+input   [7:0]RxByte;
+input   RxDataWEn;
+input   RxOverflow;
+input   [7:0]RxStatus;
+input   RxTimeOut;
+input   SCGlobalEn;
+input   sendPacketRdy;
+input   [4:0]USBEndPControlReg;
+input   [6:0]USBTgtAddress;
+output  clrEPRdy;
+output  endPMuxErrorsWEn;
+output  endPointReadyToGetPkt;
+output  [10:0]frameNum;
+output  getPacketREn;
+output  NAKSent;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  SOFRxed;
+output  stallSent;
+output  transDone;
+output  [3:0]USBEndP;
+output  [1:0]USBEndPNakTransTypeReg;
+output  [1:0]USBEndPTransTypeReg;
+
+wire    bitStuffError;
+wire    clk;
+reg     clrEPRdy, next_clrEPRdy;
+wire    CRCError;
+reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg     endPointReadyToGetPkt, next_endPointReadyToGetPkt;
+reg     [10:0]frameNum, next_frameNum;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+reg     NAKSent, next_NAKSent;
+wire    rst;
+wire    [7:0]RxByte;
+wire    RxDataWEn;
+wire    RxOverflow;
+wire    [7:0]RxStatus;
+wire    RxTimeOut;
+wire    SCGlobalEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     SOFRxed, next_SOFRxed;
+reg     stallSent, next_stallSent;
+reg     transDone, next_transDone;
+reg     [3:0]USBEndP, next_USBEndP;
+wire    [4:0]USBEndPControlReg;
+reg     [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg     [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire    [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg  [7:0]addrEndPTemp, next_addrEndPTemp;
+reg  [7:0]endpCRCTemp, next_endpCRCTemp;
+reg  [7:0]PIDByte, next_PIDByte;
+reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg  [6:0]USBAddress, next_USBAddress;
+reg  [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define SETUP_OUT_CHK 5'b01011
+`define SETUP_OUT_SEND 5'b01100
+`define SETUP_OUT_GET_PKT 5'b01101
+`define START_S1 5'b01110
+`define GET_TOKEN_DELAY 5'b01111
+`define GET_TOKEN_CHK_ADDR 5'b10000
+`define IN_RESP_GET_RESP 5'b10001
+`define IN_RESP_DATA 5'b10010
+`define IN_RESP_CHK_ISO 5'b10011
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlRegCopy or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or USBEndPControlReg or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or endPointReadyToGetPkt or CurrState_slvCntrl)
+begin
+  NextState_slvCntrl <= CurrState_slvCntrl;
+  // Set default values for outputs and signals
+  next_stallSent <= stallSent;
+  next_NAKSent <= NAKSent;
+  next_SOFRxed <= SOFRxed;
+  next_PIDByte <= PIDByte;
+  next_transDone <= transDone;
+  next_clrEPRdy <= clrEPRdy;
+  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+  next_endpCRCTemp <= endpCRCTemp;
+  next_addrEndPTemp <= addrEndPTemp;
+  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+  next_frameNum <= frameNum;
+  next_USBAddress <= USBAddress;
+  next_USBEndP <= USBEndP;
+  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  next_getPacketREn <= getPacketREn;
+  next_USBEndPControlRegCopy <= USBEndPControlRegCopy;
+  next_endPointReadyToGetPkt <= endPointReadyToGetPkt;
+  case (CurrState_slvCntrl)  // synopsys parallel_case full_case
+    `WAIT_RX1:
+    begin
+      next_stallSent <= 1'b0;
+      next_NAKSent <= 1'b0;
+      next_SOFRxed <= 1'b0;
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_START && 
+        RxByte[1:0] == `TOKEN)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+        next_PIDByte <= RxByte;
+      end
+    end
+    `FIN_SC:
+    begin
+      next_transDone <= 1'b0;
+      next_clrEPRdy <= 1'b0;
+      next_endPMuxErrorsWEn <= 1'b0;
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_PID:
+    begin
+      if (PIDByte[3:0] == `SETUP)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if (PIDByte[3:0] == `OUT)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `IN_CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+      else if (PIDByte[3:0] == `IN)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `PID_ERROR;
+      end
+    end
+    `PID_ERROR:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_RDY:
+    begin
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_transDone <= 1'b1;
+        next_clrEPRdy <= 1'b1;
+        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else if (NAKSent == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+      end
+    end
+    `SETUP_OUT_CHK:
+    begin
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `SETUP_OUT_SEND:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `SETUP_OUT_GET_PKT:
+    begin
+      next_getPacketREn <= 1'b0;
+      if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+      else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+        bitStuffError == 1'b0 && 
+        RxOverflow == 1'b0 && 
+        RxTimeOut == 1'b0))
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_CHK;
+      end
+      else if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_NAK_STALL:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_CHK_RDY:
+    begin
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `IN_RESP_GET_RESP:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_RESP_DATA:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_RESP_CHK_ISO;
+      end
+    end
+    `IN_RESP_CHK_ISO:
+    begin
+      if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_GET_RESP;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `START_S1:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `GET_TOKEN_WAIT_CRC:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+        next_endpCRCTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_ADDR:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+        next_addrEndPTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_STOP:
+    begin
+      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+      end
+      else if (RxDataWEn == 1'b1)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_CHK_SOF:
+    begin
+      if (PIDByte[3:0] == `SOF)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+        next_SOFRxed <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_DELAY;
+        next_USBAddress <= addrEndPTemp[6:0];
+        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+      end
+    end
+    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndP etc to update
+    begin
+      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+    end
+    `GET_TOKEN_CHK_ADDR:
+    begin
+      if (USBEndP < `NUM_OF_ENDPOINTS  &&
+        USBAddress == USBTgtAddress &&
+        SCGlobalEn == 1'b1 &&
+        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_PID;
+        next_USBEndPControlRegCopy <= USBEndPControlReg;
+        next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
+      end
+      else
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvCntrl <= `START_S1;
+  else
+    CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    stallSent <= 1'b0;
+    NAKSent <= 1'b0;
+    SOFRxed <= 1'b0;
+    transDone <= 1'b0;
+    clrEPRdy <= 1'b0;
+    endPMuxErrorsWEn <= 1'b0;
+    frameNum <= 11'b00000000000;
+    USBEndP <= 4'h0;
+    USBEndPTransTypeReg <= 2'b00;
+    USBEndPNakTransTypeReg <= 2'b00;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    getPacketREn <= 1'b0;
+    endPointReadyToGetPkt <= 1'b0;
+    PIDByte <= 8'h00;
+    endpCRCTemp <= 8'h00;
+    addrEndPTemp <= 8'h00;
+    tempUSBEndPTransTypeReg <= 2'b00;
+    USBAddress <= 7'b0000000;
+    USBEndPControlRegCopy <= 5'b00000;
+  end
+  else 
+  begin
+    stallSent <= next_stallSent;
+    NAKSent <= next_NAKSent;
+    SOFRxed <= next_SOFRxed;
+    transDone <= next_transDone;
+    clrEPRdy <= next_clrEPRdy;
+    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+    frameNum <= next_frameNum;
+    USBEndP <= next_USBEndP;
+    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+    getPacketREn <= next_getPacketREn;
+    endPointReadyToGetPkt <= next_endPointReadyToGetPkt;
+    PIDByte <= next_PIDByte;
+    endpCRCTemp <= next_endpCRCTemp;
+    addrEndPTemp <= next_addrEndPTemp;
+    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+    USBAddress <= next_USBAddress;
+    USBEndPControlRegCopy <= next_USBEndPControlRegCopy;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.asf	(revision 264)
@@ -0,0 +1,408 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=863
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
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+L 834 833 0 TEXT "State Labels" | 56676,100586 1 0 0 "GET_RESP\n/17/"
+S 839 821 110592 ELLIPSE "States" | 49830,194919 6500 6500
+L 840 839 0 TEXT "State Labels" | 49830,194919 1 0 0 "DATA\n/18/"
+A 843 833 4 TEXT "Actions" | 70674,110022 1 0 0 "getPacketREn <= 1'b0;"
+W 844 821 0 839 847 BEZIER "Transitions" | 51640,188679 108408,173735 108918,187523 139645,180358
+C 845 844 0 TEXT "Conditions" | 79180,187273 1 0 0 "sendPacketRdy == 1'b1"
+A 846 839 4 TEXT "Actions" | 65120,205455 1 0 0 "sendPacketWEn <= 1'b0;"
+S 847 821 114688 ELLIPSE "States" | 145546,183083 6500 6500
+I 862 0 2 Builtin OutPort | 120122,261308 "" ""
+L 861 862 0 TEXT "Labels" | 126122,261308 1 0 0 "endPointReadyToGetPkt"
+A 860 457 16 TEXT "Actions" | 93778,19821 1 0 0 "USBEndPControlRegCopy <= USBEndPControlReg;\nendPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT] ;"
+I 859 0 130 Builtin Signal | 35412,208838 "" ""
+L 858 859 0 TEXT "Labels" | 38412,208838 1 0 0 "USBEndPControlRegCopy[4:0]"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+I 587 589 0 Builtin Exit | 192962,45432
+I 588 589 0 Builtin Entry | 205195,243792
+L 848 847 0 TEXT "State Labels" | 145546,183083 1 0 0 "CHK_ISO\n/19/"
+I 850 821 0 Builtin Entry | 49920,240120
+W 851 821 0 850 839 BEZIER "Transitions" | 49920,237971 49996,228608 49199,210758 49275,201395
+W 852 589 1 800 605 BEZIER "Transitions" | 112033,243004 131211,241916 168722,239928 178018,237332\
+                                           187314,234737 186141,226528 176133,223346 166125,220164\
+                                           127582,215026 108152,212765
+C 853 852 0 TEXT "Conditions" | 112257,227462 1 0 0 "USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0"
+W 854 821 0 833 832 BEZIER "Transitions" | 63119,99731 96001,98583 159828,94028 192710,92880
+C 855 854 0 TEXT "Conditions" | 79768,96292 1 0 0 "getPacketRdy == 1'b1"
+W 856 589 0 820 587 BEZIER "Transitions" | 73765,64656 103240,60314 160481,49774 189956,45432
+S 596 589 49152 ELLIPSE "States" | 180409,114797 6500 6500
+L 597 596 0 TEXT "State Labels" | 181443,115599 1 0 0 "NAK_STALL\n/9/"
+C 598 600 0 TEXT "Conditions" | 169310,83968 1 0 0 "sendPacketRdy == 1'b1"
+A 599 601 16 TEXT "Actions" | 160934,183503 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 600 589 8192 596 587 BEZIER "Transitions" | 180237,108305 188996,66496 180453,87386 196184,45432
+W 601 589 8193 605 596 BEZIER "Transitions" | 108219,211536 117760,212835 193154,194500 186733,113295
+A 603 596 4 TEXT "Actions" | 173404,104745 1 0 0 "sendPacketWEn <= 1'b0;"
+L 604 605 0 TEXT "State Labels" | 101725,211799 1 0 0 "CHK_RDY\n/10/"
+S 605 589 53248 ELLIPSE "States" | 101725,211799 6500 6500
+W 606 589 0 588 800 BEZIER "Transitions" | 201176,243744 189026,243939 117602,246614 110257,246222
+C 607 601 0 TEXT "Conditions" | 120473,202106 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 612 589 8194 605 596 BEZIER "Transitions" | 102126,205324 97268,194370 163866,132884 176477,119972
+W 613 589 8195 605 617 BEZIER "Transitions" | 96173,208420 81310,204985 61686,186612 53042,177585
+C 614 612 0 TEXT "Conditions" | 62794,182643 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 615 612 16 TEXT "Actions" | 138346,155279 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 619 618 0 Builtin Entry | 96520,152400
+I 620 618 0 Builtin Exit | 144780,101600
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 630 589 8193 617 820 BEZIER "Transitions" | 48004,172793 44616,170945 44594,164562 42823,162021\
+                                              41052,159480 41752,153900 40959,141711 40167,129522\
+                                              46701,89176 50135,78506 53570,67837 54978,65340\
+                                              57981,65109 60984,64878 60458,64813 61074,64659
+W 631 589 8194 617 820 BEZIER "Transitions" | 54078,173688 59930,171532 83885,163128 122946,146882\
+                                              162008,130636 151291,117855 140238,106874 129185,95894\
+                                              77774,78896 71279,71294
+C 636 630 0 TEXT "Conditions" | 35003,128975 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+A 637 630 16 TEXT "Actions" | 47297,102245 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 638 631 16 TEXT "Actions" | 117990,107831 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+I 96 722 0 Builtin Reset | 76296,129336
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+S 376 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 380 377 0 Builtin Entry | 48940,236580
+I 381 377 0 Builtin Exit | 206487,14249
+I 649 559 0 Builtin Entry | 37971,243103
+I 650 559 0 Builtin Exit | 194044,45058
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+C 652 651 0 TEXT "Conditions" | 116707,136533 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+S 654 559 61440 ELLIPSE "States" | 92422,152802 6500 6500
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/11/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+I 399 377 0 Builtin Link | 54419,17564
+S 656 559 65536 ELLIPSE "States" | 109789,85208 5889 6500
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/12/"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+                                              46511,172964 33727,90292 34975,71611 36223,52930\
+                                              35724,34993 37785,28932 39847,22872 46307,16188\
+                                              54419,15564
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+                                              60053,165183 57484,160822 55722,148570 53960,136319\
+                                              36935,95064 38880,77714 40826,60365 38327,20823\
+                                              54419,15564
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+                                           108160,233400 112640,227800 113920,224400 115200,221000\
+                                           116013,213096 116333,209096
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 422 421 0 Builtin Entry | 96520,152400
+I 423 421 0 Builtin Exit | 144780,101600
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+                                              69948,104476 47394,95074 43302,84878 39210,74682\
+                                              42917,24960 54419,15564
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/13/"
+S 690 559 69632 ELLIPSE "States" | 98991,238090 6500 6500
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+W 692 559 8194 698 654 BEZIER "Transitions" | 115978,206479 88070,190212 85643,190437 93781,159154
+C 693 692 0 TEXT "Conditions" | 66756,183110 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+                                              39220,148925 36609,140943 36571,133460 36533,125977\
+                                              38989,104026 47738,97617 56488,91209 87662,87731\
+                                              103933,85889
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 696 559 8195 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+                                              200304,203038 205920,186346 207441,167119 208962,147892\
+                                              209430,87676 208962,71608 208494,55540 206154,51484\
+                                              204438,50041 202722,48598 199528,45916 197266,45058
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+S 698 559 73748 ELLIPSE "Junction" | 117000,209824 3500 3500
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 700 699 0 Builtin Entry | 96520,152400
+I 701 699 0 Builtin Exit | 144780,101600
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+S 462 377 94208 ELLIPSE "States" | 94684,51331 6500 6500
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/16/"
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 723 722 81920 ELLIPSE "States" | 120650,127000 6500 6500
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/14/"
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;\nUSBEndPControlRegCopy <= 5'b00000;\nendPointReadyToGetPkt <= 1'b0;"
+I 726 722 0 Builtin Entry | 96520,152400
+I 727 722 0 Builtin Exit | 144780,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+C 468 457 0 TEXT "Conditions" | 82804,40533 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS  &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[4:0]"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+                                              46860,73975 46530,57145 47396,48771 48262,40398\
+                                              52522,23896 54419,15564
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+                                           209214,43082 209522,23062 208983,17094 208444,11127\
+                                           205980,7277 191773,6353 177567,5429 123205,5583\
+                                           106804,9317 90403,13052 79161,27836 75696,31763\
+                                           72231,35690 70888,36159 69579,36621
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+                                              53866,34676 56339,23332 57169,17564
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+                                            60717,97705 62441,84600 62616,78575
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+                                            105236,81091 81842,75191 69908,73378
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
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+                                           197050,45058
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+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
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+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
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+C 812 807 0 TEXT "Conditions" | 65637,235739 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlaveWrap.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlaveWrap.v	(revision 264)
@@ -0,0 +1,195 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlaveWrap.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. Enable connection to Altera Avalon bus
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module usbHostSlaveWrap(
+  clk, 
+  reset,
+  address, 
+  writedata, 
+  readdata, 
+  write, 
+  read,
+  waitrequest,
+  chipselect,
+  irq, 
+  usbClk,
+  USBWireVPI,
+  USBWireVMI,
+  USBWireDataInTick,
+  USBWireVPO,
+  USBWireVMO,
+  USBWireDataOutTick,
+  USBWireOutEn_n,
+  USBFullSpeed
+   );
+
+input clk;
+input reset;
+input [7:0] address; 
+input [7:0] writedata; 
+output [7:0] readdata; 
+input write; 
+input read;
+output waitrequest;
+input chipselect;
+output irq; 
+input usbClk;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+
+wire clk;
+wire reset;
+wire [7:0] address; 
+wire [7:0] writedata; 
+wire [7:0] readdata; 
+wire write; 
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire usbClk;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+
+//internal wiring 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+             hostResumeIntOut | hostTransDoneIntOut |
+             slaveSOFRxedIntOut | slaveResetEventIntOut |
+             slaveResumeIntOut | slaveTransDoneIntOut |
+             slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut; 
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+//Parameters declaration: 
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+  .clk_i(clk),
+  .rst_i(reset),
+  .address_i(address),
+  .data_i(writedata),
+  .data_o(readdata),
+  .we_i(write),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .usbClk(usbClk),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_01_00/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifoBI.v	(revision 264)
@@ -0,0 +1,146 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+  address, writeEn, strobe_i,
+  busClk, 
+  usbClk, 
+  rstSyncToBusClk, 
+  fifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoWEn,
+  forceEmptySyncToUsbClk,
+  forceEmptySyncToBusClk,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoWEn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+reg fifoWEn;
+reg forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg [5:0] forceEmptyShift;
+reg forceEmpty;
+reg forceEmptySyncToUsbClkFirst;
+
+//sync write
+always @(posedge busClk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+//generate 'forceEmptySyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) 
+    forceEmptyShift <= 6'b000000;
+  else begin
+    if (forceEmpty == 1'b1)
+      forceEmptyShift <= 6'b111111;
+    else
+      forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
+  end
+end
+assign forceEmptySyncToBusClk = forceEmptyShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+    forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
+    forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
+end
+
+
+
+// async read mux
+assign busDataOut = 8'h00;
+//always @(address or fifoFull or numElementsInFifo)
+//begin
+//  case (address)
+//      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+//      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+//      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+//      default: busDataOut <= 8'h00;
+//  endcase
+//end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoWEn <= 1'b1;
+  else
+    fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.asf	(revision 264)
@@ -0,0 +1,290 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=292
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveGetPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
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+W 24 6 0 9 23 BEZIER "Transitions" | 80937,195399 85165,197611 97342,194836 103310,191016
+S 23 6 69632 ELLIPSE "States" | 103550,184536 6500 6500
+L 22 23 0 TEXT "State Labels" | 103550,184536 1 0 0 "WAIT_EN\n/15/"
+C 20 18 0 TEXT "Conditions" | 110328,141940 1 0 0 "RXDataValid == 1'b1"
+W 18 6 0 11 15 BEZIER "Transitions" | 107724,143520 114924,137020 128014,124286 135214,117786
+W 288 120 1 137 287 BEZIER "Transitions" | 95908,234299 107108,237729 126700,246250 135590,247825\
+                                           144480,249400 155451,246954 162031,246674
+W 289 120 0 287 150 BEZIER "Transitions" | 171165,238205 175575,227075 185570,206490 187145,196410\
+                                           188720,186330 186200,168270 182490,161515 178780,154760\
+                                           166460,145800 160440,144225 154420,142650 142660,145310\
+                                           136360,146115 130060,146920 116620,147480 112140,147865\
+                                           107660,148250 105485,148701 103245,149191
+C 290 288 0 TEXT "Conditions" | 109060,253040 1 0 0 "endPointReady == 1'b0"
+K 291 287 0 TEXT "Comments" | 165840,251410 1 0 0 "Discard data"
+C 35 34 0 TEXT "Conditions" | 122487,97401 1 0 0 "RXStreamStatus == `RX_PACKET_START"
+W 34 6 8193 15 33 BEZIER "Transitions" | 139672,106864 139470,99693 141572,86202 141370,79031
+S 33 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141266,72558 6500 6500
+L 32 33 0 TEXT "State Labels" | 141266,72558 1 0 0 "PROC_PKT"
+L 39 40 0 TEXT "State Labels" | 106676,27624 1 0 0 "PKT_RDY\n/16/"
+S 40 6 73728 ELLIPSE "States" | 106676,27624 6500 6500
+W 44 6 8194 15 40 BEZIER "Transitions" | 146436,112921 157397,112582 178653,111583 184472,109549\
+                                         190292,107515 191648,100057 191987,92429 192326,84802\
+                                         192326,61750 188540,53162 184755,44574 169613,33274\
+                                         159556,30336 149499,27398 125714,27614 113171,27388
+A 45 44 16 TEXT "Actions" | 155714,31240 1 0 0 "RXTimeOut <= 1'b1;"
+H 46 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 50 46 0 Builtin Exit | 180308,72140
+I 49 46 0 Builtin Entry | 47660,248640
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+W 59 46 0 49 54 BEZIER "Transitions" | 52122,248640 63735,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8194 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+C 133 131 0 TEXT "Conditions" | 102150,145171 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8195 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176807,72082 177204,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177624,25344 184036,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.v	(revision 264)
@@ -0,0 +1,265 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveSendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   [3:0]PID;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   sendPacketWEn;
+output  fifoReadEn;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+wire    [3:0]PID;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: slvSndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
+begin
+  NextState_slvSndPkt <= CurrState_slvSndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvSndPkt)  // synopsys parallel_case full_case
+    `START_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+    end
+    `SP_WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP1_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `SP1_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_SCTxPortReq <= 1'b0;
+    end
+    `SP_NOT_DATA:
+    begin
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_SEND_PID_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= PIDNotPID;
+        next_SCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SP_SEND_PID_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_NOT_DATA;
+      end
+    end
+    `SP_D0_D1_READ_FIFO:
+    begin
+      next_SCTxPortWEn <= 1'b1;
+      next_SCTxPortData <= fifoData;
+      next_SCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+    end
+    `SP_D0_D1_WAIT_READ_FIFO:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `SP_D0_D1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+      end
+    end
+    `SP_D0_D1_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_D0_D1_TERM_BYTE:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `SP_D0_D1_CLR_WEN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+    end
+    `SP_D0_D1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvSndPkt <= `START_SP1;
+  else
+    CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    SCTxPortData <= 8'h00;
+    SCTxPortCntl <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(revision 264)
@@ -0,0 +1,208 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbTxWireArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input   clk;
+input   prcTxByteCtrl;
+input   [1:0]prcTxByteData;
+input   prcTxByteFSRate;
+input   prcTxByteReq;
+input   prcTxByteWEn;
+input   rst;
+input   SIETxCtrl;
+input   [1:0]SIETxData;
+input   SIETxFSRate;
+input   SIETxReq;
+input   SIETxWEn;
+input   USBWireRdyIn;
+output  prcTxByteGnt;
+output  SIETxGnt;
+output  [1:0]TxBits;
+output  TxCtl;
+output  TxFSRate;
+output  USBWireRdyOut;
+output  USBWireWEn;
+
+wire    clk;
+wire    prcTxByteCtrl;
+wire    [1:0]prcTxByteData;
+wire    prcTxByteFSRate;
+reg     prcTxByteGnt, next_prcTxByteGnt;
+wire    prcTxByteReq;
+wire    prcTxByteWEn;
+wire    rst;
+wire    SIETxCtrl;
+wire    [1:0]SIETxData;
+wire    SIETxFSRate;
+reg     SIETxGnt, next_SIETxGnt;
+wire    SIETxReq;
+wire    SIETxWEn;
+reg     [1:0]TxBits, next_TxBits;
+reg     TxCtl, next_TxCtl;
+reg     TxFSRate, next_TxFSRate;
+wire    USBWireRdyIn;
+reg     USBWireRdyOut, next_USBWireRdyOut;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
+SIETxFSRate or prcTxByteFSRate)
+begin
+if (muxSIENotPTXB  == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+TxFSRate <= SIETxFSRate;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+TxFSRate <= prcTxByteFSRate;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+  NextState_txWireArb <= CurrState_txWireArb;
+  // Set default values for outputs and signals
+  next_prcTxByteGnt <= prcTxByteGnt;
+  next_SIETxGnt <= SIETxGnt;
+  next_muxSIENotPTXB <= muxSIENotPTXB;
+  case (CurrState_txWireArb)  // synopsys parallel_case full_case
+    `START_TARB:
+    begin
+      NextState_txWireArb <= `TARB_WAIT_REQ;
+    end
+    `TARB_WAIT_REQ:
+    begin
+      if (prcTxByteReq == 1'b1)
+      begin
+        NextState_txWireArb <= `PTXB_ACT;
+        next_prcTxByteGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b0;
+      end
+      else if (SIETxReq == 1'b1)
+      begin
+        NextState_txWireArb <= `SIE_TX_ACT;
+        next_SIETxGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b1;
+      end
+    end
+    `PTXB_ACT:
+    begin
+      if (prcTxByteReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_prcTxByteGnt <= 1'b0;
+      end
+    end
+    `SIE_TX_ACT:
+    begin
+      if (SIETxReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_SIETxGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_txWireArb <= `START_TARB;
+  else
+    CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    prcTxByteGnt <= 1'b0;
+    SIETxGnt <= 1'b0;
+    muxSIENotPTXB <= 1'b0;
+  end
+  else 
+  begin
+    prcTxByteGnt <= next_prcTxByteGnt;
+    SIETxGnt <= next_SIETxGnt;
+    muxSIENotPTXB <= next_muxSIENotPTXB;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/fifoMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/fifoMux.v	(revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMux (
+  currEndP,
+  //TxFifo
+  TxFifoREn,
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoData,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEmpty,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  //RxFifo
+  RxFifoWEn,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoFull,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+  //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+  //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+  TxFifoREn or
+  RxFifoWEn or
+  TxFifoEP0Data or
+  TxFifoEP1Data or
+  TxFifoEP2Data or
+  TxFifoEP3Data or
+  TxFifoEP0Empty or
+  TxFifoEP1Empty or
+  TxFifoEP2Empty or
+  TxFifoEP3Empty or
+  RxFifoEP0Full or
+  RxFifoEP1Full or
+  RxFifoEP2Full or
+  RxFifoEP3Full)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      TxFifoEP0REn <= TxFifoREn;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP0Data;
+      TxFifoEmpty <= TxFifoEP0Empty;
+      RxFifoEP0WEn <= RxFifoWEn;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP0Full;
+    end
+    2'b01: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= TxFifoREn;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP1Data;
+      TxFifoEmpty <= TxFifoEP1Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= RxFifoWEn;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP1Full;
+    end
+    2'b10: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= TxFifoREn;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP2Data;
+      TxFifoEmpty <= TxFifoEP2Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= RxFifoWEn;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP2Full;
+    end
+    2'b11: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= TxFifoREn;
+      TxFifoData <= TxFifoEP3Data;
+      TxFifoEmpty <= TxFifoEP3Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= RxFifoWEn;
+      RxFifoFull <= RxFifoEP3Full;
+    end
+  endcase  
+end      
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.v	(revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveDirectControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+  NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+  // Set default values for outputs and signals
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvDrctCntl)  // synopsys parallel_case full_case
+    `START_SDC:
+    begin
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+        next_SCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= {6'b000000, directControlLineState};
+        next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      next_SCTxPortReq <= 1'b0;
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvDrctCntl <= `START_SDC;
+  else
+    CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SCTxPortCntl <= 8'h00;
+    SCTxPortData <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.asf	(revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveSendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
+INSTHEADER 1
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+END
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+END
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+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: slaveSendPacket"
+I 12 6 0 Builtin Reset | 74872,202290
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+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
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+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
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+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
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+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
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+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
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+                                      55734,158585 71438,158887 78535,158887 85632,158887\
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+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 127 65 0 Builtin Exit | 176933,37229
+I 126 65 0 Builtin Entry | 68162,237252
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1;	 \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
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+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
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+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
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+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
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+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
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+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
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+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
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+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
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+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+END

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/usbSlaveControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/usbSlaveControl.v	(revision 264)
@@ -0,0 +1,507 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSlaveControl(
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  //getPacket
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut, RxFifoData,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //SCTxPortArbiter
+  SCTxPortEn, SCTxPortRdy,
+  SCTxPortData, SCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFRxedIntOut, 
+  resetEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  NAKSentIntOut,
+  slaveControlSelect,
+  //fifoMux
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [4:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut; 
+output resetEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut; 
+wire resetEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed; 
+wire CRCError; 
+wire RXOverflow; 
+wire RXTimeOut; 
+wire bitStuffError; 
+wire dataSequence; 
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [4:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire endPointReadyFromSlaveCtrlrToGetPkt;
+
+USBSlaveControlBI u_USBSlaveControlBI
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .SOFRxedIntOut(SOFRxedIntOut), 
+  .resetEventIntOut(resetEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .NAKSentIntOut(NAKSentIntOut),
+  .endP0TransTypeReg(endP0TransTypeReg), 
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg), 
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg), 
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg), 
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .EP0StatusReg(endP0StatusReg),
+  .EP1StatusReg(endP1StatusReg),
+  .EP2StatusReg(endP2StatusReg),
+  .EP3StatusReg(endP3StatusReg),
+  .SCAddrReg(USBTgtAddress), 
+  .frameNum(frameNum),
+  .connectStateIn(connectStateOut),
+  .SOFRxedIn(SOFRxed), 
+  .resetEventIn(resetEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .NAKSentIn(NAKSent),
+  .slaveControlSelect(slaveControlSelect),
+  .clrEP0Ready(clrEP0Rdy), 
+  .clrEP1Ready(clrEP1Rdy), 
+  .clrEP2Ready(clrEP2Rdy), 
+  .clrEP3Ready(clrEP3Rdy),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .SCGlobalEn(SCGlobalEn)
+  );
+
+slavecontroller u_slavecontroller
+  (.CRCError(CRCError), 
+  .NAKSent(NAKSent), 
+  .RxByte(RxData), 
+  .RxDataWEn(RxDataValid), 
+  .RxOverflow(RXOverflow), 
+  .RxStatus(RxByteStatus), 
+  .RxTimeOut(RXTimeOut), 
+  .SCGlobalEn(SCGlobalEn), 
+  .SOFRxed(SOFRxed), 
+  .USBEndPControlReg(endPControlReg), 
+  .USBEndPNakTransTypeReg(transTypeNAK), 
+  .USBEndPTransTypeReg(transType), 
+  .USBEndP(currEndP), 
+  .USBTgtAddress(USBTgtAddress),
+  .bitStuffError(bitStuffError), 
+  .clk(usbClk), 
+  .clrEPRdy(clrEPRdy), 
+  .endPMuxErrorsWEn(endPMuxErrorsWEn), 
+  .frameNum(frameNum), 
+  .getPacketREn(getPacketREn), 
+  .getPacketRdy(getPacketRdy), 
+  .rst(rstSyncToUsbClk), 
+  .sendPacketPID(slaveControllerPIDOut), 
+  .sendPacketRdy(slaveControllerReadyIn), 
+  .sendPacketWEn(slaveControllerWEnOut), 
+  .stallSent(stallSent), 
+  .transDone(transDone),
+  .endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
+    );
+
+
+endpMux u_endpMux (
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .currEndP(currEndP),
+  .NAKSent(NAKSent),
+  .stallSent(stallSent),
+  .CRCError(CRCError),
+  .bitStuffError(bitStuffError),
+  .RxOverflow(RXOverflow),
+  .RxTimeOut(RXTimeOut),
+  .dataSequence(dataSequence),
+  .ACKRxed(ACKRxed),
+  .transType(transType),
+  .transTypeNAK(transTypeNAK),
+  .endPControlReg(endPControlReg),
+  .clrEPRdy(clrEPRdy),
+  .endPMuxErrorsWEn(endPMuxErrorsWEn),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .endP0StatusReg(endP0StatusReg),
+  .endP1StatusReg(endP1StatusReg),
+  .endP2StatusReg(endP2StatusReg),
+  .endP3StatusReg(endP3StatusReg),
+  .endP0TransTypeReg(endP0TransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg),
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .clrEP0Rdy(clrEP0Rdy),
+  .clrEP1Rdy(clrEP1Rdy),
+  .clrEP2Rdy(clrEP2Rdy),
+  .clrEP3Rdy(clrEP3Rdy)
+    );
+
+slaveSendPacket u_slaveSendPacket
+  (.PID(slaveControllerPIDOut), 
+  .SCTxPortCntl(sendPacketCntl),
+  .SCTxPortData(sendPacketData),
+  .SCTxPortGnt(sendPacketGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(sendPacketReq),
+  .SCTxPortWEn(sendPacketWEn),
+  .clk(usbClk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .rst(rstSyncToUsbClk),
+  .sendPacketRdy(slaveControllerReadyIn),
+  .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+  (.SCTxPortCntl(directCntlCntl),
+  .SCTxPortData(directCntlData),
+  .SCTxPortGnt(directCntlGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(directCntlReq),
+  .SCTxPortWEn(directCntlWEn),
+  .clk(usbClk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rstSyncToUsbClk) ); 
+
+SCTxPortArbiter u_SCTxPortArbiter
+  (.SCTxPortCntl(SCTxPortCtrl),
+  .SCTxPortData(SCTxPortData),
+  .SCTxPortRdyIn(SCTxPortRdy),
+  .SCTxPortRdyOut(SCTxPortArbRdyOut),
+  .SCTxPortWEnable(SCTxPortEn),
+  .clk(usbClk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+
+slaveGetPacket u_slaveGetPacket
+  (.ACKRxed(ACKRxed), 
+  .CRCError(CRCError), 
+  .RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .clk(usbClk),
+  .RXOverflow(RXOverflow), 
+  .RXTimeOut(RXTimeOut), 
+  .bitStuffError(bitStuffError), 
+  .dataSequence(dataSequence), 
+  .getPacketEn(getPacketREn),
+  .rst(rstSyncToUsbClk),
+  .endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
+  ); 
+
+slaveRxStatusMonitor  u_slaveRxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .resetEventOut(resetEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk)  );    
+  
+fifoMux u_fifoMux (
+  .currEndP(currEndP),
+  //TxFifo
+  .TxFifoREn(TxFifoRE),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoData(TxFifoData),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEmpty(TxFifoEmpty),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  //RxFifo
+  .RxFifoWEn(RxFifoWE),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoFull(RxFifoFull),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+    );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/doc/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/doc/README.txt	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/doc/README.txt	(revision 264)
@@ -0,0 +1,37 @@
+USBHostSlave has been successfully compiled using Quartus 4.2
+For some reason I have not been able to use SOPC Builder 4.2 to build the usb SOPC component
+However, SOPC Builder 4.1 generates a usable SOPC component. This may be an error on my part, I need to
+investigate further.
+USBHostSlave has been tested in a SystemC simulation, and on a Altera Nios development kit Cyclone edition.
+
+
+Release notes:
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+//             control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect 
+//             time outs, added low speed EOP keep alive. The TX bit rate is now controlled by 
+//             SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+//             speed, and TX resume is always low speed.
+//             Fixed read clock recovery (readUSBWireData.v) issue which was resulting 
+//             in missing receive packets.
+//             Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+//             by adding kludged delay to softranmit. This needs to be fixed properly.
+//             This version has undergone limited testing
+//             with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+//             with uClinux, and is known to work with a full speed USB flash stick.
+//             Moving Opencores project status from Beta to done.
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+//               Modified RX and TX fifo status registers, and removed TX fifo data count
+//               register. Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
+//               Fixed slave mode bug which caused receive fifo to
+//               be filled with incoming data when the slave was
+//               responding with a NAK, and the data should have been discarded.
+//             TODO: Test isochronous mode, and low speed mode using uClinux driver
+//                   Add frame period adjustment capability
+//                   Add compilation flags for slave only and host only versions
+//                   Create data bus width options beyond 8-bit              
+
+ 
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/doc/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifo.v	(revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo read access via bus interface, fifo write access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module RxFifo(
+  busClk,
+  usbClk,
+  rstSyncToBusClk, 
+  rstSyncToUsbClk, 
+  fifoWEn, 
+  fifoFull,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataIn  );
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input busClk; 
+input usbClk; 
+input rstSyncToBusClk; 
+input rstSyncToUsbClk; 
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire busClk; 
+wire usbClk; 
+wire rstSyncToBusClk; 
+wire rstSyncToUsbClk; 
+wire fifoWEn; 
+wire fifoFull;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmptySyncToBusClk;
+wire forceEmptySyncToUsbClk;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;   //not used
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .wrClk(usbClk), 
+  .rdClk(busClk), 
+  .rstSyncToWrClk(rstSyncToUsbClk), 
+  .rstSyncToRdClk(rstSyncToBusClk), 
+  .dataIn(fifoDataIn), 
+  .dataOut(dataFromFifoToBus), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmptySyncToWrClk(forceEmptySyncToUsbClk), 
+  .forceEmptySyncToRdClk(forceEmptySyncToBusClk), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+RxfifoBI u_RxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .fifoSelect(busFifoSelect),
+  .fifoDataIn(dataFromFifoToBus),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoREn(fifoREn),
+  .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+  .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/dpMem_dc.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/dpMem_dc.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/dpMem_dc.v	(revision 264)
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// dpMem_dc.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Synchronous dual port memory with dual clocks
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module dpMem_dc(  addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input wrClk;
+input rdClk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire wrClk;
+wire rdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge rdClk) begin
+  dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge wrClk) begin
+  if (writeEn == 1'b1)
+    buffer[addrIn] <= dataIn;
+end                  
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/dpMem_dc.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// directControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
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+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1"
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
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+                                       47285,153175 50048,167625 56316,171290 62585,174956\
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+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
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+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.asf	(revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hctxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+                                      186275,384997 193806,383684 201338,382371 213515,373400\
+                                      220004,369229
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n  `SOF_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= SOFCntlWEn;\n    HCTxPortData <= SOFCntlData;\n    HCTxPortCntl <= SOFCntlCntl;\n  end\n  `DIRECT_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= directCntlWEn;\n    HCTxPortData <= directCntlData;\n    HCTxPortCntl <= directCntlCntl;\n  end\n  `SEND_PACKET_MUX :\n  begin  \n    HCTxPortWEnable <= sendPacketWEn;\n    HCTxPortData <= sendPacketData;\n    HCTxPortCntl <= sendPacketCntl;\n  end\n  default :\n  begin  \n    HCTxPortWEnable <= 1'b0;\n    HCTxPortData <= 8'h00;\n    HCTxPortCntl <= 8'h00;\n  end\nendcase	\nend"
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+I 89 0 130 Builtin Signal | 141050,528812 "" ""
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286404,388600 275724,388298\
+                                      265045,387996 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_01_00/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifoBI.v	(revision 264)
@@ -0,0 +1,148 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+  address, 
+  writeEn, 
+  strobe_i,
+  busClk, 
+  usbClk, 
+  rstSyncToBusClk, 
+  fifoSelect,
+  fifoDataIn,
+  busDataIn, 
+  busDataOut,
+  fifoREn,
+  forceEmptySyncToUsbClk,
+  forceEmptySyncToBusClk,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoREn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoREn;
+reg forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg [5:0] forceEmptyShift;
+reg forceEmpty;
+reg forceEmptySyncToUsbClkFirst;
+
+//sync write
+always @(posedge busClk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+    address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+//generate 'forceEmptySyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) 
+    forceEmptyShift <= 6'b000000;
+  else begin
+    if (forceEmpty == 1'b1)
+      forceEmptyShift <= 6'b111111;
+    else
+      forceEmptyShift <= {1'b0, forceEmptyShift[5:1]};
+  end
+end
+assign forceEmptySyncToBusClk = forceEmptyShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+    forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk;
+    forceEmptySyncToUsbClk <= forceEmptySyncToUsbClkFirst;
+end
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo)
+begin
+  case (address)
+      `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00; 
+  endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b0 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoREn <= 1'b1;
+  else
+    fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/fifoRTL.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/fifoRTL.v	(revision 264)
@@ -0,0 +1,164 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoRTL.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized dual clock domain fifo. 
+////  fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn, 
+  dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty,
+  forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+
+// Two clock domains within this module
+// These ports are within 'wrClk' domain
+input wrClk;
+input rstSyncToWrClk;
+input [FIFO_WIDTH-1:0] dataIn;
+input fifoWEn;
+input forceEmptySyncToWrClk;
+output fifoFull;
+
+// These ports are within 'rdClk' domain
+input rdClk;
+input rstSyncToRdClk;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoREn;
+input forceEmptySyncToRdClk;
+output fifoEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire wrClk;
+wire rdClk;
+wire rstSyncToWrClk;
+wire rstSyncToRdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg  [15:0]numElementsInFifo;
+
+
+// local registers
+reg  [ADDR_WIDTH:0]bufferInIndex; 
+reg  [ADDR_WIDTH:0]bufferInIndexSyncToRdClk;
+reg  [ADDR_WIDTH:0]bufferOutIndex;
+reg  [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk;
+reg  [ADDR_WIDTH-1:0]bufferInIndexToMem;
+reg  [ADDR_WIDTH-1:0]bufferOutIndexToMem;
+reg  [ADDR_WIDTH:0]bufferCnt;
+reg  fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge wrClk)
+begin
+  bufferOutIndexSyncToWrClk <= bufferOutIndex;
+  if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1)
+  begin
+    fifoFull <= 1'b0;
+    bufferInIndex <= 0;
+  end
+    else
+    begin
+      if (fifoWEn == 1'b1) begin
+        bufferInIndex <= bufferInIndex + 1'b1;
+      end 
+      if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
+          (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
+        fifoFull <= 1'b1;
+      else
+        fifoFull <= 1'b0;
+    end
+end
+
+always @(bufferInIndexSyncToRdClk or bufferOutIndex) 
+  bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
+
+always @(posedge rdClk)
+begin
+  numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes
+  bufferInIndexSyncToRdClk <= bufferInIndex;
+  if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1)
+  begin
+    fifoEmpty <= 1'b1;
+    bufferOutIndex <= 0;
+    fifoREnDelayed <= 1'b0;
+  end
+    else
+    begin
+      fifoREnDelayed <= fifoREn;
+      if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        dataOut <= dataFromMem;
+        bufferOutIndex <= bufferOutIndex + 1'b1;
+      end
+      if (bufferInIndexSyncToRdClk == bufferOutIndex) 
+        fifoEmpty <= 1'b1;
+      else
+        fifoEmpty <= 1'b0;
+    end
+end
+
+
+always @(bufferInIndex or bufferOutIndex) begin
+  bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
+  bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
+end
+
+dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_dpMem_dc (
+  .addrIn(bufferInIndexToMem),
+  .addrOut(bufferOutIndexToMem),
+  .wrClk(wrClk),
+  .rdClk(rdClk),
+  .dataIn(dataIn),
+  .writeEn(fifoWEn),
+  .readEn(fifoREn),
+  .dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.v	(revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// directControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (clk, directControlEn, directControlLineState, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_drctCntl, NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: drctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or HCTxPortGnt or HCTxPortRdy or directControlLineState or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_drctCntl)
+begin
+  NextState_drctCntl <= CurrState_drctCntl;
+  // Set default values for outputs and signals
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_drctCntl)  // synopsys parallel_case full_case
+    `START_DC:
+    begin
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_drctCntl <= `CHK_DRCT_CNTL;
+        next_HCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {6'b000000, directControlLineState};
+        next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_HCTxPortReq <= 1'b0;
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_drctCntl <= `IDLE_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_drctCntl <= `START_DC;
+  else
+    CurrState_drctCntl <= NextState_drctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/rxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/rxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// rxStatusMonitor.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      connectionEventOut <= 1'b1;
+    else
+      connectionEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.v	(revision 264)
@@ -0,0 +1,177 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketarbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (clk, HC_PID, HC_SP_WEn, HCTxGnt, HCTxReq, rst, sendPacketPID, sendPacketWEnable, SOF_SP_WEn, SOFTxGnt, SOFTxReq);
+input   clk;
+input   [3:0]HC_PID;
+input   HC_SP_WEn;
+input   HCTxReq;
+input   rst;
+input   SOF_SP_WEn;
+input   SOFTxReq;
+output  HCTxGnt;
+output  [3:0]sendPacketPID;
+output  sendPacketWEnable;
+output  SOFTxGnt;
+
+wire    clk;
+wire    [3:0]HC_PID;
+wire    HC_SP_WEn;
+reg     HCTxGnt, next_HCTxGnt;
+wire    HCTxReq;
+wire    rst;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+reg     sendPacketWEnable, next_sendPacketWEnable;
+wire    SOF_SP_WEn;
+reg     SOFTxGnt, next_SOFTxGnt;
+wire    SOFTxReq;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_sendPktArb, NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+if (muxSOFNotHC  == 1'b1)
+begin
+sendPacketWEnable <= SOF_SP_WEn;
+sendPacketPID <= `SOF;
+end
+else
+begin
+sendPacketWEnable <= HC_SP_WEn;
+sendPacketPID <= HC_PID;
+end
+end
+
+
+// Machine: sendPktArb
+
+// NextState logic (combinatorial)
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin
+  NextState_sendPktArb <= CurrState_sendPktArb;
+  // Set default values for outputs and signals
+  next_HCTxGnt <= HCTxGnt;
+  next_SOFTxGnt <= SOFTxGnt;
+  next_muxSOFNotHC <= muxSOFNotHC;
+  case (CurrState_sendPktArb)  // synopsys parallel_case full_case
+    `HC_ACT:
+    begin
+      if (HCTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_HCTxGnt <= 1'b0;
+      end
+    end
+    `SOF_ACT:
+    begin
+      if (SOFTxReq == 1'b0)
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_SOFTxGnt <= 1'b0;
+      end
+    end
+    `SARB_WAIT_REQ:
+    begin
+      if (SOFTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `SOF_ACT;
+        next_SOFTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b1;
+      end
+      else if (HCTxReq == 1'b1)
+      begin
+        NextState_sendPktArb <= `HC_ACT;
+        next_HCTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_sendPktArb <= `SARB_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktArb <= `START_SARB;
+  else
+    CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    HCTxGnt <= 1'b0;
+    SOFTxGnt <= 1'b0;
+    muxSOFNotHC <= 1'b0;
+  end
+  else 
+  begin
+    HCTxGnt <= next_HCTxGnt;
+    SOFTxGnt <= next_SOFTxGnt;
+    muxSOFNotHC <= next_muxSOFNotHC;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.v	(revision 264)
@@ -0,0 +1,178 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sofcontroller
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (clk, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, rst, SOFEnable, SOFTimer, SOFTimerClr);
+input   clk;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   rst;
+input   SOFEnable;
+input   SOFTimerClr;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [15:0]SOFTimer;
+
+wire    clk;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    rst;
+wire    SOFEnable;
+reg     [15:0]SOFTimer, next_SOFTimer;
+wire    SOFTimerClr;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0]CurrState_sofCntl, NextState_sofCntl;
+
+
+// Machine: sofCntl
+
+// NextState logic (combinatorial)
+always @ (SOFTimerClr or SOFEnable or HCTxPortRdy or SOFTimer or HCTxPortGnt or HCTxPortCntl or HCTxPortData or HCTxPortWEn or HCTxPortReq or CurrState_sofCntl)
+begin
+  NextState_sofCntl <= CurrState_sofCntl;
+  // Set default values for outputs and signals
+  next_SOFTimer <= SOFTimer;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  case (CurrState_sofCntl)  // synopsys parallel_case full_case
+    `START_SC:
+    begin
+      NextState_sofCntl <= `WAIT_SOF_EN;
+    end
+    `WAIT_SOF_EN:
+    begin
+      if (SOFEnable == 1'b1)
+      begin
+        NextState_sofCntl <= `SC_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `WAIT_SEND_RESUME:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sofCntl <= `CLR_WEN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_RESUME_START;
+      end
+    end
+    `INC_TIMER:
+    begin
+      next_HCTxPortReq <= 1'b0;
+      if (SOFTimerClr == 1'b1)
+      next_SOFTimer <= 16'h0000;
+      else
+      next_SOFTimer <= SOFTimer + 1'b1;
+      if (SOFEnable == 1'b0)
+      begin
+        NextState_sofCntl <= `WAIT_SOF_EN;
+        next_SOFTimer <= 16'h0000;
+      end
+    end
+    `SC_WAIT_GNT:
+    begin
+      if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sofCntl <= `WAIT_SEND_RESUME;
+      end
+    end
+    `CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sofCntl <= `INC_TIMER;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sofCntl <= `START_SC;
+  else
+    CurrState_sofCntl <= NextState_sofCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFTimer <= 16'h0000;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SOFTimer <= next_SOFTimer;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/usbHostControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/usbHostControl.v	(revision 264)
@@ -0,0 +1,397 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostControl(
+  busClk, rstSyncToBusClk,
+  usbClk, rstSyncToUsbClk,
+  //sendPacket
+  TxFifoRE, TxFifoData, TxFifoEmpty,
+  //getPacket
+  RxFifoWE, RxFifoData, RxFifoFull,
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut, SIERxTimeOutEn,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //HCTxPortArbiter
+  HCTxPortEn, HCTxPortRdy,
+  HCTxPortData, HCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFSentIntOut, 
+  connEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  hostControlSelect
+    );
+
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output SIERxTimeOutEn;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [3:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut; 
+output connEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+input hostControlSelect;
+
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire SIERxTimeOutEn;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut; 
+wire connEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire isoEn;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI 
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .SOFSentIntOut(SOFSentIntOut), 
+  .connEventIntOut(connEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .TxTransTypeReg(transType), 
+  .TxSOFEnableReg(SOFEnable),
+  .TxAddrReg(TxAddr), 
+  .TxEndPReg(TxEndP), 
+  .frameNumIn(frameNum), 
+  .RxPktStatusIn(RxPktStatus), 
+  .RxPIDIn(RxPID),
+  .connectStateIn(connectStateOut),
+  .SOFSentIn(SOFSent), 
+  .connEventIn(connectionEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .hostControlSelect(hostControlSelect),
+  .clrTransReq(clrTxReq),
+  .preambleEn(preAmbleEnable),
+  .SOFSync(SOFSyncEn),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .transReq(transReq),
+  .isoEn(isoEn),
+  .SOFTimer(SOFTimer)
+  );
+
+
+hostcontroller u_hostController
+  (.RXStatus(RxPktStatus), 
+  .clearTXReq(clrTxReq),
+  .clk(usbClk),
+  .getPacketREn(getPacketREn),
+  .getPacketRdy(getPacketRdy),
+  .rst(rstSyncToUsbClk),
+  .sendPacketArbiterGnt(HCTxGnt),
+  .sendPacketArbiterReq(HCTxReq),
+  .sendPacketPID(HC_PID),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(HC_SP_WEn),
+  .transDone(transDone),
+  .transReq(transReq),
+  .transType(transType),
+  .isoEn(isoEn) );
+
+SOFController u_SOFController
+  (.HCTxPortCntl(SOFCntlCntl),
+  .HCTxPortData(SOFCntlData),
+  .HCTxPortGnt(SOFCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(SOFCntlReq),
+  .HCTxPortWEn(SOFCntlWEn),
+  .SOFEnable(SOFEnable),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk) ); 
+
+SOFTransmit u_SOFTransmit
+  (.SOFEnable(SOFEnable),
+  .SOFSent(SOFSent),
+  .SOFSyncEn(SOFSyncEn),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk),
+  .sendPacketArbiterGnt(SOFTxGnt),
+  .sendPacketArbiterReq(SOFTxReq),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(SOF_SP_WEn) );  
+
+
+sendPacketArbiter u_sendPacketArbiter
+  (.HCTxGnt(HCTxGnt),
+  .HCTxReq(HCTxReq),
+  .HC_PID(HC_PID),
+  .HC_SP_WEn(HC_SP_WEn),
+  .SOFTxGnt(SOFTxGnt),
+  .SOFTxReq(SOFTxReq),
+  .SOF_SP_WEn(SOF_SP_WEn),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk),
+  .sendPacketPID(sendPacketCPPIDIn),
+  .sendPacketWEnable(sendPacketCPWEnIn) );    
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+  (.sendPacketCPPID(sendPacketCPPIDIn),
+  .clk(usbClk),
+  .preAmbleEnable(preAmbleEnable),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCPReady(sendPacketCPReadyOut),
+  .sendPacketCPWEn(sendPacketCPWEnIn),
+  .sendPacketPID(sendPacketCPPIDOut),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+  (.HCTxPortCntl(sendPacketCntl),
+  .HCTxPortData(sendPacketData),
+  .HCTxPortGnt(sendPacketGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(sendPacketReq),
+  .HCTxPortWEn(sendPacketWEn),
+  .PID(sendPacketCPPIDOut),
+  .TxAddr(TxAddr),
+  .TxEndP(TxEndP),
+  .clk(usbClk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .frameNum(frameNum),
+  .rst(rstSyncToUsbClk),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut),
+  .fullSpeedPolarity(fullSpeedPol) );
+  
+directControl u_directControl
+  (.HCTxPortCntl(directCntlCntl),
+  .HCTxPortData(directCntlData),
+  .HCTxPortGnt(directCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(directCntlReq),
+  .HCTxPortWEn(directCntlWEn),
+  .clk(usbClk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rstSyncToUsbClk) ); 
+
+HCTxPortArbiter u_HCTxPortArbiter
+  (.HCTxPortCntl(HCTxPortCtrl),
+  .HCTxPortData(HCTxPortData),
+  .HCTxPortWEnable(HCTxPortEn),
+  .SOFCntlCntl(SOFCntlCntl),
+  .SOFCntlData(SOFCntlData),
+  .SOFCntlGnt(SOFCntlGnt),
+  .SOFCntlReq(SOFCntlReq),
+  .SOFCntlWEn(SOFCntlWEn),
+  .clk(usbClk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+getPacket u_getPacket
+  (.RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXPktStatus(RxPktStatus),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .SIERxTimeOutEn(SIERxTimeOutEn),
+  .clk(usbClk),
+  .getPacketEn(getPacketREn),
+  .rst(rstSyncToUsbClk) ); 
+
+rxStatusMonitor  u_rxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .connectionEventOut(connectionEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostControl_h.v	(revision 264)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v                                          
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HOST_SOF_TIMER_MSB_REG 4'hf
+
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+`define ISO_ENABLE_BIT 3
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+ 
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants 
+//`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval   
+//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer 
+`define SOF_TX_TIME 16'hbb7d     //Correct SOF interval for 48MHz clock.
+//`define SOF_TX_MARGIN 2 
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+       
+//Host RXStatusRegIndices 
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined 

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/wishBoneBus_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/wishBoneBus_h.v	(revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+ 
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.asf	(revision 264)
@@ -0,0 +1,315 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=258
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processrxbit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
+W 35 41 0 40 37 BEZIER "Transitions" | 111741,134422 116780,127404 121695,118778 126735,111760
+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
+I 37 41 0 Builtin Exit | 129540,111760
+I 38 41 0 Builtin Entry | 86360,167640
+L 39 40 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK\n/9/"
+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 119820,36808 1 0 0 "RES_END"
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 51 6 0 213 16 BEZIER "Transitions" | 42388,154240 42522,148478 41966,137442 42502,133556\
+                                       43038,129670 44914,125650 53423,124511 61932,123372\
+                                       93489,123426 109569,123158
+W 52 6 0 213 24 BEZIER "Transitions" | 42699,154238 43235,140704 42636,114126 43641,106354\
+                                       44646,98582 47594,94562 55902,93624 64210,92686\
+                                       94494,92954 102132,93021 109770,93088 110325,93078\
+                                       110459,93078
+W 53 6 0 213 33 BEZIER "Transitions" | 42645,154234 43047,131722 42770,88800 43976,77142\
+                                       45182,65484 49202,63876 57711,63474 66220,63072\
+                                       96236,63072 103807,63072 111378,63072 111758,63165\
+                                       111892,63165
+W 54 6 0 213 42 BEZIER "Transitions" | 42671,154227 43609,125551 43842,70308 45115,54764\
+                                       46388,39220 49604,34396 58247,33391 66890,32386\
+                                       97657,35973 113335,36375
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+                                       188238,99472 188778,113512 186145,122422 183513,131332\
+                                       167904,143587 159264,149864 150624,156142 133542,158851\
+                                       125779,159931 118017,161011 123617,159646 119837,160051
+W 68 6 0 16 219 BEZIER "Transitions" | 121312,119265 131167,111435 152206,96104 162061,88274
+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 114133,117894 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h0;                          \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+W 76 17 4096 241 18 BEZIER "Transitions" | 152390,172884 131374,171355 101683,127861 94565,116677
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
+W 82 17 8194 75 21 BEZIER "Transitions" | 74719,170800 72243,162260 51221,151750 45574,140719\
+                                          39928,129688 39788,80170 47763,75675 55738,71180\
+                                          102436,61038 148189,26024
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 95824,146799 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+                                            151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+                                        176540,156388 181096,131196 181431,113977 181766,96758\
+                                        182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit)                           //if current bit is a JBit, then\n  RXBitStMachCurrState <= `IDLE_BIT_ST;       //next state is idle\nelse                                          //else\nbegin\n  RXBitStMachCurrState <= `WAIT_RESUME_ST;    //check for resume\n  resumeWaitCnt <= 5'h0;                          \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte;       \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit)  //line must leave KBit state for the end of resume\nbegin\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\n  resumeDetected <= 1'b0;   //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit)  //can only be a resume if line remains in Kbit state\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n  resumeWaitCnt <= resumeWaitCnt + 1'b1; \n  //if we've waited long enough, then\n  if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)\n  begin	\n    RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n    resumeDetected <= 1'b1;  //report resume detected\n  end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+                                         107061,21822 137747,20482 148467,20415 159187,20348\
+                                         171381,21420 174463,22458 177545,23497 178090,26035\
+                                         178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+                                         145117,36964 157043,31068 161599,29627 166155,28187\
+                                         172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 5'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[4:0]"
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 25628,249822 1 0 0 "if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n  RXSameBitCount <= RXSameBitCount + 1'b1;  //inc 'RXSameBitCount'\n  if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error\n    bitStuffError <= 1'b1;                         //flag 'bitStuffError'\n  else                                          //else no bit stuffing error\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin\n      processRxBitRdy <= 1'b1;                   //early indication of ready\n	end\n    RXByte <= { 1'b1, RXByte[7:1]};              //RZ bit = 1 (ie no change in 'RxBits')\n  end\nend\nelse                                            //else current 'RxBits' are different from old 'RxBits'\nbegin\n  if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;	               //early indication of ready\n	end\n    RXByte <= {1'b0, RXByte[7:1]};             //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n  end\n   RXSameBitCount <= 4'h0;                      //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 151892,179359 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 151892,179359 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 135677,178559 145432,178646
+C 243 242 0 TEXT "Conditions" | 82407,188660 1 0 0 "(RxBits == KBit) && (RxWireActive == 1'b1)"
+C 244 76 0 TEXT "Conditions" | 137618,163943 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+I 257 0 2 Builtin InPort | 150840,260800 "" ""
+L 256 257 0 TEXT "Labels" | 156840,260800 1 0 0 "RxWireActive"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.asf	(revision 264)
@@ -0,0 +1,311 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1126
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processTxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 874
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 887
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 994
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 1025
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 1034
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 1103 1035 0 1084 1100 BEZIER "Transitions" | 50775,157143 50927,152127 51227,143877 51379,138861
+S 1100 1035 110592 ELLIPSE "States" | 52016,132400 6500 6500
+L 1099 1100 0 TEXT "State Labels" | 52016,132400 1 0 0 "W_RDY1\n/22/"
+W 1093 6 0 1034 874 BEZIER "Transitions" | 107126,38228 93109,49095 67454,69717 53517,80692
+C 1092 1091 0 TEXT "Conditions" | 145670,31298 1 0 0 "TxByteFullSpeedRate  == 1'b0"
+W 1091 6 1 1025 1034 BEZIER "Transitions" | 176852,45724 174332,42574 169925,36810 163940,34881\
+                                            157955,32952 139055,31533 132716,31415 126377,31297\
+                                            121929,32154 118701,32626
+A 1090 1084 4 TEXT "Actions" | 60764,178497 1 0 0 "USBWireWEn <= 1'b0;"
+C 1089 1087 0 TEXT "Conditions" | 68348,136414 1 0 0 "USBWireRdy == 1'b1"
+A 1088 1087 16 TEXT "Actions" | 81756,164067 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 12 6 0 Builtin Reset | 22016,204762
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 816 0 2 Builtin InPort | 123679,253114 "" ""
+L 817 818 0 TEXT "Labels" | 127572,248474 1 0 0 "processTxByteRdy"
+I 818 0 2 Builtin OutPort | 121572,248474 "" ""
+L 819 820 0 TEXT "Labels" | 129679,243601 1 0 0 "TxByteIn[7:0]"
+I 820 0 130 Builtin InPort | 123679,243601 "" ""
+L 821 822 0 TEXT "Labels" | 129679,239194 1 0 0 "TxByteCtrlIn[7:0]"
+I 822 0 130 Builtin InPort | 123679,239194 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+L 1094 1095 0 TEXT "State Labels" | 102676,41870 1 0 0 "FIN\n/21/"
+S 1095 1035 106496 ELLIPSE "States" | 102676,41870 6500 6500
+A 1096 1095 4 TEXT "Actions" | 110058,56736 1 0 0 "USBWireWEn <= 1'b0;"
+I 1097 1035 0 Builtin Exit | 133008,37611
+W 1098 1035 0 1095 1097 BEZIER "Transitions" | 108942,40143 114373,39761 124823,37993 130254,37611
+W 1119 895 0 942 1113 BEZIER "Transitions" | 81422,174858 96749,175660 126155,175178 141482,175980
+W 1118 895 0 948 1111 BEZIER "Transitions" | 78609,218255 90004,218415 111471,218138 122866,218298
+S 1117 895 135168 ELLIPSE "States" | 157607,86664 6500 6500
+L 1116 1117 0 TEXT "State Labels" | 157607,86664 1 0 0 "W_RDY4\n/28/"
+S 1115 895 131072 ELLIPSE "States" | 152471,133209 6500 6500
+L 1114 1115 0 TEXT "State Labels" | 152471,133209 1 0 0 "W_RDY3\n/27/"
+S 1113 895 126976 ELLIPSE "States" | 147977,176223 6500 6500
+L 1112 1113 0 TEXT "State Labels" | 147977,176223 1 0 0 "W_RDY2\n/26/"
+S 1111 895 122880 ELLIPSE "States" | 129359,218595 6500 6500
+L 1110 1111 0 TEXT "State Labels" | 129359,218595 1 0 0 "W_RDY1\n/25/"
+W 1109 1035 0 1068 1107 BEZIER "Transitions" | 127810,93623 140198,90963 162007,83161 174395,80501
+W 1108 1035 0 1046 1105 BEZIER "Transitions" | 125077,143006 136439,141182 157968,135884 169330,134060
+S 1107 1035 118784 ELLIPSE "States" | 180608,78592 6500 6500
+L 1106 1107 0 TEXT "State Labels" | 180608,78592 1 0 0 "W_RDY3\n/24/"
+S 1105 1035 114688 ELLIPSE "States" | 175744,133008 6500 6500
+L 1104 1105 0 TEXT "State Labels" | 175744,133008 1 0 0 "W_RDY2\n/23/"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 1125 0 2 Builtin OutPort | 17114,248843 "" ""
+L 1124 1125 0 TEXT "Labels" | 23114,248843 1 0 0 "USBWireFullSpeedRate"
+I 1123 0 2 Builtin Signal | 69653,217706 "" ""
+L 1122 1123 0 TEXT "Labels" | 72332,217706 1 0 0 "TxByteFullSpeedRate"
+W 1121 895 0 962 1117 BEZIER "Transitions" | 87535,83532 103906,84093 134787,85298 151158,85859
+W 1120 895 0 956 1115 BEZIER "Transitions" | 84631,133419 97918,132655 128828,133044 145972,133233
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48799,85161 6500 6500
+L 873 874 0 TEXT "State Labels" | 48799,85161 1 0 0 "SEND_BYTE"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+A 871 869 16 TEXT "Actions" | 38769,162443 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;\nTxByteFullSpeedRate <= TxByteFullSpeedRateIn;\nUSBWireFullSpeedRate <= TxByteFullSpeedRateIn;"
+C 870 869 0 TEXT "Conditions" | 45385,167359 1 0 0 "processTxByteWEn == 1'b1"
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+I 884 880 0 Builtin Exit | 178131,23271
+I 883 880 0 Builtin Entry | 38120,248040
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1)                      //If this bit is 1, then\n  TXOneCount <= TXOneCount + 1'b1;          //increment 'TXOneCount'\nelse                                        //else this is a zero bit\nbegin\n  TXOneCount <= 4'h0;                            //reset 'TXOneCount'\n  if (TXLineState == JBit) \n    TXLineState <= KBit; //toggle the line state\n  else \n    TXLineState <= JBit;\nend"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+                                         25630,50244 23766,53274 22950,67894 22135,82515\
+                                         20737,137969 21261,153813 21785,169657 25281,177579\
+                                         27028,179792 28775,182006 32271,182938 33727,182355\
+                                         35183,181773 37321,179186 38486,177555
+W 897 6 0 874 887 BEZIER "Transitions" | 48492,78681 48772,71498 48867,58679 49333,51573
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47452,100861 48245,91628
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h0;                                //reset 'TXOneCount'\nif (TXLineState == JBit) \n  TXLineState <= KBit;   //toggle the line state\nelse \n  TXLineState <= JBit;"
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == `MAX_CONSEC_SAME_BITS"
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+C 941 940 0 TEXT "Conditions" | 159104,107836 1 0 0 "USBWireGnt == 1'b1"
+W 940 6 0 936 1005 BEZIER "Transitions" | 152571,107755 158885,103151 166953,83129 172936,74254
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 4'h0;       \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+                                              40522,42856 31562,47464 29098,65320 26634,83176\
+                                              25738,149992 26858,168968 27978,187944 33354,197032\
+                                              36938,198888 40522,200744 49226,198568 51498,198152\
+                                              53770,197736 54409,198230 54473,198230
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+                                              113354,23912 154429,23527 174909,23271
+A 959 958 16 TEXT "Actions" | 127881,161233 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+W 958 895 0 1113 956 BEZIER "Transitions" | 148099,169766 148727,162473 88842,149177 77593,139316
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+A 947 944 16 TEXT "Actions" | 109865,203040 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 946 942 4 TEXT "Actions" | 92250,183175 1 0 0 "USBWireWEn <= 1'b0;"
+C 945 944 0 TEXT "Conditions" | 128791,211803 1 0 0 "USBWireRdy == 1'b1"
+W 944 895 0 1111 942 BEZIER "Transitions" | 129757,212112 130385,204819 80759,192930 74325,181785
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+                                           90132,26172 93257,24084 94765,23272
+I 974 895 0 Builtin Exit | 97904,23272
+C 973 970 0 TEXT "Conditions" | 155824,79891 1 0 0 "USBWireRdy == 1'b1"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+A 971 970 16 TEXT "Actions" | 138904,72921 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 970 895 0 1117 968 BEZIER "Transitions" | 157812,80182 158440,72889 82671,57884 83299,50591
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+C 967 964 0 TEXT "Conditions" | 151835,126496 1 0 0 "USBWireRdy == 1'b1"
+A 966 962 4 TEXT "Actions" | 90331,92695 1 0 0 "USBWireWEn <= 1'b0;"
+A 965 964 16 TEXT "Actions" | 130933,116536 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+W 964 895 0 1115 962 BEZIER "Transitions" | 152792,126730 153420,119437 79847,97645 80475,90352
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+C 961 958 0 TEXT "Conditions" | 146391,169184 1 0 0 "USBWireRdy == 1'b1"
+A 960 956 4 TEXT "Actions" | 86480,140378 1 0 0 "USBWireWEn <= 1'b0;"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+A 979 9 4 TEXT "Actions" | 127034,208396 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;\nUSBWireFullSpeedRate <= 1'b0;\nTxByteFullSpeedRate <= 1'b0;"
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+I 977 895 0 Builtin Entry | 34452,259216
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+                                              30972,218732 29812,212468 29638,189094 29464,165720\
+                                              29928,78488 31900,55230 33872,31972 41296,26172\
+                                              49358,24664 57420,23156 82353,23388 94765,23272
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+                                              41124,121640 36948,124424 36020,132602 35092,140780\
+                                              35556,170708 38166,179350 40776,187992 50140,192687\
+                                              55128,195007
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+                                              104561,139388 153745,139620 168013,138576 182281,137532\
+                                              190169,133124 192141,121582 194113,110040 194113,68280\
+                                              192025,55114 189937,41948 185529,28723 181353,23271
+L 1006 1005 0 TEXT "State Labels" | 178403,71114 1 0 0 "WAIT_RDY_WIRE\n/15/"
+S 1005 6 73728 ELLIPSE "States" | 178403,70739 6500 6500
+A 1001 1000 16 TEXT "Actions" | 97876,75175 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit;  \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 1000 6 2 1025 1011 BEZIER "Transitions" | 175446,48001 143324,42707 116663,67496 88157,75929
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 996 995 0 Builtin Entry | 86360,167640
+I 997 995 0 Builtin Exit | 129540,111760
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+I 1022 0 2 Builtin InPort | 123637,233935 "" ""
+L 1021 1022 0 TEXT "Labels" | 129637,233935 1 0 0 "TxByteFullSpeedRateIn"
+W 1020 6 0 1011 874 BEZIER "Transitions" | 75467,77142 69580,78790 60425,80424 54545,82123
+L 1013 1011 0 TEXT "State Labels" | 81933,77802 1 0 0 "WAIT_RDY_PKT\n/16/"
+A 1012 1011 4 TEXT "Actions" | 89664,97554 1 0 0 "USBWireWEn <= 1'b0;"
+S 1011 6 77824 ELLIPSE "States" | 81933,77802 6500 6500
+H 1035 1034 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 1034 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112501,34575 6500 6500
+L 1033 1034 0 TEXT "State Labels" | 112501,34575 1 0 0 "LS_START"
+C 1032 1031 0 TEXT "Conditions" | 160740,61840 1 0 0 "USBWireRdy == 1'b1"
+W 1031 6 0 1005 1025 BEZIER "Transitions" | 178252,64280 178492,60600 178502,55716 178742,52036
+W 1030 1027 0 1028 1029 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 1029 1027 0 Builtin Exit | 129540,111760
+I 1028 1027 0 Builtin Entry | 86360,167640
+L 1026 1025 0 TEXT "State Labels" | 178900,48560 1 0 0 "J2"
+S 1025 6 81940 ELLIPSE "Junction" | 178900,48560 3500 3500
+H 1027 1025 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 1047 1046 0 TEXT "State Labels" | 118913,145067 1 0 0 "SND_IDLE3\n/17/"
+S 1046 1035 90112 ELLIPSE "States" | 118913,145067 6500 6500
+L 1071 1068 0 TEXT "State Labels" | 121801,96100 1 0 0 "SND_J1\n/18/"
+A 1070 1066 16 TEXT "Actions" | 152238,115920 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 1069 1068 4 TEXT "Actions" | 140396,98815 1 0 0 "USBWireWEn <= 1'b0;"
+S 1068 1035 94208 ELLIPSE "States" | 121801,96100 6500 6500
+C 1067 1066 0 TEXT "Conditions" | 172627,126718 1 0 0 "USBWireRdy == 1'b1"
+W 1066 1035 0 1105 1068 BEZIER "Transitions" | 174692,126596 175320,119303 120603,109864 121231,102571
+A 1064 1060 16 TEXT "Actions" | 145913,63353 1 0 0 "//Drive the first JBit\nUSBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+C 1061 1060 0 TEXT "Conditions" | 146295,70754 1 0 0 "USBWireRdy == 1'b1"
+W 1060 1035 0 1107 1095 BEZIER "Transitions" | 176710,73393 172416,69158 96436,74541 101513,48264
+W 1087 1035 0 1100 1046 BEZIER "Transitions" | 56057,127311 71885,129746 98436,147110 112744,147113
+L 1085 1084 0 TEXT "State Labels" | 50985,163622 1 0 0 "SND_IDLE2\n/20/"
+S 1084 1035 102400 ELLIPSE "States" | 50985,163622 6500 6500
+C 1082 1080 0 TEXT "Conditions" | 60959,213403 1 0 0 "USBWireRdy == 1'b1"
+A 1081 1080 16 TEXT "Actions" | 52141,196692 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 1080 1035 0 1077 1084 BEZIER "Transitions" | 60047,214302 60675,207009 52849,177084 50437,170095
+W 1079 1035 0 1075 1077 BEZIER "Transitions" | 75208,269307 75836,262014 61041,234231 58933,227242
+L 1078 1077 0 TEXT "State Labels" | 59497,220774 1 0 0 "SND_IDLE1\n/19/"
+S 1077 1035 98304 ELLIPSE "States" | 59497,220774 6500 6500
+I 1075 1035 0 Builtin Entry | 75208,271435
+A 1073 1046 4 TEXT "Actions" | 137508,147782 1 0 0 "USBWireWEn <= 1'b0;"
+L 815 816 0 TEXT "Labels" | 129679,253114 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/USBHostControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/USBHostControlBI.v	(revision 264)
@@ -0,0 +1,380 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBHostControlBI.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbHostControl_h.v"
+ 
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+  TxTransTypeReg, TxSOFEnableReg,
+  TxAddrReg, TxEndPReg, frameNumIn, 
+  RxPktStatusIn, RxPIDIn,
+  connectStateIn,
+  SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+  hostControlSelect,
+  clrTransReq,
+  preambleEn,
+  SOFSync,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  transReq,
+  isoEn,
+  SOFTimer
+  );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output transReq;
+output isoEn;     //enable isochronous mode
+input [15:0] SOFTimer;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg transReq;
+reg isoEn;
+wire [15:0] SOFTimer;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [1:0] TxTransTypeRegSTB;
+reg TxSOFEnableRegSTB;
+reg [6:0] TxAddrRegSTB;
+reg [3:0] TxEndPRegSTB;
+reg preambleEnSTB;
+reg SOFSyncSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB; 
+reg fullSpeedRateSTB;
+reg transReqSTB;
+reg isoEnSTB;   
+reg [10:0] frameNumInSTB;
+reg [7:0] RxPktStatusInSTB;
+reg [3:0] RxPIDInSTB;
+reg [1:0] connectStateInSTB;
+reg SOFSentInSTB;
+reg connEventInSTB;
+reg resumeIntInSTB;
+reg transDoneInSTB;
+reg clrTransReqSTB;
+reg [15:0] SOFTimerSTB;
+
+  
+//sync write demux
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    isoEnSTB <= 1'b0;
+    preambleEnSTB <= 1'b0;
+    SOFSyncSTB <= 1'b0;
+    TxTransTypeRegSTB <= 2'b00;
+    TxLineControlReg <= 5'h00;
+    TxSOFEnableRegSTB <= 1'b0;
+    TxAddrRegSTB <= 7'h00;
+    TxEndPRegSTB <= 4'h0;
+    interruptMaskReg <= 4'h0;
+  end
+  else begin
+    clrSOFReq <= 1'b0;
+    clrConnEvtReq <= 1'b0;
+    clrResInReq <= 1'b0;
+    clrTransDoneReq <= 1'b0;
+    setTransReq <= 1'b0;
+    if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+    begin
+      case (address)
+        `TX_CONTROL_REG : begin
+          isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
+          preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
+          SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
+          setTransReq <= dataIn[`TRANS_REQ_BIT];
+        end
+        `TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
+        `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+        `TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
+        `TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
+        `TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
+        `INTERRUPT_STATUS_REG :  begin
+          clrSOFReq <= dataIn[`SOF_SENT_BIT];
+          clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
+          clrResInReq <= dataIn[`RESUME_INT_BIT];
+          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+        end
+        `INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[3:0];
+      endcase
+    end 
+  end
+end
+
+//interrupt control
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    SOFSentInt <= 1'b0;
+    connEventInt <= 1'b0;
+    resumeInt <= 1'b0;
+    transDoneInt <= 1'b0;
+  end
+  else begin
+    if (SOFSentInSTB == 1'b1)
+      SOFSentInt <= 1'b1;
+    else if (clrSOFReq == 1'b1)
+      SOFSentInt <= 1'b0;
+    
+    if (connEventInSTB == 1'b1)
+      connEventInt <= 1'b1;
+    else if (clrConnEvtReq == 1'b1)
+      connEventInt <= 1'b0;
+    
+    if (resumeIntInSTB == 1'b1)
+      resumeInt <= 1'b1;
+    else if (clrResInReq == 1'b1)
+      resumeInt <= 1'b0;  
+
+    if (transDoneInSTB == 1'b1)
+      transDoneInt <= 1'b1;
+    else if (clrTransDoneReq == 1'b1)
+      transDoneInt <= 1'b0;
+  end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end  
+  
+//transaction request set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'setTransReq' must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the transaction request is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'transReq' and sampling of related control signals.always @(posedge busClk)
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    transReqSTB <= 1'b0;
+  end
+  else begin
+    if (setTransReq == 1'b1)
+      transReqSTB <= 1'b1;
+    else if (clrTransReqSTB == 1'b1)
+      transReqSTB <= 1'b0;
+  end
+end  
+  
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+  TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+  LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+  fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+  
+// async read mux
+always @(address or
+  TxControlReg or TxTransTypeRegSTB or TxLineControlReg or TxSOFEnableRegSTB or
+  TxAddrRegSTB or TxEndPRegSTB or frameNumInSTB or 
+  SOFSentInt or connEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or RxPktStatusInSTB or RxPIDInSTB or connectStateInSTB or
+  preambleEnSTB or SOFSyncSTB or transReqSTB or isoEnSTB or SOFTimer)
+begin
+  case (address)
+      `TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
+      `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
+      `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+      `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
+      `TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
+      `TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
+      `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
+      `FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
+      `INTERRUPT_STATUS_REG :  dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+      `INTERRUPT_MASK_REG  : dataOut <= {4'h0, interruptMaskReg};
+      `RX_STATUS_REG  : dataOut <= RxPktStatusInSTB;
+      `RX_PID_REG  : dataOut <= {4'b0000, RxPIDInSTB};
+      `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
+      `HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimer[15:8];
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+//re-sync from busClk to usbClk. 
+always @(posedge usbClk) begin
+  if (rstSyncToUsbClk == 1'b1) begin
+    isoEn <= 1'b0;
+    preambleEn <= 1'b0;
+    SOFSync <= 1'b0;
+    TxTransTypeReg <= 2'b00;
+    TxSOFEnableReg <= 1'b0;
+    TxAddrReg <= 7'h00;
+    TxEndPReg <= 4'h0;
+    TxLineState <= 2'b00;
+    LineDirectControlEn <= 1'b0;
+    fullSpeedPol <= 1'b0; 
+    fullSpeedRate <= 1'b0;
+    transReq <= 1'b0;
+  end
+  else begin
+    isoEn <= isoEnSTB;     
+    preambleEn <= preambleEnSTB;
+    SOFSync <= SOFSyncSTB;
+    TxTransTypeReg <= TxTransTypeRegSTB;
+    TxSOFEnableReg <= TxSOFEnableRegSTB;
+    TxAddrReg <= TxAddrRegSTB;
+    TxEndPReg <= TxEndPRegSTB;
+    TxLineState <= TxLineStateSTB;
+    LineDirectControlEn <= LineDirectControlEnSTB;
+    fullSpeedPol <= fullSpeedPolSTB; 
+    fullSpeedRate <= fullSpeedRateSTB;
+    transReq <= transReqSTB;
+  end
+end
+
+//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted 
+//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
+always @(posedge busClk) begin
+  frameNumInSTB <= frameNumIn;
+  RxPktStatusInSTB <= RxPktStatusIn;
+  RxPIDInSTB <= RxPIDIn;
+  connectStateInSTB <= connectStateIn;
+  SOFSentInSTB <= SOFSentIn;
+  connEventInSTB <= connEventIn;
+  resumeIntInSTB <= resumeIntIn;
+  transDoneInSTB <= transDoneIn;
+  clrTransReqSTB <= clrTransReq;
+  SOFTimerSTB <= SOFTimer;
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.v	(revision 264)
@@ -0,0 +1,404 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// getpacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (clk, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RxPID, RXPktStatus, RXStreamStatusIn, SIERxTimeOut, SIERxTimeOutEn);
+input   clk;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  [7:0]RXPktStatus;
+output  SIERxTimeOutEn;
+
+wire    clk;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+reg     [7:0]RXPktStatus;
+wire    [7:0]RXStreamStatusIn;
+wire    SIERxTimeOut;
+reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg RXOverflow, next_RXOverflow;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+reg RXTimeOut, next_RXTimeOut;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0]CurrState_getPkt, NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+RXOverflow or RXTimeOut or
+NAKRxed or stallRxed or
+ACKRxed or dataSequence)
+begin
+RXPktStatus <= {
+dataSequence, ACKRxed,
+stallRxed, NAKRxed,
+RXTimeOut, RXOverflow,
+bitStuffError, CRCError};
+end
+
+
+// Machine: getPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or NAKRxed or stallRxed or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_getPkt)
+begin
+  NextState_getPkt <= CurrState_getPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  next_SIERxTimeOutEn <= SIERxTimeOutEn;
+  case (CurrState_getPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b1;
+      if (SIERxTimeOut == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_getPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_getPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_getPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+        next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_getPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (RXFifoFull == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_getPkt <= `START_GP;
+  else
+    CurrState_getPkt <= NextState_getPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RxPID <= 4'h0;
+    SIERxTimeOutEn <= 1'b0;
+    RXOverflow <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXByteOld <= 8'h00;
+    RXTimeOut <= 1'b0;
+  end
+  else 
+  begin
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RxPID <= next_RxPID;
+    SIERxTimeOutEn <= next_SIERxTimeOutEn;
+    RXOverflow <= next_RXOverflow;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXByteOld <= next_RXByteOld;
+    RXTimeOut <= next_RXTimeOut;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.v	(revision 264)
@@ -0,0 +1,447 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (clearTXReq, clk, getPacketRdy, getPacketREn, isoEn, rst, RXStatus, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input   clk;
+input   getPacketRdy;
+input   isoEn;
+input   rst;
+input   [7:0]RXStatus;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   transReq;
+input   [1:0]transType;
+output  clearTXReq;
+output  getPacketREn;
+output  sendPacketArbiterReq;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  transDone;
+
+reg     clearTXReq, next_clearTXReq;
+wire    clk;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+wire    isoEn;
+wire    rst;
+wire    [7:0]RXStatus;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     transDone, next_transDone;
+wire    transReq;
+wire    [1:0]transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 6'b000000
+`define TX_REQ 6'b000001
+`define CHK_TYPE 6'b000010
+`define FLAG 6'b000011
+`define IN_WAIT_DATA_RXED 6'b000100
+`define IN_CHK_FOR_ERROR 6'b000101
+`define IN_CLR_SP_WEN2 6'b000110
+`define SETUP_CLR_SP_WEN1 6'b000111
+`define SETUP_CLR_SP_WEN2 6'b001000
+`define FIN 6'b001001
+`define WAIT_GNT 6'b001010
+`define SETUP_WAIT_PKT_RXED 6'b001011
+`define IN_WAIT_IN_SENT 6'b001100
+`define OUT0_WAIT_RX_DATA 6'b001101
+`define OUT0_WAIT_DATA0_SENT 6'b001110
+`define OUT0_WAIT_OUT_SENT 6'b001111
+`define SETUP_HC_WAIT_RDY 6'b010000
+`define IN_WAIT_SP_RDY1 6'b010001
+`define IN_WAIT_SP_RDY2 6'b010010
+`define OUT0_WAIT_SP_RDY1 6'b010011
+`define SETUP_WAIT_SETUP_SENT 6'b010100
+`define SETUP_WAIT_DATA_SENT 6'b010101
+`define IN_CLR_SP_WEN1 6'b010110
+`define IN_WAIT_ACK_SENT 6'b010111
+`define OUT0_CLR_WEN1 6'b011000
+`define OUT0_CLR_WEN2 6'b011001
+`define OUT1_WAIT_RX_DATA 6'b011010
+`define OUT1_WAIT_OUT_SENT 6'b011011
+`define OUT1_WAIT_DATA1_SENT 6'b011100
+`define OUT1_WAIT_SP_RDY1 6'b011101
+`define OUT1_CLR_WEN1 6'b011110
+`define OUT1_CLR_WEN2 6'b011111
+`define OUT0_CHK_ISO 6'b100000
+`define DEL1 6'b100001
+`define DEL2 6'b100010
+
+reg [5:0]CurrState_hstCntrl, NextState_hstCntrl;
+
+
+// Machine: hstCntrl
+
+// NextState logic (combinatorial)
+always @ (transReq or transType or getPacketRdy or isoEn or RXStatus or sendPacketArbiterGnt or sendPacketRdy or transDone or clearTXReq or getPacketREn or sendPacketArbiterReq or sendPacketPID or sendPacketWEn or CurrState_hstCntrl)
+begin
+  NextState_hstCntrl <= CurrState_hstCntrl;
+  // Set default values for outputs and signals
+  next_transDone <= transDone;
+  next_clearTXReq <= clearTXReq;
+  next_getPacketREn <= getPacketREn;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketPID <= sendPacketPID;
+  next_sendPacketWEn <= sendPacketWEn;
+  case (CurrState_hstCntrl)  // synopsys parallel_case full_case
+    `START_HC:
+    begin
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `TX_REQ:
+    begin
+      if (transReq == 1'b1)
+      begin
+        NextState_hstCntrl <= `WAIT_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `CHK_TYPE:
+    begin
+      if (transType == `OUTDATA0_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+      end
+      else if (transType == `IN_TRANS)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+      end
+      else if (transType == `SETUP_TRANS)
+      begin
+        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+      end
+      else if (transType == `OUTDATA1_TRANS)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+      end
+    end
+    `FLAG:
+    begin
+      next_transDone <= 1'b1;
+      next_clearTXReq <= 1'b1;
+      next_sendPacketArbiterReq <= 1'b0;
+      NextState_hstCntrl <= `FIN;
+    end
+    `FIN:
+    begin
+      next_clearTXReq <= 1'b0;
+      next_transDone <= 1'b0;
+      //now wait for 'transReq' to clear
+      NextState_hstCntrl <= `DEL1;
+    end
+    `WAIT_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1)
+      begin
+        NextState_hstCntrl <= `CHK_TYPE;
+      end
+    end
+    `DEL1:
+    begin
+      NextState_hstCntrl <= `DEL2;
+    end
+    `DEL2:
+    begin
+      NextState_hstCntrl <= `TX_REQ;
+    end
+    `SETUP_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+    end
+    `SETUP_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+    end
+    `SETUP_WAIT_PKT_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `SETUP_HC_WAIT_RDY:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `SETUP;
+      end
+    end
+    `SETUP_WAIT_SETUP_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `SETUP_WAIT_DATA_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_DATA_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+      end
+    end
+    `IN_CHK_FOR_ERROR:
+    begin
+      if (isoEn == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+      else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+      end
+      else
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `IN_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+    end
+    `IN_WAIT_IN_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `IN_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `IN;
+      end
+    end
+    `IN_WAIT_SP_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `IN_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+    end
+    `IN_WAIT_ACK_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT0_WAIT_DATA0_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CHK_ISO;
+      end
+    end
+    `OUT0_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    end
+    `OUT0_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT0_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+    end
+    `OUT0_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+    end
+    `OUT0_CHK_ISO:
+    begin
+      if (isoEn == 1'b0)
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+      else
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT1_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `FLAG;
+      end
+    end
+    `OUT1_WAIT_OUT_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `OUT1_WAIT_DATA1_SENT:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `OUT1_WAIT_SP_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    end
+    `OUT1_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+    end
+    `OUT1_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_hstCntrl <= `START_HC;
+  else
+    CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    transDone <= 1'b0;
+    clearTXReq <= 1'b0;
+    getPacketREn <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketPID <= 4'b0;
+    sendPacketWEn <= 1'b0;
+  end
+  else 
+  begin
+    transDone <= next_transDone;
+    clearTXReq <= next_clearTXReq;
+    getPacketREn <= next_getPacketREn;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketPID <= next_sendPacketPID;
+    sendPacketWEn <= next_sendPacketWEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketarbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
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+GRIDSIZE 5000,5000 10000,10000
+END
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+I 51 0 2 Builtin InPort | 38527,153081 "" ""
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+I 53 0 130 Builtin InPort | 38410,162874 "" ""
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
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+                                      189371,107780 182843,108050 176316,108321 158239,103840\
+                                      151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 184576,32757 1 0 0 "HCTxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)  \nbegin\n  if (muxSOFNotHC  == 1'b1)  \n  begin\n    sendPacketWEnable <= SOF_SP_WEn;\n    sendPacketPID <= `SOF;\n  end\n  else\n  begin\n    sendPacketWEnable <= HC_SP_WEn;\n    sendPacketPID <= HC_PID;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "SOFTxGnt <= 1'b0;"
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+                                      123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "HCTxGnt <= 1'b0;"
+I 85 0 2 Builtin InPort | 38222,167883 "" ""
+L 86 85 0 TEXT "Labels" | 44222,167883 1 0 0 "HC_SP_WEn"
+I 89 0 2 Builtin InPort | 92234,162554 "" ""
+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sofcontroller\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
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+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: SOFController"
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+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "sofCntl"
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+A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n  SOFTimer <= 16'h0000;\nelse\n  SOFTimer <= SOFTimer + 1'b1;"
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+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/speedCtrlMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/speedCtrlMux.v	(revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// speedCtrlMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input   directCtrlRate;
+input   directCtrlPol;
+input   sendPacketRate;
+input   sendPacketPol;
+input   sendPacketSel;
+output  fullSpeedRate;
+output  fullSpeedPol;
+
+wire   directCtrlRate;
+wire   directCtrlPol;
+wire   sendPacketRate;
+wire   sendPacketPol;
+wire   sendPacketSel;
+reg   fullSpeedRate;
+reg   fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+  if (sendPacketSel == 1'b1) 
+  begin
+  fullSpeedRate <= sendPacketRate;
+  fullSpeedPol <= sendPacketPol;
+  end
+  else
+  begin
+  fullSpeedRate <= directCtrlRate;
+  fullSpeedPol <= directCtrlPol;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbConstants_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbConstants_h.v	(revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v                                             
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc 
+     
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined       
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSlaveControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSlaveControl_h.v	(revision 264)
@@ -0,0 +1,81 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v                                           
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants 
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices 
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices 
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices 
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+`define ENDPOINT_ISO_ENABLE_BIT 4
+//SCMasterControlegIndices 
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices 
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes 
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts 
+`define SC_RX_PACKET_TOUT 18
+       
+`endif //usbSlaveControl_h_vdefined  

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/lineControlUpdate.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/lineControlUpdate.v	(revision 264)
@@ -0,0 +1,76 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// lineControlUpdate.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+    if (fullSpeedPolarity == 1'b1)
+  begin
+      JBit = `ONE_ZERO;
+      KBit = `ZERO_ONE;
+    end
+    else
+  begin
+      JBit = `ZERO_ONE;
+      KBit = `ONE_ZERO;
+    end
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.v	(revision 264)
@@ -0,0 +1,498 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processRxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, processRxByteRdy, processRxDataInWEn, rst, rstCRC, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOut, RxDataOutWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   processRxDataInWEn;
+input   rst;
+input   [7:0]RxByteIn;
+input   [7:0]RxCtrlIn;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processRxByteRdy;
+output  rstCRC;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+output  RxDataOutWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+reg     processRxByteRdy, next_processRxByteRdy;
+wire    processRxDataInWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]RxByteIn;
+wire    [7:0]RxCtrlIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+reg     RxDataOutWEn, next_RxDataOutWEn;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg bitStuffError, next_bitStuffError;
+reg CRCError, next_CRCError;
+reg dataSequence, next_dataSequence;
+reg NAKRxed, next_NAKRxed;
+reg  [7:0]RxByte, next_RxByte;
+reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg  [7:0]RxCtrl, next_RxCtrl;
+reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg RxOverflow, next_RxOverflow;
+reg  [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0]CurrState_prRxByte, NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+next_RxOverflow or next_NAKRxed or
+next_stallRxed or next_ACKRxed or
+next_dataSequence)
+begin
+RxStatus <=
+{1'b0, next_dataSequence,
+next_ACKRxed,
+next_stallRxed, next_NAKRxed,
+next_RxOverflow,
+next_bitStuffError, next_CRCError };
+end
+
+
+// Machine: prRxByte
+
+// NextState logic (combinatorial)
+always @ (RXByteStMachCurrState or processRxDataInWEn or CRC16Result or CRC5Result or RxByteIn or RxCtrlIn or RxByte or RxStatus or RXDataByteCnt or CRC5UpdateRdy or CRC16UpdateRdy or RxCtrl or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin
+  NextState_prRxByte <= CurrState_prRxByte;
+  // Set default values for outputs and signals
+  next_RxByte <= RxByte;
+  next_RxCtrl <= RxCtrl;
+  next_RXByteStMachCurrState <= RXByteStMachCurrState;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RxOverflow <= RxOverflow;
+  next_RxTimeOut <= RxTimeOut;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_RxDataOut <= RxDataOut;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOutWEn <= RxDataOutWEn;
+  next_rstCRC <= rstCRC;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_RXDataByteCnt <= RXDataByteCnt;
+  next_processRxByteRdy <= processRxByteRdy;
+  case (CurrState_prRxByte)  // synopsys parallel_case full_case
+    `CHK_ST:
+    begin
+      if (RXByteStMachCurrState == `TOKEN_BYTE_ST)
+      begin
+        NextState_prRxByte <= `TOKEN_WAIT_CRC;
+      end
+      else if (RXByteStMachCurrState == `HS_BYTE_ST)
+      begin
+        NextState_prRxByte <= `HSHAKE_CHK;
+      end
+      else if (RXByteStMachCurrState == `CHECK_PID_ST)
+      begin
+        NextState_prRxByte <= `CHK_PID_DO_CHK;
+      end
+      else if (RXByteStMachCurrState == `CHECK_SYNC_ST)
+      begin
+        NextState_prRxByte <= `CHK_SYNC_DO;
+      end
+      else if (RXByteStMachCurrState == `IDLE_BYTE_ST)
+      begin
+        NextState_prRxByte <= `IDLE_CHK_START;
+      end
+      else if (RXByteStMachCurrState == `DATA_BYTE_ST)
+      begin
+        NextState_prRxByte <= `DATA_WAIT_CRC;
+      end
+    end
+    `START_PRBY:
+    begin
+      next_RxByte <= 8'h00;
+      next_RxCtrl <= 8'h00;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RxOverflow <= 1'b0;
+      next_RxTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_RxDataOut <= 8'h00;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOutWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_RXDataByteCnt <= 10'h00;
+      next_processRxByteRdy <= 1'b1;
+      NextState_prRxByte <= `WAIT_BYTE;
+    end
+    `WAIT_BYTE:
+    begin
+      if (processRxDataInWEn == 1'b1)
+      begin
+        NextState_prRxByte <= `CHK_ST;
+        next_RxByte <= RxByteIn;
+        next_RxCtrl <= RxCtrlIn;
+        next_processRxByteRdy <= 1'b0;
+      end
+    end
+    `HSHAKE_FIN:
+    begin
+      next_RxDataOutWEn <= 1'b0;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `HSHAKE_CHK:
+    begin
+      NextState_prRxByte <= `HSHAKE_FIN;
+      if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RxDataOutWEn <= 1'b1;
+    end
+    `CHK_PID_DO_CHK:
+    begin
+      if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)
+      begin
+        NextState_prRxByte <= `WAIT_BYTE;
+        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+        next_processRxByteRdy <= 1'b1;
+      end
+      else
+      begin
+        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+        next_CRCError <= 1'b0;
+        next_bitStuffError <= 1'b0;
+        next_RxOverflow <= 1'b0;
+        next_NAKRxed <= 1'b0;
+        next_stallRxed <= 1'b0;
+        next_ACKRxed <= 1'b0;
+        next_dataSequence <= 1'b0;
+        next_RxTimeOut <= 1'b0;
+        next_RXDataByteCnt <= 0;
+        next_RxDataOut <= RxByte;
+        next_RxCtrlOut <= `RX_PACKET_START;
+        next_RxDataOutWEn <= 1'b1;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `CHK_PID_FIRST_BYTE_PROC:
+    begin
+      next_rstCRC <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      case (RxByte[1:0] )
+      `SPECIAL:                              //Special PID.
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      `TOKEN:                                //Token PID
+      begin
+      next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      `HANDSHAKE:                            //Handshake PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_ACKRxed <= 1'b1;
+      2'b10:
+      next_NAKRxed <= 1'b1;
+      2'b11:
+      next_stallRxed <= 1'b1;
+      default:
+      begin
+      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+      end
+      endcase
+      next_RXByteStMachCurrState <= `HS_BYTE_ST;
+      end
+      `DATA:                                  //Data PID
+      begin
+      case (RxByte[3:2] )
+      2'b00:
+      next_dataSequence <= 1'b0;
+      2'b10:
+      next_dataSequence <= 1'b1;
+      default:
+      $display ("Invalid DATA PID detected in ProcessRXByte\n");
+      endcase
+      next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+      next_RXDataByteCnt <= 0;
+      end
+      endcase
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_FIN:
+    begin
+      next_CRC16En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC16Result != 16'hb001)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC16En <= 1'b1;
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `DATA_FIN;
+    end
+    `DATA_WAIT_CRC:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `DATA_CHK_STRM;
+      end
+    end
+    `TOKEN_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+      `DATA_STOP:
+      begin
+      if (CRC5Result != 5'h6)
+      next_CRCError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_BIT_STUFF_ERROR:
+      begin
+      next_bitStuffError <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      `DATA_STREAM:
+      begin
+      if (RXDataByteCnt > 10'h2)
+      begin
+      next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      end
+      else
+      begin
+      next_RxDataOut <= RxByte;
+      next_RxCtrlOut <= `RX_PACKET_STREAM;
+      next_CRCData <= RxByte;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      end
+      end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `TOKEN_FIN;
+    end
+    `TOKEN_FIN:
+    begin
+      next_CRC5En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `TOKEN_WAIT_CRC:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_prRxByte <= `TOKEN_CHK_STRM;
+      end
+    end
+    `CHK_SYNC_DO:
+    begin
+      if (RxByte == `SYNC_BYTE)
+      next_RXByteStMachCurrState <= `CHECK_PID_ST;
+      else
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `IDLE_CHK_START:
+    begin
+      if (RxCtrl == `DATA_START)
+      next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxByte <= `START_PRBY;
+  else
+    CurrState_prRxByte <= NextState_prRxByte;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RxDataOut <= 8'h00;
+    RxCtrlOut <= 8'h00;
+    RxDataOutWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    processRxByteRdy <= 1'b1;
+    RxByte <= 8'h00;
+    RxCtrl <= 8'h00;
+    RXByteStMachCurrState <= `IDLE_BYTE_ST;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RxOverflow <= 1'b0;
+    RxTimeOut <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    RXDataByteCnt <= 10'h00;
+  end
+  else 
+  begin
+    RxDataOut <= next_RxDataOut;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOutWEn <= next_RxDataOutWEn;
+    rstCRC <= next_rstCRC;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    processRxByteRdy <= next_processRxByteRdy;
+    RxByte <= next_RxByte;
+    RxCtrl <= next_RxCtrl;
+    RXByteStMachCurrState <= next_RXByteStMachCurrState;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RxOverflow <= next_RxOverflow;
+    RxTimeOut <= next_RxTimeOut;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    RXDataByteCnt <= next_RXDataByteCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.v	(revision 264)
@@ -0,0 +1,236 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hctxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, HCTxPortCntl, HCTxPortData, HCTxPortWEnable, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+input   [7:0]SOFCntlCntl;
+input   [7:0]SOFCntlData;
+input   SOFCntlReq;
+input   SOFCntlWEn;
+output  directCntlGnt;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortWEnable;
+output  sendPacketGnt;
+output  SOFCntlGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+reg     HCTxPortWEnable, next_HCTxPortWEnable;
+wire    rst;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+wire    [7:0]SOFCntlCntl;
+wire    [7:0]SOFCntlData;
+reg     SOFCntlGnt, next_SOFCntlGnt;
+wire    SOFCntlReq;
+wire    SOFCntlWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg  [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0]CurrState_HCTxArb, NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+`SOF_CTRL_MUX :
+begin
+HCTxPortWEnable <= SOFCntlWEn;
+HCTxPortData <= SOFCntlData;
+HCTxPortCntl <= SOFCntlCntl;
+end
+`DIRECT_CTRL_MUX :
+begin
+HCTxPortWEnable <= directCntlWEn;
+HCTxPortData <= directCntlData;
+HCTxPortCntl <= directCntlCntl;
+end
+`SEND_PACKET_MUX :
+begin
+HCTxPortWEnable <= sendPacketWEn;
+HCTxPortData <= sendPacketData;
+HCTxPortCntl <= sendPacketCntl;
+end
+default :
+begin
+HCTxPortWEnable <= 1'b0;
+HCTxPortData <= 8'h00;
+HCTxPortCntl <= 8'h00;
+end
+endcase
+end
+
+
+// Machine: HCTxArb
+
+// NextState logic (combinatorial)
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or sendPacketGnt or directCntlGnt or muxCntl or CurrState_HCTxArb)
+begin
+  NextState_HCTxArb <= CurrState_HCTxArb;
+  // Set default values for outputs and signals
+  next_SOFCntlGnt <= SOFCntlGnt;
+  next_sendPacketGnt <= sendPacketGnt;
+  next_directCntlGnt <= directCntlGnt;
+  next_muxCntl <= muxCntl;
+  case (CurrState_HCTxArb)  // synopsys parallel_case full_case
+    `START_HARB:
+    begin
+      NextState_HCTxArb <= `WAIT_REQ;
+    end
+    `WAIT_REQ:
+    begin
+      if (SOFCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb <= `SEND_SOF;
+        next_SOFCntlGnt <= 1'b1;
+        next_muxCntl <= `SOF_CTRL_MUX;
+      end
+      else if (sendPacketReq == 1'b1)
+      begin
+        NextState_HCTxArb <= `SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxCntl <= `SEND_PACKET_MUX;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_HCTxArb <= `DIRECT_CONTROL;
+        next_directCntlGnt <= 1'b1;
+        next_muxCntl <= `DIRECT_CTRL_MUX;
+      end
+    end
+    `SEND_SOF:
+    begin
+      if (SOFCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb <= `WAIT_REQ;
+        next_SOFCntlGnt <= 1'b0;
+      end
+    end
+    `SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_HCTxArb <= `WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `DIRECT_CONTROL:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_HCTxArb <= `WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_HCTxArb <= `START_HARB;
+  else
+    CurrState_HCTxArb <= NextState_HCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFCntlGnt <= 1'b0;
+    sendPacketGnt <= 1'b0;
+    directCntlGnt <= 1'b0;
+    muxCntl <= 2'b00;
+  end
+  else 
+  begin
+    SOFCntlGnt <= next_SOFCntlGnt;
+    sendPacketGnt <= next_sendPacketGnt;
+    directCntlGnt <= next_directCntlGnt;
+    muxCntl <= next_muxCntl;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.asf	(revision 264)
@@ -0,0 +1,285 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=260
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
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+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888
+W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311
+W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500
+L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
+S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
+I 84 51 0 Builtin Entry | 48374,241112
+I 83 51 0 Builtin Exit | 161275,73621
+W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
+C 81 50 0 TEXT "Conditions" | 135398,83918 1 0 0 "PID == `DATA0 || PID == `DATA1"
+C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
+S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
+L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
+W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
+A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+I 110 58 0 Builtin Exit | 176204,35771
+I 111 58 0 Builtin Entry | 69864,225148
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1;	 \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127618,200894 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+                                          48213,88528 42471,75064 41184,67490 39897,59917\
+                                          40491,43087 47668,36800 54846,30514 82962,22198\
+                                          91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+                                          200128,135446 205472,144130 205681,151728 205890,159327\
+                                          201380,181037 194241,189595 187102,198154 163054,210680\
+                                          152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+H 229 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 227 6 102420 ELLIPSE "Junction" | 165212,109319 3500 3500
+L 228 227 0 TEXT "State Labels" | 165212,109319 1 0 0 "J1"
+I 230 229 0 Builtin Entry | 86360,167640
+I 231 229 0 Builtin Exit | 129540,111760
+W 232 229 0 230 231 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+L 233 234 0 TEXT "Labels" | 162660,245408 1 0 0 "fullSpeedPolarity"
+I 234 0 2 Builtin InPort | 156660,245408 "" ""
+L 235 236 0 TEXT "State Labels" | 198623,87106 1 0 0 "LS_EOP"
+S 236 6 106500 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 198623,87106 6500 6500
+W 237 6 1 227 236 BEZIER "Transitions" | 168384,107842 175000,104995 188420,97278 193251,90764
+W 238 6 2 227 21 BEZIER "Transitions" | 161819,108462 150848,105699 131009,99230 120038,96467
+W 239 6 0 236 47 BEZIER "Transitions" | 199566,80679 201782,68823 204064,53250 203352,44331\
+                                        202640,35412 197280,23183 191376,19540 185472,15898\
+                                        167213,13552 158043,13342 148873,13133 131482,15160\
+                                        122270,15913
+C 240 237 0 TEXT "Conditions" | 144637,101038 1 0 0 "PID == `SOF && fullSpeedPolarity == 1'b0"
+H 241 236 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 248 241 110592 ELLIPSE "States" | 84074,210161 6500 6500
+L 249 248 0 TEXT "State Labels" | 84074,210864 1 0 0 "WAIT_RDY\n/21/"
+I 250 241 0 Builtin Entry | 60577,248468
+I 251 241 0 Builtin Exit | 157344,113693
+W 252 241 0 250 248 BEZIER "Transitions" | 64714,248468 68921,238227 72224,227202 80510,215594
+S 253 241 114688 ELLIPSE "States" | 86361,171124 6500 6500
+L 254 253 0 TEXT "State Labels" | 86361,171124 1 0 0 "FIN\n/22/"
+W 255 241 0 248 253 BEZIER "Transitions" | 84293,203686 84642,196968 85300,184294 85649,177576
+C 256 255 0 TEXT "Conditions" | 86576,203303 1 0 0 "HCTxPortRdy == 1'b1"
+A 257 255 16 TEXT "Actions" | 78942,195669 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_LS_KEEP_ALIVE;"
+A 258 253 4 TEXT "Actions" | 104967,172420 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 259 241 0 253 251 BEZIER "Transitions" | 90715,166299 107284,153460 137919,126532 154488,113693
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.asf	(revision 264)
@@ -0,0 +1,146 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=161
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketcheckpreamble\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 32
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 158 37 BEZIER "Transitions" | 116216,34379 122135,26559 180161,53114 186081,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 70466,115662 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 156 60 BEZIER "Transitions" | 58983,118146 59059,114780 91699,99435 91452,95786
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88319,164339 88052,159633
+S 55 33 20480 ELLIPSE "States" | 88319,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88319,153150 1 0 0 "PREAM_SENT\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "PID_SENT\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+C 73 39 0 TEXT "Conditions" | 145852,37243 1 0 0 "sendPacketRdy == 1'b1"
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+                                        94907,51569 61918,50756 52575,52503 43232,54250\
+                                        38843,62050 37706,72734 36569,83418 36406,118357\
+                                        40062,129609 43718,140862 58507,150938 67687,153172\
+                                        76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 34428,222262 "" ""
+L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;"
+A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;"
+L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/"
+S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500
+L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/"
+S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500
+W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011
+W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.asf	(revision 264)
@@ -0,0 +1,110 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=95
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// softransmit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+F 6 0 671089152 54 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 16 6 0 Builtin Reset | 76112,190530
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+                                     119442,151760 119430,151725 119430,151571
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
+W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429
+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;\ni <= 8'h00;"
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+S 79 6 24576 ELLIPSE "States" | 54655,123733 6500 6500
+L 78 79 0 TEXT "State Labels" | 54655,123733 1 0 0 "DLY_SOF_CHK2\n/6/"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+                                         105450,47318 105450,38252 107207,34228 108965,30205\
+                                         115846,23167 119361,19652
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+L 73 74 0 TEXT "State Labels" | 63408,80448 1 0 0 "DLY_SOF_CHK1\n/5/"
+S 74 6 20480 ELLIPSE "States" | 63408,80448 6500 6500
+W 75 6 0 26 74 BEZIER "Transitions" | 117387,14280 106719,14616 86172,13920 78234,17868\
+                                      70296,21816 59880,36936 57948,44622 56016,52308\
+                                      59778,66554 61122,74366
+A 76 75 16 TEXT "Actions" | 55404,31002 1 0 0 "i <= 8'h00;"
+C 94 92 0 TEXT "Conditions" | 68357,136883 1 0 0 "i==8'hff"
+A 93 79 4 TEXT "Actions" | 72777,123623 1 0 0 "i <= i + 1'b1;"
+W 92 6 0 79 11 BEZIER "Transitions" | 60486,126602 74574,130193 99716,139754 113804,143345
+A 91 82 16 TEXT "Actions" | 49949,109037 1 0 0 "sendPacketArbiterReq <= 1'b0;\ni <= 8'h00;"
+C 90 82 0 TEXT "Conditions" | 61793,96219 1 0 0 "i==8'hff"
+A 88 74 4 TEXT "Actions" | 81838,80970 1 0 0 "i <= i + 1'b1;"
+I 87 0 130 Builtin Signal | 47362,241979 "" ""
+L 86 87 0 TEXT "Labels" | 50362,241979 1 0 0 "i[7:0]"
+C 85 75 0 TEXT "Conditions" | 66368,14007 1 0 0 "sendPacketRdy == 1'b1"
+W 82 6 0 74 79 BEZIER "Transitions" | 61272,86583 60002,89345 56169,113512 55585,117302
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMux.v	(revision 264)
@@ -0,0 +1,198 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Controls the select line for the mux that enables the sharing
+//// of a single SerialInterfaceEgine between the hostController
+//// and slaveController
+//// Also a dumping area for any features common to host and slave 
+//// operation. That is reset control and version number report.
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module hostSlaveMux (
+  SIEPortCtrlInToSIE,
+  SIEPortCtrlInFromHost,
+  SIEPortCtrlInFromSlave,
+  SIEPortDataInToSIE, 
+  SIEPortDataInFromHost, 
+  SIEPortDataInFromSlave, 
+  SIEPortWEnToSIE, 
+  SIEPortWEnFromHost, 
+  SIEPortWEnFromSlave, 
+  fullSpeedPolarityToSIE,
+  fullSpeedPolarityFromHost,
+  fullSpeedPolarityFromSlave,
+  fullSpeedBitRateToSIE,
+  fullSpeedBitRateFromHost,
+  fullSpeedBitRateFromSlave,
+  noActivityTimeOutEnableToSIE,
+  noActivityTimeOutEnableFromHost,
+  noActivityTimeOutEnableFromSlave,
+  dataIn, 
+  dataOut,
+  address,
+  writeEn,
+  strobe_i,
+  busClk, 
+  usbClk, 
+  hostSlaveMuxSel,
+  rstFromWire,
+  rstSyncToBusClkOut,
+  rstSyncToUsbClkOut
+);
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE; 
+input [7:0] SIEPortDataInFromHost; 
+input [7:0] SIEPortDataInFromSlave; 
+output SIEPortWEnToSIE; 
+input SIEPortWEnFromHost; 
+input SIEPortWEnFromSlave; 
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+output noActivityTimeOutEnableToSIE;
+input noActivityTimeOutEnableFromHost;
+input noActivityTimeOutEnableFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE; 
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+reg SIEPortWEnToSIE; 
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+reg noActivityTimeOutEnableToSIE;
+wire noActivityTimeOutEnableFromHost;
+wire noActivityTimeOutEnableFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClkOut;
+wire rstSyncToUsbClkOut;
+wire rstFromWire;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+  SIEPortCtrlInFromHost or
+  SIEPortCtrlInFromSlave or
+  SIEPortDataInFromHost or 
+  SIEPortDataInFromSlave or 
+  SIEPortWEnFromHost or 
+  SIEPortWEnFromSlave or 
+  fullSpeedPolarityFromHost or
+  fullSpeedPolarityFromSlave or
+  fullSpeedBitRateFromHost or
+  fullSpeedBitRateFromSlave or
+  noActivityTimeOutEnableFromHost or
+  noActivityTimeOutEnableFromSlave)
+begin
+  if (hostMode == 1'b1) 
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+    SIEPortDataInToSIE <=  SIEPortDataInFromHost;
+    SIEPortWEnToSIE <= SIEPortWEnFromHost;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+    noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromHost;
+  end
+  else
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+    SIEPortDataInToSIE <=  SIEPortDataInFromSlave;
+    SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+    noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromSlave;
+  end
+end      
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(dataIn), 
+  .dataOut(dataOut),
+  .address(address),
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .hostMode(hostMode), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),  
+  .rstFromWire(rstFromWire),
+  .rstSyncToBusClkOut(rstSyncToBusClkOut),
+  .rstSyncToUsbClkOut(rstSyncToUsbClkOut) );
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostSlave_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostSlave_h.v	(revision 264)
@@ -0,0 +1,55 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+//             control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect 
+//             time outs, added low speed EOP keep alive. The TX bit rate is now controlled by 
+//             SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+//             speed, and TX resume is always low speed.
+//             Fixed read clock recovery (readUSBWireData.v) issue which was resulting 
+//             in missing receive packets.
+//             Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+//             by adding kludged delay to softranmit. This needs to be fixed properly.
+//             This version has undergone limited testing
+//             with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+//             with uClinux, and is known to work with a full speed USB flash stick.
+//             Moving Opencores project status from Beta to done.
+//             TODO: Test isochronous mode, and low speed mode using uClinux driver
+//                   Create a seperate clock domain for the bus interface
+//                   Add frame period adjustment capability
+//                   Add compilation flags for slave only and host only versions
+//                   Create data bus width options beyond 8-bit
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+//             Removed TX and RX fifo status registers, and removed 
+//             TX fifo data count register.
+//             Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG. 
+//             Fixed slave mode bug which caused receive fifo to be filled with 
+//             incoming data when the slave was responding with a NAK, and the 
+//             data should have been discarded.
+// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
+//             Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
+//             there was no detected activity on the USB data lines. This caused an infrequent
+//             misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
+//             the higher level state machines are actively looking for receive packets. 
+//             Modified USB RX data clock recovery, so that data is sampled during the middle
+//             of a USB bit period. Fixed a bug which could result in double sampling
+//             of USB RX data if clock phase adjustments were required in the middle of a 
+//             USB packet.
+
+// Most significant nibble corresponds to major revision.
+// Least significant nibble corresponds to minor revision.
+`define USBHOSTSLAVE_VERSION_NUM 8'h11   
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbHostSlave_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.asf	(revision 264)
@@ -0,0 +1,638 @@
+VERSION=1.15
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FRAMES=ON
+FREEOID=1083
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIETransmitter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 16
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 213
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 455
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+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 465
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
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+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
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+END
+INSTHEADER 483
+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
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+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 626
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
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+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 720
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
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+END
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+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
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+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 958
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 1073
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 130 Builtin OutPort | 64372,246658 "" ""
+L 821 822 0 TEXT "Labels" | 70372,246658 1 0 0 "TxByteOutCtrl[7:0]"
+I 820 0 130 Builtin OutPort | 64372,251298 "" ""
+L 819 820 0 TEXT "Labels" | 70372,251298 1 0 0 "TxByteOut[7:0]"
+I 818 0 2 Builtin InPort | 66692,255938 "" ""
+L 817 818 0 TEXT "Labels" | 72692,255938 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin OutPort | 64372,260578 "" ""
+L 15 16 0 TEXT "State Labels" | 115356,124706 1 0 0 "RES_ST"
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "STX_CHK_ST\n/19/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: SIETransmitter"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,209519
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "SIETx"
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_SIETX\n/18/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 847 0 130 Builtin InPort | 124599,219647 "" ""
+I 846 0 130 Builtin InPort | 125108,215006 "" ""
+L 845 846 0 TEXT "Labels" | 131108,215006 1 0 0 "KBit[1:0]"
+I 844 0 130 Builtin Signal | 71500,215836 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[2:0]"
+I 840 0 130 Builtin Signal | 71500,220244 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 838 0 130 Builtin Signal | 71732,224652 "" ""
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+A 836 63 4 TEXT "Actions" | 118825,194982 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,123104 6500 6500
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/31/"
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/10/"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+I 572 458 0 Builtin Entry | 44780,253519
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+W 574 458 0 567 540 BEZIER "Transitions" | 44528,153207 48588,141781 61374,54759 65434,43333
+A 835 9 4 TEXT "Actions" | 153876,207727 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 3'h0;\nresumeCnt <= 16'h0000;\nTxByteOutFullSpeedRate <= 1'b0;\nUSBWireFullSpeedRate <= 1'b0;"
+L 848 847 0 TEXT "Labels" | 130599,219647 1 0 0 "JBit[1:0]"
+L 319 320 0 TEXT "Labels" | 133337,226207 1 0 0 "fullSpeedRateIn"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 606 489 0 Builtin Exit | 101068,51939
+I 599 489 0 Builtin Entry | 29952,254306
+I 324 0 130 Builtin InPort | 126267,235982 "" ""
+L 323 324 0 TEXT "Labels" | 132267,235982 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin InPort | 127337,226207 "" ""
+S 63 6 0 ELLIPSE "States" | 138700,177505 6500 6500
+L 62 63 0 TEXT "State Labels" | 139687,176678 1 0 0 "STX_WAIT_BYTE\n/20/"
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+                                      42326,129670 44202,125650 52711,124511 61220,123372\
+                                      92777,123293 108857,123025
+I 872 360 0 Builtin Exit | 188676,86316
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 77071,148182 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 74766,198892 6500 6500
+L 608 609 0 TEXT "State Labels" | 74766,198892 1 0 0 "PID"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+                                        161730,108850 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 144540,155815\
+                                        141750,161305 138960,166795 141442,165439 137520,171118
+A 78 65 16 TEXT "Actions" | 53177,187164 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;\nTxByteOutFullSpeedRate <= fullSpeedRateIn;\nUSBWireFullSpeedRate <= fullSpeedRateIn;"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+C 66 65 0 TEXT "Conditions" | 70342,165567 1 0 0 "SIEPortWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 132240,176792 119927,171164 59299,174571 47927,176730
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/0/"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 3'h7"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 636 610 0 Builtin Entry | 71380,236621
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 634 626 0 TEXT "State Labels" | 75688,89174 1 0 0 "CRC"
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 75688,89174 6500 6500
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 77071,148182 1 0 0 "BYTE1"
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 80182,200322 122622,188930 134753,182668
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 363 360 0 Builtin Entry | 26888,244668
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+                                        43361,99065 46384,95576 54928,94878 63472,94181\
+                                        94207,96080 109784,96428
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/38/"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/29/"
+I 908 224 0 Builtin Entry | 85162,237767
+I 909 224 0 Builtin Exit | 108872,88817
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+I 914 912 0 Builtin Exit | 129540,111760
+I 913 912 0 Builtin Entry | 86360,167640
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/22/"
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+W 651 489 0 626 606 BEZIER "Transitions" | 78534,83332 83720,75495 93087,59776 98273,51939
+W 650 489 0 617 626 BEZIER "Transitions" | 76796,141693 76220,129592 76063,107757 75487,95656
+W 649 489 0 609 617 BEZIER "Transitions" | 74835,192396 75180,182600 76125,164449 76470,154653
+W 648 489 0 599 609 BEZIER "Transitions" | 33927,254306 41205,251054 71176,221478 73868,205326
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+I 645 610 0 Builtin Exit | 114540,97930
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/33/"
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 3'h0;"
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+S 939 633 8192 ELLIPSE "States" | 39277,179580 6500 6500
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/42/"
+I 671 624 0 Builtin Exit | 116402,43935
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+                                           104039,47385 110550,45085 113597,43935
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+I 663 624 0 Builtin Entry | 59190,254840
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/26/"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+W 956 360 0 363 1073 BEZIER "Transitions" | 30725,244668 34469,239130 89108,253575 97764,256633
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+S 952 624 16384 ELLIPSE "States" | 35474,185224 6500 6500
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/44/"
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+S 947 734 12288 ELLIPSE "States" | 160390,197270 6500 6500
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/43/"
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+I 682 633 0 Builtin Exit | 119917,39891
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/21/"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/36/"
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+A 414 413 16 TEXT "Actions" | 50560,239516 1 0 0 "USBWireReq <= 1'b1;\nresumeCnt  <= 16'h0000;\nUSBWireFullSpeedRate <= 1'b0; //resume always uses low speed timing"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/35/"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/1/"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;	\nresumeCnt  <= resumeCnt  + 1'b1;"
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+L 957 958 0 TEXT "State Labels" | 118124,69006 1 0 0 "TX_LS_EOP"
+S 958 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118124,67086 6500 6500
+W 959 6 0 11 958 BEZIER "Transitions" | 41589,169153 41990,145961 42609,100547 43291,87547\
+                                        43973,74547 45899,68928 54485,67524 63072,66120\
+                                        95424,66959 111633,66752
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/32/"
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/8/"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/25/"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "W_RDY1\n/24/"
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+I 418 17 0 Builtin Exit | 171923,20004
+I 417 17 0 Builtin Entry | 44586,243455
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/28/"
+W 425 17 1 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+C 426 425 0 TEXT "Conditions" | 62970,121537 1 0 0 "resumeCnt == `HOST_TX_RESUME_TIME"
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "SND_SE0_1\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 429 430 0 TEXT "State Labels" | 62301,61312 1 0 0 "SND_SE0_2\n/17/"
+S 430 17 0 ELLIPSE "States" | 62301,61312 6500 6500
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "SND_J_1\n/14/"
+C 960 959 0 TEXT "Conditions" | 51998,64924 1 0 0 "SIEPortCtrl == `TX_LS_KEEP_ALIVE"
+H 961 958 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 973 961 0 979 993 BEZIER "Transitions" | 70323,232853 70198,226566 70679,201498 70554,195211
+C 974 973 0 TEXT "Conditions" | 71910,232073 1 0 0 "USBWireGnt == 1'b1"
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+I 716 471 0 Builtin Entry | 83616,227615
+I 715 471 0 Builtin Exit | 140592,59380
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 713 480 0 Builtin Exit | 85376,122104
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 711 480 0 Builtin Entry | 43257,253243
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251031 41695,239812 59162,227406 68316,218108
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/7/"
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/30/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "SND_J_2\n/15/"
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+W 436 17 0 1026 430 BEZIER "Transitions" | 180912,80742 169329,74775 79549,70544 67972,64487
+W 437 17 0 1028 432 BEZIER "Transitions" | 51111,44834 62356,44473 153909,58971 165141,58620
+W 438 17 0 1030 434 BEZIER "Transitions" | 180827,34395 168542,28662 79732,38178 67447,32445
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+C 442 436 0 TEXT "Conditions" | 142323,77914 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 53546,46742 1 0 0 "USBWireRdy == 1'b1"
+C 444 438 0 TEXT "Conditions" | 151980,31125 1 0 0 "USBWireRdy == 1'b1"
+A 445 436 16 TEXT "Actions" | 93935,80043 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 94027,64120 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 447 438 16 TEXT "Actions" | 100527,44161 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 977 961 0 989 979 BEZIER "Transitions" | 59230,267637 62248,262230 65883,250383 66893,244725
+A 978 977 16 TEXT "Actions" | 61762,259858 1 0 0 "USBWireReq <= 1'b1;"
+S 979 961 24576 ELLIPSE "States" | 70526,239337 6500 6500
+S 982 961 28672 ELLIPSE "States" | 72541,157710 6500 6500
+L 983 982 0 TEXT "State Labels" | 72541,157710 1 0 0 "SND_SE0_2\n/46/"
+S 984 961 32768 ELLIPSE "States" | 180649,189534 6500 6500
+L 985 984 0 TEXT "State Labels" | 180649,189534 1 0 0 "SND_SE0_1\n/47/"
+L 988 979 0 TEXT "State Labels" | 70526,239337 1 0 0 "WAIT_GNT1\n/45/"
+I 989 961 0 Builtin Entry | 55468,267637
+I 990 961 0 Builtin Exit | 202744,115664
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/23/"
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 731 727 0 Builtin Entry | 71380,236621
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+A 448 432 4 TEXT "Actions" | 159702,69949 1 0 0 "USBWireWEn <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34545,73018 1 0 0 "USBWireWEn <= 1'b0;"
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 150428,26102 169066,20266
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/41/"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 993 961 36864 ELLIPSE "States" | 71111,188744 6500 6500
+L 994 993 0 TEXT "State Labels" | 71111,188744 1 0 0 "W_RDY1\n/48/"
+W 997 961 0 1018 1008 BEZIER "Transitions" | 102841,134185 114073,133834 169562,153024 180794,152673
+A 998 997 16 TEXT "Actions" | 129506,151946 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 999 961 0 1016 982 BEZIER "Transitions" | 191758,179211 180175,173244 89868,166719 78285,160752
+A 1000 999 16 TEXT "Actions" | 104380,176838 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1002 997 0 TEXT "Conditions" | 110626,136953 1 0 0 "USBWireRdy == 1'b1"
+C 1003 999 0 TEXT "Conditions" | 156382,176802 1 0 0 "USBWireRdy == 1'b1"
+A 1004 984 4 TEXT "Actions" | 165556,203106 1 0 0 "USBWireWEn <= 1'b0;"
+W 1005 961 0 993 984 BEZIER "Transitions" | 77608,188557 88723,188674 163036,189296 174151,189413
+A 1006 1005 16 TEXT "Actions" | 120336,197940 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 1007 1005 0 TEXT "Conditions" | 80771,193665 1 0 0 "USBWireRdy == 1'b1"
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 750 734 0 Builtin Entry | 59190,254840
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+I 744 734 0 Builtin Exit | 116402,43935
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/6/"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/34/"
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 738 727 0 Builtin Exit | 114540,97930
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+S 1008 961 40960 ELLIPSE "States" | 187291,152508 6500 6500
+L 1009 1008 0 TEXT "State Labels" | 187291,152508 1 0 0 "SND_J\n/49/"
+W 1010 961 0 1008 990 BEZIER "Transitions" | 189673,146461 206752,122150 181346,115781 199949,115664
+A 1011 1008 4 TEXT "Actions" | 175523,169038 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 1012 982 4 TEXT "Actions" | 80404,154242 1 0 0 "USBWireWEn <= 1'b0;"
+W 1014 6 0 958 911 BEZIER "Transitions" | 124457,68547 133850,72702 151714,79462 161174,83437
+L 1015 1016 0 TEXT "State Labels" | 197328,182560 1 0 0 "W_RDY2\n/50/"
+S 1016 961 45056 ELLIPSE "States" | 197328,182560 6500 6500
+L 1017 1018 0 TEXT "State Labels" | 96400,133312 1 0 0 "W_RDY3\n/51/"
+S 1018 961 49152 ELLIPSE "States" | 96400,133312 6500 6500
+W 1019 961 0 984 1016 BEZIER "Transitions" | 186591,186901 188111,186673 190020,185744 191540,185516
+W 1020 961 0 982 1018 BEZIER "Transitions" | 76114,152281 80446,148557 87065,141183 91397,137459
+L 1021 1022 0 TEXT "State Labels" | 32738,152469 1 0 0 "DELAY\n/52/"
+S 1022 17 53248 ELLIPSE "States" | 32738,152469 6500 6500
+W 1023 17 2 407 1022 BEZIER "Transitions" | 52990,130254 48496,130815 40121,131043 37433,133209\
+                                            34745,135375 33783,142213 32901,145984
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+I 762 733 0 Builtin Exit | 119917,39891
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/27/"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+S 216 6 0 ELLIPSE "States" | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE\n/4/"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/2/"
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+W 1024 17 0 1022 411 BEZIER "Transitions" | 33384,158929 34668,162139 36269,168519 38877,170084\
+                                            41485,171649 49107,171706 53039,171626
+L 1025 1026 0 TEXT "State Labels" | 186818,83454 1 0 0 "W_RDY2\n/53/"
+S 1026 17 57344 ELLIPSE "States" | 186818,83454 6500 6500
+L 1027 1028 0 TEXT "State Labels" | 44615,44613 1 0 0 "W_RDY3\n/54/"
+S 1028 17 61440 ELLIPSE "States" | 44615,44613 6500 6500
+L 1029 1030 0 TEXT "State Labels" | 187139,35946 1 0 0 "W_RDY4\n/55/"
+S 1030 17 65536 ELLIPSE "States" | 187139,35946 6500 6500
+W 1031 17 0 428 1026 BEZIER "Transitions" | 175312,89747 176917,88865 179480,87397 181085,86515
+W 1032 17 0 430 1028 BEZIER "Transitions" | 56906,57687 55061,55440 50351,52066 48506,49819
+W 1033 17 0 432 1030 BEZIER "Transitions" | 175464,53250 177630,50201 181501,44488 183667,41439
+L 1034 1035 0 TEXT "State Labels" | 59060,143481 1 0 0 "DELAY\n/56/"
+S 1035 224 69632 ELLIPSE "States" | 59060,143481 6500 6500
+W 1036 224 2 891 1035 BEZIER "Transitions" | 101504,123089 91624,127529 74202,135226 64322,139666
+W 1037 224 0 1035 897 BEZIER "Transitions" | 64606,146870 74406,150350 91859,157715 101659,161195
+L 1038 1039 0 TEXT "Labels" | 74756,230822 1 0 0 "resumeCnt[15:0]"
+I 1039 0 130 Builtin Signal | 71756,230822 "" ""
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/40/"
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/37/"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/5/"
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+                                           46299,139871 48829,136075 59202,135063 69575,134052\
+                                           106314,125693 125795,125567
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+                                           46931,109511 49715,104703 60024,103501 70334,102300\
+                                           108774,103037 128002,103037
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+                                           48196,74723 50474,70169 60657,69030 70840,67892\
+                                           108432,68626 127660,68626
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+                                           48829,42592 51359,37532 61605,36267 71852,35002\
+                                           109061,35775 128289,35775
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+L 1040 1041 0 TEXT "Labels" | 70301,241139 1 0 0 "TxByteOutFullSpeedRate"
+I 1041 0 2 Builtin OutPort | 64301,241139 "" ""
+L 1042 1043 0 TEXT "Labels" | 27464,245142 1 0 0 "USBWireFullSpeedRate"
+I 1043 0 2 Builtin OutPort | 21464,245142 "" ""
+A 1046 451 16 TEXT "Actions" | 91713,26530 1 0 0 "USBWireFullSpeedRate <= fullSpeedRateIn;"
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+                                           128857,67252 162473,65260 171997,66691 181521,68123\
+                                           186003,75843 187123,97692 188244,119542 188244,199222\
+                                           184384,221196 180525,243170 165087,251388 155563,253628\
+                                           146039,255869 123379,256617 115100,254625 106821,252633\
+                                           98206,243956 92977,239599
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+                                              31250,150650 32250,89650 34750,72525 37250,55400\
+                                              46250,47900 56000,46150 65750,44400 95896,46012\
+                                              103573,44899 111250,43786 113107,43935 113607,43935
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/3/"
+I 787 733 0 Builtin Entry | 62705,250796
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+L 1071 1072 0 TEXT "Labels" | 130970,231188 1 0 0 "CRC16En"
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+I 814 0 130 Builtin InPort | 19062,250526 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,255166 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/39/"
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+I 540 458 0 Builtin Exit | 68103,43333
+I 1072 0 2 Builtin OutPort | 124970,231188 "" ""
+H 1075 1073 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 1073 360 73748 ELLIPSE "Junction" | 100383,254312 3500 3500
+L 1074 1073 0 TEXT "State Labels" | 100383,254312 1 0 0 "J3"
+I 1076 1075 0 Builtin Entry | 86360,167640
+I 1077 1075 0 Builtin Exit | 129540,111760
+W 1078 1075 0 1076 1077 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+W 1079 360 2 1073 453 BEZIER "Transitions" | 97595,252197 93012,236072 61888,222891 52340,220350
+W 1080 360 1 1073 453 BEZIER "Transitions" | 103127,252141 112392,249752 130361,224032 127627,220759\
+                                             124894,217487 107954,214253 97790,213829 87626,213406\
+                                             65074,215466 53216,216236
+C 1081 1080 0 TEXT "Conditions" | 102248,241873 1 0 0 "SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE"
+A 1082 1080 16 TEXT "Actions" | 95072,224240 1 0 0 "TxByteOutFullSpeedRate <= 1'b1; //SOF and PRE always at full speed"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.v	(revision 264)
@@ -0,0 +1,412 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processrxbit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (clk, JBit, KBit, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive);
+input   clk;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processRxBitsWEn;
+input   processRxByteRdy;
+input   rst;
+input   [1:0]RxBitsIn;
+input   RxWireActive;
+output  processRxBitRdy;
+output  processRxByteWEn;
+output  resumeDetected;
+output  [7:0]RxCtrlOut;
+output  [7:0]RxDataOut;
+
+wire    clk;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processRxBitRdy, next_processRxBitRdy;
+wire    processRxBitsWEn;
+wire    processRxByteRdy;
+reg     processRxByteWEn, next_processRxByteWEn;
+reg     resumeDetected, next_resumeDetected;
+wire    rst;
+wire    [1:0]RxBitsIn;
+reg     [7:0]RxCtrlOut, next_RxCtrlOut;
+reg     [7:0]RxDataOut, next_RxDataOut;
+wire    RxWireActive;
+
+// diagram signals declarations
+reg bitStuffError, next_bitStuffError;
+reg  [1:0]oldRXBits, next_oldRXBits;
+reg  [4:0]resumeWaitCnt, next_resumeWaitCnt;
+reg  [3:0]RXBitCount, next_RXBitCount;
+reg  [1:0]RxBits, next_RxBits;
+reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg  [7:0]RXByte, next_RXByte;
+reg  [3:0]RXSameBitCount, next_RXSameBitCount;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0]CurrState_prRxBit, NextState_prRxBit;
+
+
+// Machine: prRxBit
+
+// NextState logic (combinatorial)
+always @ (RxBits or processRxBitsWEn or JBit or RxBitsIn or KBit or RxWireActive or RXSameBitCount or RXBitCount or RXByte or processRxByteRdy or resumeWaitCnt or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or RXBitStMachCurrState or oldRXBits or bitStuffError or processRxBitRdy or CurrState_prRxBit)
+begin
+  NextState_prRxBit <= CurrState_prRxBit;
+  // Set default values for outputs and signals
+  next_processRxByteWEn <= processRxByteWEn;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOut <= RxDataOut;
+  next_resumeDetected <= resumeDetected;
+  next_RXBitStMachCurrState <= RXBitStMachCurrState;
+  next_RxBits <= RxBits;
+  next_RXSameBitCount <= RXSameBitCount;
+  next_RXBitCount <= RXBitCount;
+  next_oldRXBits <= oldRXBits;
+  next_RXByte <= RXByte;
+  next_bitStuffError <= bitStuffError;
+  next_resumeWaitCnt <= resumeWaitCnt;
+  next_processRxBitRdy <= processRxBitRdy;
+  case (CurrState_prRxBit)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOut <= 8'h00;
+      next_resumeDetected <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_RxBits <= 2'b00;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h0;
+      next_oldRXBits <= 2'b00;
+      next_RXByte <= 8'h00;
+      next_bitStuffError <= 1'b0;
+      next_resumeWaitCnt <= 5'h0;
+      next_processRxBitRdy <= 1'b1;
+      NextState_prRxBit <= `WAIT_BITS;
+    end
+    `WAIT_BITS:
+    begin
+      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
+      begin
+        NextState_prRxBit <= `DATA_RX_CHK_SE0;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
+      begin
+        NextState_prRxBit <= `RES_RX_CHK;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
+      begin
+        NextState_prRxBit <= `RES_END_CHK1;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
+      begin
+        NextState_prRxBit <= `IDLE_CHK_KBIT;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+    end
+    `IDLE_FIRST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h1;
+      next_oldRXBits <= RxBits;
+      //zero is always the first RZ data bit of a new packet
+      next_RXByte <= 8'h00;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `IDLE_CHK_KBIT:
+    begin
+      if ((RxBits == KBit) && (RxWireActive == 1'b1))
+      begin
+        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `IDLE_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `IDLE_FIRST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_START;
+        //start of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_LAST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_CHK_SE0:
+    begin
+      next_bitStuffError <= 1'b0;
+      if (RxBits == `SE0)
+      begin
+        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
+        begin
+        next_RXSameBitCount <= RXSameBitCount + 1'b1;
+        //inc 'RXSameBitCount'
+        if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+        next_bitStuffError <= 1'b1;
+        //flag 'bitStuffError'
+        else                                          //else no bit stuffing error
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= { 1'b1, RXByte[7:1]};
+        //RZ bit <= 1 (ie no change in 'RxBits')
+        end
+        end
+        else                                            //else current 'RxBits' are different from old 'RxBits'
+        begin
+        if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+        begin
+        next_RXBitCount <= RXBitCount + 1'b1;
+        if (RXBitCount != 4'h7) begin
+        next_processRxBitRdy <= 1'b1;
+        //early indication of ready
+        end
+        next_RXByte <= {1'b0, RXByte[7:1]};
+        //RZ bit <= 0 (ie current'RxBits' is different than old 'RxBits')
+        end
+        next_RXSameBitCount <= 4'h0;
+        //reset 'RXSameBitCount'
+        end
+        next_oldRXBits <= RxBits;
+      end
+    end
+    `DATA_RX_WAIT_PRB_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_LAST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_STOP;
+        //end of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_DATA_DESTUFF:
+    begin
+      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+      end
+      else if (bitStuffError == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    end
+    `DATA_RX_BYTE_SEND2:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_BYTE_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+        next_RXBitCount <= 4'h0;
+        next_RxDataOut <= RXByte;
+        next_RxCtrlOut <= `DATA_STREAM;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `DATA_RX_ERROR_CHK_RES:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      if (RxBits == JBit)                           //if current bit is a JBit, then
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      //next state is idle
+      else                                          //else
+      begin
+      next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+      //check for resume
+      next_resumeWaitCnt <= 5'h0;
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_ERROR_WAIT_RDY:
+    begin
+      if (processRxByteRdy == 1'b1)
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+        next_processRxByteWEn <= 1'b1;
+      end
+    end
+    `RES_RX_CHK:
+    begin
+      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      else
+      begin
+      next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+      //if we've waited long enough, then
+      if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
+      begin
+      next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+      next_resumeDetected <= 1'b1;
+      //report resume detected
+      end
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `RES_END_CHK1:
+    begin
+      if (RxBits != KBit)  //line must leave KBit state for the end of resume
+      begin
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_resumeDetected <= 1'b0;
+      //clear resume detected flag
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prRxBit <= `START;
+  else
+    CurrState_prRxBit <= NextState_prRxBit;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processRxByteWEn <= 1'b0;
+    RxCtrlOut <= 8'h00;
+    RxDataOut <= 8'h00;
+    resumeDetected <= 1'b0;
+    processRxBitRdy <= 1'b1;
+    RXBitStMachCurrState <= `IDLE_BIT_ST;
+    RxBits <= 2'b00;
+    RXSameBitCount <= 4'h0;
+    RXBitCount <= 4'h0;
+    oldRXBits <= 2'b00;
+    RXByte <= 8'h00;
+    bitStuffError <= 1'b0;
+    resumeWaitCnt <= 5'h0;
+  end
+  else 
+  begin
+    processRxByteWEn <= next_processRxByteWEn;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOut <= next_RxDataOut;
+    resumeDetected <= next_resumeDetected;
+    processRxBitRdy <= next_processRxBitRdy;
+    RXBitStMachCurrState <= next_RXBitStMachCurrState;
+    RxBits <= next_RxBits;
+    RXSameBitCount <= next_RXSameBitCount;
+    RXBitCount <= next_RXBitCount;
+    oldRXBits <= next_oldRXBits;
+    RXByte <= next_RXByte;
+    bitStuffError <= next_bitStuffError;
+    resumeWaitCnt <= next_resumeWaitCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.v	(revision 264)
@@ -0,0 +1,276 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIEReceiver
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (clk, connectState, rst, RxWireDataIn, RxWireDataWEn);
+input   clk;
+input   rst;
+input   [1:0]RxWireDataIn;
+input   RxWireDataWEn;
+output  [1:0]connectState;
+
+wire    clk;
+reg     [1:0]connectState, next_connectState;
+wire    rst;
+wire    [1:0]RxWireDataIn;
+wire    RxWireDataWEn;
+
+// diagram signals declarations
+reg  [1:0]RxBits, next_RxBits;
+reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg  [7:0]RXWaitCount, next_RXWaitCount;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0]CurrState_rcvr, NextState_rcvr;
+
+
+// Machine: rcvr
+
+// NextState logic (combinatorial)
+always @ (RXWaitCount or RxBits or RxWireDataWEn or RxWireDataIn or connectState or RXStMachCurrState or CurrState_rcvr)
+begin
+  NextState_rcvr <= CurrState_rcvr;
+  // Set default values for outputs and signals
+  next_RXWaitCount <= RXWaitCount;
+  next_connectState <= connectState;
+  next_RXStMachCurrState <= RXStMachCurrState;
+  next_RxBits <= RxBits;
+  case (CurrState_rcvr)  // synopsys parallel_case full_case
+    `WAIT_BIT:
+    begin
+      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
+      begin
+        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
+      begin
+        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
+      begin
+        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+        next_RxBits <= RxWireDataIn;
+      end
+    end
+    `START_SRX:
+    begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_RXWaitCount <= 8'h00;
+      next_connectState <= `DISCONNECT;
+      next_RxBits <= 2'b00;
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `DISCNCT_CHK_RXBITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else if (RxBits == `ONE_ZERO)
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+      end
+    end
+    `WAIT_FS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ONE_ZERO)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `FULL_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `WAIT_LS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `CONNECT_WAIT_TIME)
+      begin
+      next_connectState <= `LOW_SPEED_CONNECT;
+      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `LS_CONN_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+      next_RXWaitCount <= 0;
+      end
+    end
+    `FS_CONN_CHK_RX_BITS1:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+      next_RXWaitCount <= 0;
+      end
+    end
+    `WAIT_LS_DIS_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_connectState <= `DISCONNECT;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+    end
+    `WAIT_FS_DIS_CHK_RX_BITS2:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+      next_RXWaitCount <= RXWaitCount + 1'b1;
+      if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+      begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_connectState <= `DISCONNECT;
+      end
+      end
+      else
+      begin
+      next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_rcvr <= `START_SRX;
+  else
+    CurrState_rcvr <= NextState_rcvr;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    connectState <= `DISCONNECT;
+    RXWaitCount <= 8'h00;
+    RXStMachCurrState <= `DISCONNECT_ST;
+    RxBits <= 2'b00;
+  end
+  else 
+  begin
+    connectState <= next_connectState;
+    RXWaitCount <= next_RXWaitCount;
+    RXStMachCurrState <= next_RXStMachCurrState;
+    RxBits <= next_RxBits;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(revision 264)
@@ -0,0 +1,111 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=134
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// usbTxWireArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
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+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 173058,181792 "" ""
+L 110 111 0 TEXT "Labels" | 179058,181792 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 140655,159238 "" ""
+L 108 109 0 TEXT "Labels" | 146655,159238 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 175368,186412 "" ""
+L 106 107 0 TEXT "Labels" | 181368,186412 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 138576,154618 "" ""
+L 104 105 0 TEXT "Labels" | 144576,154618 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 130 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 175137,200041 "" ""
+L 122 123 0 TEXT "Labels" | 181137,200041 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 175137,195652 "" ""
+L 120 121 0 TEXT "Labels" | 181137,195652 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 175137,191032 "" ""
+L 118 119 0 TEXT "Labels" | 181137,191032 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 140655,173329 "" ""
+L 116 117 0 TEXT "Labels" | 146655,173329 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 140655,168940 "" ""
+L 114 115 0 TEXT "Labels" | 146655,168940 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 140655,164089 "" ""
+L 112 113 0 TEXT "Labels" | 146655,164089 1 0 0 "SIETxData[1:0]"
+L 128 129 0 TEXT "Labels" | 146868,178208 1 0 0 "SIETxFSRate"
+I 129 0 2 Builtin InPort | 140868,178208 "" ""
+L 130 131 0 TEXT "Labels" | 181140,205088 1 0 0 "prcTxByteFSRate"
+I 131 0 2 Builtin InPort | 175140,205088 "" ""
+L 132 133 0 TEXT "Labels" | 148212,207440 1 0 0 "TxFSRate"
+I 133 0 2 Builtin OutPort | 142212,207440 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/endpMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/endpMux.v	(revision 264)
@@ -0,0 +1,260 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// endpMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbSlaveControl_h.v" 
+
+module endpMux (
+  clk, 
+  rst,
+  currEndP,
+  NAKSent,
+  stallSent,
+  CRCError,
+  bitStuffError,
+  RxOverflow,
+  RxTimeOut,
+  dataSequence,
+  ACKRxed,
+  transType,
+  transTypeNAK,
+  endPControlReg,
+  clrEPRdy,
+  endPMuxErrorsWEn,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  endP0StatusReg,
+  endP1StatusReg,
+  endP2StatusReg,
+  endP3StatusReg,
+  endP0TransTypeReg,
+  endP1TransTypeReg,
+  endP2TransTypeReg,
+  endP3TransTypeReg,
+  endP0NAKTransTypeReg,
+  endP1NAKTransTypeReg,
+  endP2NAKTransTypeReg,
+  endP3NAKTransTypeReg,
+  clrEP0Rdy,
+  clrEP1Rdy,
+  clrEP2Rdy,
+  clrEP3Rdy);
+
+
+input clk; 
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [4:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [4:0] endP0ControlReg;
+input [4:0] endP1ControlReg;
+input [4:0] endP2ControlReg;
+input [4:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk; 
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [4:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      endPControlReg <= endP0ControlReg;
+      clrEP0Rdy <= clrEPRdy;
+    end
+    2'b01: begin
+      endPControlReg <= endP1ControlReg;
+      clrEP1Rdy <= clrEPRdy;
+    end
+    2'b10: begin
+      endPControlReg <= endP2ControlReg;
+      clrEP2Rdy <= clrEPRdy;
+    end
+    2'b11: begin
+      endPControlReg <= endP3ControlReg;
+      clrEP3Rdy <= clrEPRdy;
+    end
+  endcase  
+end      
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+  if (rst) begin
+    endP0NAKTransTypeReg <= 2'b00;
+    endP1NAKTransTypeReg <= 2'b00;
+    endP2NAKTransTypeReg <= 2'b00;
+    endP3NAKTransTypeReg <= 2'b00;
+    endP0TransTypeReg <= 2'b00;
+    endP1TransTypeReg <= 2'b00;
+    endP2TransTypeReg <= 2'b00;
+    endP3TransTypeReg <= 2'b00;
+    endP0StatusReg <= 4'h0;
+    endP1StatusReg <= 4'h0;
+    endP2StatusReg <= 4'h0;
+    endP3StatusReg <= 4'h0;
+  end
+  else begin
+    if (endPMuxErrorsWEn == 1'b1) begin
+      if (NAKSent == 1'b1) begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0NAKTransTypeReg <= transTypeNAK;
+            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; 
+          end
+          2'b01: begin
+            endP1NAKTransTypeReg <= transTypeNAK;
+            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; 
+          end
+          2'b10: begin
+            endP2NAKTransTypeReg <= transTypeNAK;
+            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; 
+          end
+          2'b11: begin
+            endP3NAKTransTypeReg <= transTypeNAK;
+            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; 
+          end
+        endcase
+      end
+      else begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0TransTypeReg <= transType;
+            endP0StatusReg <= endPStatusCombine; 
+          end
+          2'b01: begin
+            endP1TransTypeReg <= transType;
+            endP1StatusReg <= endPStatusCombine; 
+          end
+          2'b10: begin
+            endP2TransTypeReg <= transType;
+            endP2StatusReg <= endPStatusCombine; 
+          end
+          2'b11: begin
+            endP3TransTypeReg <= transType;
+            endP3StatusReg <= endPStatusCombine; 
+          end
+        endcase
+      end
+    end
+  end
+end
+        
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveDirectControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+I 160 0 2 Builtin InPort | 111543,239893 "" ""
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+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
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+L 178 179 0 TEXT "Labels" | 63352,247790 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,247790 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveRxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveRxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveRxStatusMonitor.v                                       ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      resetEventOut <= 1'b1;
+    else
+      resetEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.asf	(revision 264)
@@ -0,0 +1,251 @@
+VERSION=1.15
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FRAMES=ON
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIEReceiver\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 237 236 0 Builtin Entry | 86360,167640
+I 238 236 0 Builtin Exit | 129540,111760
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+A 255 194 16 TEXT "Actions" | 77086,121516 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend"
+A 252 204 16 TEXT "Actions" | 71150,119778 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend"
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+S 241 6 69652 ELLIPSE "Junction" | 55410,156008 3500 3500
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 243 242 0 Builtin Entry | 86360,167640
+I 244 242 0 Builtin Exit | 129540,111760
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+A 259 169 16 TEXT "Actions" | 77229,121214 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+A 258 183 16 TEXT "Actions" | 76648,132819 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+I 261 0 130 Builtin OutPort | 74654,253805 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(revision 264)
@@ -0,0 +1,394 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine.v                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSerialInterfaceEngine(
+  clk, rst,
+  //readUSBWireData
+  USBWireDataIn,
+  USBWireDataInTick,
+  //writeUSBWireData
+  USBWireDataOut,
+  USBWireCtrlOut,
+  USBWireDataOutTick,
+  //SIEReceiver
+  connectState,
+  //processRxBit
+  resumeDetected,
+  //processRxByte
+  RxCtrlOut, 
+  RxDataOutWEn, 
+  RxDataOut, 
+    //SIETransmitter
+  SIEPortCtrlIn,
+  SIEPortDataIn, 
+  SIEPortTxRdy, 
+  SIEPortWEn, 
+    //lineControlUpdate
+  fullSpeedPolarity,
+  fullSpeedBitRate,
+  noActivityTimeOut,
+  noActivityTimeOutEnable
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+output noActivityTimeOut;
+input noActivityTimeOutEnable;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut; 
+output RxDataOutWEn; 
+output [7:0] RxDataOut; 
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy; 
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut; 
+wire RxDataOutWEn; 
+wire [7:0] RxDataOut; 
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy; 
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En; 
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En; 
+wire [4:0] RxCRC5Result; 
+wire RxCRC5_8Bit; 
+wire [7:0] RxCRCData; 
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En; 
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En; 
+wire [4:0] TxCRC5Result; 
+wire TxCRC5_8Bit; 
+wire [7:0] TxCRCData; 
+wire TxRstCRC; 
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy; 
+wire processTxByteWEn; 
+
+wire SIEFsRate;
+wire TxFSRateFromSIETxToPrcTxByte;
+wire prcTxByteFSRate;
+wire FSRateFromArbiterToWire;
+
+wire RxWireActive;
+
+lineControlUpdate u_lineControlUpdate
+  (.fullSpeedPolarity(fullSpeedPolarity),
+  .fullSpeedBitRate(fullSpeedBitRate),
+  .JBit(JBit),
+  .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+  (
+  .RxWireDataIn(RxWireDataFromWireRx), 
+  .RxWireDataWEn(RxWireDataWEn), 
+  .clk(clk),
+  .connectState(connectState),
+  .rst(rst) );
+
+  
+processRxBit u_processRxBit
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .RxBitsIn(RxWireDataFromWireRx), 
+  .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxDataOut(RxDataFromPrcRxBitToPrcRxByte), 
+  .clk(clk), 
+  .processRxBitRdy(processRxBitRdy), 
+  .processRxBitsWEn(RxWireDataWEn), 
+  .processRxByteWEn(processRxByteWEn), 
+  .resumeDetected(resumeDetected), 
+  .rst(rst),
+  .processRxByteRdy(processRxByteRdy),
+  .RxWireActive(RxWireActive)
+  );
+  
+processRxByte u_processRxByte
+  (.CRC16En(RxCRC16En), 
+  .CRC16Result(RxCRC16Result), 
+  .CRC16UpdateRdy(RxCRC16UpdateRdy),
+  .CRC5En(RxCRC5En), 
+  .CRC5Result(RxCRC5Result), 
+  .CRC5_8Bit(RxCRC5_8Bit),
+  .CRC5UpdateRdy(RxCRC5UpdateRdy),
+  .CRCData(RxCRCData), 
+  .RxByteIn(RxDataFromPrcRxBitToPrcRxByte), 
+  .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataOut), 
+  .clk(clk), 
+  .processRxDataInWEn(processRxByteWEn), 
+  .rst(rst), 
+  .rstCRC(RxRstCRC),
+  .processRxByteRdy(processRxByteRdy) ); 
+  
+  
+updateCRC5 RxUpdateCRC5
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC5Result), 
+  .CRCEn(RxCRC5En), 
+  .CRC5_8BitIn(RxCRC5_8Bit), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 RxUpdateCRC16
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC16Result), 
+  .CRCEn(RxCRC16En), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+SIETransmitter u_SIETransmitter
+  (.CRC16En(TxCRC16En), 
+  .CRC16Result(TxCRC16Result), 
+  .CRC5En(TxCRC5En), 
+  .CRC5Result(TxCRC5Result), 
+  .CRC5_8Bit(TxCRC5_8Bit), 
+  .CRCData(TxCRCData),
+  .CRC5UpdateRdy(TxCRC5UpdateRdy),
+  .CRC16UpdateRdy(TxCRC16UpdateRdy),
+  .JBit(JBit), 
+  .KBit(KBit), 
+  .SIEPortCtrlIn(SIEPortCtrlIn),
+  .SIEPortDataIn(SIEPortDataIn), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEn), 
+  .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteOut(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(SIETxCtrl), 
+  .USBWireData(SIETxData), 
+  .USBWireGnt(SIETxGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(SIETxReq), 
+  .USBWireWEn(SIETxWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst), 
+  .rstCRC(TxRstCRC),
+  .USBWireFullSpeedRate(SIEFsRate),
+  .TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
+  .fullSpeedRateIn(fullSpeedBitRate)
+  );    
+
+updateCRC5 TxUpdateCRC5
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC5Result), 
+  .CRCEn(TxCRC5En), 
+  .CRC5_8BitIn(TxCRC5_8Bit), 
+  .dataIn(TxCRCData),
+  .ready(TxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 TxUpdateCRC16
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC16Result), 
+  .CRCEn(TxCRC16En), 
+  .dataIn(TxCRCData), 
+  .ready(TxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+
+processTxByte u_processTxByte
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteIn(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(prcTxByteCtrl), 
+  .USBWireData(prcTxByteData), 
+  .USBWireGnt(prcTxByteGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(prcTxByteReq), 
+  .USBWireWEn(prcTxByteWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst),
+  .USBWireFullSpeedRate(prcTxByteFSRate),
+  .TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
+  ); 
+  
+USBTxWireArbiter u_USBTxWireArbiter
+  (.SIETxCtrl(SIETxCtrl), 
+  .SIETxData(SIETxData), 
+  .SIETxGnt(SIETxGnt), 
+  .SIETxReq(SIETxReq), 
+  .SIETxWEn(SIETxWEn), 
+  .TxBits(TxBitsFromArbToWire), 
+  .TxCtl(TxCtrlFromArbToWire), 
+  .USBWireRdyIn(USBWireRdy), 
+  .USBWireRdyOut(USBWireReadyFromTxArb), 
+  .USBWireWEn(USBWireWEn),
+  .clk(clk), 
+  .prcTxByteCtrl(prcTxByteCtrl), 
+  .prcTxByteData(prcTxByteData), 
+  .prcTxByteGnt(prcTxByteGnt), 
+  .prcTxByteReq(prcTxByteReq), 
+  .prcTxByteWEn(prcTxByteWEn), 
+  .rst(rst),
+  .SIETxFSRate(SIEFsRate),
+  .prcTxByteFSRate(prcTxByteFSRate),
+  .TxFSRate(FSRateFromArbiterToWire)
+  ); 
+  
+writeUSBWireData u_writeUSBWireData
+  (.TxBitsIn(TxBitsFromArbToWire), 
+  .TxBitsOut(USBWireDataOut), 
+  .TxDataOutTick(USBWireDataOutTick),
+  .TxCtrlIn(TxCtrlFromArbToWire), 
+  .TxCtrlOut(USBWireCtrlOut), 
+  .USBWireRdy(USBWireRdy), 
+  .USBWireWEn(USBWireWEn),
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .fullSpeedRate(FSRateFromArbiterToWire), 
+  .clk(clk),
+  .rst(rst)
+   );  
+
+  
+  
+readUSBWireData u_readUSBWireData
+  (.RxBitsIn(USBWireDataIn), 
+  .RxDataInTick(USBWireDataInTick),
+  .RxBitsOut(RxWireDataFromWireRx), 
+  .SIERxRdyIn(processRxBitRdy), 
+  .SIERxWEn(RxWireDataWEn), 
+  .fullSpeedRate(fullSpeedBitRate), 
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .clk(clk),
+  .rst(rst),
+  .noActivityTimeOut(noActivityTimeOut),
+  .RxWireActive(RxWireActive),
+  .noActivityTimeOutEnable(noActivityTimeOutEnable)
+  );
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/USBSlaveControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/USBSlaveControlBI.v	(revision 264)
@@ -0,0 +1,527 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBSlaveControlBI.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////       
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+`include "usbSlaveControl_h.v"
+ 
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+  endP0TransTypeReg, endP0NAKTransTypeReg,
+  endP1TransTypeReg, endP1NAKTransTypeReg,
+  endP2TransTypeReg, endP2NAKTransTypeReg,
+  endP3TransTypeReg, endP3NAKTransTypeReg,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  EP0StatusReg,
+  EP1StatusReg,
+  EP2StatusReg,
+  EP3StatusReg,
+  SCAddrReg, frameNum,
+  connectStateIn,
+  SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+  slaveControlSelect,
+  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  SCGlobalEn
+  );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg; 
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg; 
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg; 
+input [1:0] endP3NAKTransTypeReg;
+output [4:0] endP0ControlReg;
+output [4:0] endP1ControlReg;
+output [4:0] endP2ControlReg;
+output [4:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg; 
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg; 
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg; 
+wire [1:0] endP3NAKTransTypeReg;
+reg [4:0] endP0ControlReg;
+reg [4:0] endP1ControlReg;
+reg [4:0] endP2ControlReg;
+reg [4:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0IsoEn;
+reg EP1IsoEn;
+reg EP2IsoEn;
+reg EP3IsoEn;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [4:0] endP0ControlRegSTB;
+reg [4:0] endP1ControlRegSTB;
+reg [4:0] endP2ControlRegSTB;
+reg [4:0] endP3ControlRegSTB;
+reg NAKSentInSTB;
+reg SOFRxedInSTB;
+reg resetEventInSTB;
+reg resumeIntInSTB;
+reg transDoneInSTB;
+reg clrEP0ReadySTB;
+reg clrEP1ReadySTB;
+reg clrEP2ReadySTB;
+reg clrEP3ReadySTB;
+reg SCGlobalEnSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB; 
+reg fullSpeedRateSTB;
+reg [7:0] EP0StatusRegSTB;
+reg [7:0] EP1StatusRegSTB;
+reg [7:0] EP2StatusRegSTB;
+reg [7:0] EP3StatusRegSTB;
+reg [1:0] endP0TransTypeRegSTB;
+reg [1:0] endP0NAKTransTypeRegSTB;
+reg [1:0] endP1TransTypeRegSTB; 
+reg [1:0] endP1NAKTransTypeRegSTB;
+reg [1:0] endP2TransTypeRegSTB; 
+reg [1:0] endP2NAKTransTypeRegSTB;
+reg [1:0] endP3TransTypeRegSTB; 
+reg [1:0] endP3NAKTransTypeRegSTB;
+reg [10:0] frameNumSTB;
+
+  
+//sync write demux
+always @(posedge busClk)
+begin   
+  if (rstSyncToBusClk == 1'b1) begin
+    EP0IsoEn <= 1'b0;
+    EP0SendStall <= 1'b0;
+    EP0DataSequence <= 1'b0;
+    EP0Enable <= 1'b0;
+    EP1IsoEn <= 1'b0;
+    EP1SendStall <= 1'b0;
+    EP1DataSequence <= 1'b0;
+    EP1Enable <= 1'b0;
+    EP2IsoEn <= 1'b0;
+    EP2SendStall <= 1'b0;
+    EP2DataSequence <= 1'b0;
+    EP2Enable <= 1'b0;
+    EP3IsoEn <= 1'b0;
+    EP3SendStall <= 1'b0;
+    EP3DataSequence <= 1'b0;
+    EP3Enable <= 1'b0;
+    SCControlReg <= 6'h00;
+    SCAddrReg <= 7'h00;
+    interruptMaskReg <= 5'h00;
+  end
+  else begin
+    clrNAKReq <= 1'b0;
+    clrSOFReq <= 1'b0;
+    clrResetReq <= 1'b0;
+    clrResInReq <= 1'b0;
+    clrTransDoneReq <= 1'b0;
+    EP0SetReady <= 1'b0;
+    EP1SetReady <= 1'b0;
+    EP2SetReady <= 1'b0;
+    EP3SetReady <= 1'b0;
+    if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+    begin
+      case (address)
+        `EP0_CTRL_REG : begin
+          EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP1_CTRL_REG : begin
+          EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP2_CTRL_REG : begin
+          EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP3_CTRL_REG : begin
+          EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+        `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+        `SC_INTERRUPT_STATUS_REG : begin
+          clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
+          clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
+          clrResetReq <= dataIn[`RESET_EVENT_BIT];
+          clrResInReq <= dataIn[`RESUME_INT_BIT];
+          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+        end
+        `SC_INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[4:0];
+      endcase
+    end
+  end
+end
+
+//interrupt control 
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    NAKSentInt <= 1'b0;
+    SOFRxedInt <= 1'b0;
+    resetEventInt <= 1'b0;
+    resumeInt <= 1'b0;
+    transDoneInt <= 1'b0;
+  end
+  else begin
+    if (NAKSentInSTB == 1'b1)
+      NAKSentInt <= 1'b1;
+    else if (clrNAKReq == 1'b1)
+      NAKSentInt <= 1'b0; 
+    
+    if (SOFRxedInSTB == 1'b1)
+      SOFRxedInt <= 1'b1;
+    else if (clrSOFReq == 1'b1)
+      SOFRxedInt <= 1'b0;
+    
+    if (resetEventInSTB == 1'b1)
+      resetEventInt <= 1'b1;
+    else if (clrResetReq == 1'b1)
+      resetEventInt <= 1'b0;
+    
+    if (resumeIntInSTB == 1'b1)
+      resumeInt <= 1'b1;
+    else if (clrResInReq == 1'b1)
+      resumeInt <= 1'b0;  
+
+    if (transDoneInSTB == 1'b1)
+      transDoneInt <= 1'b1;
+    else if (clrTransDoneReq == 1'b1)
+      transDoneInt <= 1'b0;
+  end
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end  
+
+//end point ready, set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'EP0SetReady' etc must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the ready is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'EP0Ready' and sampling of related control signals.always @(posedge busClk)
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    EP0Ready <= 1'b0;
+    EP1Ready <= 1'b0;
+    EP2Ready <= 1'b0;
+    EP3Ready <= 1'b0;
+  end
+  else begin
+    if (EP0SetReady == 1'b1)
+      EP0Ready <= 1'b1;
+    else if (clrEP0ReadySTB == 1'b1)
+      EP0Ready <= 1'b0;
+    
+    if (EP1SetReady == 1'b1)
+      EP1Ready <= 1'b1;
+    else if (clrEP1ReadySTB == 1'b1)
+      EP1Ready <= 1'b0;
+    
+    if (EP2SetReady == 1'b1)
+      EP2Ready <= 1'b1;
+    else if (clrEP2ReadySTB == 1'b1)
+      EP2Ready <= 1'b0;
+    
+    if (EP3SetReady == 1'b1)
+      EP3Ready <= 1'b1;
+    else if (clrEP3ReadySTB == 1'b1)
+      EP3Ready <= 1'b0;
+  end
+end  
+  
+//break out control signals
+always @(SCControlReg) begin
+  SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+  TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+  LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+  fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals 
+always @(EP0IsoEn or EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1IsoEn or EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2IsoEn or EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3IsoEn or EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable) 
+begin
+  endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+  endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+  endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+  endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+      
+      
+// async read mux
+// FIX ME
+// Not sure why 'EP0SendStall' etc are in sensitivity list. May be related to
+// some translation bug
+always @(address or
+  EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+  EP0StatusRegSTB or EP1StatusRegSTB or EP2StatusRegSTB or EP3StatusRegSTB or
+  endP0ControlRegSTB or endP1ControlRegSTB or endP2ControlRegSTB or endP3ControlRegSTB or
+  endP0NAKTransTypeRegSTB or endP1NAKTransTypeRegSTB or endP2NAKTransTypeRegSTB or endP3NAKTransTypeRegSTB or 
+  endP0TransTypeRegSTB or endP1TransTypeRegSTB or endP2TransTypeRegSTB or endP3TransTypeRegSTB or
+  SCControlReg or connectStateIn or
+  NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or SCAddrReg or frameNumSTB)
+begin
+  case (address)
+      `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
+      `EP0_STS_REG : dataOut <= EP0StatusRegSTB;
+      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
+      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
+      `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
+      `EP1_STS_REG :  dataOut <= EP1StatusRegSTB;
+      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
+      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
+      `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
+      `EP2_STS_REG :  dataOut <= EP2StatusRegSTB;
+      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
+      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
+      `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
+      `EP3_STS_REG :  dataOut <= EP3StatusRegSTB;
+      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
+      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
+      `SC_CONTROL_REG : dataOut <= SCControlReg;
+      `SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn}; 
+      `SC_INTERRUPT_STATUS_REG :  dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+      `SC_INTERRUPT_MASK_REG  : dataOut <= {3'b000, interruptMaskReg};
+      `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+      `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
+      `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+//re-sync from busClk to usbClk. 
+always @(posedge usbClk) begin
+  endP0ControlReg <= endP0ControlRegSTB;
+  endP1ControlReg <= endP1ControlRegSTB;
+  endP2ControlReg <= endP2ControlRegSTB;
+  endP3ControlReg <= endP3ControlRegSTB;
+  SCGlobalEn <= SCGlobalEnSTB;
+  TxLineState <= TxLineStateSTB;
+  LineDirectControlEn <= LineDirectControlEnSTB;
+  fullSpeedPol <= fullSpeedPolSTB; 
+  fullSpeedRate <= fullSpeedRateSTB;
+end
+
+//re-sync from usbClk to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc are only asserted 
+//for one 'usbClk' tick, busClk freq must be greater than or equal to usbClk freq
+always @(posedge busClk) begin
+  NAKSentInSTB <= NAKSentIn;
+  SOFRxedInSTB <= SOFRxedIn;
+  resetEventInSTB <= resetEventIn;
+  resumeIntInSTB <= resumeIntIn;
+  transDoneInSTB <= transDoneIn;
+  clrEP0ReadySTB <= clrEP0Ready;
+  clrEP1ReadySTB <= clrEP1Ready;
+  clrEP2ReadySTB <= clrEP2Ready;
+  clrEP3ReadySTB <= clrEP3Ready;
+  EP0StatusRegSTB <= EP0StatusReg;
+  EP1StatusRegSTB <= EP1StatusReg;
+  EP2StatusRegSTB <= EP2StatusReg;
+  EP3StatusRegSTB <= EP3StatusReg;
+  endP0TransTypeRegSTB <= endP0TransTypeReg;
+  endP1TransTypeRegSTB <= endP1TransTypeReg;
+  endP2TransTypeRegSTB <= endP2TransTypeReg;
+  endP3TransTypeRegSTB <= endP3TransTypeReg;
+  endP0NAKTransTypeRegSTB <= endP0NAKTransTypeReg;
+  endP1NAKTransTypeRegSTB <= endP1NAKTransTypeReg;
+  endP2NAKTransTypeRegSTB <= endP2NAKTransTypeReg;
+  endP3NAKTransTypeRegSTB <= endP3NAKTransTypeReg;
+  frameNumSTB <= frameNum;
+end
+
+endmodule

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.v	(revision 264)
@@ -0,0 +1,197 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SCTxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   clk;
+input   [7:0]directCntlCntl;
+input   [7:0]directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   SCTxPortRdyIn;
+input   [7:0]sendPacketCntl;
+input   [7:0]sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  directCntlGnt;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortRdyOut;
+output  SCTxPortWEnable;
+output  sendPacketGnt;
+
+wire    clk;
+wire    [7:0]directCntlCntl;
+wire    [7:0]directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortRdyIn;
+reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg     SCTxPortWEnable, next_SCTxPortWEnable;
+wire    [7:0]sendPacketCntl;
+wire    [7:0]sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0]CurrState_SCTxArb, NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+directCntlWEn or directCntlData or directCntlCntl or
+directCntlWEn or directCntlData or directCntlCntl or
+sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+begin
+SCTxPortWEnable <= directCntlWEn;
+SCTxPortData <= directCntlData;
+SCTxPortCntl <= directCntlCntl;
+end
+else
+begin
+SCTxPortWEnable <= sendPacketWEn;
+SCTxPortData <= sendPacketData;
+SCTxPortCntl <= sendPacketCntl;
+end
+end
+
+
+// Machine: SCTxArb
+
+// NextState logic (combinatorial)
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin
+  NextState_SCTxArb <= CurrState_SCTxArb;
+  // Set default values for outputs and signals
+  next_sendPacketGnt <= sendPacketGnt;
+  next_muxDCEn <= muxDCEn;
+  next_directCntlGnt <= directCntlGnt;
+  case (CurrState_SCTxArb)  // synopsys parallel_case full_case
+    `SARB1_WAIT_REQ:
+    begin
+      if (sendPacketReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxDCEn <= 1'b0;
+      end
+      else if (directCntlReq == 1'b1)
+      begin
+        NextState_SCTxArb <= `SARB_DC;
+        next_directCntlGnt <= 1'b1;
+        next_muxDCEn <= 1'b1;
+      end
+    end
+    `SARB_SEND_PACKET:
+    begin
+      if (sendPacketReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    end
+    `SARB_DC:
+    begin
+      if (directCntlReq == 1'b0)
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    end
+    `START_SARB:
+    begin
+      NextState_SCTxArb <= `SARB1_WAIT_REQ;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SCTxArb <= `START_SARB;
+  else
+    CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketGnt <= 1'b0;
+    directCntlGnt <= 1'b0;
+    muxDCEn <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketGnt <= next_sendPacketGnt;
+    directCntlGnt <= next_directCntlGnt;
+    muxDCEn <= next_muxDCEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.v	(revision 264)
@@ -0,0 +1,390 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveGetPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, bitStuffError, clk, CRCError, dataSequence, endPointReady, getPacketEn, rst, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RxPID, RXStreamStatusIn, RXTimeOut, SIERxTimeOut, SIERxTimeOutEn);
+input   clk;
+input   endPointReady;
+input   getPacketEn;
+input   rst;
+input   [7:0]RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0]RXStreamStatusIn;
+input   SIERxTimeOut;    // Single cycle pulse
+output  ACKRxed;
+output  bitStuffError;
+output  CRCError;
+output  dataSequence;
+output  [7:0]RXFifoData;
+output  RXFifoWEn;
+output  RXOverflow;
+output  RXPacketRdy;
+output  [3:0]RxPID;
+output  RXTimeOut;
+output  SIERxTimeOutEn;
+
+reg     ACKRxed, next_ACKRxed;
+reg     bitStuffError, next_bitStuffError;
+wire    clk;
+reg     CRCError, next_CRCError;
+reg     dataSequence, next_dataSequence;
+wire    endPointReady;
+wire    getPacketEn;
+wire    rst;
+wire    [7:0]RXDataIn;
+wire    RXDataValid;
+reg     [7:0]RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXOverflow, next_RXOverflow;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [3:0]RxPID, next_RxPID;
+wire    [7:0]RXStreamStatusIn;
+reg     RXTimeOut, next_RXTimeOut;
+wire    SIERxTimeOut;
+reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
+
+// diagram signals declarations
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
+
+reg [4:0]CurrState_slvGetPkt, NextState_slvGetPkt;
+
+
+// Machine: slvGetPkt
+
+// NextState logic (combinatorial)
+always @ (RXByte or RXDataValid or RXDataIn or RXStreamStatusIn or RXStreamStatus or endPointReady or RXFifoFull or RXByteOldest or RXByteOld or SIERxTimeOut or getPacketEn or RXOverflow or ACKRxed or CRCError or bitStuffError or dataSequence or RXFifoWEn or RXFifoData or RXPacketRdy or RXTimeOut or RxPID or SIERxTimeOutEn or CurrState_slvGetPkt)
+begin
+  NextState_slvGetPkt <= CurrState_slvGetPkt;
+  // Set default values for outputs and signals
+  next_RXOverflow <= RXOverflow;
+  next_ACKRxed <= ACKRxed;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RXByteOldest <= RXByteOldest;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_dataSequence <= dataSequence;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXTimeOut <= RXTimeOut;
+  next_RxPID <= RxPID;
+  next_SIERxTimeOutEn <= SIERxTimeOutEn;
+  case (CurrState_slvGetPkt)  // synopsys parallel_case full_case
+    `START_GP:
+    begin
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b1;
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (SIERxTimeOut == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `CHK_PKT_START:
+    begin
+      if (RXStreamStatus == `RX_PACKET_START)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b0;
+      if (getPacketEn == 1'b1)
+      begin
+        NextState_slvGetPkt <= `WAIT_PKT;
+      end
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+    begin
+      if (RXByte[1:0] == `HANDSHAKE)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_HS;
+      end
+      else if (RXByte[1:0] == `DATA)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+      end
+    end
+    `PROC_PKT_HS:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    end
+    `PROC_PKT_DATA_W_D1:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D1:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D2:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_slvGetPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_W_D3:
+    begin
+      if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_CHK_D3:
+    begin
+      if (RXStreamStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+    begin
+      if (endPointReady == 1'b0)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
+      end
+      else if (RXFifoFull == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+      end
+      else if (RXDataValid == 1'b1)
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    end
+    `PROC_PKT_DATA_LOOP_EP_N_RDY:    // Discard data
+    begin
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvGetPkt <= `START_GP;
+  else
+    CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    RXOverflow <= 1'b0;
+    ACKRxed <= 1'b0;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    dataSequence <= 1'b0;
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RXTimeOut <= 1'b0;
+    RxPID <= 4'h0;
+    SIERxTimeOutEn <= 1'b0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXByteOldest <= 8'h00;
+    RXByteOld <= 8'h00;
+  end
+  else 
+  begin
+    RXOverflow <= next_RXOverflow;
+    ACKRxed <= next_ACKRxed;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    dataSequence <= next_dataSequence;
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RXPacketRdy <= next_RXPacketRdy;
+    RXTimeOut <= next_RXTimeOut;
+    RxPID <= next_RxPID;
+    SIERxTimeOutEn <= next_SIERxTimeOutEn;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXByteOldest <= next_RXByteOldest;
+    RXByteOld <= next_RXByteOld;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlave.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlave.v	(revision 264)
@@ -0,0 +1,549 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlave.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostSlave(
+  clk_i,
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  usbClk,
+  hostSOFSentIntOut, 
+  hostConnEventIntOut, 
+  hostResumeIntOut, 
+  hostTransDoneIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+  USBWireDataIn,
+  USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+  USBWireCtrlOut,
+  USBFullSpeed
+   );
+  parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+  parameter HOST_FIFO_ADDR_WIDTH = 6;   
+  parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+  parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+  parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+  parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk_i;               //Wishbone bus clock. Maximum 5*usbClk=240MHz
+input rst_i;               //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
+input [7:0] address_i;     //Wishbone bus address in
+input [7:0] data_i;        //Wishbone bus data in
+output [7:0] data_o;       //Wishbone bus data out
+input we_i;                //Wishbone bus write enable in
+input strobe_i;            //Wishbone bus strobe in
+output ack_o;              //Wishbone bus acknowledge out
+input usbClk;              //usb clock. 48Mhz +/-0.25%
+output hostSOFSentIntOut; 
+output hostConnEventIntOut; 
+output hostResumeIntOut; 
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire we_i; 
+wire strobe_i;
+wire ack_o;
+wire usbClk;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel; 
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE; 
+wire [7:0] hostTxFifoData; 
+wire hostTxFifoEmpty;
+wire hostRxFifoWE; 
+wire [7:0] hostRxFifoData; 
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost; 
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+
+assign USBFullSpeed = fullSpeedBitRateToSIE;  
+
+usbHostControl u_usbHostControl(
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .TxFifoRE(hostTxFifoRE), 
+  .TxFifoData(hostTxFifoData), 
+  .TxFifoEmpty(hostTxFifoEmpty),
+  .RxFifoWE(hostRxFifoWE), 
+  .RxFifoData(hostRxFifoData), 
+  .RxFifoFull(hostRxFifoFull),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut),
+  .fullSpeedRate(fullSpeedBitRateFromHost), 
+  .fullSpeedPol(fullSpeedPolarityFromHost),
+  .HCTxPortEn(SIEPortWEnFromHost), 
+  .HCTxPortRdy(SIEPortTxRdy),
+  .HCTxPortData(SIEPortDataInFromHost), 
+  .HCTxPortCtrl(SIEPortCtrlInFromHost),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[3:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostControl), 
+  .busWriteEn(we_i),
+  .busStrobe_i(strobe_i),
+  .SOFSentIntOut(hostSOFSentIntOut), 
+  .connEventIntOut(hostConnEventIntOut), 
+  .resumeIntOut(hostResumeIntOut), 
+  .transDoneIntOut(hostTransDoneIntOut),
+  .hostControlSelect(hostControlSel) );
+  
+
+usbSlaveControl u_usbSlaveControl(
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut), 
+  .RxFifoData(slaveRxFifoData),
+  .fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+  .SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+  .SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(we_i),
+  .busStrobe_i(strobe_i),
+  .SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(we_i), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk_i), 
+  .rst(rstSyncToBusClk),
+  .hostControlSel(hostControlSel), 
+  .hostRxFifoSel(hostRxFifoSel), 
+  .hostTxFifoSel(hostTxFifoSel),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(dataFromHostControl),
+  .dataFromHostRxFifo(dataFromHostRxFifo),
+  .dataFromHostTxFifo(dataFromHostTxFifo),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+   );
+
+hostSlaveMux u_hostSlaveMux(
+  .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+  .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+  .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+  .SIEPortDataInToSIE(SIEPortDataInToSIE), 
+  .SIEPortDataInFromHost(SIEPortDataInFromHost), 
+  .SIEPortDataInFromSlave(SIEPortDataInFromSlave), 
+  .SIEPortWEnToSIE(SIEPortWEnToSIE), 
+  .SIEPortWEnFromHost(SIEPortWEnFromHost), 
+  .SIEPortWEnFromSlave(SIEPortWEnFromSlave), 
+  .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+  .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+  .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+  .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+  .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+  .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux),
+  .address(address_i[0]),
+  .writeEn(we_i),
+  .strobe_i(strobe_i),
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .rstFromWire(rst_i),
+  .rstSyncToBusClkOut(rstSyncToBusClk),
+  .rstSyncToUsbClkOut(rstSyncToUsbClk)
+);
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .connectState(connectState),
+  .resumeDetected(resumeDetected),
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataFromSIE), 
+  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+  .SIEPortDataIn(SIEPortDataInToSIE), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEnToSIE), 
+  .fullSpeedPolarity(fullSpeedPolarityToSIE),
+  .fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(hostTxFifoRE), 
+  .fifoEmpty(hostTxFifoEmpty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostTxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostTxFifo),
+  .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i),
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(hostRxFifoWE), 
+  .fifoFull(hostRxFifoFull),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostRxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostRxFifo),
+  .fifoDataIn(hostRxFifoData)  );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i),
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_00/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_00/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_01_00/doc/html/src/hostController/USBHostControlBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_00/doc/html/src/hostController/USBHostControlBI.v/index.htm	(revision 264)
@@ -0,0 +1,276 @@
+<html>
+<head>
+<title>USBHostControlBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBHostControlBI.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+ 
+<span id=t_kwd>module</span> <span id=t_idt>USBHostControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>SOFSentIntOut</span>, <span id=t_idt>connEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>TxTransTypeReg</span>, <span id=t_idt>TxSOFEnableReg</span>,
+  <span id=t_idt>TxAddrReg</span>, <span id=t_idt>TxEndPReg</span>, <span id=t_idt>frameNumIn</span>, 
+  <span id=t_idt>RxPktStatusIn</span>, <span id=t_idt>RxPIDIn</span>,
+  <span id=t_idt>connectStateIn</span>,
+  <span id=t_idt>SOFSentIn</span>, <span id=t_idt>connEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>,
+  <span id=t_idt>hostControlSelect</span>,
+  <span id=t_idt>clrTransReq</span>,
+  <span id=t_idt>preambleEn</span>,
+  <span id=t_idt>SOFSync</span>,
+  <span id=t_idt>TxLineState</span>,
+  <span id=t_idt>LineDirectControlEn</span>,
+  <span id=t_idt>fullSpeedPol</span>, 
+  <span id=t_idt>fullSpeedRate</span>,
+  <span id=t_idt>transReq</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>output</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transReq</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transReq</span>;
+
+<span id=t_com>//internal wire and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineControlReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrConnEvtReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>setTransReq</span>;
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResInReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>setTransReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>hostControlSelect</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>preambleEn</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>SOFSync</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>setTransReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>TxTransTypeReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>TxLineControlReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>TxSOFEnableReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>TxAddrReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>TxEndPReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_kwd>begin</span>
+        <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>clrResInReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>interruptMaskReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+   <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//interrupt control</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>SOFSentIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>connEventIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrConnEvtReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b0</span>;  
+
+  <span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//mask interrupts</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSentInt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>transDoneIntOut</span> &lt;= <span id=t_idt>transDoneInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>];
+  <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_idt>resumeInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>];
+  <span id=t_idt>connEventIntOut</span> &lt;= <span id=t_idt>connEventInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>CONNECTION_EVENT_BIT</span>];
+  <span id=t_idt>SOFSentIntOut</span> &lt;= <span id=t_idt>SOFSentInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_SENT_BIT</span>];
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//transaction request set/clear</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>setTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//break out control signals</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>TxLineState</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>TX_LINE_STATE_LSBIT</span>];
+  <span id=t_idt>LineDirectControlEn</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>DIRECT_CONTROL_BIT</span>];
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span>]; 
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span>];
+<span id=t_kwd>end</span>
+  
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxSOFEnableReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndPReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNumIn</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SOFSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span>
+  <span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>RxPktStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxPIDIn</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>preambleEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSync</span> <span id=t_kwd>or</span> <span id=t_idt>transReq</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>preambleEn</span>, <span id=t_idt>SOFSync</span>, <span id=t_idt>transReq</span>} ;
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>TxTransTypeReg</span>};
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>TxLineControlReg</span>};
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>TxSOFEnableReg</span>};
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxAddrReg</span>};
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>TxEndPReg</span>};
+     `<span id=t_idt>FRAME_NUM_MSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>frameNumIn</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>];
+     `<span id=t_idt>FRAME_NUM_LSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNumIn</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]};
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>SOFSentInt</span>, <span id=t_idt>connEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>};
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>interruptMaskReg</span>};
+     `<span id=t_idt>RX_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>RxPktStatusIn</span>;
+     `<span id=t_idt>RX_PID_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'b0000</span>, <span id=t_idt>RxPIDIn</span>};
+     `<span id=t_idt>RX_CONNECT_STATE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>};
+      <span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_01_00/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifo.v	(revision 264)
@@ -0,0 +1,132 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo write access via bus interface, fifo read access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module TxFifo(
+  busClk,
+  usbClk,
+  rstSyncToBusClk, 
+  rstSyncToUsbClk, 
+  fifoREn, 
+  fifoEmpty,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn,
+  busDataOut,
+  fifoDataOut ); 
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input busClk; 
+input usbClk; 
+input rstSyncToBusClk; 
+input rstSyncToUsbClk; 
+input fifoREn; 
+output fifoEmpty;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+output [7:0] fifoDataOut;
+
+wire busClk; 
+wire usbClk; 
+wire rstSyncToBusClk; 
+wire rstSyncToUsbClk; 
+wire fifoREn; 
+wire fifoEmpty;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .wrClk(busClk), 
+  .rdClk(usbClk), 
+  .rstSyncToWrClk(rstSyncToBusClk), 
+  .rstSyncToRdClk(rstSyncToUsbClk), 
+  .dataIn(busDataIn), 
+  .dataOut(fifoDataOut), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmptySyncToWrClk(forceEmptySyncToBusClk), 
+  .forceEmptySyncToRdClk(forceEmptySyncToUsbClk), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+TxfifoBI u_TxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .fifoSelect(busFifoSelect),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut), 
+  .fifoWEn(fifoWEn),
+  .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+  .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/busInterface/wishBoneBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/busInterface/wishBoneBI.v	(revision 264)
@@ -0,0 +1,246 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBI.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "wishBoneBus_h.v"
+
+ 
+module wishBoneBI (
+  address, dataIn, dataOut, writeEn, 
+  strobe_i,
+  ack_o,
+  clk, rst,
+  hostControlSel, 
+  hostRxFifoSel, hostTxFifoSel,
+  slaveControlSel,
+  slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, 
+  slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, 
+  hostSlaveMuxSel,
+  dataFromHostControl,
+  dataFromHostRxFifo,
+  dataFromHostTxFifo,
+  dataFromSlaveControl,
+  dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+  dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+  dataFromHostSlaveMux
+   );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+  dataFromHostControl or
+  dataFromHostRxFifo or
+  dataFromHostTxFifo or
+  dataFromSlaveControl or
+  dataFromEP0RxFifo or 
+  dataFromEP1RxFifo or
+  dataFromEP2RxFifo or
+  dataFromEP3RxFifo or
+  dataFromHostSlaveMux or 
+  dataFromEP0TxFifo or
+  dataFromEP1TxFifo or
+  dataFromEP2TxFifo or
+  dataFromEP3TxFifo)
+begin
+  hostControlSel <= 1'b0;
+  hostRxFifoSel <= 1'b0;
+  hostTxFifoSel <= 1'b0;
+  slaveControlSel <= 1'b0;
+  slaveEP0RxFifoSel <= 1'b0;
+  slaveEP0TxFifoSel <= 1'b0;
+  slaveEP1RxFifoSel <= 1'b0;
+  slaveEP1TxFifoSel <= 1'b0;
+  slaveEP2RxFifoSel <= 1'b0;
+  slaveEP2TxFifoSel <= 1'b0;
+  slaveEP3RxFifoSel <= 1'b0;
+  slaveEP3TxFifoSel <= 1'b0;
+  hostSlaveMuxSel <= 1'b0;
+  case (address & `ADDRESS_DECODE_MASK)
+    `HCREG_BASE : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HCREG_BASE_PLUS_0X10 : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HOST_RX_FIFO_BASE : begin
+      hostRxFifoSel <= 1'b1;
+      dataOut <= dataFromHostRxFifo;
+    end
+    `HOST_TX_FIFO_BASE : begin
+      hostTxFifoSel <= 1'b1;
+      dataOut <= dataFromHostTxFifo;
+    end
+    `SCREG_BASE : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `SCREG_BASE_PLUS_0X10 : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `EP0_RX_FIFO_BASE : begin
+      slaveEP0RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0RxFifo;
+    end
+    `EP0_TX_FIFO_BASE : begin
+      slaveEP0TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0TxFifo;
+    end
+    `EP1_RX_FIFO_BASE : begin
+      slaveEP1RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1RxFifo;
+    end
+    `EP1_TX_FIFO_BASE : begin
+      slaveEP1TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1TxFifo;
+    end
+    `EP2_RX_FIFO_BASE : begin
+      slaveEP2RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2RxFifo;
+    end
+    `EP2_TX_FIFO_BASE : begin
+      slaveEP2TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2TxFifo;
+    end
+    `EP3_RX_FIFO_BASE : begin
+      slaveEP3RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3RxFifo;
+    end
+    `EP3_TX_FIFO_BASE : begin
+      slaveEP3TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3TxFifo;
+    end
+    `HOST_SLAVE_CONTROL_BASE : begin
+      hostSlaveMuxSel <= 1'b1; 
+      dataOut <= dataFromHostSlaveMux;
+    end
+    default: 
+      dataOut <= 8'h00;
+  endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+  ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+  ack_immediate <= strobe_i;
+end 
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+  if (writeEn == 1'b0 &&
+      (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+  begin
+    ack_o <= ack_delayed;
+  end
+  else
+  begin
+    ack_o <= ack_immediate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.asf	(revision 264)
@@ -0,0 +1,289 @@
+VERSION=1.15
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FRAMES=ON
+FREEOID=261
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// getpacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
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+OBJECTS
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+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176799,72082 177196,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177616,25344 184028,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+I 207 0 128 Builtin OutPort | 77404,226912 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,180996 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nSIERxTimeOutEn <= 1'b1;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;\nSIERxTimeOutEn <= 1'b0;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n  RXPktStatus = { \n  dataSequence, ACKRxed, \n  stallRxed, NAKRxed,\n  RXTimeOut, RXOverflow, \n  bitStuffError, CRCError};\nend"
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 260 0 2 Builtin OutPort | 77376,232444 "" ""
+L 259 260 0 TEXT "Labels" | 83376,232444 1 0 0 "SIERxTimeOutEn"
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+                                           57686,214631 75382,223396 84426,228258
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.asf	(revision 264)
@@ -0,0 +1,304 @@
+VERSION=1.15
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FRAMES=ON
+FREEOID=455
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hostController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 47
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 49
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 51
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+A 302 83 16 TEXT "Actions" | 127391,163104 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "clearTXReq <= 1'b0;\ntransDone <= 1'b0;\n//now wait for 'transReq' to clear"
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+                                        170250,145750 137550,145450 128737,144962 119925,144475\
+                                        117963,142662 116688,141837
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+I 56 52 0 Builtin Exit | 155694,46048
+I 55 52 0 Builtin Entry | 88756,239499
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+W 332 66 0 220 435 BEZIER "Transitions" | 82899,126626 83372,118876 55983,116868 40261,109385
+C 333 332 0 TEXT "Conditions" | 54763,123556 1 0 0 "sendPacketRdy == 1'b1"
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+                                          110726,37400 115182,37514 117348,37514
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+                                          129080,35838 133536,35952 135702,35952
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+I 365 73 0 Builtin Exit | 138662,35952
+I 366 73 0 Builtin Entry | 66816,246531
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+W 371 59 3 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+                                          40160,89849 37728,77233 37462,69633 37196,62033\
+                                          38564,44249 44378,36953 50192,29657 72080,18257\
+                                          79528,15331 86976,12405 94012,13028 97964,12876
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+I 96 6 0 Builtin Reset | 67359,192312
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+I 411 59 0 Builtin Exit | 100924,12876
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+                                          134254,207065 123583,209376 117848,210301
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+C 444 320 0 TEXT "Conditions" | 127768,183900 1 0 0 "sendPacketRdy == 1'b1"
+C 442 441 0 TEXT "Conditions" | 70632,78432 1 0 0 "isoEn == 1'b1"
+W 441 59 1 152 411 BEZIER "Transitions" | 80207,97867 74663,87703 63240,68436 60930,60120\
+                                          58620,51804 60468,38868 64038,33660 67608,28452\
+                                          80040,20556 84492,18330 88944,16104 95212,13380\
+                                          97900,12876
+W 440 66 2 435 216 BEZIER "Transitions" | 37283,96930 37450,86034 36933,64502 39250,56716\
+                                          41567,48930 50502,39578 58559,36864 66617,34151\
+                                          89914,32647 97658,32793 105403,32939 113545,36471\
+                                          117386,37514
+C 439 436 0 TEXT "Conditions" | 45200,98446 1 0 0 "isoEn == 1'b0"
+A 437 436 16 TEXT "Actions" | 45964,81812 1 0 0 "getPacketREn <= 1'b1;"
+W 436 66 1 435 331 BEZIER "Transitions" | 43135,99848 51564,83991 80050,72911 89986,72452
+S 435 66 147456 ELLIPSE "States" | 37700,103412 6500 6500
+L 434 435 0 TEXT "State Labels" | 37700,103412 1 0 0 "CHK_ISO\n/32/"
+I 433 0 2 Builtin InPort | 150555,227440 "" ""
+L 432 433 0 TEXT "Labels" | 156555,227440 1 0 0 "isoEn"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+L 445 446 0 TEXT "State Labels" | 91983,29847 1 0 0 "DEL1\n/33/"
+S 446 6 151552 ELLIPSE "States" | 91983,29847 6500 6500
+L 447 448 0 TEXT "State Labels" | 71118,38835 1 0 0 "DEL2\n/34/"
+S 448 6 155648 ELLIPSE "States" | 71118,38835 6500 6500
+W 451 6 0 294 446 BEZIER "Transitions" | 113064,28940 108490,29421 103055,29490 98481,29971
+W 452 6 0 446 448 BEZIER "Transitions" | 86012,32413 83123,33616 79949,35000 77060,36203
+W 454 6 0 448 41 BEZIER "Transitions" | 67046,43901 63355,51524 38215,83856 36770,94047\
+                                        35326,104238 36932,129759 42870,138987 48808,148215\
+                                        70958,159612 79745,162701 88532,165790 99731,166612\
+                                        106231,167093
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+I 215 66 0 Builtin Entry | 50996,240683
+I 216 66 0 Builtin Exit | 120308,37514
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.v	(revision 264)
@@ -0,0 +1,372 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, rst, sendPacketRdy, sendPacketWEn, TxAddr, TxEndP);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   fullSpeedPolarity;
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   [3:0]PID;
+input   rst;
+input   sendPacketWEn;
+input   [6:0]TxAddr;
+input   [3:0]TxEndP;
+output  fifoReadEn;
+output  [10:0]frameNum;
+output  [7:0]HCTxPortCntl;
+output  [7:0]HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+reg     [10:0]frameNum, next_frameNum;
+wire    fullSpeedPolarity;
+reg     [7:0]HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0]HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    [3:0]PID;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+wire    [6:0]TxAddr;
+wire    [3:0]TxEndP;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+`define LS_EOP_WAIT_RDY 5'b10101
+`define LS_EOP_FIN 5'b10110
+
+reg [4:0]CurrState_sndPkt, NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: sndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or HCTxPortGnt or fullSpeedPolarity or HCTxPortRdy or PIDNotPID or PID or TxEndP or TxAddr or frameNum or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or HCTxPortData or HCTxPortCntl or HCTxPortWEn or HCTxPortReq or CurrState_sndPkt)
+begin
+  NextState_sndPkt <= CurrState_sndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortReq <= HCTxPortReq;
+  next_frameNum <= frameNum;
+  case (CurrState_sndPkt)  // synopsys parallel_case full_case
+    `START_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+    end
+    `WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_sndPkt <= `SP_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_HCTxPortReq <= 1'b1;
+      end
+    end
+    `SP_WAIT_GNT:
+    begin
+      if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))
+      begin
+        NextState_sndPkt <= `LS_EOP_WAIT_RDY;
+      end
+      else if (HCTxPortGnt == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_HCTxPortReq <= 1'b0;
+    end
+    `SEND_PID_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_PID_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= PIDNotPID;
+        next_HCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SEND_PID_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+      end
+      else if (PID == `SOF)
+      begin
+        NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+      end
+      else if (PID == `OUT || 
+        PID == `IN || 
+        PID == `SETUP)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sndPkt <= `FIN_SP;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY1:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_WAIT_RDY2:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `OUT_IN_SETUP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `OUT_IN_SETUP_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+    end
+    `SEND_SOF_FIN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_frameNum <= frameNum + 1'b1;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `SEND_SOF_WAIT_RDY3:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= frameNum[7:0];
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_WAIT_RDY4:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `SEND_SOF_FIN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    end
+    `SEND_SOF_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+    end
+    `DATA0_DATA1_READ_FIFO:
+    begin
+      next_HCTxPortWEn <= 1'b1;
+      next_HCTxPortData <= fifoData;
+      next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+    end
+    `DATA0_DATA1_WAIT_READ_FIFO:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `DATA0_DATA1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+      end
+    end
+    `DATA0_DATA1_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `DATA0_DATA1_TERM_BYTE:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `DATA0_DATA1_CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+    end
+    `DATA0_DATA1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+    end
+    `LS_EOP_WAIT_RDY:
+    begin
+      if (HCTxPortRdy == 1'b1)
+      begin
+        NextState_sndPkt <= `LS_EOP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
+      end
+    end
+    `LS_EOP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sndPkt <= `START_SP;
+  else
+    CurrState_sndPkt <= NextState_sndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    HCTxPortData <= 8'h00;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+    frameNum <= 11'h000;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+    frameNum <= next_frameNum;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.v	(revision 264)
@@ -0,0 +1,218 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketcheckpreamble
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   preAmbleEnable;
+input   rst;
+input   [3:0]sendPacketCPPID;
+input   sendPacketCPWEn;
+input   sendPacketRdy;
+output  sendPacketCPReady;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+
+wire    clk;
+wire    preAmbleEnable;
+wire    rst;
+wire    [3:0]sendPacketCPPID;
+reg     sendPacketCPReady, next_sendPacketCPReady;
+wire    sendPacketCPWEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_PREAM_SENT 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_PID_SENT 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+`define PREAM_PKT_WAIT_RDY2 4'b1100
+`define PREAM_PKT_WAIT_RDY3 4'b1101
+
+reg [3:0]CurrState_sendPktCP, NextState_sendPktCP;
+
+
+// Machine: sendPktCP
+
+// NextState logic (combinatorial)
+always @ (sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPPID or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
+begin
+  NextState_sendPktCP <= CurrState_sendPktCP;
+  // Set default values for outputs and signals
+  next_sendPacketCPReady <= sendPacketCPReady;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  case (CurrState_sendPktCP)  // synopsys parallel_case full_case
+    `SPC_WAIT_EN:
+    begin
+      if (sendPacketCPWEn == 1'b1)
+      begin
+        NextState_sendPktCP <= `CHK_PREAM;
+        next_sendPacketCPReady <= 1'b0;
+      end
+    end
+    `START_SPC:
+    begin
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `CHK_PREAM:
+    begin
+      if (preAmbleEnable == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+      end
+    end
+    `READY:
+    begin
+      next_sendPacketCPReady <= 1'b1;
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `PREAM_PKT_SND_PREAM:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= `PREAMBLE;
+      NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
+    end
+    `PREAM_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+      end
+    end
+    `PREAM_PKT_PREAM_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+    end
+    `PREAM_PKT_SND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
+    end
+    `PREAM_PKT_PID_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+    end
+    `PREAM_PKT_WAIT_RDY2:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+      end
+    end
+    `PREAM_PKT_WAIT_RDY3:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `READY;
+      end
+    end
+    `REG_PKT_SEND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+    end
+    `REG_PKT_WAIT_RDY1:
+    begin
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_sendPktCP <= `REG_PKT_SEND_PID;
+      end
+    end
+    `REG_PKT_WAIT_RDY:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `READY;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_sendPktCP <= `START_SPC;
+  else
+    CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketCPReady <= 1'b1;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+  end
+  else 
+  begin
+    sendPacketCPReady <= next_sendPacketCPReady;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.v	(revision 264)
@@ -0,0 +1,201 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// softransmit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, SOFEnable, SOFSent, SOFSyncEn, SOFTimer, SOFTimerClr);
+input   clk;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   SOFEnable;    // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input   SOFSyncEn;
+input   [15:0]SOFTimer;
+output  sendPacketArbiterReq;
+output  sendPacketWEn;
+output  SOFSent;    // single cycle pulse
+output  SOFTimerClr;    // Single cycle pulse
+
+wire    clk;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+wire    SOFEnable;
+reg     SOFSent, next_SOFSent;
+wire    SOFSyncEn;
+wire    [15:0]SOFTimer;
+reg     SOFTimerClr, next_SOFTimerClr;
+
+// diagram signals declarations
+reg  [7:0]i, next_i;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+`define DLY_SOF_CHK1 3'b101
+`define DLY_SOF_CHK2 3'b110
+
+reg [2:0]CurrState_SOFTx, NextState_SOFTx;
+
+
+// Machine: SOFTx
+
+// NextState logic (combinatorial)
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or i or SOFSent or SOFTimerClr or sendPacketArbiterReq or sendPacketWEn or CurrState_SOFTx)
+begin
+  NextState_SOFTx <= CurrState_SOFTx;
+  // Set default values for outputs and signals
+  next_SOFSent <= SOFSent;
+  next_SOFTimerClr <= SOFTimerClr;
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_i <= i;
+  case (CurrState_SOFTx)  // synopsys parallel_case full_case
+    `START_STX:
+    begin
+      NextState_SOFTx <= `WAIT_SOF_NEAR;
+    end
+    `WAIT_SOF_NEAR:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+        (SOFSyncEn == 1'b1 &&
+        SOFEnable == 1'b1))
+      begin
+        NextState_SOFTx <= `WAIT_SP_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    end
+    `WAIT_SP_GNT:
+    begin
+      if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
+      begin
+        NextState_SOFTx <= `WAIT_SOF_NOW;
+      end
+    end
+    `WAIT_SOF_NOW:
+    begin
+      if (SOFTimer >= `SOF_TX_TIME)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_sendPacketWEn <= 1'b1;
+        next_SOFTimerClr <= 1'b1;
+        next_SOFSent <= 1'b1;
+      end
+      else if (SOFEnable == 1'b0)
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_SOFTimerClr <= 1'b1;
+      end
+    end
+    `SOF_FIN:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      next_SOFTimerClr <= 1'b0;
+      next_SOFSent <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_SOFTx <= `DLY_SOF_CHK1;
+        next_i <= 8'h00;
+      end
+    end
+    `DLY_SOF_CHK1:
+    begin
+      next_i <= i + 1'b1;
+      if (i==8'hff)
+      begin
+        NextState_SOFTx <= `DLY_SOF_CHK2;
+        next_sendPacketArbiterReq <= 1'b0;
+        next_i <= 8'h00;
+      end
+    end
+    `DLY_SOF_CHK2:
+    begin
+      next_i <= i + 1'b1;
+      if (i==8'hff)
+      begin
+        NextState_SOFTx <= `WAIT_SOF_NEAR;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SOFTx <= `START_STX;
+  else
+    CurrState_SOFTx <= NextState_SOFTx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SOFSent <= 1'b0;
+    SOFTimerClr <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketWEn <= 1'b0;
+    i <= 8'h00;
+  end
+  else 
+  begin
+    SOFSent <= next_SOFSent;
+    SOFTimerClr <= next_SOFTimerClr;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketWEn <= next_sendPacketWEn;
+    i <= next_i;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMuxBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMuxBI.v	(revision 264)
@@ -0,0 +1,125 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMuxBI.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+`include "usbHostSlave_h.v"
+
+module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
+  hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+wire rstFromWire;
+reg rstSyncToBusClkOut;
+reg rstSyncToUsbClkOut;
+
+//internal wire and regs
+reg [5:0] rstShift;
+reg rstFromBus;
+reg rstSyncToUsbClkFirst;
+
+//sync write demux
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClkOut == 1'b1)
+    hostMode <= 1'b0;
+  else begin
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+      hostMode <= dataIn[0];
+    end
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
+      rstFromBus <= 1'b1;
+    else
+      rstFromBus <= 1'b0;
+end
+
+// async read mux
+always @(address or hostMode)
+begin
+  case (address)
+    `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+    `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+  endcase
+end
+
+// reset control
+//generate 'rstSyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+  if (rstFromWire == 1'b1 || rstFromBus == 1'b1) 
+    rstShift <= 6'b111111;
+  else
+    rstShift <= {1'b0, rstShift[5:1]};
+end
+
+always @(rstShift)
+  rstSyncToBusClkOut <= rstShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+    rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
+    rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
+end
+
+endmodule

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSerialInterfaceEngine_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSerialInterfaceEngine_h.v	(revision 264)
@@ -0,0 +1,104 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v                                
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+`define RX_EDGE_DET_TOUT 7
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+`define TX_LS_KEEP_ALIVE 8'h06
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+// RESUME_RX_WAIT_TIME defines the time period for resume detection
+// The resume counter is incremented at the bit rate, so
+// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
+// and 30 * 1/1.5MHz =  20uS at low speed, both of which are within the USB spec of 
+// 2.5uS <= resumeDetectTime <= 100uS
+`define RESUME_RX_WAIT_TIME 5'd29
+//`define RESUME_WAIT_TIME_MINUS1 9
+// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate 
+`define HOST_TX_RESUME_TIME 16'd30000  //Host sends resume for 30000 * 1/1.5MHz = 20mS
+//`define CONNECT_WAIT_TIME 8'd20
+`define CONNECT_WAIT_TIME 8'd120      //Device connect detected after 120 * 1/48MHz = 2.5uS
+//`define DISCONNECT_WAIT_TIME 8'd20   
+`define DISCONNECT_WAIT_TIME 8'd120   //Device disconnect detected after 120 * 1/48MHz = 2.5uS
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates 
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.v	(revision 264)
@@ -0,0 +1,787 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIETransmitter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (clk, CRC16En, CRC16Result, CRC16UpdateRdy, CRC5_8Bit, CRC5En, CRC5Result, CRC5UpdateRdy, CRCData, fullSpeedRateIn, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, rstCRC, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOut, TxByteOutCtrl, TxByteOutFullSpeedRate, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   [15:0]CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0]CRC5Result;
+input   CRC5UpdateRdy;
+input   fullSpeedRateIn;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteRdy;
+input   rst;
+input   [7:0]SIEPortCtrlIn;
+input   [7:0]SIEPortDataIn;
+input   SIEPortWEn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  CRC16En;
+output  CRC5_8Bit;
+output  CRC5En;
+output  [7:0]CRCData;
+output  processTxByteWEn;
+output  rstCRC;
+output  SIEPortTxRdy;
+output  [7:0]TxByteOut;
+output  [7:0]TxByteOutCtrl;
+output  TxByteOutFullSpeedRate;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+reg     CRC16En, next_CRC16En;
+wire    [15:0]CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     CRC5En, next_CRC5En;
+wire    [4:0]CRC5Result;
+wire    CRC5UpdateRdy;
+reg     [7:0]CRCData, next_CRCData;
+wire    fullSpeedRateIn;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+wire    processTxByteRdy;
+reg     processTxByteWEn, next_processTxByteWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+wire    [7:0]SIEPortCtrlIn;
+wire    [7:0]SIEPortDataIn;
+reg     SIEPortTxRdy, next_SIEPortTxRdy;
+wire    SIEPortWEn;
+reg     [7:0]TxByteOut, next_TxByteOut;
+reg     [7:0]TxByteOutCtrl, next_TxByteOutCtrl;
+reg     TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [2:0]i, next_i;
+reg  [15:0]resumeCnt, next_resumeCnt;
+reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg  [7:0]SIEPortData, next_SIEPortData;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define DIR_CTL_CHK_FIN 6'b000000
+`define RES_ST_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
+`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
+`define PKT_ST_HS_PKT_SENT 6'b000111
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
+`define PKT_ST_SPCL_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_SND_J_1 6'b001110
+`define RES_ST_SND_J_2 6'b001111
+`define RES_ST_SND_SE0_1 6'b010000
+`define RES_ST_SND_SE0_2 6'b010001
+`define START_SIETX 6'b010010
+`define STX_CHK_ST 6'b010011
+`define STX_WAIT_BYTE 6'b010100
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
+`define RES_ST_W_RDY1 6'b011000
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011001
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011010
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011011
+`define RES_ST_WAIT_GNT 6'b011100
+`define DIR_CTL_WAIT_GNT 6'b011101
+`define PKT_ST_HS_WAIT_RDY 6'b011110
+`define PKT_ST_SPCL_WAIT_RDY 6'b011111
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100010
+`define RES_ST_WAIT_RDY 6'b100011
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100101
+`define DIR_CTL_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100111
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101000
+`define PKT_ST_WAIT_RDY_PKT 6'b101001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
+`define TX_LS_EOP_WAIT_GNT1 6'b101101
+`define TX_LS_EOP_SND_SE0_2 6'b101110
+`define TX_LS_EOP_SND_SE0_1 6'b101111
+`define TX_LS_EOP_W_RDY1 6'b110000
+`define TX_LS_EOP_SND_J 6'b110001
+`define TX_LS_EOP_W_RDY2 6'b110010
+`define TX_LS_EOP_W_RDY3 6'b110011
+`define RES_ST_DELAY 6'b110100
+`define RES_ST_W_RDY2 6'b110101
+`define RES_ST_W_RDY3 6'b110110
+`define RES_ST_W_RDY4 6'b110111
+`define DIR_CTL_DELAY 6'b111000
+
+reg [5:0]CurrState_SIETx, NextState_SIETx;
+
+
+// Machine: SIETx
+
+// NextState logic (combinatorial)
+always @ (i or resumeCnt or SIEPortData or SIEPortCtrl or fullSpeedRateIn or SIEPortWEn or SIEPortDataIn or SIEPortCtrlIn or USBWireRdy or USBWireGnt or processTxByteRdy or CRC5Result or KBit or CRC16Result or CRC5UpdateRdy or CRC16UpdateRdy or JBit or USBWireWEn or USBWireReq or processTxByteWEn or rstCRC or USBWireFullSpeedRate or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or CurrState_SIETx)
+begin
+  NextState_SIETx <= CurrState_SIETx;
+  // Set default values for outputs and signals
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_USBWireReq <= USBWireReq;
+  next_processTxByteWEn <= processTxByteWEn;
+  next_rstCRC <= rstCRC;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  next_TxByteOut <= TxByteOut;
+  next_TxByteOutCtrl <= TxByteOutCtrl;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_SIEPortTxRdy <= SIEPortTxRdy;
+  next_SIEPortData <= SIEPortData;
+  next_SIEPortCtrl <= SIEPortCtrl;
+  next_resumeCnt <= resumeCnt;
+  next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
+  case (CurrState_SIETx)  // synopsys parallel_case full_case
+    `IDLE:
+    begin
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `START_SIETX:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_TxByteOut <= 8'h00;
+      next_TxByteOutCtrl <= 8'h00;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_SIEPortTxRdy <= 1'b0;
+      next_SIEPortData <= 8'h00;
+      next_SIEPortCtrl <= 8'h00;
+      next_i <= 3'h0;
+      next_resumeCnt <= 16'h0000;
+      next_TxByteOutFullSpeedRate <= 1'b0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `STX_CHK_ST:
+    begin
+      if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+        next_TxByteOutFullSpeedRate <= 1'b1;
+        //SOF and PRE always at full speed
+      end
+      else if (SIEPortCtrl == `TX_PACKET_START)
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+      end
+      else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_IDLE)
+      begin
+        NextState_SIETx <= `IDLE;
+      end
+      else if (SIEPortCtrl == `TX_RESUME_START)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+        next_resumeCnt <= 16'h0000;
+        next_USBWireFullSpeedRate <= 1'b0;
+        //resume always uses low speed timing
+      end
+    end
+    `STX_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `STX_CHK_ST;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+        next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
+        next_USBWireFullSpeedRate <= fullSpeedRateIn;
+      end
+    end
+    `DIR_CTL_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_i <= i + 1'b1;
+      if (i == 3'h7)
+      begin
+        NextState_SIETx <= `STX_WAIT_BYTE;
+        next_USBWireReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_SIETx <= `DIR_CTL_DELAY;
+      end
+    end
+    `DIR_CTL_WAIT_GNT:
+    begin
+      next_i <= 3'h0;
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+      end
+    end
+    `DIR_CTL_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `DIR_CTL_CHK_FIN;
+        next_USBWireData <= SIEPortData[1:0];
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `DIR_CTL_DELAY:
+    begin
+      NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+    end
+    `PKT_ST_CHK_PID:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      if (SIEPortData[1:0] == `TOKEN)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `HANDSHAKE)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `DATA)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+      end
+      else if (SIEPortData[1:0] == `SPECIAL)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+      end
+    end
+    `PKT_ST_WAIT_RDY_PKT:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_CHK_PID;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= `SYNC_BYTE;
+        next_TxByteOutCtrl <= `DATA_START;
+      end
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT2:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY1:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[7:0];
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY2:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[15:8];
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_DATA_DATA_CHK_STOP:
+    begin
+      if (SIEPortCtrl == `TX_PACKET_STOP)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+      end
+      else
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+      end
+    end
+    `PKT_ST_DATA_DATA_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_DATA_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC16En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+    end
+    `PKT_ST_DATA_DATA_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_RDY:
+    begin
+      next_CRC16En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+    begin
+      if (CRC16UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+      end
+    end
+    `PKT_ST_DATA_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `PKT_ST_HS_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_HS_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_SPCL_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_SPCL_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_BYTE1_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_CRC_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_CRC_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+    end
+    `PKT_ST_TKN_CRC_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+    begin
+      if (CRC5UpdateRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+      end
+    end
+    `PKT_ST_TKN_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_PID_WAIT_RDY:
+    begin
+      if (processTxByteRdy == 1'b1)
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    end
+    `RES_ST_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (resumeCnt == `HOST_TX_RESUME_TIME)
+      begin
+        NextState_SIETx <= `RES_ST_W_RDY1;
+      end
+      else
+      begin
+        NextState_SIETx <= `RES_ST_DELAY;
+      end
+    end
+    `RES_ST_SND_J_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY4;
+    end
+    `RES_ST_SND_J_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+      next_USBWireFullSpeedRate <= fullSpeedRateIn;
+    end
+    `RES_ST_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY2;
+    end
+    `RES_ST_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY3;
+    end
+    `RES_ST_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_RDY;
+      end
+    end
+    `RES_ST_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_CHK_FIN;
+        next_USBWireData <= KBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+        next_resumeCnt <= resumeCnt  + 1'b1;
+      end
+    end
+    `RES_ST_DELAY:
+    begin
+      NextState_SIETx <= `RES_ST_WAIT_RDY;
+    end
+    `RES_ST_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `RES_ST_W_RDY4:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_2;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `TX_LS_EOP_WAIT_GNT1:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_W_RDY1;
+      end
+    end
+    `TX_LS_EOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY3;
+    end
+    `TX_LS_EOP_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY2;
+    end
+    `TX_LS_EOP_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `TX_LS_EOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `TX_LS_EOP_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `TX_LS_EOP_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_J;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_SIETx <= `START_SIETX;
+  else
+    CurrState_SIETx <= NextState_SIETx;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    USBWireWEn <= 1'b0;
+    USBWireReq <= 1'b0;
+    processTxByteWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+    TxByteOut <= 8'h00;
+    TxByteOutCtrl <= 8'h00;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    SIEPortTxRdy <= 1'b0;
+    TxByteOutFullSpeedRate <= 1'b0;
+    i <= 3'h0;
+    SIEPortData <= 8'h00;
+    SIEPortCtrl <= 8'h00;
+    resumeCnt <= 16'h0000;
+  end
+  else 
+  begin
+    USBWireWEn <= next_USBWireWEn;
+    USBWireReq <= next_USBWireReq;
+    processTxByteWEn <= next_processTxByteWEn;
+    rstCRC <= next_rstCRC;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+    TxByteOut <= next_TxByteOut;
+    TxByteOutCtrl <= next_TxByteOutCtrl;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    SIEPortTxRdy <= next_SIEPortTxRdy;
+    TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
+    i <= next_i;
+    SIEPortData <= next_SIEPortData;
+    SIEPortCtrl <= next_SIEPortCtrl;
+    resumeCnt <= next_resumeCnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.asf	(revision 264)
@@ -0,0 +1,305 @@
+VERSION=1.15
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FRAMES=ON
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processRxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
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+OBJECTS
+L 15 16 0 TEXT "State Labels" | 115714,125064 1 0 0 "CHK_PID"
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "CHK_ST\n/0/"
+S 9 6 4096 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PRBY\n/1/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: processRxByte"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prRxByte"
+A 278 257 4 TEXT "Actions" | 130366,127109 1 0 0 "RxDataOutWEn <= 1'b0;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;"
+L 279 280 0 TEXT "State Labels" | 49504,129936 1 0 0 "FIN\n/10/"
+S 280 41 69632 ELLIPSE "States" | 49504,129936 6500 6500
+W 281 41 0 40 280 BEZIER "Transitions" | 71655,187272 66885,174036 56388,149316 51618,136080
+A 282 280 4 TEXT "Actions" | 68321,131530 1 0 0 "CRC5En <= 1'b0;\nRxDataOutWEn <= 1'b0;"
+W 284 41 0 280 37 BEZIER "Transitions" | 54276,125525 62504,119205 73926,104895 82154,98575
+W 285 50 0 286 291 BEZIER "Transitions" | 59473,89872 67701,83552 79123,69242 87351,62922
+S 286 50 73728 ELLIPSE "States" | 54701,94283 6500 6500
+A 287 286 4 TEXT "Actions" | 73518,95877 1 0 0 "CRC16En <= 1'b0;\nRxDataOutWEn <= 1'b0;"
+L 303 304 0 TEXT "Labels" | 84462,243195 1 0 0 "RxByteIn[7:0]"
+I 302 0 2 Builtin OutPort | 76139,250245 "" ""
+L 301 302 0 TEXT "Labels" | 82139,250245 1 0 0 "RxDataOutWEn"
+I 300 0 130 Builtin OutPort | 76848,255265 "" ""
+L 299 300 0 TEXT "Labels" | 82848,255265 1 0 0 "RxCtrlOut[7:0]"
+I 298 0 130 Builtin OutPort | 76848,260279 "" ""
+L 297 298 0 TEXT "Labels" | 82848,260279 1 0 0 "RxDataOut[7:0]"
+A 296 0 1 TEXT "Actions" | 13933,264927 1 0 0 "always @\n(next_CRCError or next_bitStuffError or\n next_RxOverflow or next_NAKRxed or \n next_stallRxed or next_ACKRxed or \n next_dataSequence)\nbegin	\n  RxStatus <= \n  {1'b0, next_dataSequence, \n  next_ACKRxed, \n  next_stallRxed, next_NAKRxed, \n  next_RxOverflow, \n  next_bitStuffError, next_CRCError };\nend"
+L 25 24 0 TEXT "State Labels" | 115892,94696 1 0 0 "HSHAKE"
+S 24 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115892,94696 6500 6500
+I 21 17 0 Builtin Exit | 89220,92674
+I 20 17 0 Builtin Entry | 45216,248076
+L 19 18 0 TEXT "State Labels" | 109233,155402 1 0 0 "FIRST_BYTE"
+S 18 17 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 109233,155402 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 16 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115714,123462 6500 6500
+W 288 50 0 293 286 BEZIER "Transitions" | 76852,151619 72082,138383 61585,113663 56815,100427
+L 289 286 0 TEXT "State Labels" | 54701,94283 1 0 0 "FIN\n/11/"
+I 291 50 0 Builtin Exit | 90483,62922
+I 292 50 0 Builtin Entry | 33692,252435
+S 293 50 77824 ELLIPSE "States" | 79792,157415 6500 6500
+L 294 293 0 TEXT "State Labels" | 79792,157415 1 0 0 "CHK_STRM\n/12/"
+A 295 293 4 TEXT "Actions" | 114075,218259 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC16Result != 16'hb001)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    RxDataOut <= RxByte;\n    RxCtrlOut <= `RX_PACKET_STREAM;\n    CRCData <= RxByte;\n    CRC16En <= 1'b1;\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,250603 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,255220 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 308 0 2 Builtin InPort | 78462,232428 "" ""
+L 307 308 0 TEXT "Labels" | 85176,232428 1 0 0 "processRxDataInWEn"
+I 306 0 130 Builtin InPort | 78465,238172 "" ""
+L 305 306 0 TEXT "Labels" | 84465,238172 1 0 0 "RxCtrlIn[7:0]"
+I 304 0 130 Builtin InPort | 78462,243195 "" ""
+L 43 42 0 TEXT "State Labels" | 118750,36808 1 0 0 "DATA"
+S 42 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118750,36808 6500 6500
+S 40 41 65536 ELLIPSE "States" | 74595,193068 6500 6500
+L 39 40 0 TEXT "State Labels" | 74595,193068 1 0 0 "CHK_STRM\n/9/"
+I 38 41 0 Builtin Entry | 30541,258592
+I 37 41 0 Builtin Exit | 85286,98575
+W 36 41 0 38 371 BEZIER "Transitions" | 34704,258592 38731,254357 47806,246433 31745,235718
+L 34 33 0 TEXT "State Labels" | 117500,64680 1 0 0 "TOKEN"
+S 33 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 117500,64680 6500 6500
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 17144,15700 201644,263700
+L 335 336 0 TEXT "Labels" | 175074,243343 1 0 0 "ACKRxed"
+I 334 0 2 Builtin Signal | 172074,247627 "" ""
+L 333 334 0 TEXT "Labels" | 175074,247627 1 0 0 "stallRxed"
+I 332 0 2 Builtin Signal | 171717,252268 "" ""
+L 331 332 0 TEXT "Labels" | 174717,252268 1 0 0 "NAKRxed"
+I 330 0 2 Builtin Signal | 172074,256552 "" ""
+L 329 330 0 TEXT "Labels" | 175074,256552 1 0 0 "RxTimeOut"
+I 328 0 2 Builtin Signal | 172074,260836 "" ""
+L 327 328 0 TEXT "Labels" | 175074,260836 1 0 0 "RxOverflow"
+I 326 0 2 Builtin Signal | 172074,265120 "" ""
+L 325 326 0 TEXT "Labels" | 175074,265120 1 0 0 "bitStuffError"
+I 324 0 130 Builtin InPort | 126267,236303 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+S 63 6 24576 ELLIPSE "States" | 112744,173179 6500 6500
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "WAIT_BYTE\n/2/"
+C 58 54 0 TEXT "Conditions" | 46403,31524 1 0 0 "RXByteStMachCurrState == `DATA_BYTE_ST"
+C 57 53 0 TEXT "Conditions" | 45420,58426 1 0 0 "RXByteStMachCurrState == `TOKEN_BYTE_ST"
+C 56 52 0 TEXT "Conditions" | 45596,90880 1 0 0 "RXByteStMachCurrState == `HS_BYTE_ST"
+C 55 51 0 TEXT "Conditions" | 43455,121392 1 0 0 "RXByteStMachCurrState == `CHECK_PID_ST"
+W 54 6 0 11 42 BEZIER "Transitions" | 41669,169131 42607,140455 43130,70308 44403,54764\
+                                      45676,39220 48892,34396 57535,33391 66178,32386\
+                                      96662,35330 112340,35732
+W 53 6 0 11 33 BEZIER "Transitions" | 41642,169108 42044,146596 42058,88800 43264,77142\
+                                      44470,65484 48490,63876 56999,63474 65508,63072\
+                                      95524,63072 103095,63072 110666,63072 111053,63134\
+                                      111187,63134
+W 52 6 0 11 24 BEZIER "Transitions" | 41273,169115 41809,155581 41924,114126 42929,106354\
+                                      43934,98582 46882,94562 55190,93624 63498,92686\
+                                      93782,92954 101420,93021 109058,93088 109445,93150\
+                                      109579,93150
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+                                      42326,129670 44202,125650 52711,124511 61220,123372\
+                                      93136,123615 109216,123347
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 340 0 128 Builtin Signal | 172498,229252 "" ""
+L 339 340 0 TEXT "Labels" | 175498,229252 1 0 0 "RxStatus[7:0]"
+W 351 6 0 357 63 BEZIER "Transitions" | 165899,88318 165621,91424 166582,101426 164321,105232\
+                                        162060,109038 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 135270,157360\
+                                        132480,162850 129690,168340 122852,170455 118982,171355
+A 349 9 4 TEXT "Actions" | 143783,207627 1 0 0 "RxByte <= 8'h00;\nRxCtrl <= 8'h00;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nRxTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxDataOut <= 8'h00;\nRxCtrlOut <= 8'h00;\nRxDataOutWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nRXDataByteCnt <= 10'h00;\nprocessRxByteRdy <= 1'b1;"
+I 346 0 130 Builtin Signal | 116382,216211 "" ""
+L 345 346 0 TEXT "Labels" | 119382,216211 1 0 0 "RXByteStMachCurrState[2:0]"
+I 344 0 130 Builtin Signal | 172286,221621 "" ""
+L 343 344 0 TEXT "Labels" | 175286,221621 1 0 0 "RxCtrl[7:0]"
+I 342 0 130 Builtin Signal | 171929,216623 "" ""
+L 341 342 0 TEXT "Labels" | 174929,216623 1 0 0 "RxByte[7:0]"
+I 338 0 2 Builtin Signal | 172074,238702 "" ""
+L 337 338 0 TEXT "Labels" | 175074,238702 1 0 0 "dataSequence"
+I 336 0 2 Builtin Signal | 172074,243343 "" ""
+A 78 65 16 TEXT "Actions" | 51039,182627 1 0 0 "RxByte <= RxByteIn;\nRxCtrl <= RxCtrlIn;\nprocessRxByteRdy <= 1'b0;"
+W 76 17 8194 75 18 BEZIER "Transitions" | 69849,207737 75657,200807 99461,167483 105269,160553
+S 75 17 45056 ELLIPSE "States" | 65748,212778 6500 6500
+L 74 75 0 TEXT "State Labels" | 65748,212778 1 0 0 "DO_CHK\n/5/"
+W 72 6 0 42 357 BEZIER "Transitions" | 123133,41607 132448,51732 153635,72170 162950,82295
+W 71 6 0 33 357 BEZIER "Transitions" | 123360,67490 132540,71405 152828,79824 162008,83739
+W 69 6 0 24 357 BEZIER "Transitions" | 122281,93503 131596,91478 152599,87697 161914,85672
+W 68 6 0 16 357 BEZIER "Transitions" | 120926,119581 130781,111751 152663,94796 162518,86966
+C 66 65 0 TEXT "Conditions" | 62843,168563 1 0 0 "processRxDataInWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59763,178747 47927,176730
+W 64 6 0 9 63 BEZIER "Transitions" | 48012,197411 59579,195797 95649,181504 106856,175930
+I 367 0 2 Builtin Signal | 77453,221558 "" ""
+L 366 367 0 TEXT "Labels" | 80453,221558 1 0 0 "Signal1"
+I 355 0 130 Builtin Signal | 77612,216204 "" ""
+L 354 355 0 TEXT "Labels" | 80612,216204 1 0 0 "RXDataByteCnt[9:0]"
+I 353 0 2 Builtin Signal | 172356,234668 "" ""
+L 352 353 0 TEXT "Labels" | 175356,234668 1 0 0 "CRCError"
+W 81 17 0 20 75 BEZIER "Transitions" | 49379,248076 53439,241189 58262,225186 62322,218299
+W 82 17 4097 75 21 BEZIER "Transitions" | 63199,206800 60009,197085 40708,156469 41288,147696\
+                                          41868,138924 51896,113272 59871,108777 67846,104282\
+                                          74724,97474 86324,92674
+L 356 357 0 TEXT "State Labels" | 165320,84870 1 0 0 "J1"
+S 357 6 81940 ELLIPSE "Junction" | 165320,84870 3500 3500
+H 358 357 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 359 358 0 Builtin Entry | 86360,167640
+I 360 358 0 Builtin Exit | 129540,111760
+W 361 358 0 359 360 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+C 380 379 0 TEXT "Conditions" | 39560,213610 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 379 50 0 377 293 BEZIER "Transitions" | 76802,222169 77769,207119 78297,178932 79264,163882
+W 378 50 0 292 377 BEZIER "Transitions" | 37855,252435 46562,247168 62458,237581 71165,232314
+S 377 50 90112 ELLIPSE "States" | 76540,228660 6500 6500
+L 376 377 0 TEXT "State Labels" | 76540,228660 1 0 0 "WAIT_CRC\n/14/"
+I 375 0 2 Builtin InPort | 126404,222116 "" ""
+L 374 375 0 TEXT "Labels" | 132404,222116 1 0 0 "CRC16UpdateRdy"
+C 373 372 0 TEXT "Conditions" | 40381,225556 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 372 41 0 371 40 BEZIER "Transitions" | 35330,224745 46935,215765 58540,206785 70145,197805
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+I 369 0 2 Builtin InPort | 126404,226868 "" ""
+L 368 369 0 TEXT "Labels" | 132404,226868 1 0 0 "CRC5UpdateRdy"
+L 381 382 0 TEXT "Labels" | 84990,227664 1 0 0 "processRxByteRdy"
+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC5Result != 5'h6)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    if (RXDataByteCnt > 10'h2) \n    begin\n      RxOverflow <= 1'b1;\n      RxDataOut <= RxStatus;\n      RxCtrlOut <= `RX_PACKET_STOP;\n      RXByteStMachCurrState <= `IDLE_BYTE_ST;\n    end\n    else \n    begin\n      RxDataOut <= RxByte;\n      RxCtrlOut <= `RX_PACKET_STREAM;\n      CRCData <= RxByte;\n      CRC5_8Bit <= 1'b1;\n      CRC5En <= 1'b1;\n    end\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+I 221 217 0 Builtin Exit | 136710,89055
+I 220 217 0 Builtin Entry | 86360,167640
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+I 228 224 0 Builtin Exit | 129540,111760
+I 227 224 0 Builtin Entry | 86360,167640
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+I 253 248 0 Builtin Exit | 78564,173120
+I 252 248 0 Builtin Entry | 35384,229000
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n  `SPECIAL:                              //Special PID.\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  `TOKEN:                                //Token PID\n  begin\n    RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\n  `HANDSHAKE:                            //Handshake PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        ACKRxed <= 1'b1;\n      2'b10:\n        NAKRxed <= 1'b1;\n      2'b11:\n        stallRxed <= 1'b1;\n      default:\n      begin\n        $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n      end\n    endcase\n    RXByteStMachCurrState <= `HS_BYTE_ST;\n  end\n  `DATA:                                  //Data PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        dataSequence <= 1'b0;\n      2'b10:\n        dataSequence <= 1'b1;\n      default:\n        $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n    endcase\n    RXByteStMachCurrState <= `DATA_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\nendcase"
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n  RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n  RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n  RXByteStMachCurrState = `IDLE_BYTE_ST;"
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+                                        89364,102368 89220,95212 89220,94846
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+I 259 32 0 Builtin Entry | 66351,233704
+I 260 32 0 Builtin Exit | 110355,78302
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n  RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+                                          110499,87996 110355,80840 110355,80474
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/readUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/readUSBWireData.v	(revision 264)
@@ -0,0 +1,266 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// readUSBWireData.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////      This module reads data from the differential USB data lines
+////      and writes into a 4 entry FIFO. The data is read from
+////      the fifo and output from the module when the higher level
+////      state machine is ready to receive the data.
+////      This module must recover the clock phase from the incoming
+////      USB data. 'sampleCnt' is reset to zero whenever a RX data
+////      edge is detected. Note that due to metastability the data
+////      at the edge may not be registered correctly, but this does
+////      not matter. All that matters is that an edge was detected. The
+////      data will be accurately sampled in the middle of the USB bit 
+////      period without metastability issues. 
+////      After the edge detect, 'sampleCnt' is incremented at every clock
+////      tick, and when it indicates the middle of a USB bit period
+////      the RX data is sampled and written to the input buffer.
+////      Single clock tick adjustments to 'sampleCnt' can be made at 
+////      every RX data edge detect without double sampling the incoming
+////      data. However, the first RX data bit in a packet may cause 
+////      'sampleCnt' to be adjusted by a value greater than a single 
+////      clock tick, and this can result in double sampling of the 
+////      first data bit a RX packet. This 
+////      double sampled data must be rejected by the higher level module.
+////      This is achieved by 
+////      qualifying the outgoing data with 'RxWireActive'. Thus 
+////      the first data bit in a RX packet may be double sampled
+////      as the clock recovery mechanism synchronizes to 'RxBitsIn'
+////      but the double sampled data will be rejected by the higher 
+////      level module.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable);
+input   [1:0] RxBitsIn;
+output  RxDataInTick;
+input   SIERxRdyIn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+input   TxWireActiveDrive;
+output  [1:0] RxBitsOut;
+output  SIERxWEn;
+output noActivityTimeOut;
+output RxWireActive;
+input  noActivityTimeOutEnable;
+
+wire   [1:0] RxBitsIn;
+reg    RxDataInTick;
+wire   SIERxRdyIn;
+wire   clk;
+wire   fullSpeedRate;
+wire   rst;
+reg    [1:0] RxBitsOut;
+reg    SIERxWEn;
+reg    noActivityTimeOut;
+reg    RxWireActive;
+wire   noActivityTimeOutEnable;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]sampleCnt;
+reg incBufferCnt;
+reg  [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg [7:0] rxActiveCnt;
+reg RxWireEdgeDetect;
+reg RxWireActiveReg;
+reg RxWireActiveReg2;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    sampleCnt <= 5'b00000;
+    incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    RxDataInTick <= 1'b0;
+    RxWireEdgeDetect <= 1'b0;
+    RxWireActiveReg <= 1'b0;
+    RxWireActiveReg2 <= 1'b0;
+  end
+  else begin
+    RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
+    RxBitsInReg <= RxBitsIn;    
+    oldRxBitsIn <= RxBitsInReg;
+    incBufferCnt <= 1'b0;         //default value
+    if ( (TxWireActiveDrive == 1'b0) && (RxBitsIn != RxBitsInReg)) begin  //if edge detected then
+      sampleCnt <= 5'b00000;        
+      RxWireEdgeDetect <= 1'b1;   // flag receive activity 
+      RxWireActiveReg <= 1'b1;
+      rxActiveCnt <= 8'h00;
+    end
+    else begin
+      sampleCnt <= sampleCnt + 1'b1;
+      RxWireEdgeDetect <= 1'b0;
+      rxActiveCnt <= rxActiveCnt + 1'b1;
+      //clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods 
+      if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE)
+        || (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) ) 
+        RxWireActiveReg <= 1'b0;
+    end
+    if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) )
+    begin
+      RxDataInTick <= !RxDataInTick;
+      if (TxWireActiveDrive != 1'b1)  //do not read wire data when transmitter is active
+      begin
+        incBufferCnt <= 1'b1;
+        bufferInIndex <= bufferInIndex + 1'b1;
+        case (bufferInIndex)
+          2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn}; 
+          2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn};
+          2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn};
+          2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn};
+        endcase
+      end
+    end
+  end
+end
+
+        
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    decBufferCnt <= 1'b0;
+    bufferOutIndex <= 2'b00;
+    RxBitsOut <= 2'b00;
+    SIERxWEn <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+  end
+  else begin
+    case (bufferOutStMachCurrState)
+      `WAIT_BUFFER_NOT_EMPTY:
+      begin
+        if (bufferCnt != 3'b000)
+          bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+      end
+      `WAIT_SIE_RX_READY:
+      begin
+        if (SIERxRdyIn == 1'b1)
+        begin 
+          SIERxWEn <= 1'b1;
+          bufferOutStMachCurrState <= `SIE_RX_WRITE;
+          decBufferCnt <= 1'b1;
+          bufferOutIndex <= bufferOutIndex + 1'b1;
+          case (bufferOutIndex)
+            2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
+            2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
+            2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
+            2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
+          endcase
+        end
+      end
+      `SIE_RX_WRITE:
+      begin
+        SIERxWEn <= 1'b0;
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+      end
+    endcase
+  end
+end
+
+//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods
+//'noActivityTimeOut'  pulse can only be generated when the host or slave getPacket
+//process enables via 'noActivityTimeOutEnable' signal
+//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if 
+//there has been a response time out.
+always @(posedge clk) begin
+  if (rst) begin
+    timeOutCnt <= 16'h0000;
+    noActivityTimeOut <= 1'b0;
+  end
+  else begin
+    if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0)
+      timeOutCnt <= 16'h0000;
+    else
+      timeOutCnt <= timeOutCnt + 1'b1;
+    if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+      || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) ) 
+      noActivityTimeOut <= 1'b1; 
+    else 
+      noActivityTimeOut <= 1'b0;
+  end
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC5.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC5.v	(revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC5.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   CRC5_8BitIn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [4:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   CRC5_8BitIn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 5'h1f;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0) begin
+      if (CRCEn == 1'b1) begin
+        ready <= 1'b0;
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        if (CRC5_8BitIn == 1'b1) begin
+          loopEnd <= 4'h7; 
+        end
+        else begin
+          loopEnd <= 4'h2;
+        end
+      end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[4:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == loopEnd) begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/writeUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/writeUSBWireData.v	(revision 264)
@@ -0,0 +1,281 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// writeUSBWireData.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL  3'b100
+
+module writeUSBWireData (
+  TxBitsIn, 
+  TxBitsOut,
+   TxDataOutTick,
+  TxCtrlIn, 
+  TxCtrlOut, 
+  USBWireRdy,
+  USBWireWEn, 
+  TxWireActiveDrive, 
+  fullSpeedRate, 
+  clk, 
+  rst
+   );
+  
+input   [1:0] TxBitsIn;
+input   TxCtrlIn;
+input   USBWireWEn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+output  [1:0] TxBitsOut;
+output TxDataOutTick;
+output  TxCtrlOut;
+output  USBWireRdy;
+output  TxWireActiveDrive;
+
+wire    [1:0] TxBitsIn;
+reg     [1:0] TxBitsOut;
+reg     TxDataOutTick;
+wire    TxCtrlIn;
+reg     TxCtrlOut;
+reg     USBWireRdy;
+wire    USBWireWEn;
+wire    clk;
+wire    fullSpeedRate;
+wire    rst;
+reg     TxWireActiveDrive;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else
+  begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+//buffer input state machine 
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+     incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    USBWireRdy <= 1'b0;
+    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+  end
+  else begin
+    case (bufferInStMachCurrState)
+      `WAIT_BUFFER_NOT_FULL:
+      begin
+        if (bufferCnt != `BUFFER_FULL)  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+      end
+      `WAIT_WRITE_REQ:
+      begin
+        if (USBWireWEn == 1'b1)
+        begin
+          incBufferCnt <= 1'b1;
+          USBWireRdy <= 1'b0;
+          bufferInIndex <= bufferInIndex + 1'b1;
+          case (bufferInIndex)
+            2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+            2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+            2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+            2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+          endcase
+          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+        end
+      end
+      `CLR_INC_BUFFER_CNT:
+      begin
+        incBufferCnt <= 1'b0;
+        if (bufferCnt != (`BUFFER_FULL - 1'b1) )  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+        else begin
+          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+        end
+      end
+    endcase
+  end
+end
+        
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    fullSpeedTick <= 1'b0;
+    lowSpeedTick <= 1'b0;
+  end
+  else
+  begin
+    i <= i + 1'b1;
+    if (i[1:0] == 2'b00)
+      fullSpeedTick <= 1'b1;
+    else
+      fullSpeedTick <= 1'b0; 
+    if (i == 5'b00000)
+      lowSpeedTick <= 1'b1;
+    else
+      lowSpeedTick <= 1'b0;
+  end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferOutIndex <= 2'b00;
+    decBufferCnt <= 1'b0;
+    TxBitsOut <= 2'b00;
+    TxCtrlOut <= `TRI_STATE;
+    TxDataOutTick <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+  end
+  else
+  begin
+    case (bufferOutStMachCurrState)
+      `WAIT_LINE_WRITE:
+      begin
+        if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+        begin
+          TxDataOutTick <= !TxDataOutTick;
+          if (bufferCnt == 0) begin
+            TxBitsOut <= 2'b00;
+            TxCtrlOut <= `TRI_STATE;
+          end
+          else begin
+            bufferOutStMachCurrState <= `LINE_WRITE;
+            decBufferCnt <= 1'b1;
+            bufferOutIndex <= bufferOutIndex + 1'b1;
+            case (bufferOutIndex)
+              2'b00 :
+            begin 
+              TxBitsOut <= buffer0[2:1];
+              TxCtrlOut <= buffer0[0];
+            end
+            2'b01 : 
+            begin
+              TxBitsOut <= buffer1[2:1];
+              TxCtrlOut <= buffer1[0];
+            end
+            2'b10 : 
+            begin 
+              TxBitsOut <= buffer2[2:1];
+              TxCtrlOut <= buffer2[0];
+            end
+            2'b11 : 
+            begin
+              TxBitsOut <= buffer3[2:1];
+              TxCtrlOut <= buffer3[0];
+            end
+            endcase
+          end
+        end
+      end
+      `LINE_WRITE:
+      begin
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+      end
+    endcase
+  end
+end
+
+// control 'TxWireActiveDrive' 
+always @(TxCtrlOut)
+begin  
+  if (TxCtrlOut == `DRIVE)
+    TxWireActiveDrive <= 1'b1;
+  else
+    TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.asf	(revision 264)
@@ -0,0 +1,107 @@
+VERSION=1.15
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SCTxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n"
+END
+BUNDLES
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+S 14 6 4096 ELLIPSE "States" | 269063,296392 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 10 6 0 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_SARB\n/3/"
+S 8 6 12288 ELLIPSE "States" | 225591,395370 6500 6500
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,543100 1 0 0 "Module: SCTxPortArbiter"
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+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+C 26 17 0 TEXT "Conditions" | 202073,391408 1 0 0 "rst"
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+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
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+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
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+L 43 42 0 TEXT "Labels" | 172566,462781 1 0 0 "SCTxPortRdyIn"
+I 42 0 2 Builtin InPort | 166566,462781 "" ""
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+L 40 39 0 TEXT "Labels" | 195447,542126 1 0 0 "rst"
+I 39 0 2 Builtin InPort | 189447,542126 "" ""
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+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "SCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 61 41 0 TEXT "Labels" | 196061,536582 1 0 0 "clk"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "SCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+A 54 0 1 TEXT "Actions" | 21871,418957 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n  SCTxPortRdyOut = SCTxPortRdyIn;\nend\n	  \nalways @(muxDCEn or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n  begin  \n    SCTxPortWEnable <= directCntlWEn;\n    SCTxPortData <= directCntlData;\n    SCTxPortCntl <= directCntlCntl;\n  end\nelse\n  begin  \n    SCTxPortWEnable <= sendPacketWEn;\n    SCTxPortData <= sendPacketData;\n    SCTxPortCntl <= sendPacketCntl;\n  end\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
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+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+L 65 64 0 TEXT "Labels" | 170048,467134 1 0 0 "SCTxPortRdyOut"
+I 64 0 2 Builtin OutPort | 164048,467134 "" ""
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+W 92 6 4098 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+S 91 6 8192 ELLIPSE "States" | 230314,289948 6500 6500
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "SARB_DC\n/2/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxDCEn"
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
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+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
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+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286142,395412 275462,395110\
+                                      264783,394808 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.asf	(revision 264)
@@ -0,0 +1,292 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=294
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveGetPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
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+W 59 46 0 49 54 BEZIER "Transitions" | 52122,248640 63735,242665 85368,230107 96981,224132
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+C 63 61 0 TEXT "Conditions" | 120868,199573 1 0 0 "RXByte[1:0] == `DATA"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 75 72 0 Builtin Entry | 33260,254940
+I 76 72 0 Builtin Exit | 187140,27160
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8194 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+C 133 131 0 TEXT "Conditions" | 102150,145171 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8195 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176807,72082 177204,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177624,25344 184036,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nSIERxTimeOutEn <= 1'b1;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;\nSIERxTimeOutEn <= 1'b0;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.v	(revision 264)
@@ -0,0 +1,265 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveSendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (clk, fifoData, fifoEmpty, fifoReadEn, PID, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   [7:0]fifoData;
+input   fifoEmpty;
+input   [3:0]PID;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   sendPacketWEn;
+output  fifoReadEn;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+output  sendPacketRdy;
+
+wire    clk;
+wire    [7:0]fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+wire    [3:0]PID;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0]CurrState_slvSndPkt, NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+// Machine: slvSndPkt
+
+// NextState logic (combinatorial)
+always @ (sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PIDNotPID or PID or fifoData or fifoEmpty or sendPacketRdy or fifoReadEn or SCTxPortData or SCTxPortCntl or SCTxPortWEn or SCTxPortReq or CurrState_slvSndPkt)
+begin
+  NextState_slvSndPkt <= CurrState_slvSndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_fifoReadEn <= fifoReadEn;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvSndPkt)  // synopsys parallel_case full_case
+    `START_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+    end
+    `SP_WAIT_ENABLE:
+    begin
+      if (sendPacketWEn == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP1_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `SP1_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+      end
+    end
+    `FIN_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_SCTxPortReq <= 1'b0;
+    end
+    `SP_NOT_DATA:
+    begin
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_SEND_PID_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= PIDNotPID;
+        next_SCTxPortCntl <= `TX_PACKET_START;
+      end
+    end
+    `SP_SEND_PID_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_NOT_DATA;
+      end
+    end
+    `SP_D0_D1_READ_FIFO:
+    begin
+      next_SCTxPortWEn <= 1'b1;
+      next_SCTxPortData <= fifoData;
+      next_SCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+    end
+    `SP_D0_D1_WAIT_READ_FIFO:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    end
+    `SP_D0_D1_FIFO_EMPTY:
+    begin
+      if (fifoEmpty == 1'b0)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+      end
+      else
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+      end
+    end
+    `SP_D0_D1_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_D0_D1_TERM_BYTE:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    end
+    `SP_D0_D1_CLR_WEN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+    end
+    `SP_D0_D1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvSndPkt <= `START_SP1;
+  else
+    CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    sendPacketRdy <= 1'b1;
+    fifoReadEn <= 1'b0;
+    SCTxPortData <= 8'h00;
+    SCTxPortCntl <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    fifoReadEn <= next_fifoReadEn;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.v	(revision 264)
@@ -0,0 +1,518 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (bitStuffError, clk, clrEPRdy, CRCError, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketRdy, getPacketREn, NAKSent, rst, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, sendPacketPID, sendPacketRdy, sendPacketWEn, SOFRxed, stallSent, transDone, USBEndP, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBTgtAddress);
+input   bitStuffError;
+input   clk;
+input   CRCError;
+input   getPacketRdy;
+input   rst;
+input   [7:0]RxByte;
+input   RxDataWEn;
+input   RxOverflow;
+input   [7:0]RxStatus;
+input   RxTimeOut;
+input   SCGlobalEn;
+input   sendPacketRdy;
+input   [4:0]USBEndPControlReg;
+input   [6:0]USBTgtAddress;
+output  clrEPRdy;
+output  endPMuxErrorsWEn;
+output  endPointReadyToGetPkt;
+output  [10:0]frameNum;
+output  getPacketREn;
+output  NAKSent;
+output  [3:0]sendPacketPID;
+output  sendPacketWEn;
+output  SOFRxed;
+output  stallSent;
+output  transDone;
+output  [3:0]USBEndP;
+output  [1:0]USBEndPNakTransTypeReg;
+output  [1:0]USBEndPTransTypeReg;
+
+wire    bitStuffError;
+wire    clk;
+reg     clrEPRdy, next_clrEPRdy;
+wire    CRCError;
+reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg     endPointReadyToGetPkt, next_endPointReadyToGetPkt;
+reg     [10:0]frameNum, next_frameNum;
+wire    getPacketRdy;
+reg     getPacketREn, next_getPacketREn;
+reg     NAKSent, next_NAKSent;
+wire    rst;
+wire    [7:0]RxByte;
+wire    RxDataWEn;
+wire    RxOverflow;
+wire    [7:0]RxStatus;
+wire    RxTimeOut;
+wire    SCGlobalEn;
+reg     [3:0]sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     SOFRxed, next_SOFRxed;
+reg     stallSent, next_stallSent;
+reg     transDone, next_transDone;
+reg     [3:0]USBEndP, next_USBEndP;
+wire    [4:0]USBEndPControlReg;
+reg     [1:0]USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg     [1:0]USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+wire    [6:0]USBTgtAddress;
+
+// diagram signals declarations
+reg  [7:0]addrEndPTemp, next_addrEndPTemp;
+reg  [7:0]endpCRCTemp, next_endpCRCTemp;
+reg  [7:0]PIDByte, next_PIDByte;
+reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+reg  [6:0]USBAddress, next_USBAddress;
+reg  [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define SETUP_OUT_CHK 5'b01011
+`define SETUP_OUT_SEND 5'b01100
+`define SETUP_OUT_GET_PKT 5'b01101
+`define START_S1 5'b01110
+`define GET_TOKEN_DELAY 5'b01111
+`define GET_TOKEN_CHK_ADDR 5'b10000
+`define IN_RESP_GET_RESP 5'b10001
+`define IN_RESP_DATA 5'b10010
+`define IN_RESP_CHK_ISO 5'b10011
+
+reg [4:0]CurrState_slvCntrl, NextState_slvCntrl;
+
+
+// Machine: slvCntrl
+
+// NextState logic (combinatorial)
+always @ (RxDataWEn or RxStatus or CRCError or bitStuffError or RxOverflow or RxTimeOut or RxByte or PIDByte or endpCRCTemp or addrEndPTemp or USBEndPControlRegCopy or tempUSBEndPTransTypeReg or NAKSent or sendPacketRdy or getPacketRdy or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or USBEndPControlReg or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or frameNum or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or getPacketREn or endPointReadyToGetPkt or CurrState_slvCntrl)
+begin
+  NextState_slvCntrl <= CurrState_slvCntrl;
+  // Set default values for outputs and signals
+  next_stallSent <= stallSent;
+  next_NAKSent <= NAKSent;
+  next_SOFRxed <= SOFRxed;
+  next_PIDByte <= PIDByte;
+  next_transDone <= transDone;
+  next_clrEPRdy <= clrEPRdy;
+  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+  next_endpCRCTemp <= endpCRCTemp;
+  next_addrEndPTemp <= addrEndPTemp;
+  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+  next_frameNum <= frameNum;
+  next_USBAddress <= USBAddress;
+  next_USBEndP <= USBEndP;
+  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  next_getPacketREn <= getPacketREn;
+  next_USBEndPControlRegCopy <= USBEndPControlRegCopy;
+  next_endPointReadyToGetPkt <= endPointReadyToGetPkt;
+  case (CurrState_slvCntrl)  // synopsys parallel_case full_case
+    `WAIT_RX1:
+    begin
+      next_stallSent <= 1'b0;
+      next_NAKSent <= 1'b0;
+      next_SOFRxed <= 1'b0;
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_START && 
+        RxByte[1:0] == `TOKEN)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+        next_PIDByte <= RxByte;
+      end
+    end
+    `FIN_SC:
+    begin
+      next_transDone <= 1'b0;
+      next_clrEPRdy <= 1'b0;
+      next_endPMuxErrorsWEn <= 1'b0;
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_PID:
+    begin
+      if (PIDByte[3:0] == `SETUP)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if (PIDByte[3:0] == `OUT)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `IN_CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+      else if (PIDByte[3:0] == `IN)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `PID_ERROR;
+      end
+    end
+    `PID_ERROR:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_RDY:
+    begin
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_transDone <= 1'b1;
+        next_clrEPRdy <= 1'b1;
+        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else if (NAKSent == 1'b1)
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+      end
+    end
+    `SETUP_OUT_CHK:
+    begin
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    end
+    `SETUP_OUT_SEND:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `SETUP_OUT_GET_PKT:
+    begin
+      next_getPacketREn <= 1'b0;
+      if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+      else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+        bitStuffError == 1'b0 && 
+        RxOverflow == 1'b0 && 
+        RxTimeOut == 1'b0))
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_CHK;
+      end
+      else if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_NAK_STALL:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_CHK_RDY:
+    begin
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    end
+    `IN_RESP_GET_RESP:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+    end
+    `IN_RESP_DATA:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)
+      begin
+        NextState_slvCntrl <= `IN_RESP_CHK_ISO;
+      end
+    end
+    `IN_RESP_CHK_ISO:
+    begin
+      if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_GET_RESP;
+        next_getPacketREn <= 1'b1;
+      end
+    end
+    `START_S1:
+    begin
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `GET_TOKEN_WAIT_CRC:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+        next_endpCRCTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_ADDR:
+    begin
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+        next_addrEndPTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_WAIT_STOP:
+    begin
+      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RxByte [`RX_OVERFLOW_BIT] == 1'b0))
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+      end
+      else if (RxDataWEn == 1'b1)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+    `GET_TOKEN_CHK_SOF:
+    begin
+      if (PIDByte[3:0] == `SOF)
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+        next_SOFRxed <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_DELAY;
+        next_USBAddress <= addrEndPTemp[6:0];
+        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+      end
+    end
+    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndP etc to update
+    begin
+      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+    end
+    `GET_TOKEN_CHK_ADDR:
+    begin
+      if (USBEndP < `NUM_OF_ENDPOINTS  &&
+        USBAddress == USBTgtAddress &&
+        SCGlobalEn == 1'b1 &&
+        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)
+      begin
+        NextState_slvCntrl <= `CHK_PID;
+        next_USBEndPControlRegCopy <= USBEndPControlReg;
+        next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
+      end
+      else
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvCntrl <= `START_S1;
+  else
+    CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    stallSent <= 1'b0;
+    NAKSent <= 1'b0;
+    SOFRxed <= 1'b0;
+    transDone <= 1'b0;
+    clrEPRdy <= 1'b0;
+    endPMuxErrorsWEn <= 1'b0;
+    frameNum <= 11'b00000000000;
+    USBEndP <= 4'h0;
+    USBEndPTransTypeReg <= 2'b00;
+    USBEndPNakTransTypeReg <= 2'b00;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    getPacketREn <= 1'b0;
+    endPointReadyToGetPkt <= 1'b0;
+    PIDByte <= 8'h00;
+    endpCRCTemp <= 8'h00;
+    addrEndPTemp <= 8'h00;
+    tempUSBEndPTransTypeReg <= 2'b00;
+    USBAddress <= 7'b0000000;
+    USBEndPControlRegCopy <= 5'b00000;
+  end
+  else 
+  begin
+    stallSent <= next_stallSent;
+    NAKSent <= next_NAKSent;
+    SOFRxed <= next_SOFRxed;
+    transDone <= next_transDone;
+    clrEPRdy <= next_clrEPRdy;
+    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+    frameNum <= next_frameNum;
+    USBEndP <= next_USBEndP;
+    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+    getPacketREn <= next_getPacketREn;
+    endPointReadyToGetPkt <= next_endPointReadyToGetPkt;
+    PIDByte <= next_PIDByte;
+    endpCRCTemp <= next_endpCRCTemp;
+    addrEndPTemp <= next_addrEndPTemp;
+    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+    USBAddress <= next_USBAddress;
+    USBEndPControlRegCopy <= next_USBEndPControlRegCopy;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.asf	(revision 264)
@@ -0,0 +1,408 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=863
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 102610,273136 1 0 0 "Module: slavecontroller"
+F 6 0 671089152 282 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "slvCntrl"
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START"
+S 15 6 77828 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111713,189976 6500 6500
+L 272 271 0 TEXT "Labels" | 186628,209022 1 0 0 "getPacketREn"
+I 273 0 130 Builtin InPort | 182869,214288 "" ""
+L 274 273 0 TEXT "Labels" | 190399,213982 1 0 0 "getPacketRdy"
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+C 285 97 0 TEXT "Conditions" | 99944,129593 1 0 0 "rst"
+W 546 6 8194 531 81 BEZIER "Transitions" | 193355,54360 193121,48042 196557,33707 194740,28964\
+                                           192923,24221 173766,19421 163644,19865 153522,20309\
+                                           122483,20608 111915,23020 101347,25432 81761,37919\
+                                           69710,37919
+C 547 546 0 TEXT "Conditions" | 180628,44450 1 0 0 "NAKSent == 1'b1"
+A 548 546 16 TEXT "Actions" | 104043,25328 1 0 0 "USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+W 550 6 0 81 41 BEZIER "Transitions" | 57945,41731 51978,46294 36355,53695 33342,69899\
+                                       30330,86104 25492,143212 35905,156667 46318,170122\
+                                       96612,168665 117496,167729
+H 559 551 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3275 212900,251275
+S 551 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63527,72146 6500 6500
+L 554 551 0 TEXT "State Labels" | 63527,72146 1 0 0 "SETUP_OUT"
+L 819 820 0 TEXT "State Labels" | 67420,66064 1 0 0 "RESP"
+S 820 589 102404 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 67420,66064 6500 6500
+H 821 820 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 828 821 2 847 833 BEZIER "Transitions" | 143788,176826 110094,161523 73824,121282 61589,104841
+A 829 828 16 TEXT "Actions" | 74668,133998 1 0 0 "getPacketREn <= 1'b1;"
+W 830 821 1 847 832 BEZIER "Transitions" | 149052,177611 172803,163396 180803,116530 192775,92880
+C 831 830 0 TEXT "Conditions" | 112905,152704 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+I 832 821 0 Builtin Exit | 195662,92880
+S 833 821 106496 ELLIPSE "States" | 56676,100586 6500 6500
+L 834 833 0 TEXT "State Labels" | 56676,100586 1 0 0 "GET_RESP\n/17/"
+S 839 821 110592 ELLIPSE "States" | 49830,194919 6500 6500
+L 840 839 0 TEXT "State Labels" | 49830,194919 1 0 0 "DATA\n/18/"
+A 843 833 4 TEXT "Actions" | 70674,110022 1 0 0 "getPacketREn <= 1'b0;"
+W 844 821 0 839 847 BEZIER "Transitions" | 51640,188679 108408,173735 108918,187523 139645,180358
+C 845 844 0 TEXT "Conditions" | 79180,187273 1 0 0 "sendPacketRdy == 1'b1"
+A 846 839 4 TEXT "Actions" | 65120,205455 1 0 0 "sendPacketWEn <= 1'b0;"
+S 847 821 114688 ELLIPSE "States" | 145546,183083 6500 6500
+I 862 0 2 Builtin OutPort | 120122,261308 "" ""
+L 861 862 0 TEXT "Labels" | 126122,261308 1 0 0 "endPointReadyToGetPkt"
+A 860 457 16 TEXT "Actions" | 93778,19821 1 0 0 "USBEndPControlRegCopy <= USBEndPControlReg;\nendPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT] ;"
+I 859 0 130 Builtin Signal | 35412,208838 "" ""
+L 858 859 0 TEXT "Labels" | 38412,208838 1 0 0 "USBEndPControlRegCopy[4:0]"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+I 587 589 0 Builtin Exit | 192962,45432
+I 588 589 0 Builtin Entry | 205195,243792
+L 848 847 0 TEXT "State Labels" | 145546,183083 1 0 0 "CHK_ISO\n/19/"
+I 850 821 0 Builtin Entry | 49920,240120
+W 851 821 0 850 839 BEZIER "Transitions" | 49920,237971 49996,228608 49199,210758 49275,201395
+W 852 589 1 800 605 BEZIER "Transitions" | 112033,243004 131211,241916 168722,239928 178018,237332\
+                                           187314,234737 186141,226528 176133,223346 166125,220164\
+                                           127582,215026 108152,212765
+C 853 852 0 TEXT "Conditions" | 112257,227462 1 0 0 "USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0"
+W 854 821 0 833 832 BEZIER "Transitions" | 63119,99731 96001,98583 159828,94028 192710,92880
+C 855 854 0 TEXT "Conditions" | 79768,96292 1 0 0 "getPacketRdy == 1'b1"
+W 856 589 0 820 587 BEZIER "Transitions" | 73765,64656 103240,60314 160481,49774 189956,45432
+S 596 589 49152 ELLIPSE "States" | 180409,114797 6500 6500
+L 597 596 0 TEXT "State Labels" | 181443,115599 1 0 0 "NAK_STALL\n/9/"
+C 598 600 0 TEXT "Conditions" | 169310,83968 1 0 0 "sendPacketRdy == 1'b1"
+A 599 601 16 TEXT "Actions" | 160934,183503 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 600 589 8192 596 587 BEZIER "Transitions" | 180237,108305 188996,66496 180453,87386 196184,45432
+W 601 589 8193 605 596 BEZIER "Transitions" | 108219,211536 117760,212835 193154,194500 186733,113295
+A 603 596 4 TEXT "Actions" | 173404,104745 1 0 0 "sendPacketWEn <= 1'b0;"
+L 604 605 0 TEXT "State Labels" | 101725,211799 1 0 0 "CHK_RDY\n/10/"
+S 605 589 53248 ELLIPSE "States" | 101725,211799 6500 6500
+W 606 589 0 588 800 BEZIER "Transitions" | 201176,243744 189026,243939 117602,246614 110257,246222
+C 607 601 0 TEXT "Conditions" | 120473,202106 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 612 589 8194 605 596 BEZIER "Transitions" | 102126,205324 97268,194370 163866,132884 176477,119972
+W 613 589 8195 605 617 BEZIER "Transitions" | 96173,208420 81310,204985 61686,186612 53042,177585
+C 614 612 0 TEXT "Conditions" | 62794,182643 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 615 612 16 TEXT "Actions" | 138346,155279 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 619 618 0 Builtin Entry | 96520,152400
+I 620 618 0 Builtin Exit | 144780,101600
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 630 589 8193 617 820 BEZIER "Transitions" | 48004,172793 44616,170945 44594,164562 42823,162021\
+                                              41052,159480 41752,153900 40959,141711 40167,129522\
+                                              46701,89176 50135,78506 53570,67837 54978,65340\
+                                              57981,65109 60984,64878 60458,64813 61074,64659
+W 631 589 8194 617 820 BEZIER "Transitions" | 54078,173688 59930,171532 83885,163128 122946,146882\
+                                              162008,130636 151291,117855 140238,106874 129185,95894\
+                                              77774,78896 71279,71294
+C 636 630 0 TEXT "Conditions" | 35003,128975 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+A 637 630 16 TEXT "Actions" | 47297,102245 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 638 631 16 TEXT "Actions" | 117990,107831 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+I 96 722 0 Builtin Reset | 76296,129336
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+S 376 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 380 377 0 Builtin Entry | 48940,236580
+I 381 377 0 Builtin Exit | 206487,14249
+I 649 559 0 Builtin Entry | 37971,243103
+I 650 559 0 Builtin Exit | 194044,45058
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+C 652 651 0 TEXT "Conditions" | 116707,136533 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+S 654 559 61440 ELLIPSE "States" | 92422,152802 6500 6500
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/11/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+I 399 377 0 Builtin Link | 54419,17564
+S 656 559 65536 ELLIPSE "States" | 109789,85208 5889 6500
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/12/"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+                                              46511,172964 33727,90292 34975,71611 36223,52930\
+                                              35724,34993 37785,28932 39847,22872 46307,16188\
+                                              54419,15564
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+                                              60053,165183 57484,160822 55722,148570 53960,136319\
+                                              36935,95064 38880,77714 40826,60365 38327,20823\
+                                              54419,15564
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+                                           108160,233400 112640,227800 113920,224400 115200,221000\
+                                           116013,213096 116333,209096
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 422 421 0 Builtin Entry | 96520,152400
+I 423 421 0 Builtin Exit | 144780,101600
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+                                              69948,104476 47394,95074 43302,84878 39210,74682\
+                                              42917,24960 54419,15564
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/13/"
+S 690 559 69632 ELLIPSE "States" | 98991,238090 6500 6500
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+W 692 559 8194 698 654 BEZIER "Transitions" | 115978,206479 88070,190212 85643,190437 93781,159154
+C 693 692 0 TEXT "Conditions" | 66756,183110 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+                                              39220,148925 36609,140943 36571,133460 36533,125977\
+                                              38989,104026 47738,97617 56488,91209 87662,87731\
+                                              103933,85889
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 696 559 8195 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+                                              200304,203038 205920,186346 207441,167119 208962,147892\
+                                              209430,87676 208962,71608 208494,55540 206154,51484\
+                                              204438,50041 202722,48598 199528,45916 197266,45058
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+S 698 559 73748 ELLIPSE "Junction" | 117000,209824 3500 3500
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 700 699 0 Builtin Entry | 96520,152400
+I 701 699 0 Builtin Exit | 144780,101600
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+S 462 377 94208 ELLIPSE "States" | 94684,51331 6500 6500
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/16/"
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 723 722 81920 ELLIPSE "States" | 120650,127000 6500 6500
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/14/"
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;\nUSBEndPControlRegCopy <= 5'b00000;\nendPointReadyToGetPkt <= 1'b0;"
+I 726 722 0 Builtin Entry | 96520,152400
+I 727 722 0 Builtin Exit | 144780,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+C 468 457 0 TEXT "Conditions" | 82804,40533 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS  &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[4:0]"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+                                              46860,73975 46530,57145 47396,48771 48262,40398\
+                                              52522,23896 54419,15564
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+                                           209214,43082 209522,23062 208983,17094 208444,11127\
+                                           205980,7277 191773,6353 177567,5429 123205,5583\
+                                           106804,9317 90403,13052 79161,27836 75696,31763\
+                                           72231,35690 70888,36159 69579,36621
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+                                              53866,34676 56339,23332 57169,17564
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+                                            60717,97705 62441,84600 62616,78575
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+                                            105236,81091 81842,75191 69908,73378
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/15/"
+S 786 377 90112 ELLIPSE "States" | 123152,53144 6500 6500
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+K 788 786 0 TEXT "Comments" | 122196,51478 1 0 0 "Insert delay to allow USBEndP etc to update"
+W 790 559 1 698 650 BEZIER "Transitions" | 120235,208489 139440,201809 176211,187874 186899,181444\
+                                           197587,175015 201929,162657 202973,147251 204017,131846\
+                                           203849,82580 202847,68719 201846,54859 198970,48147\
+                                           197050,45058
+C 791 790 0 TEXT "Conditions" | 102423,188540 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+C 535 532 0 TEXT "Conditions" | 69699,59883 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+H 805 800 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 800 589 98324 ELLIPSE "Junction" | 108538,243174 3500 3500
+L 801 800 0 TEXT "State Labels" | 108538,243174 1 0 0 "J4"
+W 802 805 0 804 803 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+I 803 805 0 Builtin Exit | 144780,101600
+I 804 805 0 Builtin Entry | 96520,152400
+W 807 589 2 800 617 BEZIER "Transitions" | 106097,240666 80398,219718 50449,190675 50573,178391
+W 810 589 3 800 587 BEZIER "Transitions" | 105040,243281 73377,254491 34925,221320 34178,196665\
+                                           33432,172010 34721,79558 53522,54375 72324,29193\
+                                           153226,30396 173104,33029 192983,35662 193169,40577\
+                                           192962,43440
+C 812 807 0 TEXT "Conditions" | 65637,235739 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlaveWrap.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlaveWrap.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlaveWrap.v	(revision 264)
@@ -0,0 +1,195 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlaveWrap.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. Enable connection to Altera Avalon bus
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+
+module usbHostSlaveWrap(
+  clk, 
+  reset,
+  address, 
+  writedata, 
+  readdata, 
+  write, 
+  read,
+  waitrequest,
+  chipselect,
+  irq, 
+  usbClk,
+  USBWireVPI,
+  USBWireVMI,
+  USBWireDataInTick,
+  USBWireVPO,
+  USBWireVMO,
+  USBWireDataOutTick,
+  USBWireOutEn_n,
+  USBFullSpeed
+   );
+
+input clk;
+input reset;
+input [7:0] address; 
+input [7:0] writedata; 
+output [7:0] readdata; 
+input write; 
+input read;
+output waitrequest;
+input chipselect;
+output irq; 
+input usbClk;
+input USBWireVPI;
+input USBWireVMI;
+output USBWireVPO;
+output USBWireVMO;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireOutEn_n;
+output USBFullSpeed;
+
+wire clk;
+wire reset;
+wire [7:0] address; 
+wire [7:0] writedata; 
+wire [7:0] readdata; 
+wire write; 
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire usbClk;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+
+//internal wiring 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+             hostResumeIntOut | hostTransDoneIntOut |
+             slaveSOFRxedIntOut | slaveResetEventIntOut |
+             slaveResumeIntOut | slaveTransDoneIntOut |
+             slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut; 
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+//Parameters declaration: 
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+  .clk_i(clk),
+  .rst_i(reset),
+  .address_i(address),
+  .data_i(writedata),
+  .data_o(readdata),
+  .we_i(write),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .usbClk(usbClk),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlaveWrap.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.v	(revision 264)
@@ -0,0 +1,481 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processTxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (clk, JBit, KBit, processTxByteRdy, processTxByteWEn, rst, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn);
+input   clk;
+input   [1:0]JBit;
+input   [1:0]KBit;
+input   processTxByteWEn;
+input   rst;
+input   [7:0]TxByteCtrlIn;
+input   TxByteFullSpeedRateIn;
+input   [7:0]TxByteIn;
+input   USBWireGnt;
+input   USBWireRdy;
+output  processTxByteRdy;
+output  USBWireCtrl;
+output  [1:0]USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+
+wire    clk;
+wire    [1:0]JBit;
+wire    [1:0]KBit;
+reg     processTxByteRdy, next_processTxByteRdy;
+wire    processTxByteWEn;
+wire    rst;
+wire    [7:0]TxByteCtrlIn;
+wire    TxByteFullSpeedRateIn;
+wire    [7:0]TxByteIn;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0]USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg  [3:0]i, next_i;
+reg  [7:0]TxByte, next_TxByte;
+reg  [7:0]TxByteCtrl, next_TxByteCtrl;
+reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;
+reg  [1:0]TXLineState, next_TXLineState;
+reg  [3:0]TXOneCount, next_TXOneCount;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+`define LS_START_W_RDY1 5'b10110
+`define LS_START_W_RDY2 5'b10111
+`define LS_START_W_RDY3 5'b11000
+`define STOP_W_RDY1 5'b11001
+`define STOP_W_RDY2 5'b11010
+`define STOP_W_RDY3 5'b11011
+`define STOP_W_RDY4 5'b11100
+
+reg [4:0]CurrState_prcTxB, NextState_prcTxB;
+
+
+// Machine: prcTxB
+
+// NextState logic (combinatorial)
+always @ (processTxByteWEn or TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or i or TxByte or TXOneCount or KBit or JBit or USBWireRdy or TXLineState or USBWireGnt or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or TxByteFullSpeedRate or CurrState_prcTxB)
+begin
+  NextState_prcTxB <= CurrState_prcTxB;
+  // Set default values for outputs and signals
+  next_processTxByteRdy <= processTxByteRdy;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_USBWireReq <= USBWireReq;
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_TxByte <= TxByte;
+  next_TxByteCtrl <= TxByteCtrl;
+  next_TXLineState <= TXLineState;
+  next_TXOneCount <= TXOneCount;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
+  case (CurrState_prcTxB)  // synopsys parallel_case full_case
+    `START_PTBY:
+    begin
+      next_processTxByteRdy <= 1'b0;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_i <= 4'h0;
+      next_TxByte <= 8'h00;
+      next_TxByteCtrl <= 8'h00;
+      next_TXLineState <= 2'b0;
+      next_TXOneCount <= 4'h0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      next_TxByteFullSpeedRate <= 1'b0;
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `PTBY_WAIT_EN:
+    begin
+      next_processTxByteRdy <= 1'b1;
+      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_GNT;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_TXOneCount <= 4'h0;
+        next_TXLineState <= JBit;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (processTxByteWEn == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_i <= 4'h0;
+      end
+    end
+    `PTBY_WAIT_GNT:
+    begin
+      if (USBWireGnt == 1'b1)
+      begin
+        NextState_prcTxB <= `WAIT_RDY_WIRE;
+      end
+    end
+    `WAIT_RDY_WIRE:
+    begin
+      if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate  == 1'b0))
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE1;
+      end
+      else if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `WAIT_RDY_PKT;
+        //actively drive the first J bit
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    end
+    `WAIT_RDY_PKT:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `SEND_BYTE_UPDATE_BYTE:
+    begin
+      next_i <= i + 1'b1;
+      next_TxByte <= {1'b0, TxByte[7:1] };
+      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
+      next_TXOneCount <= TXOneCount + 1'b1;
+      //increment 'TXOneCount'
+      else                                        //else this is a zero bit
+      begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      end
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+    end
+    `SEND_BYTE_WAIT_RDY:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (TXOneCount == `MAX_CONSEC_SAME_BITS)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+      end
+      else if (i != 4'h8)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+      else
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+    end
+    `SEND_BYTE_BIT_STUFF:
+    begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+      next_TXLineState <= KBit;
+      //toggle the line state
+      else
+      next_TXLineState <= JBit;
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+    end
+    `SEND_BYTE_WAIT_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `SEND_BYTE_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (i == 4'h8)
+      begin
+        NextState_prcTxB <= `STOP_CHK;
+      end
+      else
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      end
+    end
+    `STOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY2;
+    end
+    `STOP_SND_SE0_1:
+    begin
+      NextState_prcTxB <= `STOP_W_RDY1;
+    end
+    `STOP_CHK:
+    begin
+      if (TxByteCtrl == `DATA_STOP)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_1;
+      end
+      else
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_EN;
+      end
+    end
+    `STOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY3;
+    end
+    `STOP_SND_IDLE:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY4;
+    end
+    `STOP_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      //release the wire
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `STOP_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_J;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_SND_IDLE;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+    `STOP_W_RDY4:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `STOP_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_SND_IDLE3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY2;
+    end
+    `LS_START_SND_J1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY3;
+    end
+    `LS_START_SND_IDLE1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_SND_IDLE2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY1;
+    end
+    `LS_START_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `LS_START_W_RDY1:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE3;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_W_RDY2:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_SND_J1;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    end
+    `LS_START_W_RDY3:
+    begin
+      if (USBWireRdy == 1'b1)
+      begin
+        NextState_prcTxB <= `LS_START_FIN;
+        //Drive the first JBit
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_prcTxB <= `START_PTBY;
+  else
+    CurrState_prcTxB <= NextState_prcTxB;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    processTxByteRdy <= 1'b0;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    USBWireReq <= 1'b0;
+    USBWireWEn <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+    i <= 4'h0;
+    TxByte <= 8'h00;
+    TxByteCtrl <= 8'h00;
+    TXLineState <= 2'b0;
+    TXOneCount <= 4'h0;
+    TxByteFullSpeedRate <= 1'b0;
+  end
+  else 
+  begin
+    processTxByteRdy <= next_processTxByteRdy;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    USBWireReq <= next_USBWireReq;
+    USBWireWEn <= next_USBWireWEn;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+    i <= next_i;
+    TxByte <= next_TxByte;
+    TxByteCtrl <= next_TxByteCtrl;
+    TXLineState <= next_TXLineState;
+    TXOneCount <= next_TXOneCount;
+    TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC16.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC16.v	(revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC16.v                                                ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [15:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [15:0] CRCResult;
+reg    ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 16'hffff;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0)
+    begin
+      if (CRCEn == 1'b1) begin
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        ready <= 1'b0;
+    end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[15:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == 4'h7)
+      begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(revision 264)
@@ -0,0 +1,208 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbTxWireArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst, SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn);
+input   clk;
+input   prcTxByteCtrl;
+input   [1:0]prcTxByteData;
+input   prcTxByteFSRate;
+input   prcTxByteReq;
+input   prcTxByteWEn;
+input   rst;
+input   SIETxCtrl;
+input   [1:0]SIETxData;
+input   SIETxFSRate;
+input   SIETxReq;
+input   SIETxWEn;
+input   USBWireRdyIn;
+output  prcTxByteGnt;
+output  SIETxGnt;
+output  [1:0]TxBits;
+output  TxCtl;
+output  TxFSRate;
+output  USBWireRdyOut;
+output  USBWireWEn;
+
+wire    clk;
+wire    prcTxByteCtrl;
+wire    [1:0]prcTxByteData;
+wire    prcTxByteFSRate;
+reg     prcTxByteGnt, next_prcTxByteGnt;
+wire    prcTxByteReq;
+wire    prcTxByteWEn;
+wire    rst;
+wire    SIETxCtrl;
+wire    [1:0]SIETxData;
+wire    SIETxFSRate;
+reg     SIETxGnt, next_SIETxGnt;
+wire    SIETxReq;
+wire    SIETxWEn;
+reg     [1:0]TxBits, next_TxBits;
+reg     TxCtl, next_TxCtl;
+reg     TxFSRate, next_TxFSRate;
+wire    USBWireRdyIn;
+reg     USBWireRdyOut, next_USBWireRdyOut;
+reg     USBWireWEn, next_USBWireWEn;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0]CurrState_txWireArb, NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
+SIETxFSRate or prcTxByteFSRate)
+begin
+if (muxSIENotPTXB  == 1'b1)
+begin
+USBWireWEn <= SIETxWEn;
+TxBits <= SIETxData;
+TxCtl <= SIETxCtrl;
+TxFSRate <= SIETxFSRate;
+end
+else
+begin
+USBWireWEn <= prcTxByteWEn;
+TxBits <= prcTxByteData;
+TxCtl <= prcTxByteCtrl;
+TxFSRate <= prcTxByteFSRate;
+end
+end
+
+
+// Machine: txWireArb
+
+// NextState logic (combinatorial)
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or SIETxGnt or muxSIENotPTXB or CurrState_txWireArb)
+begin
+  NextState_txWireArb <= CurrState_txWireArb;
+  // Set default values for outputs and signals
+  next_prcTxByteGnt <= prcTxByteGnt;
+  next_SIETxGnt <= SIETxGnt;
+  next_muxSIENotPTXB <= muxSIENotPTXB;
+  case (CurrState_txWireArb)  // synopsys parallel_case full_case
+    `START_TARB:
+    begin
+      NextState_txWireArb <= `TARB_WAIT_REQ;
+    end
+    `TARB_WAIT_REQ:
+    begin
+      if (prcTxByteReq == 1'b1)
+      begin
+        NextState_txWireArb <= `PTXB_ACT;
+        next_prcTxByteGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b0;
+      end
+      else if (SIETxReq == 1'b1)
+      begin
+        NextState_txWireArb <= `SIE_TX_ACT;
+        next_SIETxGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b1;
+      end
+    end
+    `PTXB_ACT:
+    begin
+      if (prcTxByteReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_prcTxByteGnt <= 1'b0;
+      end
+    end
+    `SIE_TX_ACT:
+    begin
+      if (SIETxReq == 1'b0)
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_SIETxGnt <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_txWireArb <= `START_TARB;
+  else
+    CurrState_txWireArb <= NextState_txWireArb;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    prcTxByteGnt <= 1'b0;
+    SIETxGnt <= 1'b0;
+    muxSIENotPTXB <= 1'b0;
+  end
+  else 
+  begin
+    prcTxByteGnt <= next_prcTxByteGnt;
+    SIETxGnt <= next_SIETxGnt;
+    muxSIENotPTXB <= next_muxSIENotPTXB;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/fifoMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/fifoMux.v	(revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module fifoMux (
+  currEndP,
+  //TxFifo
+  TxFifoREn,
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoData,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEmpty,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  //RxFifo
+  RxFifoWEn,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoFull,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+  //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+  //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+  TxFifoREn or
+  RxFifoWEn or
+  TxFifoEP0Data or
+  TxFifoEP1Data or
+  TxFifoEP2Data or
+  TxFifoEP3Data or
+  TxFifoEP0Empty or
+  TxFifoEP1Empty or
+  TxFifoEP2Empty or
+  TxFifoEP3Empty or
+  RxFifoEP0Full or
+  RxFifoEP1Full or
+  RxFifoEP2Full or
+  RxFifoEP3Full)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      TxFifoEP0REn <= TxFifoREn;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP0Data;
+      TxFifoEmpty <= TxFifoEP0Empty;
+      RxFifoEP0WEn <= RxFifoWEn;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP0Full;
+    end
+    2'b01: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= TxFifoREn;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP1Data;
+      TxFifoEmpty <= TxFifoEP1Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= RxFifoWEn;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP1Full;
+    end
+    2'b10: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= TxFifoREn;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP2Data;
+      TxFifoEmpty <= TxFifoEP2Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= RxFifoWEn;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP2Full;
+    end
+    2'b11: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= TxFifoREn;
+      TxFifoData <= TxFifoEP3Data;
+      TxFifoEmpty <= TxFifoEP3Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= RxFifoWEn;
+      RxFifoFull <= RxFifoEP3Full;
+    end
+  endcase  
+end      
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.v	(revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveDirectControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (clk, directControlEn, directControlLineState, rst, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn);
+input   clk;
+input   directControlEn;
+input   [1:0]directControlLineState;
+input   rst;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+output  [7:0]SCTxPortCntl;
+output  [7:0]SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+
+wire    clk;
+wire    directControlEn;
+wire    [1:0]directControlLineState;
+wire    rst;
+reg     [7:0]SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0]SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0]CurrState_slvDrctCntl, NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: slvDrctCntl
+
+// NextState logic (combinatorial)
+always @ (directControlEn or SCTxPortGnt or SCTxPortRdy or directControlLineState or SCTxPortCntl or SCTxPortData or SCTxPortWEn or SCTxPortReq or CurrState_slvDrctCntl)
+begin
+  NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+  // Set default values for outputs and signals
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortReq <= SCTxPortReq;
+  case (CurrState_slvDrctCntl)  // synopsys parallel_case full_case
+    `START_SDC:
+    begin
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `CHK_DRCT_CNTL:
+    begin
+      if (directControlEn == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+    end
+    `DRCT_CNTL_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)
+      begin
+        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+        next_SCTxPortReq <= 1'b0;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+      end
+    end
+    `DRCT_CNTL_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= {6'b000000, directControlLineState};
+        next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    end
+    `IDLE_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      next_SCTxPortReq <= 1'b0;
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+    begin
+      if (SCTxPortGnt == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+      end
+    end
+    `IDLE_WAIT_RDY:
+    begin
+      if (SCTxPortRdy == 1'b1)
+      begin
+        NextState_slvDrctCntl <= `IDLE_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_IDLE;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst)
+    CurrState_slvDrctCntl <= `START_SDC;
+  else
+    CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst)
+  begin
+    SCTxPortCntl <= 8'h00;
+    SCTxPortData <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.asf	(revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveSendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
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+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
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+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
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+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "SP_WAIT_ENABLE\n/1/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP1\n/0/"
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
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+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nSCTxPortReq <= 1'b1;"
+L 20 21 0 TEXT "State Labels" | 113767,93734 1 0 0 "SP_SEND_PID"
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113767,93734 6500 6500
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 112951,104607 113260,100204
+C 23 22 0 TEXT "Conditions" | 114630,116691 1 0 0 "SCTxPortGnt == 1'b1"
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 29624,2084 214124,250084
+S 26 25 16384 ELLIPSE "States" | 72734,192072 6500 6500
+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
+I 28 25 0 Builtin Entry | 49237,230379
+I 29 25 0 Builtin Exit | 146004,95604
+W 30 25 0 28 26 BEZIER "Transitions" | 53779,230379 60054,220138 63123,209223 69341,197615
+L 32 33 0 TEXT "State Labels" | 75021,153035 1 0 0 "FIN\n/4/"
+S 33 25 20480 ELLIPSE "States" | 75021,153035 6500 6500
+W 34 25 0 26 33 BEZIER "Transitions" | 72953,185597 73302,178879 73960,166205 74309,159487
+C 36 34 0 TEXT "Conditions" | 75236,185214 1 0 0 "SCTxPortRdy == 1'b1"
+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
+A 38 33 4 TEXT "Actions" | 93627,154331 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 39 25 0 33 29 BEZIER "Transitions" | 79375,148210 95944,135371 126275,108443 142844,95604
+L 44 45 0 TEXT "State Labels" | 182202,45960 1 0 0 "SP_D0_D1"
+S 45 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,45960 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
+S 47 6 28672 ELLIPSE "States" | 115848,16910 6500 6500
+W 48 6 8194 21 205 BEZIER "Transitions" | 108645,89734 97773,80901 77133,63853 66261,55020
+W 50 6 8193 21 45 BEZIER "Transitions" | 119169,90120 134042,80003 162156,60011 177029,49894
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+W 73 6 0 45 47 BEZIER "Transitions" | 176581,42697 162161,37714 135904,25306 121888,19311
+W 74 6 0 205 47 BEZIER "Transitions" | 67096,47093 78647,41129 99521,27639 110324,20335
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 127 65 0 Builtin Exit | 176933,37229
+I 126 65 0 Builtin Entry | 68162,237252
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1;	 \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
+S 136 65 32768 ELLIPSE "States" | 97326,133352 6500 6500
+W 128 65 0 126 145 BEZIER "Transitions" | 72704,237252 77515,245311 99394,235265 108723,227500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170187,37688 173773,37229
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "SCTxPortWEn"
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
+W 210 65 0 207 145 BEZIER "Transitions" | 169895,125680 176804,126013 188953,127552 193864,130465\
+                                          198775,133379 204604,144369 205686,152818 206768,161268\
+                                          205269,184079 201481,192903 197694,201727 184040,214216\
+                                          173218,217462 162396,220708 133810,221642 118992,221891
+W 209 65 0 136 207 BEZIER "Transitions" | 103712,132145 117531,130730 143304,126529 157123,125114
+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 76973,151815 1 0 0 "CLR_REN\n/13/"
+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+END

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/usbSlaveControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/usbSlaveControl.v	(revision 264)
@@ -0,0 +1,510 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbSlaveControl(
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  //getPacket
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut, RxFifoData, SIERxTimeOutEn,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //SCTxPortArbiter
+  SCTxPortEn, SCTxPortRdy,
+  SCTxPortData, SCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFRxedIntOut, 
+  resetEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  NAKSentIntOut,
+  slaveControlSelect,
+  //fifoMux
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut; 
+output SIERxTimeOutEn;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [4:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut; 
+output resetEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire SIERxTimeOutEn;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut; 
+wire resetEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed; 
+wire CRCError; 
+wire RXOverflow; 
+wire RXTimeOut; 
+wire bitStuffError; 
+wire dataSequence; 
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [4:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire endPointReadyFromSlaveCtrlrToGetPkt;
+
+USBSlaveControlBI u_USBSlaveControlBI
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .SOFRxedIntOut(SOFRxedIntOut), 
+  .resetEventIntOut(resetEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .NAKSentIntOut(NAKSentIntOut),
+  .endP0TransTypeReg(endP0TransTypeReg), 
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg), 
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg), 
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg), 
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .EP0StatusReg(endP0StatusReg),
+  .EP1StatusReg(endP1StatusReg),
+  .EP2StatusReg(endP2StatusReg),
+  .EP3StatusReg(endP3StatusReg),
+  .SCAddrReg(USBTgtAddress), 
+  .frameNum(frameNum),
+  .connectStateIn(connectStateOut),
+  .SOFRxedIn(SOFRxed), 
+  .resetEventIn(resetEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .NAKSentIn(NAKSent),
+  .slaveControlSelect(slaveControlSelect),
+  .clrEP0Ready(clrEP0Rdy), 
+  .clrEP1Ready(clrEP1Rdy), 
+  .clrEP2Ready(clrEP2Rdy), 
+  .clrEP3Ready(clrEP3Rdy),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .SCGlobalEn(SCGlobalEn)
+  );
+
+slavecontroller u_slavecontroller
+  (.CRCError(CRCError), 
+  .NAKSent(NAKSent), 
+  .RxByte(RxData), 
+  .RxDataWEn(RxDataValid), 
+  .RxOverflow(RXOverflow), 
+  .RxStatus(RxByteStatus), 
+  .RxTimeOut(RXTimeOut), 
+  .SCGlobalEn(SCGlobalEn), 
+  .SOFRxed(SOFRxed), 
+  .USBEndPControlReg(endPControlReg), 
+  .USBEndPNakTransTypeReg(transTypeNAK), 
+  .USBEndPTransTypeReg(transType), 
+  .USBEndP(currEndP), 
+  .USBTgtAddress(USBTgtAddress),
+  .bitStuffError(bitStuffError), 
+  .clk(usbClk), 
+  .clrEPRdy(clrEPRdy), 
+  .endPMuxErrorsWEn(endPMuxErrorsWEn), 
+  .frameNum(frameNum), 
+  .getPacketREn(getPacketREn), 
+  .getPacketRdy(getPacketRdy), 
+  .rst(rstSyncToUsbClk), 
+  .sendPacketPID(slaveControllerPIDOut), 
+  .sendPacketRdy(slaveControllerReadyIn), 
+  .sendPacketWEn(slaveControllerWEnOut), 
+  .stallSent(stallSent), 
+  .transDone(transDone),
+  .endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
+    );
+
+
+endpMux u_endpMux (
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .currEndP(currEndP),
+  .NAKSent(NAKSent),
+  .stallSent(stallSent),
+  .CRCError(CRCError),
+  .bitStuffError(bitStuffError),
+  .RxOverflow(RXOverflow),
+  .RxTimeOut(RXTimeOut),
+  .dataSequence(dataSequence),
+  .ACKRxed(ACKRxed),
+  .transType(transType),
+  .transTypeNAK(transTypeNAK),
+  .endPControlReg(endPControlReg),
+  .clrEPRdy(clrEPRdy),
+  .endPMuxErrorsWEn(endPMuxErrorsWEn),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .endP0StatusReg(endP0StatusReg),
+  .endP1StatusReg(endP1StatusReg),
+  .endP2StatusReg(endP2StatusReg),
+  .endP3StatusReg(endP3StatusReg),
+  .endP0TransTypeReg(endP0TransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg),
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .clrEP0Rdy(clrEP0Rdy),
+  .clrEP1Rdy(clrEP1Rdy),
+  .clrEP2Rdy(clrEP2Rdy),
+  .clrEP3Rdy(clrEP3Rdy)
+    );
+
+slaveSendPacket u_slaveSendPacket
+  (.PID(slaveControllerPIDOut), 
+  .SCTxPortCntl(sendPacketCntl),
+  .SCTxPortData(sendPacketData),
+  .SCTxPortGnt(sendPacketGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(sendPacketReq),
+  .SCTxPortWEn(sendPacketWEn),
+  .clk(usbClk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .rst(rstSyncToUsbClk),
+  .sendPacketRdy(slaveControllerReadyIn),
+  .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+  (.SCTxPortCntl(directCntlCntl),
+  .SCTxPortData(directCntlData),
+  .SCTxPortGnt(directCntlGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(directCntlReq),
+  .SCTxPortWEn(directCntlWEn),
+  .clk(usbClk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rstSyncToUsbClk) ); 
+
+SCTxPortArbiter u_SCTxPortArbiter
+  (.SCTxPortCntl(SCTxPortCtrl),
+  .SCTxPortData(SCTxPortData),
+  .SCTxPortRdyIn(SCTxPortRdy),
+  .SCTxPortRdyOut(SCTxPortArbRdyOut),
+  .SCTxPortWEnable(SCTxPortEn),
+  .clk(usbClk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+
+slaveGetPacket u_slaveGetPacket
+  (.ACKRxed(ACKRxed), 
+  .CRCError(CRCError), 
+  .RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .SIERxTimeOutEn(SIERxTimeOutEn),
+  .clk(usbClk),
+  .RXOverflow(RXOverflow), 
+  .RXTimeOut(RXTimeOut), 
+  .bitStuffError(bitStuffError), 
+  .dataSequence(dataSequence), 
+  .getPacketEn(getPacketREn),
+  .rst(rstSyncToUsbClk),
+  .endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
+  ); 
+
+slaveRxStatusMonitor  u_slaveRxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .resetEventOut(resetEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk)  );    
+  
+fifoMux u_fifoMux (
+  .currEndP(currEndP),
+  //TxFifo
+  .TxFifoREn(TxFifoRE),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoData(TxFifoData),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEmpty(TxFifoEmpty),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  //RxFifo
+  .RxFifoWEn(RxFifoWE),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoFull(RxFifoFull),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+    );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/doc/README.txt
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/doc/README.txt	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/doc/README.txt	(revision 264)
@@ -0,0 +1,46 @@
+USBHostSlave has been successfully compiled using Quartus 4.2
+For some reason I have not been able to use SOPC Builder 4.2 to build the usb SOPC component
+However, SOPC Builder 4.1 generates a usable SOPC component. This may be an error on my part, I need to
+investigate further.
+USBHostSlave has been tested in a SystemC simulation, and on a Altera Nios development kit Cyclone edition.
+
+
+Release notes:
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+//             control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect 
+//             time outs, added low speed EOP keep alive. The TX bit rate is now controlled by 
+//             SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+//             speed, and TX resume is always low speed.
+//             Fixed read clock recovery (readUSBWireData.v) issue which was resulting 
+//             in missing receive packets.
+//             Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+//             by adding kludged delay to softranmit. This needs to be fixed properly.
+//             This version has undergone limited testing
+//             with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+//             with uClinux, and is known to work with a full speed USB flash stick.
+//             Moving Opencores project status from Beta to done.
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+//               Modified RX and TX fifo status registers, and removed TX fifo data count
+//               register. Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
+//               Fixed slave mode bug which caused receive fifo to
+//               be filled with incoming data when the slave was
+//               responding with a NAK, and the data should have been discarded.
+//             TODO: Test isochronous mode, and low speed mode using uClinux driver
+//                   Add frame period adjustment capability
+//                   Add compilation flags for slave only and host only versions
+//                   Create data bus width options beyond 8-bit              
+// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
+//             Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
+//             there was no detected activity on the USB data lines. This caused an infrequent
+//             misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
+//             the higher level state machines are actively looking for receive packets. 
+//             Modified USB RX data clock recovery, so that data is sampled during the middle
+//             of a USB bit period. Fixed a bug which could result in double sampling
+//             of USB RX data if clock phase adjustments were required in the middle of a 
+//             USB packet.
+
+ 
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/doc/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/buffers/RxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/buffers/RxFifo.v	(revision 264)
@@ -0,0 +1,130 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo read access via bus interface, fifo write access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: RxFifo.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module RxFifo(
+  clk, 
+  rst, 
+  fifoWEn, 
+  fifoFull,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataIn  );
+  //FIFO_DEPTH = ADDR_WIDTH^2
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire clk; 
+wire rst; 
+wire fifoWEn; 
+wire fifoFull;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(fifoDataIn), 
+  .dataOut(dataFromFifoToBus), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+RxfifoBI u_RxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .fifoDataIn(dataFromFifoToBus),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoREn(fifoREn),
+  .fifoEmpty(fifoEmpty),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/buffers/fifoMem.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/buffers/fifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/buffers/fifoMem.v	(revision 264)
@@ -0,0 +1,102 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMem.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoMem.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module fifoMem(	addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+wire [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+
+/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(
+	// Generic synchronous dual-port RAM interface
+	.rclk(clk), 
+  .rrst(1'b0), 
+  .rce(1'b1), 
+  .oe(readEn), 
+  .raddr(addrOut), 
+  .do(dataOut),
+	.wclk(clk), 
+  .wrst(1'b0), 
+  .wce(1'b1),
+  .we(writeEn), 
+  .waddr(addrIn), 
+  .di(dataIn)
+); */
+
+
+ simFifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_simFifoMem (
+	.addrIn(addrIn),
+	.addrOut(addrOut),
+	.clk(clk),
+	.dataIn(dataIn),
+	.writeEn(writeEn),
+	.readEn(readEn),
+	.dataOut(dataOut));  
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/buffers/fifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/USBHostControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/USBHostControlBI.v	(revision 264)
@@ -0,0 +1,264 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBHostControlBI.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: USBHostControlBI.v,v 1.1.1.1 2004-10-11 04:00:56 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbHostControl_h.v"
+ 
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+	SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+	TxTransTypeReg, TxSOFEnableReg,
+	TxAddrReg, TxEndPReg, frameNumIn, 
+	RxPktStatusIn, RxPIDIn,
+	connectStateIn,
+	SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+  hostControlSelect,
+  clrTransReq,
+  preambleEn,
+  SOFSync,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  transReq
+  );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output transReq;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg TxSOFEnableReg;
+reg [6:0] TxAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg SOFSync;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg transReq;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+
+//sync write demux
+always @(posedge clk)
+begin
+	clrSOFReq <= 1'b0;
+  clrConnEvtReq <= 1'b0;
+  clrResInReq <= 1'b0;
+  clrTransDoneReq <= 1'b0;
+  setTransReq <= 1'b0;
+	if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+	begin
+		case (address)
+			`TX_CONTROL_REG : begin
+        preambleEn <= dataIn[2];
+        SOFSync <= dataIn[1];
+        setTransReq <= dataIn[0];
+      end
+			`TX_TRANS_TYPE_REG : TxTransTypeReg <= dataIn[1:0];
+			`TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+			`TX_SOF_ENABLE_REG : TxSOFEnableReg <= dataIn[0];
+			`TX_ADDR_REG : TxAddrReg <= dataIn[6:0];
+			`TX_ENDP_REG : TxEndPReg <= dataIn[3:0];
+			`INTERRUPT_STATUS_REG :	begin
+        clrSOFReq <= dataIn[3];
+        clrConnEvtReq <= dataIn[2];
+        clrResInReq <= dataIn[1];
+        clrTransDoneReq <= dataIn[0];
+      end
+			`INTERRUPT_MASK_REG	: interruptMaskReg <= dataIn[3:0];
+		endcase
+	end
+end
+
+//interrupt control
+always @(posedge clk)
+begin
+	if (SOFSentIn == 1'b1)
+		SOFSentInt <= 1'b1;
+	else if (clrSOFReq == 1'b1)
+		SOFSentInt <= 1'b0;
+		
+	if (connEventIn == 1'b1)
+		connEventInt <= 1'b1;
+	else if (clrConnEvtReq == 1'b1)
+		connEventInt <= 1'b0;
+		
+	if (resumeIntIn == 1'b1)
+		resumeInt <= 1'b1;
+	else if (clrResInReq == 1'b1)
+		resumeInt <= 1'b0;	
+
+	if (transDoneIn == 1'b1)
+		transDoneInt <= 1'b1;
+	else if (clrTransDoneReq == 1'b1)
+		transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or connEventInt or SOFSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end  
+  
+//transaction request set/clear
+always @(posedge clk)
+begin
+	if (setTransReq == 1'b1)
+		transReq <= 1'b1;
+	else if (clrTransReq == 1'b1)
+		transReq <= 1'b0;
+end  
+  
+//break out control signals
+always @(TxControlReg or TxLineControlReg) begin
+  TxLineState <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+  fullSpeedPol <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+  
+// async read mux
+always @(address or
+	TxControlReg or TxTransTypeReg or TxLineControlReg or TxSOFEnableReg or
+	TxAddrReg or TxEndPReg or frameNumIn or 
+	SOFSentInt or connEventInt or resumeInt or transDoneInt or
+	interruptMaskReg or RxPktStatusIn or RxPIDIn or connectStateIn or
+  preambleEn or SOFSync or transReq)
+begin
+	case (address)
+			`TX_CONTROL_REG : dataOut <= {5'b00000, preambleEn, SOFSync, transReq} ;
+			`TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeReg};
+			`TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+			`TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableReg};
+			`TX_ADDR_REG : dataOut <= {1'b0, TxAddrReg};
+			`TX_ENDP_REG : dataOut <= {4'h0, TxEndPReg};
+			`FRAME_NUM_MSB_REG : dataOut <= frameNumIn[10:3];
+			`FRAME_NUM_LSB_REG : dataOut <= {5'b00000, frameNumIn[2:0]};
+			`INTERRUPT_STATUS_REG :	dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+			`INTERRUPT_MASK_REG	: dataOut <= {4'h0, interruptMaskReg};
+			`RX_STATUS_REG	: dataOut <= RxPktStatusIn;
+			`RX_PID_REG	: dataOut <= {4'b0000, RxPIDIn};
+			`RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateIn};
+      default: dataOut <= 8'h00;
+	endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/getpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/getpacket.v	(revision 264)
@@ -0,0 +1,337 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\getpacket.v
+// Generated   : 09/22/04 06:01:21
+// From        : c:\projects\USBHostSlave\RTL\hostController\getpacket.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, clk, getPacketEn, rst);
+input   [7:0] RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0] RXStreamStatusIn;
+input   SIERxTimeOut;		// Single cycle pulse
+input   clk;
+input   getPacketEn;
+input   rst;
+output  [7:0] RXFifoData;
+output  RXFifoWEn;
+output  RXPacketRdy;
+output  [7:0] RXPktStatus;
+output  [3:0] RxPID;
+
+wire    [7:0] RXDataIn;
+wire    RXDataValid;
+reg     [7:0] RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [7:0] RXPktStatus;
+wire    [7:0] RXStreamStatusIn;
+reg     [3:0] RxPID, next_RxPID;
+wire    SIERxTimeOut;
+wire    clk;
+wire    getPacketEn;
+wire    rst;
+
+// diagram signals declarations
+reg  ACKRxed, next_ACKRxed;
+reg  CRCError, next_CRCError;
+reg  NAKRxed, next_NAKRxed;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXByte, next_RXByte;
+reg  RXOverflow, next_RXOverflow;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+reg  RXTimeOut, next_RXTimeOut;
+reg  bitStuffError, next_bitStuffError;
+reg  dataSequence, next_dataSequence;
+reg  stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0] CurrState_getPkt;
+reg [4:0] NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(CRCError or bitStuffError or
+  RXOverflow or RXTimeOut or
+  NAKRxed or stallRxed or
+  ACKRxed or dataSequence)
+begin
+    RXPktStatus = {
+    dataSequence, ACKRxed,
+    stallRxed, NAKRxed,
+    RXTimeOut, RXOverflow,
+    bitStuffError, CRCError};
+end
+
+
+//--------------------------------------------------------------------
+// Machine: getPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)
+begin : getPkt_NextState
+	NextState_getPkt <= CurrState_getPkt;
+	// Set default values for outputs and signals
+	next_CRCError <= CRCError;
+	next_bitStuffError <= bitStuffError;
+	next_RXOverflow <= RXOverflow;
+	next_RXTimeOut <= RXTimeOut;
+	next_NAKRxed <= NAKRxed;
+	next_stallRxed <= stallRxed;
+	next_ACKRxed <= ACKRxed;
+	next_dataSequence <= dataSequence;
+	next_RXByte <= RXByte;
+	next_RXStreamStatus <= RXStreamStatus;
+	next_RxPID <= RxPID;
+	next_RXPacketRdy <= RXPacketRdy;
+	next_RXByteOldest <= RXByteOldest;
+	next_RXByteOld <= RXByteOld;
+	next_RXFifoWEn <= RXFifoWEn;
+	next_RXFifoData <= RXFifoData;
+	case (CurrState_getPkt) // synopsys parallel_case full_case
+		`START_GP:
+			NextState_getPkt <= `WAIT_EN;
+		`WAIT_PKT:
+		begin
+			next_CRCError <= 1'b0;
+			next_bitStuffError <= 1'b0;
+			next_RXOverflow <= 1'b0;
+			next_RXTimeOut <= 1'b0;
+			next_NAKRxed <= 1'b0;
+			next_stallRxed <= 1'b0;
+			next_ACKRxed <= 1'b0;
+			next_dataSequence <= 1'b0;
+			if (SIERxTimeOut == 1'b1)	
+			begin
+				NextState_getPkt <= `PKT_RDY;
+				next_RXTimeOut <= 1'b1;
+			end
+			else if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `CHK_PKT_START;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		end
+		`CHK_PKT_START:
+			if (RXStreamStatus == `RX_PACKET_START)	
+			begin
+				NextState_getPkt <= `PROC_PKT_CHK_PID;
+				next_RxPID <= RXByte[3:0];
+			end
+			else
+			begin
+				NextState_getPkt <= `PKT_RDY;
+				next_RXTimeOut <= 1'b1;
+			end
+		`WAIT_EN:
+		begin
+			next_RXPacketRdy <= 1'b0;
+			if (getPacketEn == 1'b1)	
+				NextState_getPkt <= `WAIT_PKT;
+		end
+		`PKT_RDY:
+		begin
+			next_RXPacketRdy <= 1'b1;
+			NextState_getPkt <= `WAIT_EN;
+		end
+		`PROC_PKT_CHK_PID:
+			if (RXByte[1:0] == `HANDSHAKE)	
+				NextState_getPkt <= `PROC_PKT_HS;
+			else if (RXByte[1:0] == `DATA)	
+				NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+			else
+				NextState_getPkt <= `PKT_RDY;
+		`PROC_PKT_HS:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PKT_RDY;
+				next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+				next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+				next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+				next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+			end
+		`PROC_PKT_DATA_W_D1:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_CHK_D1:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+				next_RXByteOldest <= RXByte;
+			end
+			else
+				NextState_getPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_W_D2:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_FIN:
+		begin
+			next_CRCError <= RXByte[`CRC_ERROR_BIT];
+			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+			NextState_getPkt <= `PKT_RDY;
+		end
+		`PROC_PKT_DATA_CHK_D2:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+				next_RXByteOld <= RXByte;
+			end
+			else
+				NextState_getPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_W_D3:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_CHK_D3:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+				NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+			else
+				NextState_getPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_LOOP_CHK_FIFO:
+			if (RXFifoFull == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+				next_RXOverflow <= 1'b1;
+			end
+			else
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+				next_RXFifoWEn <= 1'b1;
+				next_RXFifoData <= RXByteOldest;
+				next_RXByteOldest <= RXByteOld;
+				next_RXByteOld <= RXByte;
+			end
+		`PROC_PKT_DATA_LOOP_FIFO_FULL:
+			NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+		`PROC_PKT_DATA_LOOP_W_D:
+		begin
+			next_RXFifoWEn <= 1'b0;
+			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+			else if (RXDataValid == 1'b1)	
+			begin
+				NextState_getPkt <= `PROC_PKT_DATA_FIN;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		end
+		`PROC_PKT_DATA_LOOP_DELAY:
+			NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : getPkt_CurrentState
+	if (rst)	
+		CurrState_getPkt <= `START_GP;
+	else
+		CurrState_getPkt <= NextState_getPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : getPkt_RegOutput
+	if (rst)	
+	begin
+		RXByteOld <= 8'h00;
+		RXByteOldest <= 8'h00;
+		CRCError <= 1'b0;
+		bitStuffError <= 1'b0;
+		RXOverflow <= 1'b0;
+		RXTimeOut <= 1'b0;
+		NAKRxed <= 1'b0;
+		stallRxed <= 1'b0;
+		ACKRxed <= 1'b0;
+		dataSequence <= 1'b0;
+		RXByte <= 8'h00;
+		RXStreamStatus <= 8'h00;
+		RXPacketRdy <= 1'b0;
+		RXFifoWEn <= 1'b0;
+		RXFifoData <= 8'h00;
+		RxPID <= 4'h0;
+	end
+	else 
+	begin
+		RXByteOld <= next_RXByteOld;
+		RXByteOldest <= next_RXByteOldest;
+		CRCError <= next_CRCError;
+		bitStuffError <= next_bitStuffError;
+		RXOverflow <= next_RXOverflow;
+		RXTimeOut <= next_RXTimeOut;
+		NAKRxed <= next_NAKRxed;
+		stallRxed <= next_stallRxed;
+		ACKRxed <= next_ACKRxed;
+		dataSequence <= next_dataSequence;
+		RXByte <= next_RXByte;
+		RXStreamStatus <= next_RXStreamStatus;
+		RXPacketRdy <= next_RXPacketRdy;
+		RXFifoWEn <= next_RXFifoWEn;
+		RXFifoData <= next_RXFifoData;
+		RxPID <= next_RxPID;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/hostcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/hostcontroller.v	(revision 264)
@@ -0,0 +1,348 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\hostcontroller.v
+// Generated   : 09/14/04 22:52:06
+// From        : c:\projects\USBHostSlave\RTL\hostController\hostcontroller.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input   [7:0] RXStatus;
+input   clk;
+input   getPacketRdy;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   transReq;
+input   [1:0] transType;
+output  clearTXReq;
+output  getPacketREn;
+output  sendPacketArbiterReq;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+output  transDone;
+
+wire    [7:0] RXStatus;
+reg     clearTXReq, next_clearTXReq;
+wire    clk;
+reg     getPacketREn, next_getPacketREn;
+wire    getPacketRdy;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     transDone, next_transDone;
+wire    transReq;
+wire    [1:0] transType;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 5'b00000
+`define TX_REQ 5'b00001
+`define CHK_TYPE 5'b00010
+`define FLAG 5'b00011
+`define IN_WAIT_DATA_RXED 5'b00100
+`define IN_CHK_FOR_ERROR 5'b00101
+`define IN_CLR_SP_WEN2 5'b00110
+`define SETUP_CLR_SP_WEN1 5'b00111
+`define SETUP_CLR_SP_WEN2 5'b01000
+`define FIN 5'b01001
+`define WAIT_GNT 5'b01010
+`define SETUP_WAIT_PKT_RXED 5'b01011
+`define IN_WAIT_IN_SENT 5'b01100
+`define OUT0_WAIT_RX_DATA 5'b01101
+`define OUT0_WAIT_DATA0_SENT 5'b01110
+`define OUT0_WAIT_OUT_SENT 5'b01111
+`define SETUP_HC_WAIT_RDY 5'b10000
+`define IN_WAIT_SP_RDY1 5'b10001
+`define IN_WAIT_SP_RDY2 5'b10010
+`define OUT0_WAIT_SP_RDY1 5'b10011
+`define SETUP_WAIT_SETUP_SENT 5'b10100
+`define SETUP_WAIT_DATA_SENT 5'b10101
+`define IN_CLR_SP_WEN1 5'b10110
+`define IN_WAIT_ACK_SENT 5'b10111
+`define OUT0_CLR_WEN1 5'b11000
+`define OUT0_CLR_WEN2 5'b11001
+`define OUT1_WAIT_RX_DATA 5'b11010
+`define OUT1_WAIT_OUT_SENT 5'b11011
+`define OUT1_WAIT_DATA1_SENT 5'b11100
+`define OUT1_WAIT_SP_RDY1 5'b11101
+`define OUT1_CLR_WEN1 5'b11110
+`define OUT1_CLR_WEN2 5'b11111
+
+reg [4:0] CurrState_hstCntrl;
+reg [4:0] NextState_hstCntrl;
+
+
+//--------------------------------------------------------------------
+// Machine: hstCntrl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
+begin : hstCntrl_NextState
+	NextState_hstCntrl <= CurrState_hstCntrl;
+	// Set default values for outputs and signals
+	next_sendPacketArbiterReq <= sendPacketArbiterReq;
+	next_transDone <= transDone;
+	next_clearTXReq <= clearTXReq;
+	next_sendPacketWEn <= sendPacketWEn;
+	next_getPacketREn <= getPacketREn;
+	next_sendPacketPID <= sendPacketPID;
+	case (CurrState_hstCntrl) // synopsys parallel_case full_case
+		`START_HC:
+			NextState_hstCntrl <= `TX_REQ;
+		`TX_REQ:
+			if (transReq == 1'b1)	
+			begin
+				NextState_hstCntrl <= `WAIT_GNT;
+				next_sendPacketArbiterReq <= 1'b1;
+			end
+		`CHK_TYPE:
+			if (transType == `IN_TRANS)	
+				NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+			else if (transType == `OUTDATA0_TRANS)	
+				NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+			else if (transType == `OUTDATA1_TRANS)	
+				NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+			else if (transType == `SETUP_TRANS)	
+				NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+		`FLAG:
+		begin
+			next_transDone <= 1'b1;
+			next_clearTXReq <= 1'b1;
+			next_sendPacketArbiterReq <= 1'b0;
+			NextState_hstCntrl <= `FIN;
+		end
+		`FIN:
+		begin
+			next_transDone <= 1'b0;
+			next_clearTXReq <= 1'b0;
+			NextState_hstCntrl <= `TX_REQ;
+		end
+		`WAIT_GNT:
+			if (sendPacketArbiterGnt == 1'b1)	
+				NextState_hstCntrl <= `CHK_TYPE;
+		`SETUP_CLR_SP_WEN1:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+		end
+		`SETUP_CLR_SP_WEN2:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+		end
+		`SETUP_WAIT_PKT_RXED:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `FLAG;
+		end
+		`SETUP_HC_WAIT_RDY:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `SETUP;
+			end
+		`SETUP_WAIT_SETUP_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA0;
+			end
+		`SETUP_WAIT_DATA_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+				next_getPacketREn <= 1'b1;
+			end
+		`IN_WAIT_DATA_RXED:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+		end
+		`IN_CHK_FOR_ERROR:
+			if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+				RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+				RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+				RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+				RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+				RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)	
+				NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+			else
+				NextState_hstCntrl <= `FLAG;
+		`IN_CLR_SP_WEN2:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+		end
+		`IN_WAIT_IN_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+				next_getPacketREn <= 1'b1;
+			end
+		`IN_WAIT_SP_RDY1:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `IN;
+			end
+		`IN_WAIT_SP_RDY2:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `ACK;
+			end
+		`IN_CLR_SP_WEN1:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+		end
+		`IN_WAIT_ACK_SENT:
+			if (sendPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `FLAG;
+		`OUT0_WAIT_RX_DATA:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `FLAG;
+		end
+		`OUT0_WAIT_DATA0_SENT:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+				next_getPacketREn <= 1'b1;
+			end
+		end
+		`OUT0_WAIT_OUT_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT0_CLR_WEN2;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA0;
+			end
+		`OUT0_WAIT_SP_RDY1:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT0_CLR_WEN1;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `OUT;
+			end
+		`OUT0_CLR_WEN1:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+		end
+		`OUT0_CLR_WEN2:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+		end
+		`OUT1_WAIT_RX_DATA:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_hstCntrl <= `FLAG;
+		end
+		`OUT1_WAIT_OUT_SENT:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT1_CLR_WEN2;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA1;
+			end
+		`OUT1_WAIT_DATA1_SENT:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+				next_getPacketREn <= 1'b1;
+			end
+		end
+		`OUT1_WAIT_SP_RDY1:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_hstCntrl <= `OUT1_CLR_WEN1;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `OUT;
+			end
+		`OUT1_CLR_WEN1:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+		end
+		`OUT1_CLR_WEN2:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : hstCntrl_CurrentState
+	if (rst)	
+		CurrState_hstCntrl <= `START_HC;
+	else
+		CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : hstCntrl_RegOutput
+	if (rst)	
+	begin
+		transDone <= 1'b0;
+		clearTXReq <= 1'b0;
+		getPacketREn <= 1'b0;
+		sendPacketArbiterReq <= 1'b0;
+		sendPacketWEn <= 1'b0;
+		sendPacketPID <= 4'b0;
+	end
+	else 
+	begin
+		transDone <= next_transDone;
+		clearTXReq <= next_clearTXReq;
+		getPacketREn <= next_getPacketREn;
+		sendPacketArbiterReq <= next_sendPacketArbiterReq;
+		sendPacketWEn <= next_sendPacketWEn;
+		sendPacketPID <= next_sendPacketPID;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/sendpacketarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/sendpacketarbiter.asf	(revision 264)
@@ -0,0 +1,96 @@
+VERSION=1.19
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FREEOID=98
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,sendPacketArbiter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
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+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: sendPacketArbiter"
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+S 11 6 8192 ELLIPSE "States" | 128339,87513 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "SOF_ACT\n/1/"
+S 13 6 4096 ELLIPSE "States" | 95226,16087 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "HC_ACT\n/0/"
+S 15 6 0 ELLIPSE "States" | 172430,18866 6500 6500
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+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "HCTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b0;"
+I 47 0 2 Builtin OutPort | 89651,157673 "" ""
+L 46 47 0 TEXT "Labels" | 95651,157673 1 0 0 "SOFTxGnt"
+I 45 0 130 Builtin OutPort | 162661,153684 "" ""
+L 44 45 0 TEXT "Labels" | 168661,153684 1 0 0 "sendPacketPID[3:0]"
+I 43 0 2 Builtin OutPort | 162738,158202 "" ""
+L 42 43 0 TEXT "Labels" | 168738,158202 1 0 0 "sendPacketWEnable"
+I 41 0 2 Builtin OutPort | 36274,157869 "" ""
+L 40 41 0 TEXT "Labels" | 42274,157869 1 0 0 "HCTxGnt"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "SOFTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b1;"
+A 39 9 2 TEXT "Actions" | 134973,143961 1 0 0 "SOFTxGnt <= 1'b0;\nHCTxGnt <= 1'b0; \nmuxSOFNotHC <= 1'b0;"
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+I 53 0 130 Builtin InPort | 38410,162874 "" ""
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+I 51 0 2 Builtin InPort | 38527,153081 "" ""
+L 50 51 0 TEXT "Labels" | 44527,153081 1 0 0 "HCTxReq"
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+L 48 49 0 TEXT "Labels" | 98038,153080 1 0 0 "SOFTxReq"
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+                                      151634,101445 145030,99051 137656,94031 133485,91482
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
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+L 86 85 0 TEXT "Labels" | 44222,167883 1 0 0 "HC_SP_WEn"
+I 85 0 2 Builtin InPort | 38222,167883 "" ""
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "HCTxGnt <= 1'b0;"
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+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)  \nbegin\n  if (muxSOFNotHC  == 1'b1)  \n  begin\n    sendPacketWEnable <= SOF_SP_WEn;\n    sendPacketPID <= `SOF;\n  end\n  else\n  begin\n    sendPacketWEnable <= HC_SP_WEn;\n    sendPacketPID <= HC_PID;\n  end\nend"
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/sofcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/sofcontroller.asf	(revision 264)
@@ -0,0 +1,96 @@
+VERSION=1.19
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FREEOID=65
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/19/2004"
+HEADER_PARAM="TITLE,SOFController"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
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+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
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+END
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+MARGINS 12700,12700 12700,12700
+END
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+I 16 0 3 Builtin InPort | 180096,262516 "" ""
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+A 32 24 4 TEXT "Actions" | 140026,70890 1 0 0 "HCTxPortReq <= 1'b0;\nif (SOFTimerClr == 1'b1)\n  SOFTimer <= 16'h0000;\nelse\n  SOFTimer <= SOFTimer + 1'b1;"
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+L 59 60 0 TEXT "Labels" | 29316,251905 1 0 0 "SOFTimerClr"
+A 48 9 2 TEXT "Actions" | 114168,219502 1 0 0 "SOFTimer <= 16'h0000;\nHCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+L 49 50 0 TEXT "State Labels" | 162077,151882 1 0 0 "SC_WAIT_GNT\n/4/"
+S 50 6 16384 ELLIPSE "States" | 162077,151882 6500 6500
+W 51 6 0 50 21 BEZIER "Transitions" | 155785,150253 143926,148645 122475,143375 110616,144581
+C 52 51 0 TEXT "Conditions" | 129444,145489 1 0 0 "HCTxPortGnt == 1'b1"
+A 53 22 16 TEXT "Actions" | 118898,162608 1 0 0 "HCTxPortReq <= 1'b1;"
+A 54 33 16 TEXT "Actions" | 41502,87168 1 0 0 "SOFTimer <= 16'h0000;"
+L 55 56 0 TEXT "Labels" | 139062,239200 1 0 0 "HCTxPortReq"
+I 56 0 2 Builtin OutPort | 133062,239200 "" ""
+L 57 58 0 TEXT "Labels" | 141474,244024 1 0 0 "HCTxPortGnt"
+I 58 0 2 Builtin InPort | 135474,244024 "" ""
+L 61 62 0 TEXT "State Labels" | 118352,95112 1 0 0 "CLR_WEN\n/5/"
+S 62 6 20480 ELLIPSE "States" | 118352,95112 6500 6500
+A 63 62 4 TEXT "Actions" | 137072,99272 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 64 6 0 62 24 BEZIER "Transitions" | 116496,88885 114624,81865 110713,68112 108841,61092
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_01_01/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/buffers/TxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/buffers/TxFifoBI.v	(revision 264)
@@ -0,0 +1,123 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: TxFifoBI.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+  address, writeEn, strobe_i,
+  clk, rst, fifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoWEn,
+  fifoFull,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoWEn;
+input fifoFull;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoWEn;
+wire fifoFull;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+	if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoFull or numElementsInFifo)
+begin
+	case (address)
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00;
+	endcase
+end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoWEn <= 1'b1;
+  else
+    fifoWEn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/buffers/TxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/busInterface/wishBoneBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/busInterface/wishBoneBI.v	(revision 264)
@@ -0,0 +1,251 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBI.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: wishBoneBI.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "wishBoneBus_h.v"
+
+ 
+module wishBoneBI (
+  address, dataIn, dataOut, writeEn, 
+  strobe_i,
+  ack_o,
+  clk, rst,
+	hostControlSel, 
+  hostRxFifoSel, hostTxFifoSel,
+  slaveControlSel,
+  slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, 
+  slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, 
+  hostSlaveMuxSel,
+  dataFromHostControl,
+  dataFromHostRxFifo,
+  dataFromHostTxFifo,
+  dataFromSlaveControl,
+  dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+  dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+  dataFromHostSlaveMux
+	 );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+  dataFromHostControl or
+  dataFromHostRxFifo or
+  dataFromHostTxFifo or
+  dataFromSlaveControl or
+  dataFromEP0RxFifo or 
+  dataFromEP1RxFifo or
+  dataFromEP2RxFifo or
+  dataFromEP3RxFifo or
+  dataFromHostSlaveMux or 
+  dataFromEP0TxFifo or
+  dataFromEP1TxFifo or
+  dataFromEP2TxFifo or
+  dataFromEP3TxFifo)
+begin
+  hostControlSel <= 1'b0;
+  hostRxFifoSel <= 1'b0;
+  hostTxFifoSel <= 1'b0;
+  slaveControlSel <= 1'b0;
+  slaveEP0RxFifoSel <= 1'b0;
+  slaveEP0TxFifoSel <= 1'b0;
+  slaveEP1RxFifoSel <= 1'b0;
+  slaveEP1TxFifoSel <= 1'b0;
+  slaveEP2RxFifoSel <= 1'b0;
+  slaveEP2TxFifoSel <= 1'b0;
+  slaveEP3RxFifoSel <= 1'b0;
+  slaveEP3TxFifoSel <= 1'b0;
+  hostSlaveMuxSel <= 1'b0;
+  case (address & `ADDRESS_DECODE_MASK)
+    `HCREG_BASE : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HCREG_BASE_PLUS_0X10 : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HOST_RX_FIFO_BASE : begin
+      hostRxFifoSel <= 1'b1;
+      dataOut <= dataFromHostRxFifo;
+    end
+    `HOST_TX_FIFO_BASE : begin
+      hostTxFifoSel <= 1'b1;
+      dataOut <= dataFromHostTxFifo;
+    end
+    `SCREG_BASE : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `SCREG_BASE_PLUS_0X10 : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `EP0_RX_FIFO_BASE : begin
+      slaveEP0RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0RxFifo;
+    end
+    `EP0_TX_FIFO_BASE : begin
+      slaveEP0TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0TxFifo;
+    end
+    `EP1_RX_FIFO_BASE : begin
+      slaveEP1RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1RxFifo;
+    end
+    `EP1_TX_FIFO_BASE : begin
+      slaveEP1TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1TxFifo;
+    end
+    `EP2_RX_FIFO_BASE : begin
+      slaveEP2RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2RxFifo;
+    end
+    `EP2_TX_FIFO_BASE : begin
+      slaveEP2TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2TxFifo;
+    end
+    `EP3_RX_FIFO_BASE : begin
+      slaveEP3RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3RxFifo;
+    end
+    `EP3_TX_FIFO_BASE : begin
+      slaveEP3TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3TxFifo;
+    end
+    `HOST_SLAVE_CONTROL_BASE : begin
+      hostSlaveMuxSel <= 1'b1; 
+      dataOut <= dataFromHostSlaveMux;
+    end
+    default: 
+      dataOut <= 8'h00;
+	endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+  ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+  ack_immediate <= strobe_i;
+end 
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+  if (writeEn == 1'b0 &&
+      (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+  begin
+    ack_o <= ack_delayed;
+  end
+  else
+  begin
+    ack_o <= ack_immediate;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/getpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/getpacket.asf	(revision 264)
@@ -0,0 +1,280 @@
+VERSION=1.19
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FREEOID=259
+"LIBRARIES=`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/22/2004"
+HEADER_PARAM="TITLE,getPacket"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
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+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 33
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+END
+INSTHEADER 251
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: getPacket"
+F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15236 200200,215950
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "getPkt"
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
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+A 30 23 4 TEXT "Actions" | 121604,184804 1 0 0 "RXPacketRdy <= 1'b0;"
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+C 62 60 0 TEXT "Conditions" | 58179,193710 1 0 0 "RXByte[1:0] == `HANDSHAKE"
+W 61 46 8194 54 58 BEZIER "Transitions" | 106682,215726 120437,200731 146339,171979 160094,156984
+W 60 46 8193 54 56 BEZIER "Transitions" | 98533,215553 88273,200670 67711,171725 57451,156842
+W 59 46 0 49 54 BEZIER "Transitions" | 52133,248640 63746,242665 85368,230107 96981,224132
+S 58 46 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 164600,152300 6500 6500
+L 57 58 0 TEXT "State Labels" | 164600,152300 1 0 0 "DATA"
+S 56 46 4096 ELLIPSE "States" | 53900,151400 6500 6500
+L 55 56 0 TEXT "State Labels" | 53900,151400 1 0 0 "HS\n/1/"
+S 54 46 0 ELLIPSE "States" | 102500,220700 6500 6500
+L 53 54 0 TEXT "State Labels" | 102500,220700 1 0 0 "CHK_PID\n/0/"
+I 49 46 0 Builtin Entry | 47660,248640
+I 50 46 0 Builtin Exit | 180308,72140
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+I 76 72 0 Builtin Exit | 187140,27160
+I 75 72 0 Builtin Entry | 33260,254940
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nNAKRxed <= RXDataIn[`NAK_RXED_BIT];\nstallRxed <= RXDataIn[`STALL_RXED_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+W 87 72 0 75 80 BEZIER "Transitions" | 37733,254940 43032,249077 61954,258197 67253,252334
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177616,25344 184028,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176799,72082 177196,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 2 Builtin InPort | 114408,221254 "" ""
+I 191 0 2 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 2 Builtin Signal | 19204,221408 "" ""
+L 198 199 0 TEXT "Labels" | 22068,244340 1 0 0 "RXOverflow"
+I 199 0 2 Builtin Signal | 19068,244340 "" ""
+L 200 201 0 TEXT "Labels" | 22380,239536 1 0 0 "NAKRxed"
+I 201 0 2 Builtin Signal | 19380,239536 "" ""
+L 202 203 0 TEXT "Labels" | 22840,230756 1 0 0 "stallRxed"
+I 203 0 2 Builtin Signal | 19840,230756 "" ""
+L 204 205 0 TEXT "Labels" | 22880,234404 1 0 0 "ACKRxed"
+I 205 0 2 Builtin Signal | 19416,234868 "" ""
+L 206 207 0 TEXT "Labels" | 83404,226912 1 0 0 "RXPktStatus[7:0]"
+I 207 0 0 Builtin OutPort | 77404,226912 "" ""
+L 208 209 0 TEXT "Labels" | 22024,249240 1 0 0 "RXTimeOut"
+I 209 0 2 Builtin Signal | 19024,249240 "" ""
+L 210 211 0 TEXT "Labels" | 21792,253880 1 0 0 "CRCError"
+I 211 0 2 Builtin Signal | 18792,253880 "" ""
+L 212 213 0 TEXT "Labels" | 22024,258288 1 0 0 "bitStuffError"
+I 213 0 2 Builtin Signal | 19024,258288 "" ""
+L 214 215 0 TEXT "Labels" | 22024,262928 1 0 0 "dataSequence"
+I 215 0 2 Builtin Signal | 19024,262928 "" ""
+I 216 0 2 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 2 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,68440 129157,59392 116484,42555 109437,33507
+I 238 0 2 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139444,90956 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 2 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 2 Builtin OutPort | 77780,242452 "" ""
+A 235 0 1 TEXT "Actions" | 156850,265490 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n  RXPktStatus = { \n  dataSequence, ACKRxed, \n  stallRxed, NAKRxed,\n  RXTimeOut, RXOverflow, \n  bitStuffError, CRCError};\nend"
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+                                           57686,214631 75382,223396 84426,228258
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlave.v	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlave.v	(revision 264)
@@ -0,0 +1,558 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlave.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`timescale 1ns / 1ps
+
+module usbHostSlave(
+  clk_i,
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  usbClk,
+  hostSOFSentIntOut, 
+  hostConnEventIntOut, 
+  hostResumeIntOut, 
+  hostTransDoneIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+  USBWireDataIn,
+  USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+  USBWireCtrlOut,
+  USBFullSpeed
+   );
+  parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+  parameter HOST_FIFO_ADDR_WIDTH = 6;   
+  parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+  parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+  parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+  parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk_i;               //Wishbone bus clock. Maximum 5*usbClk=240MHz
+input rst_i;               //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
+input [7:0] address_i;     //Wishbone bus address in
+input [7:0] data_i;        //Wishbone bus data in
+output [7:0] data_o;       //Wishbone bus data out
+input we_i;                //Wishbone bus write enable in
+input strobe_i;            //Wishbone bus strobe in
+output ack_o;              //Wishbone bus acknowledge out
+input usbClk;              //usb clock. 48Mhz +/-0.25%
+output hostSOFSentIntOut; 
+output hostConnEventIntOut; 
+output hostResumeIntOut; 
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire we_i; 
+wire strobe_i;
+wire ack_o;
+wire usbClk;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel; 
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE; 
+wire [7:0] hostTxFifoData; 
+wire hostTxFifoEmpty;
+wire hostRxFifoWE; 
+wire [7:0] hostRxFifoData; 
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost; 
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+wire noActivityTimeOutEnableToSIE;
+wire noActivityTimeOutEnableFromHost;
+wire noActivityTimeOutEnableFromSlave;
+
+assign USBFullSpeed = fullSpeedBitRateToSIE;  
+
+usbHostControl u_usbHostControl(
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .TxFifoRE(hostTxFifoRE), 
+  .TxFifoData(hostTxFifoData), 
+  .TxFifoEmpty(hostTxFifoEmpty),
+  .RxFifoWE(hostRxFifoWE), 
+  .RxFifoData(hostRxFifoData), 
+  .RxFifoFull(hostRxFifoFull),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut),
+  .SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
+  .fullSpeedRate(fullSpeedBitRateFromHost), 
+  .fullSpeedPol(fullSpeedPolarityFromHost),
+  .HCTxPortEn(SIEPortWEnFromHost), 
+  .HCTxPortRdy(SIEPortTxRdy),
+  .HCTxPortData(SIEPortDataInFromHost), 
+  .HCTxPortCtrl(SIEPortCtrlInFromHost),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[3:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostControl), 
+  .busWriteEn(we_i),
+  .busStrobe_i(strobe_i),
+  .SOFSentIntOut(hostSOFSentIntOut), 
+  .connEventIntOut(hostConnEventIntOut), 
+  .resumeIntOut(hostResumeIntOut), 
+  .transDoneIntOut(hostTransDoneIntOut),
+  .hostControlSelect(hostControlSel) );
+  
+
+usbSlaveControl u_usbSlaveControl(
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut), 
+  .SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
+  .RxFifoData(slaveRxFifoData),
+  .fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+  .SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+  .SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(we_i),
+  .busStrobe_i(strobe_i),
+  .SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(we_i), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk_i), 
+  .rst(rstSyncToBusClk),
+  .hostControlSel(hostControlSel), 
+  .hostRxFifoSel(hostRxFifoSel), 
+  .hostTxFifoSel(hostTxFifoSel),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(dataFromHostControl),
+  .dataFromHostRxFifo(dataFromHostRxFifo),
+  .dataFromHostTxFifo(dataFromHostTxFifo),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+   );
+
+hostSlaveMux u_hostSlaveMux(
+  .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+  .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+  .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+  .SIEPortDataInToSIE(SIEPortDataInToSIE), 
+  .SIEPortDataInFromHost(SIEPortDataInFromHost), 
+  .SIEPortDataInFromSlave(SIEPortDataInFromSlave), 
+  .SIEPortWEnToSIE(SIEPortWEnToSIE), 
+  .SIEPortWEnFromHost(SIEPortWEnFromHost), 
+  .SIEPortWEnFromSlave(SIEPortWEnFromSlave), 
+  .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+  .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+  .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+  .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+  .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+  .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+  .noActivityTimeOutEnableToSIE(noActivityTimeOutEnableToSIE),
+  .noActivityTimeOutEnableFromHost(noActivityTimeOutEnableFromHost),
+  .noActivityTimeOutEnableFromSlave(noActivityTimeOutEnableFromSlave),
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux),
+  .address(address_i[0]),
+  .writeEn(we_i),
+  .strobe_i(strobe_i),
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .rstFromWire(rst_i),
+  .rstSyncToBusClkOut(rstSyncToBusClk),
+  .rstSyncToUsbClkOut(rstSyncToUsbClk)
+);
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .connectState(connectState),
+  .resumeDetected(resumeDetected),
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataFromSIE), 
+  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+  .SIEPortDataIn(SIEPortDataInToSIE), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEnToSIE), 
+  .fullSpeedPolarity(fullSpeedPolarityToSIE),
+  .fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut),
+  .noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(hostTxFifoRE), 
+  .fifoEmpty(hostTxFifoEmpty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostTxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostTxFifo),
+  .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i),
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(hostRxFifoWE), 
+  .fifoFull(hostRxFifoFull),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostRxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostRxFifo),
+  .fifoDataIn(hostRxFifoData)  );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i),
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/tags/rel_01_01/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/rel_01_01/doc/html/src/hostController/USBHostControlBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/rel_01_01/doc/html/src/hostController/USBHostControlBI.v/index.htm	(revision 264)
@@ -0,0 +1,276 @@
+<html>
+<head>
+<title>USBHostControlBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBHostControlBI.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+ 
+<span id=t_kwd>module</span> <span id=t_idt>USBHostControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>SOFSentIntOut</span>, <span id=t_idt>connEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>TxTransTypeReg</span>, <span id=t_idt>TxSOFEnableReg</span>,
+  <span id=t_idt>TxAddrReg</span>, <span id=t_idt>TxEndPReg</span>, <span id=t_idt>frameNumIn</span>, 
+  <span id=t_idt>RxPktStatusIn</span>, <span id=t_idt>RxPIDIn</span>,
+  <span id=t_idt>connectStateIn</span>,
+  <span id=t_idt>SOFSentIn</span>, <span id=t_idt>connEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>,
+  <span id=t_idt>hostControlSelect</span>,
+  <span id=t_idt>clrTransReq</span>,
+  <span id=t_idt>preambleEn</span>,
+  <span id=t_idt>SOFSync</span>,
+  <span id=t_idt>TxLineState</span>,
+  <span id=t_idt>LineDirectControlEn</span>,
+  <span id=t_idt>fullSpeedPol</span>, 
+  <span id=t_idt>fullSpeedRate</span>,
+  <span id=t_idt>transReq</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>output</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transReq</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transReq</span>;
+
+<span id=t_com>//internal wire and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineControlReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrConnEvtReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>setTransReq</span>;
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResInReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>setTransReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>hostControlSelect</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>preambleEn</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>SOFSync</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>setTransReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>TxTransTypeReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>TxLineControlReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>TxSOFEnableReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>TxAddrReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>TxEndPReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_kwd>begin</span>
+        <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>clrResInReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>interruptMaskReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+   <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//interrupt control</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>SOFSentIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>connEventIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrConnEvtReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b0</span>;  
+
+  <span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//mask interrupts</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSentInt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>transDoneIntOut</span> &lt;= <span id=t_idt>transDoneInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>];
+  <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_idt>resumeInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>];
+  <span id=t_idt>connEventIntOut</span> &lt;= <span id=t_idt>connEventInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>CONNECTION_EVENT_BIT</span>];
+  <span id=t_idt>SOFSentIntOut</span> &lt;= <span id=t_idt>SOFSentInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_SENT_BIT</span>];
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//transaction request set/clear</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>setTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//break out control signals</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>TxLineState</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>TX_LINE_STATE_LSBIT</span>];
+  <span id=t_idt>LineDirectControlEn</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>DIRECT_CONTROL_BIT</span>];
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span>]; 
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span>];
+<span id=t_kwd>end</span>
+  
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxSOFEnableReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndPReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNumIn</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SOFSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span>
+  <span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>RxPktStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxPIDIn</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>preambleEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSync</span> <span id=t_kwd>or</span> <span id=t_idt>transReq</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>preambleEn</span>, <span id=t_idt>SOFSync</span>, <span id=t_idt>transReq</span>} ;
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>TxTransTypeReg</span>};
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>TxLineControlReg</span>};
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>TxSOFEnableReg</span>};
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxAddrReg</span>};
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>TxEndPReg</span>};
+     `<span id=t_idt>FRAME_NUM_MSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>frameNumIn</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>];
+     `<span id=t_idt>FRAME_NUM_LSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNumIn</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]};
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>SOFSentInt</span>, <span id=t_idt>connEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>};
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>interruptMaskReg</span>};
+     `<span id=t_idt>RX_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>RxPktStatusIn</span>;
+     `<span id=t_idt>RX_PID_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'b0000</span>, <span id=t_idt>RxPIDIn</span>};
+     `<span id=t_idt>RX_CONNECT_STATE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>};
+      <span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/rel_01_01/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/buffers/TxFifo.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/buffers/TxFifo.v	(revision 264)
@@ -0,0 +1,128 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo write access via bus interface, fifo read access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: TxFifo.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module TxFifo(
+  clk, 
+  rst, 
+  fifoREn, 
+  fifoEmpty,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataOut ); 
+  //FIFO_DEPTH = ADDR_WIDTH^2
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk; 
+input rst; 
+input fifoREn; 
+output fifoEmpty;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output [7:0] fifoDataOut;
+
+wire clk; 
+wire rst; 
+wire fifoREn; 
+wire fifoEmpty;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .clk(clk), 
+  .rst(rst), 
+  .dataIn(busDataIn), 
+  .dataOut(fifoDataOut), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmpty(forceEmpty), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+TxfifoBI u_TxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst), 
+  .fifoSelect(busFifoSelect),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoWEn(fifoWEn),
+  .fifoFull(fifoFull),
+  .forceEmpty(forceEmpty),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/buffers/simFifoMem.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/buffers/simFifoMem.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/buffers/simFifoMem.v	(revision 264)
@@ -0,0 +1,89 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// simFifoMem.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: simFifoMem.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module simFifoMem(	addrIn, addrOut, clk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire clk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge clk) begin
+  dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge clk) begin
+  if (writeEn == 1'b1)
+    buffer[addrIn] <= dataIn;
+end                  
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/buffers/simFifoMem.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/directcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/directcontrol.v	(revision 264)
@@ -0,0 +1,167 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\directcontrol.v
+// Generated   : 06/05/04 05:32:20
+// From        : c:\projects\USBHostSlave\RTL\hostController\directcontrol.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, clk, directControlEn, directControlLineState, rst);
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   clk;
+input   directControlEn;
+input   [1:0] directControlLineState;
+input   rst;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    clk;
+wire    directControlEn;
+wire    [1:0] directControlLineState;
+wire    rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0] CurrState_drctCntl;
+reg [2:0] NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+//--------------------------------------------------------------------
+// Machine: drctCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (directControlLineState or directControlEn or HCTxPortGnt or HCTxPortRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_drctCntl)
+begin : drctCntl_NextState
+	NextState_drctCntl <= CurrState_drctCntl;
+	// Set default values for outputs and signals
+	next_HCTxPortReq <= HCTxPortReq;
+	next_HCTxPortWEn <= HCTxPortWEn;
+	next_HCTxPortData <= HCTxPortData;
+	next_HCTxPortCntl <= HCTxPortCntl;
+	case (CurrState_drctCntl) // synopsys parallel_case full_case
+		`START_DC:
+			NextState_drctCntl <= `CHK_DRCT_CNTL;
+		`CHK_DRCT_CNTL:
+			if (directControlEn == 1'b1)	
+			begin
+				NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+				next_HCTxPortReq <= 1'b1;
+			end
+			else
+			begin
+				NextState_drctCntl <= `IDLE_WAIT_GNT;
+				next_HCTxPortReq <= 1'b1;
+			end
+		`DRCT_CNTL_WAIT_GNT:
+			if (HCTxPortGnt == 1'b1)	
+				NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+		`DRCT_CNTL_CHK_LOOP:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			if (directControlEn == 1'b0)	
+			begin
+				NextState_drctCntl <= `CHK_DRCT_CNTL;
+				next_HCTxPortReq <= 1'b0;
+			end
+			else
+				NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+		end
+		`DRCT_CNTL_WAIT_RDY:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= {6'b000000, directControlLineState};
+				next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+			end
+		`IDLE_FIN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			next_HCTxPortReq <= 1'b0;
+			NextState_drctCntl <= `CHK_DRCT_CNTL;
+		end
+		`IDLE_WAIT_GNT:
+			if (HCTxPortGnt == 1'b1)	
+				NextState_drctCntl <= `IDLE_WAIT_RDY;
+		`IDLE_WAIT_RDY:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_drctCntl <= `IDLE_FIN;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= 8'h00;
+				next_HCTxPortCntl <= `TX_IDLE;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : drctCntl_CurrentState
+	if (rst)	
+		CurrState_drctCntl <= `START_DC;
+	else
+		CurrState_drctCntl <= NextState_drctCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : drctCntl_RegOutput
+	if (rst)	
+	begin
+		HCTxPortCntl <= 8'h00;
+		HCTxPortData <= 8'h00;
+		HCTxPortWEn <= 1'b0;
+		HCTxPortReq <= 1'b0;
+	end
+	else 
+	begin
+		HCTxPortCntl <= next_HCTxPortCntl;
+		HCTxPortData <= next_HCTxPortData;
+		HCTxPortWEn <= next_HCTxPortWEn;
+		HCTxPortReq <= next_HCTxPortReq;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/hctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/hctxportarbiter.v	(revision 264)
@@ -0,0 +1,210 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\hctxportarbiter.v
+// Generated   : 09/10/04 20:20:21
+// From        : c:\projects\USBHostSlave\RTL\hostController\hctxportarbiter.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+
+module HCTxPortArbiter (HCTxPortCntl, HCTxPortData, HCTxPortWEnable, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   [7:0] SOFCntlCntl;
+input   [7:0] SOFCntlData;
+input   SOFCntlReq;
+input   SOFCntlWEn;
+input   clk;
+input   [7:0] directCntlCntl;
+input   [7:0] directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0] sendPacketCntl;
+input   [7:0] sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortWEnable;
+output  SOFCntlGnt;
+output  directCntlGnt;
+output  sendPacketGnt;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+reg     HCTxPortWEnable, next_HCTxPortWEnable;
+wire    [7:0] SOFCntlCntl;
+wire    [7:0] SOFCntlData;
+reg     SOFCntlGnt, next_SOFCntlGnt;
+wire    SOFCntlReq;
+wire    SOFCntlWEn;
+wire    clk;
+wire    [7:0] directCntlCntl;
+wire    [7:0] directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+wire    [7:0] sendPacketCntl;
+wire    [7:0] sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg  [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0] CurrState_HCTxArb;
+reg [2:0] NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+		 		 directCntlWEn or directCntlData or directCntlCntl or
+                  directCntlWEn or directCntlData or directCntlCntl or
+ 		  		 sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+    `SOF_CTRL_MUX :
+    begin
+        HCTxPortWEnable <= SOFCntlWEn;
+        HCTxPortData <= SOFCntlData;
+        HCTxPortCntl <= SOFCntlCntl;
+    end
+    `DIRECT_CTRL_MUX :
+    begin
+        HCTxPortWEnable <= directCntlWEn;
+        HCTxPortData <= directCntlData;
+        HCTxPortCntl <= directCntlCntl;
+    end
+    `SEND_PACKET_MUX :
+    begin
+        HCTxPortWEnable <= sendPacketWEn;
+        HCTxPortData <= sendPacketData;
+        HCTxPortCntl <= sendPacketCntl;
+    end
+    default :
+    begin
+        HCTxPortWEnable <= 1'b0;
+        HCTxPortData <= 8'h00;
+        HCTxPortCntl <= 8'h00;
+    end
+endcase
+end
+
+
+//--------------------------------------------------------------------
+// Machine: HCTxArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or muxCntl or sendPacketGnt or directCntlGnt or CurrState_HCTxArb)
+begin : HCTxArb_NextState
+	NextState_HCTxArb <= CurrState_HCTxArb;
+	// Set default values for outputs and signals
+	next_SOFCntlGnt <= SOFCntlGnt;
+	next_muxCntl <= muxCntl;
+	next_sendPacketGnt <= sendPacketGnt;
+	next_directCntlGnt <= directCntlGnt;
+	case (CurrState_HCTxArb) // synopsys parallel_case full_case
+		`START_HARB:
+			NextState_HCTxArb <= `WAIT_REQ;
+		`WAIT_REQ:
+			if (SOFCntlReq == 1'b1)	
+			begin
+				NextState_HCTxArb <= `SEND_SOF;
+				next_SOFCntlGnt <= 1'b1;
+				next_muxCntl <= `SOF_CTRL_MUX;
+			end
+			else if (sendPacketReq == 1'b1)	
+			begin
+				NextState_HCTxArb <= `SEND_PACKET;
+				next_sendPacketGnt <= 1'b1;
+				next_muxCntl <= `SEND_PACKET_MUX;
+			end
+			else if (directCntlReq == 1'b1)	
+			begin
+				NextState_HCTxArb <= `DIRECT_CONTROL;
+				next_directCntlGnt <= 1'b1;
+				next_muxCntl <= `DIRECT_CTRL_MUX;
+			end
+		`SEND_SOF:
+			if (SOFCntlReq == 1'b0)	
+			begin
+				NextState_HCTxArb <= `WAIT_REQ;
+				next_SOFCntlGnt <= 1'b0;
+			end
+		`SEND_PACKET:
+			if (sendPacketReq == 1'b0)	
+			begin
+				NextState_HCTxArb <= `WAIT_REQ;
+				next_sendPacketGnt <= 1'b0;
+			end
+		`DIRECT_CONTROL:
+			if (directCntlReq == 1'b0)	
+			begin
+				NextState_HCTxArb <= `WAIT_REQ;
+				next_directCntlGnt <= 1'b0;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : HCTxArb_CurrentState
+	if (rst)	
+		CurrState_HCTxArb <= `START_HARB;
+	else
+		CurrState_HCTxArb <= NextState_HCTxArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : HCTxArb_RegOutput
+	if (rst)	
+	begin
+		muxCntl <= 2'b00;
+		SOFCntlGnt <= 1'b0;
+		sendPacketGnt <= 1'b0;
+		directCntlGnt <= 1'b0;
+	end
+	else 
+	begin
+		muxCntl <= next_muxCntl;
+		SOFCntlGnt <= next_SOFCntlGnt;
+		sendPacketGnt <= next_sendPacketGnt;
+		directCntlGnt <= next_directCntlGnt;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/sendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/sendpacket.asf	(revision 264)
@@ -0,0 +1,238 @@
+VERSION=1.19
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FREEOID=225
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,sendPacket"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 21
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 41
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 43
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 45
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "WAIT_ENABLE\n/1/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP\n/0/"
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "sndPkt"
+F 6 0 671089152 188 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: sendPacket"
+I 12 6 0 Builtin Reset | 74872,202290
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/"
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
+L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 113134,104869 113443,100466
+C 23 22 0 TEXT "Conditions" | 114645,116706 1 0 0 "HCTxPortGnt == 1'b1"
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500
+L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/"
+I 28 25 0 Builtin Entry | 48013,256695
+I 29 25 0 Builtin Exit | 144780,121920
+W 30 25 0 28 26 BEZIER "Transitions" | 52150,256695 56357,246454 59660,235429 67946,223821
+L 32 33 0 TEXT "State Labels" | 73797,179351 1 0 0 "FIN\n/4/"
+S 33 25 20480 ELLIPSE "States" | 73797,179351 6500 6500
+W 34 25 0 26 33 BEZIER "Transitions" | 71729,211913 72078,205195 72736,192521 73085,185803
+C 36 34 0 TEXT "Conditions" | 74012,211530 1 0 0 "HCTxPortRdy == 1'b1"
+A 37 34 16 TEXT "Actions" | 66378,203896 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= PIDNotPID;\nHCTxPortCntl <= `TX_PACKET_START;"
+A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 39 25 0 33 29 BEZIER "Transitions" | 78151,174526 94720,161687 125355,134759 141924,121920
+L 40 41 0 TEXT "State Labels" | 61608,50536 1 0 0 "OUT_IN_SETUP"
+S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500
+L 42 43 0 TEXT "State Labels" | 116148,48718 1 0 0 "SEND_SOF"
+S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,46294 1 0 0 "DATA0_DATA1"
+S 45 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,46294 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP\n/5/"
+S 47 6 36864 ELLIPSE "States" | 115848,16910 6500 6500
+W 48 6 8195 21 41 BEZIER "Transitions" | 108751,90198 97879,81365 77125,63914 66253,55081
+W 49 6 8194 21 43 BEZIER "Transitions" | 114327,87507 114704,79202 115453,63508 115830,55203
+W 50 6 8193 21 45 BEZIER "Transitions" | 119411,90353 134284,80236 162142,60327 177015,50210
+H 51 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+H 58 43 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,5152 212900,250284
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379
+W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311
+W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nHCTxPortReq <= 1'b0;"
+C 79 48 0 TEXT "Conditions" | 70608,88862 1 0 0 "PID == `OUT || \nPID == `IN || \nPID == `SETUP"
+S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
+C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
+C 81 50 0 TEXT "Conditions" | 136066,86256 1 0 0 "PID == `DATA0 || PID == `DATA1"
+W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
+I 83 51 0 Builtin Exit | 161275,73621
+I 84 51 0 Builtin Entry | 48374,241112
+S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
+L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
+S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500
+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
+L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/"
+I 111 58 0 Builtin Entry | 69864,225148
+I 110 58 0 Builtin Exit | 176204,35771
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
+W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
+L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
+I 127 65 0 Builtin Exit | 176933,37229
+I 126 65 0 Builtin Entry | 68558,236856
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1;	 \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 173 0 2 Builtin InPort | 35299,213676 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 2 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170179,37688 173765,37229
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+I 185 0 2 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 183 0 2 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+                                          48213,88528 42471,75064 41184,67490 39897,59917\
+                                          40491,43087 47668,36800 54846,30514 82962,22198\
+                                          91674,19921 100386,17644 105983,17263 109349,16867
+I 203 0 2 Builtin OutPort | 102204,236768 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 201 0 2 Builtin InPort | 101760,245904 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 199 0 2 Builtin OutPort | 101972,241240 "" ""
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 0 Builtin Signal | 35000,231468 "" ""
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+                                          200128,135446 205472,144130 205681,151728 205890,159327\
+                                          201380,181037 194241,189595 187102,198154 163054,210680\
+                                          152909,214312 142764,217944 127179,220153 118913,221155
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/sendpacketcheckpreamble.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/sendpacketcheckpreamble.asf	(revision 264)
@@ -0,0 +1,149 @@
+VERSION=1.19
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FREEOID=153
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,sendPacketCheckPreamble"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 32
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 95
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+A 45 44 16 TEXT "Actions" | 74811,210616 1 0 0 "fullSpeedBitRate <= 1'b1;\nfullSpeedPolarity <= 1'b1;\ngrabLineControl <= 1'b1;"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
+S 42 33 12288 ELLIPSE "States" | 88281,184091 6500 6500
+W 39 33 0 68 37 BEZIER "Transitions" | 95534,53084 101453,45264 180021,53114 185941,45293
+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 93181,145786 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 55 60 BEZIER "Transitions" | 89225,146684 89301,143318 91477,99456 91230,95807
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 59 56 16 TEXT "Actions" | 87075,172050 1 0 0 "sendPacketWEn <= 1'b0;"
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88382,164186 88295,159636
+S 55 33 20480 ELLIPSE "States" | 88650,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88650,153150 1 0 0 "WAIT_RDY2\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "WAIT_RDY3\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+A 66 65 16 TEXT "Actions" | 90202,77286 1 0 0 "sendPacketWEn <= 1'b0;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+A 64 62 16 TEXT "Actions" | 78524,125856 1 0 0 "fullSpeedBitRate <= 1'b1;"
+A 72 39 16 TEXT "Actions" | 141267,52580 1 0 0 "grabLineControl <= 1'b0;"
+C 73 39 0 TEXT "Conditions" | 97529,56755 1 0 0 "sendPacketRdy == 1'b1"
+L 74 75 0 TEXT "Labels" | 35624,223586 1 0 0 "grabLineControl"
+I 75 0 2 Builtin OutPort | 29624,223586 "" ""
+L 76 77 0 TEXT "Labels" | 37072,218796 1 0 0 "fullSpeedPolarity"
+I 77 0 2 Builtin OutPort | 29360,218796 "" ""
+L 78 79 0 TEXT "Labels" | 35397,214093 1 0 0 "fullSpeedBitRate"
+I 79 0 2 Builtin OutPort | 29397,214093 "" ""
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+                                        94907,51569 61918,50756 52575,52503 43232,54250\
+                                        38843,62050 37706,72734 36569,83418 36406,118357\
+                                        40062,129609 43718,140862 58507,150938 67687,153172\
+                                        76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 95904,234688 "" ""
+L 150 151 0 TEXT "Labels" | 101904,234688 1 0 0 "preAmbleEnable"
+K 149 75 0 TEXT "Comments" | 60868,223364 1 0 0 "mux select"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nfullSpeedBitRate <= 1'b0;\nfullSpeedPolarity <= 1'b0;\ngrabLineControl <= 1'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/softransmit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/softransmit.asf	(revision 264)
@@ -0,0 +1,101 @@
+VERSION=1.19
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FREEOID=73
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,SOFTransmit"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+F 6 0 671089152 54 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+W 27 6 8193 15 26 BEZIER "Transitions" | 127758,63214 198581,44766 138746,22583 123372,21429
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+                                     119442,151760 119430,151725 119430,151571
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+I 16 6 0 Builtin Reset | 76112,190530
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+I 32 0 2 Builtin OutPort | 29866,205279 "" ""
+L 33 32 0 TEXT "Labels" | 35866,205279 1 0 0 "sendPacketWEn"
+I 34 0 2 Builtin InPort | 85672,219426 "" ""
+L 35 34 0 TEXT "Labels" | 91672,219426 1 0 0 "SOFSyncEn"
+L 40 41 0 TEXT "Labels" | 89735,214646 1 0 0 "SOFSent"
+I 41 0 2 Builtin OutPort | 83735,214646 "" ""
+K 44 41 0 TEXT "Comments" | 107898,214935 1 0 0 "single cycle pulse"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;"
+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+I 47 0 2 Builtin OutPort | 83987,210042 "" ""
+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+A 50 26 4 TEXT "Actions" | 141965,16918 1 0 0 "sendPacketWEn <= 1'b0;\nSOFTimerClr <= 1'b0;\nSOFSent <= 1'b0;"
+W 51 6 0 26 11 BEZIER "Transitions" | 117404,14128 103585,14128 76675,12449 68441,16586\
+                                      60208,20724 54912,37274 53629,49148 52346,61023\
+                                      52495,91978 54333,104221 56172,116465 66907,131666\
+                                      73940,137333 80974,143001 92272,144264 98160,144352\
+                                      104049,144440 109926,143957 113732,143626
+L 53 54 0 TEXT "Labels" | 206335,250729 1 0 0 "clk"
+I 54 0 1 Builtin InPort | 200335,250729 "" ""
+C 55 17 0 TEXT "Conditions" | 98239,182492 1 0 0 "rst"
+I 56 0 130 Builtin InPort | 200475,245251 "" ""
+L 57 56 0 TEXT "Labels" | 206475,245251 1 0 0 "rst"
+I 58 0 2 Builtin InPort | 32035,210006 "" ""
+L 59 58 0 TEXT "Labels" | 38035,210006 1 0 0 "sendPacketRdy"
+I 60 0 2 Builtin InPort | 85642,229951 "" ""
+L 61 60 0 TEXT "Labels" | 91642,229951 1 0 0 "SOFEnable"
+I 62 0 2 Builtin OutPort | 29880,214737 "" ""
+L 63 62 0 TEXT "Labels" | 35880,214737 1 0 0 "sendPacketArbiterReq"
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+A 67 51 16 TEXT "Actions" | 33349,35565 1 0 0 "sendPacketArbiterReq <= 1'b0;"
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+                                         105450,47318 105450,38252 107207,34228 108965,30205\
+                                         115846,23167 119361,19652
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/speedCtrlMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/speedCtrlMux.v	(revision 264)
@@ -0,0 +1,82 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// speedCtrlMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: speedCtrlMux.v,v 1.1.1.1 2004-10-11 04:00:55 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input   directCtrlRate;
+input   directCtrlPol;
+input   sendPacketRate;
+input   sendPacketPol;
+input   sendPacketSel;
+output  fullSpeedRate;
+output  fullSpeedPol;
+
+wire   directCtrlRate;
+wire   directCtrlPol;
+wire   sendPacketRate;
+wire   sendPacketPol;
+wire   sendPacketSel;
+reg   fullSpeedRate;
+reg   fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+  if (sendPacketSel == 1'b1) 
+  begin
+	fullSpeedRate <= sendPacketRate;
+	fullSpeedPol <= sendPacketPol;
+  end
+  else
+  begin
+	fullSpeedRate <= directCtrlRate;
+	fullSpeedPol <= directCtrlPol;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostSlaveMux/hostSlaveMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostSlaveMux/hostSlaveMux.v	(revision 264)
@@ -0,0 +1,168 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostSlaveMux.v,v 1.1.1.1 2004-10-11 04:00:56 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module hostSlaveMux (
+	SIEPortCtrlInToSIE,
+	SIEPortCtrlInFromHost,
+	SIEPortCtrlInFromSlave,
+	SIEPortDataInToSIE, 
+	SIEPortDataInFromHost, 
+	SIEPortDataInFromSlave, 
+	SIEPortWEnToSIE, 
+	SIEPortWEnFromHost, 
+	SIEPortWEnFromSlave, 
+	fullSpeedPolarityToSIE,
+	fullSpeedPolarityFromHost,
+	fullSpeedPolarityFromSlave,
+	fullSpeedBitRateToSIE,
+	fullSpeedBitRateFromHost,
+	fullSpeedBitRateFromSlave,
+  dataIn, 
+  dataOut, 
+  writeEn,
+  strobe_i,
+  clk, 
+  rst,
+  hostSlaveMuxSel  );
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE; 
+input [7:0] SIEPortDataInFromHost; 
+input [7:0] SIEPortDataInFromSlave; 
+output SIEPortWEnToSIE; 
+input SIEPortWEnFromHost; 
+input SIEPortWEnFromSlave; 
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE; 
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+reg SIEPortWEnToSIE; 
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+	SIEPortCtrlInFromHost or
+	SIEPortCtrlInFromSlave or
+	SIEPortDataInFromHost or 
+	SIEPortDataInFromSlave or 
+	SIEPortWEnFromHost or 
+	SIEPortWEnFromSlave or 
+	fullSpeedPolarityFromHost or
+	fullSpeedPolarityFromSlave or
+	fullSpeedBitRateFromHost or
+	fullSpeedBitRateFromSlave)
+begin
+  if (hostMode == 1'b1) 
+  begin
+	  SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+	  SIEPortDataInToSIE <=	SIEPortDataInFromHost;
+	  SIEPortWEnToSIE <= SIEPortWEnFromHost;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+  end
+  else
+  begin
+	  SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+	  SIEPortDataInToSIE <=	SIEPortDataInFromSlave;
+	  SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+  end
+end      
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(dataIn), 
+  .dataOut(dataOut), 
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+	.hostMode(hostMode), 
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/include/usbSerialInterfaceEngine_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/include/usbSerialInterfaceEngine_h.v	(revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine_h.v                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSerialInterfaceEngine_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+ // Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate
+`define OVER_SAMPLE_RATE 4
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 6
+`define RESUME_WAIT_TIME 10
+`define RESUME_WAIT_TIME_MINUS1 9
+`define RESUME_LEN 20
+`define CONNECT_WAIT_TIME 8'd20
+`define DISCONNECT_WAIT_TIME 8'd20
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates 
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+
+

Property changes on: common/components/usbhostslave/tags/start/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/rel_01_01/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/rel_01_01/doc/USBHostSlave_IPCore_Specification.pdf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/buffers/RxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/buffers/RxFifoBI.v	(revision 264)
@@ -0,0 +1,131 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: RxFifoBI.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+  address, 
+  writeEn, 
+  strobe_i,
+  clk, 
+  rst, 
+  fifoSelect,
+  fifoDataIn,
+  busDataIn, 
+  busDataOut,
+  fifoREn,
+  fifoEmpty,
+  forceEmpty,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoREn;
+input fifoEmpty;
+output forceEmpty;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoREn;
+wire fifoEmpty;
+reg forceEmpty;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+
+//sync write
+always @(posedge clk)
+begin
+	if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo or fifoEmpty)
+begin
+	case (address)
+      `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoEmpty};
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00; 
+	endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b0 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoREn <= 1'b1;
+  else
+    fifoREn <= 1'b0;
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/buffers/fifoRTL.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/buffers/fifoRTL.v	(revision 264)
@@ -0,0 +1,146 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoRTL.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+////  User must check full and empty flags before accessing fifo
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoRTL.v,v 1.1.1.1 2004-10-11 04:00:51 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+
+module fifoRTL(clk, rst, dataIn, dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, forceEmpty, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+  parameter FIFO_WIDTH = 8;
+	parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input clk;
+input rst;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoWEn;
+input fifoREn;
+output fifoFull;
+output fifoEmpty;
+input forceEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire clk;
+wire rst;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg  [15:0]numElementsInFifo;
+
+
+// local registers
+reg  [ADDR_WIDTH-1:0]bufferInIndex;
+reg  [ADDR_WIDTH-1:0]bufferOutIndex;
+reg  [ADDR_WIDTH:0]bufferCnt;
+reg  fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || forceEmpty == 1'b1)
+  begin
+    bufferCnt <= 0;
+    fifoFull <= 1'b0;
+    fifoEmpty <= 1'b1;
+		bufferInIndex <= 0;
+		bufferOutIndex <= 0;
+    fifoREnDelayed <= 1'b0;
+	end
+    else
+    begin
+      if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        dataOut <= dataFromMem;
+      end
+      fifoREnDelayed <= fifoREn;
+      if (fifoWEn == 1'b1 && fifoREn == 1'b0) begin
+        bufferCnt <= bufferCnt + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end 
+      else if (fifoWEn == 1'b0 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferCnt <= bufferCnt - 1;
+        bufferOutIndex <= bufferOutIndex + 1;
+      end
+      else if (fifoWEn == 1'b1 && fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        bufferOutIndex <= bufferOutIndex + 1;
+        bufferInIndex <= bufferInIndex + 1;
+      end
+      if (bufferCnt[ADDR_WIDTH] == 1'b1)
+        fifoFull <= 1'b1;
+      else
+        fifoFull <= 1'b0;
+      if (|bufferCnt == 1'b0) 
+        fifoEmpty <= 1'b1;
+      else
+        fifoEmpty <= 1'b0;
+    end
+end
+
+//pad bufferCnt with leading zeroes
+always @(bufferCnt) begin
+  numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt };
+end
+
+fifoMem #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_fifoMem (
+	.addrIn(bufferInIndex),
+	.addrOut(bufferOutIndex),
+	.clk(clk),
+	.dataIn(dataIn),
+	.writeEn(fifoWEn),
+	.readEn(fifoREn),
+	.dataOut(dataFromMem));
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/directcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/directcontrol.asf	(revision 264)
@@ -0,0 +1,132 @@
+VERSION=1.19
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FREEOID=180
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/20/2004"
+HEADER_PARAM="TITLE,directControl"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 78
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 127
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: directControl"
+A 5 0 1 TEXT "Actions" | 17700,253700 1 0 0 "// diagram ACTION"
+F 6 0 671089152 16 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "drctCntl"
+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_DC\n/0/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+I 13 6 0 Builtin Reset | 48900,215400
+W 14 6 0 13 9 BEZIER "Transitions" | 48900,215400 60300,214600 83007,213291 94407,212491
+L 15 16 0 TEXT "Labels" | 187300,263800 1 0 0 "clk"
+I 16 0 3 Builtin InPort | 181300,263800 "" ""
+L 17 18 0 TEXT "Labels" | 187500,257400 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 181500,257400 "" ""
+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
+L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn"
+I 21 0 2 Builtin InPort | 57252,239123 "" ""
+W 26 6 0 9 11 BEZIER "Transitions" | 100525,205718 101125,199618 101292,188766 101892,182666
+W 27 6 8193 11 78 BEZIER "Transitions" | 99393,170493 94693,161093 75357,144887 70657,135487
+C 28 27 0 TEXT "Conditions" | 80136,160617 1 0 0 "directControlEn == 1'b1"
+W 51 6 8194 11 127 BEZIER "Transitions" | 108159,173005 122851,164817 139855,136277 144754,128309
+L 77 78 0 TEXT "State Labels" | 68590,129326 1 0 0 "DRCT_CNTL"
+S 78 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 68590,129326 6500 6500
+H 79 78 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 88 79 4096 124 90 BEZIER "Transitions" | 105569,175900 100869,166500 70569,161175 65869,151775
+S 90 79 12288 ELLIPSE "States" | 62621,146145 6500 6500
+L 91 90 0 TEXT "State Labels" | 62621,146145 1 0 0 "WAIT_GNT\n/2/"
+W 92 79 8194 93 102 BEZIER "Transitions" | 62907,72842 59107,76242 50421,81945 48421,85645\
+                                           46421,89345 46021,97345 47471,100295 48921,103245\
+                                           55748,105011 58848,106911
+S 93 79 16384 ELLIPSE "States" | 68621,69745 6500 6500
+A 94 93 4 TEXT "Actions" | 87021,72145 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 95 79 0 102 93 BEZIER "Transitions" | 65496,102474 65896,97574 67230,81067 67630,76167
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;"
+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1"
+L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/"
+W 99 79 0 90 102 BEZIER "Transitions" | 62834,139649 63234,133449 64005,121613 64405,115413
+C 100 99 0 TEXT "Conditions" | 62221,136545 1 0 0 "HCTxPortGnt == 1'b1"
+S 102 79 20480 ELLIPSE "States" | 65021,108945 6500 6500
+L 103 102 0 TEXT "State Labels" | 65021,108945 1 0 0 "WAIT_RDY\n/4/"
+I 122 79 0 Builtin Exit | 138103,36586
+I 124 79 0 Builtin Entry | 109800,175900
+W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\
+                                       47285,153175 50048,167625 56316,171290 62585,174956\
+                                       84856,175714 96012,175820
+L 126 127 0 TEXT "State Labels" | 147819,122579 1 0 0 "IDLE"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
+H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
+C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "HCTxPortGnt == 1'b1"
+S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;"
+S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "HCTxPortReq <= 1'b1;"
+I 150 128 0 Builtin Entry | 67068,204814
+I 151 128 0 Builtin Exit | 67380,61048
+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+                                        171826,160150 159742,169266 150997,171704 142252,174142\
+                                        120424,175336 108976,175654
+I 154 0 2 Builtin OutPort | 108837,257571 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "HCTxPortCntl[7:0]"
+I 156 0 2 Builtin OutPort | 109440,251139 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "HCTxPortWEn"
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "HCTxPortRdy"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "HCTxPortGnt"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
+A 166 9 2 TEXT "Actions" | 121708,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+I 179 0 2 Builtin InPort | 57352,249414 "" ""
+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/hctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/hctxportarbiter.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.19
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FREEOID=101
+"LIBRARIES=`timescale 1ns / 1ps\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/20/2004"
+HEADER_PARAM="TITLE,HCTxPortArbiter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 431800,558800
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SEND_PACKET\n/3/"
+S 14 6 12288 ELLIPSE "States" | 269063,296392 6500 6500
+L 13 12 0 TEXT "State Labels" | 191859,293613 1 0 0 "SEND_SOF\n/2/"
+S 12 6 8192 ELLIPSE "States" | 191859,293613 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "WAIT_REQ\n/1/"
+S 10 6 4096 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_HARB\n/0/"
+S 8 6 0 ELLIPSE "States" | 225591,395370 6500 6500
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "HCTxArb"
+F 6 0 671089152 41 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,543100 1 0 0 "Module: HCTxPortArbiter"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+W 28 6 0 12 10 BEZIER "Transitions" | 186560,297376 167155,311353 168429,333163 167686,340659\
+                                      166944,348155 168507,364217 173450,370590 178394,376963\
+                                      186275,384997 193806,383684 201338,382371 213515,373400\
+                                      220004,369229
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+                                      288786,359372 287077,371461 282417,376909 277757,382357\
+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+C 26 17 0 TEXT "Conditions" | 201742,391978 1 0 0 "rst"
+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
+A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxCntl <= `SEND_PACKET_MUX;"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+C 21 20 0 TEXT "Conditions" | 185611,358255 1 0 0 "SOFCntlReq == 1'b1"
+W 20 6 1 10 12 BEZIER "Transitions" | 219884,360995 214322,355742 203672,314353 193976,299756
+W 19 6 2 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210052,391894 219337,393602
+I 16 6 0 Builtin Reset | 178237,395710
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n  `SOF_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= SOFCntlWEn;\n    HCTxPortData <= SOFCntlData;\n    HCTxPortCntl <= SOFCntlCntl;\n  end\n  `DIRECT_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= directCntlWEn;\n    HCTxPortData <= directCntlData;\n    HCTxPortCntl <= directCntlCntl;\n  end\n  `SEND_PACKET_MUX :\n  begin  \n    HCTxPortWEnable <= sendPacketWEn;\n    HCTxPortData <= sendPacketData;\n    HCTxPortCntl <= sendPacketCntl;\n  end\n  default :\n  begin  \n    HCTxPortWEnable <= 1'b0;\n    HCTxPortData <= 8'h00;\n    HCTxPortCntl <= 8'h00;\n  end\nendcase	\nend"
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286404,388600 275724,388298\
+                                      265045,387996 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/rxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/rxStatusMonitor.v	(revision 264)
@@ -0,0 +1,99 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// rxStatusMonitor.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: rxStatusMonitor.v,v 1.1.1.1 2004-10-11 04:00:53 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+	connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+	if (rst == 1'b1)
+	begin
+		oldConnectState <= connectStateIn;
+		oldResumeDetected <= resumeDetectedIn;
+	end
+	else
+	begin
+		oldConnectState <= connectStateIn;
+		oldResumeDetected <= resumeDetectedIn;
+		if (oldConnectState != connectStateIn)
+			connectionEventOut <= 1'b1;
+		else
+			connectionEventOut <= 1'b0;
+		if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+			resumeIntOut <= 1'b1;
+		else 
+			resumeIntOut <= 1'b0;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/sendpacketarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/sendpacketarbiter.v	(revision 264)
@@ -0,0 +1,153 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacketarbiter.v
+// Generated   : 09/10/04 20:20:24
+// From        : c:\projects\USBHostSlave\RTL\hostController\sendpacketarbiter.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (HCTxGnt, HCTxReq, HC_PID, HC_SP_WEn, SOFTxGnt, SOFTxReq, SOF_SP_WEn, clk, rst, sendPacketPID, sendPacketWEnable);
+input   HCTxReq;
+input   [3:0] HC_PID;
+input   HC_SP_WEn;
+input   SOFTxReq;
+input   SOF_SP_WEn;
+input   clk;
+input   rst;
+output  HCTxGnt;
+output  SOFTxGnt;
+output  [3:0] sendPacketPID;
+output  sendPacketWEnable;
+
+reg     HCTxGnt, next_HCTxGnt;
+wire    HCTxReq;
+wire    [3:0] HC_PID;
+wire    HC_SP_WEn;
+reg     SOFTxGnt, next_SOFTxGnt;
+wire    SOFTxReq;
+wire    SOF_SP_WEn;
+wire    clk;
+wire    rst;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+reg     sendPacketWEnable, next_sendPacketWEnable;
+
+// diagram signals declarations
+reg muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0] CurrState_sendPktArb;
+reg [1:0] NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+    if (muxSOFNotHC  == 1'b1)
+    begin
+        sendPacketWEnable <= SOF_SP_WEn;
+        sendPacketPID <= `SOF;
+    end
+    else
+    begin
+        sendPacketWEnable <= HC_SP_WEn;
+        sendPacketPID <= HC_PID;
+    end
+end
+
+
+//--------------------------------------------------------------------
+// Machine: sendPktArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin : sendPktArb_NextState
+	NextState_sendPktArb <= CurrState_sendPktArb;
+	// Set default values for outputs and signals
+	next_HCTxGnt <= HCTxGnt;
+	next_SOFTxGnt <= SOFTxGnt;
+	next_muxSOFNotHC <= muxSOFNotHC;
+	case (CurrState_sendPktArb) // synopsys parallel_case full_case
+		`HC_ACT:
+			if (HCTxReq == 1'b0)	
+			begin
+				NextState_sendPktArb <= `SARB_WAIT_REQ;
+				next_HCTxGnt <= 1'b0;
+			end
+		`SOF_ACT:
+			if (SOFTxReq == 1'b0)	
+			begin
+				NextState_sendPktArb <= `SARB_WAIT_REQ;
+				next_SOFTxGnt <= 1'b0;
+			end
+		`SARB_WAIT_REQ:
+			if (SOFTxReq == 1'b1)	
+			begin
+				NextState_sendPktArb <= `SOF_ACT;
+				next_SOFTxGnt <= 1'b1;
+				next_muxSOFNotHC <= 1'b1;
+			end
+			else if (HCTxReq == 1'b1)	
+			begin
+				NextState_sendPktArb <= `HC_ACT;
+				next_HCTxGnt <= 1'b1;
+				next_muxSOFNotHC <= 1'b0;
+			end
+		`START_SARB:
+			NextState_sendPktArb <= `SARB_WAIT_REQ;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktArb_CurrentState
+	if (rst)	
+		CurrState_sendPktArb <= `START_SARB;
+	else
+		CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktArb_RegOutput
+	if (rst)	
+	begin
+		muxSOFNotHC <= 1'b0;
+		SOFTxGnt <= 1'b0;
+		HCTxGnt <= 1'b0;
+	end
+	else 
+	begin
+		muxSOFNotHC <= next_muxSOFNotHC;
+		SOFTxGnt <= next_SOFTxGnt;
+		HCTxGnt <= next_HCTxGnt;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/sofcontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/sofcontroller.v	(revision 264)
@@ -0,0 +1,152 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sofcontroller.v
+// Generated   : 09/08/04 06:24:36
+// From        : c:\projects\USBHostSlave\RTL\hostController\sofcontroller.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, SOFEnable, SOFTimerClr, SOFTimer, clk, rst);
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   SOFEnable;
+input   SOFTimerClr;
+input   clk;
+input   rst;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [15:0] SOFTimer;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    SOFEnable;
+wire    SOFTimerClr;
+reg     [15:0] SOFTimer, next_SOFTimer;
+wire    clk;
+wire    rst;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0] CurrState_sofCntl;
+reg [2:0] NextState_sofCntl;
+
+
+//--------------------------------------------------------------------
+// Machine: sofCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl)
+begin : sofCntl_NextState
+	NextState_sofCntl <= CurrState_sofCntl;
+	// Set default values for outputs and signals
+	next_HCTxPortReq <= HCTxPortReq;
+	next_HCTxPortWEn <= HCTxPortWEn;
+	next_HCTxPortData <= HCTxPortData;
+	next_HCTxPortCntl <= HCTxPortCntl;
+	next_SOFTimer <= SOFTimer;
+	case (CurrState_sofCntl) // synopsys parallel_case full_case
+		`START_SC:
+			NextState_sofCntl <= `WAIT_SOF_EN;
+		`WAIT_SOF_EN:
+			if (SOFEnable == 1'b1)	
+			begin
+				NextState_sofCntl <= `SC_WAIT_GNT;
+				next_HCTxPortReq <= 1'b1;
+			end
+		`WAIT_SEND_RESUME:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sofCntl <= `CLR_WEN;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= 8'h00;
+				next_HCTxPortCntl <= `TX_RESUME_START;
+			end
+		`INC_TIMER:
+		begin
+			next_HCTxPortReq <= 1'b0;
+			if (SOFTimerClr == 1'b1)
+			  next_SOFTimer <= 16'h0000;
+			else
+			  next_SOFTimer <= SOFTimer + 1'b1;
+			if (SOFEnable == 1'b0)	
+			begin
+				NextState_sofCntl <= `WAIT_SOF_EN;
+				next_SOFTimer <= 16'h0000;
+			end
+		end
+		`SC_WAIT_GNT:
+			if (HCTxPortGnt == 1'b1)	
+				NextState_sofCntl <= `WAIT_SEND_RESUME;
+		`CLR_WEN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sofCntl <= `INC_TIMER;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sofCntl_CurrentState
+	if (rst)	
+		CurrState_sofCntl <= `START_SC;
+	else
+		CurrState_sofCntl <= NextState_sofCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sofCntl_RegOutput
+	if (rst)	
+	begin
+		SOFTimer <= 16'h0000;
+		HCTxPortCntl <= 8'h00;
+		HCTxPortData <= 8'h00;
+		HCTxPortWEn <= 1'b0;
+		HCTxPortReq <= 1'b0;
+	end
+	else 
+	begin
+		SOFTimer <= next_SOFTimer;
+		HCTxPortCntl <= next_HCTxPortCntl;
+		HCTxPortData <= next_HCTxPortData;
+		HCTxPortWEn <= next_HCTxPortWEn;
+		HCTxPortReq <= next_HCTxPortReq;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/usbHostControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/usbHostControl.v	(revision 264)
@@ -0,0 +1,403 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostControl.v,v 1.1.1.1 2004-10-11 04:00:56 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+module usbHostControl(
+	clk, rst,
+	//sendPacket
+	TxFifoRE, TxFifoData, TxFifoEmpty,
+	//getPacket
+	RxFifoWE, RxFifoData, RxFifoFull,
+	RxByteStatus, RxData, RxDataValid,
+	SIERxTimeOut,
+	//speedCtrlMux
+	fullSpeedRate, fullSpeedPol,
+	//HCTxPortArbiter
+	HCTxPortEn, HCTxPortRdy,
+	HCTxPortData, HCTxPortCtrl,
+	//rxStatusMonitor
+	connectStateIn, 
+	resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+	SOFSentIntOut, 
+  connEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  hostControlSelect
+ 	 );
+
+input clk, rst;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [3:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut; 
+output connEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+input hostControlSelect;
+
+wire clk;
+wire rst;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut; 
+wire connEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire sendPacketCPFSRate;
+wire sendPacketCPFSPol;
+wire sendPacketCPGrabLine;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;	  
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire directCtrlRate;
+wire directCtrlPol;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI 
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+	.SOFSentIntOut(SOFSentIntOut), 
+  .connEventIntOut(connEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .TxTransTypeReg(transType), 
+  .TxSOFEnableReg(SOFEnable),
+	.TxAddrReg(TxAddr), 
+  .TxEndPReg(TxEndP), 
+  .frameNumIn(frameNum), 
+  .RxPktStatusIn(RxPktStatus), 
+  .RxPIDIn(RxPID),
+  .connectStateIn(connectStateOut),
+	.SOFSentIn(SOFSent), 
+  .connEventIn(connectionEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .hostControlSelect(hostControlSelect),
+  .clrTransReq(clrTxReq),
+  .preambleEn(preAmbleEnable),
+  .SOFSync(SOFSyncEn),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(directCtrlPol), 
+  .fullSpeedRate(directCtrlRate),
+  .transReq(transReq)
+  
+  );
+
+
+hostcontroller u_hostController
+	(.RXStatus(RxPktStatus), 
+	.clearTXReq(clrTxReq),
+	.clk(clk),
+	.getPacketREn(getPacketREn),
+	.getPacketRdy(getPacketRdy),
+	.rst(rst),
+	.sendPacketArbiterGnt(HCTxGnt),
+	.sendPacketArbiterReq(HCTxReq),
+	.sendPacketPID(HC_PID),
+	.sendPacketRdy(sendPacketCPReadyOut),
+	.sendPacketWEn(HC_SP_WEn),
+	.transDone(transDone),
+	.transReq(transReq),
+	.transType(transType) );
+
+SOFController u_SOFController
+	(.HCTxPortCntl(SOFCntlCntl),
+	.HCTxPortData(SOFCntlData),
+	.HCTxPortGnt(SOFCntlGnt),
+	.HCTxPortRdy(HCTxPortRdy),
+	.HCTxPortReq(SOFCntlReq),
+	.HCTxPortWEn(SOFCntlWEn),
+	.SOFEnable(SOFEnable),
+	.SOFTimerClr(SOFTimerClr),
+	.SOFTimer(SOFTimer),
+	.clk(clk),
+	.rst(rst) ); 
+
+SOFTransmit u_SOFTransmit
+	(.SOFEnable(SOFEnable),
+	.SOFSent(SOFSent),
+	.SOFSyncEn(SOFSyncEn),
+	.SOFTimerClr(SOFTimerClr),
+	.SOFTimer(SOFTimer),
+	.clk(clk),
+	.rst(rst),
+	.sendPacketArbiterGnt(SOFTxGnt),
+	.sendPacketArbiterReq(SOFTxReq),
+	.sendPacketRdy(sendPacketCPReadyOut),
+	.sendPacketWEn(SOF_SP_WEn) );	
+
+
+sendPacketArbiter u_sendPacketArbiter
+	(.HCTxGnt(HCTxGnt),
+	.HCTxReq(HCTxReq),
+	.HC_PID(HC_PID),
+	.HC_SP_WEn(HC_SP_WEn),
+	.SOFTxGnt(SOFTxGnt),
+	.SOFTxReq(SOFTxReq),
+	.SOF_SP_WEn(SOF_SP_WEn),
+	.clk(clk),
+	.rst(rst),
+	.sendPacketPID(sendPacketCPPIDIn),
+	.sendPacketWEnable(sendPacketCPWEnIn) );	  
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+	(.sendPacketCPPID(sendPacketCPPIDIn),
+	.clk(clk),
+	.fullSpeedBitRate(sendPacketCPFSRate),
+	.fullSpeedPolarity(sendPacketCPFSPol),
+	.grabLineControl(sendPacketCPGrabLine),
+	.preAmbleEnable(preAmbleEnable),
+	.rst(rst),
+	.sendPacketCPReady(sendPacketCPReadyOut),
+	.sendPacketCPWEn(sendPacketCPWEnIn),
+	.sendPacketPID(sendPacketCPPIDOut),
+	.sendPacketRdy(sendPacketCPReadyIn),
+	.sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+	(.HCTxPortCntl(sendPacketCntl),
+	.HCTxPortData(sendPacketData),
+	.HCTxPortGnt(sendPacketGnt),
+	.HCTxPortRdy(HCTxPortRdy),
+	.HCTxPortReq(sendPacketReq),
+	.HCTxPortWEn(sendPacketWEn),
+	.PID(sendPacketCPPIDOut),
+	.TxAddr(TxAddr),
+	.TxEndP(TxEndP),
+	.clk(clk),
+	.fifoData(TxFifoData),
+	.fifoEmpty(TxFifoEmpty),
+	.fifoReadEn(TxFifoRE),
+	.frameNum(frameNum),
+	.rst(rst),
+	.sendPacketRdy(sendPacketCPReadyIn),
+	.sendPacketWEn(sendPacketCPWEnOut) );
+	
+directControl u_directControl
+	(.HCTxPortCntl(directCntlCntl),
+	.HCTxPortData(directCntlData),
+	.HCTxPortGnt(directCntlGnt),
+	.HCTxPortRdy(HCTxPortRdy),
+	.HCTxPortReq(directCntlReq),
+	.HCTxPortWEn(directCntlWEn),
+	.clk(clk),
+	.directControlEn(directLineCtrlEn),
+	.directControlLineState(directLineState),
+	.rst(rst) ); 
+
+HCTxPortArbiter u_HCTxPortArbiter
+	(.HCTxPortCntl(HCTxPortCtrl),
+	.HCTxPortData(HCTxPortData),
+	.HCTxPortWEnable(HCTxPortEn),
+	.SOFCntlCntl(SOFCntlCntl),
+	.SOFCntlData(SOFCntlData),
+	.SOFCntlGnt(SOFCntlGnt),
+	.SOFCntlReq(SOFCntlReq),
+	.SOFCntlWEn(SOFCntlWEn),
+	.clk(clk),
+	.directCntlCntl(directCntlCntl),
+	.directCntlData(directCntlData),
+	.directCntlGnt(directCntlGnt),
+	.directCntlReq(directCntlReq),
+	.directCntlWEn(directCntlWEn),
+	.rst(rst),
+	.sendPacketCntl(sendPacketCntl),
+	.sendPacketData(sendPacketData),
+	.sendPacketGnt(sendPacketGnt),
+	.sendPacketReq(sendPacketReq),
+	.sendPacketWEn(sendPacketWEn) );	  
+
+getPacket u_getPacket
+	(.RXDataIn(RxData),
+	.RXDataValid(RxDataValid),
+	.RXFifoData(RxFifoData),
+	.RXFifoFull(RxFifoFull),
+	.RXFifoWEn(RxFifoWE),
+	.RXPacketRdy(getPacketRdy),
+	.RXPktStatus(RxPktStatus),
+	.RXStreamStatusIn(RxByteStatus),
+	.RxPID(RxPID),
+	.SIERxTimeOut(SIERxTimeOut),
+	.clk(clk),
+	.getPacketEn(getPacketREn),
+	.rst(rst) ); 
+
+speedCtrlMux u_speedCtrlMux
+	(.directCtrlRate(directCtrlRate),
+	.directCtrlPol(directCtrlPol),
+	.sendPacketRate(sendPacketCPFSRate),
+	.sendPacketPol(sendPacketCPFSPol),
+	.sendPacketSel(sendPacketCPGrabLine),
+	.fullSpeedRate(fullSpeedRate),
+	.fullSpeedPol(fullSpeedPol) );
+
+rxStatusMonitor	u_rxStatusMonitor
+	(.connectStateIn(connectStateIn),
+	.connectStateOut(connectStateOut),
+	.resumeDetectedIn(resumeDetectedIn),
+	.connectionEventOut(connectionEventFromRxStatusMon),
+	.resumeIntOut(resumeIntFromRxStatusMon),
+	.clk(clk),
+	.rst(rst)  );
+
+endmodule
+
+	
+	
+
+
+
+

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/include/usbHostControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/include/usbHostControl_h.v	(revision 264)
@@ -0,0 +1,111 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl_h.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostControl_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+ 
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants 
+`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval
+`define SOF_TX_MARGIN 2
+       
+//Host RXStatusRegIndices 
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+

Property changes on: common/components/usbhostslave/tags/start/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/SIETransmitter.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/SIETransmitter.v	(revision 264)
@@ -0,0 +1,674 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\SIETransmitter.v
+// Generated   : 09/27/04 21:05:15
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\SIETransmitter.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOut, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst, rstCRC);
+input   [15:0] CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0] CRC5Result;
+input   CRC5UpdateRdy;
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [7:0] SIEPortCtrlIn;
+input   [7:0] SIEPortDataIn;
+input   SIEPortWEn;
+input   USBWireGnt;
+input   USBWireRdy;
+input   clk;
+input   processTxByteRdy;
+input   rst;
+output  CRC16En;
+output  CRC5En;
+output  CRC5_8Bit;
+output  [7:0] CRCData;
+output  SIEPortTxRdy;
+output  [7:0] TxByteOutCtrl;
+output  [7:0] TxByteOut;
+output  USBWireCtrl;
+output  [1:0] USBWireData;
+output  USBWireReq;
+output  USBWireWEn;
+output  processTxByteWEn;
+output  rstCRC;
+
+reg     CRC16En, next_CRC16En;
+wire    [15:0] CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5En, next_CRC5En;
+wire    [4:0] CRC5Result;
+wire    CRC5UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     [7:0] CRCData, next_CRCData;
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [7:0] SIEPortCtrlIn;
+wire    [7:0] SIEPortDataIn;
+reg     SIEPortTxRdy, next_SIEPortTxRdy;
+wire    SIEPortWEn;
+reg     [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
+reg     [7:0] TxByteOut, next_TxByteOut;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0] USBWireData, next_USBWireData;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+wire    processTxByteRdy;
+reg     processTxByteWEn, next_processTxByteWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+
+// diagram signals declarations
+reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg  [7:0]SIEPortData, next_SIEPortData;
+reg  [4:0]i, next_i;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define RES_ST_CHK_FIN 6'b000000
+`define IDLE_CHK_FIN 6'b000001
+`define DIR_CTL_CHK_FIN 6'b000010
+`define PKT_ST_CHK_PID 6'b000011
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000100
+`define PKT_ST_SPCL_PKT_SENT 6'b000101
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b000110
+`define PKT_ST_TKN_PID_PKT_SENT 6'b000111
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b001000
+`define PKT_ST_DATA_PID_PKT_SENT 6'b001001
+`define PKT_ST_HS_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_S1 6'b001110
+`define RES_ST_S3 6'b001111
+`define RES_ST_S4 6'b010000
+`define RES_ST_S5 6'b010001
+`define RES_ST_S6 6'b010010
+`define PKT_ST_SPCL_SEND_IDLE1 6'b010011
+`define PKT_ST_SPCL_SEND_IDLE2 6'b010100
+`define PKT_ST_SPCL_SEND_IDLE3 6'b010101
+`define START_SIETX 6'b010110
+`define STX_CHK_ST 6'b010111
+`define STX_WAIT_BYTE 6'b011000
+`define IDLE_STX_WAIT_GNT 6'b011001
+`define IDLE_STX_WAIT_RDY 6'b011010
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b011011
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b011100
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b011101
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011110
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011111
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b100000
+`define DIR_CTL_WAIT_GNT 6'b100001
+`define RES_ST_WAIT_GNT 6'b100010
+`define PKT_ST_HS_WAIT_RDY 6'b100011
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100100
+`define PKT_ST_SPCL_WAIT_RDY 6'b100101
+`define RES_ST_WAIT_RDY 6'b100110
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100111
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b101000
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b101001
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b101010
+`define DIR_CTL_WAIT_RDY 6'b101011
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b101100
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b101101
+`define PKT_ST_WAIT_RDY_PKT 6'b101110
+`define PKT_ST_SPCL_WAIT_WIRE 6'b101111
+`define PKT_ST_WAIT_RDY_WIRE 6'b110000
+`define PKT_ST_WAIT_GNT 6'b110001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b110010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b110011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b110100
+
+reg [5:0] CurrState_SIETx;
+reg [5:0] NextState_SIETx;
+
+
+//--------------------------------------------------------------------
+// Machine: SIETx
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SIEPortDataIn or SIEPortCtrlIn or i or SIEPortData or JBit or CRC16Result or CRC5Result or KBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or CurrState_SIETx)
+begin : SIETx_NextState
+	NextState_SIETx <= CurrState_SIETx;
+	// Set default values for outputs and signals
+	next_processTxByteWEn <= processTxByteWEn;
+	next_TxByteOut <= TxByteOut;
+	next_TxByteOutCtrl <= TxByteOutCtrl;
+	next_USBWireData <= USBWireData;
+	next_USBWireCtrl <= USBWireCtrl;
+	next_USBWireReq <= USBWireReq;
+	next_USBWireWEn <= USBWireWEn;
+	next_rstCRC <= rstCRC;
+	next_CRCData <= CRCData;
+	next_CRC5En <= CRC5En;
+	next_CRC5_8Bit <= CRC5_8Bit;
+	next_CRC16En <= CRC16En;
+	next_SIEPortTxRdy <= SIEPortTxRdy;
+	next_SIEPortData <= SIEPortData;
+	next_SIEPortCtrl <= SIEPortCtrl;
+	next_i <= i;
+	case (CurrState_SIETx) // synopsys parallel_case full_case
+		`START_SIETX:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			next_TxByteOut <= 8'h00;
+			next_TxByteOutCtrl <= 8'h00;
+			next_USBWireData <= 2'b00;
+			next_USBWireCtrl <= `TRI_STATE;
+			next_USBWireReq <= 1'b0;
+			next_USBWireWEn <= 1'b0;
+			next_rstCRC <= 1'b0;
+			next_CRCData <= 8'h00;
+			next_CRC5En <= 1'b0;
+			next_CRC5_8Bit <= 1'b0;
+			next_CRC16En <= 1'b0;
+			next_SIEPortTxRdy <= 1'b0;
+			next_SIEPortData <= 8'h00;
+			next_SIEPortCtrl <= 8'h00;
+			next_i <= 5'h0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`STX_CHK_ST:
+			if (SIEPortCtrl == `TX_PACKET_START)	
+			begin
+				NextState_SIETx <= `PKT_ST_WAIT_GNT;
+				next_USBWireReq <= 1'b1;
+			end
+			else if (SIEPortCtrl == `TX_IDLE)	
+			begin
+				NextState_SIETx <= `IDLE_STX_WAIT_GNT;
+				next_USBWireReq <= 1'b1;
+			end
+			else if (SIEPortCtrl == `TX_DIRECT_CONTROL)	
+			begin
+				NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+				next_USBWireReq <= 1'b1;
+			end
+			else if (SIEPortCtrl == `TX_RESUME_START)	
+			begin
+				NextState_SIETx <= `RES_ST_WAIT_GNT;
+				next_USBWireReq <= 1'b1;
+				next_i <= 5'h0;
+			end
+		`STX_WAIT_BYTE:
+		begin
+			next_SIEPortTxRdy <= 1'b1;
+			if (SIEPortWEn == 1'b1)	
+			begin
+				NextState_SIETx <= `STX_CHK_ST;
+				next_SIEPortData <= SIEPortDataIn;
+				next_SIEPortCtrl <= SIEPortCtrlIn;
+				next_SIEPortTxRdy <= 1'b0;
+			end
+		end
+		`DIR_CTL_CHK_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_i <= i + 1'b1;
+			if (i == 5'h7)	
+			begin
+				NextState_SIETx <= `STX_WAIT_BYTE;
+				next_USBWireReq <= 1'b0;
+			end
+			else
+				NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+		end
+		`DIR_CTL_WAIT_GNT:
+		begin
+			next_i <= 5'h0;
+			if (USBWireGnt == 1'b1)	
+				NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+		end
+		`DIR_CTL_WAIT_RDY:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `DIR_CTL_CHK_FIN;
+				next_USBWireData <= SIEPortData[1:0];
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`IDLE_CHK_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_i <= i + 1'b1;
+			if (i == 5'h7)	
+			begin
+				NextState_SIETx <= `STX_WAIT_BYTE;
+				next_USBWireReq <= 1'b0;
+			end
+			else
+				NextState_SIETx <= `IDLE_STX_WAIT_RDY;
+		end
+		`IDLE_STX_WAIT_GNT:
+		begin
+			next_i <= 5'h0;
+			if (USBWireGnt == 1'b1)	
+				NextState_SIETx <= `IDLE_STX_WAIT_RDY;
+		end
+		`IDLE_STX_WAIT_RDY:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `IDLE_CHK_FIN;
+				next_USBWireData <= 2'b00;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`PKT_ST_CHK_PID:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			if (SIEPortData[1:0] == `HANDSHAKE)	
+				NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+			else if (SIEPortData[1:0] == `TOKEN)	
+				NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+			else if (SIEPortData[1:0] == `SPECIAL)	
+				NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+			else if (SIEPortData[1:0] == `DATA)	
+				NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+		end
+		`PKT_ST_WAIT_RDY_PKT:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_USBWireReq <= 1'b0;
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_CHK_PID;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= `SYNC_BYTE;
+				next_TxByteOutCtrl <= `DATA_START;
+			end
+		end
+		`PKT_ST_WAIT_RDY_WIRE:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+				//actively drive the first J bit
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`PKT_ST_WAIT_GNT:
+			if (USBWireGnt == 1'b1)	
+				NextState_SIETx <= `PKT_ST_WAIT_RDY_WIRE;
+		`PKT_ST_DATA_CRC_PKT_SENT1:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+		end
+		`PKT_ST_DATA_CRC_PKT_SENT2:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`PKT_ST_DATA_CRC_WAIT_RDY1:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= ~CRC16Result[7:0];
+				next_TxByteOutCtrl <= `DATA_STREAM;
+			end
+		`PKT_ST_DATA_CRC_WAIT_RDY2:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= ~CRC16Result[15:8];
+				next_TxByteOutCtrl <= `DATA_STOP;
+			end
+		`PKT_ST_DATA_DATA_CHK_STOP:
+			if (SIEPortCtrl == `TX_PACKET_STOP)	
+				NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+			else
+				NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+		`PKT_ST_DATA_DATA_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+		end
+		`PKT_ST_DATA_DATA_UPD_CRC:
+		begin
+			next_CRCData <= SIEPortData;
+			next_CRC16En <= 1'b1;
+			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+		end
+		`PKT_ST_DATA_DATA_WAIT_BYTE:
+		begin
+			next_SIEPortTxRdy <= 1'b1;
+			if (SIEPortWEn == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+				next_SIEPortData <= SIEPortDataIn;
+				next_SIEPortCtrl <= SIEPortCtrlIn;
+				next_SIEPortTxRdy <= 1'b0;
+			end
+		end
+		`PKT_ST_DATA_DATA_WAIT_RDY:
+		begin
+			next_CRC16En <= 1'b0;
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STREAM;
+			end
+		end
+		`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+			if (CRC16UpdateRdy == 1'b1)	
+				NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+		`PKT_ST_DATA_PID_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			next_rstCRC <= 1'b0;
+			NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+		end
+		`PKT_ST_DATA_PID_WAIT_RDY:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STREAM;
+				next_rstCRC <= 1'b1;
+			end
+		`PKT_ST_HS_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`PKT_ST_HS_WAIT_RDY:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STOP;
+			end
+		`PKT_ST_SPCL_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `PKT_ST_SPCL_WAIT_WIRE;
+		end
+		`PKT_ST_SPCL_SEND_IDLE1:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE2;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`PKT_ST_SPCL_SEND_IDLE2:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE3;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`PKT_ST_SPCL_SEND_IDLE3:
+		begin
+			next_USBWireWEn <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`PKT_ST_SPCL_WAIT_RDY:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STOP;
+			end
+		`PKT_ST_SPCL_WAIT_WIRE:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_SPCL_SEND_IDLE1;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`PKT_ST_TKN_BYTE1_PKT_SENT1:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+		end
+		`PKT_ST_TKN_BYTE1_UPD_CRC:
+		begin
+			next_CRCData <= SIEPortData;
+			next_CRC5_8Bit <= 1'b1;
+			next_CRC5En <= 1'b1;
+			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+		end
+		`PKT_ST_TKN_BYTE1_WAIT_BYTE:
+		begin
+			next_SIEPortTxRdy <= 1'b1;
+			if (SIEPortWEn == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+				next_SIEPortData <= SIEPortDataIn;
+				next_SIEPortCtrl <= SIEPortCtrlIn;
+				next_SIEPortTxRdy <= 1'b0;
+			end
+		end
+		`PKT_ST_TKN_BYTE1_WAIT_RDY:
+		begin
+			next_CRC5En <= 1'b0;
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STREAM;
+			end
+		end
+		`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+			if (CRC5UpdateRdy == 1'b1)	
+				NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+		`PKT_ST_TKN_CRC_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`PKT_ST_TKN_CRC_UPD_CRC:
+		begin
+			next_CRCData <= SIEPortData;
+			next_CRC5_8Bit <= 1'b0;
+			next_CRC5En <= 1'b1;
+			NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+		end
+		`PKT_ST_TKN_CRC_WAIT_BYTE:
+		begin
+			next_SIEPortTxRdy <= 1'b1;
+			if (SIEPortWEn == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+				next_SIEPortData <= SIEPortDataIn;
+				next_SIEPortCtrl <= SIEPortCtrlIn;
+				next_SIEPortTxRdy <= 1'b0;
+			end
+		end
+		`PKT_ST_TKN_CRC_WAIT_RDY:
+		begin
+			next_CRC5En <= 1'b0;
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+				next_TxByteOutCtrl <= `DATA_STOP;
+			end
+		end
+		`PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+			if (CRC5UpdateRdy == 1'b1)	
+				NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+		`PKT_ST_TKN_PID_PKT_SENT:
+		begin
+			next_processTxByteWEn <= 1'b0;
+			next_rstCRC <= 1'b0;
+			NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+		end
+		`PKT_ST_TKN_PID_WAIT_RDY:
+			if (processTxByteRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+				next_processTxByteWEn <= 1'b1;
+				next_TxByteOut <= SIEPortData;
+				next_TxByteOutCtrl <= `DATA_STREAM;
+				next_rstCRC <= 1'b1;
+			end
+		`RES_ST_CHK_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (i == `RESUME_LEN)	
+				NextState_SIETx <= `RES_ST_S1;
+			else
+				NextState_SIETx <= `RES_ST_WAIT_RDY;
+		end
+		`RES_ST_S1:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_S3;
+				next_USBWireData <= `SE0;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		`RES_ST_S3:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_S4;
+				next_USBWireData <= `SE0;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`RES_ST_S4:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_S5;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`RES_ST_S5:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_S6;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+				next_USBWireWEn <= 1'b1;
+			end
+		end
+		`RES_ST_S6:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_USBWireReq <= 1'b0;
+			NextState_SIETx <= `STX_WAIT_BYTE;
+		end
+		`RES_ST_WAIT_GNT:
+			if (USBWireGnt == 1'b1)	
+				NextState_SIETx <= `RES_ST_WAIT_RDY;
+		`RES_ST_WAIT_RDY:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_SIETx <= `RES_ST_CHK_FIN;
+				next_USBWireData <= KBit;
+				next_USBWireCtrl <= `DRIVE;
+				next_USBWireWEn <= 1'b1;
+				next_i <= i + 1'b1;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SIETx_CurrentState
+	if (rst)	
+		CurrState_SIETx <= `START_SIETX;
+	else
+		CurrState_SIETx <= NextState_SIETx;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SIETx_RegOutput
+	if (rst)	
+	begin
+		SIEPortData <= 8'h00;
+		SIEPortCtrl <= 8'h00;
+		i <= 5'h0;
+		processTxByteWEn <= 1'b0;
+		TxByteOut <= 8'h00;
+		TxByteOutCtrl <= 8'h00;
+		USBWireData <= 2'b00;
+		USBWireCtrl <= `TRI_STATE;
+		USBWireReq <= 1'b0;
+		USBWireWEn <= 1'b0;
+		rstCRC <= 1'b0;
+		CRCData <= 8'h00;
+		CRC5En <= 1'b0;
+		CRC5_8Bit <= 1'b0;
+		CRC16En <= 1'b0;
+		SIEPortTxRdy <= 1'b0;
+	end
+	else 
+	begin
+		SIEPortData <= next_SIEPortData;
+		SIEPortCtrl <= next_SIEPortCtrl;
+		i <= next_i;
+		processTxByteWEn <= next_processTxByteWEn;
+		TxByteOut <= next_TxByteOut;
+		TxByteOutCtrl <= next_TxByteOutCtrl;
+		USBWireData <= next_USBWireData;
+		USBWireCtrl <= next_USBWireCtrl;
+		USBWireReq <= next_USBWireReq;
+		USBWireWEn <= next_USBWireWEn;
+		rstCRC <= next_rstCRC;
+		CRCData <= next_CRCData;
+		CRC5En <= next_CRC5En;
+		CRC5_8Bit <= next_CRC5_8Bit;
+		CRC16En <= next_CRC16En;
+		SIEPortTxRdy <= next_SIEPortTxRdy;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxByte.asf	(revision 264)
@@ -0,0 +1,292 @@
+VERSION=1.19
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FREEOID=384
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/9/2004"
+HEADER_PARAM="TITLE,processRxByte"
+END
+BUNDLES
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
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+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
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+END
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+END
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+A 295 293 4 TEXT "Actions" | 114075,218259 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC16Result != 16'hb001)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    RxDataOut <= RxByte;\n    RxCtrlOut <= `RX_PACKET_STREAM;\n    CRCData <= RxByte;\n    CRC16En <= 1'b1;\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
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+L 299 300 0 TEXT "Labels" | 82848,255265 1 0 0 "RxCtrlOut[7:0]"
+I 300 0 2 Builtin OutPort | 76848,255265 "" ""
+L 301 302 0 TEXT "Labels" | 82139,250245 1 0 0 "RxDataOutWEn"
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+                                      96662,35330 112340,35732
+C 55 51 0 TEXT "Conditions" | 43455,121392 1 0 0 "RXByteStMachCurrState == `CHECK_PID_ST"
+C 56 52 0 TEXT "Conditions" | 45596,90880 1 0 0 "RXByteStMachCurrState == `HS_BYTE_ST"
+C 57 53 0 TEXT "Conditions" | 45420,58426 1 0 0 "RXByteStMachCurrState == `TOKEN_BYTE_ST"
+C 58 54 0 TEXT "Conditions" | 46403,31524 1 0 0 "RXByteStMachCurrState == `DATA_BYTE_ST"
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "WAIT_BYTE\n/2/"
+S 63 6 24576 ELLIPSE "States" | 112744,173179 6500 6500
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+L 325 326 0 TEXT "Labels" | 175074,265120 1 0 0 "bitStuffError"
+I 326 0 2 Builtin Signal | 172074,265120 "" ""
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+I 328 0 2 Builtin Signal | 172074,260836 "" ""
+L 329 330 0 TEXT "Labels" | 175074,256552 1 0 0 "RxTimeOut"
+I 330 0 2 Builtin Signal | 172074,256552 "" ""
+L 331 332 0 TEXT "Labels" | 174717,252268 1 0 0 "NAKRxed"
+I 332 0 2 Builtin Signal | 171717,252268 "" ""
+L 333 334 0 TEXT "Labels" | 175074,247627 1 0 0 "stallRxed"
+I 334 0 2 Builtin Signal | 172074,247627 "" ""
+L 335 336 0 TEXT "Labels" | 175074,243343 1 0 0 "ACKRxed"
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+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59763,178747 47927,176730
+C 66 65 0 TEXT "Conditions" | 62843,168563 1 0 0 "processRxDataInWEn == 1'b1"
+W 68 6 0 16 357 BEZIER "Transitions" | 120926,119581 130781,111751 152663,94796 162518,86966
+W 69 6 0 24 357 BEZIER "Transitions" | 122281,93503 131596,91478 152599,87697 161914,85672
+W 71 6 0 33 357 BEZIER "Transitions" | 123360,67490 132540,71405 152828,79824 162008,83739
+W 72 6 0 42 357 BEZIER "Transitions" | 123133,41607 132448,51732 153635,72170 162950,82295
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+S 75 17 45056 ELLIPSE "States" | 65748,212778 6500 6500
+W 76 17 8194 75 18 BEZIER "Transitions" | 69849,207737 75657,200807 99461,167483 105269,160553
+A 78 65 16 TEXT "Actions" | 51039,182627 1 0 0 "RxByte <= RxByteIn;\nRxCtrl <= RxCtrlIn;\nprocessRxByteRdy <= 1'b0;"
+I 336 0 2 Builtin Signal | 172074,243343 "" ""
+L 337 338 0 TEXT "Labels" | 175074,238702 1 0 0 "dataSequence"
+I 338 0 2 Builtin Signal | 172074,238702 "" ""
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+I 342 0 2 Builtin Signal | 171929,216623 "" ""
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+L 345 346 0 TEXT "Labels" | 119382,216211 1 0 0 "RXByteStMachCurrState[2:0]"
+I 346 0 2 Builtin Signal | 116382,216211 "" ""
+A 349 9 4 TEXT "Actions" | 148079,209775 1 0 0 "RxByte <= 8'h00;\nRxCtrl <= 8'h00;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nRxTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxDataOut <= 8'h00;\nRxCtrlOut <= 8'h00;\nRxDataOutWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nRXDataByteCnt <= 10'h00;\nprocessRxByteRdy <= 1'b1;"
+W 351 6 0 357 63 BEZIER "Transitions" | 165899,88318 165621,91424 166582,101426 164321,105232\
+                                        162060,109038 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 135270,157360\
+                                        132480,162850 129690,168340 122852,170455 118982,171355
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+I 340 0 0 Builtin Signal | 172498,229252 "" ""
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+I 360 358 0 Builtin Exit | 129540,111760
+I 359 358 0 Builtin Entry | 86360,167640
+H 358 357 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 357 6 81940 ELLIPSE "Junction" | 165320,84870 3500 3500
+L 356 357 0 TEXT "State Labels" | 165320,84870 1 0 0 "J1"
+W 82 17 4097 75 21 BEZIER "Transitions" | 63199,206800 60009,197085 40708,156469 41288,147696\
+                                          41868,138924 51896,113272 59871,108777 67846,104282\
+                                          74724,97474 86324,92674
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+I 355 0 2 Builtin Signal | 77612,216204 "" ""
+L 366 367 0 TEXT "Labels" | 80453,221558 1 0 0 "Signal1"
+I 367 0 2 Builtin Signal | 77453,221558 "" ""
+A 383 351 16 TEXT "Actions" | 154286,108204 1 0 0 "processRxByteRdy <= 1'b1;"
+I 382 0 2 Builtin OutPort | 78990,227664 "" ""
+L 381 382 0 TEXT "Labels" | 84990,227664 1 0 0 "processRxByteRdy"
+L 368 369 0 TEXT "Labels" | 132404,226868 1 0 0 "CRC5UpdateRdy"
+I 369 0 2 Builtin InPort | 126404,226868 "" ""
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
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+I 375 0 2 Builtin InPort | 126404,222116 "" ""
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+A 162 40 4 TEXT "Actions" | 108520,254835 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC5Result != 5'h6)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    if (RXDataByteCnt > 10'h2) \n    begin\n      RxOverflow <= 1'b1;\n      RxDataOut <= RxStatus;\n      RxCtrlOut <= `RX_PACKET_STOP;\n      RXByteStMachCurrState <= `IDLE_BYTE_ST;\n    end\n    else \n    begin\n      RxDataOut <= RxByte;\n      RxCtrlOut <= `RX_PACKET_STREAM;\n      CRCData <= RxByte;\n      CRC5_8Bit <= 1'b1;\n      CRC5En <= 1'b1;\n    end\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,260362 "" ""
+L 186 187 0 TEXT "Labels" | 160691,260362 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 155048,265416 "" ""
+L 184 185 0 TEXT "Labels" | 161048,265416 1 0 0 "clk"
+L 212 213 0 TEXT "State Labels" | 113934,142150 1 0 0 "CHK_SYNC"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+I 220 217 0 Builtin Entry | 86360,167640
+I 221 217 0 Builtin Exit | 136710,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+I 227 224 0 Builtin Entry | 86360,167640
+I 228 224 0 Builtin Exit | 129540,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121598,118782 126644,111760
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 41970,135220 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+C 234 231 0 TEXT "Conditions" | 42504,153376 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,151931 129033,135644 151793,104087 163407,87800
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,135782 128966,124034 152340,99194 162953,87446
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n  RXByteStMachCurrState = `CHECK_PID_ST;\nelse\n  RXByteStMachCurrState = `IDLE_BYTE_ST;"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n  RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST"
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 0;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n  `SPECIAL:                              //Special PID.\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  `TOKEN:                                //Token PID\n  begin\n    RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\n  `HANDSHAKE:                            //Handshake PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        ACKRxed <= 1'b1;\n      2'b10:\n        NAKRxed <= 1'b1;\n      2'b11:\n        stallRxed <= 1'b1;\n      default:\n      begin\n        $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n      end\n    endcase\n    RXByteStMachCurrState <= `HS_BYTE_ST;\n  end\n  `DATA:                                  //Data PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        dataSequence <= 1'b0;\n      2'b10:\n        dataSequence <= 1'b1;\n      default:\n        $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n    endcase\n    RXByteStMachCurrState <= `DATA_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\nendcase"
+I 252 248 0 Builtin Entry | 35384,229000
+I 253 248 0 Builtin Exit | 78564,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+                                          110499,87996 110355,80840 110355,80474
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n  RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+I 260 32 0 Builtin Exit | 110355,78302
+I 259 32 0 Builtin Entry | 66351,233704
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+                                        89364,102368 89220,95212 89220,94846
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/readUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/readUSBWireData.v	(revision 264)
@@ -0,0 +1,198 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// readUSBWireData.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: readUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:01 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, disableWireRead, clk, rst);
+input   [1:0] RxBitsIn;
+output  RxDataInTick;
+input   SIERxRdyIn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+input   disableWireRead;
+output  [1:0] RxBitsOut;
+output  SIERxWEn;
+
+wire   [1:0] RxBitsIn;
+reg    RxDataInTick;
+wire   SIERxRdyIn;
+wire   clk;
+wire   fullSpeedRate;
+wire   rst;
+reg    [1:0] RxBitsOut;
+reg    SIERxWEn;
+
+// local registers
+reg  [1:0]buffer0;
+reg  [1:0]buffer1;
+reg  [1:0]buffer2;
+reg  [1:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg  [1:0]oldRxBitsIn;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+	end
+  else begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+ 		incBufferCnt <= 1'b0;
+		bufferInIndex <= 2'b00;
+		buffer0 <= 2'b00;
+		buffer1 <= 2'b00;
+		buffer2 <= 2'b00;
+		buffer3 <= 2'b00;
+    RxDataInTick <= 1'b0;
+	end
+  else begin
+	  incBufferCnt <= 1'b0;         //default value
+	  oldRxBitsIn <= RxBitsIn;
+	  if (oldRxBitsIn != RxBitsIn)  //if edge detected then
+		  i <= 5'b00000;              //reset the counter
+	  else
+		  i <= i + 1'b1;
+    if ( (fullSpeedRate == 1'b1 && i[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && i == 5'b10000) )
+	  begin
+      RxDataInTick <= !RxDataInTick;
+      if (disableWireRead != 1'b1)  //do not read wire data when transmitter is active
+      begin
+        incBufferCnt <= 1'b1;
+		    bufferInIndex <= bufferInIndex + 1'b1;
+		    case (bufferInIndex)
+			    2'b00 : buffer0 <= RxBitsIn;
+			    2'b01 : buffer1 <= RxBitsIn;
+			    2'b10 : buffer2 <= RxBitsIn;
+			    2'b11 : buffer3 <= RxBitsIn;
+		    endcase
+      end
+	  end
+  end
+end
+
+				
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+		decBufferCnt <= 1'b0;
+		bufferOutIndex <= 2'b00;
+		RxBitsOut <= 2'b00;
+		SIERxWEn <= 1'b0;
+		bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+	end
+  else begin
+	  case (bufferOutStMachCurrState)
+		  `WAIT_BUFFER_NOT_EMPTY:
+		  begin
+			  if (bufferCnt != 3'b000)
+				  bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+		  end
+		  `WAIT_SIE_RX_READY:
+		  begin
+			  if (SIERxRdyIn == 1'b1)
+			  begin 
+				  SIERxWEn <= 1'b1;
+				  bufferOutStMachCurrState <= `SIE_RX_WRITE;
+				  decBufferCnt <= 1'b1;
+				  bufferOutIndex <= bufferOutIndex + 1'b1;
+				  case (bufferOutIndex)
+  			    2'b00 :	RxBitsOut <= buffer0;
+					  2'b01 : RxBitsOut <= buffer1;
+					  2'b10 : RxBitsOut <= buffer2;
+					  2'b11 : RxBitsOut <= buffer3;
+				  endcase
+			  end
+		  end
+		  `SIE_RX_WRITE:
+		  begin
+			  SIERxWEn <= 1'b0;
+			  decBufferCnt <= 1'b0;
+			  bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+		  end
+	  endcase
+  end
+end
+
+			
+
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/updateCRC5.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/updateCRC5.v	(revision 264)
@@ -0,0 +1,117 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC5.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: updateCRC5.v,v 1.1.1.1 2004-10-11 04:01:04 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   CRC5_8BitIn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [4:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   CRC5_8BitIn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+	  i <= 4'h0;
+	  CRCResult <= 5'h1f;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0) begin
+      if (CRCEn == 1'b1) begin
+        ready <= 1'b0;
+	      doUpdateCRC <= 1'b1;
+	      data <= dataIn;
+	      if (CRC5_8BitIn == 1'b1) begin
+	        loopEnd <= 4'h7; 
+        end
+	      else begin
+		      loopEnd <= 4'h2;
+        end
+	    end
+    end
+    else begin
+	    i <= i + 1'b1;
+	    if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+		    CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+	    end
+      else begin
+        CRCResult <= {1'b0, CRCResult[4:1]};
+      end
+	    data <= {1'b0, data[7:1]};
+	    if (i == loopEnd) begin
+	      doUpdateCRC <= 1'b0; 
+		    i <= 4'h0;
+        ready <= 1'b1;
+	    end
+    end
+  end
+end
+		
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/writeUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/writeUSBWireData.v	(revision 264)
@@ -0,0 +1,308 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// writeUSBWireData.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: writeUSBWireData.v,v 1.1.1.1 2004-10-11 04:01:05 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL  3'b100
+
+module writeUSBWireData (
+  TxBitsIn, 
+  TxBitsOut,
+ 	TxDataOutTick,
+  TxCtrlIn, 
+  TxCtrlOut, 
+  USBWireRdy,
+  USBWireWEn, 
+  disableWireReadOut, 
+  fullSpeedRate, 
+  clk, 
+  rst,
+  noActivityTimeOut );
+  
+input   [1:0] TxBitsIn;
+input   TxCtrlIn;
+input   USBWireWEn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+output  [1:0] TxBitsOut;
+output TxDataOutTick;
+output  TxCtrlOut;
+output  USBWireRdy;
+output  disableWireReadOut;
+output noActivityTimeOut;
+
+wire    [1:0] TxBitsIn;
+reg     [1:0] TxBitsOut;
+reg     TxDataOutTick;
+wire    TxCtrlIn;
+reg     TxCtrlOut;
+reg     USBWireRdy;
+wire    USBWireWEn;
+wire    clk;
+wire    fullSpeedRate;
+wire    rst;
+reg  disableWireReadOut;
+reg noActivityTimeOut;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+reg [15:0] timeOutCnt;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+	end
+  else
+  begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+//buffer input state machine 
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+ 		incBufferCnt <= 1'b0;
+		bufferInIndex <= 2'b00;
+		buffer0 <= 3'b000;
+		buffer1 <= 3'b000;
+		buffer2 <= 3'b000;
+		buffer3 <= 3'b000;
+		USBWireRdy <= 1'b0;
+		bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+	end
+  else begin
+	  case (bufferInStMachCurrState)
+	  	`WAIT_BUFFER_NOT_FULL:
+	  	begin
+			  if (bufferCnt != `BUFFER_FULL)	
+			  begin
+				  bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+				  USBWireRdy <= 1'b1;
+			  end
+		  end
+		  `WAIT_WRITE_REQ:
+		  begin
+			  if (USBWireWEn == 1'b1)
+			  begin
+				  incBufferCnt <= 1'b1;
+				  USBWireRdy <= 1'b0;
+				  bufferInIndex <= bufferInIndex + 1'b1;
+				  case (bufferInIndex)
+					  2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+					  2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+					  2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+					  2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+				  endcase
+				  bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+			  end
+		  end
+		  `CLR_INC_BUFFER_CNT:
+		  begin
+			  incBufferCnt <= 1'b0;
+			  if (bufferCnt != (`BUFFER_FULL - 1'b1) )	
+			  begin
+				  bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+				  USBWireRdy <= 1'b1;
+			  end
+        else begin
+		      bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+        end
+		  end
+	  endcase
+  end
+end
+				
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    fullSpeedTick <= 1'b0;
+    lowSpeedTick <= 1'b0;
+  end
+  else
+  begin
+    i <= i + 1'b1;
+    if (i[1:0] == 2'b00)
+      fullSpeedTick <= 1'b1;
+    else
+      fullSpeedTick <= 1'b0; 
+    if (i == 5'b00000)
+      lowSpeedTick <= 1'b1;
+    else
+      lowSpeedTick <= 1'b0;
+  end
+end
+
+//buffer output state machine
+//After reset, waits for the output buffer to become full.
+//Once the buffer is full then it is constantly emptied at either
+//the full or low speed rate with no under run protection
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+		bufferOutIndex <= 2'b00;
+		decBufferCnt <= 1'b0;
+		TxBitsOut <= 2'b00;
+		TxCtrlOut <= `TRI_STATE;
+    TxDataOutTick <= 1'b0;
+		bufferOutStMachCurrState <= `WAIT_BUFFER_FULL;
+	end
+  else
+  begin
+	  case (bufferOutStMachCurrState)
+		  `WAIT_BUFFER_FULL:
+		  begin
+			  if (bufferCnt == `BUFFER_FULL)
+				  bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+		  end
+		  `WAIT_LINE_WRITE:
+		  begin
+			  if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+			  begin
+          TxDataOutTick <= !TxDataOutTick;
+				  bufferOutStMachCurrState <= `LINE_WRITE;
+				  decBufferCnt <= 1'b1;
+				  bufferOutIndex <= bufferOutIndex + 1'b1;
+				  case (bufferOutIndex)
+  				  2'b00 :
+				  begin 
+					  TxBitsOut <= buffer0[2:1];
+					  TxCtrlOut <= buffer0[0];
+				  end
+				  2'b01 : 
+				  begin
+					  TxBitsOut <= buffer1[2:1];
+					  TxCtrlOut <= buffer1[0];
+				  end
+				  2'b10 : 
+				  begin 
+					  TxBitsOut <= buffer2[2:1];
+					  TxCtrlOut <= buffer2[0];
+				  end
+				  2'b11 : 
+				  begin
+					  TxBitsOut <= buffer3[2:1];
+					  TxCtrlOut <= buffer3[0];
+				  end
+				  endcase
+			  end
+		  end
+		  `LINE_WRITE:
+		  begin
+			  decBufferCnt <= 1'b0;
+			  bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+		  end
+	  endcase
+  end
+end
+
+// control 'disableWireReadOut' 
+always @(TxCtrlOut)
+begin	
+	if (TxCtrlOut == `DRIVE)
+		disableWireReadOut <= 1'b1;
+	else
+		disableWireReadOut <= 1'b0;
+end
+
+//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks
+always @(posedge clk) begin
+  if (rst) begin
+    timeOutCnt <= 16'h0000;
+    noActivityTimeOut <= 1'b0;
+  end
+  else begin
+    if (TxCtrlOut == `DRIVE)
+      timeOutCnt <= 16'h0000;
+    else 
+      timeOutCnt <= timeOutCnt + 1'b1;
+    //if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)
+    if (timeOutCnt == 16'h200)  //temporary fix
+      noActivityTimeOut <= 1'b1;
+    else
+      noActivityTimeOut <= 1'b0;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/sctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/sctxportarbiter.asf	(revision 264)
@@ -0,0 +1,110 @@
+VERSION=1.19
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FREEOID=101
+"LIBRARIES=`timescale 1ns / 1ps\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/20/2004"
+HEADER_PARAM="TITLE,SCTxPortArbiter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
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+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 431800,558800
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SARB_SEND_PACKET\n/1/"
+S 14 6 4096 ELLIPSE "States" | 269063,296392 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 10 6 0 ELLIPSE "States" | 224972,365039 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_SARB\n/3/"
+S 8 6 12288 ELLIPSE "States" | 225591,395370 6500 6500
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "SCTxArb"
+F 6 0 671089152 41 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,543100 1 0 0 "Module: SCTxPortArbiter"
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+C 26 17 0 TEXT "Conditions" | 202073,391408 1 0 0 "rst"
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+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
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+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxDCEn <= 1'b1;"
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+W 92 6 4098 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+S 91 6 8192 ELLIPSE "States" | 230314,289948 6500 6500
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "SARB_DC\n/2/"
+I 89 0 2 Builtin Signal | 141050,528812 "" ""
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxDCEn"
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286142,395412 275462,395110\
+                                      264783,394808 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/hostcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/hostcontroller.asf	(revision 264)
@@ -0,0 +1,280 @@
+VERSION=1.19
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FREEOID=432
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,hostController"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 45
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 47
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 49
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 51
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+F 6 0 671089152 282 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;"
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+A 302 83 16 TEXT "Actions" | 136700,161820 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+                                        170250,145750 137550,145450 128737,144962 119925,144475\
+                                        117963,142662 116688,141837
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+A 334 332 16 TEXT "Actions" | 87236,105298 1 0 0 "getPacketREn <= 1'b1;"
+C 333 332 0 TEXT "Conditions" | 48120,123470 1 0 0 "sendPacketRdy == 1'b1"
+W 332 66 0 220 331 BEZIER "Transitions" | 82714,126587 85717,114267 91541,91328 94544,79008
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+I 55 52 0 Builtin Entry | 88756,239499
+I 56 52 0 Builtin Exit | 155694,46048
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+C 321 320 0 TEXT "Conditions" | 124852,185328 1 0 0 "sendPacketRdy == 1'b1"
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+                                          110726,37400 115182,37514 117348,37514
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+I 366 73 0 Builtin Entry | 66816,246531
+I 365 73 0 Builtin Exit | 138662,35952
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+                                          129080,35838 133536,35952 135702,35952
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 95 6 0 294 41 BEZIER "Transitions" | 117484,22592 114800,20099 105581,15162 96803,16522\
+                                       88026,17883 53248,36150 43780,48625 34312,61101\
+                                       33772,117285 37441,132224 41110,147164 52980,154980\
+                                       61012,157537 69044,160095 94076,164012 106263,166770
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+A 368 362 4 TEXT "Actions" | 121320,126002 1 0 0 "sendPacketWEn <= 1'b0;"
+I 96 6 0 Builtin Reset | 67359,192312
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+W 371 59 2 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+                                          40160,89849 37728,77233 37462,69633 37196,62033\
+                                          38564,44249 44378,36953 50192,29657 72080,18257\
+                                          79528,15331 86976,12405 94012,13028 97964,12876
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+I 411 59 0 Builtin Exit | 100924,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+                                          134254,207065 123583,209376 117848,210301
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+W 167 59 1 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+I 216 66 0 Builtin Exit | 120308,37514
+I 215 66 0 Builtin Entry | 50996,240683
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+A 231 220 4 TEXT "Actions" | 102966,127564 1 0 0 "sendPacketWEn <= 1'b0;"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/sendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/sendpacket.v	(revision 264)
@@ -0,0 +1,297 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacket.v
+// Generated   : 09/25/04 06:36:27
+// From        : c:\projects\USBHostSlave\RTL\hostController\sendpacket.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, rst, sendPacketRdy, sendPacketWEn);
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   [3:0] PID;
+input   [6:0] TxAddr;
+input   clk;
+input   [7:0] fifoData;
+input   fifoEmpty;
+input   rst;
+input   sendPacketWEn;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [3:0] TxEndP;
+output  fifoReadEn;
+output  [10:0] frameNum;
+output  sendPacketRdy;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    [3:0] PID;
+wire    [6:0] TxAddr;
+reg     [3:0] TxEndP, next_TxEndP;
+wire    clk;
+wire    [7:0] fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+reg     [10:0] frameNum, next_frameNum;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+
+reg [4:0] CurrState_sndPkt;
+reg [4:0] NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+    PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+//--------------------------------------------------------------------
+// Machine: sndPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or HCTxPortRdy or PID or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt)
+begin : sndPkt_NextState
+	NextState_sndPkt <= CurrState_sndPkt;
+	// Set default values for outputs and signals
+	next_sendPacketRdy <= sendPacketRdy;
+	next_HCTxPortReq <= HCTxPortReq;
+	next_HCTxPortWEn <= HCTxPortWEn;
+	next_HCTxPortData <= HCTxPortData;
+	next_HCTxPortCntl <= HCTxPortCntl;
+	next_frameNum <= frameNum;
+	next_fifoReadEn <= fifoReadEn;
+	case (CurrState_sndPkt) // synopsys parallel_case full_case
+		`START_SP:
+			NextState_sndPkt <= `WAIT_ENABLE;
+		`WAIT_ENABLE:
+			if (sendPacketWEn == 1'b1)	
+			begin
+				NextState_sndPkt <= `SP_WAIT_GNT;
+				next_sendPacketRdy <= 1'b0;
+				next_HCTxPortReq <= 1'b1;
+			end
+		`SP_WAIT_GNT:
+			if (HCTxPortGnt == 1'b1)	
+				NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+		`FIN_SP:
+		begin
+			NextState_sndPkt <= `WAIT_ENABLE;
+			next_sendPacketRdy <= 1'b1;
+			next_HCTxPortReq <= 1'b0;
+		end
+		`SEND_PID_WAIT_RDY:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `SEND_PID_FIN;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= PIDNotPID;
+				next_HCTxPortCntl <= `TX_PACKET_START;
+			end
+		`SEND_PID_FIN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			if (PID == `DATA0 || PID == `DATA1)	
+				NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+			else if (PID == `SOF)	
+				NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+			else if (PID == `OUT || 
+				PID == `IN || 
+				PID == `SETUP)	
+				NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+			else
+				NextState_sndPkt <= `FIN_SP;
+		end
+		`OUT_IN_SETUP_WAIT_RDY1:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+				next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			end
+		`OUT_IN_SETUP_WAIT_RDY2:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+				next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			end
+		`OUT_IN_SETUP_FIN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `FIN_SP;
+		end
+		`OUT_IN_SETUP_CLR_WEN1:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+		end
+		`SEND_SOF_FIN1:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			next_frameNum <= frameNum + 1'b1;
+			NextState_sndPkt <= `FIN_SP;
+		end
+		`SEND_SOF_WAIT_RDY3:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= frameNum[7:0];
+				next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			end
+		`SEND_SOF_WAIT_RDY4:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `SEND_SOF_FIN1;
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+				next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			end
+		`SEND_SOF_CLR_WEN1:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+		end
+		`DATA0_DATA1_READ_FIFO:
+		begin
+			next_HCTxPortWEn <= 1'b1;
+			next_HCTxPortData <= fifoData;
+			next_HCTxPortCntl <= `TX_PACKET_STREAM;
+			NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+		end
+		`DATA0_DATA1_WAIT_READ_FIFO:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+				next_fifoReadEn <= 1'b1;
+			end
+		`DATA0_DATA1_FIFO_EMPTY:
+			if (fifoEmpty == 1'b0)	
+				NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+			else
+				NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+		`DATA0_DATA1_FIN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `FIN_SP;
+		end
+		`DATA0_DATA1_TERM_BYTE:
+			if (HCTxPortRdy == 1'b1)	
+			begin
+				NextState_sndPkt <= `DATA0_DATA1_FIN;
+				//Last byte is not valid data,
+				//but the 'TX_PACKET_STOP' flag is required
+				//by the SIE state machine to detect end of data packet
+				next_HCTxPortWEn <= 1'b1;
+				next_HCTxPortData <= 8'h00;
+				next_HCTxPortCntl <= `TX_PACKET_STOP;
+			end
+		`DATA0_DATA1_CLR_WEN:
+		begin
+			next_HCTxPortWEn <= 1'b0;
+			NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+		end
+		`DATA0_DATA1_CLR_REN:
+		begin
+			next_fifoReadEn <= 1'b0;
+			NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sndPkt_CurrentState
+	if (rst)	
+		CurrState_sndPkt <= `START_SP;
+	else
+		CurrState_sndPkt <= NextState_sndPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sndPkt_RegOutput
+	if (rst)	
+	begin
+		sendPacketRdy <= 1'b1;
+		HCTxPortReq <= 1'b0;
+		HCTxPortWEn <= 1'b0;
+		HCTxPortData <= 8'h00;
+		HCTxPortCntl <= 8'h00;
+		frameNum <= 11'h000;
+		fifoReadEn <= 1'b0;
+	end
+	else 
+	begin
+		sendPacketRdy <= next_sendPacketRdy;
+		HCTxPortReq <= next_HCTxPortReq;
+		HCTxPortWEn <= next_HCTxPortWEn;
+		HCTxPortData <= next_HCTxPortData;
+		HCTxPortCntl <= next_HCTxPortCntl;
+		frameNum <= next_frameNum;
+		fifoReadEn <= next_fifoReadEn;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/sendpacketcheckpreamble.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/sendpacketcheckpreamble.v	(revision 264)
@@ -0,0 +1,192 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sendpacketcheckpreamble.v
+// Generated   : 09/10/04 20:20:24
+// From        : c:\projects\USBHostSlave\RTL\hostController\sendpacketcheckpreamble.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, fullSpeedBitRate, fullSpeedPolarity, grabLineControl, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   preAmbleEnable;
+input   rst;
+input   [3:0] sendPacketCPPID;
+input   sendPacketCPWEn;
+input   sendPacketRdy;
+output  fullSpeedBitRate;
+output  fullSpeedPolarity;
+output  grabLineControl;		// mux select
+output  sendPacketCPReady;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+
+wire    clk;
+reg     fullSpeedBitRate, next_fullSpeedBitRate;
+reg     fullSpeedPolarity, next_fullSpeedPolarity;
+reg     grabLineControl, next_grabLineControl;
+wire    preAmbleEnable;
+wire    rst;
+wire    [3:0] sendPacketCPPID;
+reg     sendPacketCPReady, next_sendPacketCPReady;
+wire    sendPacketCPWEn;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_WAIT_RDY2 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_WAIT_RDY3 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+
+reg [3:0] CurrState_sendPktCP;
+reg [3:0] NextState_sendPktCP;
+
+
+//--------------------------------------------------------------------
+// Machine: sendPktCP
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or fullSpeedBitRate or fullSpeedPolarity or grabLineControl or CurrState_sendPktCP)
+begin : sendPktCP_NextState
+	NextState_sendPktCP <= CurrState_sendPktCP;
+	// Set default values for outputs and signals
+	next_sendPacketCPReady <= sendPacketCPReady;
+	next_sendPacketWEn <= sendPacketWEn;
+	next_sendPacketPID <= sendPacketPID;
+	next_fullSpeedBitRate <= fullSpeedBitRate;
+	next_fullSpeedPolarity <= fullSpeedPolarity;
+	next_grabLineControl <= grabLineControl;
+	case (CurrState_sendPktCP) // synopsys parallel_case full_case
+		`SPC_WAIT_EN:
+			if (sendPacketCPWEn == 1'b1)	
+			begin
+				NextState_sendPktCP <= `CHK_PREAM;
+				next_sendPacketCPReady <= 1'b0;
+			end
+		`START_SPC:
+			NextState_sendPktCP <= `SPC_WAIT_EN;
+		`CHK_PREAM:
+			if (preAmbleEnable == 1'b1)	
+				NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+			else
+				NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+		`READY:
+		begin
+			next_sendPacketCPReady <= 1'b1;
+			NextState_sendPktCP <= `SPC_WAIT_EN;
+		end
+		`PREAM_PKT_SND_PREAM:
+		begin
+			next_sendPacketWEn <= 1'b1;
+			next_sendPacketPID <= `PREAMBLE;
+			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+			next_sendPacketWEn <= 1'b0;
+		end
+		`PREAM_PKT_WAIT_RDY1:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+				next_fullSpeedBitRate <= 1'b1;
+				next_fullSpeedPolarity <= 1'b1;
+				next_grabLineControl <= 1'b1;
+			end
+		`PREAM_PKT_WAIT_RDY2:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+				next_fullSpeedBitRate <= 1'b1;
+			end
+		`PREAM_PKT_SND_PID:
+		begin
+			next_sendPacketWEn <= 1'b1;
+			next_sendPacketPID <= sendPacketCPPID;
+			NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+			next_sendPacketWEn <= 1'b0;
+		end
+		`PREAM_PKT_WAIT_RDY3:
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_sendPktCP <= `READY;
+				next_grabLineControl <= 1'b0;
+			end
+		`REG_PKT_SEND_PID:
+		begin
+			next_sendPacketWEn <= 1'b1;
+			next_sendPacketPID <= sendPacketCPPID;
+			NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+		end
+		`REG_PKT_WAIT_RDY1:
+			if (sendPacketRdy == 1'b1)	
+				NextState_sendPktCP <= `REG_PKT_SEND_PID;
+		`REG_PKT_WAIT_RDY:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			NextState_sendPktCP <= `READY;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktCP_CurrentState
+	if (rst)	
+		CurrState_sendPktCP <= `START_SPC;
+	else
+		CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktCP_RegOutput
+	if (rst)	
+	begin
+		sendPacketWEn <= 1'b0;
+		sendPacketPID <= 4'b0;
+		fullSpeedBitRate <= 1'b0;
+		fullSpeedPolarity <= 1'b0;
+		grabLineControl <= 1'b0;
+		sendPacketCPReady <= 1'b1;
+	end
+	else 
+	begin
+		sendPacketWEn <= next_sendPacketWEn;
+		sendPacketPID <= next_sendPacketPID;
+		fullSpeedBitRate <= next_fullSpeedBitRate;
+		fullSpeedPolarity <= next_fullSpeedPolarity;
+		grabLineControl <= next_grabLineControl;
+		sendPacketCPReady <= next_sendPacketCPReady;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostController/softransmit.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostController/softransmit.v	(revision 264)
@@ -0,0 +1,146 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\softransmit.v
+// Generated   : 09/14/04 21:51:27
+// From        : c:\projects\USBHostSlave\RTL\hostController\softransmit.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn);
+input   SOFEnable;		// After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input   SOFSyncEn;
+input   [15:0] SOFTimer;
+input   clk;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+output  SOFSent;		// single cycle pulse
+output  SOFTimerClr;		// Single cycle pulse
+output  sendPacketArbiterReq;
+output  sendPacketWEn;
+
+wire    SOFEnable;
+reg     SOFSent, next_SOFSent;
+wire    SOFSyncEn;
+reg     SOFTimerClr, next_SOFTimerClr;
+wire    [15:0] SOFTimer;
+wire    clk;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+
+reg [2:0] CurrState_SOFTx;
+reg [2:0] NextState_SOFTx;
+
+
+//--------------------------------------------------------------------
+// Machine: SOFTx
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
+begin : SOFTx_NextState
+	NextState_SOFTx <= CurrState_SOFTx;
+	// Set default values for outputs and signals
+	next_sendPacketArbiterReq <= sendPacketArbiterReq;
+	next_sendPacketWEn <= sendPacketWEn;
+	next_SOFTimerClr <= SOFTimerClr;
+	next_SOFSent <= SOFSent;
+	case (CurrState_SOFTx) // synopsys parallel_case full_case
+		`START_STX:
+			NextState_SOFTx <= `WAIT_SOF_NEAR;
+		`WAIT_SOF_NEAR:
+			if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
+				(SOFSyncEn == 1'b1 &&
+				SOFEnable == 1'b1))	
+			begin
+				NextState_SOFTx <= `WAIT_SP_GNT;
+				next_sendPacketArbiterReq <= 1'b1;
+			end
+		`WAIT_SP_GNT:
+			if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)	
+				NextState_SOFTx <= `WAIT_SOF_NOW;
+		`WAIT_SOF_NOW:
+			if (SOFTimer >= `SOF_TX_TIME)	
+			begin
+				NextState_SOFTx <= `SOF_FIN;
+				next_sendPacketWEn <= 1'b1;
+				next_SOFTimerClr <= 1'b1;
+				next_SOFSent <= 1'b1;
+			end
+			else if (SOFEnable == 1'b0)	
+			begin
+				NextState_SOFTx <= `SOF_FIN;
+				next_SOFTimerClr <= 1'b1;
+			end
+		`SOF_FIN:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			next_SOFTimerClr <= 1'b0;
+			next_SOFSent <= 1'b0;
+			NextState_SOFTx <= `WAIT_SOF_NEAR;
+			next_sendPacketArbiterReq <= 1'b0;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SOFTx_CurrentState
+	if (rst)	
+		CurrState_SOFTx <= `START_STX;
+	else
+		CurrState_SOFTx <= NextState_SOFTx;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SOFTx_RegOutput
+	if (rst)	
+	begin
+		SOFSent <= 1'b0;
+		SOFTimerClr <= 1'b0;
+		sendPacketArbiterReq <= 1'b0;
+		sendPacketWEn <= 1'b0;
+	end
+	else 
+	begin
+		SOFSent <= next_SOFSent;
+		SOFTimerClr <= next_SOFTimerClr;
+		sendPacketArbiterReq <= next_sendPacketArbiterReq;
+		sendPacketWEn <= next_sendPacketWEn;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/hostSlaveMux/hostSlaveMuxBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/hostSlaveMux/hostSlaveMuxBI.v	(revision 264)
@@ -0,0 +1,92 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMuxBI.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: hostSlaveMuxBI.v,v 1.1.1.1 2004-10-11 04:00:56 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+ module hostSlaveMuxBI (dataIn, dataOut, writeEn, strobe_i, clk, rst,
+	hostMode, hostSlaveMuxSel);
+
+input [7:0] dataIn;
+input writeEn;
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+
+//internal wire and regs
+
+//sync write demux
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+    hostMode <= 1'b0;
+  else begin
+	  if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1)
+			hostMode <= dataIn[0];
+  end
+end
+
+
+// async read mux
+always @(hostMode)
+begin
+	dataOut <= {7'h0, hostMode};
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/include/usbConstants_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/include/usbConstants_h.v	(revision 264)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbConstants_h.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  USB global constants as defined by USB spec 1.1
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbConstants_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc 
+	   
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+       
+

Property changes on: common/components/usbhostslave/tags/start/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/include/wishBoneBus_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/include/wishBoneBus_h.v	(revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBus_h.v                                              ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: wishBoneBus_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+ 
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+
+

Property changes on: common/components/usbhostslave/tags/start/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/slaveGetpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/slaveGetpacket.asf	(revision 264)
@@ -0,0 +1,268 @@
+VERSION=1.19
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FREEOID=280
+"LIBRARIES=`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/22/2004"
+HEADER_PARAM="TITLE,slaveGetPacket"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
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+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
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+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
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+END
+OBJECTS
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+I 49 46 0 Builtin Entry | 47660,248640
+I 50 46 0 Builtin Exit | 180308,72140
+L 79 80 0 TEXT "State Labels" | 73724,251728 1 0 0 "W_D1\n/2/"
+I 76 72 0 Builtin Exit | 187140,27160
+I 75 72 0 Builtin Entry | 33260,254940
+H 72 58 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 71 69 16 TEXT "Actions" | 64339,118484 1 0 0 "RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];\nACKRxed <= RXDataIn[`ACK_RXED_BIT];"
+C 70 69 0 TEXT "Conditions" | 56338,138027 1 0 0 "RXDataValid == 1'b1"
+W 69 46 0 56 251 BEZIER "Transitions" | 54000,144905 54225,137689 107734,98899 116203,93057
+C 95 93 0 TEXT "Conditions" | 80158,211576 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 94 92 0 TEXT "Conditions" | 75213,244607 1 0 0 "RXDataValid == 1'b1"
+W 93 72 8193 89 91 BEZIER "Transitions" | 76671,212483 76896,208199 77562,200846 77787,196562
+W 92 72 0 80 89 BEZIER "Transitions" | 74019,245253 74357,241194 75110,229474 75448,225415
+S 91 72 20480 ELLIPSE "States" | 78474,190102 6500 6500
+L 90 91 0 TEXT "State Labels" | 78474,190102 1 0 0 "W_D2\n/4/"
+S 89 72 16384 ELLIPSE "States" | 76219,218966 6500 6500
+L 88 89 0 TEXT "State Labels" | 76219,218966 1 0 0 "CHK_D1\n/3/"
+W 87 72 0 75 80 BEZIER "Transitions" | 37722,254940 43021,249077 61954,258197 67253,252334
+S 80 72 12288 ELLIPSE "States" | 73724,251728 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177624,25344 184036,27160
+I 169 6 0 Builtin Reset | 40672,207751
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176807,72082 177204,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 2 Builtin InPort | 114408,221254 "" ""
+I 191 0 2 Builtin InPort | 114421,225994 "" ""
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+I 197 0 2 Builtin Signal | 19204,221408 "" ""
+I 216 0 2 Builtin Signal | 19488,226184 "" ""
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;"
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+I 222 0 2 Builtin Signal | 52956,259852 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+I 238 0 2 Builtin OutPort | 77500,221804 "" ""
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 2 Builtin Signal | 52956,265100 "" ""
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 232 0 2 Builtin OutPort | 77780,242452 "" ""
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/slaveSendpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/slaveSendpacket.v	(revision 264)
@@ -0,0 +1,222 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveSendpacket.v
+// Generated   : 09/25/04 06:34:38
+// From        : c:\projects\USBHostSlave\RTL\slaveController\slaveSendpacket.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn);
+input   [3:0] PID;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   clk;
+input   [7:0] fifoData;
+input   fifoEmpty;
+input   rst;
+input   sendPacketWEn;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+output  fifoReadEn;
+output  sendPacketRdy;
+
+wire    [3:0] PID;
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+wire    clk;
+wire    [7:0] fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0] CurrState_slvSndPkt;
+reg [3:0] NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @(PID)
+begin
+    PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+
+//--------------------------------------------------------------------
+// Machine: slvSndPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt)
+begin : slvSndPkt_NextState
+	NextState_slvSndPkt <= CurrState_slvSndPkt;
+	// Set default values for outputs and signals
+	next_sendPacketRdy <= sendPacketRdy;
+	next_SCTxPortReq <= SCTxPortReq;
+	next_SCTxPortWEn <= SCTxPortWEn;
+	next_SCTxPortData <= SCTxPortData;
+	next_SCTxPortCntl <= SCTxPortCntl;
+	next_fifoReadEn <= fifoReadEn;
+	case (CurrState_slvSndPkt) // synopsys parallel_case full_case
+		`START_SP1:
+			NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+		`SP_WAIT_ENABLE:
+			if (sendPacketWEn == 1'b1)	
+			begin
+				NextState_slvSndPkt <= `SP1_WAIT_GNT;
+				next_sendPacketRdy <= 1'b0;
+				next_SCTxPortReq <= 1'b1;
+			end
+		`SP1_WAIT_GNT:
+			if (SCTxPortGnt == 1'b1)	
+				NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+		`FIN_SP1:
+		begin
+			NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+			next_sendPacketRdy <= 1'b1;
+			next_SCTxPortReq <= 1'b0;
+		end
+		`SP_NOT_DATA:
+			NextState_slvSndPkt <= `FIN_SP1;
+		`SP_SEND_PID_WAIT_RDY:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+				next_SCTxPortWEn <= 1'b1;
+				next_SCTxPortData <= PIDNotPID;
+				next_SCTxPortCntl <= `TX_PACKET_START;
+			end
+		`SP_SEND_PID_FIN:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			if (PID == `DATA0 || PID == `DATA1)	
+				NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+			else
+				NextState_slvSndPkt <= `SP_NOT_DATA;
+		end
+		`SP_D0_D1_READ_FIFO:
+		begin
+			next_SCTxPortWEn <= 1'b1;
+			next_SCTxPortData <= fifoData;
+			next_SCTxPortCntl <= `TX_PACKET_STREAM;
+			NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+		end
+		`SP_D0_D1_WAIT_READ_FIFO:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+				next_fifoReadEn <= 1'b1;
+			end
+		`SP_D0_D1_FIFO_EMPTY:
+			if (fifoEmpty == 1'b0)	
+				NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+			else
+				NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+		`SP_D0_D1_FIN:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			NextState_slvSndPkt <= `FIN_SP1;
+		end
+		`SP_D0_D1_TERM_BYTE:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvSndPkt <= `SP_D0_D1_FIN;
+				//Last byte is not valid data,
+				//but the 'TX_PACKET_STOP' flag is required
+				//by the SIE state machine to detect end of data packet
+				next_SCTxPortWEn <= 1'b1;
+				next_SCTxPortData <= 8'h00;
+				next_SCTxPortCntl <= `TX_PACKET_STOP;
+			end
+		`SP_D0_D1_CLR_WEN:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+		end
+		`SP_D0_D1_CLR_REN:
+		begin
+			next_fifoReadEn <= 1'b0;
+			NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvSndPkt_CurrentState
+	if (rst)	
+		CurrState_slvSndPkt <= `START_SP1;
+	else
+		CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvSndPkt_RegOutput
+	if (rst)	
+	begin
+		sendPacketRdy <= 1'b1;
+		SCTxPortReq <= 1'b0;
+		SCTxPortWEn <= 1'b0;
+		SCTxPortData <= 8'h00;
+		SCTxPortCntl <= 8'h00;
+		fifoReadEn <= 1'b0;
+	end
+	else 
+	begin
+		sendPacketRdy <= next_sendPacketRdy;
+		SCTxPortReq <= next_SCTxPortReq;
+		SCTxPortWEn <= next_SCTxPortWEn;
+		SCTxPortData <= next_SCTxPortData;
+		SCTxPortCntl <= next_SCTxPortCntl;
+		fifoReadEn <= next_fifoReadEn;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/wrapper/usbHostSlave.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/wrapper/usbHostSlave.v	(revision 264)
@@ -0,0 +1,515 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlave.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbHostSlave.v,v 1.1.1.1 2004-10-11 04:01:11 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module usbHostSlave(
+	clk, 
+  rst,
+  address_i, 
+  data_i, 
+  data_o, 
+  writeEn, 
+  strobe_i,
+  ack_o,
+  hostSOFSentIntOut, 
+  hostConnEventIntOut, 
+  hostResumeIntOut, 
+  hostTransDoneIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+	USBWireDataIn,
+	USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+	USBWireCtrlOut
+	 );
+	parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+  parameter HOST_FIFO_ADDR_WIDTH = 6;   
+	parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+	parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+	parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+	parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk;
+input rst;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input writeEn; 
+input strobe_i;
+output ack_o;
+output hostSOFSentIntOut; 
+output hostConnEventIntOut; 
+output hostResumeIntOut; 
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+
+wire clk;
+wire rst;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire writeEn; 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel; 
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE; 
+wire [7:0] hostTxFifoData; 
+wire hostTxFifoEmpty;
+wire hostRxFifoWE; 
+wire [7:0] hostRxFifoData; 
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost; 
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+
+usbHostControl u_usbHostControl(
+  .clk(clk), 
+  .rst(rst),
+	.TxFifoRE(hostTxFifoRE), 
+  .TxFifoData(hostTxFifoData), 
+  .TxFifoEmpty(hostTxFifoEmpty),
+	.RxFifoWE(hostRxFifoWE), 
+  .RxFifoData(hostRxFifoData), 
+  .RxFifoFull(hostRxFifoFull),
+	.RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+	.SIERxTimeOut(noActivityTimeOut),
+	.fullSpeedRate(fullSpeedBitRateFromHost), 
+  .fullSpeedPol(fullSpeedPolarityFromHost),
+	.HCTxPortEn(SIEPortWEnFromHost), 
+  .HCTxPortRdy(SIEPortTxRdy),
+	.HCTxPortData(SIEPortDataInFromHost), 
+  .HCTxPortCtrl(SIEPortCtrlInFromHost),
+	.connectStateIn(connectState), 
+	.resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[3:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+	.SOFSentIntOut(hostSOFSentIntOut), 
+  .connEventIntOut(hostConnEventIntOut), 
+  .resumeIntOut(hostResumeIntOut), 
+  .transDoneIntOut(hostTransDoneIntOut),
+  .hostControlSelect(hostControlSel) );
+  
+
+usbSlaveControl u_usbSlaveControl(
+  .clk(clk), 
+  .rst(rst),
+	.RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+	.SIERxTimeOut(noActivityTimeOut), 
+  .RxFifoData(slaveRxFifoData),
+	.fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+	.SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+	.SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+	.connectStateIn(connectState), 
+	.resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(writeEn),
+  .busStrobe_i(strobe_i),
+	.SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk), 
+  .rst(rst),
+	.hostControlSel(hostControlSel), 
+  .hostRxFifoSel(hostRxFifoSel), 
+  .hostTxFifoSel(hostTxFifoSel),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(dataFromHostControl),
+  .dataFromHostRxFifo(dataFromHostRxFifo),
+  .dataFromHostTxFifo(dataFromHostTxFifo),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+	 );
+
+hostSlaveMux u_hostSlaveMux(
+	.SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+	.SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+	.SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+	.SIEPortDataInToSIE(SIEPortDataInToSIE), 
+	.SIEPortDataInFromHost(SIEPortDataInFromHost), 
+	.SIEPortDataInFromSlave(SIEPortDataInFromSlave), 
+	.SIEPortWEnToSIE(SIEPortWEnToSIE), 
+	.SIEPortWEnFromHost(SIEPortWEnFromHost), 
+	.SIEPortWEnFromSlave(SIEPortWEnFromSlave), 
+	.fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+	.fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+	.fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+	.fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+	.fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+	.fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux), 
+  .writeEn(writeEn),
+  .strobe_i(strobe_i),
+  .clk(clk), 
+  .rst(rst),
+  .hostSlaveMuxSel(hostSlaveMuxSel)  );
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(clk), 
+  .rst(rst),
+	.USBWireDataIn(USBWireDataIn),
+	.USBWireDataOut(USBWireDataOut),
+	.USBWireDataInTick(USBWireDataInTick),
+	.USBWireDataOutTick(USBWireDataOutTick),
+	.USBWireCtrlOut(USBWireCtrlOut),
+	.connectState(connectState),
+	.resumeDetected(resumeDetected),
+	.RxCtrlOut(RxCtrlOut), 
+	.RxDataOutWEn(RxDataOutWEn), 
+	.RxDataOut(RxDataFromSIE), 
+	.SIEPortCtrlIn(SIEPortCtrlInToSIE),
+	.SIEPortDataIn(SIEPortDataInToSIE), 
+	.SIEPortTxRdy(SIEPortTxRdy), 
+	.SIEPortWEn(SIEPortWEnToSIE), 
+	.fullSpeedPolarity(fullSpeedPolarityToSIE),
+	.fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(hostTxFifoRE), 
+  .fifoEmpty(hostTxFifoEmpty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostTxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostTxFifo),
+  .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(hostRxFifoWE), 
+  .fifoFull(hostRxFifoFull),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostRxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostRxFifo),
+  .fifoDataIn(hostRxFifoData)  );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+  TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+  TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .clk(clk), 
+  .rst(rst), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .clk(clk), 
+  .rst(rst), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(writeEn), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+endmodule
+
+	
+	
+
+
+
+

Property changes on: common/components/usbhostslave/tags/start/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/aldec.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/aldec.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/SIETransmitter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/SIETransmitter.asf	(revision 264)
@@ -0,0 +1,587 @@
+VERSION=1.19
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FREEOID=955
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/9/2004"
+HEADER_PARAM="TITLE,SIETransmitter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 16
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 216
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 213
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 359
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 455
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 465
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 474
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 483
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 609
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 617
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 626
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 718
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 720
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 717
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 911
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_SIETX\n/22/"
+W 545 458 0 530 540 BEZIER "Transitions" | 168710,66267 156425,60534 83183,49066 70898,43333
+C 557 555 0 TEXT "Conditions" | 72988,107460 1 0 0 "USBWireRdy == 1'b1"
+A 556 555 16 TEXT "Actions" | 112553,111735 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 555 458 0 543 534 BEZIER "Transitions" | 69825,102352 80940,102469 155253,103091 166368,103208
+A 554 534 4 TEXT "Actions" | 157773,116901 1 0 0 "USBWireWEn <= 1'b0;"
+C 553 549 0 TEXT "Conditions" | 134841,94437 1 0 0 "USBWireRdy == 1'b1"
+C 552 547 0 TEXT "Conditions" | 72597,69165 1 0 0 "USBWireRdy == 1'b1"
+A 550 549 16 TEXT "Actions" | 89913,93969 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 549 458 0 534 532 BEZIER "Transitions" | 166590,101641 155007,95674 81782,81027 70199,75060
+A 548 547 16 TEXT "Actions" | 109101,76185 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 547 458 0 532 530 BEZIER "Transitions" | 71250,71190 82482,70839 157007,69015 168239,68664
+L 544 543 0 TEXT "State Labels" | 63328,102539 1 0 0 "WAIT_WIRE\n/47/"
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "SIETx"
+F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: SIETransmitter"
+L 10 11 0 TEXT "State Labels" | 41526,175604 1 0 0 "STX_CHK_ST\n/23/"
+S 11 6 0 ELLIPSE "States" | 41526,175604 6500 6500
+I 12 6 0 Builtin Reset | 22016,204762
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+L 15 16 0 TEXT "State Labels" | 115356,124706 1 0 0 "RES_ST"
+I 816 0 2 Builtin OutPort | 64372,260578 "" ""
+L 817 818 0 TEXT "Labels" | 72692,255938 1 0 0 "processTxByteRdy"
+I 818 0 2 Builtin InPort | 66692,255938 "" ""
+L 819 820 0 TEXT "Labels" | 70372,251298 1 0 0 "TxByteOut[7:0]"
+I 820 0 2 Builtin OutPort | 64372,251298 "" ""
+L 821 822 0 TEXT "Labels" | 70372,246658 1 0 0 "TxByteOutCtrl[7:0]"
+I 822 0 2 Builtin OutPort | 64372,246658 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 824 0 2 Builtin OutPort | 15604,240596 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+A 835 9 4 TEXT "Actions" | 153876,205564 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 5'h0;"
+W 574 458 0 567 543 BEZIER "Transitions" | 44298,153135 48358,141709 56556,119871 60616,108445
+A 563 530 4 TEXT "Actions" | 161517,83673 1 0 0 "USBWireWEn <= 1'b0;"
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+I 572 458 0 Builtin Entry | 44780,253519
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/5/"
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/37/"
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+A 562 532 4 TEXT "Actions" | 37965,60741 1 0 0 "USBWireWEn <= 1'b0;"
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+A 836 63 4 TEXT "Actions" | 101212,188184 1 0 0 "SIEPortTxRdy <= 1'b1;"
+L 837 838 0 TEXT "Labels" | 74732,224652 1 0 0 "SIEPortData[7:0]"
+I 838 0 2 Builtin Signal | 71732,224652 "" ""
+L 839 840 0 TEXT "Labels" | 74500,220244 1 0 0 "SIEPortCtrl[7:0]"
+I 840 0 2 Builtin Signal | 71500,220244 "" ""
+L 843 844 0 TEXT "Labels" | 74500,215836 1 0 0 "i[4:0]"
+I 844 0 2 Builtin Signal | 71500,215836 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 846 0 2 Builtin InPort | 125108,216932 "" ""
+I 847 0 2 Builtin InPort | 125241,221252 "" ""
+L 309 310 0 TEXT "Labels" | 129515,260188 1 0 0 "rstCRC"
+I 310 0 2 Builtin OutPort | 123515,260188 "" ""
+L 311 312 0 TEXT "Labels" | 129156,255220 1 0 0 "CRCData[7:0]"
+I 312 0 2 Builtin OutPort | 123156,255220 "" ""
+L 313 314 0 TEXT "Labels" | 131655,250603 1 0 0 "CRC5Result[4:0]"
+I 314 0 2 Builtin InPort | 125655,250603 "" ""
+L 315 316 0 TEXT "Labels" | 129509,245629 1 0 0 "CRC5En"
+I 316 0 2 Builtin OutPort | 123509,245629 "" ""
+L 317 318 0 TEXT "Labels" | 129866,241010 1 0 0 "CRC5_8Bit"
+I 318 0 2 Builtin OutPort | 123866,241010 "" ""
+L 319 320 0 TEXT "Labels" | 130127,231343 1 0 0 "CRC16En"
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+I 872 360 0 Builtin Exit | 188676,86316
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,169119 41353,163357 41254,137442 41790,133556\
+                                      42326,129670 44202,125650 52711,124511 61220,123372\
+                                      92777,123293 108857,123025
+C 55 51 0 TEXT "Conditions" | 43286,121215 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+L 62 63 0 TEXT "State Labels" | 113731,172352 1 0 0 "STX_WAIT_BYTE\n/24/"
+S 63 6 0 ELLIPSE "States" | 112744,173179 6500 6500
+I 320 0 2 Builtin OutPort | 124127,231343 "" ""
+L 323 324 0 TEXT "Labels" | 132267,236303 1 0 0 "CRC16Result[15:0]"
+I 324 0 2 Builtin InPort | 126267,236303 "" ""
+I 599 489 0 Builtin Entry | 81144,219546
+I 606 489 0 Builtin Exit | 138120,51311
+W 895 224 8194 891 897 BEZIER "Transitions" | 101794,119505 95833,118125 85494,117151 81290,118312\
+                                              77086,119473 72191,126878 71751,132901 71312,138925\
+                                              74451,155618 76866,160637 79282,165657 85808,169046\
+                                              89165,169297 92522,169548 98692,166980 102143,165788
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 5'h7"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/2/"
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+L 890 885 0 TEXT "State Labels" | 60832,129059 1 0 0 "CHK_FIN\n/1/"
+C 889 888 0 TEXT "Conditions" | 62558,122269 1 0 0 "i == 5'h7"
+W 888 217 8193 885 221 BEZIER "Transitions" | 60935,122562 61052,115893 61713,104679 61830,98010
+W 887 217 8194 885 883 BEZIER "Transitions" | 54752,126763 48791,125383 38452,124409 34248,125570\
+                                              30044,126731 25149,134136 24709,140159 24270,146183\
+                                              27409,162876 29824,167895 32240,172915 38766,176304\
+                                              42123,176555 45480,176806 51650,174238 55101,173046
+A 886 885 4 TEXT "Actions" | 76742,138579 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+S 885 217 0 ELLIPSE "States" | 60832,129059 6500 6500
+L 884 883 0 TEXT "State Labels" | 60901,170112 1 0 0 "STX_WAIT_RDY\n/26/"
+S 883 217 0 ELLIPSE "States" | 60901,170112 6500 6500
+C 882 880 0 TEXT "Conditions" | 61330,163577 1 0 0 "USBWireRdy == 1'b1"
+A 881 880 16 TEXT "Actions" | 49805,157344 1 0 0 "USBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+W 880 217 0 883 885 BEZIER "Transitions" | 60836,163644 60774,157457 60714,141730 60652,135543
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,172815 94419,170798 59299,174571 47927,176730
+C 66 65 0 TEXT "Conditions" | 67688,166172 1 0 0 "SIEPortWEn == 1'b1"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,118853 129598,109443 150861,93096 161245,86846
+A 78 65 16 TEXT "Actions" | 54348,179673 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,88472 164661,92612 166410,102460 164070,105655\
+                                        161730,108850 152965,112617 149770,115182 146575,117747\
+                                        142560,124240 140625,130720 138690,137200 135270,157360\
+                                        132480,162850 129690,168340 122852,170455 118982,171355
+L 608 609 0 TEXT "State Labels" | 111818,198264 1 0 0 "PID"
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111818,198264 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114123,147554 6500 6500
+I 909 224 0 Builtin Exit | 108872,88817
+I 908 224 0 Builtin Entry | 85162,237767
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/33/"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/43/"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,169132 41831,151927 41618,118013 42489,108539\
+                                        43361,99065 46384,95576 54928,94878 63472,94181\
+                                        94207,96080 109784,96428
+I 363 360 0 Builtin Entry | 47792,257148
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,97088 6500 6500
+L 358 359 0 TEXT "State Labels" | 116250,97088 1 0 0 "PKT_ST"
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,198320 68542,191838 89078,185356 109614,178874
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 114123,147554 1 0 0 "BYTE1"
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112740,88546 6500 6500
+L 634 626 0 TEXT "State Labels" | 112740,88546 1 0 0 "CRC"
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 636 610 0 Builtin Entry | 71380,236621
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+L 910 911 0 TEXT "State Labels" | 164265,85078 1 0 0 "J1"
+S 911 6 4116 ELLIPSE "Junction" | 164265,85078 3500 3500
+W 927 360 0 933 929 BEZIER "Transitions" | 144010,222256 143885,215969 143879,198227 143754,191940
+C 924 922 0 TEXT "Conditions" | 97818,190135 1 0 0 "USBWireRdy == 1'b1"
+A 923 922 16 TEXT "Actions" | 93859,209922 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit;  \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 922 360 0 929 453 BEZIER "Transitions" | 138043,187612 109537,196045 81451,206574 52945,215007
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+A 920 888 16 TEXT "Actions" | 54464,112031 1 0 0 "USBWireReq <= 1'b0;"
+A 917 371 4 TEXT "Actions" | 71825,218040 1 0 0 "i <= 5'h0;"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 5'h0;"
+C 378 377 0 TEXT "Conditions" | 56860,208360 1 0 0 "USBWireGnt == 1'b1"
+W 377 217 0 371 883 BEZIER "Transitions" | 52975,210241 55849,199016 58723,187790 61597,176565
+A 374 373 16 TEXT "Actions" | 43761,237148 1 0 0 "USBWireReq <= 1'b1;"
+W 373 217 0 220 371 BEZIER "Transitions" | 41882,245025 44900,239618 46527,227520 49545,222113
+S 371 217 0 ELLIPSE "States" | 53178,216725 6500 6500
+L 370 371 0 TEXT "State Labels" | 53178,216725 1 0 0 "STX_WAIT_GNT\n/25/"
+C 369 367 0 TEXT "Conditions" | 48825,92438 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,95197 131651,92175 151659,88825 160842,85803
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/7/"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/40/"
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 645 610 0 Builtin Exit | 114540,97930
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+W 648 489 0 599 609 BEZIER "Transitions" | 84906,219546 91705,215743 99788,205923 106587,202120
+W 649 489 0 609 617 BEZIER "Transitions" | 111887,191768 112232,181972 113177,163821 113522,154025
+W 650 489 0 617 626 BEZIER "Transitions" | 113848,141065 113272,128964 113115,107129 112539,95028
+W 651 489 0 626 606 BEZIER "Transitions" | 115586,82704 120772,74867 130139,59148 135325,51311
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/29/"
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 913 912 0 Builtin Entry | 86360,167640
+I 914 912 0 Builtin Exit | 129540,111760
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+A 937 453 4 TEXT "Actions" | 60460,224205 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+L 934 933 0 TEXT "State Labels" | 144285,228746 1 0 0 "WAIT_GNT\n/49/"
+S 933 360 12288 ELLIPSE "States" | 144285,228746 6500 6500
+A 932 931 16 TEXT "Actions" | 105661,247407 1 0 0 "USBWireReq <= 1'b1;"
+W 931 360 0 363 933 BEZIER "Transitions" | 51554,257148 80200,248283 109429,239528 138075,230663
+L 930 929 0 TEXT "State Labels" | 144175,185833 1 0 0 "WAIT_RDY_WIRE\n/48/"
+S 929 360 8192 ELLIPSE "States" | 144175,185458 6500 6500
+C 928 927 0 TEXT "Conditions" | 145669,221771 1 0 0 "USBWireGnt == 1'b1"
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/31/"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 663 624 0 Builtin Entry | 59190,254840
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+                                           104039,47385 110550,45085 113597,43935
+I 671 624 0 Builtin Exit | 116402,43935
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/50/"
+S 939 633 16384 ELLIPSE "States" | 39277,179580 6500 6500
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 942 943 0 TEXT "Labels" | 171188,226482 1 0 0 "CRC5UpdateRdy"
+I 943 0 2 Builtin InPort | 165188,226482 "" ""
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;	\ni <= i + 1'b1;"
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/0/"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/38/"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+A 414 413 16 TEXT "Actions" | 50880,235676 1 0 0 "USBWireReq <= 1'b1;\ni <= 5'h0;"
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/42/"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/27/"
+I 682 633 0 Builtin Exit | 119917,39891
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+I 944 0 2 Builtin InPort | 165012,221724 "" ""
+L 945 944 0 TEXT "Labels" | 171012,221724 1 0 0 "CRC16UpdateRdy"
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/51/"
+S 947 734 20480 ELLIPSE "States" | 160390,197270 6500 6500
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/52/"
+S 952 624 24576 ELLIPSE "States" | 35474,185224 6500 6500
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "S5\n/17/"
+S 430 17 0 ELLIPSE "States" | 61659,61312 6500 6500
+L 429 430 0 TEXT "State Labels" | 61659,61312 1 0 0 "S4\n/16/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "S3\n/15/"
+C 426 425 0 TEXT "Conditions" | 60723,121216 1 0 0 "i == `RESUME_LEN"
+W 425 17 0 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/34/"
+I 417 17 0 Builtin Entry | 44586,243455
+I 418 17 0 Builtin Exit | 145044,30588
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+W 422 17 8194 407 411 BEZIER "Transitions" | 53385,128518 47424,127138 37085,126164 32881,127325\
+                                             28677,128486 23782,135891 23342,141914 22903,147938\
+                                             26042,164631 28457,169650 30873,174670 37399,178059\
+                                             40756,178310 44113,178561 50283,175993 53734,174801
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "S1\n/14/"
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/30/"
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/6/"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/41/"
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+A 447 438 16 TEXT "Actions" | 92898,48208 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 106002,65992 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 445 436 16 TEXT "Actions" | 86814,83776 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 444 438 0 TEXT "Conditions" | 142974,49612 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 69498,58972 1 0 0 "USBWireRdy == 1'b1"
+C 442 436 0 TEXT "Conditions" | 131742,84244 1 0 0 "USBWireRdy == 1'b1"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+W 438 17 0 432 434 BEZIER "Transitions" | 165378,56758 153093,51025 79495,38601 67210,32868
+W 437 17 0 430 432 BEZIER "Transitions" | 68151,60997 79383,60646 153908,58822 165140,58471
+W 436 17 0 428 430 BEZIER "Transitions" | 163491,91448 151908,85481 78683,70834 67100,64867
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "S6\n/18/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/35/"
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/10/"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251308 41695,240089 71091,229875 69529,218656
+I 711 480 0 Builtin Entry | 43257,253243
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 713 480 0 Builtin Exit | 85376,122104
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79261,129618 82581,122104
+I 715 471 0 Builtin Exit | 140592,59380
+I 716 471 0 Builtin Entry | 83616,227615
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/46/"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 123646,30705 142249,30588
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34866,50548 1 0 0 "USBWireWEn <= 1'b0;"
+A 448 432 4 TEXT "Actions" | 158418,73480 1 0 0 "USBWireWEn <= 1'b0;"
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 731 727 0 Builtin Entry | 71380,236621
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/28/"
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+I 738 727 0 Builtin Exit | 114540,97930
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/36/"
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/9/"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+I 744 734 0 Builtin Exit | 116402,43935
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+I 750 734 0 Builtin Entry | 59190,254840
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/3/"
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 212 213 0 TEXT "State Labels" | 113703,142150 1 0 0 "DIR_CTL"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,140548 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,157040 1 0 0 "IDLE"
+S 216 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,157040 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 220 217 0 Builtin Entry | 38120,245025
+I 221 217 0 Builtin Exit | 61830,96075
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/32/"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+I 762 733 0 Builtin Exit | 119917,39891
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+                                           48829,42592 51359,37532 61605,36267 71852,35002\
+                                           109061,35775 128289,35775
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+                                           48196,74723 50474,70169 60657,69030 70840,67892\
+                                           108432,68626 127660,68626
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+                                           46931,109511 49715,104703 60024,103501 70334,102300\
+                                           108774,103037 128002,103037
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+                                           46299,139871 48829,136075 59202,135063 69575,134052\
+                                           106314,125693 125795,125567
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,169131 41386,166461 41370,161119 41770,159283\
+                                        42170,157448 43639,155445 51849,155011 60059,154577\
+                                        91249,156261 106935,156394
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,169111 41443,162637 41370,149971 41770,146133\
+                                        42170,142296 43639,139892 51882,139324 60126,138757\
+                                        91699,140001 107452,140067
+C 233 232 0 TEXT "Conditions" | 46155,137545 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+C 234 231 0 TEXT "Conditions" | 59709,153376 1 0 0 "SIEPortCtrl == `TX_IDLE"
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,151931 129033,135644 150867,104376 162481,88089
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,135782 128966,124034 151320,99434 161933,87686
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/8/"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/39/"
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/45/"
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+I 787 733 0 Builtin Entry | 62705,250796
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/4/"
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+                                              31250,150650 32250,89650 34750,72525 37250,55400\
+                                              46250,47900 56000,46150 65750,44400 95896,46012\
+                                              103573,44899 111250,43786 113107,43935 113607,43935
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+                                           128857,67252 162473,65260 171997,66691 181521,68123\
+                                           186003,75843 187123,97692 188244,119542 188244,199222\
+                                           184384,221196 180525,243170 165087,251388 155563,253628\
+                                           146039,255869 123379,256617 115100,254625 106821,252633\
+                                           98206,243956 92977,239599
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+S 530 458 0 ELLIPSE "States" | 174738,68697 6500 6500
+L 531 530 0 TEXT "State Labels" | 174738,68697 1 0 0 "SEND_IDLE3\n/21/"
+S 543 458 0 ELLIPSE "States" | 63328,102539 6500 6500
+I 540 458 0 Builtin Exit | 68103,43333
+L 535 534 0 TEXT "State Labels" | 172866,103329 1 0 0 "SEND_IDLE1\n/19/"
+S 534 458 0 ELLIPSE "States" | 172866,103329 6500 6500
+L 533 532 0 TEXT "State Labels" | 64758,71505 1 0 0 "SEND_IDLE2\n/20/"
+S 532 458 0 ELLIPSE "States" | 64758,71505 6500 6500
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/44/"
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+L 807 808 0 TEXT "Labels" | 24830,264678 1 0 0 "SIEPortWEn"
+I 808 0 2 Builtin InPort | 18830,264678 "" ""
+L 809 810 0 TEXT "Labels" | 22510,259806 1 0 0 "SIEPortTxRdy"
+I 810 0 2 Builtin OutPort | 16510,259806 "" ""
+L 811 812 0 TEXT "Labels" | 24598,255166 1 0 0 "SIEPortDataIn[7:0]"
+I 812 0 2 Builtin InPort | 18598,255166 "" ""
+L 813 814 0 TEXT "Labels" | 25062,250526 1 0 0 "SIEPortCtrlIn[7:0]"
+I 814 0 2 Builtin InPort | 19062,250526 "" ""
+L 815 816 0 TEXT "Labels" | 70372,260578 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxBit.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxBit.v	(revision 264)
@@ -0,0 +1,372 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processRxBit.v
+// Generated   : 09/12/04 22:54:47
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processRxBit.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [1:0] RxBitsIn;
+input   clk;
+input   processRxBitsWEn;
+input   processRxByteRdy;
+input   rst;
+output  [7:0] RxCtrlOut;
+output  [7:0] RxDataOut;
+output  processRxBitRdy;
+output  processRxByteWEn;
+output  resumeDetected;
+
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [1:0] RxBitsIn;
+reg     [7:0] RxCtrlOut, next_RxCtrlOut;
+reg     [7:0] RxDataOut, next_RxDataOut;
+wire    clk;
+reg     processRxBitRdy, next_processRxBitRdy;
+wire    processRxBitsWEn;
+wire    processRxByteRdy;
+reg     processRxByteWEn, next_processRxByteWEn;
+reg     resumeDetected, next_resumeDetected;
+wire    rst;
+
+// diagram signals declarations
+reg  [3:0]RXBitCount, next_RXBitCount;
+reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg  [7:0]RXByte, next_RXByte;
+reg  [3:0]RXSameBitCount, next_RXSameBitCount;
+reg  [1:0]RxBits, next_RxBits;
+reg bitStuffError, next_bitStuffError;
+reg  [1:0]oldRXBits, next_oldRXBits;
+reg  [3:0]resumeWaitCnt, next_resumeWaitCnt;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0] CurrState_prRxBit;
+reg [3:0] NextState_prRxBit;
+
+
+//--------------------------------------------------------------------
+// Machine: prRxBit
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
+begin : prRxBit_NextState
+	NextState_prRxBit <= CurrState_prRxBit;
+	// Set default values for outputs and signals
+	next_processRxByteWEn <= processRxByteWEn;
+	next_RxCtrlOut <= RxCtrlOut;
+	next_RxDataOut <= RxDataOut;
+	next_resumeDetected <= resumeDetected;
+	next_RXBitStMachCurrState <= RXBitStMachCurrState;
+	next_RxBits <= RxBits;
+	next_RXSameBitCount <= RXSameBitCount;
+	next_RXBitCount <= RXBitCount;
+	next_oldRXBits <= oldRXBits;
+	next_RXByte <= RXByte;
+	next_bitStuffError <= bitStuffError;
+	next_resumeWaitCnt <= resumeWaitCnt;
+	next_processRxBitRdy <= processRxBitRdy;
+	case (CurrState_prRxBit) // synopsys parallel_case full_case
+		`START:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			next_RxCtrlOut <= 8'h00;
+			next_RxDataOut <= 8'h00;
+			next_resumeDetected <= 1'b0;
+			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			next_RxBits <= 2'b00;
+			next_RXSameBitCount <= 4'h0;
+			next_RXBitCount <= 4'h0;
+			next_oldRXBits <= 2'b00;
+			next_RXByte <= 8'h00;
+			next_bitStuffError <= 1'b0;
+			next_resumeWaitCnt <= 4'h0;
+			next_processRxBitRdy <= 1'b1;
+			NextState_prRxBit <= `WAIT_BITS;
+		end
+		`WAIT_BITS:
+			if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))	
+			begin
+				NextState_prRxBit <= `DATA_RX_CHK_SE0;
+				next_RxBits <= RxBitsIn;
+				next_processRxBitRdy <= 1'b0;
+			end
+			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))	
+			begin
+				NextState_prRxBit <= `RES_RX_CHK;
+				next_RxBits <= RxBitsIn;
+				next_processRxBitRdy <= 1'b0;
+			end
+			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))	
+			begin
+				NextState_prRxBit <= `RES_END_CHK1;
+				next_RxBits <= RxBitsIn;
+				next_processRxBitRdy <= 1'b0;
+			end
+			else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))	
+			begin
+				NextState_prRxBit <= `IDLE_CHK_KBIT;
+				next_RxBits <= RxBitsIn;
+				next_processRxBitRdy <= 1'b0;
+			end
+		`IDLE_FIRST_BIT:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+			next_RXSameBitCount <= 4'h1;
+			next_RXBitCount <= 4'h1;
+			next_oldRXBits <= RxBits;
+			//zero is always the first RZ data bit of a new packet
+			next_RXByte <= 8'h00;
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`IDLE_CHK_KBIT:
+			if (RxBits == KBit)	
+				NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+			else
+			begin
+				NextState_prRxBit <= `WAIT_BITS;
+				next_processRxBitRdy <= 1'b1;
+			end
+		`IDLE_WAIT_PRB_RDY:
+			if (processRxByteRdy == 1'b1)	
+			begin
+				NextState_prRxBit <= `IDLE_FIRST_BIT;
+				next_RxDataOut <= 8'h00;
+				//redundant data
+				next_RxCtrlOut <= `DATA_START;
+				//start of packet
+				next_processRxByteWEn <= 1'b1;
+			end
+		`DATA_RX_LAST_BIT:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`DATA_RX_CHK_SE0:
+		begin
+			next_bitStuffError <= 1'b0;
+			if (RxBits == `SE0)	
+				NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+			else
+			begin
+				NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+				if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
+				begin
+				  next_RXSameBitCount <= RXSameBitCount + 1'b1;
+				    //inc 'RXSameBitCount'
+				    if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error
+				    next_bitStuffError <= 1'b1;
+				        //flag 'bitStuffError'
+				    else                                          //else no bit stuffing error
+				    begin
+				    next_RXBitCount <= RXBitCount + 1'b1;
+				        if (RXBitCount != 4'h7) begin
+				      next_processRxBitRdy <= 1'b1;
+				            //early indication of ready
+						end
+				    next_RXByte <= { 1'b1, RXByte[7:1]};
+				        //RZ bit = 1 (ie no change in 'RxBits')
+				    end
+				end
+				else                                            //else current 'RxBits' are different from old 'RxBits'
+				begin
+				    if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+				    begin
+				    next_RXBitCount <= RXBitCount + 1'b1;
+				        if (RXBitCount != 4'h7) begin
+				      next_processRxBitRdy <= 1'b1;
+				            //early indication of ready
+						end
+				    next_RXByte <= {1'b0, RXByte[7:1]};
+				        //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
+				    end
+				  next_RXSameBitCount <= 4'h1;
+				    //reset 'RXSameBitCount'
+				end
+				next_oldRXBits <= RxBits;
+			end
+		end
+		`DATA_RX_WAIT_PRB_RDY:
+			if (processRxByteRdy == 1'b1)	
+			begin
+				NextState_prRxBit <= `DATA_RX_LAST_BIT;
+				next_RxDataOut <= 8'h00;
+				//redundant data
+				next_RxCtrlOut <= `DATA_STOP;
+				//end of packet
+				next_processRxByteWEn <= 1'b1;
+			end
+		`DATA_RX_DATA_DESTUFF:
+			if (RXBitCount == 4'h8 & bitStuffError == 1'b0)	
+				NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+			else if (bitStuffError == 1'b1)	
+				NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+			else
+			begin
+				NextState_prRxBit <= `WAIT_BITS;
+				next_processRxBitRdy <= 1'b1;
+			end
+		`DATA_RX_BYTE_SEND2:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`DATA_RX_BYTE_WAIT_RDY:
+			if (processRxByteRdy == 1'b1)	
+			begin
+				NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+				next_RXBitCount <= 4'h0;
+				next_RxDataOut <= RXByte;
+				next_RxCtrlOut <= `DATA_STREAM;
+				next_processRxByteWEn <= 1'b1;
+			end
+		`DATA_RX_ERROR_CHK_RES:
+		begin
+			next_processRxByteWEn <= 1'b0;
+			if (RxBits == JBit)                           //if current bit is a JBit, then
+			  next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			    //next state is idle
+			else                                          //else
+			begin
+			  next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+			    //check for resume
+			  next_resumeWaitCnt <= 0;
+			end
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`DATA_RX_ERROR_WAIT_RDY:
+			if (processRxByteRdy == 1'b1)	
+			begin
+				NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+				next_RxDataOut <= 8'h00;
+				//redundant data
+				next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+				next_processRxByteWEn <= 1'b1;
+			end
+		`RES_RX_CHK:
+		begin
+			if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
+			  next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			else
+			begin
+			  next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+			    //if we've waited long enough, then
+			    if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)
+			    begin
+			    next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+			    next_resumeDetected <= 1'b1;
+			        //report resume detected
+			    end
+			end
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+		`RES_END_CHK1:
+		begin
+			if (RxBits != KBit)  //line must leave KBit state for the end of resume
+			begin
+			  next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+			  next_resumeDetected <= 1'b0;
+			    //clear resume detected flag
+			end
+			NextState_prRxBit <= `WAIT_BITS;
+			next_processRxBitRdy <= 1'b1;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prRxBit_CurrentState
+	if (rst)	
+		CurrState_prRxBit <= `START;
+	else
+		CurrState_prRxBit <= NextState_prRxBit;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prRxBit_RegOutput
+	if (rst)	
+	begin
+		RXBitStMachCurrState <= `IDLE_BIT_ST;
+		RxBits <= 2'b00;
+		RXSameBitCount <= 4'h0;
+		RXBitCount <= 4'h0;
+		oldRXBits <= 2'b00;
+		RXByte <= 8'h00;
+		bitStuffError <= 1'b0;
+		resumeWaitCnt <= 4'h0;
+		processRxByteWEn <= 1'b0;
+		RxCtrlOut <= 8'h00;
+		RxDataOut <= 8'h00;
+		resumeDetected <= 1'b0;
+		processRxBitRdy <= 1'b1;
+	end
+	else 
+	begin
+		RXBitStMachCurrState <= next_RXBitStMachCurrState;
+		RxBits <= next_RxBits;
+		RXSameBitCount <= next_RXSameBitCount;
+		RXBitCount <= next_RXBitCount;
+		oldRXBits <= next_oldRXBits;
+		RXByte <= next_RXByte;
+		bitStuffError <= next_bitStuffError;
+		resumeWaitCnt <= next_resumeWaitCnt;
+		processRxByteWEn <= next_processRxByteWEn;
+		RxCtrlOut <= next_RxCtrlOut;
+		RxDataOut <= next_RxDataOut;
+		resumeDetected <= next_resumeDetected;
+		processRxBitRdy <= next_processRxBitRdy;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processTxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processTxByte.v	(revision 264)
@@ -0,0 +1,308 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processTxByte.v
+// Generated   : 08/29/04 21:36:09
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processTxByte.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteIn, USBWireCtrl, USBWireData, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [7:0] TxByteCtrlIn;
+input   [7:0] TxByteIn;
+input   USBWireGnt;
+input   USBWireRdy;
+input   clk;
+input   processTxByteWEn;
+input   rst;
+output  USBWireCtrl;
+output  [1:0] USBWireData;
+output  USBWireReq;
+output  USBWireWEn;
+output  processTxByteRdy;
+
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [7:0] TxByteCtrlIn;
+wire    [7:0] TxByteIn;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0] USBWireData, next_USBWireData;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+reg     processTxByteRdy, next_processTxByteRdy;
+wire    processTxByteWEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [1:0]TXLineState, next_TXLineState;
+reg  [3:0]TXOneCount, next_TXOneCount;
+reg  [7:0]TxByteCtrl, next_TxByteCtrl;
+reg  [7:0]TxByte, next_TxByte;
+reg  [3:0]i, next_i;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 4'b0000
+`define PTBY_WAIT_EN 4'b0001
+`define SEND_BYTE_UPDATE_BYTE 4'b0010
+`define SEND_BYTE_WAIT_RDY 4'b0011
+`define SEND_BYTE_CHK 4'b0100
+`define SEND_BYTE_BIT_STUFF 4'b0101
+`define SEND_BYTE_WAIT_RDY2 4'b0110
+`define SEND_BYTE_CHK_FIN 4'b0111
+`define PTBY_WAIT_GNT 4'b1000
+`define STOP_SND_SE0_2 4'b1001
+`define STOP_SND_SE0_1 4'b1010
+`define STOP_CHK 4'b1011
+`define STOP_SND_J 4'b1100
+`define STOP_SND_IDLE 4'b1101
+`define STOP_FIN 4'b1110
+
+reg [3:0] CurrState_prcTxB;
+reg [3:0] NextState_prcTxB;
+
+
+//--------------------------------------------------------------------
+// Machine: prcTxB
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (TxByteIn or TxByteCtrlIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or CurrState_prcTxB)
+begin : prcTxB_NextState
+	NextState_prcTxB <= CurrState_prcTxB;
+	// Set default values for outputs and signals
+	next_processTxByteRdy <= processTxByteRdy;
+	next_USBWireData <= USBWireData;
+	next_USBWireCtrl <= USBWireCtrl;
+	next_USBWireReq <= USBWireReq;
+	next_USBWireWEn <= USBWireWEn;
+	next_i <= i;
+	next_TxByte <= TxByte;
+	next_TxByteCtrl <= TxByteCtrl;
+	next_TXLineState <= TXLineState;
+	next_TXOneCount <= TXOneCount;
+	case (CurrState_prcTxB) // synopsys parallel_case full_case
+		`START_PTBY:
+		begin
+			next_processTxByteRdy <= 1'b0;
+			next_USBWireData <= 2'b00;
+			next_USBWireCtrl <= `TRI_STATE;
+			next_USBWireReq <= 1'b0;
+			next_USBWireWEn <= 1'b0;
+			next_i <= 4'h0;
+			next_TxByte <= 8'h00;
+			next_TxByteCtrl <= 8'h00;
+			next_TXLineState <= 2'b0;
+			next_TXOneCount <= 4'h0;
+			NextState_prcTxB <= `PTBY_WAIT_EN;
+		end
+		`PTBY_WAIT_EN:
+		begin
+			next_processTxByteRdy <= 1'b1;
+			if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))	
+			begin
+				NextState_prcTxB <= `PTBY_WAIT_GNT;
+				next_processTxByteRdy <= 1'b0;
+				next_TxByte <= TxByteIn;
+				next_TxByteCtrl <= TxByteCtrlIn;
+				next_TXOneCount <= 1;
+				next_TXLineState <= JBit;
+				next_USBWireReq <= 1'b1;
+			end
+			else if (processTxByteWEn == 1'b1)	
+			begin
+				NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+				next_processTxByteRdy <= 1'b0;
+				next_TxByte <= TxByteIn;
+				next_TxByteCtrl <= TxByteCtrlIn;
+				next_i <= 4'h0;
+			end
+		end
+		`PTBY_WAIT_GNT:
+			if (USBWireGnt == 1'b1)	
+			begin
+				NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+				next_i <= 4'h0;
+			end
+		`SEND_BYTE_UPDATE_BYTE:
+		begin
+			next_i <= i + 1'b1;
+			next_TxByte <= {1'b0, TxByte[7:1] };
+			if (TxByte[0] == 1'b1)                      //If this bit is 1, then
+			  next_TXOneCount <= TXOneCount + 1'b1;
+			    //increment 'TXOneCount'
+			else                                        //else this is a zero bit
+			begin
+			  next_TXOneCount <= 4'h1;
+			    //reset 'TXOneCount'
+			  if (TXLineState == JBit) next_TXLineState <= KBit;
+			    //toggle the line state
+			  else next_TXLineState <= JBit;
+			end
+			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+		end
+		`SEND_BYTE_WAIT_RDY:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `SEND_BYTE_CHK;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= TXLineState;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		`SEND_BYTE_CHK:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (TXOneCount == 4'h6)	
+				NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+			else if (i != 4'h8)	
+				NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+			else
+				NextState_prcTxB <= `STOP_CHK;
+		end
+		`SEND_BYTE_BIT_STUFF:
+		begin
+			next_TXOneCount <= 4'h1;
+			//reset 'TXOneCount'
+			if (TXLineState == JBit) next_TXLineState <= KBit;
+			//toggle the line state
+			else next_TXLineState <= JBit;
+			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+		end
+		`SEND_BYTE_WAIT_RDY2:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= TXLineState;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		`SEND_BYTE_CHK_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (i == 4'h8)	
+				NextState_prcTxB <= `STOP_CHK;
+			else
+				NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+		end
+		`STOP_SND_SE0_2:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `STOP_SND_J;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= `SE0;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		end
+		`STOP_SND_SE0_1:
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `STOP_SND_SE0_2;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= `SE0;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		`STOP_CHK:
+			if (TxByteCtrl == `DATA_STOP)	
+				NextState_prcTxB <= `STOP_SND_SE0_1;
+			else
+				NextState_prcTxB <= `PTBY_WAIT_EN;
+		`STOP_SND_J:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `STOP_SND_IDLE;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `DRIVE;
+			end
+		end
+		`STOP_SND_IDLE:
+		begin
+			next_USBWireWEn <= 1'b0;
+			if (USBWireRdy == 1'b1)	
+			begin
+				NextState_prcTxB <= `STOP_FIN;
+				next_USBWireWEn <= 1'b1;
+				next_USBWireData <= JBit;
+				next_USBWireCtrl <= `TRI_STATE;
+			end
+		end
+		`STOP_FIN:
+		begin
+			next_USBWireWEn <= 1'b0;
+			next_USBWireReq <= 1'b0;
+			//release the wire
+			NextState_prcTxB <= `PTBY_WAIT_EN;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prcTxB_CurrentState
+	if (rst)	
+		CurrState_prcTxB <= `START_PTBY;
+	else
+		CurrState_prcTxB <= NextState_prcTxB;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prcTxB_RegOutput
+	if (rst)	
+	begin
+		i <= 4'h0;
+		TxByte <= 8'h00;
+		TxByteCtrl <= 8'h00;
+		TXLineState <= 2'b0;
+		TXOneCount <= 4'h0;
+		processTxByteRdy <= 1'b0;
+		USBWireData <= 2'b00;
+		USBWireCtrl <= `TRI_STATE;
+		USBWireReq <= 1'b0;
+		USBWireWEn <= 1'b0;
+	end
+	else 
+	begin
+		i <= next_i;
+		TxByte <= next_TxByte;
+		TxByteCtrl <= next_TxByteCtrl;
+		TXLineState <= next_TXLineState;
+		TXOneCount <= next_TXOneCount;
+		processTxByteRdy <= next_processTxByteRdy;
+		USBWireData <= next_USBWireData;
+		USBWireCtrl <= next_USBWireCtrl;
+		USBWireReq <= next_USBWireReq;
+		USBWireWEn <= next_USBWireWEn;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/updateCRC16.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/updateCRC16.v	(revision 264)
@@ -0,0 +1,110 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC16.v                                                ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: updateCRC16.v,v 1.1.1.1 2004-10-11 04:01:04 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [15:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [15:0] CRCResult;
+reg    ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 16'hffff;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0)
+    begin
+      if (CRCEn == 1'b1) begin
+	      doUpdateCRC = 1'b1;
+	      data <= dataIn;
+        ready <= 1'b0;
+	  end
+    end
+    else begin
+	    i <= i + 1'b1;
+	    if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+	      CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+	    end
+	    else begin
+	      CRCResult <= {1'b0, CRCResult[15:1]};
+	    end
+	    data <= {1'b0, data[7:1]};
+	    if (i == 4'h7)
+	    begin
+	      doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+	    end
+    end
+  end
+end
+		
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(revision 264)
@@ -0,0 +1,172 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\usbTxWireArbiter.v
+// Generated   : 06/05/04 05:53:14
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\usbTxWireArbiter.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbConstants_h.v"
+
+module USBWireTxArbiter (SIETxCtrl, SIETxData, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, USBWireRdyIn, USBWireRdyOut, USBWireWEn, clk, prcTxByteCtrl, prcTxByteData, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst);
+input   SIETxCtrl;
+input   [1:0] SIETxData;
+input   SIETxReq;
+input   SIETxWEn;
+input   USBWireRdyIn;
+input   clk;
+input   prcTxByteCtrl;
+input   [1:0] prcTxByteData;
+input   prcTxByteReq;
+input   prcTxByteWEn;
+input   rst;
+output  SIETxGnt;
+output  [1:0] TxBits;
+output  TxCtl;
+output  USBWireRdyOut;
+output  USBWireWEn;
+output  prcTxByteGnt;
+
+wire    SIETxCtrl;
+wire    [1:0] SIETxData;
+reg     SIETxGnt, next_SIETxGnt;
+wire    SIETxReq;
+wire    SIETxWEn;
+reg     [1:0] TxBits, next_TxBits;
+reg     TxCtl, next_TxCtl;
+wire    USBWireRdyIn;
+reg     USBWireRdyOut, next_USBWireRdyOut;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+wire    prcTxByteCtrl;
+wire    [1:0] prcTxByteData;
+reg     prcTxByteGnt, next_prcTxByteGnt;
+wire    prcTxByteReq;
+wire    prcTxByteWEn;
+wire    rst;
+
+// diagram signals declarations
+reg muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0] CurrState_txWireArb;
+reg [1:0] NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+    USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)
+begin
+    if (muxSIENotPTXB  == 1'b1)
+    begin
+        USBWireWEn <= SIETxWEn;
+        TxBits <= SIETxData;
+        TxCtl <= SIETxCtrl;
+    end
+    else
+    begin
+        USBWireWEn <= prcTxByteWEn;
+        TxBits <= prcTxByteData;
+        TxCtl <= prcTxByteCtrl;
+    end
+end
+
+
+//--------------------------------------------------------------------
+// Machine: txWireArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb)
+begin : txWireArb_NextState
+	NextState_txWireArb <= CurrState_txWireArb;
+	// Set default values for outputs and signals
+	next_prcTxByteGnt <= prcTxByteGnt;
+	next_muxSIENotPTXB <= muxSIENotPTXB;
+	next_SIETxGnt <= SIETxGnt;
+	case (CurrState_txWireArb) // synopsys parallel_case full_case
+		`START_TARB:
+			NextState_txWireArb <= `TARB_WAIT_REQ;
+		`TARB_WAIT_REQ:
+			if (prcTxByteReq == 1'b1)	
+			begin
+				NextState_txWireArb <= `PTXB_ACT;
+				next_prcTxByteGnt <= 1'b1;
+				next_muxSIENotPTXB <= 1'b0;
+			end
+			else if (SIETxReq == 1'b1)	
+			begin
+				NextState_txWireArb <= `SIE_TX_ACT;
+				next_SIETxGnt <= 1'b1;
+				next_muxSIENotPTXB <= 1'b1;
+			end
+		`PTXB_ACT:
+			if (prcTxByteReq == 1'b0)	
+			begin
+				NextState_txWireArb <= `TARB_WAIT_REQ;
+				next_prcTxByteGnt <= 1'b0;
+			end
+		`SIE_TX_ACT:
+			if (SIETxReq == 1'b0)	
+			begin
+				NextState_txWireArb <= `TARB_WAIT_REQ;
+				next_SIETxGnt <= 1'b0;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : txWireArb_CurrentState
+	if (rst)	
+		CurrState_txWireArb <= `START_TARB;
+	else
+		CurrState_txWireArb <= NextState_txWireArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : txWireArb_RegOutput
+	if (rst)	
+	begin
+		muxSIENotPTXB <= 1'b0;
+		prcTxByteGnt <= 1'b0;
+		SIETxGnt <= 1'b0;
+	end
+	else 
+	begin
+		muxSIENotPTXB <= next_muxSIENotPTXB;
+		prcTxByteGnt <= next_prcTxByteGnt;
+		SIETxGnt <= next_SIETxGnt;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/fifoMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/fifoMux.v	(revision 264)
@@ -0,0 +1,217 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: fifoMux.v,v 1.1.1.1 2004-10-11 04:01:05 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module fifoMux (
+  currEndP,
+  //TxFifo
+  TxFifoREn,
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoData,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEmpty,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  //RxFifo
+  RxFifoWEn,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoFull,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+  //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+  //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+  TxFifoREn or
+  RxFifoWEn or
+  TxFifoEP0Data or
+  TxFifoEP1Data or
+  TxFifoEP2Data or
+  TxFifoEP3Data or
+  TxFifoEP0Empty or
+  TxFifoEP1Empty or
+  TxFifoEP2Empty or
+  TxFifoEP3Empty or
+  RxFifoEP0Full or
+  RxFifoEP1Full or
+  RxFifoEP2Full or
+  RxFifoEP3Full)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      TxFifoEP0REn <= TxFifoREn;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP0Data;
+      TxFifoEmpty <= TxFifoEP0Empty;
+      RxFifoEP0WEn <= RxFifoWEn;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP0Full;
+    end
+    2'b01: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= TxFifoREn;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP1Data;
+      TxFifoEmpty <= TxFifoEP1Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= RxFifoWEn;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP1Full;
+    end
+    2'b10: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= TxFifoREn;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP2Data;
+      TxFifoEmpty <= TxFifoEP2Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= RxFifoWEn;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP2Full;
+    end
+    2'b11: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= TxFifoREn;
+      TxFifoData <= TxFifoEP3Data;
+      TxFifoEmpty <= TxFifoEP3Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= RxFifoWEn;
+      RxFifoFull <= RxFifoEP3Full;
+    end
+  endcase  
+end      
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/slaveDirectcontrol.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/slaveDirectcontrol.v	(revision 264)
@@ -0,0 +1,167 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveDirectcontrol.v
+// Generated   : 06/05/04 05:59:19
+// From        : c:\projects\USBHostSlave\RTL\slaveController\slaveDirectcontrol.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   clk;
+input   directControlEn;
+input   [1:0] directControlLineState;
+input   rst;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+wire    clk;
+wire    directControlEn;
+wire    [1:0] directControlLineState;
+wire    rst;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0] CurrState_slvDrctCntl;
+reg [2:0] NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+//--------------------------------------------------------------------
+// Machine: slvDrctCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)
+begin : slvDrctCntl_NextState
+	NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+	// Set default values for outputs and signals
+	next_SCTxPortReq <= SCTxPortReq;
+	next_SCTxPortWEn <= SCTxPortWEn;
+	next_SCTxPortData <= SCTxPortData;
+	next_SCTxPortCntl <= SCTxPortCntl;
+	case (CurrState_slvDrctCntl) // synopsys parallel_case full_case
+		`START_SDC:
+			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+		`CHK_DRCT_CNTL:
+			if (directControlEn == 1'b1)	
+			begin
+				NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+				next_SCTxPortReq <= 1'b1;
+			end
+			else
+			begin
+				NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+				next_SCTxPortReq <= 1'b1;
+			end
+		`DRCT_CNTL_WAIT_GNT:
+			if (SCTxPortGnt == 1'b1)	
+				NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+		`DRCT_CNTL_CHK_LOOP:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			if (directControlEn == 1'b0)	
+			begin
+				NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+				next_SCTxPortReq <= 1'b0;
+			end
+			else
+				NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+		end
+		`DRCT_CNTL_WAIT_RDY:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+				next_SCTxPortWEn <= 1'b1;
+				next_SCTxPortData <= {6'b000000, directControlLineState};
+				next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+			end
+		`IDLE_FIN:
+		begin
+			next_SCTxPortWEn <= 1'b0;
+			next_SCTxPortReq <= 1'b0;
+			NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+		end
+		`IDLE_WAIT_GNT:
+			if (SCTxPortGnt == 1'b1)	
+				NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+		`IDLE_WAIT_RDY:
+			if (SCTxPortRdy == 1'b1)	
+			begin
+				NextState_slvDrctCntl <= `IDLE_FIN;
+				next_SCTxPortWEn <= 1'b1;
+				next_SCTxPortData <= 8'h00;
+				next_SCTxPortCntl <= `TX_IDLE;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_CurrentState
+	if (rst)	
+		CurrState_slvDrctCntl <= `START_SDC;
+	else
+		CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_RegOutput
+	if (rst)	
+	begin
+		SCTxPortCntl <= 8'h00;
+		SCTxPortData <= 8'h00;
+		SCTxPortWEn <= 1'b0;
+		SCTxPortReq <= 1'b0;
+	end
+	else 
+	begin
+		SCTxPortCntl <= next_SCTxPortCntl;
+		SCTxPortData <= next_SCTxPortData;
+		SCTxPortWEn <= next_SCTxPortWEn;
+		SCTxPortReq <= next_SCTxPortReq;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/slaveSendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/slaveSendpacket.asf	(revision 264)
@@ -0,0 +1,170 @@
+VERSION=1.19
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FREEOID=215
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,slaveSendPacket"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 21
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 45
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "SP_WAIT_ENABLE\n/1/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP1\n/0/"
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
+F 6 0 671089152 188 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: slaveSendPacket"
+I 12 6 0 Builtin Reset | 74872,202290
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP1_WAIT_GNT\n/2/"
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nSCTxPortReq <= 1'b1;"
+L 20 21 0 TEXT "State Labels" | 113767,93734 1 0 0 "SP_SEND_PID"
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113767,93734 6500 6500
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 112951,104607 113260,100204
+C 23 22 0 TEXT "Conditions" | 114630,116691 1 0 0 "SCTxPortGnt == 1'b1"
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 29624,2084 214124,250084
+S 26 25 16384 ELLIPSE "States" | 72734,192072 6500 6500
+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
+I 28 25 0 Builtin Entry | 49237,230379
+I 29 25 0 Builtin Exit | 146004,95604
+W 30 25 0 28 26 BEZIER "Transitions" | 53779,230379 60054,220138 63123,209223 69341,197615
+L 32 33 0 TEXT "State Labels" | 75021,153035 1 0 0 "FIN\n/4/"
+S 33 25 20480 ELLIPSE "States" | 75021,153035 6500 6500
+W 34 25 0 26 33 BEZIER "Transitions" | 72953,185597 73302,178879 73960,166205 74309,159487
+C 36 34 0 TEXT "Conditions" | 75236,185214 1 0 0 "SCTxPortRdy == 1'b1"
+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
+A 38 33 4 TEXT "Actions" | 93627,154331 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 39 25 0 33 29 BEZIER "Transitions" | 79375,148210 95944,135371 126275,108443 142844,95604
+L 44 45 0 TEXT "State Labels" | 182202,45960 1 0 0 "SP_D0_D1"
+S 45 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,45960 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
+S 47 6 28672 ELLIPSE "States" | 115848,16910 6500 6500
+W 48 6 8194 21 205 BEZIER "Transitions" | 108645,89734 97773,80901 77133,63853 66261,55020
+W 50 6 8193 21 45 BEZIER "Transitions" | 119169,90120 134042,80003 162156,60011 177029,49894
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+W 73 6 0 45 47 BEZIER "Transitions" | 176581,42697 162161,37714 135904,25306 121888,19311
+W 74 6 0 205 47 BEZIER "Transitions" | 67096,47093 78647,41129 99521,27639 110324,20335
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 127 65 0 Builtin Exit | 176933,37229
+I 126 65 0 Builtin Entry | 68162,237252
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1;	 \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
+S 136 65 32768 ELLIPSE "States" | 97326,133352 6500 6500
+W 128 65 0 126 145 BEZIER "Transitions" | 72704,237252 77515,245311 99394,235265 108723,227500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 173 0 2 Builtin InPort | 35299,213676 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 2 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170187,37688 173773,37229
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+I 185 0 2 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 183 0 2 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "SCTxPortWEn"
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 0 Builtin Signal | 35000,231468 "" ""
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
+W 210 65 0 207 145 BEZIER "Transitions" | 169895,125680 176804,126013 188953,127552 193864,130465\
+                                          198775,133379 204604,144369 205686,152818 206768,161268\
+                                          205269,184079 201481,192903 197694,201727 184040,214216\
+                                          173218,217462 162396,220708 133810,221642 118992,221891
+W 209 65 0 136 207 BEZIER "Transitions" | 103712,132145 117531,130730 143304,126529 157123,125114
+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 76973,151815 1 0 0 "CLR_REN\n/13/"
+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/usbSlaveControl.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/usbSlaveControl.v	(revision 264)
@@ -0,0 +1,498 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSlaveControl.v,v 1.1.1.1 2004-10-11 04:01:10 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module usbSlaveControl(
+	clk, rst,
+	//getPacket
+	RxByteStatus, RxData, RxDataValid,
+	SIERxTimeOut, RxFifoData,
+	//speedCtrlMux
+	fullSpeedRate, fullSpeedPol,
+	//SCTxPortArbiter
+	SCTxPortEn, SCTxPortRdy,
+	SCTxPortData, SCTxPortCtrl,
+	//rxStatusMonitor
+	connectStateIn, 
+	resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+	SOFRxedIntOut, 
+  resetEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  NAKSentIntOut,
+  slaveControlSelect,
+  //fifoMux
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+ 	 );
+
+input clk, rst;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [4:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut; 
+output resetEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire clk;
+wire rst;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut; 
+wire resetEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;	  
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed; 
+wire CRCError; 
+wire RXOverflow; 
+wire RXTimeOut; 
+wire bitStuffError; 
+wire dataSequence; 
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [3:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+
+USBSlaveControlBI u_USBSlaveControlBI
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .clk(clk), 
+  .rst(rst),
+	.SOFRxedIntOut(SOFRxedIntOut), 
+  .resetEventIntOut(resetEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+	.NAKSentIntOut(NAKSentIntOut),
+  .endP0TransTypeReg(endP0TransTypeReg), 
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg), 
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg), 
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg), 
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .EP0StatusReg(endP0StatusReg),
+  .EP1StatusReg(endP1StatusReg),
+  .EP2StatusReg(endP2StatusReg),
+  .EP3StatusReg(endP3StatusReg),
+  .SCAddrReg(USBTgtAddress), 
+  .frameNum(frameNum),
+  .connectStateIn(connectStateOut),
+	.SOFRxedIn(SOFRxed), 
+  .resetEventIn(resetEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .NAKSentIn(NAKSent),
+  .slaveControlSelect(slaveControlSelect),
+  .clrEP0Ready(clrEP0Rdy), 
+  .clrEP1Ready(clrEP1Rdy), 
+  .clrEP2Ready(clrEP2Rdy), 
+  .clrEP3Ready(clrEP3Rdy),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .SCGlobalEn(SCGlobalEn)
+  );
+
+slavecontroller u_slavecontroller
+  (.CRCError(CRCError), 
+  .NAKSent(NAKSent), 
+  .RxByte(RxData), 
+  .RxDataWEn(RxDataValid), 
+  .RxOverflow(RXOverflow), 
+  .RxStatus(RxByteStatus), 
+  .RxTimeOut(RXTimeOut), 
+  .SCGlobalEn(SCGlobalEn), 
+  .SOFRxed(SOFRxed), 
+  .USBEndPControlReg(endPControlReg), 
+  .USBEndPNakTransTypeReg(transTypeNAK), 
+  .USBEndPTransTypeReg(transType), 
+  .USBEndP(currEndP), 
+  .USBTgtAddress(USBTgtAddress),
+  .bitStuffError(bitStuffError), 
+  .clk(clk), 
+  .clrEPRdy(clrEPRdy), 
+  .endPMuxErrorsWEn(endPMuxErrorsWEn), 
+  .frameNum(frameNum), 
+  .getPacketREn(getPacketREn), 
+  .getPacketRdy(getPacketRdy), 
+  .rst(rst), 
+  .sendPacketPID(slaveControllerPIDOut), 
+  .sendPacketRdy(slaveControllerReadyIn), 
+  .sendPacketWEn(slaveControllerWEnOut), 
+  .stallSent(stallSent), 
+  .transDone(transDone) 
+    );
+
+
+endpMux u_endpMux (
+  .clk(clk), 
+  .rst(rst),
+  .currEndP(currEndP),
+  .NAKSent(NAKSent),
+  .stallSent(stallSent),
+  .CRCError(CRCError),
+  .bitStuffError(bitStuffError),
+  .RxOverflow(RXOverflow),
+  .RxTimeOut(RXTimeOut),
+  .dataSequence(dataSequence),
+  .ACKRxed(ACKRxed),
+  .transType(transType),
+  .transTypeNAK(transTypeNAK),
+  .endPControlReg(endPControlReg),
+  .clrEPRdy(clrEPRdy),
+  .endPMuxErrorsWEn(endPMuxErrorsWEn),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .endP0StatusReg(endP0StatusReg),
+  .endP1StatusReg(endP1StatusReg),
+  .endP2StatusReg(endP2StatusReg),
+  .endP3StatusReg(endP3StatusReg),
+  .endP0TransTypeReg(endP0TransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg),
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .clrEP0Rdy(clrEP0Rdy),
+  .clrEP1Rdy(clrEP1Rdy),
+  .clrEP2Rdy(clrEP2Rdy),
+  .clrEP3Rdy(clrEP3Rdy)
+    );
+
+slaveSendPacket u_slaveSendPacket
+  (.PID(slaveControllerPIDOut), 
+	.SCTxPortCntl(sendPacketCntl),
+	.SCTxPortData(sendPacketData),
+	.SCTxPortGnt(sendPacketGnt),
+	.SCTxPortRdy(SCTxPortArbRdyOut),
+	.SCTxPortReq(sendPacketReq),
+	.SCTxPortWEn(sendPacketWEn),
+	.clk(clk),
+	.fifoData(TxFifoData),
+	.fifoEmpty(TxFifoEmpty),
+	.fifoReadEn(TxFifoRE),
+	.rst(rst),
+	.sendPacketRdy(slaveControllerReadyIn),
+	.sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+	(.SCTxPortCntl(directCntlCntl),
+	.SCTxPortData(directCntlData),
+	.SCTxPortGnt(directCntlGnt),
+	.SCTxPortRdy(SCTxPortArbRdyOut),
+	.SCTxPortReq(directCntlReq),
+	.SCTxPortWEn(directCntlWEn),
+	.clk(clk),
+	.directControlEn(directLineCtrlEn),
+	.directControlLineState(directLineState),
+	.rst(rst) ); 
+
+SCTxPortArbiter u_SCTxPortArbiter
+	(.SCTxPortCntl(SCTxPortCtrl),
+	.SCTxPortData(SCTxPortData),
+	.SCTxPortRdyIn(SCTxPortRdy),
+	.SCTxPortRdyOut(SCTxPortArbRdyOut),
+	.SCTxPortWEnable(SCTxPortEn),
+	.clk(clk),
+	.directCntlCntl(directCntlCntl),
+	.directCntlData(directCntlData),
+	.directCntlGnt(directCntlGnt),
+	.directCntlReq(directCntlReq),
+	.directCntlWEn(directCntlWEn),
+	.rst(rst),
+	.sendPacketCntl(sendPacketCntl),
+	.sendPacketData(sendPacketData),
+	.sendPacketGnt(sendPacketGnt),
+	.sendPacketReq(sendPacketReq),
+	.sendPacketWEn(sendPacketWEn) );	  
+
+
+slaveGetPacket u_slaveGetPacket
+  (.ACKRxed(ACKRxed), 
+  .CRCError(CRCError), 
+	.RXDataIn(RxData),
+	.RXDataValid(RxDataValid),
+	.RXFifoData(RxFifoData),
+	.RXFifoFull(RxFifoFull),
+	.RXFifoWEn(RxFifoWE),
+	.RXPacketRdy(getPacketRdy),
+	.RXStreamStatusIn(RxByteStatus),
+	.RxPID(RxPID),
+	.SIERxTimeOut(SIERxTimeOut),
+	.clk(clk),
+  .RXOverflow(RXOverflow), 
+  .RXTimeOut(RXTimeOut), 
+  .bitStuffError(bitStuffError), 
+  .dataSequence(dataSequence), 
+	.getPacketEn(getPacketREn),
+	.rst(rst) ); 
+
+slaveRxStatusMonitor	u_slaveRxStatusMonitor
+	(.connectStateIn(connectStateIn),
+	.connectStateOut(connectStateOut),
+	.resumeDetectedIn(resumeDetectedIn),
+	.resetEventOut(resetEventFromRxStatusMon),
+	.resumeIntOut(resumeIntFromRxStatusMon),
+	.clk(clk),
+	.rst(rst)  );    
+  
+fifoMux u_fifoMux (
+  .currEndP(currEndP),
+  //TxFifo
+  .TxFifoREn(TxFifoRE),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoData(TxFifoData),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEmpty(TxFifoEmpty),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  //RxFifo
+  .RxFifoWEn(RxFifoWE),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoFull(RxFifoFull),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+    );
+
+endmodule
+
+	
+	
+
+
+
+

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/css/lst.css
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/css/lst.css	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/css/lst.css	(revision 264)
@@ -0,0 +1,14 @@
+body   { background-color: silver; margin: 0 }
+#title { color: #000000; background-color: silver;
+         font-family: Arial; font-size: 10pt;
+         text-align: center; }
+#divider { background-color: #808080; }
+#value { color: #000000; background-color: #FFFFFF;
+         font-family: Arial; font-size: 10pt;
+         text-align: center }
+#time  { color: #000000; background-color: #FFFFDE;
+         font-family: Arial; font-size: 10pt;
+         text-align: right }
+#delta { color: #000000; background-color: #FFFFDE;
+         font-family: Arial; font-size: 10pt;
+         text-align: right }

Property changes on: common/components/usbhostslave/tags/start/doc/html/css/lst.css
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxBit.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxBit.asf	(revision 264)
@@ -0,0 +1,296 @@
+VERSION=1.19
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FREEOID=256
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/9/2004"
+HEADER_PARAM="TITLE,processRxBit"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
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+END
+INSTHEADER 227
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+L 7 6 0 TEXT "Labels" | 23239,210942 1 0 0 "prRxBit"
+F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,221539
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 94226,265828 1 0 0 "Module: processRxBit"
+L 8 9 0 TEXT "State Labels" | 42238,183458 1 0 0 "START\n/0/"
+S 9 6 0 ELLIPSE "States" | 42238,183458 6500 6500
+I 12 6 0 Builtin Reset | 22728,190398
+W 13 6 0 12 9 BEZIER "Transitions" | 22728,190398 27224,190134 31822,186104 35786,184244
+L 15 16 0 TEXT "State Labels" | 116068,123104 1 0 0 "IDLE"
+S 16 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116068,123104 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 18 17 8192 ELLIPSE "States" | 107950,139700 6500 6500
+L 19 18 0 TEXT "State Labels" | 107950,139700 1 0 0 "FIRST_BIT\n/1/"
+I 20 17 0 Builtin Entry | 56736,212076
+I 21 17 0 Builtin Exit | 128380,96970
+W 23 17 0 18 21 BEZIER "Transitions" | 111741,134422 116780,127404 120535,103988 125575,96970
+S 24 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116801,94499 6500 6500
+L 25 24 0 TEXT "State Labels" | 116801,94499 1 0 0 "DATA_RX"
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15330,15700 199830,263700
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 33 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118212,64680 6500 6500
+L 34 33 0 TEXT "State Labels" | 118212,64680 1 0 0 "RES_RX"
+W 35 41 0 40 37 BEZIER "Transitions" | 111741,134422 116780,127404 121695,118778 126735,111760
+W 36 41 0 38 40 BEZIER "Transitions" | 90251,167640 94982,160656 99574,152064 104305,145080
+I 37 41 0 Builtin Exit | 129540,111760
+I 38 41 0 Builtin Entry | 86360,167640
+L 39 40 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK\n/9/"
+S 40 41 65536 ELLIPSE "States" | 107950,139700 6500 6500
+S 42 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 119820,36808 6500 6500
+L 43 42 0 TEXT "State Labels" | 119820,36808 1 0 0 "RES_END"
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 51 6 0 213 16 BEZIER "Transitions" | 42388,154240 42522,148478 41966,137442 42502,133556\
+                                       43038,129670 44914,125650 53423,124511 61932,123372\
+                                       93489,123426 109569,123158
+W 52 6 0 213 24 BEZIER "Transitions" | 42699,154238 43235,140704 42636,114126 43641,106354\
+                                       44646,98582 47594,94562 55902,93624 64210,92686\
+                                       94494,92954 102132,93021 109770,93088 110325,93078\
+                                       110459,93078
+W 53 6 0 213 33 BEZIER "Transitions" | 42645,154234 43047,131722 42770,88800 43976,77142\
+                                       45182,65484 49202,63876 57711,63474 66220,63072\
+                                       96236,63072 103807,63072 111378,63072 111758,63165\
+                                       111892,63165
+W 54 6 0 213 42 BEZIER "Transitions" | 42671,154227 43609,125551 43842,70308 45115,54764\
+                                       46388,39220 49604,34396 58247,33391 66890,32386\
+                                       97657,35973 113335,36375
+C 55 51 0 TEXT "Conditions" | 46862,121215 1 0 0 "RXBitStMachCurrState == `IDLE_BIT_ST"
+C 56 52 0 TEXT "Conditions" | 48456,87658 1 0 0 "RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST"
+C 57 53 0 TEXT "Conditions" | 50070,58068 1 0 0 "RXBitStMachCurrState == `WAIT_RESUME_ST"
+C 58 54 0 TEXT "Conditions" | 37965,30092 1 0 0 "RXBitStMachCurrState == `RESUME_END_WAIT_ST"
+L 62 63 0 TEXT "State Labels" | 113723,160148 1 0 0 "WAIT_BITS\n/2/"
+S 63 6 24576 ELLIPSE "States" | 113456,158815 6500 6500
+W 64 6 0 9 63 BEZIER "Transitions" | 48724,183047 60291,181433 96001,163180 107568,161566
+W 65 6 0 63 213 BEZIER "Transitions" | 107011,157978 95175,155961 57808,160629 45972,158612
+C 66 65 0 TEXT "Conditions" | 64836,155511 1 0 0 "processRxBitsWEn == 1'b1"
+W 67 6 0 219 63 BEZIER "Transitions" | 168098,86660 172418,87740 183648,91372 185943,95422\
+                                       188238,99472 188778,113512 186145,122422 183513,131332\
+                                       167904,143587 159264,149864 150624,156142 133542,158851\
+                                       125779,159931 118017,161011 123617,159646 119837,160051
+W 68 6 0 16 219 BEZIER "Transitions" | 121312,119265 131167,111435 152206,96104 162061,88274
+W 69 6 0 24 219 BEZIER "Transitions" | 123174,93221 132840,90845 152243,88111 161207,86437
+W 71 6 0 33 219 BEZIER "Transitions" | 124072,67490 133252,71405 152285,80632 161465,84547
+W 72 6 0 42 219 BEZIER "Transitions" | 124182,41625 133497,51750 153075,73168 162390,83293
+A 73 18 4 TEXT "Actions" | 122746,145328 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;\nRXSameBitCount <= 4'h1;                          \nRXBitCount <= 4'h1;\noldRXBits <= RxBits;\n//zero is always the first RZ data bit of a new packet\nRXByte <= 8'h00;"
+L 74 75 0 TEXT "State Labels" | 77268,176778 1 0 0 "CHK_KBIT\n/3/"
+S 75 17 28672 ELLIPSE "States" | 77268,176778 6500 6500
+W 76 17 4096 241 18 BEZIER "Transitions" | 130017,172236 121274,163054 112530,153872 103787,144690
+A 78 65 16 TEXT "Actions" | 57414,163918 1 0 0 "RxBits <= RxBitsIn;\nprocessRxBitRdy <= 1'b0;"
+A 95 91 16 TEXT "Actions" | 81602,214284 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_STOP; //end of packet\nprocessRxByteWEn <= 1'b1;"
+W 94 32 0 85 89 BEZIER "Transitions" | 41504,245373 45564,238486 43946,239209 48006,232322
+W 91 32 4096 246 83 BEZIER "Transitions" | 118511,229192 108252,217383 97992,205574 87733,193765
+L 90 89 0 TEXT "State Labels" | 51785,227035 1 0 0 "CHK_SE0\n/5/"
+S 89 32 36864 ELLIPSE "States" | 51785,227035 6500 6500
+A 88 83 4 TEXT "Actions" | 104179,197041 1 0 0 "processRxByteWEn <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;"
+I 86 32 0 Builtin Exit | 178157,29567
+I 85 32 0 Builtin Entry | 37613,245373
+L 84 83 0 TEXT "State Labels" | 82467,189957 1 0 0 "LAST_BIT\n/4/"
+S 83 32 32768 ELLIPSE "States" | 82467,189957 6500 6500
+W 82 17 8194 75 21 BEZIER "Transitions" | 74719,170800 71529,161085 64380,142085 64960,133312\
+                                          65540,124540 74240,108880 82215,104385 90190,99890\
+                                          113975,98130 125575,96970
+W 81 17 0 20 75 BEZIER "Transitions" | 60627,212076 64687,205189 69782,189186 73842,182299
+A 80 76 16 TEXT "Actions" | 98161,161647 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_START; //start of packet\nprocessRxByteWEn <= 1'b1;"
+W 111 32 0 97 227 BEZIER "Transitions" | 66477,135648 66678,131226 66890,120750 67091,116328
+W 108 101 0 102 106 BEZIER "Transitions" | 122599,92427 127505,85589 132688,76607 137595,69768
+W 107 101 0 105 102 BEZIER "Transitions" | 101111,125648 105710,118844 110572,109896 115171,103091
+I 106 101 0 Builtin Exit | 140400,69768
+I 105 101 0 Builtin Entry | 97220,125648
+L 103 102 0 TEXT "State Labels" | 118810,97708 1 0 0 "DESTUFF\n/6/"
+S 102 101 45056 ELLIPSE "States" | 118810,97708 6500 6500
+H 101 97 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 99 89 4 TEXT "Actions" | 56907,247297 1 0 0 "bitStuffError <= 1'b0;"
+W 98 32 8194 89 97 BEZIER "Transitions" | 49942,220803 46756,202617 58189,166563 64651,148377
+S 97 32 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 66418,142124 6500 6500
+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
+H 122 113 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+                                            151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+                                        176540,156388 181096,131196 181431,113977 181766,96758\
+                                        182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit)                           //if current bit is a JBit, then\n  RXBitStMachCurrState <= `IDLE_BIT_ST;       //next state is idle\nelse                                          //else\nbegin\n  RXBitStMachCurrState <= `WAIT_RESUME_ST;    //check for resume\n  resumeWaitCnt <= 0;                          \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte;       \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 2 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 2 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit)  //line must leave KBit state for the end of resume\nbegin\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\n  resumeDetected <= 1'b0;   //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit)  //can only be a resume if line remains in Kbit state\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n  resumeWaitCnt <= resumeWaitCnt + 1'b1; \n  //if we've waited long enough, then\n  if (resumeWaitCnt == `RESUME_WAIT_TIME_MINUS1)\n  begin	\n    RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n    resumeDetected <= 1'b1;  //report resume detected\n  end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+                                         107061,21822 137747,20482 148467,20415 159187,20348\
+                                         171381,21420 174463,22458 177545,23497 178090,26035\
+                                         178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+                                         145117,36964 157043,31068 161599,29627 166155,28187\
+                                         172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 134636,218473 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 4'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 2 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 2 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 2 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 2 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 2 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 2 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 2 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 2 Builtin Signal | 78080,259259 "" ""
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[3:0]"
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 2 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 35548,248222 1 0 0 "if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n  RXSameBitCount <= RXSameBitCount + 1'b1;  //inc 'RXSameBitCount'\n  if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 7 there has been a bit stuff error\n    bitStuffError <= 1'b1;                         //flag 'bitStuffError'\n  else                                          //else no bit stuffing error\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;                   //early indication of ready\n	end\n    RXByte <= { 1'b1, RXByte[7:1]};              //RZ bit = 1 (ie no change in 'RxBits')\n  end\nend\nelse                                            //else current 'RxBits' are different from old 'RxBits'\nbegin\n  if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;	               //early indication of ready\n	end\n    RXByte <= {1'b0, RXByte[7:1]};             //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n  end\n  RXSameBitCount <= 4'h1;                      //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 127967,178402 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 127967,178402 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 111780,177768 121508,177678
+C 243 242 0 TEXT "Conditions" | 86880,174058 1 0 0 "RxBits == KBit"
+C 244 76 0 TEXT "Conditions" | 125584,169201 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processTxByte.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processTxByte.asf	(revision 264)
@@ -0,0 +1,215 @@
+VERSION=1.19
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FREEOID=1000
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/9/2004"
+HEADER_PARAM="TITLE,processTxByte"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 874
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 887
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 994
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+OBJECTS
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 824 0 2 Builtin OutPort | 15604,240596 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 822 0 2 Builtin InPort | 20959,250108 "" ""
+L 821 822 0 TEXT "Labels" | 26959,250108 1 0 0 "TxByteCtrlIn[7:0]"
+I 820 0 2 Builtin InPort | 20959,254515 "" ""
+L 819 820 0 TEXT "Labels" | 26959,254515 1 0 0 "TxByteIn[7:0]"
+I 818 0 2 Builtin OutPort | 18852,259388 "" ""
+L 817 818 0 TEXT "Labels" | 24852,259388 1 0 0 "processTxByteRdy"
+I 816 0 2 Builtin InPort | 20959,264028 "" ""
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 12 6 0 Builtin Reset | 22016,204762
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+I 847 0 2 Builtin InPort | 125241,221252 "" ""
+I 846 0 2 Builtin InPort | 125108,216932 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 844 0 2 Builtin Signal | 69660,223196 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+C 870 869 0 TEXT "Conditions" | 44743,165433 1 0 0 "processTxByteWEn == 1'b1"
+A 871 869 16 TEXT "Actions" | 40695,156023 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+L 873 874 0 TEXT "State Labels" | 48483,85161 1 0 0 "SEND_BYTE"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48483,85161 6500 6500
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 883 880 0 Builtin Entry | 38120,248040
+I 884 880 0 Builtin Exit | 178131,23271
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47391,100834 47973,91631
+W 897 6 0 874 887 BEZIER "Transitions" | 48237,78679 48703,71573 48867,58679 49333,51573
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+                                         25630,50244 23766,53274 22950,67894 22135,82515\
+                                         20737,137969 21261,153813 21785,169657 25281,177579\
+                                         27028,179792 28775,182006 32271,182938 33727,182355\
+                                         35183,181773 37321,179186 38486,177555
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+A 902 901 4 TEXT "Actions" | 75251,207304 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1)                      //If this bit is 1, then\n  TXOneCount <= TXOneCount + 1'b1;          //increment 'TXOneCount'\nelse                                        //else this is a zero bit\nbegin\n  TXOneCount <= 4'h1;                            //reset 'TXOneCount'\n  if (TXLineState == JBit) TXLineState <= KBit; //toggle the line state\n  else TXLineState <= JBit;\nend"
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == 4'h6"
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h1;                                //reset 'TXOneCount'\nif (TXLineState == JBit) TXLineState <= KBit;   //toggle the line state\nelse TXLineState <= JBit;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+                                              113354,23912 154429,23527 174909,23271
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+                                              40522,42856 31562,47464 29098,65320 26634,83176\
+                                              25738,149992 26858,168968 27978,187944 33354,197032\
+                                              36938,198888 40522,200744 49226,198568 51498,198152\
+                                              53770,197736 54409,198230 54473,198230
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 1;       \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+W 940 6 0 936 874 BEZIER "Transitions" | 142661,111545 128565,105371 68178,94636 54082,88462
+C 941 940 0 TEXT "Conditions" | 111729,100310 1 0 0 "USBWireGnt == 1'b1"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+W 944 895 0 948 942 BEZIER "Transitions" | 72730,212275 73358,204982 73632,189078 74260,181785
+C 945 944 0 TEXT "Conditions" | 73971,211371 1 0 0 "USBWireRdy == 1'b1"
+A 946 942 4 TEXT "Actions" | 93534,178039 1 0 0 "USBWireWEn <= 1'b0;"
+A 947 944 16 TEXT "Actions" | 69416,202253 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+W 958 895 0 942 956 BEZIER "Transitions" | 75377,168841 76005,161548 76957,146611 77585,139318
+A 959 958 16 TEXT "Actions" | 72304,159240 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 960 956 4 TEXT "Actions" | 96752,135563 1 0 0 "USBWireWEn <= 1'b0;"
+C 961 958 0 TEXT "Conditions" | 76516,167828 1 0 0 "USBWireRdy == 1'b1"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+W 964 895 0 956 962 BEZIER "Transitions" | 78681,126377 79309,119084 79833,97641 80461,90348
+A 965 964 16 TEXT "Actions" | 75410,113723 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+A 966 962 4 TEXT "Actions" | 99640,86596 1 0 0 "USBWireWEn <= 1'b0;"
+C 967 964 0 TEXT "Conditions" | 79852,125749 1 0 0 "USBWireRdy == 1'b1"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+W 970 895 0 962 968 BEZIER "Transitions" | 81334,77407 81962,70114 82544,57872 83172,50579
+A 971 970 16 TEXT "Actions" | 77621,69378 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+C 973 970 0 TEXT "Conditions" | 81643,77033 1 0 0 "USBWireRdy == 1'b1"
+I 974 895 0 Builtin Exit | 97904,23272
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+                                           90132,26172 93257,24084 94765,23272
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+                                              104561,139388 153745,139620 168013,138576 182281,137532\
+                                              190169,133124 192141,121582 194113,110040 194113,68280\
+                                              192025,55114 189937,41948 185529,28723 181353,23271
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+                                              41124,121640 36948,124424 36020,132602 35092,140780\
+                                              35556,170708 38166,179350 40776,187992 50140,192687\
+                                              55128,195007
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+                                              30972,218732 29812,212468 29638,189094 29464,165720\
+                                              29928,78488 31900,55230 33872,31972 41296,26172\
+                                              49358,24664 57420,23156 82353,23388 94765,23272
+I 977 895 0 Builtin Entry | 34452,259216
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+A 979 9 4 TEXT "Actions" | 108416,207754 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;"
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+I 981 0 2 Builtin Signal | 69434,227674 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 983 0 2 Builtin Signal | 69201,232334 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 985 0 2 Builtin Signal | 69201,236994 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 987 0 2 Builtin Signal | 69201,241421 "" ""
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 997 995 0 Builtin Exit | 129540,111760
+I 996 995 0 Builtin Entry | 86360,167640
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+L 815 816 0 TEXT "Labels" | 26959,264028 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/siereceiver.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/siereceiver.v	(revision 264)
@@ -0,0 +1,328 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\siereceiver.v
+// Generated   : 09/06/04 06:18:21
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\siereceiver.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (RxBitsOut, RxWireDataIn, RxWireDataWEn, SIERxRdyOut, clk, connectState, processRxBitRdyIn, processRxBitsWEn, rst);
+input   [1:0] RxWireDataIn;
+input   RxWireDataWEn;
+input   clk;
+input   processRxBitRdyIn;
+input   rst;
+output  [1:0] RxBitsOut;
+output  SIERxRdyOut;
+output  [1:0] connectState;
+output  processRxBitsWEn;
+
+reg     [1:0] RxBitsOut, next_RxBitsOut;
+wire    [1:0] RxWireDataIn;
+wire    RxWireDataWEn;
+reg     SIERxRdyOut, next_SIERxRdyOut;
+wire    clk;
+reg     [1:0] connectState, next_connectState;
+wire    processRxBitRdyIn;
+reg     processRxBitsWEn, next_processRxBitsWEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg  [7:0]RXWaitCount, next_RXWaitCount;
+reg  [1:0]RxBits, next_RxBits;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define LS_CONN_PROC_RX_BITS 4'b0110
+`define FS_CONN_CHK_RX_BITS1 4'b0111
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b1000
+`define WAIT_LS_DIS_PROC_RX_BITS 4'b1001
+`define WAIT_FS_DIS_PROC_RX_BITS2 4'b1010
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1011
+`define FS_CONN_PROC_RX_BITS1 4'b1100
+
+reg [3:0] CurrState_rcvr;
+reg [3:0] NextState_rcvr;
+
+
+//--------------------------------------------------------------------
+// Machine: rcvr
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or processRxBitRdyIn or SIERxRdyOut or connectState or RxBitsOut or processRxBitsWEn or CurrState_rcvr)
+begin : rcvr_NextState
+	NextState_rcvr <= CurrState_rcvr;
+	// Set default values for outputs and signals
+	next_RxBits <= RxBits;
+	next_SIERxRdyOut <= SIERxRdyOut;
+	next_RXStMachCurrState <= RXStMachCurrState;
+	next_RXWaitCount <= RXWaitCount;
+	next_connectState <= connectState;
+	next_RxBitsOut <= RxBitsOut;
+	next_processRxBitsWEn <= processRxBitsWEn;
+	case (CurrState_rcvr) // synopsys parallel_case full_case
+		`WAIT_BIT:
+			if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))	
+			begin
+				NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))	
+			begin
+				NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))	
+			begin
+				NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))	
+			begin
+				NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))	
+			begin
+				NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))	
+			begin
+				NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))	
+			begin
+				NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+				next_RxBits <= RxWireDataIn;
+				next_SIERxRdyOut <= 1'b0;
+			end
+		`START_SRX:
+		begin
+			next_RXStMachCurrState <= `DISCONNECT_ST;
+			next_RXWaitCount <= 8'h00;
+			next_connectState <= `DISCONNECT;
+			next_RxBits <= 2'b00;
+			next_RxBitsOut <= 2'b00;
+			next_processRxBitsWEn <= 1'b0;
+			next_SIERxRdyOut <= 1'b1;
+			NextState_rcvr <= `WAIT_BIT;
+		end
+		`DISCNCT_CHK_RXBITS:
+			if (RxBits == `ZERO_ONE)	
+			begin
+				NextState_rcvr <= `WAIT_BIT;
+				next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+				next_RXWaitCount <= 8'h00;
+				next_SIERxRdyOut <= 1'b1;
+			end
+			else if (RxBits == `ONE_ZERO)	
+			begin
+				NextState_rcvr <= `WAIT_BIT;
+				next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+				next_RXWaitCount <= 8'h00;
+				next_SIERxRdyOut <= 1'b1;
+			end
+			else
+			begin
+				NextState_rcvr <= `WAIT_BIT;
+				next_SIERxRdyOut <= 1'b1;
+			end
+		`WAIT_FS_CONN_CHK_RX_BITS:
+		begin
+			if (RxBits == `ONE_ZERO)
+			begin
+			  next_RXWaitCount <= RXWaitCount + 1'b1;
+			    if (RXWaitCount == `CONNECT_WAIT_TIME)
+			    begin
+			    next_connectState <= `FULL_SPEED_CONNECT;
+			    next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+			    end
+			end
+			else
+			begin
+			  next_RXStMachCurrState = `DISCONNECT_ST;
+			end
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`WAIT_LS_CONN_CHK_RX_BITS:
+		begin
+			if (RxBits == `ZERO_ONE)
+			begin
+			  next_RXWaitCount <= RXWaitCount + 1'b1;
+			    if (RXWaitCount == `CONNECT_WAIT_TIME)
+			    begin
+			    next_connectState <= `LOW_SPEED_CONNECT;
+			    next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+			    end
+			end
+			else
+			begin
+			  next_RXStMachCurrState = `DISCONNECT_ST;
+			end
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`LS_CONN_CHK_RX_BITS:
+			if (processRxBitRdyIn == 1'b1)	
+			begin
+				NextState_rcvr <= `LS_CONN_PROC_RX_BITS;
+				if (RxBits == `SE0)
+				begin
+				  next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+				  next_RXWaitCount <= 0;
+				end
+				next_processRxBitsWEn <= 1'b1;
+				next_RxBitsOut <= RxBits;
+			end
+		`LS_CONN_PROC_RX_BITS:
+		begin
+			next_processRxBitsWEn <= 1'b0;
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`FS_CONN_CHK_RX_BITS1:
+			if (processRxBitRdyIn == 1'b1)	
+			begin
+				NextState_rcvr <= `FS_CONN_PROC_RX_BITS1;
+				if (RxBits == `SE0)
+				begin
+				  next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+				  next_RXWaitCount <= 0;
+				end
+				next_processRxBitsWEn <= 1'b1;
+				next_RxBitsOut <= RxBits;
+				next_SIERxRdyOut <= 1'b1;
+				//early indication of ready
+			end
+		`FS_CONN_PROC_RX_BITS1:
+		begin
+			next_processRxBitsWEn <= 1'b0;
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`WAIT_LS_DIS_CHK_RX_BITS:
+			if (processRxBitRdyIn == 1'b1)	
+			begin
+				NextState_rcvr <= `WAIT_LS_DIS_PROC_RX_BITS;
+				if (RxBits == `SE0)
+				begin
+				  next_RXWaitCount <= RXWaitCount + 1'b1;
+				    if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+				    begin
+				    next_RXStMachCurrState <= `DISCONNECT_ST;
+				    next_connectState = `DISCONNECT;
+				    end
+				end
+				else
+				begin
+				  next_RXStMachCurrState = `CONNECT_LOW_SPEED_ST;
+				end
+				next_processRxBitsWEn <= 1'b1;
+			end
+		`WAIT_LS_DIS_PROC_RX_BITS:
+		begin
+			next_processRxBitsWEn <= 1'b0;
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`WAIT_FS_DIS_PROC_RX_BITS2:
+		begin
+			next_processRxBitsWEn <= 1'b0;
+			NextState_rcvr <= `WAIT_BIT;
+			next_SIERxRdyOut <= 1'b1;
+		end
+		`WAIT_FS_DIS_CHK_RX_BITS2:
+			if (processRxBitRdyIn == 1'b1)	
+			begin
+				NextState_rcvr <= `WAIT_FS_DIS_PROC_RX_BITS2;
+				if (RxBits == `SE0)
+				begin
+				  next_RXWaitCount <= RXWaitCount + 1'b1;
+				    if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+				    begin
+				    next_RXStMachCurrState <= `DISCONNECT_ST;
+				    next_connectState = `DISCONNECT;
+				    end
+				end
+				else
+				begin
+				  next_RXStMachCurrState = `CONNECT_FULL_SPEED_ST;
+				end
+				next_processRxBitsWEn <= 1'b1;
+			end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : rcvr_CurrentState
+	if (rst)	
+		CurrState_rcvr <= `START_SRX;
+	else
+		CurrState_rcvr <= NextState_rcvr;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : rcvr_RegOutput
+	if (rst)	
+	begin
+		RXStMachCurrState <= `DISCONNECT_ST;
+		RXWaitCount <= 8'h00;
+		RxBits <= 2'b00;
+		connectState <= `DISCONNECT;
+		RxBitsOut <= 2'b00;
+		processRxBitsWEn <= 1'b0;
+		SIERxRdyOut <= 1'b1;
+	end
+	else 
+	begin
+		RXStMachCurrState <= next_RXStMachCurrState;
+		RXWaitCount <= next_RXWaitCount;
+		RxBits <= next_RxBits;
+		connectState <= next_connectState;
+		RxBitsOut <= next_RxBitsOut;
+		processRxBitsWEn <= next_processRxBitsWEn;
+		SIERxRdyOut <= next_SIERxRdyOut;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(revision 264)
@@ -0,0 +1,108 @@
+VERSION=1.19
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBWireTxArbiter"
+FREEOID=128
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,USBWireTxArbiter"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
+F 6 0 671089152 59 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 106825,252275 1 0 0 "Module: USBWireTxArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
+W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
+W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
+W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 144675,143037 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0; \nUSBWireWEn <= 1'b0;\nTxBits <= 2'b00;\nTxCtl <= `TRI_STATE;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+C 62 21 0 TEXT "Conditions" | 105671,125880 1 0 0 "rst"
+W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
+                                      200193,83454 202194,93721 199799,97969 197405,102218\
+                                      189371,107780 182843,108050 176316,108321 158239,103840\
+                                      151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n  USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl)  \nbegin\n  if (muxSIENotPTXB  == 1'b1)  \n  begin\n    USBWireWEn <= SIETxWEn;\n    TxBits <= SIETxData;\n    TxCtl <= SIETxCtrl;\n  end\n  else\n  begin\n    USBWireWEn <= prcTxByteWEn;\n    TxBits <= prcTxByteData;\n    TxCtl <= prcTxByteCtrl;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+                                      70311,70629 71874,86691 76817,93064 81761,99437\
+                                      89642,107471 97173,106158 104705,104845 116882,95874\
+                                      123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 153906,181456 "" ""
+L 110 111 0 TEXT "Labels" | 159906,181456 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 156447,157894 "" ""
+L 108 109 0 TEXT "Labels" | 162447,157894 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 156216,186076 "" ""
+L 106 107 0 TEXT "Labels" | 162216,186076 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 154368,153274 "" ""
+L 104 105 0 TEXT "Labels" | 160368,153274 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 2 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 155985,199705 "" ""
+L 122 123 0 TEXT "Labels" | 161985,199705 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 155985,195316 "" ""
+L 120 121 0 TEXT "Labels" | 161985,195316 1 0 0 "prcTxByteCtrl"
+I 119 0 2 Builtin InPort | 155985,190696 "" ""
+L 118 119 0 TEXT "Labels" | 161985,190696 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 156447,171985 "" ""
+L 116 117 0 TEXT "Labels" | 162447,171985 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 156447,167596 "" ""
+L 114 115 0 TEXT "Labels" | 162447,167596 1 0 0 "SIETxCtrl"
+I 113 0 2 Builtin InPort | 156447,162745 "" ""
+L 112 113 0 TEXT "Labels" | 162447,162745 1 0 0 "SIETxData[1:0]"
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/endpMux.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/endpMux.v	(revision 264)
@@ -0,0 +1,265 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// endpMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: endpMux.v,v 1.1.1.1 2004-10-11 04:01:05 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbSlaveControl_h.v" 
+
+module endpMux (
+  clk, 
+  rst,
+  currEndP,
+  NAKSent,
+  stallSent,
+  CRCError,
+  bitStuffError,
+  RxOverflow,
+  RxTimeOut,
+  dataSequence,
+  ACKRxed,
+  transType,
+  transTypeNAK,
+  endPControlReg,
+  clrEPRdy,
+  endPMuxErrorsWEn,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  endP0StatusReg,
+  endP1StatusReg,
+  endP2StatusReg,
+  endP3StatusReg,
+  endP0TransTypeReg,
+  endP1TransTypeReg,
+  endP2TransTypeReg,
+  endP3TransTypeReg,
+  endP0NAKTransTypeReg,
+  endP1NAKTransTypeReg,
+  endP2NAKTransTypeReg,
+  endP3NAKTransTypeReg,
+  clrEP0Rdy,
+  clrEP1Rdy,
+  clrEP2Rdy,
+  clrEP3Rdy);
+
+
+input clk; 
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [3:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [3:0] endP0ControlReg;
+input [3:0] endP1ControlReg;
+input [3:0] endP2ControlReg;
+input [3:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk; 
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [3:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [3:0] endP0ControlReg;
+wire [3:0] endP1ControlReg;
+wire [3:0] endP2ControlReg;
+wire [3:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      endPControlReg <= endP0ControlReg;
+      clrEP0Rdy <= clrEPRdy;
+    end
+    2'b01: begin
+      endPControlReg <= endP1ControlReg;
+      clrEP1Rdy <= clrEPRdy;
+    end
+    2'b10: begin
+      endPControlReg <= endP2ControlReg;
+      clrEP2Rdy <= clrEPRdy;
+    end
+    2'b11: begin
+      endPControlReg <= endP3ControlReg;
+      clrEP3Rdy <= clrEPRdy;
+    end
+  endcase  
+end      
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+  if (rst) begin
+    endP0NAKTransTypeReg <= 2'b00;
+    endP1NAKTransTypeReg <= 2'b00;
+    endP2NAKTransTypeReg <= 2'b00;
+    endP3NAKTransTypeReg <= 2'b00;
+    endP0TransTypeReg <= 2'b00;
+    endP1TransTypeReg <= 2'b00;
+    endP2TransTypeReg <= 2'b00;
+    endP3TransTypeReg <= 2'b00;
+    endP0StatusReg <= 4'h0;
+    endP1StatusReg <= 4'h0;
+    endP2StatusReg <= 4'h0;
+    endP3StatusReg <= 4'h0;
+  end
+  else begin
+    if (endPMuxErrorsWEn == 1'b1) begin
+      if (NAKSent == 1'b1) begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0NAKTransTypeReg <= transTypeNAK;
+            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; 
+          end
+          2'b01: begin
+            endP1NAKTransTypeReg <= transTypeNAK;
+            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; 
+          end
+          2'b10: begin
+            endP2NAKTransTypeReg <= transTypeNAK;
+            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; 
+          end
+          2'b11: begin
+            endP3NAKTransTypeReg <= transTypeNAK;
+            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; 
+          end
+        endcase
+      end
+      else begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0TransTypeReg <= transType;
+            endP0StatusReg <= endPStatusCombine; 
+          end
+          2'b01: begin
+            endP1TransTypeReg <= transType;
+            endP1StatusReg <= endPStatusCombine; 
+          end
+          2'b10: begin
+            endP2TransTypeReg <= transType;
+            endP2StatusReg <= endPStatusCombine; 
+          end
+          2'b11: begin
+            endP3TransTypeReg <= transType;
+            endP3StatusReg <= endPStatusCombine; 
+          end
+        endcase
+      end
+    end
+  end
+end
+        
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/slaveDirectcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/slaveDirectcontrol.asf	(revision 264)
@@ -0,0 +1,132 @@
+VERSION=1.19
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FREEOID=180
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,3/20/2004"
+HEADER_PARAM="TITLE,slaveDirectControl"
+END
+BUNDLES
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+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
+INSTHEADER 78
+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
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+PAGE 0,0 215900,279400
+MARGINS 12700,12700 12700,12700
+END
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+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_SDC\n/0/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+I 13 6 0 Builtin Reset | 48900,215400
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+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
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+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "SCTxPortRdy == 1'b1"
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+A 177 174 16 TEXT "Actions" | 102262,47300 1 0 0 "SCTxPortReq <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/slaveRxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/slaveRxStatusMonitor.v	(revision 264)
@@ -0,0 +1,100 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveRxStatusMonitor.v                                       ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: slaveRxStatusMonitor.v,v 1.1.1.1 2004-10-11 04:01:09 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+	connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+	if (rst == 1'b1)
+	begin
+		oldConnectState <= connectStateIn;
+		oldResumeDetected <= resumeDetectedIn;
+	end
+	else
+	begin
+		oldConnectState <= connectStateIn;
+		oldResumeDetected <= resumeDetectedIn;
+		if (oldConnectState != connectStateIn)
+			resetEventOut <= 1'b1;
+		else
+			resetEventOut <= 1'b0;
+		if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+			resumeIntOut <= 1'b1;
+		else 
+			resumeIntOut <= 1'b0;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/slavecontroller.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/slavecontroller.v	(revision 264)
@@ -0,0 +1,406 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : 
+// Company     : 
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slavecontroller.v
+// Generated   : 09/22/04 06:01:23
+// From        : c:\projects\USBHostSlave\RTL\slaveController\slavecontroller.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (CRCError, NAKSent, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, SOFRxed, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBEndP, USBTgtAddress, bitStuffError, clk, clrEPRdy, endPMuxErrorsWEn, frameNum, getPacketREn, getPacketRdy, rst, sendPacketPID, sendPacketRdy, sendPacketWEn, stallSent, transDone);
+input   CRCError;
+input   [7:0] RxByte;
+input   RxDataWEn;
+input   RxOverflow;
+input   [7:0] RxStatus;
+input   RxTimeOut;
+input   SCGlobalEn;
+input   [3:0] USBEndPControlReg;
+input   [6:0] USBTgtAddress;
+input   bitStuffError;
+input   clk;
+input   getPacketRdy;
+input   rst;
+input   sendPacketRdy;
+output  NAKSent;
+output  SOFRxed;
+output  [1:0] USBEndPNakTransTypeReg;
+output  [1:0] USBEndPTransTypeReg;
+output  [3:0] USBEndP;
+output  clrEPRdy;
+output  endPMuxErrorsWEn;
+output  [10:0] frameNum;
+output  getPacketREn;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+output  stallSent;
+output  transDone;
+
+wire    CRCError;
+reg     NAKSent, next_NAKSent;
+wire    [7:0] RxByte;
+wire    RxDataWEn;
+wire    RxOverflow;
+wire    [7:0] RxStatus;
+wire    RxTimeOut;
+wire    SCGlobalEn;
+reg     SOFRxed, next_SOFRxed;
+wire    [3:0] USBEndPControlReg;
+reg     [1:0] USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg     [1:0] USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+reg     [3:0] USBEndP, next_USBEndP;
+wire    [6:0] USBTgtAddress;
+wire    bitStuffError;
+wire    clk;
+reg     clrEPRdy, next_clrEPRdy;
+reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg     [10:0] frameNum, next_frameNum;
+reg     getPacketREn, next_getPacketREn;
+wire    getPacketRdy;
+wire    rst;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     stallSent, next_stallSent;
+reg     transDone, next_transDone;
+
+// diagram signals declarations
+reg  [7:0]PIDByte, next_PIDByte;
+reg  [6:0]USBAddress, next_USBAddress;
+reg  [7:0]addrEndPTemp, next_addrEndPTemp;
+reg  [7:0]endpCRCTemp, next_endpCRCTemp;
+reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define IN_DATA 5'b01011
+`define IN_GET_RESP 5'b01100
+`define SETUP_OUT_CHK 5'b01101
+`define SETUP_OUT_SEND 5'b01110
+`define SETUP_OUT_GET_PKT 5'b01111
+`define START_S1 5'b10000
+`define GET_TOKEN_DELAY 5'b10001
+`define GET_TOKEN_CHK_ADDR 5'b10010
+
+reg [4:0] CurrState_slvCntrl;
+reg [4:0] NextState_slvCntrl;
+
+
+//--------------------------------------------------------------------
+// Machine: slvCntrl
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxByte or tempUSBEndPTransTypeReg or endpCRCTemp or addrEndPTemp or RxDataWEn or RxStatus or PIDByte or USBEndPControlReg or NAKSent or sendPacketRdy or getPacketRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or getPacketREn or USBEndPTransTypeReg or USBEndPNakTransTypeReg or sendPacketWEn or sendPacketPID or frameNum or CurrState_slvCntrl)
+begin : slvCntrl_NextState
+	NextState_slvCntrl <= CurrState_slvCntrl;
+	// Set default values for outputs and signals
+	next_stallSent <= stallSent;
+	next_NAKSent <= NAKSent;
+	next_SOFRxed <= SOFRxed;
+	next_PIDByte <= PIDByte;
+	next_transDone <= transDone;
+	next_clrEPRdy <= clrEPRdy;
+	next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+	next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+	next_getPacketREn <= getPacketREn;
+	next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+	next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+	next_sendPacketWEn <= sendPacketWEn;
+	next_sendPacketPID <= sendPacketPID;
+	next_endpCRCTemp <= endpCRCTemp;
+	next_addrEndPTemp <= addrEndPTemp;
+	next_frameNum <= frameNum;
+	next_USBAddress <= USBAddress;
+	next_USBEndP <= USBEndP;
+	case (CurrState_slvCntrl) // synopsys parallel_case full_case
+		`WAIT_RX1:
+		begin
+			next_stallSent <= 1'b0;
+			next_NAKSent <= 1'b0;
+			next_SOFRxed <= 1'b0;
+			if (RxDataWEn == 1'b1 && 
+				RxStatus == `RX_PACKET_START && 
+				RxByte[1:0] == `TOKEN)	
+			begin
+				NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+				next_PIDByte <= RxByte;
+			end
+		end
+		`FIN_SC:
+		begin
+			next_transDone <= 1'b0;
+			next_clrEPRdy <= 1'b0;
+			next_endPMuxErrorsWEn <= 1'b0;
+			NextState_slvCntrl <= `WAIT_RX1;
+		end
+		`CHK_PID:
+			if (PIDByte[3:0] == `SETUP)	
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+				next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+				next_getPacketREn <= 1'b1;
+			end
+			else if (PIDByte[3:0] == `OUT)	
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+				next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+				next_getPacketREn <= 1'b1;
+			end
+			else if (PIDByte[3:0] == `IN)	
+			begin
+				NextState_slvCntrl <= `IN_CHK_RDY;
+				next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+			end
+			else
+				NextState_slvCntrl <= `PID_ERROR;
+		`PID_ERROR:
+			NextState_slvCntrl <= `WAIT_RX1;
+		`CHK_RDY:
+			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1)	
+			begin
+				NextState_slvCntrl <= `FIN_SC;
+				next_transDone <= 1'b1;
+				next_clrEPRdy <= 1'b1;
+				next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+				next_endPMuxErrorsWEn <= 1'b1;
+			end
+			else if (NAKSent == 1'b1)	
+			begin
+				NextState_slvCntrl <= `FIN_SC;
+				next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+				next_endPMuxErrorsWEn <= 1'b1;
+			end
+			else
+				NextState_slvCntrl <= `FIN_SC;
+		`SETUP_OUT_CHK:
+			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)	
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_SEND;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `NAK;
+				next_NAKSent <= 1'b1;
+			end
+			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)	
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_SEND;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `STALL;
+				next_stallSent <= 1'b1;
+			end
+			else
+			begin
+				NextState_slvCntrl <= `SETUP_OUT_SEND;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `ACK;
+			end
+		`SETUP_OUT_SEND:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+				NextState_slvCntrl <= `CHK_RDY;
+		end
+		`SETUP_OUT_GET_PKT:
+		begin
+			next_getPacketREn <= 1'b0;
+			if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+				bitStuffError == 1'b0 &&
+				RxOverflow == 1'b0 &&
+				RxTimeOut == 1'b0))	
+				NextState_slvCntrl <= `SETUP_OUT_CHK;
+			else if (getPacketRdy == 1'b1)	
+				NextState_slvCntrl <= `CHK_RDY;
+		end
+		`IN_NAK_STALL:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+				NextState_slvCntrl <= `CHK_RDY;
+		end
+		`IN_CHK_RDY:
+			if (USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0)	
+			begin
+				NextState_slvCntrl <= `IN_NAK_STALL;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `NAK;
+				next_NAKSent <= 1'b1;
+			end
+			else if (USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1)	
+			begin
+				NextState_slvCntrl <= `IN_NAK_STALL;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `STALL;
+				next_stallSent <= 1'b1;
+			end
+			else if (USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)	
+			begin
+				NextState_slvCntrl <= `IN_DATA;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA0;
+			end
+			else
+			begin
+				NextState_slvCntrl <= `IN_DATA;
+				next_sendPacketWEn <= 1'b1;
+				next_sendPacketPID <= `DATA1;
+			end
+		`IN_DATA:
+		begin
+			next_sendPacketWEn <= 1'b0;
+			if (sendPacketRdy == 1'b1)	
+			begin
+				NextState_slvCntrl <= `IN_GET_RESP;
+				next_getPacketREn <= 1'b1;
+			end
+		end
+		`IN_GET_RESP:
+		begin
+			next_getPacketREn <= 1'b0;
+			if (getPacketRdy == 1'b1)	
+				NextState_slvCntrl <= `CHK_RDY;
+		end
+		`START_S1:
+			NextState_slvCntrl <= `WAIT_RX1;
+		`GET_TOKEN_WAIT_CRC:
+			if (RxDataWEn == 1'b1 && 
+				RxStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+				next_endpCRCTemp <= RxByte;
+			end
+			else if (RxDataWEn == 1'b1 && 
+				RxStatus != `RX_PACKET_STREAM)	
+				NextState_slvCntrl <= `WAIT_RX1;
+		`GET_TOKEN_WAIT_ADDR:
+			if (RxDataWEn == 1'b1 && 
+				RxStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+				next_addrEndPTemp <= RxByte;
+			end
+			else if (RxDataWEn == 1'b1 && 
+				RxStatus != `RX_PACKET_STREAM)	
+				NextState_slvCntrl <= `WAIT_RX1;
+		`GET_TOKEN_WAIT_STOP:
+			if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+				RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+				RxByte [`RX_OVERFLOW_BIT] == 1'b0))	
+				NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+			else if (RxDataWEn == 1'b1)	
+				NextState_slvCntrl <= `WAIT_RX1;
+		`GET_TOKEN_CHK_SOF:
+			if (PIDByte[3:0] == `SOF)	
+			begin
+				NextState_slvCntrl <= `WAIT_RX1;
+				next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+				next_SOFRxed <= 1'b1;
+			end
+			else
+			begin
+				NextState_slvCntrl <= `GET_TOKEN_DELAY;
+				next_USBAddress <= addrEndPTemp[6:0];
+				next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+			end
+		`GET_TOKEN_DELAY:		// Insert delay to allow USBEndPControlReg to update
+			NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+		`GET_TOKEN_CHK_ADDR:
+			if (USBEndP < `NUM_OF_ENDPOINTS  &&
+				USBAddress == USBTgtAddress &&
+				SCGlobalEn == 1'b1 &&
+				USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)	
+				NextState_slvCntrl <= `CHK_PID;
+			else
+				NextState_slvCntrl <= `WAIT_RX1;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_CurrentState
+	if (rst)	
+		CurrState_slvCntrl <= `START_S1;
+	else
+		CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_RegOutput
+	if (rst)	
+	begin
+		tempUSBEndPTransTypeReg <= 2'b00;
+		addrEndPTemp <= 8'h00;
+		endpCRCTemp <= 8'h00;
+		USBAddress <= 7'b0000000;
+		PIDByte <= 8'h00;
+		transDone <= 1'b0;
+		getPacketREn <= 1'b0;
+		sendPacketPID <= 4'b0;
+		sendPacketWEn <= 1'b0;
+		clrEPRdy <= 1'b0;
+		USBEndPTransTypeReg <= 2'b00;
+		USBEndPNakTransTypeReg <= 2'b00;
+		NAKSent <= 1'b0;
+		stallSent <= 1'b0;
+		SOFRxed <= 1'b0;
+		endPMuxErrorsWEn <= 1'b0;
+		frameNum <= 11'b00000000000;
+		USBEndP <= 4'h0;
+	end
+	else 
+	begin
+		tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+		addrEndPTemp <= next_addrEndPTemp;
+		endpCRCTemp <= next_endpCRCTemp;
+		USBAddress <= next_USBAddress;
+		PIDByte <= next_PIDByte;
+		transDone <= next_transDone;
+		getPacketREn <= next_getPacketREn;
+		sendPacketPID <= next_sendPacketPID;
+		sendPacketWEn <= next_sendPacketWEn;
+		clrEPRdy <= next_clrEPRdy;
+		USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+		USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+		NAKSent <= next_NAKSent;
+		stallSent <= next_stallSent;
+		SOFRxed <= next_SOFRxed;
+		endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+		frameNum <= next_frameNum;
+		USBEndP <= next_USBEndP;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/css/hde.css
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/css/hde.css	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/css/hde.css	(revision 264)
@@ -0,0 +1,13 @@
+body   { color: #000000; background-color: #FFFFFF }
+pre    { font-family: Courier New, monospace; font-size: 10pt; }
+#t_com { color: #008000; font-style: italic; }
+#t_kwd { color: #0000FF; }
+#t_cns { color: #848484; }
+#t_idt { }
+#t_msb { }
+#t_dir { color: #6B6D9C; }
+#t_sdt { font-weight: bold; }
+#t_sdv { }
+#t_sdf { }
+#t_sys { color: #6B6D9C; }
+

Property changes on: common/components/usbhostslave/tags/start/doc/html/css/hde.css
___________________________________________________________________
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+*
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Index: common/components/usbhostslave/tags/start/doc/html/images/bde/bar.gif
===================================================================
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Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/bar.gif
___________________________________________________________________
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+*
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+application/octet-stream
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Index: common/components/usbhostslave/tags/start/doc/html/images/bde/codeover.gif
===================================================================
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Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/codeover.gif
___________________________________________________________________
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+*
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## -0,0 +1 ##
+application/octet-stream
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Index: common/components/usbhostslave/tags/start/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/include/usbSlaveControl_h.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/include/usbSlaveControl_h.v	(revision 264)
@@ -0,0 +1,122 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSlaveControl_h.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+
+//endPointConstants 
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices 
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices 
+`define NAK_SET_MASK 8'h10
+//`define CRC_ERROR_BIT 0
+//`define BIT_STUFF_ERROR_BIT 1
+//`define RX_OVERFLOW_BIT 2
+//`define RX_TIME_OUT_BIT 3
+//`define NAK_SENT_BIT 4
+//`define STALL_SENT_BIT 5
+//`define ACK_RXED_BIT 6
+//`define DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices 
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+//SCMasterControlegIndices 
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+//SCinterruptRegIndices 
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+//TXTransactionTypes 
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts 
+`define SC_RX_PACKET_TOUT 18
+       

Property changes on: common/components/usbhostslave/tags/start/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/lineControlUpdate.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/lineControlUpdate.v	(revision 264)
@@ -0,0 +1,82 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// lineControlUpdate.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: lineControlUpdate.v,v 1.1.1.1 2004-10-11 04:00:57 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+    if (fullSpeedPolarity == 1'b1)
+	begin
+      JBit = `ONE_ZERO;
+      KBit = `ZERO_ONE;
+    end
+    else
+	begin
+      JBit = `ZERO_ONE;
+      KBit = `ONE_ZERO;
+    end
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxByte.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxByte.v	(revision 264)
@@ -0,0 +1,456 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\processRxByte.v
+// Generated   : 09/13/04 06:05:00
+// From        : c:\projects\USBHostSlave\RTL\serialInterfaceEngine\processRxByte.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC);
+input   [15:0] CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0] CRC5Result;
+input   CRC5UpdateRdy;
+input   [7:0] RxByteIn;
+input   [7:0] RxCtrlIn;
+input   clk;
+input   processRxDataInWEn;
+input   rst;
+output  CRC16En;
+output  CRC5En;
+output  CRC5_8Bit;
+output  [7:0] CRCData;
+output  [7:0] RxCtrlOut;
+output  RxDataOutWEn;
+output  [7:0] RxDataOut;
+output  processRxByteRdy;
+output  rstCRC;
+
+reg     CRC16En, next_CRC16En;
+wire    [15:0] CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5En, next_CRC5En;
+wire    [4:0] CRC5Result;
+wire    CRC5UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     [7:0] CRCData, next_CRCData;
+wire    [7:0] RxByteIn;
+wire    [7:0] RxCtrlIn;
+reg     [7:0] RxCtrlOut, next_RxCtrlOut;
+reg     RxDataOutWEn, next_RxDataOutWEn;
+reg     [7:0] RxDataOut, next_RxDataOut;
+wire    clk;
+reg     processRxByteRdy, next_processRxByteRdy;
+wire    processRxDataInWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+
+// diagram signals declarations
+reg ACKRxed, next_ACKRxed;
+reg CRCError, next_CRCError;
+reg NAKRxed, next_NAKRxed;
+reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg  [7:0]RxByte, next_RxByte;
+reg  [7:0]RxCtrl, next_RxCtrl;
+reg RxOverflow, next_RxOverflow;
+reg  [7:0]RxStatus;
+reg RxTimeOut, next_RxTimeOut;
+reg Signal1, next_Signal1;
+reg bitStuffError, next_bitStuffError;
+reg dataSequence, next_dataSequence;
+reg stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0] CurrState_prRxByte;
+reg [3:0] NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+always @
+(next_CRCError or next_bitStuffError or
+  next_RxOverflow or next_NAKRxed or
+  next_stallRxed or next_ACKRxed or
+  next_dataSequence)
+begin
+    RxStatus <=
+    {1'b0, next_dataSequence,
+    next_ACKRxed,
+    next_stallRxed, next_NAKRxed,
+    next_RxOverflow,
+    next_bitStuffError, next_CRCError };
+end
+
+
+//--------------------------------------------------------------------
+// Machine: prRxByte
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin : prRxByte_NextState
+	NextState_prRxByte <= CurrState_prRxByte;
+	// Set default values for outputs and signals
+	next_RxByte <= RxByte;
+	next_RxCtrl <= RxCtrl;
+	next_RXByteStMachCurrState <= RXByteStMachCurrState;
+	next_CRCError <= CRCError;
+	next_bitStuffError <= bitStuffError;
+	next_RxOverflow <= RxOverflow;
+	next_RxTimeOut <= RxTimeOut;
+	next_NAKRxed <= NAKRxed;
+	next_stallRxed <= stallRxed;
+	next_ACKRxed <= ACKRxed;
+	next_dataSequence <= dataSequence;
+	next_RxDataOut <= RxDataOut;
+	next_RxCtrlOut <= RxCtrlOut;
+	next_RxDataOutWEn <= RxDataOutWEn;
+	next_rstCRC <= rstCRC;
+	next_CRCData <= CRCData;
+	next_CRC5En <= CRC5En;
+	next_CRC5_8Bit <= CRC5_8Bit;
+	next_CRC16En <= CRC16En;
+	next_RXDataByteCnt <= RXDataByteCnt;
+	next_processRxByteRdy <= processRxByteRdy;
+	case (CurrState_prRxByte) // synopsys parallel_case full_case
+		`CHK_ST:
+			if (RXByteStMachCurrState == `HS_BYTE_ST)	
+				NextState_prRxByte <= `HSHAKE_CHK;
+			else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)	
+				NextState_prRxByte <= `TOKEN_WAIT_CRC;
+			else if (RXByteStMachCurrState == `DATA_BYTE_ST)	
+				NextState_prRxByte <= `DATA_WAIT_CRC;
+			else if (RXByteStMachCurrState == `IDLE_BYTE_ST)	
+				NextState_prRxByte <= `IDLE_CHK_START;
+			else if (RXByteStMachCurrState == `CHECK_SYNC_ST)	
+				NextState_prRxByte <= `CHK_SYNC_DO;
+			else if (RXByteStMachCurrState == `CHECK_PID_ST)	
+				NextState_prRxByte <= `CHK_PID_DO_CHK;
+		`START_PRBY:
+		begin
+			next_RxByte <= 8'h00;
+			next_RxCtrl <= 8'h00;
+			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			next_CRCError <= 1'b0;
+			next_bitStuffError <= 1'b0;
+			next_RxOverflow <= 1'b0;
+			next_RxTimeOut <= 1'b0;
+			next_NAKRxed <= 1'b0;
+			next_stallRxed <= 1'b0;
+			next_ACKRxed <= 1'b0;
+			next_dataSequence <= 1'b0;
+			next_RxDataOut <= 8'h00;
+			next_RxCtrlOut <= 8'h00;
+			next_RxDataOutWEn <= 1'b0;
+			next_rstCRC <= 1'b0;
+			next_CRCData <= 8'h00;
+			next_CRC5En <= 1'b0;
+			next_CRC5_8Bit <= 1'b0;
+			next_CRC16En <= 1'b0;
+			next_RXDataByteCnt <= 10'h00;
+			next_processRxByteRdy <= 1'b1;
+			NextState_prRxByte <= `WAIT_BYTE;
+		end
+		`WAIT_BYTE:
+			if (processRxDataInWEn == 1'b1)	
+			begin
+				NextState_prRxByte <= `CHK_ST;
+				next_RxByte <= RxByteIn;
+				next_RxCtrl <= RxCtrlIn;
+				next_processRxByteRdy <= 1'b0;
+			end
+		`HSHAKE_FIN:
+		begin
+			next_RxDataOutWEn <= 1'b0;
+			next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`HSHAKE_CHK:
+		begin
+			NextState_prRxByte <= `HSHAKE_FIN;
+			if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+			  next_RxOverflow <= 1'b1;
+			next_RxDataOut <= RxStatus;
+			next_RxCtrlOut <= `RX_PACKET_STOP;
+			next_RxDataOutWEn <= 1'b1;
+		end
+		`CHK_PID_DO_CHK:
+			if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)	
+			begin
+				NextState_prRxByte <= `WAIT_BYTE;
+				next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+				next_processRxByteRdy <= 1'b1;
+			end
+			else
+			begin
+				NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+				next_CRCError <= 1'b0;
+				next_bitStuffError <= 1'b0;
+				next_RxOverflow <= 1'b0;
+				next_NAKRxed <= 1'b0;
+				next_stallRxed <= 1'b0;
+				next_ACKRxed <= 1'b0;
+				next_dataSequence <= 1'b0;
+				next_RxTimeOut <= 1'b0;
+				next_RXDataByteCnt <= 0;
+				next_RxDataOut <= RxByte;
+				next_RxCtrlOut <= `RX_PACKET_START;
+				next_RxDataOutWEn <= 1'b1;
+				next_rstCRC <= 1'b1;
+			end
+		`CHK_PID_FIRST_BYTE_PROC:
+		begin
+			next_rstCRC <= 1'b0;
+			next_RxDataOutWEn <= 1'b0;
+			case (RxByte[1:0] )
+			    `SPECIAL:                              //Special PID.
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    `TOKEN:                                //Token PID
+			    begin
+			    next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+			    next_RXDataByteCnt <= 0;
+			    end
+			    `HANDSHAKE:                            //Handshake PID
+			    begin
+			        case (RxByte[3:2] )
+			            2'b00:
+			        next_ACKRxed <= 1'b1;
+			            2'b10:
+			        next_NAKRxed <= 1'b1;
+			            2'b11:
+			        next_stallRxed <= 1'b1;
+			            default:
+			            begin
+			                $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+			            end
+			        endcase
+			    next_RXByteStMachCurrState <= `HS_BYTE_ST;
+			    end
+			    `DATA:                                  //Data PID
+			    begin
+			        case (RxByte[3:2] )
+			            2'b00:
+			        next_dataSequence <= 1'b0;
+			            2'b10:
+			        next_dataSequence <= 1'b1;
+			            default:
+			                $display ("Invalid DATA PID detected in ProcessRXByte\n");
+			        endcase
+			    next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+			    next_RXDataByteCnt <= 0;
+			    end
+			endcase
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`DATA_FIN:
+		begin
+			next_CRC16En <= 1'b0;
+			next_RxDataOutWEn <= 1'b0;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`DATA_CHK_STRM:
+		begin
+			next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+			case (RxCtrl)
+			    `DATA_STOP:
+			    begin
+			        if (CRC16Result != 16'hb001)
+			      next_CRCError <= 1'b1;
+			    next_RxDataOut <= RxStatus;
+			    next_RxCtrlOut <= `RX_PACKET_STOP;
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    end
+			    `DATA_BIT_STUFF_ERROR:
+			    begin
+			    next_bitStuffError <= 1'b1;
+			    next_RxDataOut <= RxStatus;
+			    next_RxCtrlOut <= `RX_PACKET_STOP;
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    end
+			    `DATA_STREAM:
+			    begin
+			    next_RxDataOut <= RxByte;
+			    next_RxCtrlOut <= `RX_PACKET_STREAM;
+			    next_CRCData <= RxByte;
+			    next_CRC16En <= 1'b1;
+			    end
+			endcase
+			next_RxDataOutWEn <= 1'b1;
+			NextState_prRxByte <= `DATA_FIN;
+		end
+		`DATA_WAIT_CRC:
+			if (CRC16UpdateRdy == 1'b1)	
+				NextState_prRxByte <= `DATA_CHK_STRM;
+		`TOKEN_CHK_STRM:
+		begin
+			next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+			case (RxCtrl)
+			    `DATA_STOP:
+			    begin
+			        if (CRC5Result != 5'h6)
+			      next_CRCError <= 1'b1;
+			    next_RxDataOut <= RxStatus;
+			    next_RxCtrlOut <= `RX_PACKET_STOP;
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    end
+			    `DATA_BIT_STUFF_ERROR:
+			    begin
+			    next_bitStuffError <= 1'b1;
+			    next_RxDataOut <= RxStatus;
+			    next_RxCtrlOut <= `RX_PACKET_STOP;
+			    next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			    end
+			    `DATA_STREAM:
+			    begin
+			        if (RXDataByteCnt > 10'h2)
+			        begin
+			      next_RxOverflow <= 1'b1;
+			      next_RxDataOut <= RxStatus;
+			      next_RxCtrlOut <= `RX_PACKET_STOP;
+			      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+			        end
+			        else
+			        begin
+			      next_RxDataOut <= RxByte;
+			      next_RxCtrlOut <= `RX_PACKET_STREAM;
+			      next_CRCData <= RxByte;
+			      next_CRC5_8Bit <= 1'b1;
+			      next_CRC5En <= 1'b1;
+			        end
+			    end
+			endcase
+			next_RxDataOutWEn <= 1'b1;
+			NextState_prRxByte <= `TOKEN_FIN;
+		end
+		`TOKEN_FIN:
+		begin
+			next_CRC5En <= 1'b0;
+			next_RxDataOutWEn <= 1'b0;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`TOKEN_WAIT_CRC:
+			if (CRC5UpdateRdy == 1'b1)	
+				NextState_prRxByte <= `TOKEN_CHK_STRM;
+		`CHK_SYNC_DO:
+		begin
+			if (RxByte == `SYNC_BYTE)
+			  next_RXByteStMachCurrState = `CHECK_PID_ST;
+			else
+			  next_RXByteStMachCurrState = `IDLE_BYTE_ST;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+		`IDLE_CHK_START:
+		begin
+			if (RxCtrl == `DATA_START)
+			  next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+			NextState_prRxByte <= `WAIT_BYTE;
+			next_processRxByteRdy <= 1'b1;
+		end
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prRxByte_CurrentState
+	if (rst)	
+		CurrState_prRxByte <= `START_PRBY;
+	else
+		CurrState_prRxByte <= NextState_prRxByte;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prRxByte_RegOutput
+	if (rst)	
+	begin
+		RxByte <= 8'h00;
+		RxCtrl <= 8'h00;
+		RXByteStMachCurrState <= `IDLE_BYTE_ST;
+		CRCError <= 1'b0;
+		bitStuffError <= 1'b0;
+		RxOverflow <= 1'b0;
+		RxTimeOut <= 1'b0;
+		NAKRxed <= 1'b0;
+		stallRxed <= 1'b0;
+		ACKRxed <= 1'b0;
+		dataSequence <= 1'b0;
+		RXDataByteCnt <= 10'h00;
+		RxDataOut <= 8'h00;
+		RxCtrlOut <= 8'h00;
+		RxDataOutWEn <= 1'b0;
+		rstCRC <= 1'b0;
+		CRCData <= 8'h00;
+		CRC5En <= 1'b0;
+		CRC5_8Bit <= 1'b0;
+		CRC16En <= 1'b0;
+		processRxByteRdy <= 1'b1;
+	end
+	else 
+	begin
+		RxByte <= next_RxByte;
+		RxCtrl <= next_RxCtrl;
+		RXByteStMachCurrState <= next_RXByteStMachCurrState;
+		CRCError <= next_CRCError;
+		bitStuffError <= next_bitStuffError;
+		RxOverflow <= next_RxOverflow;
+		RxTimeOut <= next_RxTimeOut;
+		NAKRxed <= next_NAKRxed;
+		stallRxed <= next_stallRxed;
+		ACKRxed <= next_ACKRxed;
+		dataSequence <= next_dataSequence;
+		RXDataByteCnt <= next_RXDataByteCnt;
+		RxDataOut <= next_RxDataOut;
+		RxCtrlOut <= next_RxCtrlOut;
+		RxDataOutWEn <= next_RxDataOutWEn;
+		rstCRC <= next_rstCRC;
+		CRCData <= next_CRCData;
+		CRC5En <= next_CRC5En;
+		CRC5_8Bit <= next_CRC5_8Bit;
+		CRC16En <= next_CRC16En;
+		processRxByteRdy <= next_processRxByteRdy;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/siereceiver.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/siereceiver.asf	(revision 264)
@@ -0,0 +1,265 @@
+VERSION=1.19
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FREEOID=262
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,Steve"
+HEADER_PARAM="COMPANY,Base2Designs"
+HEADER_PARAM="CREATIONDATE,4/6/2004"
+HEADER_PARAM="TITLE,SIEReceiver"
+END
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+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
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+END
+INSTHEADER 1
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+W 15 6 0 11 241 BEZIER "Transitions" | 54697,186192 54895,182331 55070,163352 55268,159491
+W 14 6 0 9 11 BEZIER "Transitions" | 53793,212320 54090,208657 54044,202830 54341,199167
+S 11 6 16384 ELLIPSE "States" | 54795,192690 6500 6500
+L 10 11 0 TEXT "State Labels" | 54795,192690 1 0 0 "WAIT_BIT\n/4/"
+S 9 6 20480 ELLIPSE "States" | 54004,218793 6500 6500
+L 8 9 0 TEXT "State Labels" | 54004,218793 1 0 0 "START_SRX\n/5/"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,263700 1 0 0 "Module: SIEReceiver"
+F 6 0 671089152 228 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14253,12655 205887,234211
+L 7 6 0 TEXT "Labels" | 17253,231211 1 0 0 "rcvr"
+S 23 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 143681,32406 6500 6500
+L 22 23 0 TEXT "State Labels" | 143681,32406 1 0 0 "DISCNCT"
+A 21 15 16 TEXT "Actions" | 50061,176470 1 0 0 "RxBits <= RxWireDataIn;\nSIERxRdyOut <= 1'b0;"
+C 19 15 0 TEXT "Conditions" | 55867,186045 1 0 0 "RxWireDataWEn == 1'b1"
+W 17 6 0 16 9 BEZIER "Transitions" | 25106,221421 30781,219421 43306,224917 48981,222917
+I 16 6 0 Builtin Reset | 25106,221421
+H 39 23 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 40 39 12288 ELLIPSE "States" | 64508,213851 6500 6500
+L 41 40 0 TEXT "State Labels" | 64508,213851 1 0 0 "CHK_RXBITS\n/3/"
+I 42 39 0 Builtin Entry | 42918,241791
+I 43 39 0 Builtin Exit | 147281,109121
+W 44 39 0 42 40 BEZIER "Transitions" | 47426,241791 52025,234967 56275,226064 60875,219240
+S 46 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 142838,49983 6500 6500
+L 47 46 0 TEXT "State Labels" | 142838,49983 1 0 0 "WAIT_FS_CONN"
+H 54 46 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 48 54 4096 53 50 BEZIER "Transitions" | 111761,134435 116730,128048 137142,101490 142112,94624
+W 49 54 0 51 53 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 50 54 0 Builtin Exit | 145248,94624
+I 51 54 0 Builtin Entry | 86360,167640
+L 52 53 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/0/"
+S 53 54 0 ELLIPSE "States" | 107950,139700 6500 6500
+H 63 55 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 55 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 141452,68793 6500 6500
+L 56 55 0 TEXT "State Labels" | 141452,68793 1 0 0 "WAIT_LS_CONN"
+W 57 63 0 62 59 BEZIER "Transitions" | 111761,134435 116730,127570 121442,118626 126412,111760
+W 58 63 0 60 62 BEZIER "Transitions" | 90868,167640 95467,160816 99717,151913 104317,145089
+I 59 63 0 Builtin Exit | 129540,111760
+I 60 63 0 Builtin Entry | 86360,167640
+L 61 62 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_RX_BITS\n/1/"
+S 62 63 4096 ELLIPSE "States" | 107950,139700 6500 6500
+H 72 64 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 64 6 36868 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 140066,86613 6500 6500
+L 65 64 0 TEXT "State Labels" | 140066,86613 1 0 0 "LS_CONN"
+W 67 72 0 69 71 BEZIER "Transitions" | 69044,194920 73643,188096 77893,179193 82493,172369
+I 68 72 0 Builtin Exit | 131860,37310
+I 69 72 0 Builtin Entry | 64536,194920
+L 70 71 0 TEXT "State Labels" | 86126,166980 1 0 0 "CHK_RX_BITS\n/2/"
+S 71 72 8192 ELLIPSE "States" | 86126,166980 6500 6500
+S 73 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 139274,106215 6500 6500
+L 74 73 0 TEXT "State Labels" | 139274,106215 1 0 0 "FS_CONN"
+H 81 73 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 90 82 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 82 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 137888,126411 6500 6500
+L 83 82 0 TEXT "State Labels" | 137888,126411 1 0 0 "WAIT_LS_DIS"
+S 91 6 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 136700,148244 6500 6500
+L 92 91 0 TEXT "State Labels" | 136700,148244 1 0 0 "WAIT_FS_DIS"
+H 99 91 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 129 39 8194 40 43 BEZIER "Transitions" | 67288,207977 90867,158271 120574,158827 144153,109121
+W 130 39 8193 40 43 BEZIER "Transitions" | 69252,218293 110985,257468 165540,129446 150409,109121
+C 131 129 0 TEXT "Conditions" | 55856,199298 1 0 0 "RxBits == `ONE_ZERO"
+C 132 130 0 TEXT "Conditions" | 98621,230429 1 0 0 "RxBits == `ZERO_ONE"
+A 133 130 16 TEXT "Actions" | 102033,204788 1 0 0 "RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+A 134 129 16 TEXT "Actions" | 41551,160050 1 0 0 "RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST\nRXWaitCount <= 8'h00;"
+W 138 6 0 241 91 BEZIER "Transitions" | 55726,152526 55825,150740 55689,148412 56830,147271\
+                                        57971,146130 62339,145137 65812,144988 69286,144839\
+                                        125497,147159 130261,147357
+W 139 6 0 241 82 BEZIER "Transitions" | 54775,152569 53765,144812 51800,131524 53198,127807\
+                                        54597,124090 58369,121813 62636,121465 66904,121118\
+                                        125138,124972 131490,125269
+W 140 6 0 241 73 BEZIER "Transitions" | 54816,152562 53725,141843 49733,121615 49138,115313\
+                                        48543,109011 48344,105238 49038,103700 49733,102162\
+                                        52773,100254 56507,99743 60241,99232 74292,101683\
+                                        79033,101771 83774,101859 131499,104027 132998,104525
+W 141 6 0 241 64 BEZIER "Transitions" | 54966,152543 53478,134579 47748,100673 48939,91443\
+                                        50130,82213 57873,81220 62984,81170 68095,81121\
+                                        127305,85134 133657,85531
+W 142 6 0 241 55 BEZIER "Transitions" | 55084,152531 53397,129108 47947,83900 50081,72287\
+                                        52215,60675 60863,63077 65955,63276 71048,63475\
+                                        83004,63522 85042,64000 87080,64479 134402,67217\
+                                        135100,67416
+W 143 6 0 241 46 BEZIER "Transitions" | 54918,152546 51842,126940 43778,76555 43182,62859\
+                                        42587,49163 46360,45589 52513,44944 58666,44299\
+                                        125961,48736 136382,49232
+W 159 6 0 23 235 BEZIER "Transitions" | 148132,37141 151647,41428 158891,48733 161548,55421\
+                                        164206,62109 167707,83613 169507,92702
+W 158 6 0 46 235 BEZIER "Transitions" | 146210,55537 151355,64540 163238,84117 168383,93120
+W 157 6 0 55 235 BEZIER "Transitions" | 145872,73557 150759,78444 162584,89003 167471,93890
+W 155 6 0 64 235 BEZIER "Transitions" | 146100,89028 150732,91430 162771,94113 166713,95483
+W 154 6 0 73 235 BEZIER "Transitions" | 145399,104041 150201,102669 162025,98607 166827,97235
+W 153 6 0 82 235 BEZIER "Transitions" | 142566,121900 148139,116412 162016,104012 167589,98524
+W 152 6 0 91 235 BEZIER "Transitions" | 140515,142982 147718,132349 161212,109811 168415,99178
+C 151 138 0 TEXT "Conditions" | 53061,140339 1 0 0 "RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST"
+C 150 139 0 TEXT "Conditions" | 52495,119006 1 0 0 "RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST"
+C 149 140 0 TEXT "Conditions" | 50344,99146 1 0 0 "RXStMachCurrState == `CONNECT_FULL_SPEED_ST"
+C 148 141 0 TEXT "Conditions" | 51096,80093 1 0 0 "RXStMachCurrState == `CONNECT_LOW_SPEED_ST"
+C 147 142 0 TEXT "Conditions" | 46355,62337 1 0 0 "RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST"
+C 146 143 0 TEXT "Conditions" | 46100,43512 1 0 0 "RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST"
+W 144 6 0 241 23 BEZIER "Transitions" | 54917,152544 50947,121578 41893,61271 41744,45441\
+                                        41595,29611 48940,28220 55540,28071 62140,27923\
+                                        127685,31371 137213,31768
+C 145 144 0 TEXT "Conditions" | 62881,26704 1 0 0 "RXStMachCurrState == `DISCONNECT_ST"
+W 161 39 8195 40 43 BEZIER "Transitions" | 58578,211192 49548,206204 31147,197012 26632,187509\
+                                           22117,178006 22117,149970 33211,139263 44305,128556\
+                                           88681,113764 103817,110238 118953,106712 136069,108777\
+                                           144153,109121
+W 160 6 0 235 11 BEZIER "Transitions" | 171556,99342 175414,111175 187017,133454 187960,147988\
+                                        188903,162522 181196,168609 172535,178212 163875,187816\
+                                        140506,197413 125270,198727 110035,200042 80303,196085\
+                                        61192,193841
+A 165 62 4 TEXT "Actions" | 104545,213104 1 0 0 "if (RxBits == `ZERO_ONE)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `LOW_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+A 166 53 4 TEXT "Actions" | 101814,215348 1 0 0 "if (RxBits == `ONE_ZERO)\nbegin \n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `CONNECT_WAIT_TIME) \n  begin\n    connectState <= `FULL_SPEED_CONNECT;\n    RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `DISCONNECT_ST;\nend"
+L 167 168 0 TEXT "State Labels" | 102779,73959 1 0 0 "PROC_RX_BITS\n/6/"
+S 168 72 53248 ELLIPSE "States" | 102779,73959 6500 6500
+W 169 72 0 71 168 BEZIER "Transitions" | 86126,160480 86807,152989 100534,87755 101215,80264
+W 170 72 0 168 68 BEZIER "Transitions" | 106629,68724 112767,60967 122594,45067 128732,37310
+A 173 168 4 TEXT "Actions" | 121345,75637 1 0 0 "processRxBitsWEn <= 1'b0;"
+S 174 81 57344 ELLIPSE "States" | 85374,175380 6500 6500
+L 175 174 0 TEXT "State Labels" | 85374,175380 1 0 0 "CHK_RX_BITS1\n/7/"
+I 176 81 0 Builtin Entry | 63784,203320
+I 177 81 0 Builtin Exit | 137732,35774
+W 178 81 0 176 174 BEZIER "Transitions" | 67935,203320 72534,196496 77141,187593 81741,180769
+S 179 81 81920 ELLIPSE "States" | 108651,72423 6500 6500
+A 180 179 4 TEXT "Actions" | 127217,74101 1 0 0 "processRxBitsWEn <= 1'b0;"
+W 182 81 0 179 177 BEZIER "Transitions" | 112501,67188 118639,59431 128706,43531 134844,35774
+W 183 81 0 174 179 BEZIER "Transitions" | 85374,168880 86055,161389 106112,86141 106793,78650
+L 184 179 0 TEXT "State Labels" | 108651,72423 1 0 0 "PROC_RX_BITS1\n/12/"
+S 185 90 61440 ELLIPSE "States" | 81562,170615 6500 6500
+L 186 185 0 TEXT "State Labels" | 81562,170615 1 0 0 "CHK_RX_BITS\n/8/"
+I 187 90 0 Builtin Entry | 59972,198555
+I 188 90 0 Builtin Exit | 126468,30181
+W 189 90 0 187 185 BEZIER "Transitions" | 63495,198555 68094,191731 73329,182828 77929,176004
+S 190 90 65536 ELLIPSE "States" | 97387,66830 6500 6500
+A 191 190 4 TEXT "Actions" | 115953,68508 1 0 0 "processRxBitsWEn <= 1'b0;"
+W 193 90 0 190 188 BEZIER "Transitions" | 101237,61595 107375,53838 117590,37938 123728,30181
+W 194 90 0 185 190 BEZIER "Transitions" | 81562,164115 82243,156624 95324,80670 96005,73179
+L 195 190 0 TEXT "State Labels" | 97387,66830 1 0 0 "PROC_RX_BITS\n/9/"
+S 196 99 69632 ELLIPSE "States" | 91399,59215 6500 6500
+A 197 196 4 TEXT "Actions" | 109965,60893 1 0 0 "processRxBitsWEn <= 1'b0;"
+W 198 99 0 200 201 BEZIER "Transitions" | 57914,190526 62513,183702 67134,174799 71734,167975
+I 199 99 0 Builtin Exit | 120480,22566
+I 200 99 0 Builtin Entry | 53777,190526
+S 201 99 73728 ELLIPSE "States" | 75367,162586 6500 6500
+L 202 201 0 TEXT "State Labels" | 75367,162586 1 0 0 "CHK_RX_BITS2\n/11/"
+L 203 196 0 TEXT "State Labels" | 91399,59215 1 0 0 "PROC_RX_BITS2\n/10/"
+W 204 99 0 201 196 BEZIER "Transitions" | 75367,156086 76048,148595 89316,73050 89997,65559
+W 205 99 0 196 199 BEZIER "Transitions" | 95249,53980 101387,46223 111486,30323 117624,22566
+I 221 0 2 Builtin OutPort | 129743,241655 "" ""
+L 220 221 0 TEXT "Labels" | 135743,241655 1 0 0 "processRxBitsWEn"
+I 219 0 2 Builtin Signal | 20132,253454 "" ""
+L 218 219 0 TEXT "Labels" | 23132,253454 1 0 0 "RXWaitCount[7:0]"
+I 215 0 2 Builtin Signal | 20439,258880 "" ""
+L 214 215 0 TEXT "Labels" | 23439,258880 1 0 0 "RXStMachCurrState[3:0]"
+L 208 209 0 TEXT "Labels" | 83032,244882 1 0 0 "RxWireDataIn[1:0]"
+I 209 0 2 Builtin InPort | 77032,244882 "" ""
+L 212 213 0 TEXT "Labels" | 82921,240492 1 0 0 "RxWireDataWEn"
+I 213 0 2 Builtin InPort | 76921,240492 "" ""
+I 233 0 2 Builtin Signal | 19714,243194 "" ""
+L 232 233 0 TEXT "Labels" | 22714,243194 1 0 0 "RxBits[1:0]"
+C 231 17 0 TEXT "Conditions" | 33631,221484 1 0 0 "rst"
+L 230 229 0 TEXT "Labels" | 184517,256651 1 0 0 "rst"
+I 229 0 2 Builtin InPort | 178517,256651 "" ""
+I 228 0 3 Builtin InPort | 178182,263543 "" ""
+L 227 228 0 TEXT "Labels" | 184182,263543 1 0 0 "clk"
+A 226 9 4 TEXT "Actions" | 91342,231317 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;\nRxBitsOut <= 2'b00;\nprocessRxBitsWEn <= 1'b0;\nSIERxRdyOut <= 1'b1;"
+I 225 0 2 Builtin OutPort | 129743,246614 "" ""
+L 224 225 0 TEXT "Labels" | 135743,246614 1 0 0 "RxBitsOut[1:0]"
+L 234 235 0 TEXT "State Labels" | 170150,96140 1 0 0 "J1"
+S 235 6 77844 ELLIPSE "Junction" | 170150,96140 3500 3500
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 237 236 0 Builtin Entry | 86360,167640
+I 238 236 0 Builtin Exit | 129540,111760
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+A 255 194 16 TEXT "Actions" | 61406,142366 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_LOW_SPEED_ST;\nend\nprocessRxBitsWEn <= 1'b1;"
+C 254 194 0 TEXT "Conditions" | 81005,160052 1 0 0 "processRxBitRdyIn == 1'b1"
+C 253 204 0 TEXT "Conditions" | 76690,153596 1 0 0 "processRxBitRdyIn == 1'b1"
+A 252 204 16 TEXT "Actions" | 57026,138798 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState = `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState = `CONNECT_FULL_SPEED_ST;\nend\nprocessRxBitsWEn <= 1'b1;"
+A 250 160 16 TEXT "Actions" | 151210,187452 1 0 0 "SIERxRdyOut <= 1'b1;"
+I 249 0 2 Builtin OutPort | 74763,249425 "" ""
+L 248 249 0 TEXT "Labels" | 80763,249425 1 0 0 "SIERxRdyOut"
+I 247 0 2 Builtin InPort | 132223,251370 "" ""
+L 246 247 0 TEXT "Labels" | 138223,251370 1 0 0 "processRxBitRdyIn"
+L 240 241 0 TEXT "State Labels" | 55410,156008 1 0 0 "J2"
+S 241 6 81940 ELLIPSE "Junction" | 55410,156008 3500 3500
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 243 242 0 Builtin Entry | 86360,167640
+I 244 242 0 Builtin Exit | 129540,111760
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+A 259 169 16 TEXT "Actions" | 64097,138640 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend\nprocessRxBitsWEn <= 1'b1;\nRxBitsOut <= RxBits;"
+A 258 183 16 TEXT "Actions" | 78587,143608 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend\nprocessRxBitsWEn <= 1'b1;\nRxBitsOut <= RxBits;\nSIERxRdyOut <= 1'b1; //early indication of ready"
+C 257 169 0 TEXT "Conditions" | 57276,154345 1 0 0 "processRxBitRdyIn == 1'b1"
+C 256 183 0 TEXT "Conditions" | 63784,161795 1 0 0 "processRxBitRdyIn == 1'b1"
+L 260 261 0 TEXT "Labels" | 80654,253805 1 0 0 "connectState[1:0]"
+I 261 0 2 Builtin OutPort | 74654,253805 "" ""
+END

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(revision 264)
@@ -0,0 +1,375 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine.v                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: usbSerialInterfaceEngine.v,v 1.1.1.1 2004-10-11 04:01:04 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+module usbSerialInterfaceEngine(
+	clk, rst,
+	//readUSBWireData
+	USBWireDataIn,
+	USBWireDataInTick,
+	//writeUSBWireData
+	USBWireDataOut,
+	USBWireCtrlOut,
+	USBWireDataOutTick,
+	//SIEReceiver
+	connectState,
+	//processRxBit
+	resumeDetected,
+	//processRxByte
+	RxCtrlOut, 
+	RxDataOutWEn, 
+	RxDataOut, 
+    //SIETransmitter
+	SIEPortCtrlIn,
+	SIEPortDataIn, 
+	SIEPortTxRdy, 
+	SIEPortWEn, 
+    //lineControlUpdate
+	fullSpeedPolarity,
+	fullSpeedBitRate,
+  noActivityTimeOut
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output noActivityTimeOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut; 
+output RxDataOutWEn; 
+output [7:0] RxDataOut; 
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy; 
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut; 
+wire RxDataOutWEn; 
+wire [7:0] RxDataOut; 
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy; 
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire [1:0] RxBitsFromSIERxToPrRxBit;
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRxToSIERx;
+wire RxWireDataWEn;
+wire SIERxRdyOut;
+wire disableWireRead;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En; 
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En; 
+wire [4:0] RxCRC5Result; 
+wire RxCRC5_8Bit; 
+wire [7:0] RxCRCData; 
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En; 
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En; 
+wire [4:0] TxCRC5Result; 
+wire TxCRC5_8Bit; 
+wire [7:0] TxCRCData; 
+wire TxRstCRC; 
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy; 
+wire processTxByteWEn; 
+
+lineControlUpdate u_lineControlUpdate
+	(.fullSpeedPolarity(fullSpeedPolarity),
+	.fullSpeedBitRate(fullSpeedBitRate),
+	.JBit(JBit),
+	.KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+	(.RxBitsOut(RxBitsFromSIERxToPrRxBit),
+	.RxWireDataIn(RxWireDataFromWireRxToSIERx), 
+	.RxWireDataWEn(RxWireDataWEn), 
+	.SIERxRdyOut(SIERxRdyOut), 
+	.clk(clk),
+	.connectState(connectState),
+	.processRxBitRdyIn(processRxBitRdy), 
+	.processRxBitsWEn(processRxBitsWEn), 
+	.rst(rst) );
+	
+processRxBit u_processRxBit
+	(.JBit(JBit), 
+	.KBit(KBit), 
+	.RxBitsIn(RxBitsFromSIERxToPrRxBit), 
+	.RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), 
+	.RxDataOut(RxDataFromPrcRxBitToPrcRxByte), 
+	.clk(clk), 
+	.processRxBitRdy(processRxBitRdy), 
+	.processRxBitsWEn(processRxBitsWEn), 
+	.processRxByteWEn(processRxByteWEn), 
+	.resumeDetected(resumeDetected), 
+	.rst(rst),
+  .processRxByteRdy(processRxByteRdy) );
+	
+processRxByte u_processRxByte
+	(.CRC16En(RxCRC16En), 
+	.CRC16Result(RxCRC16Result), 
+  .CRC16UpdateRdy(RxCRC16UpdateRdy),
+	.CRC5En(RxCRC5En), 
+	.CRC5Result(RxCRC5Result), 
+	.CRC5_8Bit(RxCRC5_8Bit),
+  .CRC5UpdateRdy(RxCRC5UpdateRdy),
+	.CRCData(RxCRCData), 
+	.RxByteIn(RxDataFromPrcRxBitToPrcRxByte), 
+	.RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), 
+	.RxCtrlOut(RxCtrlOut), 
+	.RxDataOutWEn(RxDataOutWEn), 
+	.RxDataOut(RxDataOut), 
+	.clk(clk), 
+	.processRxDataInWEn(processRxByteWEn), 
+	.rst(rst), 
+	.rstCRC(RxRstCRC),
+  .processRxByteRdy(processRxByteRdy) ); 
+	
+	
+updateCRC5 RxUpdateCRC5
+	(.rstCRC(RxRstCRC), 
+	.CRCResult(RxCRC5Result), 
+	.CRCEn(RxCRC5En), 
+	.CRC5_8BitIn(RxCRC5_8Bit), 
+	.dataIn(RxCRCData), 
+  .ready(RxCRC5UpdateRdy),
+	.clk(clk), 
+	.rst(rst) );  
+	
+updateCRC16 RxUpdateCRC16
+	(.rstCRC(RxRstCRC), 
+	.CRCResult(RxCRC16Result), 
+	.CRCEn(RxCRC16En), 
+	.dataIn(RxCRCData), 
+  .ready(RxCRC16UpdateRdy),
+	.clk(clk), 
+	.rst(rst) );	
+	
+SIETransmitter u_SIETransmitter
+	(.CRC16En(TxCRC16En), 
+	.CRC16Result(TxCRC16Result), 
+	.CRC5En(TxCRC5En), 
+	.CRC5Result(TxCRC5Result), 
+	.CRC5_8Bit(TxCRC5_8Bit), 
+	.CRCData(TxCRCData),
+  .CRC5UpdateRdy(TxCRC5UpdateRdy),
+  .CRC16UpdateRdy(TxCRC16UpdateRdy),
+	.JBit(JBit), 
+	.KBit(KBit), 
+	.SIEPortCtrlIn(SIEPortCtrlIn),
+	.SIEPortDataIn(SIEPortDataIn), 
+	.SIEPortTxRdy(SIEPortTxRdy), 
+	.SIEPortWEn(SIEPortWEn), 
+	.TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), 
+	.TxByteOut(TxByteFromSIEToPrcTxByte), 
+	.USBWireCtrl(SIETxCtrl), 
+	.USBWireData(SIETxData), 
+	.USBWireGnt(SIETxGnt), 
+	.USBWireRdy(USBWireReadyFromTxArb), 
+	.USBWireReq(SIETxReq), 
+	.USBWireWEn(SIETxWEn), 
+	.clk(clk), 
+	.processTxByteRdy(processTxByteRdy), 
+	.processTxByteWEn(processTxByteWEn), 
+	.rst(rst), 
+	.rstCRC(TxRstCRC) );	  
+
+updateCRC5 TxUpdateCRC5
+	(.rstCRC(TxRstCRC), 
+	.CRCResult(TxCRC5Result), 
+	.CRCEn(TxCRC5En), 
+	.CRC5_8BitIn(TxCRC5_8Bit), 
+	.dataIn(TxCRCData),
+  .ready(TxCRC5UpdateRdy),
+	.clk(clk), 
+	.rst(rst) );  
+	
+updateCRC16 TxUpdateCRC16
+	(.rstCRC(TxRstCRC), 
+	.CRCResult(TxCRC16Result), 
+	.CRCEn(TxCRC16En), 
+	.dataIn(TxCRCData), 
+  .ready(TxCRC16UpdateRdy),
+	.clk(clk), 
+	.rst(rst) );	
+
+processTxByte u_processTxByte
+	(.JBit(JBit), 
+	.KBit(KBit), 
+	.TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), 
+	.TxByteIn(TxByteFromSIEToPrcTxByte), 
+	.USBWireCtrl(prcTxByteCtrl), 
+	.USBWireData(prcTxByteData), 
+	.USBWireGnt(prcTxByteGnt), 
+	.USBWireRdy(USBWireReadyFromTxArb), 
+	.USBWireReq(prcTxByteReq), 
+	.USBWireWEn(prcTxByteWEn), 
+	.clk(clk), 
+	.processTxByteRdy(processTxByteRdy), 
+	.processTxByteWEn(processTxByteWEn), 
+	.rst(rst) ); 
+	
+USBWireTxArbiter u_USBWireTxArbiter
+	(.SIETxCtrl(SIETxCtrl), 
+	.SIETxData(SIETxData), 
+	.SIETxGnt(SIETxGnt), 
+	.SIETxReq(SIETxReq), 
+	.SIETxWEn(SIETxWEn), 
+	.TxBits(TxBitsFromArbToWire), 
+	.TxCtl(TxCtrlFromArbToWire), 
+	.USBWireRdyIn(USBWireRdy), 
+	.USBWireRdyOut(USBWireReadyFromTxArb), 
+	.USBWireWEn(USBWireWEn),
+	.clk(clk), 
+	.prcTxByteCtrl(prcTxByteCtrl), 
+	.prcTxByteData(prcTxByteData), 
+	.prcTxByteGnt(prcTxByteGnt), 
+	.prcTxByteReq(prcTxByteReq), 
+	.prcTxByteWEn(prcTxByteWEn), 
+	.rst(rst) ); 
+	
+writeUSBWireData u_writeUSBWireData
+	(.TxBitsIn(TxBitsFromArbToWire), 
+	.TxBitsOut(USBWireDataOut), 
+	.TxDataOutTick(USBWireDataOutTick),
+	.TxCtrlIn(TxCtrlFromArbToWire), 
+	.TxCtrlOut(USBWireCtrlOut), 
+	.USBWireRdy(USBWireRdy), 
+	.USBWireWEn(USBWireWEn),
+	.disableWireReadOut(disableWireRead),
+	.fullSpeedRate(fullSpeedBitRate), 
+	.clk(clk),
+	.rst(rst),
+  .noActivityTimeOut(noActivityTimeOut) );  
+	
+readUSBWireData u_readUSBWireData
+	(.RxBitsIn(USBWireDataIn), 
+	.RxDataInTick(USBWireDataInTick),
+	.RxBitsOut(RxWireDataFromWireRxToSIERx), 
+	.SIERxRdyIn(SIERxRdyOut), 
+	.SIERxWEn(RxWireDataWEn), 
+	.fullSpeedRate(fullSpeedBitRate), 
+	.disableWireRead(disableWireRead),
+	.clk(clk),
+	.rst(rst) );
+
+
+endmodule
+
+	
+	
+
+
+
+

Property changes on: common/components/usbhostslave/tags/start/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/USBSlaveControlBI.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/USBSlaveControlBI.v	(revision 264)
@@ -0,0 +1,394 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBSlaveControlBI.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// $Id: USBSlaveControlBI.v,v 1.1.1.1 2004-10-11 04:01:10 sfielding Exp $
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`include "usbSlaveControl_h.v"
+ 
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  clk, rst,
+	SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut,
+  endP0TransTypeReg, endP0NAKTransTypeReg,
+  endP1TransTypeReg, endP1NAKTransTypeReg,
+  endP2TransTypeReg, endP2NAKTransTypeReg,
+  endP3TransTypeReg, endP3NAKTransTypeReg,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  EP0StatusReg,
+  EP1StatusReg,
+  EP2StatusReg,
+  EP3StatusReg,
+  SCAddrReg, frameNum,
+	connectStateIn,
+	SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+  slaveControlSelect,
+  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  SCGlobalEn
+  );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input clk;
+input rst;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg; 
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg; 
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg; 
+input [1:0] endP3NAKTransTypeReg;
+output [3:0] endP0ControlReg;
+output [3:0] endP1ControlReg;
+output [3:0] endP2ControlReg;
+output [3:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire clk;
+wire rst;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg; 
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg; 
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg; 
+wire [1:0] endP3NAKTransTypeReg;
+reg [3:0] endP0ControlReg;
+reg [3:0] endP1ControlReg;
+reg [3:0] endP2ControlReg;
+reg [3:0] endP3ControlReg;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg LineDirectControlEn;
+reg fullSpeedPol; 
+reg fullSpeedRate;
+reg SCGlobalEn;
+
+//internal wire and regs
+reg [5:0] SCControlReg;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg NAKSentInt;
+reg [4:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+
+
+//sync write demux
+always @(posedge clk)
+begin
+	clrNAKReq <= 1'b0;
+  clrSOFReq <= 1'b0;
+  clrResetReq <= 1'b0;
+  clrResInReq <= 1'b0;
+  clrTransDoneReq <= 1'b0;
+  EP0SetReady <= 1'b0;
+  EP1SetReady <= 1'b0;
+  EP2SetReady <= 1'b0;
+  EP3SetReady <= 1'b0;
+	if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+	begin
+		case (address)
+      `EP0_CTRL_REG : begin
+        EP0SendStall <= dataIn[3];
+        EP0DataSequence <= dataIn[2];
+        EP0SetReady <= dataIn[1];
+        EP0Enable <= dataIn[0];
+      end
+      `EP1_CTRL_REG : begin
+        EP1SendStall <= dataIn[3];
+        EP1DataSequence <= dataIn[2];
+        EP1SetReady <= dataIn[1];
+        EP1Enable <= dataIn[0];
+      end
+      `EP2_CTRL_REG : begin
+        EP2SendStall <= dataIn[3];
+        EP2DataSequence <= dataIn[2];
+        EP2SetReady <= dataIn[1];
+        EP2Enable <= dataIn[0];
+      end
+      `EP3_CTRL_REG : begin
+        EP3SendStall <= dataIn[3];
+        EP3DataSequence <= dataIn[2];
+        EP3SetReady <= dataIn[1];
+        EP3Enable <= dataIn[0];
+      end
+			`SC_CONTROL_REG : SCControlReg <= dataIn[5:0];
+			`SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+			`SC_INTERRUPT_STATUS_REG : begin
+        clrNAKReq <= dataIn[4];
+        clrSOFReq <= dataIn[3];
+        clrResetReq <= dataIn[2];
+        clrResInReq <= dataIn[1];
+        clrTransDoneReq <= dataIn[0];
+      end
+			`SC_INTERRUPT_MASK_REG	: interruptMaskReg <= dataIn[4:0];
+		endcase
+	end
+end
+
+//interrupt control 
+always @(posedge clk)
+begin
+	if (NAKSentIn == 1'b1)
+		NAKSentInt <= 1'b1;
+	else if (clrNAKReq == 1'b1)
+		NAKSentInt <= 1'b0; 
+    
+	if (SOFRxedIn == 1'b1)
+		SOFRxedInt <= 1'b1;
+	else if (clrSOFReq == 1'b1)
+		SOFRxedInt <= 1'b0;
+		
+	if (resetEventIn == 1'b1)
+		resetEventInt <= 1'b1;
+	else if (clrResetReq == 1'b1)
+		resetEventInt <= 1'b0;
+		
+	if (resumeIntIn == 1'b1)
+		resumeInt <= 1'b1;
+	else if (clrResInReq == 1'b1)
+		resumeInt <= 1'b0;	
+
+	if (transDoneIn == 1'b1)
+		transDoneInt <= 1'b1;
+	else if (clrTransDoneReq == 1'b1)
+		transDoneInt <= 1'b0;
+end
+
+//mask interrupts
+always @(interruptMaskReg or transDoneInt or resumeInt or resetEventInt or SOFRxedInt or NAKSentInt) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+end  
+
+//end point ready, set/clear
+always @(posedge clk)
+begin
+	if (EP0SetReady == 1'b1)
+		EP0Ready <= 1'b1;
+	else if (clrEP0Ready == 1'b1)
+		EP0Ready <= 1'b0;
+    
+	if (EP1SetReady == 1'b1)
+		EP1Ready <= 1'b1;
+	else if (clrEP1Ready == 1'b1)
+		EP1Ready <= 1'b0;
+    
+	if (EP2SetReady == 1'b1)
+		EP2Ready <= 1'b1;
+	else if (clrEP2Ready == 1'b1)
+		EP2Ready <= 1'b0;
+    
+	if (EP3SetReady == 1'b1)
+		EP3Ready <= 1'b1;
+	else if (clrEP3Ready == 1'b1)
+		EP3Ready <= 1'b0;
+end  
+  
+//break out control signals
+always @(SCControlReg) begin
+  SCGlobalEn <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+  TxLineState <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+  LineDirectControlEn <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+  fullSpeedPol <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRate <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+end
+
+//combine endpoint control signals 
+always @(EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable) 
+begin
+  endP0ControlReg <= {EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+  endP1ControlReg <= {EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+  endP2ControlReg <= {EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+  endP3ControlReg <= {EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+      
+      
+      // async read mux
+always @(address or
+  EP0SendStall or EP0Ready or EP0DataSequence or EP0Enable or
+  EP1SendStall or EP1Ready or EP1DataSequence or EP1Enable or
+  EP2SendStall or EP2Ready or EP2DataSequence or EP2Enable or
+  EP3SendStall or EP3Ready or EP3DataSequence or EP3Enable or
+  EP0StatusReg or EP1StatusReg or EP2StatusReg or EP3StatusReg or
+  endP0ControlReg or endP1ControlReg or endP2ControlReg or endP3ControlReg or
+  endP0NAKTransTypeReg or endP1NAKTransTypeReg or endP2NAKTransTypeReg or endP3NAKTransTypeReg or 
+  endP0TransTypeReg or endP1TransTypeReg or endP2TransTypeReg or endP3TransTypeReg or
+  SCControlReg or connectStateIn or
+  NAKSentInt or SOFRxedInt or resetEventInt or resumeInt or transDoneInt or
+  interruptMaskReg or SCAddrReg or frameNum)
+begin
+	case (address)
+      `EP0_CTRL_REG : dataOut <= endP0ControlReg;
+      `EP0_STS_REG : dataOut <= EP0StatusReg;
+      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeReg;
+      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeReg;
+      `EP1_CTRL_REG : dataOut <= endP1ControlReg;
+      `EP1_STS_REG :  dataOut <= EP1StatusReg;
+      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeReg;
+      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeReg;
+      `EP2_CTRL_REG : dataOut <= endP2ControlReg;
+      `EP2_STS_REG :  dataOut <= EP2StatusReg;
+      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeReg;
+      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeReg;
+      `EP3_CTRL_REG : dataOut <= endP3ControlReg;
+      `EP3_STS_REG :  dataOut <= EP3StatusReg;
+      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeReg;
+      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeReg;
+  		`SC_CONTROL_REG : dataOut <= SCControlReg;
+			`SC_LINE_STATUS_REG : dataOut <= {6'b000000, connectStateIn}; 
+			`SC_INTERRUPT_STATUS_REG :	dataOut <= {3'b000, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+			`SC_INTERRUPT_MASK_REG	: dataOut <= {3'b000, interruptMaskReg};
+			`SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+			`SC_FRAME_NUM_MSP : dataOut <= frameNum[10:3];
+			`SC_FRAME_NUM_LSP : dataOut <= {5'b00000, frameNum[2:0]};
+      default: dataOut <= 8'h00;
+	endcase
+end
+
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/sctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/sctxportarbiter.v	(revision 264)
@@ -0,0 +1,173 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\sctxportarbiter.v
+// Generated   : 06/10/04 22:29:55
+// From        : c:\projects\USBHostSlave\RTL\slaveController\sctxportarbiter.asf
+// By          : FSM2VHDL ver. 4.0.3.8
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`timescale 1ns / 1ps
+
+module SCTxPortArbiter (SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   SCTxPortRdyIn;
+input   clk;
+input   [7:0] directCntlCntl;
+input   [7:0] directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0] sendPacketCntl;
+input   [7:0] sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortRdyOut;
+output  SCTxPortWEnable;
+output  directCntlGnt;
+output  sendPacketGnt;
+
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortRdyIn;
+reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg     SCTxPortWEnable, next_SCTxPortWEnable;
+wire    clk;
+wire    [7:0] directCntlCntl;
+wire    [7:0] directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+wire    [7:0] sendPacketCntl;
+wire    [7:0] sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0] CurrState_SCTxArb;
+reg [1:0] NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+    SCTxPortRdyOut = SCTxPortRdyIn;
+end
+always @(muxDCEn or
+		 		 directCntlWEn or directCntlData or directCntlCntl or
+                  directCntlWEn or directCntlData or directCntlCntl or
+ 		  		 sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+    begin
+        SCTxPortWEnable <= directCntlWEn;
+        SCTxPortData <= directCntlData;
+        SCTxPortCntl <= directCntlCntl;
+    end
+else
+    begin
+        SCTxPortWEnable <= sendPacketWEn;
+        SCTxPortData <= sendPacketData;
+        SCTxPortCntl <= sendPacketCntl;
+    end
+end
+
+
+//--------------------------------------------------------------------
+// Machine: SCTxArb
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin : SCTxArb_NextState
+	NextState_SCTxArb <= CurrState_SCTxArb;
+	// Set default values for outputs and signals
+	next_sendPacketGnt <= sendPacketGnt;
+	next_muxDCEn <= muxDCEn;
+	next_directCntlGnt <= directCntlGnt;
+	case (CurrState_SCTxArb) // synopsys parallel_case full_case
+		`SARB1_WAIT_REQ:
+			if (sendPacketReq == 1'b1)	
+			begin
+				NextState_SCTxArb <= `SARB_SEND_PACKET;
+				next_sendPacketGnt <= 1'b1;
+				next_muxDCEn <= 1'b0;
+			end
+			else if (directCntlReq == 1'b1)	
+			begin
+				NextState_SCTxArb <= `SARB_DC;
+				next_directCntlGnt <= 1'b1;
+				next_muxDCEn <= 1'b1;
+			end
+		`SARB_SEND_PACKET:
+			if (sendPacketReq == 1'b0)	
+			begin
+				NextState_SCTxArb <= `SARB1_WAIT_REQ;
+				next_sendPacketGnt <= 1'b0;
+			end
+		`SARB_DC:
+			if (directCntlReq == 1'b0)	
+			begin
+				NextState_SCTxArb <= `SARB1_WAIT_REQ;
+				next_directCntlGnt <= 1'b0;
+			end
+		`START_SARB:
+			NextState_SCTxArb <= `SARB1_WAIT_REQ;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_CurrentState
+	if (rst)	
+		CurrState_SCTxArb <= `START_SARB;
+	else
+		CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_RegOutput
+	if (rst)	
+	begin
+		muxDCEn <= 1'b0;
+		sendPacketGnt <= 1'b0;
+		directCntlGnt <= 1'b0;
+	end
+	else 
+	begin
+		muxDCEn <= next_muxDCEn;
+		sendPacketGnt <= next_sendPacketGnt;
+		directCntlGnt <= next_directCntlGnt;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/slaveGetpacket.v	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/slaveGetpacket.v	(revision 264)
@@ -0,0 +1,308 @@
+//--------------------------------------------------------------------------------------------------
+//
+// Title       : No Title
+// Design      : usbhostslave
+// Author      : Steve
+// Company     : Base2Designs
+//
+//-------------------------------------------------------------------------------------------------
+//
+// File        : c:\projects\USBHostSlave\Aldec\usbhostslave\usbhostslave\compile\slaveGetpacket.v
+// Generated   : 09/22/04 06:01:23
+// From        : c:\projects\USBHostSlave\RTL\slaveController\slaveGetpacket.asf
+// By          : FSM2VHDL ver. 4.0.5.2
+//
+//-------------------------------------------------------------------------------------------------
+//
+// Description : 
+//
+//-------------------------------------------------------------------------------------------------
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, bitStuffError, clk, dataSequence, getPacketEn, rst);
+input   [7:0] RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0] RXStreamStatusIn;
+input   SIERxTimeOut;		// Single cycle pulse
+input   clk;
+input   getPacketEn;
+input   rst;
+output  ACKRxed;
+output  CRCError;
+output  [7:0] RXFifoData;
+output  RXFifoWEn;
+output  RXOverflow;
+output  RXPacketRdy;
+output  RXTimeOut;
+output  [3:0] RxPID;
+output  bitStuffError;
+output  dataSequence;
+
+reg     ACKRxed, next_ACKRxed;
+reg     CRCError, next_CRCError;
+wire    [7:0] RXDataIn;
+wire    RXDataValid;
+reg     [7:0] RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXOverflow, next_RXOverflow;
+reg     RXPacketRdy, next_RXPacketRdy;
+wire    [7:0] RXStreamStatusIn;
+reg     RXTimeOut, next_RXTimeOut;
+reg     [3:0] RxPID, next_RxPID;
+wire    SIERxTimeOut;
+reg     bitStuffError, next_bitStuffError;
+wire    clk;
+reg     dataSequence, next_dataSequence;
+wire    getPacketEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0] CurrState_slvGetPkt;
+reg [4:0] NextState_slvGetPkt;
+
+
+//--------------------------------------------------------------------
+// Machine: slvGetPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// NextState logic (combinatorial)
+//----------------------------------
+always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
+begin : slvGetPkt_NextState
+	NextState_slvGetPkt <= CurrState_slvGetPkt;
+	// Set default values for outputs and signals
+	next_CRCError <= CRCError;
+	next_bitStuffError <= bitStuffError;
+	next_RXOverflow <= RXOverflow;
+	next_RXTimeOut <= RXTimeOut;
+	next_ACKRxed <= ACKRxed;
+	next_dataSequence <= dataSequence;
+	next_RXByte <= RXByte;
+	next_RXStreamStatus <= RXStreamStatus;
+	next_RxPID <= RxPID;
+	next_RXPacketRdy <= RXPacketRdy;
+	next_RXByteOldest <= RXByteOldest;
+	next_RXByteOld <= RXByteOld;
+	next_RXFifoWEn <= RXFifoWEn;
+	next_RXFifoData <= RXFifoData;
+	case (CurrState_slvGetPkt) // synopsys parallel_case full_case
+		`START_GP:
+			NextState_slvGetPkt <= `WAIT_EN;
+		`WAIT_PKT:
+		begin
+			next_CRCError <= 1'b0;
+			next_bitStuffError <= 1'b0;
+			next_RXOverflow <= 1'b0;
+			next_RXTimeOut <= 1'b0;
+			next_ACKRxed <= 1'b0;
+			next_dataSequence <= 1'b0;
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `CHK_PKT_START;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		end
+		`CHK_PKT_START:
+			if (RXStreamStatus == `RX_PACKET_START)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+				next_RxPID <= RXByte[3:0];
+			end
+			else
+			begin
+				NextState_slvGetPkt <= `PKT_RDY;
+				next_RXTimeOut <= 1'b1;
+			end
+		`WAIT_EN:
+		begin
+			next_RXPacketRdy <= 1'b0;
+			if (getPacketEn == 1'b1)	
+				NextState_slvGetPkt <= `WAIT_PKT;
+		end
+		`PKT_RDY:
+		begin
+			next_RXPacketRdy <= 1'b1;
+			NextState_slvGetPkt <= `WAIT_EN;
+		end
+		`PROC_PKT_CHK_PID:
+			if (RXByte[1:0] == `HANDSHAKE)	
+				NextState_slvGetPkt <= `PROC_PKT_HS;
+			else if (RXByte[1:0] == `DATA)	
+				NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+			else
+				NextState_slvGetPkt <= `PKT_RDY;
+		`PROC_PKT_HS:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PKT_RDY;
+				next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+				next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+			end
+		`PROC_PKT_DATA_W_D1:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_CHK_D1:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+				next_RXByteOldest <= RXByte;
+			end
+			else
+				NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_W_D2:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_FIN:
+		begin
+			next_CRCError <= RXByte[`CRC_ERROR_BIT];
+			next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+			next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+			NextState_slvGetPkt <= `PKT_RDY;
+		end
+		`PROC_PKT_DATA_CHK_D2:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+				next_RXByteOld <= RXByte;
+			end
+			else
+				NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_W_D3:
+			if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+				next_RXByte <= RXDataIn;
+				next_RXStreamStatus <= RXStreamStatusIn;
+			end
+		`PROC_PKT_DATA_CHK_D3:
+			if (RXStreamStatus == `RX_PACKET_STREAM)	
+				NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+			else
+				NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+		`PROC_PKT_DATA_LOOP_CHK_FIFO:
+			if (RXFifoFull == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+				next_RXOverflow <= 1'b1;
+			end
+			else
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+				next_RXFifoWEn <= 1'b1;
+				next_RXFifoData <= RXByteOldest;
+				next_RXByteOldest <= RXByteOld;
+				next_RXByteOld <= RXByte;
+			end
+		`PROC_PKT_DATA_LOOP_FIFO_FULL:
+			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+		`PROC_PKT_DATA_LOOP_W_D:
+		begin
+			next_RXFifoWEn <= 1'b0;
+			if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+				next_RXByte <= RXDataIn;
+			end
+			else if (RXDataValid == 1'b1)	
+			begin
+				NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+				next_RXByte <= RXDataIn;
+			end
+		end
+		`PROC_PKT_DATA_LOOP_DELAY:
+			NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+	endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_CurrentState
+	if (rst)	
+		CurrState_slvGetPkt <= `START_GP;
+	else
+		CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_RegOutput
+	if (rst)	
+	begin
+		RXByteOld <= 8'h00;
+		RXByteOldest <= 8'h00;
+		RXByte <= 8'h00;
+		RXStreamStatus <= 8'h00;
+		RXPacketRdy <= 1'b0;
+		RXFifoWEn <= 1'b0;
+		RXFifoData <= 8'h00;
+		CRCError <= 1'b0;
+		bitStuffError <= 1'b0;
+		RXOverflow <= 1'b0;
+		RXTimeOut <= 1'b0;
+		ACKRxed <= 1'b0;
+		dataSequence <= 1'b0;
+		RxPID <= 4'h0;
+	end
+	else 
+	begin
+		RXByteOld <= next_RXByteOld;
+		RXByteOldest <= next_RXByteOldest;
+		RXByte <= next_RXByte;
+		RXStreamStatus <= next_RXStreamStatus;
+		RXPacketRdy <= next_RXPacketRdy;
+		RXFifoWEn <= next_RXFifoWEn;
+		RXFifoData <= next_RXFifoData;
+		CRCError <= next_CRCError;
+		bitStuffError <= next_bitStuffError;
+		RXOverflow <= next_RXOverflow;
+		RXTimeOut <= next_RXTimeOut;
+		ACKRxed <= next_ACKRxed;
+		dataSequence <= next_dataSequence;
+		RxPID <= next_RxPID;
+	end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/tags/start/RTL/slaveController/slavecontroller.asf	(nonexistent)
+++ common/components/usbhostslave/tags/start/RTL/slaveController/slavecontroller.asf	(revision 264)
@@ -0,0 +1,347 @@
+VERSION=1.19
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FREEOID=789
+"LIBRARIES=`timescale 1ns / 1ps\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,slaveController"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 376
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 420
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 551
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 580
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 617
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 698
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 15
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+L 554 551 0 TEXT "State Labels" | 63527,72146 1 0 0 "SETUP_OUT"
+S 551 6 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63527,72146 6500 6500
+H 559 551 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3275 212900,251275
+W 550 6 0 81 41 BEZIER "Transitions" | 57945,41731 51978,46294 36355,53695 33342,69899\
+                                       30330,86104 25492,143212 35905,156667 46318,170122\
+                                       96612,168665 117496,167729
+A 548 546 16 TEXT "Actions" | 104043,25328 1 0 0 "USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+C 547 546 0 TEXT "Conditions" | 180628,44450 1 0 0 "NAKSent == 1'b1"
+W 546 6 8194 531 81 BEZIER "Transitions" | 193355,54360 193121,48042 196557,33707 194740,28964\
+                                           192923,24221 173766,19421 163644,19865 153522,20309\
+                                           122483,20608 111915,23020 101347,25432 81761,37919\
+                                           69710,37919
+C 285 97 0 TEXT "Conditions" | 99944,129593 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 190399,213982 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 182869,214288 "" ""
+L 272 271 0 TEXT "Labels" | 186628,209022 1 0 0 "getPacketREn"
+S 15 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "slvCntrl"
+F 6 0 671089152 282 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,252232 1 0 0 "Module: slavecontroller"
+A 302 83 16 TEXT "Actions" | 100377,150834 1 0 0 "PIDByte <= RxByte;"
+L 301 300 0 TEXT "Labels" | 38188,235738 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 30658,236044 "" ""
+L 299 298 0 TEXT "Labels" | 34135,231226 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 28486,231226 "" ""
+A 291 81 4 TEXT "Actions" | 34763,22801 1 0 0 "transDone <= 1'b0;\nclrEPRdy <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;"
+I 588 589 0 Builtin Entry | 89368,239805
+I 587 589 0 Builtin Exit | 192962,45432
+L 586 580 0 TEXT "State Labels" | 176572,76868 1 0 0 "IN"
+S 580 6 45060 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 176572,76868 6500 6500
+H 589 580 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+L 40 41 0 TEXT "State Labels" | 123993,167263 1 0 0 "WAIT_RX1\n/0/"
+S 41 6 0 ELLIPSE "States" | 123993,167568 6500 6500
+C 607 601 0 TEXT "Conditions" | 114440,220845 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 606 589 0 588 605 BEZIER "Transitions" | 89368,237478 89903,233730 89797,226993 90332,223245
+S 605 589 53248 ELLIPSE "States" | 91340,216824 6500 6500
+L 604 605 0 TEXT "State Labels" | 91340,216824 1 0 0 "CHK_RDY\n/10/"
+A 603 596 4 TEXT "Actions" | 174409,172080 1 0 0 "sendPacketWEn <= 1'b0;"
+W 601 589 8193 605 596 BEZIER "Transitions" | 97839,216722 109714,216534 162558,220059 167812,183210
+W 600 589 8192 596 587 BEZIER "Transitions" | 168405,170293 203966,131503 199503,89144 196184,45432
+A 599 601 16 TEXT "Actions" | 124386,212388 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+C 598 600 0 TEXT "Conditions" | 159138,161356 1 0 0 "sendPacketRdy == 1'b1"
+L 597 596 0 TEXT "State Labels" | 169718,177574 1 0 0 "NAK_STALL\n/9/"
+S 596 589 49152 ELLIPSE "States" | 168684,176772 6500 6500
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+I 620 618 0 Builtin Exit | 144780,101600
+I 619 618 0 Builtin Entry | 96520,152400
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+A 615 612 16 TEXT "Actions" | 110702,185120 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 614 612 0 TEXT "Conditions" | 69153,194735 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+W 613 589 8195 605 617 BEZIER "Transitions" | 86536,212447 76974,203420 61686,186612 53042,177585
+W 612 589 8194 605 596 BEZIER "Transitions" | 91984,210359 90899,202871 142592,172810 163035,179986
+L 639 640 0 TEXT "State Labels" | 125814,48840 1 0 0 "GET_RESP\n/12/"
+A 638 631 16 TEXT "Actions" | 118603,107061 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+A 637 630 16 TEXT "Actions" | 36344,101376 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+C 636 630 0 TEXT "Conditions" | 29568,129096 1 0 0 "USBEndPControlReg [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+W 631 589 8194 617 629 BEZIER "Transitions" | 54075,173680 59927,171524 83885,163128 122946,146882\
+                                              162008,130636 145376,121704 139603,106244 133831,90784\
+                                              72380,75586 70378,71274
+W 630 589 8193 617 629 BEZIER "Transitions" | 48383,172368 44995,170520 39116,166056 37345,163515\
+                                              35574,160974 35266,154506 35651,142263 36036,130020\
+                                              37884,87516 41041,76736 44198,65956 54978,65340\
+                                              57981,65109 60984,64878 60379,64505 60995,64351
+S 629 589 61440 ELLIPSE "States" | 67392,65502 6500 6500
+L 628 629 0 TEXT "State Labels" | 67392,65502 1 0 0 "DATA\n/11/"
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/13/"
+S 654 559 69632 ELLIPSE "States" | 92422,152802 6500 6500
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+C 652 651 0 TEXT "Conditions" | 124856,135409 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b0"
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+I 650 559 0 Builtin Exit | 194044,45058
+I 649 559 0 Builtin Entry | 37971,243103
+C 647 646 0 TEXT "Conditions" | 140247,52755 1 0 0 "getPacketRdy == 1'b1"
+W 646 589 0 640 587 BEZIER "Transitions" | 132288,49411 139757,47794 182271,47049 189740,45432
+A 645 640 4 TEXT "Actions" | 108652,38924 1 0 0 "getPacketREn <= 1'b0;"
+A 644 641 16 TEXT "Actions" | 75293,54584 1 0 0 "getPacketREn <= 1'b1;"
+C 643 641 0 TEXT "Conditions" | 73811,60869 1 0 0 "sendPacketRdy == 1'b1"
+A 642 629 4 TEXT "Actions" | 76076,71808 1 0 0 "sendPacketWEn <= 1'b0;"
+W 641 589 0 629 640 BEZIER "Transitions" | 73191,62566 81815,59948 110822,52759 119446,50141
+S 640 589 65536 ELLIPSE "States" | 125814,48840 6500 6500
+I 381 377 0 Builtin Exit | 206487,14249
+I 380 377 0 Builtin Entry | 48940,236580
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 376 6 94212 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+I 96 722 0 Builtin Reset | 76296,129336
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlReg [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/14/"
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+S 656 559 73728 ELLIPSE "States" | 109789,85208 5889 6500
+I 399 377 0 Builtin Link | 54419,17564
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+                                              60053,165183 57484,160822 55722,148570 53960,136319\
+                                              36935,95064 38880,77714 40826,60365 38327,20823\
+                                              54419,15564
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+                                              46511,172964 33727,90292 34975,71611 36223,52930\
+                                              35724,34993 37785,28932 39847,22872 46307,16188\
+                                              54419,15564
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+I 701 699 0 Builtin Exit | 144780,101600
+I 700 699 0 Builtin Entry | 96520,152400
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 698 559 81940 ELLIPSE "Junction" | 117000,209824 3500 3500
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+W 696 559 8194 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+                                              200304,203038 205920,186346 207441,167119 208962,147892\
+                                              209430,87676 208962,71608 208494,55540 206154,51484\
+                                              204438,50041 202722,48598 199528,45916 197266,45058
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+                                              39220,148925 36609,140943 36571,133460 36533,125977\
+                                              38989,104026 47738,97617 56488,91209 87662,87731\
+                                              103933,85889
+C 693 692 0 TEXT "Conditions" | 108065,184348 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 &&\nRxOverflow == 1'b0 &&\nRxTimeOut == 1'b0"
+W 692 559 8193 698 654 BEZIER "Transitions" | 115978,206479 112866,179807 96893,185826 93781,159154
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+S 690 559 77824 ELLIPSE "States" | 98991,238090 6500 6500
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/15/"
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+                                              69948,104476 47394,95074 43302,84878 39210,74682\
+                                              42917,24960 54419,15564
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+I 423 421 0 Builtin Exit | 144780,101600
+I 422 421 0 Builtin Entry | 96520,152400
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+                                           108160,233400 112640,227800 113920,224400 115200,221000\
+                                           116013,213096 116333,209096
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+I 727 722 0 Builtin Exit | 144780,101600
+I 726 722 0 Builtin Entry | 96520,152400
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;"
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/16/"
+S 723 722 90112 ELLIPSE "States" | 120650,127000 6500 6500
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/18/"
+S 462 377 102400 ELLIPSE "States" | 94684,51331 6500 6500
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 749 0 2 Builtin InPort | 122043,237048 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[3:0]"
+I 747 0 2 Builtin InPort | 29748,247328 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 743 0 2 Builtin OutPort | 119778,227003 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+C 468 457 0 TEXT "Conditions" | 76387,38022 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS  &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+A 763 41 68 TEXT "Actions" | 141963,174883 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 757 0 2 Builtin OutPort | 119853,246737 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 755 0 2 Builtin OutPort | 119826,241925 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+I 765 0 2 Builtin Signal | 120578,208940 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+                                              46860,73975 46530,57145 47396,48771 48262,40398\
+                                              52522,23896 54419,15564
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+I 769 0 2 Builtin InPort | 77236,247440 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 771 0 2 Builtin InPort | 76928,242820 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 773 0 2 Builtin Signal | 120664,213560 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 775 0 2 Builtin Signal | 120664,217872 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 777 0 2 Builtin Signal | 120664,221876 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
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+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
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+                                           72231,35690 70888,36159 69579,36621
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+C 535 532 0 TEXT "Conditions" | 73577,60437 1 0 0 "USBEndPControlReg [`ENDPOINT_READY_BIT] == 1'b1"
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
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+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
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+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
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+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+END

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Index: common/components/usbhostslave/tags/start/doc/html/images/bde/zoommodeover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/zoommodeover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/acp.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/acp.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/asf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/asf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/bas.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/bas.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/conf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/conf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/bde/newwindowover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/newwindowover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/bde/pop.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/pop.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/bde/prevdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/prevdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/awf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/awf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/bde.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/bde.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/cpp.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/cpp.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/do.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/do.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/edn.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/edn.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/asfselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/asfselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/basselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/basselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/confselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/confselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/dlmselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/dlmselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/drwselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/drwselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/dlm.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/dlm.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/drw.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/drw.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/htm.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/htm.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/pl.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/pl.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/symb.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/symb.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/txt.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/txt.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/undefselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/undefselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/hpselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/hpselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/lstselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/lstselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/sdfselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/sdfselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/tclselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/tclselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/undef.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/undef.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/vhd.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/vhd.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/vselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/vselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/xnfselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/xnfselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/hp.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/hp.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/lst.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/lst.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/sdf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/sdf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/tcl.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/tcl.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/und.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/und.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/v.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/v.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/vlsselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/vlsselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/xnf.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/xnf.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/vhdselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/vhdselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/vtb.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/vtb.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/bar.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/bar.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/fit.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/fit.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/codeover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/codeover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/bde/printover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/printover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/bde/tbl.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/tbl.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/bde/zoomin.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/zoomin.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/bde/zoommodedown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/zoommodedown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/bde/zoomoutover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/bde/zoomoutover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/ahwselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/ahwselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/awfselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/awfselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/bdeselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/bdeselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/cppselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/cppselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/doselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/doselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/ednselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/ednselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/htmselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/htmselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/plselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/plselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/symbselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/symbselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/txtselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/txtselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/undselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/undselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/vls.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/vls.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ext/vtbselected.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ext/vtbselected.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/code.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/code.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/fitdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/fitdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/full.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/full.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/newwindowdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/newwindowdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/prevover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/prevover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomin.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomin.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/frame.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/frame.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/newwindow.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/newwindow.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/prevdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/prevdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/printover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/printover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/codedown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/codedown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/fitover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/fitover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/fullover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/fullover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/prev.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/prev.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/printdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/printdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomoutdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomoutdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/empty.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/empty.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/n_nr.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/n_nr.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/s_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/s_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/logoback.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/logoback.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/lst/sig.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/lst/sig.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomout.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomout.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/back.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/back.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/n_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/n_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/right_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/right_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/logo.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/logo.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/lst/out.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/lst/out.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/fulldown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/fulldown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/newwindowover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/newwindowover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/print.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/print.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomindown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomindown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomoutover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoomoutover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/left_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/left_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/n_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/n_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/tab_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/tab_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/logoback.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/logoback.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/lst/sig.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/lst/sig.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/msie_doc.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/msie_doc.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/ns_doc_mo.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/ns_doc_mo.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/folderopen.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/folderopen.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/line.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/line.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/doc.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/doc.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/ns_doc.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/ns_doc.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/folderclosed.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/folderclosed.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/jointop.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/jointop.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoominover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/fsm/zoominover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/ico/ahdl.ico
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/ico/ahdl.ico
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/left_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/left_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/right_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/right_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/itab/tab_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/itab/tab_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/lst/in.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/lst/in.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/lst/var.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/lst/var.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/msie_doc_sel.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/msie_doc_sel.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/blank.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/blank.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/joinbottom.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/joinbottom.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/minustop.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/minustop.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/plustop.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/plustop.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/expandall_f2.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/expandall_f2.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/set/coll.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/set/coll.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/minusonly.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/minusonly.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/plusonly.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/plusonly.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/expandall.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/expandall.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/shim.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/shim.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/back.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/back.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/msie_doc_mo.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/msie_doc_mo.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/ns_doc_sel.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/ns_doc_sel.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/join.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/join.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/minus.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/minus.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/plus.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/plus.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/collapseall.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/collapseall.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/empty.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/empty.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/n_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/n_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/tab_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/tab_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/folder_o.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/folder_o.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/join_t.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/join_t.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/minusbottom.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/minusbottom.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menu/win/plusbottom.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menu/win/plusbottom.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/collapseall_f2.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/collapseall_f2.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/home_f2.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/home_f2.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/set/norm.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/set/norm.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/left_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/left_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/right_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/right_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/empty.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/empty.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/join_b.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/join_b.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/minus.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/minus.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/minus_o.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/minus_o.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/plus_o.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/plus_o.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/bar.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/bar.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/first.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/first.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/lastdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/lastdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/n_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/n_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/s_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/s_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/folder_c.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/folder_c.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/join_l.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/join_l.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/minus_b.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/minus_b.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/plus_b.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/plus_b.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/back.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/back.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/downover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/downover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/last.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/last.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/home.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/menucntrl/home.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/set/exp.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/set/exp.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/left_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/left_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/right_n.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/right_n.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tab/tab_s.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tab/tab_s.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/join.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/join.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/line.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/line.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/minus_t.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/minus_t.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/plus_t.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/plus_t.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/down.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/down.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/firstdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/firstdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/nextover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/nextover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/up.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/up.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/info/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/info/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/info/index.htm	(revision 264)
@@ -0,0 +1,59 @@
+<html>
+<head>
+<title>Active-HDL: "usbhostslave" </title>
+<style type="text/css">
+td,caption {font-size:17px; font-family: courier;}
+</style>
+</head>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" 
+marginwidth="0" bgcolor="silver">
+
+<table cellpadding=5 width=100%>
+<caption ><b>PROJECT INFORMATION:</b><hr></caption>
+<tr>
+  <td width=200px><b>#WORKSPACE NAME:</b></td>
+  <td>usbhostslave</td>
+</tr>
+<tr>
+  <td><b>#DESIGN NAME:</b></td>
+  <td>usbhostslave</td>
+</tr>
+<tr>
+  <td><b>#SYNTHESIS TOOL:</b></td>
+  <td><none></td>
+</tr>
+<tr>
+  <td><b>#IMPLEMENTATION TOOL:</b></td>
+  <td><none></td>
+</tr>
+<tr>
+  <td><b>#AUTHOR:</b></td>
+  <td>Steve</td>
+</tr>
+<tr>
+  <td><b>#COMPANY:</b></td>
+  <td>Base2Designs</td>
+</tr>
+<tr>
+  <td><b>#E-MAIL:</b></td>
+  <td><A href="mailto:sfielding@base2designs.com">sfielding@base2designs.com</A></td>
+</tr>
+<tr>
+  <td  valign=top><b>#HTML GENERATOR:</b></td>
+  <td>HDE converter 1.0<br>LST converter 1.0<br>BDE converter 1.0<br>FSM converter 1.0<br>WVF converter 1.0</td>
+</tr>
+<tr>
+  <td  valign=top><b>#DESCRIPTION:</b></td>
+  <td></td>
+</tr>
+<tr>
+  <td  valign=top><b>#COMMENT:</b></td>
+  <td></td>
+</tr>
+</table>
+
+<hr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/info/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/nextdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/nextdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/prevover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/prevover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/plus.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/plus.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/tree/project.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/tree/project.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/downdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/downdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/firstover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/firstover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/next.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/next.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/prevdown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/prevdown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/upover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/upover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/menucntrl.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/menucntrl.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/menucntrl.htm	(revision 264)
@@ -0,0 +1,70 @@
+<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML//EN">
+<HTML>
+<HEAD>
+<TITLE>Aldec Menu Control</TITLE>
+<META NAME="ROBOTS" CONTENT="NOINDEX,NOFOLLOW">
+<script language="JavaScript">
+<!--
+if ((self.name != 'menuCntrl') & (self.location.protocol != "file:")) {
+	self.location = "index.htm";
+}
+if (parent.theBrowser) {
+	if (parent.theBrowser.canOnError) {window.onerror = parent.defOnError;}
+}
+
+
+
+/* Function that displays status bar messages. */
+function MM_displayStatusMsg(msgStr)  { //v3.0
+	status=msgStr; document.MM_returnValue = true;
+}
+
+function MM_findObj(n, d) { //v3.0
+  var p,i,x;  if(!d) d=document; if((p=n.indexOf("?"))>0&&parent.frames.length) {
+    d=parent.frames[n.substring(p+1)].document; n=n.substring(0,p);}
+  if(!(x=d[n])&&d.all) x=d.all[n]; for (i=0;!x&&i<d.forms.length;i++) x=d.forms[i][n];
+  for(i=0;!x&&d.layers&&i<d.layers.length;i++) x=MM_findObj(n,d.layers[i].document); return x;
+}
+
+/* Functions that swaps images. */
+function MM_swapImage() { //v3.0
+  var i,j=0,x,a=MM_swapImage.arguments; document.MM_sr=new Array; for(i=0;i<(a.length-2);i+=3)
+   if ((x=MM_findObj(a[i]))!=null){document.MM_sr[j++]=x; if(!x.oSrc) x.oSrc=x.src; x.src=a[i+2];}
+}
+function MM_swapImgRestore() { //v3.0
+  var i,x,a=document.MM_sr; for(i=0;a&&i<a.length&&(x=a[i])&&x.oSrc;i++) x.src=x.oSrc;
+}
+
+if (document.images) {
+  expandall_f2 = new Image(18 ,16); expandall_f2.src = "images/menucntrl/expandall_f2.gif";
+  expandall_f1 = new Image(18 ,16); expandall_f1.src = "images/menucntrl/expandall.gif";
+  collapseall_f2 = new Image(18 ,16); collapseall_f2.src = "images/menucntrl/collapseall_f2.gif";
+  collapseall_f1 = new Image(18 ,16); collapseall_f1.src = "images/menucntrl/collapseall.gif";
+  normalview_f2 = new Image(18 ,16); normalview_f2.src = "images/menucntrl/normalview_f2.gif";
+  normalview_f1 = new Image(18 ,16); normalview_f1.src = "images/menucntrl/normalview.gif";
+}
+
+//-->
+</script>
+</HEAD>
+<BODY bgcolor="white" marginwidth="0" marginheight="0" background="images/aldec.gif">
+
+<table border="0" cellpadding="0" cellspacing="0">
+  <tr>
+  <tr valign="top"><!-- row 1 -->
+   <td><img src="images/menucntrl/shim.gif" width="1" height="4" border="0"></td>
+   <td><img src="images/menucntrl/shim.gif" width="1" height="4" border="0"></td>
+  </tr>
+  <tr valign="top">
+   <td><img src="images/menucntrl/shim.gif" width="7" height="20" border="0"></td>
+   <td rowspan="1" colspan="1"><a href="javascript:parent.theMenu.openAll();" onMouseOut="MM_swapImgRestore();"  onMouseOver="MM_displayStatusMsg('Click to expand all folders in the outline.');MM_swapImage('expandall','','images/menucntrl/expandall_f2.gif',1);return document.MM_returnValue" ><img name="expandall" src="images/menucntrl/expandall.gif" width="18" height="16" border="0" alt="Expand All"></a></td>
+   <td rowspan="1" colspan="1"><a href="javascript:parent.theMenu.closeAll();" onMouseOut="MM_swapImgRestore();"  onMouseOver="MM_displayStatusMsg('Click to collapse all folders in the outline');MM_swapImage('collapseall','','images/menucntrl/collapseall_f2.gif',1);return document.MM_returnValue" ><img name="collapseall" src="images/menucntrl/collapseall.gif" width="18" height="16" border="0" alt="Collapse All"></a></td>
+   <td><a href="./splash/info.htm" target="text" onMouseOut="MM_swapImgRestore();"  onMouseOver="MM_displayStatusMsg('Click to go to the Home page.');MM_swapImage('home','','images/menucntrl/home_f2.gif',1);return document.MM_returnValue" ><img name="home" src="images/menucntrl/home.gif" width="18" height="16" border="0" alt="Home"></a></td>
+  </tr>
+</tr>
+</table>
+
+</BODY>
+</HTML>
+
+

Property changes on: common/components/usbhostslave/tags/start/doc/html/menucntrl.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/index.htm	(revision 264)
@@ -0,0 +1,1186 @@
+<HTML>
+<HEAD>
+<TITLE>usbhostslave</TITLE>
+<meta name="Author" content="Steve">
+<meta name="Generator" content="ActiveHDL 6.2">
+
+<!--
+Joust Outliner Version 2.5.4
+(c) Copyright 1996-2001, MITEM (Europe) Ltd. All rights reserved.
+This code may be freely copied and distributed provided that it is accompanied by this 
+header.  For full details of the Joust license, as well as documentation and help, go 
+to http://www.ivanpeters.com/.
+
+Do not modify anything between here and the "End of Joust" marker unless you know what you
+are doing.  
+-->
+<script language="JavaScript">
+<!--
+function getDHTMLObj(docName, objName) {
+	if 	(theBrowser.hasW3CDOM) {
+		return eval(docName + '.getElementById("' + objName + '").style');
+	} else {
+		return eval(docName + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLStyleObj);
+	}
+}
+function getDHTMLObjTop(theObj) {return (theBrowser.code == "MSIE") ? theObj.pixelTop : theObj.top;}
+function getDHTMLObjHeight(docName, objName) {
+	if 	(theBrowser.hasW3CDOM) {
+		return parseInt(eval(docName + '.getElementById("' + objName + '").offsetHeight'),10);
+	} else {
+		return eval(docName + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLDivHeight);
+	}
+}
+function getDHTMLImg(docName, objName, imgName) {
+	if 	(document.layers) {
+		return getDHTMLObj(docName, objName).document.images[imgName];
+	} else {
+		return eval(docName + '.images.' + imgName);
+	}
+}
+function simpleArray() {this.item = 0;}
+function imgStoreItem(n, s, w, h) {
+	this.name = n;
+	this.src = s;
+	this.obj = null;
+	this.w = w;
+	this.h = h;
+	if ((theBrowser.canCache) && (s)) {
+		this.obj = new Image(w, h);
+		this.obj.src = s;
+	}
+}
+function imgStoreObject() {
+	this.count = -1;
+	this.img = new imgStoreItem;
+	this.find = imgStoreFind;
+	this.add = imgStoreAdd;
+	this.getSrc = imgStoreGetSrc;
+	this.getTag = imgStoreGetTag;
+}
+function imgStoreFind(theName) {
+	var foundItem = -1;
+	for (var i = 0; i <= this.count; i++) {if (this.img[i].name == theName) {foundItem = i;break;}}
+	return foundItem;
+}
+function imgStoreAdd(n, s, w, h) {
+	var i = this.find(n);
+	if (i == -1) {i = ++this.count;}
+	this.img[i] = new imgStoreItem(n, s, parseInt(w, 10), parseInt(h, 10));
+}
+function imgStoreGetSrc(theName) {
+	var i = this.find(theName);
+	var img = this.img[i];
+	return (i == -1) ? '' : ((img.obj) ? img.obj.src : img.src);
+}
+function imgStoreGetTag(theName, iconID, altText) {
+	var i = this.find(theName);
+	if (i < 0) {return ''}
+	with (this.img[i]) {
+		if (src == '') {return ''}
+		var tag = '<img src="' + src + '" width="' + w + '" height="' + h + '" border="0" align="left" hspace="0" vspace="0"';
+		tag += (iconID != '') ? ' name="' + iconID + '"' : '';
+		tag += ' alt="' + ((altText)?altText:'') + '">';
+	}
+	return tag;
+}
+// The MenuItem object.  This contains the data and functions for drawing each item.
+function MenuItem (owner, id, type, text, url, status, nItem, pItem, parent) {
+	var t = this;
+	this.owner = owner;
+	this.id = id;
+	this.type = type;
+	this.text = text;
+	this.url = url;
+	this.status = status;
+	this.target = owner.defaultTarget;
+	this.nextItem = nItem;
+	this.prevItem = pItem;
+	this.FirstChild = -1;
+	this.parent = parent;
+	this.isopen = false;
+	this.isSelected = false;
+	this.draw = MIDraw;
+	this.PMIconName = MIGetPMIconName;
+	this.docIconName = MIGetDocIconName;
+	this.setImg = MISetImage;
+	this.setIsOpen = MISetIsOpen;
+	this.setSelected = MISetSelected;
+	this.setIcon = MISetIcon;
+	this.mouseOver = MIMouseOver;
+	this.mouseOut = MIMouseOut;
+	var i = (this.owner.imgStore) ? this.owner.imgStore.find(type) : -2;
+	if (i == -1) {i = this.owner.imgStore.find('iconPlus');}
+	this.height = (i > -1) ? this.owner.imgStore.img[i].h : 0;
+}
+function MIDraw (indentStr) {
+	var o = this.owner;
+	var mRef = '="return ' + o.reverseRef + "." + o.name;
+	var tmp = mRef + '.entry[' + this.id + '].';
+	var MOver = ' onMouseOver' + tmp + 'mouseOver(\''
+	var MOut = ' onMouseOut' + tmp + 'mouseOut(\''
+	var iconTag = o.imgStore.getTag(this.PMIconName(), 'plusMinusIcon' + this.id, '');
+	var aLine = '<nobr>' + indentStr;
+	if (!this.noOutlineImg) {
+		if (this.FirstChild != -1) {
+			aLine += '<A HREF="#" onClick' + mRef + '.toggle(' + this.id + ');"' + MOver + 'plusMinusIcon\',this);"' + MOut + 'plusMinusIcon\');">' + iconTag + '</A>';				
+		} else {
+			aLine += iconTag;
+		}
+	}
+	var tip = (o.tipText == 'text') ? this.text : ((o.tipText == 'status') ? this.status : '');
+	var theEntry = o.imgStore.getTag(this.docIconName(), 'docIcon' + this.id, tip) + this.text;
+	var theImg = o.imgStore.getTag(this.docIconName(), 'docIcon' + this.id, tip);
+	var sTxt = '<SPAN CLASS="' + ((this.CSSClass) ? this.CSSClass : ((this.FirstChild != -1) ? 'node' : 'leaf')) + '">';
+	var lTxt = '<A NAME="joustEntry' + this.id + '"';
+	var theUrl = (((this.url == '') && theBrowser.canJSVoid && o.showAllAsLinks) || o.wizardInstalled) ? 'javascript:void(0);' : this.url;
+	if (theUrl != '') {
+		if (this.target.charAt(1) == "_") {theUrl = "javascript:" + o.reverseRef + ".loadURLInTarget('" + theUrl + "', '" + this.target + "');";}
+			lTxt += ' HREF="' + theUrl + '" TARGET="' + this.target + '" onClick' + mRef + '.itemClicked(' + this.id + ');"'
+			+ MOver + 'docIcon\',this);"' + MOut + 'docIcon\');"';
+	}
+	lTxt += (tip) ? ' TITLE="' + tip + '">' : '>';
+	aLine += sTxt + lTxt + theImg;
+	if (this.multiLine) {
+		aLine += '</A></SPAN><TABLE BORDER="0" CELLPADDING="0" CELLSPACING="0"><TR><TD>' + sTxt + lTxt + this.text + '</A></SPAN></TD></TR></TABLE>';
+	} else {
+		aLine += this.text + '</A></SPAN>';
+	}
+	aLine += '</nobr>';
+	if ((theBrowser.hasW3CDOM) && (theBrowser.hasDHTML) && (!this.multiLine))  { aLine += '<br>'; }
+	return aLine
+}
+function MIGetPMIconName() {
+	var n = 'icon' + ((this.FirstChild != -1) ? ((this.isopen == true) ? 'Minus' : 'Plus') : 'Join');
+	n += (this.id == this.owner.firstEntry) ? ((this.nextItem == -1) ? 'Only' : 'Top') : ((this.nextItem == -1) ? 'Bottom' : '');
+	return n;
+}
+function MIGetDocIconName() {
+	var is = this.owner.imgStore; var n = this.type;
+	n += ((this.isopen) && (is.getSrc(n + 'Expanded') != '')) ? 'Expanded' : '';
+	n += ((this.isSelected) && (is.getSrc(n + 'Selected') != '')) ? 'Selected' : '';
+	return n;
+}
+function MISetImage(imgID, imgName) {
+	var o = this.owner; var s = o.imgStore.getSrc(imgName);
+	if ((s != '') && (theBrowser.canCache) && (!o.amBusy)) {
+		var img = (theBrowser.hasDHTML) ? getDHTMLImg(o.container + '.document', 'entryDIV' + this.id, imgID) : eval(o.container).document.images[imgID];
+		if (img && img.src != s) {img.src = s;} 
+	}
+}
+function MISetIsOpen (isOpen) {
+	if ((this.isopen != isOpen) && (this.FirstChild != -1)) {
+		this.isopen = isOpen;
+		this.setImg('plusMinusIcon' + this.id, this.PMIconName());
+		this.setImg('docIcon' + this.id, this.docIconName());
+		return true;
+	} else {
+		return false;
+	}
+}
+function MISetSelected (isSelected) {
+	this.isSelected = isSelected;
+	this.setImg('docIcon' + this.id, this.docIconName());
+	if ((this.parent >= 0) && this.owner.selectParents) {this.owner.entry[this.parent].setSelected(isSelected);}
+}
+function MISetIcon (newType) {
+	this.type = newType;
+	this.setImg('docIcon' + this.id, this.docIconName());
+}
+function MIMouseOver(imgName, theURL) {
+	eval(this.owner.container).status = '';  //Needed for setStatus to work on MSIE 3 - Go figure!?
+	var newImg = '';
+	var s = '';
+	if (imgName == 'plusMinusIcon') {
+		newImg = this.PMIconName();
+		s = 'Click to ' + ((this.isopen == true) ? 'collapse.' : 'expand.');
+	} else {
+		if (imgName == 'docIcon') {
+			newImg = this.docIconName();
+			s = (this.status != null) ? this.status : theURL;
+		}
+	}
+	setStatus(s);
+	if (theBrowser.canOnMouseOut) {this.setImg(imgName + this.id, newImg + 'MouseOver');}
+	if(this.onMouseOver) {var me=this;eval(me.onMouseOver);}
+	return true;
+}
+function MIMouseOut(imgName) {
+	clearStatus();
+	var newImg = '';
+	if (imgName == 'plusMinusIcon') {
+		newImg = this.PMIconName();
+	} else {
+		if (imgName == 'docIcon') {newImg = this.docIconName();}
+	}
+	this.setImg(imgName + this.id, newImg);
+	if(this.onMouseOut) {var me=this;eval(me.onMouseOut);}
+	return true;
+}
+// The Menu object.  This is basically an array object although the data in it is a tree.
+function Menu () {
+	this.count = -1;
+	this.version = '2.5.4';
+	this.firstEntry = -1;
+	this.autoScrolling = false;
+	this.modalFolders = false;
+	this.linkOnExpand = false;
+	this.toggleOnLink = false;
+	this.showAllAsLinks = false;
+	this.savePage = true;
+	this.name = 'theMenu';
+	this.container = 'menu';
+	this.reverseRef = 'parent';
+	this.contentFrame = 'text';
+	this.defaultTarget = 'text';
+	this.tipText = 'none';
+	this.selectParents = false;
+	this.lastPMClicked = -1;
+	this.selectedEntry = -1;
+	this.wizardInstalled = false;
+	this.amBusy = true;
+	this.maxHeight = 0;
+	this.imgStore = new imgStoreObject;
+	this.entry = new MenuItem(this, 0, '', '', '', '', -1, -1, -1);
+	this.contentWin = MenuGetContentWin;
+	this.getEmptyEntry = MenuGetEmptyEntry;
+	this.addEntry = MenuAddEntry;
+	this.addMenu = MenuAddEntry;
+	this.addChild = MenuAddChild;
+	this.rmvEntry = MenuRmvEntry;
+	this.rmvChildren = MenuRmvChildren;
+	this.draw = MenuDraw;
+	this.drawALevel = MenuDrawALevel;
+	this.refresh = MenuRefresh;
+	this.reload = MenuReload;
+	this.refreshDHTML = MenuRefreshDHTML;
+	this.scrollTo = MenuScrollTo;
+	this.itemClicked = MenuItemClicked;
+	this.selectEntry = MenuSelectEntry;
+	this.setEntry = MenuSetEntry;
+	this.setEntryByURL = MenuSetEntryByURL;
+	this.setAllChildren = MenuSetAllChildren;
+	this.setAll = MenuSetAll;
+	this.openAll = MenuOpenAll;
+	this.closeAll = MenuCloseAll;
+	this.findEntry = MenuFindEntry;
+	this.toggle = MenuToggle;
+}
+function MenuGetContentWin() {
+	return eval(((myOpener != null) ? 'myOpener.' : 'self.') + this.contentFrame);
+}
+function MenuGetEmptyEntry() {
+	for (var i = 0; i <= this.count; i++) {if (this.entry[i] == null) {break;}}
+	if (i > this.count) {this.count = i};
+	return i
+}
+function MenuAddEntry (addTo, type, text, url, status, insert) {
+	if (!insert) {insert=false;}
+	var theNI = -1;var theP = -1;var thePI = -1;
+	if (addTo < 0) {
+		var i = addTo = this.firstEntry;
+		if (!insert) {while (i > -1) {addTo = i;i = this.entry[i].nextItem;}}
+	}
+	if (addTo >= 0) {
+		var e = this.entry[addTo];
+		if (!e) {return -1;}
+		thePI = (insert)?e.prevItem:addTo;
+		theNI = (insert)?addTo:e.nextItem;
+		theP = e.parent;
+	}
+	var eNum = this.getEmptyEntry();
+	if (thePI >= 0) {
+		this.entry[thePI].nextItem = eNum;
+	} else {
+		if (theP >= 0) {
+			this.entry[theP].FirstChild = eNum;
+		} else {
+			this.firstEntry = eNum;
+		}
+	}
+	if (theNI >= 0) {this.entry[theNI].prevItem = eNum;}
+	this.entry[eNum] = new MenuItem(this, eNum, type, text, url, status, theNI, thePI, theP);
+	return eNum;
+}
+function MenuAddChild (addTo, type, text, url, status, insert) {
+	if (!insert) {insert=false;}
+	var eNum = -1;
+	if ((this.count == -1) || (addTo < 0)) {
+		eNum = this.addEntry(-1, type, text, url, status, false);
+	} else {
+		var e = this.entry[addTo];
+		if (!e) {return -1;}
+		var cID = e.FirstChild;
+		if (cID < 0) {
+			e.FirstChild = eNum = this.getEmptyEntry();
+			this.entry[eNum] = new MenuItem(this, eNum, type, text, url, status, -1, -1, addTo);	
+		} else {
+			while (!insert && (this.entry[cID].nextItem >= 0)) {cID = this.entry[cID].nextItem;}
+			eNum = this.addEntry(cID, type, text, url, status, insert);
+		}
+	}
+	return eNum;
+}
+function MenuRmvEntry (theEntry) {
+	var e = this.entry[theEntry];
+	if (e == null) {return;}
+	var p = e.prevItem;
+	var n = e.nextItem;
+	if (e.FirstChild > -1) {this.rmvChildren(theEntry);}
+	if (this.firstEntry == theEntry) {this.firstEntry = n}
+	if (this.selectedEntry == theEntry) {this.selectedEntry = n}
+	if (p > -1) {
+		this.entry[p].nextItem = n;
+	} else { 
+		if (e.parent > -1) {
+			this.entry[e.parent].FirstChild = n;
+		} else {
+			if (this.firstEntry == theEntry) {this.firstEntry = n}
+		}
+	} 
+	if (n > -1) {this.entry[n].prevItem = p;}
+	this.entry[theEntry] = null;
+}
+function MenuRmvChildren (theP) {
+	var eNum;var e;var tmp;
+	if (theP == -1) {
+		eNum = this.firstEntry;
+		this.firstEntry = -1;
+	} else {
+		eNum = this.entry[theP].FirstChild;
+		this.entry[theP].FirstChild = -1;
+	}
+	while (eNum > -1) {
+		e = this.entry[eNum];
+		if (e.FirstChild > -1) {this.rmvChildren(eNum);}
+		if (this.selectedEntry == eNum) {this.selectedEntry = e.parent;}
+		tmp = eNum;
+		eNum = e.nextItem;
+		this.entry[tmp] = null;
+	}
+}
+function MenuDraw() {
+	this.maxHeight = 0;
+	var theDoc = eval(this.container + ".document");
+	eval(this.container).document.writeln(this.drawALevel(this.firstEntry, '', true, theDoc));
+	if (theBrowser.hasDHTML) {
+		for (var i = 0; i <= this.count; i++) {
+			if (this.entry[i]) {
+				this.maxHeight += getDHTMLObjHeight(this.container + '.document', 'entryDIV' + i);
+			}
+		}
+	} else {
+		if ((this.lastPMClicked > 0) && theBrowser.mustMoveAfterLoad && this.autoScrolling) {
+			this.scrollTo(this.lastPMClicked);
+		}
+	}
+}
+function MenuDrawALevel(firstItem, indentStr, isVisible, theDoc) {
+	var currEntry = firstItem;
+	var padImg = "";
+	var aLine = "";
+	var theLevel = "";
+	var e = null;
+	while (currEntry > -1) {
+		e = this.entry[currEntry];
+		aLine = e.draw(indentStr);
+		if (theBrowser.hasDHTML) {
+			aLine = '<DIV ID="entryDIV' + currEntry + '" CLASS="menuItem">' + aLine + '</DIV>';
+		} else {
+			aLine += '<BR CLEAR="ALL">';
+		}
+		theBrowser.lineByLine = true;
+		if (theBrowser.lineByLine) {theDoc.writeln(aLine);} else {theLevel += aLine;}
+		if ((e.FirstChild > -1) && ((theBrowser.hasDHTML || (e.isopen && isVisible)))) {
+			padImg = (e.noOutlineImg) ? '' : this.imgStore.getTag((e.nextItem == -1) ? 'iconBlank' : 'iconLine', '', '');
+			theLevel += this.drawALevel(e.FirstChild, indentStr + padImg, (e.isopen && isVisible), theDoc);
+		}
+		currEntry = e.nextItem;
+	}
+	return theLevel;
+}
+function MenuRefresh() {
+	if (theBrowser.hasDHTML) {
+		if (!this.amBusy) {
+			this.refreshDHTML();
+			if (this.autoScrolling) {this.scrollTo(this.lastPMClicked);}
+		}
+	} else {
+		this.reload();
+	}
+}
+function MenuReload() {
+	if (!this.amBusy) {
+		this.amBusy = true;
+		var l = eval(this.container).location;
+		var rm = theBrowser.reloadMethod;
+		var newLoc = fixPath(l.pathname);
+		var s = '';
+		if (l.search) {s = l.search;}
+		if (theBrowser.needsMenuSearch) {
+			if (s == '') {
+				s = '?jtoggle=1';
+			} else {
+				var p = s.indexOf('jtoggle=');
+				if (p < 0) {
+					s += '&jtoggle=1';
+				} else {
+					var t = (s.substring(p + 8, p + 9) == "1") ? "2" : "1";
+					s = s.substring(0, p+8) + t;
+				}
+			}
+		}
+		newLoc += s;
+		if (this.autoScrolling && (this.lastPMClicked > 0) && !theBrowser.mustMoveAfterLoad) {
+			newLoc += "#joustEntry" + this.lastPMClicked;
+		}
+		if (rm == 'replace') {
+			l.replace(newLoc);
+		} else {
+			if (rm == 'reload') {
+				l.reload();
+			} else {
+				if (rm == 'timeout') {
+					setTimeout(this.container + ".location.href ='" + newLoc + "';", 100);
+				} else {
+					l.href = newLoc;
+				}
+			}
+		}
+	}
+}
+function MenuRefreshDHTML() {
+	var nextItemArray = new simpleArray;
+	var currEntry = this.firstEntry;
+	var level = (currEntry == -1) ? 0 : 1;
+	var isVisible = true;
+	var lastVisibleLevel = 1;
+	var co = eval(this.container);
+	var yPos = co.menuStart;
+	var d = this.container + '.document';
+	var e = null;var s = null;
+	while (level > 0) {
+		e = this.entry[currEntry];
+		s = getDHTMLObj(d, 'entryDIV' + currEntry);
+		if (isVisible) {
+			s.top = yPos;
+			s.visibility = 'visible';
+			yPos += getDHTMLObjHeight(d, 'entryDIV' + currEntry);
+			lastVisibleLevel = level;
+		} else {
+			s.visibility = 'hidden';
+			s.top = 0;
+		}
+		if (e.FirstChild > -1) {
+			isVisible = (e.isopen == true) && isVisible;
+			nextItemArray[level++] = e.nextItem;
+			currEntry = e.FirstChild;
+		} else {
+			if (e.nextItem != -1) {
+				currEntry = e.nextItem;
+			} else {
+				while (level > 0) {
+					if (nextItemArray[--level] != -1) {
+						currEntry = nextItemArray[level];
+						isVisible = (lastVisibleLevel >= level);
+						break;
+					}
+				}
+			}
+		}
+	}
+	this.maxHeight = yPos;
+	co.setMenuHeight(yPos);
+}
+function MenuScrollTo(entryNo) {
+	if (theBrowser.hasDHTML) {
+		var e = this.entry[entryNo];
+		if (!e) {return;}
+		var co = eval(this.container);
+		var d = this.container + '.document';
+		var srTop = getDHTMLObjTop(getDHTMLObj(d, 'entryDIV' + entryNo));
+		var srBot = (e.nextItem > 0) ? getDHTMLObjTop(getDHTMLObj(d, 'entryDIV' + e.nextItem)) : this.maxHeight;
+		if (theBrowser.code == 'MSIE') {
+			var curTop = co.document.body.scrollTop;
+			var curBot = curTop + co.document.body.clientHeight;
+		} else {
+			var curTop = co.pageYOffset;
+			var curBot = curTop + co.innerHeight;
+		}
+		if ((srBot > curBot) || (srTop < curTop)) {
+			var scrBy = srBot - curBot;
+			if (srTop < (curTop + scrBy)) {scrBy = srTop - curTop;}
+			co.setTimeout('self.scrollBy(0, ' + scrBy + ');', 100);
+		}
+	} else {
+		var l = fixPath(eval(this.container).location.pathname) + '#joustEntry' + entryNo;
+		setTimeout(this.container + '.location.href = "' + l + '";', 100);
+	}
+}
+function MenuItemClicked(entryNo, fromToggle) {
+	var r = true;
+	var e = this.entry[entryNo];
+	var w = this.contentWin();
+	var b = theBrowser;
+
+	this.selectEntry(entryNo);
+	if (this.wizardInstalled) {w.menuItemClicked(entryNo);}
+	if(e.onClickFunc) {e.onClick = e.onClickFunc;}
+	if(e.onClick) {var me=e;if(eval(e.onClick) == false) {r = false;}}
+	if (r) {
+		if (((this.toggleOnLink) && (e.FirstChild != -1) && !(fromToggle)) || e.noOutlineImg) {
+			if (b.hasDHTML) {
+				this.toggle(entryNo, true);
+			} else {
+				setTimeout(this.name + '.toggle(' + entryNo + ', true);', 100);
+			}
+		}
+	}
+	return (e.url != '') ? r : false;
+}
+function MenuSelectEntry(entryNo) {
+	var oe = this.entry[this.selectedEntry];
+	if (oe) {oe.setSelected(false);}
+	var e = this.entry[entryNo];
+	if (e) {e.setSelected(true);}
+	this.selectedEntry = entryNo;
+}
+function MenuSetEntry(entryNo, state) {
+	var cl = ',' + entryNo + ',';
+	var e = this.entry[entryNo];
+	this.lastPMClicked = entryNo;
+	var mc = e.setIsOpen(state);
+	var p = e.parent;
+	while (p >= 0) {
+		cl += p + ',';
+		e = this.entry[p];
+		mc |= (e.setIsOpen(true));
+		p = e.parent;
+	}
+	if (this.modalFolders) {
+		for (var i = 0; i <= this.count; i++) {
+			e = this.entry[i];
+			if ((cl.indexOf(',' + i + ',') < 0) && e) {mc |= e.setIsOpen(false);}
+		}
+	}
+	return mc;
+}
+function MenuSetEntryByURL(theURL, state) {
+	var i = this.findEntry(theURL, 'url', 'right', 0);
+	return (i != -1) ? this.setEntry(i, state) : false;
+}
+function MenuSetAllChildren(state, parentID) {
+	var hasChanged = false;
+	var currEntry = (parentID > -1) ? this.entry[parentID].FirstChild : this.firstEntry;
+	while (currEntry > -1) {
+		var e = this.entry[currEntry];
+		hasChanged |= e.setIsOpen(state);
+		if (e.FirstChild > -1) {hasChanged |= this.setAllChildren(state, currEntry);}
+		currEntry = e.nextItem;
+	}
+	return hasChanged;
+}
+function MenuSetAll(state, parentID) {
+	if (theBrowser.version >= 4) {
+		if (parentID == 'undefined') {parentID = -1;}
+	} else {
+		if (parentID == null) {parentID = -1;}
+	}
+	var hasChanged = false;
+	if (parentID > -1) {hasChanged |= this.entry[parentID].setIsOpen(state);}
+	hasChanged |= this.setAllChildren(state, parentID);
+	if (hasChanged) {
+		this.lastPMClicked = this.firstEntry;
+		this.refresh();
+	}
+}
+function MenuOpenAll() {this.setAll(true, -1);}
+function MenuCloseAll() {this.setAll(false, -1)}
+function MenuFindEntry(srchVal, srchProp, matchType, start) {
+	var e;
+	var sf;
+	if (srchVal == "") {return -1;}
+	if (!srchProp) {srchProp = "url";}
+	if (!matchType) {matchType = "exact";}
+	if (!start) {start = 0;}
+	if (srchProp == "URL") {srchProp = "url";}
+	if (srchProp == "title") {srchProp = "text";}
+	eval("sf = cmp_" + matchType);
+	for (var i = start; i <= this.count; i++) {
+		if (this.entry[i]) {
+			e = this.entry[i];
+			if (sf(eval("e." + srchProp), srchVal)) {return i;}
+		}		
+	}
+	return -1;
+}
+function cmp_exact(c, s) {return (c == s);}
+function cmp_left(c, s) {
+	var l = Math.min(c.length, s.length);
+	return ((c.substring(1, l) == s.substring(1, l)) && (c != ""));
+}
+function cmp_right(c, s) {
+	var l = Math.min(c.length, s.length);
+	return ((c.substring(c.length-l) == s.substring(s.length-l)) && (c != ""));
+}
+function cmp_contains(c, s) {return (c.indexOf(s) >= 0);}
+function MenuToggle(entryNo, fromClicked) {
+	var r = true;
+	var e = this.entry[entryNo];
+	if (e.onToggle) {var me=e;if(eval(e.onToggle) == false) {r = false;}}
+	if (r) {
+		var chg = this.setEntry(entryNo, e.isopen ^ 1);
+		if (this.linkOnExpand && e.isopen) {
+			if (e.url != '') {loadURLInTarget(e.url, e.target);}
+			if (!fromClicked) {this.itemClicked(entryNo, true);}
+		}
+		if (chg) {this.refresh();}
+	}
+	return false;
+}
+// Other functions
+function DrawMenu(m) {
+	m.draw();
+}
+function browserInfo() {
+	this.code = 'unknown';
+	this.version = 0;
+	this.platform = 'Win';
+	var ua = navigator.userAgent;
+	var i = ua.indexOf('WebTV');
+	if (i >= 0) {
+		this.code = 'WebTV';
+		i += 6;
+	} else {
+		i = ua.indexOf('Opera');
+		if (i >= 0) {
+			this.code = 'OP';
+			i = ua.indexOf(') ') + 2;
+		} else {
+			i = ua.indexOf('MSIE');
+			if (i >= 0) {
+				this.code = 'MSIE';
+				i += 5;
+			} else {
+				i = ua.indexOf('Mozilla/');
+				if (i >= 0) {
+					this.code = 'NS';
+					i += 8;
+				}
+			}
+		}
+	}
+	this.version = parseFloat(ua.substring(i, i+4));
+	if (ua.indexOf('Mac') >= 0) {this.platform = 'Mac';}
+	if (ua.indexOf('OS/2') >= 0) {this.platform = 'OS/2';}
+	if (ua.indexOf('X11') >= 0) {this.platform = 'UNIX';}
+	var v = this.version;
+	var p = this.platform;
+	var NS = (this.code == 'NS');
+	var IE = (this.code == 'MSIE');
+	var WTV = (this.code == 'WebTV');
+	var OP = (this.code == 'OP');
+	var OP32up = (OP && (v >= 3.2));
+	var OP5up = (OP && (v >= 5));
+	var IE4up = (IE && (v >= 4));
+	var NS3up = (NS && (v >= 3));
+	var NS6up = (NS && (v >= 5));
+	this.canCache = NS3up || IE4up || OP32up || WTV;
+	this.canOnMouseOut = this.canCache;
+	this.canOnError = NS3up || IE4up || OP32up;
+	this.canJSVoid = !((NS && !NS3up) || (IE && !IE4up) || (OP && (v < 3.5)));
+	this.lineByLine = (v < 4);
+	this.mustMoveAfterLoad = NS3up || (IE4up && (p != 'Mac')) || WTV;
+	if (NS6up == true) {
+		this.reloadMethod = 'reload';
+	} else {
+		if (NS3up || IE4up || WTV || OP5up) {
+			this.reloadMethod = 'replace';
+		} else {
+			this.reloadMethod = (NS && (v == 2.01) && (p != 'Win')) ? 'timeout' : 'href';
+		}
+	}
+	this.needsMenuSearch = (OP && !OP5up);
+	this.canFloat = NS || (IE && !((p == 'Mac') && (v >= 4) && (v < 5)));
+	this.hasDHTML = ((NS || IE) && (v >= 4)) && !(IE && (p == 'Mac') && (v < 4.5));
+	this.slowDHTML = IE4up || NS6up;
+	this.hasW3CDOM = (document.getElementById) ? true : false;
+	this.needLM = (!this.hasW3CDOM && NS) || (IE && (p == 'Mac') && (v >= 4.5));
+	this.DHTMLRange = IE ? '.all' : '';
+	this.DHTMLStyleObj = IE ? '.style' : '';
+	this.DHTMLDivHeight = IE ? '.offsetHeight' : '.clip.height';
+}
+function getWindow() {return (floatingMode) ? myOpener : self;}
+function setStatus(theText) {
+	var theWindow = getWindow();
+	if (theWindow) {
+		theWindow.status = theText;
+		if (!theBrowser.canOnMouseOut) {
+			clearTimeout(statusTimeout);
+			statusTimeout = setTimeout('clearStatus()', 5000);
+		}
+	}
+	return true;
+}
+function clearStatus() {
+	var theWindow = getWindow();
+	if (theWindow) {theWindow.status = '';}
+}
+function unloadFloating() {
+	if (myOpener) {
+		if (myOpener.JoustFrameset) {myOpener.setTimeout('menuClosed();', 100);}
+	}
+}
+function getMode() {
+	var theMode = getParm(document.cookie, 'mode', ';');
+	return ((theMode == "Floating") || (theMode == "NoFrames")) ? theMode : "Frames";
+}
+function smOnError (msg, url, lno) {
+	smCallerWin.onerror = oldErrorHandler;
+	if (confirm(smSecurityMsg)) {setTimeout('setMode("' + smNewMode + '");', 100);}
+	return true;
+}
+function smSetCookie(theMode) {
+	document.cookie = 'mode=' + theMode + '; path=/';
+	if (getMode() != theMode) {
+		alert(smCookieMsg);
+		return false;
+	} else {
+		return true;
+	}
+}
+function setMode(theMode, callerWin) {
+	smNewMode = theMode
+	smCallerWin = (theBrowser.code == 'NS') ? callerWin : self;
+	var okToGo = true;
+	var currentMode = getMode();
+	if (theMode != currentMode) {
+		if (currentMode == 'Floating') {
+			if (smSetCookie(theMode)) {self.close();}
+		} else {
+			var dest = '';
+			if (theBrowser.canFloat) {
+				if ((theMenu.savePage) && (callerWin)) {
+					if (theBrowser.canOnError) {
+						oldErrorHandler = smCallerWin.onerror;
+						smCallerWin.onerror = smOnError;
+					}
+					var l = theMenu.contentWin().location;
+					var p = l.pathname;
+					if (theBrowser.canOnError) {smCallerWin.onerror = oldErrorHandler;}
+					if (p) {
+						dest = fixPath(p) + l.search;
+					} else {
+						if (!confirm(smSecurityMsg)) {okToGo = false;}
+					}
+				}
+			} else {
+				okToGo = false;
+			}
+			if (okToGo && smSetCookie(theMode)) {
+				if (theMode == 'NoFrames') {
+					location.href = (index3 == '') ? ((dest == '') ? '/' : dest) : index3;
+				} else {
+					location.href = index2 + ((dest == '') ? '' : '?page=' + escape(dest));
+				}
+			}
+		}
+	}
+}
+function fixPath(p) {
+	var i = p.indexOf('?', 0);
+	if (i >= 0) {p = p.substring(0,i);}
+	if (p.substring(0,2) == '/:') {p = p.substring(p.indexOf('/', 2), p.length);}
+	i = p.indexOf('\\', 0);
+	while (i >= 0) {
+		p = p.substring(0,i) + '/' + p.substring(i+1,p.length);
+		i = p.indexOf('\\', i);
+	}
+	return p;
+}
+function fileFromPath(p) {
+	p = fixPath(p);
+	var i = p.lastIndexOf('\\');
+	if (i >= 0) {p = p.substring(i+1,p.length);}
+	return p;
+}
+function getParm(theStr, parm, delim) {
+	// returns value of parm from string
+	if (theStr.length == 0) {return '';}
+	var sPos = theStr.indexOf(parm + "=");
+	if (sPos == -1) {return '';}
+	sPos = sPos + parm.length + 1;
+	var ePos = theStr.indexOf(delim, sPos);
+	if (ePos == -1) {ePos = theStr.length;}
+	return unescape(theStr.substring(sPos, ePos));
+}
+function pageFromSearch(def, m, selIt) {
+	var s = self.location.search;
+	if ((s == null) || (s.length <= 1)) {return def;}
+	var p = getParm(s, 'page', '&');
+	p = (p != '') ? fixPath(p) : def;
+	if (m != null) {
+		var e = m.findEntry(p, 'URL', 'exact');
+		if ((e != -1) && selIt) {
+			m.setEntry(e, true);
+			m.selectEntry(e);
+		}
+	}
+	return p;
+}
+function loadURLInTarget(u, t) {
+	var w = eval("self." + t);
+	if (!w && myOpener) {w = eval("myOpener." + t);}
+	if (!w && ("_top,_parent,_self".indexOf(t) >= 0)) {
+		w = eval("getWindow()." + t.substring(1));}
+	if (w) {w.location.href = u;} else {window.open(u, t);}
+}
+function defOnError(msg, url, lno) {
+	if (jsErrorMsg == '') {
+		return false;
+	} else {
+		alert(jsErrorMsg + '.\n\nError: ' + msg + '\nPage: ' + url + '\nLine: ' + lno + '\nBrowser: ' + navigator.userAgent);
+		return true;
+	}
+}
+function defaultResizeHandler() {
+	if ((theBrowser.code == "NS") && theBrowser.hasDHTML && (self.frames.length != 0)) {
+		if (!eval(theMenu.container + ".document.menuBottom")) {
+			theMenu.reload();
+		}
+	}
+}
+// Declare global variables
+var theBrowser = new browserInfo;
+
+var jsErrorMsg = 'A JavaScript error has occurred on this page!  Please note down the ';
+jsErrorMsg += 'following information and pass it on to the Webmaster.';
+if (theBrowser.canOnError) {self.onerror = defOnError;}
+
+var theMenu = new Menu;
+var JoustFrameset = true;
+var statusTimeout = 0;
+var index1 = 'index.htm';
+var index2 = 'index2.htm';
+var index3 = 'index3.htm';
+var smCallerWin;
+var smNewMode;
+var oldErrorHandler;
+var smNoFloat = 'Sorry, your browser does not support this feature!';
+var smCookieMsg = 'You must have Cookies enabled to change the display mode!';
+var smSecurityMsg = 'Due to security restrictions imposed by your browser, I cannot ';
+smSecurityMsg += 'change modes while a page from another server is being displayed. ';
+smSecurityMsg += 'The default home page for this site will be displayed instead.';
+
+var floatingMode = (getMode() == 'Floating');
+var myOpener = null;
+if (floatingMode == true) {
+	if (self.opener) {
+		myOpener = self.opener;
+		if (myOpener.JoustFrameset) {myOpener.setTimeout('setGlobals();', 100);}
+	} else {
+		document.cookie = 'mode=Frames; path=/';
+		floatingMode = false;
+	}
+} else {
+	if (getMode() != 'Frames') {document.cookie = 'mode=Frames; path=/';}
+}
+
+//	############################   End of Joust   ############################
+
+function initOutlineIcons(imgStore) {
+	var ip = 'images/menu/';
+	ip += (theBrowser.platform == 'Mac') ? 'mac/' : ((theBrowser.platform == 'OS/2') ? 'os2/' : 'win/');
+	
+	imgStore.add('iconPlusTop', ip + 'plustop.gif', 18, 16);
+	imgStore.add('iconPlus', ip + 'plus.gif', 18, 16);
+	imgStore.add('iconPlusBottom', ip + 'plusbottom.gif', 18, 16);
+	imgStore.add('iconPlusOnly', ip + 'plusonly.gif', 18, 16);
+	imgStore.add('iconMinusTop', ip + 'minustop.gif', 18, 16);
+	imgStore.add('iconMinus', ip + 'minus.gif', 18, 16);
+	imgStore.add('iconMinusBottom', ip + 'minusbottom.gif', 18, 16);
+	imgStore.add('iconMinusOnly', ip + 'minusonly.gif', 18, 16);
+	imgStore.add('iconLine', ip + 'line.gif', 18, 16);
+	imgStore.add('iconBlank', ip + 'blank.gif', 18, 16);
+	imgStore.add('iconJoinTop', ip + 'jointop.gif', 18, 16);
+	imgStore.add('iconJoin', ip + 'join.gif', 18, 16);
+	imgStore.add('iconJoinBottom', ip + 'joinbottom.gif', 18, 16);
+
+	//Add folder and document images to the imgStore.
+	imgStore.add('Folder', ip + 'folderclosed.gif', 18, 16);
+	
+	var di = 'images/menu/';
+	if ((theBrowser.code == 'NS') || (theBrowser.code == 'MSIE')) {
+		di += theBrowser.code.toLowerCase() + '_doc';
+		imgStore.add('Document', di + '.gif', 18, 16);
+		imgStore.add('DocumentMouseOver', di + '_mo.gif', 18, 16);
+		imgStore.add('DocumentSelected', di + '_sel.gif', 18, 16);
+	} else {
+		imgStore.add('Document', di + 'doc.gif', 18, 16);
+	}
+	var prjImages='images/ext/';	
+	imgStore.add('ACP', prjImages + 'acp.gif', 18, 16);
+	imgStore.add('ACPSelected', prjImages + 'acpselected.gif', 18, 16);
+	imgStore.add('ACPMouseOver', prjImages + 'acpselected.gif', 18, 16);
+	imgStore.add('AHW', prjImages + 'ahw.gif', 18, 16);
+	imgStore.add('AHWSelected', prjImages + 'ahwselected.gif', 18, 16);
+	imgStore.add('AHWMouseOver', prjImages + 'ahwselected.gif', 18, 16);
+	imgStore.add('ASF', prjImages + 'asf.gif', 18, 16);
+	imgStore.add('ASFSelected', prjImages + 'asfselected.gif', 18, 16);
+	imgStore.add('ASFMouseOver', prjImages + 'asfselected.gif', 18, 16);
+	imgStore.add('AWF', prjImages + 'awf.gif', 18, 16);
+	imgStore.add('AWFSelected', prjImages + 'awfselected.gif', 18, 16);
+	imgStore.add('AWFMouseOver', prjImages + 'awfselected.gif', 18, 16);
+	imgStore.add('BAS', prjImages + 'bas.gif', 18, 16);
+	imgStore.add('BASSelected', prjImages + 'basselected.gif', 18, 16);
+	imgStore.add('BASMouseOver', prjImages + 'basselected.gif', 18, 16);
+	imgStore.add('BDE', prjImages + 'bde.gif', 18, 16);
+	imgStore.add('BDESelected', prjImages + 'bdeselected.gif', 18, 16);
+	imgStore.add('BDEMouseOver', prjImages + 'bdeselected.gif', 18, 16);
+	imgStore.add('CONF', prjImages + 'conf.gif', 18, 16);
+	imgStore.add('CONFSelected', prjImages + 'confselected.gif', 18, 16);
+	imgStore.add('CONFMouseOver', prjImages + 'confselected.gif', 18, 16);
+	imgStore.add('CPP', prjImages + 'cpp.gif', 18, 16);
+	imgStore.add('CPPSelected', prjImages + 'cppselected.gif', 18, 16);
+	imgStore.add('CPPMouseOver', prjImages + 'cppselected.gif', 18, 16);
+	imgStore.add('DLM', prjImages + 'dlm.gif', 18, 16);
+	imgStore.add('DLMSelected', prjImages + 'dlmselected.gif', 18, 16);
+	imgStore.add('DLMMouseOver', prjImages + 'dlmselected.gif', 18, 16);
+	imgStore.add('DO', prjImages + 'do.gif', 18, 16);
+	imgStore.add('DOSelected', prjImages + 'doselected.gif', 18, 16);
+	imgStore.add('DOMouseOver', prjImages + 'doselected.gif', 18, 16);
+	imgStore.add('DRW', prjImages + 'drw.gif', 18, 16);
+	imgStore.add('DRWSelected', prjImages + 'drwselected.gif', 18, 16);
+	imgStore.add('DRWMouseOver', prjImages + 'drwselected.gif', 18, 16);
+	imgStore.add('EDN', prjImages + 'edn.gif', 18, 16);
+	imgStore.add('EDNSelected', prjImages + 'ednselected.gif', 18, 16);
+	imgStore.add('EDNMouseOver', prjImages + 'ednselected.gif', 18, 16);
+	imgStore.add('HP', prjImages + 'hp.gif', 18, 16);
+	imgStore.add('HPSelected', prjImages + 'hpselected.gif', 18, 16);
+	imgStore.add('HPMouseOver', prjImages + 'hpselected.gif', 18, 16);
+	imgStore.add('HTM', prjImages + 'htm.gif', 18, 16);
+	imgStore.add('HTMSelected', prjImages + 'htmselected.gif', 18, 16);
+	imgStore.add('HTMMouseOver', prjImages + 'htmselected.gif', 18, 16);
+	imgStore.add('LST', prjImages + 'lst.gif', 18, 16);
+	imgStore.add('LSTSelected', prjImages + 'lstselected.gif', 18, 16);
+	imgStore.add('LSTMouseOver', prjImages + 'lstselected.gif', 18, 16);
+	imgStore.add('PL', prjImages + 'pl.gif', 18, 16);
+	imgStore.add('PLSelected', prjImages + 'plselected.gif', 18, 16);
+	imgStore.add('PLMouseOver', prjImages + 'plselected.gif', 18, 16);
+	imgStore.add('SDF', prjImages + 'sdf.gif', 18, 16);
+	imgStore.add('SDFSelected', prjImages + 'sdfselected.gif', 18, 16);
+	imgStore.add('SDFMouseOver', prjImages + 'sdfselected.gif', 18, 16);
+	imgStore.add('SYMB', prjImages + 'symb.gif', 18, 16);
+	imgStore.add('SYMBSelected', prjImages + 'symbselected.gif', 18, 16);
+	imgStore.add('SYMBMouseOver', prjImages + 'symbselected.gif', 18, 16);
+	imgStore.add('TCL', prjImages + 'tcl.gif', 18, 16);
+	imgStore.add('TCLSelected', prjImages + 'tclselected.gif', 18, 16);
+	imgStore.add('TCLMouseOver', prjImages + 'tclselected.gif', 18, 16);
+	imgStore.add('TXT', prjImages + 'txt.gif', 18, 16);
+	imgStore.add('TXTSelected', prjImages + 'txtselected.gif', 18, 16);
+	imgStore.add('TXTMouseOver', prjImages + 'txtselected.gif', 18, 16);
+	imgStore.add('UND', prjImages + 'und.gif', 18, 16);
+	imgStore.add('UNDSelected', prjImages + 'undselected.gif', 18, 16);
+	imgStore.add('UNDMouseOver', prjImages + 'undselected.gif', 18, 16);
+	imgStore.add('UNDEF', prjImages + 'undef.gif', 18, 16);
+	imgStore.add('UNDEFSelected', prjImages + 'undefselected.gif', 18, 16);
+	imgStore.add('UNDEFMouseOver', prjImages + 'undefselected.gif', 18, 16);
+	imgStore.add('V', prjImages + 'v.gif', 18, 16);
+	imgStore.add('VSelected', prjImages + 'vselected.gif', 18, 16);
+	imgStore.add('VMouseOver', prjImages + 'vselected.gif', 18, 16);
+	imgStore.add('VHD', prjImages + 'vhd.gif', 18, 16);
+	imgStore.add('VHDSelected', prjImages + 'vhdselected.gif', 18, 16);
+	imgStore.add('VHDMouseOver', prjImages + 'vhdselected.gif', 18, 16);
+	imgStore.add('VLS', prjImages + 'vls.gif', 18, 16);
+	imgStore.add('VLSSelected', prjImages + 'vlsselected.gif', 18, 16);
+	imgStore.add('VLSMouseOver', prjImages + 'vlsselected.gif', 18, 16);
+	imgStore.add('VSSVER', prjImages + 'vssver.gif', 18, 16);
+	imgStore.add('VSSVERSelected', prjImages + 'vssverselected.gif', 18, 16);
+	imgStore.add('VSSVERMouseOver', prjImages + 'vssverselected.gif', 18, 16);
+	imgStore.add('VTB', prjImages + 'vtb.gif', 18, 16);
+	imgStore.add('VTBSelected', prjImages + 'vtbselected.gif', 18, 16);
+	imgStore.add('VTBMouseOver', prjImages + 'vtbselected.gif', 18, 16);
+	imgStore.add('XNF', prjImages + 'xnf.gif', 18, 16);
+	imgStore.add('XNFSelected', prjImages + 'xnfselected.gif', 18, 16);
+	imgStore.add('XNFMouseOver', prjImages + 'xnfselected.gif', 18, 16);
+
+}
+function initialise() {
+if ((theBrowser.hasDHTML) && (theBrowser.slowDHTML)) {theBrowser.hasDHTML = false;}
+
+	// Tell joust where to find the various index files it needs
+	index1 = 'index.htm';
+	index2 = 'index2.htm';
+	index3 = 'index3.htm';
+	
+	// Set up parameters to control menu behaviour
+	theMenu.autoScrolling = true;	
+	theMenu.modalFolders = false;
+	theMenu.linkOnExpand = false;
+	theMenu.toggleOnLink = false;
+	theMenu.showAllAsLinks = false;
+	theMenu.savePage = true;
+	theMenu.tipText = "status";
+	theMenu.selectParents = false;
+	theMenu.name = "theMenu";
+	theMenu.container = "self.menu";
+	theMenu.reverseRef = "parent";
+	theMenu.contentFrame = "text";
+	theMenu.defaultTarget = "text";
+	
+	// Initialise all the icons
+	initOutlineIcons(theMenu.imgStore);
+	
+	// Now set up the menu with a whole lot of addEntry and addChild function calls
+var level0ID = -1;
+var level1ID = -1;
+var level2ID = -1;
+level0ID = theMenu.addChild(level0ID, "ACP", "usbhostslave", "info/index.htm", "");
+theMenu.entry[level0ID].isopen=true;
+level1ID = theMenu.addChild(level0ID, "Folder", "buffers", "", ""
+);level2ID = theMenu.addChild(level1ID, "V", "TxFifoBI.v", "src/buffers/TxFifoBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "fifoMem.v", "src/buffers/fifoMem.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "fifoRTL.v", "src/buffers/fifoRTL.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "RxFifo.v", "src/buffers/RxFifo.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "RxFifoBI.v", "src/buffers/RxFifoBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "simFifoMem.v", "src/buffers/simFifoMem.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "TxFifo.v", "src/buffers/TxFifo.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "busInterface", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "wishBoneBI.v", "src/busInterface/wishBoneBI.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "hostController", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "USBHostControlBI.v", "src/hostController/USBHostControlBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "directcontrol.asf", "src/hostController/directcontrol.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "directcontrol.v", "src/hostController/directcontrol.asf/directcontrol.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "getpacket.asf", "src/hostController/getpacket.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "getpacket.v", "src/hostController/getpacket.asf/getpacket.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "hctxportarbiter.asf", "src/hostController/hctxportarbiter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "hctxportarbiter.v", "src/hostController/hctxportarbiter.asf/hctxportarbiter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "hostcontroller.asf", "src/hostController/hostcontroller.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "hostcontroller.v", "src/hostController/hostcontroller.asf/hostcontroller.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sendpacket.asf", "src/hostController/sendpacket.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sendpacket.v", "src/hostController/sendpacket.asf/sendpacket.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sendpacketarbiter.asf", "src/hostController/sendpacketarbiter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sendpacketarbiter.v", "src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sendpacketcheckpreamble.asf", "src/hostController/sendpacketcheckpreamble.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sendpacketcheckpreamble.v", "src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sofcontroller.asf", "src/hostController/sofcontroller.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sofcontroller.v", "src/hostController/sofcontroller.asf/sofcontroller.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "softransmit.asf", "src/hostController/softransmit.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "softransmit.v", "src/hostController/softransmit.asf/softransmit.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "rxStatusMonitor.v", "src/hostController/rxStatusMonitor.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "speedCtrlMux.v", "src/hostController/speedCtrlMux.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbHostControl.v", "src/hostController/usbHostControl.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "hostSlaveMux", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "hostSlaveMuxBI.v", "src/hostSlaveMux/hostSlaveMuxBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "hostSlaveMux.v", "src/hostSlaveMux/hostSlaveMux.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "include", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "wishBoneBus_h.v", "src/include/wishBoneBus_h.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbConstants_h.v", "src/include/usbConstants_h.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbHostControl_h.v", "src/include/usbHostControl_h.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbSerialInterfaceEngine_h.v", "src/include/usbSerialInterfaceEngine_h.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbSlaveControl_h.v", "src/include/usbSlaveControl_h.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "serialInterfaceEngine", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "writeUSBWireData.v", "src/serialInterfaceEngine/writeUSBWireData.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "processRxBit.asf", "src/serialInterfaceEngine/processRxBit.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "processRxBit.v", "src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "processRxByte.asf", "src/serialInterfaceEngine/processRxByte.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "processRxByte.v", "src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "processTxByte.asf", "src/serialInterfaceEngine/processTxByte.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "processTxByte.v", "src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "siereceiver.asf", "src/serialInterfaceEngine/siereceiver.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "siereceiver.v", "src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "SIETransmitter.asf", "src/serialInterfaceEngine/SIETransmitter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "SIETransmitter.v", "src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "usbTxWireArbiter.asf", "src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "usbTxWireArbiter.v", "src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "lineControlUpdate.v", "src/serialInterfaceEngine/lineControlUpdate.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "readUSBWireData.v", "src/serialInterfaceEngine/readUSBWireData.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "updateCRC5.v", "src/serialInterfaceEngine/updateCRC5.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "updateCRC16.v", "src/serialInterfaceEngine/updateCRC16.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbSerialInterfaceEngine.v", "src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "slaveController", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "USBSlaveControlBI.v", "src/slaveController/USBSlaveControlBI.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "sctxportarbiter.asf", "src/slaveController/sctxportarbiter.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "sctxportarbiter.v", "src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "slavecontroller.asf", "src/slaveController/slavecontroller.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "slavecontroller.v", "src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "slaveDirectcontrol.asf", "src/slaveController/slaveDirectcontrol.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "slaveDirectcontrol.v", "src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "slaveGetpacket.asf", "src/slaveController/slaveGetpacket.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "slaveGetpacket.v", "src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "ASF", "slaveSendpacket.asf", "src/slaveController/slaveSendpacket.asf/index.htm", "");
+level3ID = theMenu.addChild(level2ID, "V", "slaveSendpacket.v", "src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "endpMux.v", "src/slaveController/endpMux.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "fifoMux.v", "src/slaveController/fifoMux.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "slaveRxStatusMonitor.v", "src/slaveController/slaveRxStatusMonitor.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "V", "usbSlaveControl.v", "src/slaveController/usbSlaveControl.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "wrapper", "", "");
+level2ID = theMenu.addChild(level1ID, "V", "usbHostSlave.v", "src/wrapper/usbHostSlave.v/index.htm", "");
+level1ID = theMenu.addEntry(level1ID, "Folder", "TestBench", "", "");
+level2ID = theMenu.addChild(level1ID, "VTB", "usbHostSlave_TB.v", "src/TestBench/usbHostSlave_TB.v/index.htm", "");
+level2ID = theMenu.addEntry(level2ID, "DO", "usbHostSlave_TB_runtest.do", "src/TestBench/usbHostSlave_TB_runtest.do/index.htm", "");
+
+	
+}
+
+self.defaultStatus = "";	
+
+//-->
+</script>
+
+</HEAD>
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+if (self.name == 'menu') {
+	// Sometimes, Netscape will try to load this index inside the menu frame.  I haven't
+	// worked out why but this will detect that situation and reset the location property.
+	self.location.href = "menu.htm";
+} else {
+	initialise();
+	var thePage = pageFromSearch('./splash/info.htm', theMenu, true);
+	
+	if (floatingMode) {
+		self.document.writeln('<frameset cols="100%" rows="*,48" onUnload="unloadFloating();" onResize="defaultResizeHandler();">');
+		self.document.writeln('<frame name="menu" src="menu.htm" scrolling="auto" marginwidth="1" marginheight="1" APPLICATION="yes">');
+		self.document.writeln('<frame name="menuCntrl" src="menucntrl.htm" scrolling="no" marginwidth="0" marginheight="0" APPLICATION="yes">');
+		self.document.writeln('</frameset>');
+	} else {
+		self.document.writeln('<frameset cols="230,*" rows="100%">');
+		self.document.writeln('<frameset cols="100%" rows="30,*,48">');
+		self.document.writeln('<frame name="menuCntrl" src="menucntrl.htm"  scrolling="no" FrameBorder="no" marginwidth="0" marginheight="0"  APPLICATION="yes">');
+		self.document.writeln('<frame name="menu" src="menu.htm" scrolling="auto" noresize="noresize"  marginwidth="1" marginheight="1" APPLICATION="yes">');
+		self.document.writeln('<frame name="Aldec" src="struct/aldec.htm" scrolling="no" FrameBorder="no"  marginwidth="0" marginheight="0" noresize="noresize" APPLICATION="yes">');
+		
+		self.document.writeln('</frameset>');
+		self.document.writeln('<frame name="text" src="' + thePage +'" scrolling="auto" APPLICATION="yes">');
+		self.document.writeln('</frameset>');
+		self.document.writeln('</frameset>');
+	}
+}
+//-->
+</SCRIPT>
+<NOSCRIPT>
+<BODY BGCOLOR="#FFFFCC">
+<h1>Joust Outliner</h1>
+<P>Your browser does not support JavaScript (if you are using Netscape 3 or higher or Microsoft Internet
+Explorer 4 or higher you may have JavaScript turned off in your preferences), so this page,
+does not include site navigation features. If you use
+a JavaScript-capable browser, such as Microsoft <A HREF="http://microsoft.com/ie/ie.htm">Internet
+Explorer version 3.0</A> or <A HREF="http://www.netscape.com/comprod/mirror/">Netscape Navigator
+version 2.0</A>, you'll have a much more pleasant experience navigating around this site.</P>
+
+<P><I><B>Opera Users:</B> Although Opera 3.0 supports JavaScript, there is a bug in their implementation 
+which prevents the menu system on this site from working.  Opera 3.2 fixes the problem.</I></P>
+
+<P><I><B>Note:</B> There is a know bug in Netscape Navigator version 4.0.x which will cause you to see this message
+if you have the local cache turned off.</I></P>
+
+<P>If you have any problems with this site, please contact the Webmaster.</P>
+
+<P>Click <a HREF="index3.htm">here</a> to see the non-JavaScript version of this site.</P>
+
+<A HREF="robots.htm"> </A>
+</BODY>
+</NOSCRIPT>
+
+</HTML>

Property changes on: common/components/usbhostslave/tags/start/doc/html/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
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Index: common/components/usbhostslave/tags/start/doc/html/splash/AVhdlRegular.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/splash/AVhdlRegular.bmp
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/splash/info.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/splash/info.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/splash/info.htm	(revision 264)
@@ -0,0 +1,22 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<html>
+<head>
+<title>Active-HDL HTML Export</TITLE>
+</head>
+<body
+		bgcolor="#C0C0C0"
+		background="./../images/aldec.gif">
+
+<div align="center">
+<h1><a name="top">Active-HDL HTML Export</a></h1>
+<hr>
+<img src="avhdlregular.bmp" width="300" height="268" 
+		ALT="Aldec logo"   
+		hspace="0" vspace="0" border="0" align="middle">
+<hr>
+<h4>Copyright&copy 2004 ALDEC, Inc., Henderson, NV USA.<br> 
+All Rights Reserved.</h4><br>
+<h4>Aldec homepage <A HREF="http://www.aldec.com/">http://www.aldec.com</A></h4>
+</div>
+</body>
+</html>
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/doc/html/splash/info.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/buffers/RxFifoBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/buffers/RxFifoBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/buffers/RxFifoBI.v/index.htm	(revision 264)
@@ -0,0 +1,143 @@
+<html>
+<head>
+<title>RxFifoBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// RxfifoBI.v                                                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:29 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"wishBoneBus_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>RxfifoBI</span> (
+  <span id=t_idt>address</span>, 
+  <span id=t_idt>writeEn</span>, 
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>, 
+  <span id=t_idt>fifoSelect</span>,
+  <span id=t_idt>fifoDataIn</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>,
+  <span id=t_idt>fifoREn</span>,
+  <span id=t_idt>fifoEmpty</span>,
+  <span id=t_idt>forceEmpty</span>,
+  <span id=t_idt>numElementsInFifo</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>output</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoSelect</span>;
+
+
+<span id=t_kwd>wire</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoSelect</span>;
+
+
+<span id=t_com>//sync write</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoSelect</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+  <span id=t_idt>address</span> == `<span id=t_idt>FIFO_CONTROL_REG</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>busDataIn</span>[<span id=t_cns>0</span>] == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>forceEmpty</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+    <span id=t_idt>forceEmpty</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span> <span id=t_idt>fifoDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>numElementsInFifo</span> <span id=t_kwd>or</span> <span id=t_idt>fifoEmpty</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+      `<span id=t_idt>FIFO_DATA_REG</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>fifoDataIn</span>;
+      `<span id=t_idt>FIFO_STATUS_REG</span> : <span id=t_idt>busDataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>fifoEmpty</span>};
+      `<span id=t_idt>FIFO_DATA_COUNT_MSB</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>numElementsInFifo</span>[<span id=t_cns>15</span>:<span id=t_cns>8</span>];
+      `<span id=t_idt>FIFO_DATA_COUNT_LSB</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>numElementsInFifo</span>[<span id=t_cns>7</span>:<span id=t_cns>0</span>];
+      <span id=t_kwd>default</span>: <span id=t_idt>busDataOut</span> &lt;= <span id=t_cns>8'h00</span>; 
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//generate fifo read strobe</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span> <span id=t_idt>writeEn</span> <span id=t_kwd>or</span> <span id=t_idt>strobe_i</span> <span id=t_kwd>or</span> <span id=t_idt>fifoSelect</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>address</span> == `<span id=t_idt>FIFO_DATA_REG</span> &amp;&amp;   <span id=t_idt>writeEn</span> == <span id=t_cns>1'b0</span> &amp;&amp; 
+  <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp;   <span id=t_idt>fifoSelect</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>fifoREn</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+    <span id=t_idt>fifoREn</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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Added: svn:executable
## -0,0 +1 ##
+*
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Index: common/components/usbhostslave/tags/start/doc/html/src/buffers/fifoRTL.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/buffers/fifoRTL.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/buffers/fifoRTL.v/index.htm	(revision 264)
@@ -0,0 +1,158 @@
+<html>
+<head>
+<title>fifoRTL.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// fifoRTL.v                                                    ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////  parameterized fifo. fifo depth is restricted to 2^ADDR_WIDTH</span>
+<span id=t_com>////  No protection against over runs and under runs.</span>
+<span id=t_com>////  User must check full and empty flags before accessing fifo</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:28 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>fifoRTL</span>(<span id=t_idt>clk</span>, <span id=t_idt>rst</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>fifoWEn</span>, <span id=t_idt>fifoREn</span>, <span id=t_idt>fifoFull</span>, <span id=t_idt>fifoEmpty</span>, <span id=t_idt>forceEmpty</span>, <span id=t_idt>numElementsInFifo</span>);
+<span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_WIDTH</span> = <span id=t_cns>8</span>;
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>output</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>]<span id=t_idt>numElementsInFifo</span>; <span id=t_com>//note that this implies a max fifo depth of 65536</span>
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>reg</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>15</span>:<span id=t_cns>0</span>]<span id=t_idt>numElementsInFifo</span>;
+
+
+<span id=t_com>// local registers</span>
+<span id=t_kwd>reg</span>  [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferInIndex</span>;
+<span id=t_kwd>reg</span>  [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferOutIndex</span>;
+<span id=t_kwd>reg</span>  [<span id=t_idt>ADDR_WIDTH</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferCnt</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>fifoREnDelayed</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromMem</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span> || <span id=t_idt>forceEmpty</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>bufferCnt</span> &lt;= <span id=t_cns>0</span>;
+    <span id=t_idt>fifoFull</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_idt>fifoEmpty</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_cns>0</span>;
+   <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_cns>0</span>;
+    <span id=t_idt>fifoREnDelayed</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span>
+    <span id=t_kwd>begin</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>fifoREn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREnDelayed</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromMem</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>fifoREnDelayed</span> &lt;= <span id=t_idt>fifoREn</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>fifoWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREn</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> + <span id=t_cns>1</span>;
+        <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_idt>bufferInIndex</span> + <span id=t_cns>1</span>;
+      <span id=t_kwd>end</span> 
+      <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>fifoWEn</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>fifoREn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREnDelayed</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> - <span id=t_cns>1</span>;
+        <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_idt>bufferOutIndex</span> + <span id=t_cns>1</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>fifoWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoREnDelayed</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_idt>bufferOutIndex</span> + <span id=t_cns>1</span>;
+        <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_idt>bufferInIndex</span> + <span id=t_cns>1</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span>[<span id=t_idt>ADDR_WIDTH</span>] == <span id=t_cns>1'b1</span>)
+        <span id=t_idt>fifoFull</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>else</span>
+        <span id=t_idt>fifoFull</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_kwd>if</span> (|<span id=t_idt>bufferCnt</span> == <span id=t_cns>1'b0</span>) 
+        <span id=t_idt>fifoEmpty</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>else</span>
+        <span id=t_idt>fifoEmpty</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//pad bufferCnt with leading zeroes</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>bufferCnt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>numElementsInFifo</span> &lt;= { {<span id=t_cns>16</span>-<span id=t_idt>ADDR_WIDTH</span>+<span id=t_cns>1</span>{<span id=t_cns>1'b0</span>}}, <span id=t_idt>bufferCnt</span> };
+<span id=t_kwd>end</span>
+
+<span id=t_idt>fifoMem</span> #(<span id=t_idt>FIFO_WIDTH</span>, <span id=t_idt>FIFO_DEPTH</span>, <span id=t_idt>ADDR_WIDTH</span>)  <span id=t_idt>u_fifoMem</span> (
+  .<span id=t_idt>addrIn</span>(<span id=t_idt>bufferInIndex</span>),
+  .<span id=t_idt>addrOut</span>(<span id=t_idt>bufferOutIndex</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>dataIn</span>),
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>fifoWEn</span>),
+  .<span id=t_idt>readEn</span>(<span id=t_idt>fifoREn</span>),
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataFromMem</span>));
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/buffers/fifoRTL.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="directcontrol" alt="directcontrol"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol.v/index.htm	(revision 264)
@@ -0,0 +1,210 @@
+<html>
+<head>
+<title>directcontrol.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// directControl</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:36 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>directControl</span> (<span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortGnt</span>, <span id=t_idt>HCTxPortRdy</span>, <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>directControlEn</span>, <span id=t_idt>directControlLineState</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directControlEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directControlLineState</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortWEn</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>next_HCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>, <span id=t_idt>next_HCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>next_HCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>next_HCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directControlEn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directControlLineState</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: drctCntl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_DC</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_DRCT_CNTL</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_WAIT_GNT</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_CHK_LOOP</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_WAIT_RDY</span> <span id=t_cns>3'b100</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_FIN</span> <span id=t_cns>3'b101</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_GNT</span> <span id=t_cns>3'b110</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_RDY</span> <span id=t_cns>3'b111</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_drctCntl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_drctCntl</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// diagram ACTION</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: drctCntl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>directControlLineState</span> <span id=t_kwd>or</span> <span id=t_idt>directControlEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_drctCntl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>drctCntl_NextState</span>
+  <span id=t_idt>NextState_drctCntl</span> &lt;= <span id=t_idt>CurrState_drctCntl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_idt>HCTxPortReq</span>;
+  <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_idt>HCTxPortWEn</span>;
+  <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>HCTxPortData</span>;
+  <span id=t_idt>next_HCTxPortCntl</span> &lt;= <span id=t_idt>HCTxPortCntl</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_drctCntl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_DC</span>:
+     <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+   `<span id=t_idt>CHK_DRCT_CNTL</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>directControlEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_GNT</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>IDLE_WAIT_GNT</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DRCT_CNTL_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>;
+   `<span id=t_idt>DRCT_CNTL_CHK_LOOP</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>directControlEn</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_CHK_LOOP</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>directControlLineState</span>};
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_DIRECT_CONTROL</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>IDLE_WAIT_RDY</span>;
+   `<span id=t_idt>IDLE_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_drctCntl</span> &lt;= `<span id=t_idt>IDLE_FIN</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_IDLE</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>drctCntl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_drctCntl</span> &lt;= `<span id=t_idt>START_DC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_drctCntl</span> &lt;= <span id=t_idt>NextState_drctCntl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>drctCntl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>next_HCTxPortCntl</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>next_HCTxPortData</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_idt>next_HCTxPortWEn</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_idt>next_HCTxPortReq</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index127.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index127.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index127.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar127.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram127.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index127.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/lastover.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/lastover.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/prev.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/prev.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/images/wfm/updown.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/images/wfm/updown.gif
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/menu.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/menu.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/menu.htm	(revision 264)
@@ -0,0 +1,209 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
+<HTML>
+<HEAD>
+<TITLE>The Joust Outliner - The Menu</TITLE>
+<META NAME="ROBOTS" CONTENT="NOINDEX,NOFOLLOW">
+
+<STYLE ID="JoustStyles" TYPE="text/css">
+<!--
+	.menuItem {position:absolute; visibility:hidden; left:0px;}
+	.menuItem BR { clear: both; }
+	.node { color: black;
+		font-family : "Helvetica", "Arial", "MS Sans Serif", sans-serif;
+		font-size : 9pt;}
+	.node A:link { color: black; text-decoration: none; }
+	.node A:visited { color: black; text-decoration: none; }
+	.node A:active { color: black; text-decoration: none; }
+	.node A:hover { color: black; text-decoration: none; }
+	.leaf { color: black;
+		font-family : "Helvetica", "Arial", "MS Sans Serif", sans-serif;
+		font-size : 9pt;}
+	.leaf A:link { color: black; text-decoration: none;}
+	.leaf A:visited { color: black; text-decoration: none; }
+	.leaf A:active { color: black; text-decoration: none; }
+	.leaf A:hover { color: black; text-decoration: none; }
+	.nolink { color: #808080;
+		font-family : "Helvetica", "Arial", "MS Sans Serif", sans-serif;
+		font-size : 9pt;}
+	.nolink A:link { color: #808080; text-decoration: none;}
+	.nolink A:visited { color: #808080; text-decoration: none; }
+	.nolink A:active { color: #808080; text-decoration: none; }
+	.nolink A:hover { color: #808080; text-decoration: none; }
+-->
+</STYLE>
+
+<!--
+Joust Outliner Version 2.5.4
+(c) Copyright 1996-2001, MITEM (Europe) Ltd. All rights reserved.
+This code may be freely copied and distributed provided that it is accompanied by this 
+header.  For full details of the Joust license, as well as documentation and help, go 
+to http://www.ivanpeters.com/.
+
+Do not modify anything between here and the "End of Joust" marker unless you know what you
+are doing.  
+-->
+<script language="JavaScript">
+<!--  
+var theMenuRef = "parent.theMenu";
+var theMenu = eval(theMenuRef);
+var theBrowser = parent.theBrowser;
+var belowMenu = null;
+var menuStart = 0;
+
+if (parent.theBrowser) {
+	if (parent.theBrowser.canOnError) {window.onerror = parent.defOnError;}
+}
+
+if (theMenu) {
+	theMenu.amBusy = true;
+	if (theBrowser.hasDHTML) {
+		if (document.all) {
+			with (document.styleSheets["JoustStyles"]) {
+				addRule ("#menuTop", "position:absolute");
+				addRule ("#menuBottom", "position:absolute");
+				addRule ("#menuBottom", "visibility:hidden");
+				addRule ("#statusMsgDiv", "position:absolute");
+			}
+		} else {
+			if (document.layers) {
+				document.ids.menuTop.position = "absolute";
+				document.ids.menuBottom.position = "absolute";
+				document.ids.menuBottom.visibility = "hidden";
+				document.ids.statusMsgDiv.position = "absolute";
+			} else {
+				if (theBrowser.hasW3CDOM) {
+					var styleSheetElement = document.styleSheets[0];
+    				var styleSheetLength = styleSheetElement.cssRules.length;
+					styleSheetElement.insertRule("#menuTop { position:absolute } ", styleSheetLength++);
+					styleSheetElement.insertRule("#menuBottom { position:absolute } ", styleSheetLength++);
+					styleSheetElement.insertRule("#menuBottom { visibility:hidden } ", styleSheetLength++);
+					styleSheetElement.insertRule("#statusMsgDiv { position:absolute } ", styleSheetLength++);
+				}
+			}
+		}
+	}
+}
+function getDHTMLObj(objName) {
+	if (theBrowser.hasW3CDOM) {
+		return document.getElementById(objName).style;
+	} else {
+		return eval('document' + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLStyleObj);
+	}
+}
+function getDHTMLObjHeight(objName) {
+	if (theBrowser.hasW3CDOM) {
+		return document.getElementById(objName).offsetHeight;
+	} else {
+		return eval('document' + theBrowser.DHTMLRange + '.' + objName + theBrowser.DHTMLDivHeight);
+	}
+}
+function myVoid() { ; }
+function setMenuHeight(theHeight) {
+	getDHTMLObj('menuBottom').top = theHeight;
+}
+function drawStatusMsg() {
+	if (document.layers) {
+		document.ids.statusMsgDiv.top = menuStart;
+	} else{
+		if (document.all) {
+			document.styleSheets["JoustStyles"].addRule ("#statusMsgDiv", "top:" + menuStart);
+		}
+	}
+	document.writeln('<DIV ID="statusMsgDiv"><CENTER>Building Menu...</CENTER></DIV>');
+}
+function drawLimitMarker() {
+	var b = theBrowser;
+	if (theMenu && b.hasDHTML && b.needLM) {
+		var limitPos = theMenu.maxHeight + menuStart + getDHTMLObjHeight('menuBottom');
+		if (b.code == 'NS') {
+			document.ids.limitMarker.position = "absolute";
+			document.ids.limitMarker.visibility = "hidden";
+			document.ids.limitMarker.top = limitPos;
+		}
+		if (b.code == 'MSIE') {
+			with (document.styleSheets["JoustStyles"]) {
+				addRule ("#limitMarker", "position:absolute");
+				addRule ("#limitMarker", "visibility:hidden");
+				addRule ("#limitMarker", "top:" + limitPos + "px");
+			}
+		}
+		document.writeln('<DIV ID="limitMarker">&nbsp;</DIV>');
+	}
+}
+function setTop() {
+	if (theMenu && theBrowser.hasDHTML) {
+		if (getDHTMLObj('menuTop')) {
+			drawStatusMsg();
+			menuStart = getDHTMLObjHeight("menuTop");
+		} else {
+			theBrowser.hasDHTML = false;
+		}
+	}
+}
+function setBottom() {
+	if (theMenu) {
+		if (theBrowser.hasDHTML) {
+			var mb = getDHTMLObj('menuBottom');
+			if (mb) {
+				drawLimitMarker();
+				getDHTMLObj("statusMsgDiv").visibility = 'hidden';
+				menuStart = getDHTMLObjHeight("menuTop");
+				theMenu.refreshDHTML();
+				if (theMenu.autoScrolling) {theMenu.scrollTo(theMenu.lastPMClicked);}
+				mb.visibility = 'visible';
+			} else {
+				theBrowser.hasDHTML = false;
+				self.location.reload();
+			}
+		}
+		theMenu.amBusy = false;
+	}
+}
+
+function frameResized() {if (theBrowser.hasDHTML) {theMenu.refreshDHTML();}}
+
+//	############################   End of Joust   ############################
+
+if (self.name != 'menu') { self.location.href = 'index.htm'; }
+//-->
+</script>
+</HEAD>
+<BODY bgcolor="white" LINK="#000000" marginwidth="1" marginheight="1" onResize="frameResized();" background="images/aldec.gif" bgproperties="FIXED">
+
+<DIV ID="menuTop">
+<!-- Place anything you want to appear before the menu between these DIV tags. -->
+</DIV>
+
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+setTop();
+//-->
+</SCRIPT>
+
+<!-- Set up any font's, colours, etc. that should apply to the menu here -->
+<FONT FACE="GENEVA, ARIAL, MS SANS SERIF, SANS-SERIF" SIZE="1">
+
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+if (theMenu) {
+	parent.DrawMenu(theMenu);
+}
+//-->
+</SCRIPT>
+
+<!-- Close any tags you set up for the menu here -->
+</FONT>
+
+<DIV ID="menuBottom">
+<!-- Place anything you want to appear after the menu between these DIV tags. -->
+&nbsp;
+</DIV>
+
+<SCRIPT LANGUAGE="JavaScript">
+<!--
+setBottom();
+//-->
+</SCRIPT>
+
+</BODY>
+</HTML>

Property changes on: common/components/usbhostslave/tags/start/doc/html/menu.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/TestBench/usbHostSlave_TB.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/TestBench/usbHostSlave_TB.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/TestBench/usbHostSlave_TB.v/index.htm	(revision 264)
@@ -0,0 +1,111 @@
+<html>
+<head>
+<title>usbHostSlave_TB.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//--------------------------------------------------------------------------------------------------</span>
+<span id=t_com>//</span>
+<span id=t_com>// Title       : usbHostSlave_tb</span>
+<span id=t_com>// Design      : usbhostslave</span>
+<span id=t_com>// Author      : Steve</span>
+<span id=t_com>// Company     : Base2Designs</span>
+<span id=t_com>//</span>
+<span id=t_com>//-------------------------------------------------------------------------------------------------</span>
+<span id=t_com>//</span>
+<span id=t_com>// File        : usbHostSlave_TB.v</span>
+<span id=t_com>// Generated   : Thu Jun 10 22:02:35 2004</span>
+<span id=t_com>// From        : usbHostSlave_TB_settings.txt</span>
+<span id=t_com>// By          : tb_verilog.pl ver. ver 1.2s</span>
+<span id=t_com>//</span>
+<span id=t_com>//-------------------------------------------------------------------------------------------------</span>
+<span id=t_com>//</span>
+<span id=t_com>// Description : </span>
+<span id=t_com>//</span>
+<span id=t_com>//-------------------------------------------------------------------------------------------------</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ps</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_kwd>module</span> <span id=t_idt>usbHostSlave_tb</span>;
+<span id=t_com>//Parameters declaration: </span>
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>HOST_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>HOST_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>HOST_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>HOST_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP0_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP0_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP0_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP0_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP1_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP1_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP1_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP1_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP2_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP2_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP2_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP2_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP3_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP3_FIFO_DEPTH</span> = <span id=t_cns>64</span>;
+<span id=t_kwd>defparam</span> <span id=t_idt>UUT</span>.<span id=t_idt>EP3_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+<span id=t_kwd>parameter</span> <span id=t_idt>EP3_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;
+
+<span id=t_com>//Internal signals declarations:</span>
+<span id=t_kwd>reg</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>address_i</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>data_i</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>data_o</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>ack_o</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSOFSentIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostConnEventIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostResumeIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostTransDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveSOFRxedIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveResetEventIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveResumeIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveTransDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveNAKSentIntOut</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataInTick</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataOutTick</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireCtrlOut</span>;
+
+
+
+<span id=t_com>// Unit Under Test port map</span>
+  <span id=t_idt>usbHostSlave</span> <span id=t_idt>UUT</span> (
+   .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+   .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+   .<span id=t_idt>address_i</span>(<span id=t_idt>address_i</span>),
+   .<span id=t_idt>data_i</span>(<span id=t_idt>data_i</span>),
+   .<span id=t_idt>data_o</span>(<span id=t_idt>data_o</span>),
+   .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>),
+   .<span id=t_idt>strobe_i</span>(<span id=t_idt>strobe_i</span>),
+   .<span id=t_idt>ack_o</span>(<span id=t_idt>ack_o</span>),
+   .<span id=t_idt>hostSOFSentIntOut</span>(<span id=t_idt>hostSOFSentIntOut</span>),
+   .<span id=t_idt>hostConnEventIntOut</span>(<span id=t_idt>hostConnEventIntOut</span>),
+   .<span id=t_idt>hostResumeIntOut</span>(<span id=t_idt>hostResumeIntOut</span>),
+   .<span id=t_idt>hostTransDoneIntOut</span>(<span id=t_idt>hostTransDoneIntOut</span>),
+   .<span id=t_idt>slaveSOFRxedIntOut</span>(<span id=t_idt>slaveSOFRxedIntOut</span>),
+   .<span id=t_idt>slaveResetEventIntOut</span>(<span id=t_idt>slaveResetEventIntOut</span>),
+   .<span id=t_idt>slaveResumeIntOut</span>(<span id=t_idt>slaveResumeIntOut</span>),
+   .<span id=t_idt>slaveTransDoneIntOut</span>(<span id=t_idt>slaveTransDoneIntOut</span>),
+    .<span id=t_idt>slaveNAKSentIntOut</span>(<span id=t_idt>slaveNAKSentIntOut</span>),
+   .<span id=t_idt>USBWireDataIn</span>(<span id=t_idt>USBWireDataIn</span>),
+   .<span id=t_idt>USBWireDataInTick</span>(<span id=t_idt>USBWireDataInTick</span>),
+   .<span id=t_idt>USBWireDataOut</span>(<span id=t_idt>USBWireDataOut</span>),
+   .<span id=t_idt>USBWireDataOutTick</span>(<span id=t_idt>USBWireDataOutTick</span>),
+   .<span id=t_idt>USBWireCtrlOut</span>(<span id=t_idt>USBWireCtrlOut</span>));
+
+<span id=t_kwd>initial</span>
+  <span id=t_sys>$monitor</span>(<span id=t_sys>$realtime</span>,,<span id=t_cns>"ps %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h "</span>,<span id=t_idt>clk</span>,<span id=t_idt>rst</span>,<span id=t_idt>address_i</span>,<span id=t_idt>data_i</span>,<span id=t_idt>data_o</span>,<span id=t_idt>writeEn</span>,<span id=t_idt>strobe_i</span>,<span id=t_idt>ack_o</span>,<span id=t_idt>hostSOFSentIntOut</span>,<span id=t_idt>hostConnEventIntOut</span>,<span id=t_idt>hostResumeIntOut</span>,<span id=t_idt>hostTransDoneIntOut</span>,<span id=t_idt>slaveSOFRxedIntOut</span>,<span id=t_idt>slaveResetEventIntOut</span>,<span id=t_idt>slaveResumeIntOut</span>,<span id=t_idt>slaveTransDoneIntOut</span>,<span id=t_idt>USBWireDataIn</span>,<span id=t_idt>USBWireDataInTick</span>,<span id=t_idt>USBWireDataOut</span>,<span id=t_idt>USBWireDataOutTick</span>,<span id=t_idt>USBWireCtrlOut</span>);
+<span id=t_kwd>endmodule</span>
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/TestBench/usbHostSlave_TB.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/buffers/RxFifo.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/buffers/RxFifo.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/buffers/RxFifo.v/index.htm	(revision 264)
@@ -0,0 +1,142 @@
+<html>
+<head>
+<title>RxFifo.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// RxFifo.v                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536</span>
+<span id=t_com>////  fifo read access via bus interface, fifo write access is direct</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:29 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>RxFifo</span>(
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>, 
+  <span id=t_idt>fifoWEn</span>, 
+  <span id=t_idt>fifoFull</span>,
+  <span id=t_idt>busAddress</span>, 
+  <span id=t_idt>busWriteEn</span>, 
+  <span id=t_idt>busStrobe_i</span>,
+  <span id=t_idt>busFifoSelect</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>,
+  <span id=t_idt>fifoDataIn</span>  );
+  <span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busWriteEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>busFifoSelect</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fifoWEn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busWriteEn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>busFifoSelect</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataIn</span>;
+
+<span id=t_com>//internal wires and regs</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromFifoToBus</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoREn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoEmpty</span>;
+
+<span id=t_idt>fifoRTL</span> #(<span id=t_cns>8</span>, <span id=t_idt>FIFO_DEPTH</span>, <span id=t_idt>ADDR_WIDTH</span>) <span id=t_idt>u_fifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>fifoDataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataFromFifoToBus</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>fifoWEn</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>fifoREn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>fifoFull</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>fifoEmpty</span>), 
+  .<span id=t_idt>forceEmpty</span>(<span id=t_idt>forceEmpty</span>), 
+  .<span id=t_idt>numElementsInFifo</span>(<span id=t_idt>numElementsInFifo</span>) );
+  
+<span id=t_idt>RxfifoBI</span> <span id=t_idt>u_RxfifoBI</span>(
+  .<span id=t_idt>address</span>(<span id=t_idt>busAddress</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>busWriteEn</span>), 
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>busStrobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoSelect</span>(<span id=t_idt>busFifoSelect</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>dataFromFifoToBus</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>busDataOut</span>),
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>fifoREn</span>),
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>fifoEmpty</span>),
+  .<span id=t_idt>forceEmpty</span>(<span id=t_idt>forceEmpty</span>),
+  .<span id=t_idt>numElementsInFifo</span>(<span id=t_idt>numElementsInFifo</span>)
+  );
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/buffers/RxFifo.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/buffers/fifoMem.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/buffers/fifoMem.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/buffers/fifoMem.v/index.htm	(revision 264)
@@ -0,0 +1,114 @@
+<html>
+<head>
+<title>fifoMem.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// fifoMem.v                                                    ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:28 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>fifoMem</span>( <span id=t_idt>addrIn</span>, <span id=t_idt>addrOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>writeEn</span>, <span id=t_idt>readEn</span>, <span id=t_idt>dataOut</span>);
+  <span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_WIDTH</span> = <span id=t_cns>8</span>;
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>output</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>readEn</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrIn</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrOut</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>readEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrOut</span>;
+
+
+<span id=t_com>/* generic_dpram #(ADDR_WIDTH, FIFO_WIDTH) u_generic_dpram(</span>
+<span id=t_com>  // Generic synchronous dual-port RAM interface</span>
+<span id=t_com>  .rclk(clk), </span>
+<span id=t_com>  .rrst(1'b0), </span>
+<span id=t_com>  .rce(1'b1), </span>
+<span id=t_com>  .oe(readEn), </span>
+<span id=t_com>  .raddr(addrOut), </span>
+<span id=t_com>  .do(dataOut),</span>
+<span id=t_com>  .wclk(clk), </span>
+<span id=t_com>  .wrst(1'b0), </span>
+<span id=t_com>  .wce(1'b1),</span>
+<span id=t_com>  .we(writeEn), </span>
+<span id=t_com>  .waddr(addrIn), </span>
+<span id=t_com>  .di(dataIn)</span>
+<span id=t_com>); */</span>
+
+
+ <span id=t_idt>simFifoMem</span> #(<span id=t_idt>FIFO_WIDTH</span>, <span id=t_idt>FIFO_DEPTH</span>, <span id=t_idt>ADDR_WIDTH</span>)  <span id=t_idt>u_simFifoMem</span> (
+  .<span id=t_idt>addrIn</span>(<span id=t_idt>addrIn</span>),
+  .<span id=t_idt>addrOut</span>(<span id=t_idt>addrOut</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>dataIn</span>),
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>),
+  .<span id=t_idt>readEn</span>(<span id=t_idt>readEn</span>),
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataOut</span>));  
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/buffers/fifoMem.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/USBHostControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/USBHostControlBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/USBHostControlBI.v/index.htm	(revision 264)
@@ -0,0 +1,276 @@
+<html>
+<head>
+<title>USBHostControlBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBHostControlBI.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:11 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+ 
+<span id=t_kwd>module</span> <span id=t_idt>USBHostControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>SOFSentIntOut</span>, <span id=t_idt>connEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>TxTransTypeReg</span>, <span id=t_idt>TxSOFEnableReg</span>,
+  <span id=t_idt>TxAddrReg</span>, <span id=t_idt>TxEndPReg</span>, <span id=t_idt>frameNumIn</span>, 
+  <span id=t_idt>RxPktStatusIn</span>, <span id=t_idt>RxPIDIn</span>,
+  <span id=t_idt>connectStateIn</span>,
+  <span id=t_idt>SOFSentIn</span>, <span id=t_idt>connEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>,
+  <span id=t_idt>hostControlSelect</span>,
+  <span id=t_idt>clrTransReq</span>,
+  <span id=t_idt>preambleEn</span>,
+  <span id=t_idt>SOFSync</span>,
+  <span id=t_idt>TxLineState</span>,
+  <span id=t_idt>LineDirectControlEn</span>,
+  <span id=t_idt>fullSpeedPol</span>, 
+  <span id=t_idt>fullSpeedRate</span>,
+  <span id=t_idt>transReq</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>output</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transReq</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxTransTypeReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxSOFEnableReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddrReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNumIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatusIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPIDIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>connEventIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrTransReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>preambleEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSync</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transReq</span>;
+
+<span id=t_com>//internal wire and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineControlReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrConnEvtReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFSentInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connEventInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>setTransReq</span>;
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResInReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>setTransReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>hostControlSelect</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>preambleEn</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>SOFSync</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>setTransReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>TxTransTypeReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>TxLineControlReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>TxSOFEnableReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>TxAddrReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>TxEndPReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_kwd>begin</span>
+        <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>clrConnEvtReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>clrResInReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>interruptMaskReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+   <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//interrupt control</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>SOFSentIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFSentInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>connEventIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrConnEvtReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>connEventInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b0</span>;  
+
+  <span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//mask interrupts</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSentInt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>transDoneIntOut</span> &lt;= <span id=t_idt>transDoneInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>];
+  <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_idt>resumeInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>];
+  <span id=t_idt>connEventIntOut</span> &lt;= <span id=t_idt>connEventInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>CONNECTION_EVENT_BIT</span>];
+  <span id=t_idt>SOFSentIntOut</span> &lt;= <span id=t_idt>SOFSentInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_SENT_BIT</span>];
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//transaction request set/clear</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>setTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transReq</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//break out control signals</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>TxLineState</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>TX_LINE_STATE_LSBIT</span>];
+  <span id=t_idt>LineDirectControlEn</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>DIRECT_CONTROL_BIT</span>];
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span>]; 
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>TxLineControlReg</span>[`<span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span>];
+<span id=t_kwd>end</span>
+  
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxLineControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxSOFEnableReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndPReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNumIn</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SOFSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>connEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span>
+  <span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>RxPktStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxPIDIn</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>preambleEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSync</span> <span id=t_kwd>or</span> <span id=t_idt>transReq</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+     `<span id=t_idt>TX_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>preambleEn</span>, <span id=t_idt>SOFSync</span>, <span id=t_idt>transReq</span>} ;
+     `<span id=t_idt>TX_TRANS_TYPE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>TxTransTypeReg</span>};
+     `<span id=t_idt>TX_LINE_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>TxLineControlReg</span>};
+     `<span id=t_idt>TX_SOF_ENABLE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>TxSOFEnableReg</span>};
+     `<span id=t_idt>TX_ADDR_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxAddrReg</span>};
+     `<span id=t_idt>TX_ENDP_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>TxEndPReg</span>};
+     `<span id=t_idt>FRAME_NUM_MSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>frameNumIn</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>];
+     `<span id=t_idt>FRAME_NUM_LSB_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNumIn</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]};
+     `<span id=t_idt>INTERRUPT_STATUS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>SOFSentInt</span>, <span id=t_idt>connEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>};
+     `<span id=t_idt>INTERRUPT_MASK_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'h0</span>, <span id=t_idt>interruptMaskReg</span>};
+     `<span id=t_idt>RX_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>RxPktStatusIn</span>;
+     `<span id=t_idt>RX_PID_REG</span>  : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>4'b0000</span>, <span id=t_idt>RxPIDIn</span>};
+     `<span id=t_idt>RX_CONNECT_STATE_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>};
+      <span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/USBHostControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar127.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar127.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar127.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 127 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./directcontrol_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./directcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram33.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram33.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="getpacket PROC_PKT" alt="getpacket PROC_PKT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/TestBench/usbHostSlave_TB_runtest.do/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/TestBench/usbHostSlave_TB_runtest.do/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/TestBench/usbHostSlave_TB_runtest.do/index.htm	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<head>
+<title>usbHostSlave_TB_runtest.do</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_kwd>SetActiveLib</span> -work
+<span id=t_com>#Compiling UUT module design files</span>
+
+<span id=t_kwd>comp</span> -include "$DSN\src\TestBench\usbHostSlave_TB.v"
+<span id=t_kwd>asim</span> usbHostSlave_tb
+
+<span id=t_kwd>wave</span>
+<span id=t_kwd>wave</span> -noreg clk
+<span id=t_kwd>wave</span> -noreg rst
+<span id=t_kwd>wave</span> -noreg address_i
+<span id=t_kwd>wave</span> -noreg data_i
+<span id=t_kwd>wave</span> -noreg data_o
+<span id=t_kwd>wave</span> -noreg writeEn
+<span id=t_kwd>wave</span> -noreg strobe_i
+<span id=t_kwd>wave</span> -noreg ack_o
+<span id=t_kwd>wave</span> -noreg hostSOFSentIntOut
+<span id=t_kwd>wave</span> -noreg hostConnEventIntOut
+<span id=t_kwd>wave</span> -noreg hostResumeIntOut
+<span id=t_kwd>wave</span> -noreg hostTransDoneIntOut
+<span id=t_kwd>wave</span> -noreg slaveSOFRxedIntOut
+<span id=t_kwd>wave</span> -noreg slaveResetEventIntOut
+<span id=t_kwd>wave</span> -noreg slaveResumeIntOut
+<span id=t_kwd>wave</span> -noreg slaveTransDoneIntOut
+<span id=t_kwd>wave</span> -noreg USBWireDataIn
+<span id=t_kwd>wave</span> -noreg USBWireDataInTick
+<span id=t_kwd>wave</span> -noreg USBWireDataOut
+<span id=t_kwd>wave</span> -noreg USBWireDataOutTick
+<span id=t_kwd>wave</span> -noreg USBWireCtrlOut
+
+<span id=t_kwd>run</span>
+
+<span id=t_com>#End simulation macro</span>
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/TestBench/usbHostSlave_TB_runtest.do/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/buffers/TxFifoBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/buffers/TxFifoBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/buffers/TxFifoBI.v/index.htm	(revision 264)
@@ -0,0 +1,135 @@
+<html>
+<head>
+<title>TxFifoBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// TxfifoBI.v                                                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:30 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"wishBoneBus_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>TxfifoBI</span> (
+  <span id=t_idt>address</span>, <span id=t_idt>writeEn</span>, <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>, <span id=t_idt>fifoSelect</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>,
+  <span id=t_idt>fifoWEn</span>,
+  <span id=t_idt>fifoFull</span>,
+  <span id=t_idt>forceEmpty</span>,
+  <span id=t_idt>numElementsInFifo</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>output</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fifoSelect</span>;
+
+
+<span id=t_kwd>wire</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoFull</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoSelect</span>;
+
+
+<span id=t_com>//sync write</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fifoSelect</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+  <span id=t_idt>address</span> == `<span id=t_idt>FIFO_CONTROL_REG</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>busDataIn</span>[<span id=t_cns>0</span>] == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>forceEmpty</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+    <span id=t_idt>forceEmpty</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span> <span id=t_idt>fifoFull</span> <span id=t_kwd>or</span> <span id=t_idt>numElementsInFifo</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+      `<span id=t_idt>FIFO_STATUS_REG</span> : <span id=t_idt>busDataOut</span> &lt;= {<span id=t_cns>7'b0000000</span>, <span id=t_idt>fifoFull</span>};
+      `<span id=t_idt>FIFO_DATA_COUNT_MSB</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>numElementsInFifo</span>[<span id=t_cns>15</span>:<span id=t_cns>8</span>];
+      `<span id=t_idt>FIFO_DATA_COUNT_LSB</span> : <span id=t_idt>busDataOut</span> &lt;= <span id=t_idt>numElementsInFifo</span>[<span id=t_cns>7</span>:<span id=t_cns>0</span>];
+      <span id=t_kwd>default</span>: <span id=t_idt>busDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//generate fifo write strobe</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span> <span id=t_idt>writeEn</span> <span id=t_kwd>or</span> <span id=t_idt>strobe_i</span> <span id=t_kwd>or</span> <span id=t_idt>fifoSelect</span> <span id=t_kwd>or</span> <span id=t_idt>busDataIn</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>address</span> == `<span id=t_idt>FIFO_DATA_REG</span> &amp;&amp;   <span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+  <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp;   <span id=t_idt>fifoSelect</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>fifoWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+    <span id=t_idt>fifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/start/doc/html/src/busInterface/wishBoneBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/busInterface/wishBoneBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/busInterface/wishBoneBI.v/index.htm	(revision 264)
@@ -0,0 +1,263 @@
+<html>
+<head>
+<title>wishBoneBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// wishBoneBI.v                                                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:31 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"wishBoneBus_h.v"</span>
+
+ 
+<span id=t_kwd>module</span> <span id=t_idt>wishBoneBI</span> (
+  <span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>, 
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>ack_o</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>hostControlSel</span>, 
+  <span id=t_idt>hostRxFifoSel</span>, <span id=t_idt>hostTxFifoSel</span>,
+  <span id=t_idt>slaveControlSel</span>,
+  <span id=t_idt>slaveEP0RxFifoSel</span>, <span id=t_idt>slaveEP1RxFifoSel</span>, <span id=t_idt>slaveEP2RxFifoSel</span>, <span id=t_idt>slaveEP3RxFifoSel</span>, 
+  <span id=t_idt>slaveEP0TxFifoSel</span>, <span id=t_idt>slaveEP1TxFifoSel</span>, <span id=t_idt>slaveEP2TxFifoSel</span>, <span id=t_idt>slaveEP3TxFifoSel</span>, 
+  <span id=t_idt>hostSlaveMuxSel</span>,
+  <span id=t_idt>dataFromHostControl</span>,
+  <span id=t_idt>dataFromHostRxFifo</span>,
+  <span id=t_idt>dataFromHostTxFifo</span>,
+  <span id=t_idt>dataFromSlaveControl</span>,
+  <span id=t_idt>dataFromEP0RxFifo</span>, <span id=t_idt>dataFromEP1RxFifo</span>, <span id=t_idt>dataFromEP2RxFifo</span>, <span id=t_idt>dataFromEP3RxFifo</span>,
+  <span id=t_idt>dataFromEP0TxFifo</span>, <span id=t_idt>dataFromEP1TxFifo</span>, <span id=t_idt>dataFromEP2TxFifo</span>, <span id=t_idt>dataFromEP3TxFifo</span>,
+  <span id=t_idt>dataFromHostSlaveMux</span>
+   );
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>output</span> <span id=t_idt>ack_o</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>hostControlSel</span>;
+<span id=t_kwd>output</span> <span id=t_idt>hostRxFifoSel</span>;
+<span id=t_kwd>output</span> <span id=t_idt>hostTxFifoSel</span>;
+<span id=t_kwd>output</span> <span id=t_idt>slaveControlSel</span>;
+<span id=t_kwd>output</span> <span id=t_idt>slaveEP0RxFifoSel</span>, <span id=t_idt>slaveEP1RxFifoSel</span>, <span id=t_idt>slaveEP2RxFifoSel</span>, <span id=t_idt>slaveEP3RxFifoSel</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>slaveEP0TxFifoSel</span>, <span id=t_idt>slaveEP1TxFifoSel</span>, <span id=t_idt>slaveEP2TxFifoSel</span>, <span id=t_idt>slaveEP3TxFifoSel</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>hostSlaveMuxSel</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostControl</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostRxFifo</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostTxFifo</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromSlaveControl</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP0RxFifo</span>, <span id=t_idt>dataFromEP1RxFifo</span>, <span id=t_idt>dataFromEP2RxFifo</span>, <span id=t_idt>dataFromEP3RxFifo</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP0TxFifo</span>, <span id=t_idt>dataFromEP1TxFifo</span>, <span id=t_idt>dataFromEP2TxFifo</span>, <span id=t_idt>dataFromEP3TxFifo</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostSlaveMux</span>;
+
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>ack_o</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>hostControlSel</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>hostRxFifoSel</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>hostTxFifoSel</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>slaveControlSel</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>slaveEP0RxFifoSel</span>, <span id=t_idt>slaveEP1RxFifoSel</span>, <span id=t_idt>slaveEP2RxFifoSel</span>, <span id=t_idt>slaveEP3RxFifoSel</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>slaveEP0TxFifoSel</span>, <span id=t_idt>slaveEP1TxFifoSel</span>, <span id=t_idt>slaveEP2TxFifoSel</span>, <span id=t_idt>slaveEP3TxFifoSel</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>hostSlaveMuxSel</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostControl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostRxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostTxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromSlaveControl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP0RxFifo</span>, <span id=t_idt>dataFromEP1RxFifo</span>, <span id=t_idt>dataFromEP2RxFifo</span>, <span id=t_idt>dataFromEP3RxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP0TxFifo</span>, <span id=t_idt>dataFromEP1TxFifo</span>, <span id=t_idt>dataFromEP2TxFifo</span>, <span id=t_idt>dataFromEP3TxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostSlaveMux</span>;
+
+<span id=t_com>//internal wires and regs</span>
+<span id=t_kwd>reg</span> <span id=t_idt>ack_delayed</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>ack_immediate</span>;
+
+<span id=t_com>//address decode and data mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromHostControl</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromHostRxFifo</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromHostTxFifo</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromSlaveControl</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromEP0RxFifo</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>dataFromEP1RxFifo</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromEP2RxFifo</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromEP3RxFifo</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromHostSlaveMux</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>dataFromEP0TxFifo</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromEP1TxFifo</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromEP2TxFifo</span> <span id=t_kwd>or</span>
+  <span id=t_idt>dataFromEP3TxFifo</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>hostControlSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>hostRxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>hostTxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>slaveControlSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>slaveEP0RxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>slaveEP0TxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>slaveEP1RxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>slaveEP1TxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>slaveEP2RxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>slaveEP2TxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>slaveEP3RxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>slaveEP3TxFifoSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>hostSlaveMuxSel</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span> &amp; `<span id=t_idt>ADDRESS_DECODE_MASK</span>)
+    `<span id=t_idt>HCREG_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>hostControlSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromHostControl</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>HCREG_BASE_PLUS_0X10</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>hostControlSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromHostControl</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>HOST_RX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>hostRxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromHostRxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>HOST_TX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>hostTxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromHostTxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>SCREG_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveControlSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromSlaveControl</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>SCREG_BASE_PLUS_0X10</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveControlSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromSlaveControl</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>EP0_RX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveEP0RxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromEP0RxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>EP0_TX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveEP0TxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromEP0TxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>EP1_RX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveEP1RxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromEP1RxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>EP1_TX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveEP1TxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromEP1TxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>EP2_RX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveEP2RxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromEP2RxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>EP2_TX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveEP2TxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromEP2TxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>EP3_RX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveEP3RxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromEP3RxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>EP3_TX_FIFO_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>slaveEP3TxFifoSel</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromEP3TxFifo</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>HOST_SLAVE_CONTROL_BASE</span> : <span id=t_kwd>begin</span>
+      <span id=t_idt>hostSlaveMuxSel</span> &lt;= <span id=t_cns>1'b1</span>; 
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>dataFromHostSlaveMux</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>default</span>: 
+      <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//delayed ack</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>ack_delayed</span> &lt;= <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//immediate ack</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>strobe_i</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>ack_immediate</span> &lt;= <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>end</span> 
+
+<span id=t_com>//select between immediate and delayed ack</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>writeEn</span> <span id=t_kwd>or</span> <span id=t_idt>address</span> <span id=t_kwd>or</span> <span id=t_idt>ack_delayed</span> <span id=t_kwd>or</span> <span id=t_idt>ack_immediate</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b0</span> &amp;&amp;
+      (<span id=t_idt>address</span> == `<span id=t_idt>HOST_RX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span> ||
+       <span id=t_idt>address</span> == `<span id=t_idt>HOST_TX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span> ||
+       <span id=t_idt>address</span> == `<span id=t_idt>EP0_RX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span> ||
+       <span id=t_idt>address</span> == `<span id=t_idt>EP0_TX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span> ||
+       <span id=t_idt>address</span> == `<span id=t_idt>EP1_RX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span> ||
+       <span id=t_idt>address</span> == `<span id=t_idt>EP1_TX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span> ||
+       <span id=t_idt>address</span> == `<span id=t_idt>EP2_RX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span> ||
+       <span id=t_idt>address</span> == `<span id=t_idt>EP2_TX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span> ||
+       <span id=t_idt>address</span> == `<span id=t_idt>EP3_RX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span> ||
+       <span id=t_idt>address</span> == `<span id=t_idt>EP3_TX_FIFO_BASE</span> + `<span id=t_idt>FIFO_DATA_REG</span>) )
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>ack_o</span> &lt;= <span id=t_idt>ack_delayed</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>ack_o</span> &lt;= <span id=t_idt>ack_immediate</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/busInterface/wishBoneBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar78.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar78.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar78.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 78 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./directcontrol_DRCT_CNTL.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./directcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar78.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram58.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram58.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram58.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="getpacket DATA" alt="getpacket DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram58.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket_LOOP.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket_LOOP.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index33.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index33.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar33.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram33.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index33.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar33.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar33.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1244,949,1347,1051,Click58,Over58);
+
+//----------------------------------------------------------------------------
+function Click58(){fubclick('./index58.htm');}
+function Over58(){window.status='Hierarchical State DATA';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 33 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./getpacket_PROC_PKT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./getpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.v/index.htm	(revision 264)
@@ -0,0 +1,253 @@
+<html>
+<head>
+<title>hctxportarbiter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// HCTxPortArbiter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:45 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>HCTxPortArbiter</span> (<span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortWEnable</span>, <span id=t_idt>SOFCntlCntl</span>, <span id=t_idt>SOFCntlData</span>, <span id=t_idt>SOFCntlGnt</span>, <span id=t_idt>SOFCntlReq</span>, <span id=t_idt>SOFCntlWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>directCntlCntl</span>, <span id=t_idt>directCntlData</span>, <span id=t_idt>directCntlGnt</span>, <span id=t_idt>directCntlReq</span>, <span id=t_idt>directCntlWEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketCntl</span>, <span id=t_idt>sendPacketData</span>, <span id=t_idt>sendPacketGnt</span>, <span id=t_idt>sendPacketReq</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFCntlReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFCntlWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortWEnable</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SOFCntlGnt</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>directCntlGnt</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketGnt</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>next_HCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>, <span id=t_idt>next_HCTxPortData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortWEnable</span>, <span id=t_idt>next_HCTxPortWEnable</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFCntlGnt</span>, <span id=t_idt>next_SOFCntlGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFCntlReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFCntlWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>directCntlGnt</span>, <span id=t_idt>next_directCntlGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketGnt</span>, <span id=t_idt>next_sendPacketGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketWEn</span>;
+
+
+<span id=t_com>// Constants</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIRECT_CTRL_MUX</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_PACKET_MUX</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_CTRL_MUX</span> <span id=t_cns>2'b01</span>
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>muxCntl</span>, <span id=t_idt>next_muxCntl</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: HCTxArb</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_HARB</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_REQ</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_PACKET</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIRECT_CONTROL</span> <span id=t_cns>3'b100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_HCTxArb</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_HCTxArb</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// SOFController/directContol/sendPacket mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>muxCntl</span> <span id=t_kwd>or</span> <span id=t_idt>SOFCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>SOFCntlCntl</span> <span id=t_kwd>or</span>
+        <span id=t_idt>directCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlCntl</span> <span id=t_kwd>or</span>
+                  <span id=t_idt>directCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlCntl</span> <span id=t_kwd>or</span>
+          <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketData</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketCntl</span>)
+<span id=t_kwd>begin</span>
+<span id=t_kwd>case</span> (<span id=t_idt>muxCntl</span>)
+    `<span id=t_idt>SOF_CTRL_MUX</span> :
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>HCTxPortWEnable</span> &lt;= <span id=t_idt>SOFCntlWEn</span>;
+        <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>SOFCntlData</span>;
+        <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>SOFCntlCntl</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>DIRECT_CTRL_MUX</span> :
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>HCTxPortWEnable</span> &lt;= <span id=t_idt>directCntlWEn</span>;
+        <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>directCntlData</span>;
+        <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>directCntlCntl</span>;
+    <span id=t_kwd>end</span>
+    `<span id=t_idt>SEND_PACKET_MUX</span> :
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>HCTxPortWEnable</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+        <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>sendPacketData</span>;
+        <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>sendPacketCntl</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>default</span> :
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>HCTxPortWEnable</span> &lt;= <span id=t_cns>1'b0</span>;
+        <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+        <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: HCTxArb</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>SOFCntlReq</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketReq</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlReq</span> <span id=t_kwd>or</span> <span id=t_idt>SOFCntlGnt</span> <span id=t_kwd>or</span> <span id=t_idt>muxCntl</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketGnt</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlGnt</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_HCTxArb</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>HCTxArb_NextState</span>
+  <span id=t_idt>NextState_HCTxArb</span> &lt;= <span id=t_idt>CurrState_HCTxArb</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_SOFCntlGnt</span> &lt;= <span id=t_idt>SOFCntlGnt</span>;
+  <span id=t_idt>next_muxCntl</span> &lt;= <span id=t_idt>muxCntl</span>;
+  <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_idt>sendPacketGnt</span>;
+  <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_idt>directCntlGnt</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_HCTxArb</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_HARB</span>:
+     <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>WAIT_REQ</span>;
+   `<span id=t_idt>WAIT_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFCntlReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>SEND_SOF</span>;
+      <span id=t_idt>next_SOFCntlGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxCntl</span> &lt;= `<span id=t_idt>SOF_CTRL_MUX</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>sendPacketReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>SEND_PACKET</span>;
+      <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxCntl</span> &lt;= `<span id=t_idt>SEND_PACKET_MUX</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>directCntlReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>DIRECT_CONTROL</span>;
+      <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxCntl</span> &lt;= `<span id=t_idt>DIRECT_CTRL_MUX</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFCntlReq</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>WAIT_REQ</span>;
+      <span id=t_idt>next_SOFCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_PACKET</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>WAIT_REQ</span>;
+      <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DIRECT_CONTROL</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>directCntlReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_HCTxArb</span> &lt;= `<span id=t_idt>WAIT_REQ</span>;
+      <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>HCTxArb_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_HCTxArb</span> &lt;= `<span id=t_idt>START_HARB</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_HCTxArb</span> &lt;= <span id=t_idt>NextState_HCTxArb</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>HCTxArb_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxCntl</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>SOFCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>directCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxCntl</span> &lt;= <span id=t_idt>next_muxCntl</span>;
+   <span id=t_idt>SOFCntlGnt</span> &lt;= <span id=t_idt>next_SOFCntlGnt</span>;
+   <span id=t_idt>sendPacketGnt</span> &lt;= <span id=t_idt>next_sendPacketGnt</span>;
+   <span id=t_idt>directCntlGnt</span> &lt;= <span id=t_idt>next_directCntlGnt</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index112.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index112.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar112.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram112.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index112.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar112.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar112.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar112.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 112 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./getpacket_LOOP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./getpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar112.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/buffers/TxFifo.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/buffers/TxFifo.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/buffers/TxFifo.v/index.htm	(revision 264)
@@ -0,0 +1,140 @@
+<html>
+<head>
+<title>TxFifo.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// TxFifo.v                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536</span>
+<span id=t_com>////  fifo write access via bus interface, fifo read access is direct</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:30 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>TxFifo</span>(
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>, 
+  <span id=t_idt>fifoREn</span>, 
+  <span id=t_idt>fifoEmpty</span>,
+  <span id=t_idt>busAddress</span>, 
+  <span id=t_idt>busWriteEn</span>, 
+  <span id=t_idt>busStrobe_i</span>,
+  <span id=t_idt>busFifoSelect</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>,
+  <span id=t_idt>fifoDataOut</span> ); 
+  <span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>fifoREn</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busWriteEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>busFifoSelect</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataOut</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fifoREn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busWriteEn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>busFifoSelect</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoDataOut</span>;
+
+<span id=t_com>//internal wires and regs</span>
+<span id=t_kwd>wire</span> <span id=t_idt>fifoWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>forceEmpty</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>numElementsInFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fifoFull</span>;
+
+<span id=t_idt>fifoRTL</span> #(<span id=t_cns>8</span>, <span id=t_idt>FIFO_DEPTH</span>, <span id=t_idt>ADDR_WIDTH</span>) <span id=t_idt>u_fifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>fifoDataOut</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>fifoWEn</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>fifoREn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>fifoFull</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>fifoEmpty</span>), 
+  .<span id=t_idt>forceEmpty</span>(<span id=t_idt>forceEmpty</span>), 
+  .<span id=t_idt>numElementsInFifo</span>(<span id=t_idt>numElementsInFifo</span>) );
+  
+<span id=t_idt>TxfifoBI</span> <span id=t_idt>u_TxfifoBI</span>(
+  .<span id=t_idt>address</span>(<span id=t_idt>busAddress</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>busWriteEn</span>), 
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>busStrobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoSelect</span>(<span id=t_idt>busFifoSelect</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>busDataOut</span>),
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>fifoWEn</span>),
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>fifoFull</span>),
+  .<span id=t_idt>forceEmpty</span>(<span id=t_idt>forceEmpty</span>),
+  .<span id=t_idt>numElementsInFifo</span>(<span id=t_idt>numElementsInFifo</span>)
+  );
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/buffers/TxFifo.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/buffers/simFifoMem.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/buffers/simFifoMem.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/buffers/simFifoMem.v/index.htm	(revision 264)
@@ -0,0 +1,101 @@
+<html>
+<head>
+<title>simFifoMem.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// simFifoMem.v                                                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:29 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>simFifoMem</span>(  <span id=t_idt>addrIn</span>, <span id=t_idt>addrOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>writeEn</span>, <span id=t_idt>readEn</span>, <span id=t_idt>dataOut</span>);
+  <span id=t_com>//FIFO_DEPTH = ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_WIDTH</span> = <span id=t_cns>8</span>;
+  <span id=t_kwd>parameter</span> <span id=t_idt>FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>output</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>readEn</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrIn</span>;
+<span id=t_kwd>input</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrOut</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>reg</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>readEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_idt>ADDR_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>addrOut</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_idt>FIFO_WIDTH</span>-<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>buffer</span> [<span id=t_cns>0</span>:<span id=t_idt>FIFO_DEPTH</span>-<span id=t_cns>1</span>];
+
+<span id=t_com>// synchronous read. Introduces one clock cycle delay</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>buffer</span>[<span id=t_idt>addrOut</span>];
+<span id=t_kwd>end</span>
+
+<span id=t_com>// synchronous write</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>buffer</span>[<span id=t_idt>addrIn</span>] &lt;= <span id=t_idt>dataIn</span>;
+<span id=t_kwd>end</span>                  
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/buffers/simFifoMem.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram127.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram127.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram127.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="directcontrol IDLE" alt="directcontrol IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol_DRCT_CNTL.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol_DRCT_CNTL.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index78.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index78.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index78.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar78.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram78.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/index78.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="getpacket" alt="getpacket"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram45.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram45.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram45.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller SETUP" alt="hostcontroller SETUP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/hctxportarbiter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket_PROC_PKT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket_PROC_PKT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index58.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index58.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index58.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar58.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram58.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index58.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar58.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar58.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar58.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(662,1601,764,1703,Click112,Over112);
+
+//----------------------------------------------------------------------------
+function Click112(){fubclick('./index112.htm');}
+function Over112(){window.status='Hierarchical State LOOP';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 58 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./getpacket_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./getpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar58.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller" alt="hostcontroller"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram51.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram51.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram51.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller OUT1" alt="hostcontroller OUT1"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram51.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller_OUT1.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller_OUT1.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller_OUT0.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller_OUT0.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index45.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index45.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index45.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar45.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram45.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index45.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(341,1398,444,1500,Click45,Over45);
+FUB[1] = new Array(733,1389,836,1492,Click47,Over47);
+FUB[2] = new Array(1416,1391,1519,1494,Click51,Over51);
+FUB[3] = new Array(965,1392,1068,1495,Click49,Over49);
+
+//----------------------------------------------------------------------------
+function Click45(){fubclick('./index45.htm');}
+function Over45(){window.status='Hierarchical State SETUP';};
+function Click47(){fubclick('./index47.htm');}
+function Over47(){window.status='Hierarchical State IN';};
+function Click51(){fubclick('./index51.htm');}
+function Over51(){window.status='Hierarchical State OUT1';};
+function Click49(){fubclick('./index49.htm');}
+function Over49(){window.status='Hierarchical State OUT0';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar51.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar51.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar51.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 51 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller_OUT1.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar51.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram47.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram47.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram47.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller IN" alt="hostcontroller IN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram47.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller.v/index.htm	(revision 264)
@@ -0,0 +1,391 @@
+<html>
+<head>
+<title>hostcontroller.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// hostController</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:52 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>hostcontroller</span> (<span id=t_idt>RXStatus</span>, <span id=t_idt>clearTXReq</span>, <span id=t_idt>clk</span>, <span id=t_idt>getPacketREn</span>, <span id=t_idt>getPacketRdy</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketArbiterGnt</span>, <span id=t_idt>sendPacketArbiterReq</span>, <span id=t_idt>sendPacketPID</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>transDone</span>, <span id=t_idt>transReq</span>, <span id=t_idt>transType</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStatus</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketArbiterGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>transReq</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>clearTXReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>getPacketREn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketArbiterReq</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>transDone</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStatus</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>clearTXReq</span>, <span id=t_idt>next_clearTXReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>getPacketREn</span>, <span id=t_idt>next_getPacketREn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketArbiterGnt</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketArbiterReq</span>, <span id=t_idt>next_sendPacketArbiterReq</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>, <span id=t_idt>next_sendPacketPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>next_sendPacketWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>transDone</span>, <span id=t_idt>next_transDone</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>transReq</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: hstCntrl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_HC</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_REQ</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_TYPE</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>FLAG</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_DATA_RXED</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_CHK_FOR_ERROR</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_CLR_SP_WEN2</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_CLR_SP_WEN1</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_CLR_SP_WEN2</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIN</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_GNT</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_WAIT_PKT_RXED</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_IN_SENT</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_WAIT_RX_DATA</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_WAIT_DATA0_SENT</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_WAIT_OUT_SENT</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_HC_WAIT_RDY</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_SP_RDY1</span> <span id=t_cns>5'b10001</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_SP_RDY2</span> <span id=t_cns>5'b10010</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_WAIT_SP_RDY1</span> <span id=t_cns>5'b10011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_WAIT_SETUP_SENT</span> <span id=t_cns>5'b10100</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_WAIT_DATA_SENT</span> <span id=t_cns>5'b10101</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_CLR_SP_WEN1</span> <span id=t_cns>5'b10110</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_WAIT_ACK_SENT</span> <span id=t_cns>5'b10111</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_CLR_WEN1</span> <span id=t_cns>5'b11000</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT0_CLR_WEN2</span> <span id=t_cns>5'b11001</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_WAIT_RX_DATA</span> <span id=t_cns>5'b11010</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_WAIT_OUT_SENT</span> <span id=t_cns>5'b11011</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_WAIT_DATA1_SENT</span> <span id=t_cns>5'b11100</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_WAIT_SP_RDY1</span> <span id=t_cns>5'b11101</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_CLR_WEN1</span> <span id=t_cns>5'b11110</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT1_CLR_WEN2</span> <span id=t_cns>5'b11111</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_hstCntrl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_hstCntrl</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: hstCntrl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>transReq</span> <span id=t_kwd>or</span> <span id=t_idt>transType</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketArbiterGnt</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>RXStatus</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketArbiterReq</span> <span id=t_kwd>or</span> <span id=t_idt>transDone</span> <span id=t_kwd>or</span> <span id=t_idt>clearTXReq</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketREn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketPID</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_hstCntrl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>hstCntrl_NextState</span>
+  <span id=t_idt>NextState_hstCntrl</span> &lt;= <span id=t_idt>CurrState_hstCntrl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_idt>sendPacketArbiterReq</span>;
+  <span id=t_idt>next_transDone</span> &lt;= <span id=t_idt>transDone</span>;
+  <span id=t_idt>next_clearTXReq</span> &lt;= <span id=t_idt>clearTXReq</span>;
+  <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+  <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_idt>getPacketREn</span>;
+  <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketPID</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_hstCntrl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_HC</span>:
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>TX_REQ</span>;
+   `<span id=t_idt>TX_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>transReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>WAIT_GNT</span>;
+      <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_TYPE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>transType</span> == `<span id=t_idt>OUTDATA0_TRANS</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_WAIT_SP_RDY1</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>transType</span> == `<span id=t_idt>IN_TRANS</span>) 
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_SP_RDY1</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>transType</span> == `<span id=t_idt>SETUP_TRANS</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_HC_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>transType</span> == `<span id=t_idt>OUTDATA1_TRANS</span>) 
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_WAIT_SP_RDY1</span>;
+   `<span id=t_idt>FLAG</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_transDone</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_clearTXReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FIN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_transDone</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_clearTXReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>TX_REQ</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketArbiterGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>CHK_TYPE</span>;
+   `<span id=t_idt>SETUP_CLR_SP_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_WAIT_SETUP_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_CLR_SP_WEN2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_WAIT_DATA_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_WAIT_PKT_RXED</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_HC_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_CLR_SP_WEN1</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>SETUP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_WAIT_SETUP_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_CLR_SP_WEN2</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_WAIT_DATA_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>SETUP_WAIT_PKT_RXED</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_DATA_RXED</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_CHK_FOR_ERROR</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_CHK_FOR_ERROR</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_CRC_ERROR_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_BIT_STUFF_ERROR_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_RX_OVERFLOW_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_NAK_RXED_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_STALL_RXED_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RXStatus</span> [`<span id=t_idt>HC_RX_TIME_OUT_BIT</span>] == <span id=t_cns>1'b0</span>) 
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_SP_RDY2</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   `<span id=t_idt>IN_CLR_SP_WEN2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_ACK_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_IN_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_DATA_RXED</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_SP_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_CLR_SP_WEN1</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>IN</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_SP_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_CLR_SP_WEN2</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>ACK</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_CLR_SP_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>IN_WAIT_IN_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_WAIT_ACK_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   `<span id=t_idt>OUT0_WAIT_RX_DATA</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_WAIT_DATA0_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_WAIT_RX_DATA</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_WAIT_OUT_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_CLR_WEN2</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_WAIT_SP_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_CLR_WEN1</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>OUT</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_CLR_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_WAIT_OUT_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT0_CLR_WEN2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT0_WAIT_DATA0_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_WAIT_RX_DATA</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>FLAG</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_WAIT_OUT_SENT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_CLR_WEN2</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_WAIT_DATA1_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_WAIT_RX_DATA</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_WAIT_SP_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_CLR_WEN1</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>OUT</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_CLR_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_WAIT_OUT_SENT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT1_CLR_WEN2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_hstCntrl</span> &lt;= `<span id=t_idt>OUT1_WAIT_DATA1_SENT</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>hstCntrl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_hstCntrl</span> &lt;= `<span id=t_idt>START_HC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_hstCntrl</span> &lt;= <span id=t_idt>NextState_hstCntrl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>hstCntrl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>transDone</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>clearTXReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_cns>4'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>transDone</span> &lt;= <span id=t_idt>next_transDone</span>;
+   <span id=t_idt>clearTXReq</span> &lt;= <span id=t_idt>next_clearTXReq</span>;
+   <span id=t_idt>getPacketREn</span> &lt;= <span id=t_idt>next_getPacketREn</span>;
+   <span id=t_idt>sendPacketArbiterReq</span> &lt;= <span id=t_idt>next_sendPacketArbiterReq</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_idt>next_sendPacketWEn</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_idt>next_sendPacketPID</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller_SETUP.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller_SETUP.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index49.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index49.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index49.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar49.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram49.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index49.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar47.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar47.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar47.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 47 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller_IN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar47.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket" alt="sendpacket"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram45.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram45.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram45.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket DATA0_DATA1" alt="sendpacket DATA0_DATA1"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index47.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index47.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index47.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar47.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram47.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index47.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar45.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar45.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar45.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 45 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller_SETUP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/rxStatusMonitor.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/rxStatusMonitor.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/rxStatusMonitor.v/index.htm	(revision 264)
@@ -0,0 +1,111 @@
+<html>
+<head>
+<title>rxStatusMonitor.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// rxStatusMonitor.v                                            ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:53 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+<span id=t_kwd>module</span> <span id=t_idt>rxStatusMonitor</span>(<span id=t_idt>connectStateIn</span>, <span id=t_idt>connectStateOut</span>, <span id=t_idt>resumeDetectedIn</span>, <span id=t_idt>connectionEventOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> <span id=t_idt>connectionEventOut</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>connectionEventOut</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>oldConnectState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>oldResumeDetected</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_idt>connectStateIn</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>connectStateOut</span> &lt;= <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>oldConnectState</span> &lt;= <span id=t_idt>connectStateIn</span>;
+   <span id=t_idt>oldResumeDetected</span> &lt;= <span id=t_idt>resumeDetectedIn</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>oldConnectState</span> &lt;= <span id=t_idt>connectStateIn</span>;
+   <span id=t_idt>oldResumeDetected</span> &lt;= <span id=t_idt>resumeDetectedIn</span>;
+   <span id=t_kwd>if</span> (<span id=t_idt>oldConnectState</span> != <span id=t_idt>connectStateIn</span>)
+     <span id=t_idt>connectionEventOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>else</span>
+     <span id=t_idt>connectionEventOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>if</span> (<span id=t_idt>resumeDetectedIn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>oldResumeDetected</span> == <span id=t_cns>1'b0</span>)
+     <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>else</span> 
+     <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/rxStatusMonitor.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram43.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram43.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram43.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket SEND_SOF" alt="sendpacket SEND_SOF"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram43.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index41.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index41.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index41.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar41.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram41.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index41.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket.v/index.htm	(revision 264)
@@ -0,0 +1,340 @@
+<html>
+<head>
+<title>sendpacket.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// sendPacket</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:01 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+
+
+<span id=t_kwd>module</span> <span id=t_idt>sendPacket</span> (<span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortGnt</span>, <span id=t_idt>HCTxPortRdy</span>, <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>PID</span>, <span id=t_idt>TxAddr</span>, <span id=t_idt>TxEndP</span>, <span id=t_idt>clk</span>, <span id=t_idt>fifoData</span>, <span id=t_idt>fifoEmpty</span>, <span id=t_idt>fifoReadEn</span>, <span id=t_idt>frameNum</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>PID</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddr</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndP</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fifoReadEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketRdy</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>next_HCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>, <span id=t_idt>next_HCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>next_HCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>next_HCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>PID</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddr</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndP</span>, <span id=t_idt>next_TxEndP</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>fifoReadEn</span>, <span id=t_idt>next_fifoReadEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>, <span id=t_idt>next_frameNum</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>next_sendPacketRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>PIDNotPID</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: sndPkt</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SP</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_ENABLE</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_WAIT_GNT</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_PID_WAIT_RDY</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_PID_FIN</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIN_SP</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT_IN_SETUP_WAIT_RDY1</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT_IN_SETUP_WAIT_RDY2</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT_IN_SETUP_FIN</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF_FIN1</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF_WAIT_RDY3</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF_WAIT_RDY4</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_READ_FIFO</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_WAIT_READ_FIFO</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_FIFO_EMPTY</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_FIN</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_TERM_BYTE</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT_IN_SETUP_CLR_WEN1</span> <span id=t_cns>5'b10001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_SOF_CLR_WEN1</span> <span id=t_cns>5'b10010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_CLR_WEN</span> <span id=t_cns>5'b10011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0_DATA1_CLR_REN</span> <span id=t_cns>5'b10100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_sndPkt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_sndPkt</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>PID</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>PIDNotPID</span> &lt;=  { (<span id=t_idt>PID</span> ^ <span id=t_cns>4'hf</span>), <span id=t_idt>PID</span> };
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: sndPkt</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>PIDNotPID</span> <span id=t_kwd>or</span> <span id=t_idt>TxEndP</span> <span id=t_kwd>or</span> <span id=t_idt>TxAddr</span> <span id=t_kwd>or</span> <span id=t_idt>frameNum</span> <span id=t_kwd>or</span> <span id=t_idt>fifoData</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>PID</span> <span id=t_kwd>or</span> <span id=t_idt>fifoEmpty</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>fifoReadEn</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_sndPkt</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sndPkt_NextState</span>
+  <span id=t_idt>NextState_sndPkt</span> &lt;= <span id=t_idt>CurrState_sndPkt</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_idt>sendPacketRdy</span>;
+  <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_idt>HCTxPortReq</span>;
+  <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_idt>HCTxPortWEn</span>;
+  <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>HCTxPortData</span>;
+  <span id=t_idt>next_HCTxPortCntl</span> &lt;= <span id=t_idt>HCTxPortCntl</span>;
+  <span id=t_idt>next_frameNum</span> &lt;= <span id=t_idt>frameNum</span>;
+  <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_idt>fifoReadEn</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_sndPkt</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SP</span>:
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>WAIT_ENABLE</span>;
+   `<span id=t_idt>WAIT_ENABLE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketWEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SP_WAIT_GNT</span>;
+      <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_PID_WAIT_RDY</span>;
+   `<span id=t_idt>FIN_SP</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>WAIT_ENABLE</span>;
+     <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_PID_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_PID_FIN</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>PIDNotPID</span>;
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_START</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_PID_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>PID</span> == `<span id=t_idt>DATA0</span> || <span id=t_idt>PID</span> == `<span id=t_idt>DATA1</span>)  
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_FIFO_EMPTY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>PID</span> == `<span id=t_idt>SOF</span>)  
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_SOF_WAIT_RDY3</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>PID</span> == `<span id=t_idt>OUT</span> || 
+      <span id=t_idt>PID</span> == `<span id=t_idt>IN</span> || 
+      <span id=t_idt>PID</span> == `<span id=t_idt>SETUP</span>)  
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>OUT_IN_SETUP_WAIT_RDY1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>FIN_SP</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT_IN_SETUP_WAIT_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>OUT_IN_SETUP_CLR_WEN1</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= {<span id=t_idt>TxEndP</span>[<span id=t_cns>0</span>], <span id=t_idt>TxAddr</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>]};
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT_IN_SETUP_WAIT_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>OUT_IN_SETUP_FIN</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>TxEndP</span>[<span id=t_cns>3</span>:<span id=t_cns>1</span>]};
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT_IN_SETUP_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>FIN_SP</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>OUT_IN_SETUP_CLR_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>OUT_IN_SETUP_WAIT_RDY2</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF_FIN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_frameNum</span> &lt;= <span id=t_idt>frameNum</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>FIN_SP</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF_WAIT_RDY3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_SOF_CLR_WEN1</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>frameNum</span>[<span id=t_cns>7</span>:<span id=t_cns>0</span>];
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF_WAIT_RDY4</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_SOF_FIN1</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNum</span>[<span id=t_cns>10</span>:<span id=t_cns>8</span>]};
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_SOF_CLR_WEN1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>SEND_SOF_WAIT_RDY4</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_READ_FIFO</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>fifoData</span>;
+     <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_CLR_WEN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_WAIT_READ_FIFO</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_CLR_REN</span>;
+      <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_FIFO_EMPTY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>fifoEmpty</span> == <span id=t_cns>1'b0</span>) 
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_WAIT_READ_FIFO</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_TERM_BYTE</span>;
+   `<span id=t_idt>DATA0_DATA1_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>FIN_SP</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_TERM_BYTE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_FIN</span>;
+      <span id=t_com>//Last byte is not valid data,</span>
+      <span id=t_com>//but the 'TX_PACKET_STOP' flag is required</span>
+      <span id=t_com>//by the SIE state machine to detect end of data packet</span>
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_CLR_WEN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_FIFO_EMPTY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA0_DATA1_CLR_REN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sndPkt</span> &lt;= `<span id=t_idt>DATA0_DATA1_READ_FIFO</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sndPkt_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_sndPkt</span> &lt;= `<span id=t_idt>START_SP</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_sndPkt</span> &lt;= <span id=t_idt>NextState_sndPkt</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sndPkt_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>frameNum</span> &lt;= <span id=t_cns>11'h000</span>;
+   <span id=t_idt>fifoReadEn</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketRdy</span> &lt;= <span id=t_idt>next_sendPacketRdy</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_idt>next_HCTxPortReq</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_idt>next_HCTxPortWEn</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>next_HCTxPortData</span>;
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>next_HCTxPortCntl</span>;
+   <span id=t_idt>frameNum</span> &lt;= <span id=t_idt>next_frameNum</span>;
+   <span id=t_idt>fifoReadEn</span> &lt;= <span id=t_idt>next_fifoReadEn</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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+*
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===================================================================
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Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket_SEND_SOF.png
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+*
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+application/octet-stream
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===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram41.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram41.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket OUT_IN_SETUP" alt="sendpacket OUT_IN_SETUP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram41.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index21.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index21.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index21.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar21.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram21.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index21.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket_SEND_PID.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket_SEND_PID.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram78.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram78.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram78.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="directcontrol DRCT_CNTL" alt="directcontrol DRCT_CNTL"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/diagram78.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index43.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index43.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index43.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar43.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram43.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index43.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket_DATA0_DATA1.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket_DATA0_DATA1.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(846,1408,949,1511,Click21,Over21);
+FUB[1] = new Array(1383,1784,1485,1886,Click45,Over45);
+FUB[2] = new Array(863,1765,965,1867,Click43,Over43);
+FUB[3] = new Array(433,1750,536,1853,Click41,Over41);
+
+//----------------------------------------------------------------------------
+function Click21(){fubclick('./index21.htm');}
+function Over21(){window.status='Hierarchical State SEND_PID';};
+function Click45(){fubclick('./index45.htm');}
+function Over45(){window.status='Hierarchical State DATA0_DATA1';};
+function Click43(){fubclick('./index43.htm');}
+function Over43(){window.status='Hierarchical State SEND_SOF';};
+function Click41(){fubclick('./index41.htm');}
+function Over41(){window.status='Hierarchical State OUT_IN_SETUP';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol_IDLE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/directcontrol_IDLE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(488,1130,591,1232,Click78,Over78);
+FUB[1] = new Array(1112,1183,1215,1285,Click127,Over127);
+
+//----------------------------------------------------------------------------
+function Click78(){fubclick('./index78.htm');}
+function Over78(){window.status='Hierarchical State DRCT_CNTL';};
+function Click127(){fubclick('./index127.htm');}
+function Over127(){window.status='Hierarchical State IDLE';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./directcontrol.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./directcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/directcontrol.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram112.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram112.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram112.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="getpacket LOOP" alt="getpacket LOOP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/diagram112.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket.v/index.htm	(revision 264)
@@ -0,0 +1,380 @@
+<html>
+<head>
+<title>getpacket.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// getPacket</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:58:41 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>getPacket</span> (<span id=t_idt>RXDataIn</span>, <span id=t_idt>RXDataValid</span>, <span id=t_idt>RXFifoData</span>, <span id=t_idt>RXFifoFull</span>, <span id=t_idt>RXFifoWEn</span>, <span id=t_idt>RXPacketRdy</span>, <span id=t_idt>RXPktStatus</span>, <span id=t_idt>RXStreamStatusIn</span>, <span id=t_idt>RxPID</span>, <span id=t_idt>SIERxTimeOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>getPacketEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXDataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RXDataValid</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RXFifoFull</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStreamStatusIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIERxTimeOut</span>;   <span id=t_com>// Single cycle pulse</span>
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>getPacketEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXFifoData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXFifoWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXPacketRdy</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXPktStatus</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXDataIn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RXDataValid</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXFifoData</span>, <span id=t_idt>next_RXFifoData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RXFifoFull</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXFifoWEn</span>, <span id=t_idt>next_RXFifoWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXPacketRdy</span>, <span id=t_idt>next_RXPacketRdy</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXPktStatus</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStreamStatusIn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>, <span id=t_idt>next_RxPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>getPacketEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>ACKRxed</span>, <span id=t_idt>next_ACKRxed</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>CRCError</span>, <span id=t_idt>next_CRCError</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>NAKRxed</span>, <span id=t_idt>next_NAKRxed</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteOld</span>, <span id=t_idt>next_RXByteOld</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteOldest</span>, <span id=t_idt>next_RXByteOldest</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByte</span>, <span id=t_idt>next_RXByte</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>RXOverflow</span>, <span id=t_idt>next_RXOverflow</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXStreamStatus</span>, <span id=t_idt>next_RXStreamStatus</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>RXTimeOut</span>, <span id=t_idt>next_RXTimeOut</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>bitStuffError</span>, <span id=t_idt>next_bitStuffError</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>dataSequence</span>, <span id=t_idt>next_dataSequence</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>stallRxed</span>, <span id=t_idt>next_stallRxed</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: getPkt</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_CHK_PID</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_HS</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D1</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D1</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D2</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_FIN</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D2</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D3</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D3</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_GP</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_PKT</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PKT_START</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_EN</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_RDY</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span> <span id=t_cns>5'b10001</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_getPkt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_getPkt</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_kwd>always</span> @
+(<span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RXOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RXTimeOut</span> <span id=t_kwd>or</span>
+  <span id=t_idt>NAKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>stallRxed</span> <span id=t_kwd>or</span>
+  <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>dataSequence</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>RXPktStatus</span> = {
+    <span id=t_idt>dataSequence</span>, <span id=t_idt>ACKRxed</span>,
+    <span id=t_idt>stallRxed</span>, <span id=t_idt>NAKRxed</span>,
+    <span id=t_idt>RXTimeOut</span>, <span id=t_idt>RXOverflow</span>,
+    <span id=t_idt>bitStuffError</span>, <span id=t_idt>CRCError</span>};
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: getPkt</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RXDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>RXStreamStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RXByte</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteOldest</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteOld</span> <span id=t_kwd>or</span> <span id=t_idt>SIERxTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>RXDataValid</span> <span id=t_kwd>or</span> <span id=t_idt>RXStreamStatus</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoFull</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>RXOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RXTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>NAKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>stallRxed</span> <span id=t_kwd>or</span> <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>dataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>RxPID</span> <span id=t_kwd>or</span> <span id=t_idt>RXPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoData</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_getPkt</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>getPkt_NextState</span>
+  <span id=t_idt>NextState_getPkt</span> &lt;= <span id=t_idt>CurrState_getPkt</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>CRCError</span>;
+  <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>bitStuffError</span>;
+  <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_idt>RXOverflow</span>;
+  <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_idt>RXTimeOut</span>;
+  <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_idt>NAKRxed</span>;
+  <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_idt>stallRxed</span>;
+  <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>ACKRxed</span>;
+  <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>dataSequence</span>;
+  <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXByte</span>;
+  <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatus</span>;
+  <span id=t_idt>next_RxPID</span> &lt;= <span id=t_idt>RxPID</span>;
+  <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_idt>RXPacketRdy</span>;
+  <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByteOldest</span>;
+  <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByteOld</span>;
+  <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_idt>RXFifoWEn</span>;
+  <span id=t_idt>next_RXFifoData</span> &lt;= <span id=t_idt>RXFifoData</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_getPkt</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_GP</span>:
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>WAIT_EN</span>;
+   `<span id=t_idt>WAIT_PKT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIERxTimeOut</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>CHK_PKT_START</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PKT_START</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_START</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_CHK_PID</span>;
+      <span id=t_idt>next_RxPID</span> &lt;= <span id=t_idt>RXByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_EN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketEn</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>WAIT_PKT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_CHK_PID</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>HANDSHAKE</span>) 
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_HS</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>DATA</span>) 
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+   `<span id=t_idt>PROC_PKT_HS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>RX_OVERFLOW_BIT</span>];
+      <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>NAK_RXED_BIT</span>];
+      <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>STALL_RXED_BIT</span>];
+      <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>ACK_RXED_BIT</span>];
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_W_D1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D1</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D2</span>;
+      <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_W_D2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D2</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>CRC_ERROR_BIT</span>];
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>BIT_STUFF_ERROR_BIT</span>];
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>DATA_SEQUENCE_BIT</span>];
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D3</span>;
+      <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_W_D3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D3</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXFifoFull</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span>;
+      <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>;
+      <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_RXFifoData</span> &lt;= <span id=t_idt>RXByteOldest</span>;
+      <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByteOld</span>;
+      <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span>:
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>;
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> ((<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStreamStatusIn</span> == `<span id=t_idt>RX_PACKET_STREAM</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span>:
+     <span id=t_idt>NextState_getPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>getPkt_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_getPkt</span> &lt;= `<span id=t_idt>START_GP</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_getPkt</span> &lt;= <span id=t_idt>NextState_getPkt</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>getPkt_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXByteOld</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXByteOldest</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXStreamStatus</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXFifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXFifoData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxPID</span> &lt;= <span id=t_cns>4'h0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXByteOld</span> &lt;= <span id=t_idt>next_RXByteOld</span>;
+   <span id=t_idt>RXByteOldest</span> &lt;= <span id=t_idt>next_RXByteOldest</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_idt>next_CRCError</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_idt>next_bitStuffError</span>;
+   <span id=t_idt>RXOverflow</span> &lt;= <span id=t_idt>next_RXOverflow</span>;
+   <span id=t_idt>RXTimeOut</span> &lt;= <span id=t_idt>next_RXTimeOut</span>;
+   <span id=t_idt>NAKRxed</span> &lt;= <span id=t_idt>next_NAKRxed</span>;
+   <span id=t_idt>stallRxed</span> &lt;= <span id=t_idt>next_stallRxed</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_idt>next_ACKRxed</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_idt>next_dataSequence</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_idt>next_RXByte</span>;
+   <span id=t_idt>RXStreamStatus</span> &lt;= <span id=t_idt>next_RXStreamStatus</span>;
+   <span id=t_idt>RXPacketRdy</span> &lt;= <span id=t_idt>next_RXPacketRdy</span>;
+   <span id=t_idt>RXFifoWEn</span> &lt;= <span id=t_idt>next_RXFifoWEn</span>;
+   <span id=t_idt>RXFifoData</span> &lt;= <span id=t_idt>next_RXFifoData</span>;
+   <span id=t_idt>RxPID</span> &lt;= <span id=t_idt>next_RxPID</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/getpacket.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1059,1575,1161,1677,Click33,Over33);
+
+//----------------------------------------------------------------------------
+function Click33(){fubclick('./index33.htm');}
+function Over33(){window.status='Hierarchical State PROC_PKT';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./getpacket.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./getpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/getpacket.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hctxportarbiter" alt="hctxportarbiter"
+				width=2040 height=2640 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 3400 ;
+var PageY = 4400 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 2040;
+var h = 2640;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hctxportarbiter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hctxportarbiter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hctxportarbiter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram49.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram49.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram49.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="hostcontroller OUT0" alt="hostcontroller OUT0"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/diagram49.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar43.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar43.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar43.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 43 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket_SEND_SOF.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar43.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram32.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram32.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram32.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacketcheckpreamble PREAM_PKT" alt="sendpacketcheckpreamble PREAM_PKT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram32.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index95.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index95.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index95.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar95.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram95.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index95.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar41.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar41.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar41.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 41 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket_OUT_IN_SETUP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar41.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacketcheckpreamble" alt="sendpacketcheckpreamble"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index32.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index32.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index32.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar32.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram32.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index32.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller_IN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/hostcontroller_IN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index51.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index51.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index51.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar51.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram51.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/index51.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar49.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar49.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar49.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 49 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./hostcontroller_OUT0.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./hostcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/hostcontroller.asf/toolbar49.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram21.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram21.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram21.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacket SEND_PID" alt="sendpacket SEND_PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/diagram21.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index45.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index45.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index45.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar45.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram45.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/index45.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket_OUT_IN_SETUP.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/sendpacket_OUT_IN_SETUP.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar21.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar21.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar21.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 21 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket_SEND_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar21.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacketarbiter" alt="sendpacketarbiter"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacketarbiter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacketarbiter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm	(revision 264)
@@ -0,0 +1,235 @@
+<html>
+<head>
+<title>sendpacketcheckpreamble.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// sendPacketCheckPreamble</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:06 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>sendPacketCheckPreamble</span> (<span id=t_idt>clk</span>, <span id=t_idt>fullSpeedBitRate</span>, <span id=t_idt>fullSpeedPolarity</span>, <span id=t_idt>grabLineControl</span>, <span id=t_idt>preAmbleEnable</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketCPPID</span>, <span id=t_idt>sendPacketCPReady</span>, <span id=t_idt>sendPacketCPWEn</span>, <span id=t_idt>sendPacketPID</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>preAmbleEnable</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCPPID</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketCPWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fullSpeedBitRate</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>grabLineControl</span>;   <span id=t_com>// mux select</span>
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketCPReady</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>fullSpeedBitRate</span>, <span id=t_idt>next_fullSpeedBitRate</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>fullSpeedPolarity</span>, <span id=t_idt>next_fullSpeedPolarity</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>grabLineControl</span>, <span id=t_idt>next_grabLineControl</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>preAmbleEnable</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCPPID</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketCPReady</span>, <span id=t_idt>next_sendPacketCPReady</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketCPWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>, <span id=t_idt>next_sendPacketPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>next_sendPacketWEn</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: sendPktCP</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>SPC_WAIT_EN</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SPC</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PREAM</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_SND_PREAM</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_WAIT_RDY1</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_WAIT_RDY2</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_SND_PID</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAM_PKT_WAIT_RDY3</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>REG_PKT_SEND_PID</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>REG_PKT_WAIT_RDY1</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>REG_PKT_WAIT_RDY</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>READY</span> <span id=t_cns>4'b1011</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_sendPktCP</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_sendPktCP</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: sendPktCP</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>sendPacketCPPID</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketCPWEn</span> <span id=t_kwd>or</span> <span id=t_idt>preAmbleEnable</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketCPReady</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketPID</span> <span id=t_kwd>or</span> <span id=t_idt>fullSpeedBitRate</span> <span id=t_kwd>or</span> <span id=t_idt>fullSpeedPolarity</span> <span id=t_kwd>or</span> <span id=t_idt>grabLineControl</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_sendPktCP</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktCP_NextState</span>
+  <span id=t_idt>NextState_sendPktCP</span> &lt;= <span id=t_idt>CurrState_sendPktCP</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketCPReady</span> &lt;= <span id=t_idt>sendPacketCPReady</span>;
+  <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+  <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketPID</span>;
+  <span id=t_idt>next_fullSpeedBitRate</span> &lt;= <span id=t_idt>fullSpeedBitRate</span>;
+  <span id=t_idt>next_fullSpeedPolarity</span> &lt;= <span id=t_idt>fullSpeedPolarity</span>;
+  <span id=t_idt>next_grabLineControl</span> &lt;= <span id=t_idt>grabLineControl</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_sendPktCP</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>SPC_WAIT_EN</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketCPWEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>CHK_PREAM</span>;
+      <span id=t_idt>next_sendPacketCPReady</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>START_SPC</span>:
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>SPC_WAIT_EN</span>;
+   `<span id=t_idt>CHK_PREAM</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>preAmbleEnable</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_WAIT_RDY1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>REG_PKT_WAIT_RDY1</span>;
+   `<span id=t_idt>READY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketCPReady</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>SPC_WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_SND_PREAM</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>PREAMBLE</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_WAIT_RDY2</span>;
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_WAIT_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_SND_PREAM</span>;
+      <span id=t_idt>next_fullSpeedBitRate</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_fullSpeedPolarity</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_grabLineControl</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_WAIT_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_SND_PID</span>;
+      <span id=t_idt>next_fullSpeedBitRate</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_SND_PID</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketCPPID</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>PREAM_PKT_WAIT_RDY3</span>;
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PREAM_PKT_WAIT_RDY3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>READY</span>;
+      <span id=t_idt>next_grabLineControl</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>REG_PKT_SEND_PID</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketCPPID</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>REG_PKT_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>REG_PKT_WAIT_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>REG_PKT_SEND_PID</span>;
+   `<span id=t_idt>REG_PKT_WAIT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sendPktCP</span> &lt;= `<span id=t_idt>READY</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktCP_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_sendPktCP</span> &lt;= `<span id=t_idt>START_SPC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_sendPktCP</span> &lt;= <span id=t_idt>NextState_sendPktCP</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktCP_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_cns>4'b0</span>;
+   <span id=t_idt>fullSpeedBitRate</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>fullSpeedPolarity</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>grabLineControl</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketCPReady</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_idt>next_sendPacketWEn</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_idt>next_sendPacketPID</span>;
+   <span id=t_idt>fullSpeedBitRate</span> &lt;= <span id=t_idt>next_fullSpeedBitRate</span>;
+   <span id=t_idt>fullSpeedPolarity</span> &lt;= <span id=t_idt>next_fullSpeedPolarity</span>;
+   <span id=t_idt>grabLineControl</span> &lt;= <span id=t_idt>next_grabLineControl</span>;
+   <span id=t_idt>sendPacketCPReady</span> &lt;= <span id=t_idt>next_sendPacketCPReady</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble_REG_PKT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble_REG_PKT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sofcontroller" alt="sofcontroller"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sofcontroller.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sofcontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble_PREAM_PKT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble_PREAM_PKT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 95 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacketcheckpreamble_REG_PKT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacketcheckpreamble.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar95.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 32 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacketcheckpreamble_PREAM_PKT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacketcheckpreamble.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar32.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar45.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar45.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar45.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 45 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacket_DATA0_DATA1.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacket.asf/toolbar45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm	(revision 264)
@@ -0,0 +1,196 @@
+<html>
+<head>
+<title>sendpacketarbiter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// sendPacketArbiter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:02 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>sendPacketArbiter</span> (<span id=t_idt>HCTxGnt</span>, <span id=t_idt>HCTxReq</span>, <span id=t_idt>HC_PID</span>, <span id=t_idt>HC_SP_WEn</span>, <span id=t_idt>SOFTxGnt</span>, <span id=t_idt>SOFTxReq</span>, <span id=t_idt>SOF_SP_WEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketPID</span>, <span id=t_idt>sendPacketWEnable</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxReq</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>HC_PID</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>HC_SP_WEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFTxReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOF_SP_WEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxGnt</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SOFTxGnt</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEnable</span>;
+
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxGnt</span>, <span id=t_idt>next_HCTxGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxReq</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>HC_PID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HC_SP_WEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFTxGnt</span>, <span id=t_idt>next_SOFTxGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFTxReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOF_SP_WEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>, <span id=t_idt>next_sendPacketPID</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEnable</span>, <span id=t_idt>next_sendPacketWEnable</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>muxSOFNotHC</span>, <span id=t_idt>next_muxSOFNotHC</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: sendPktArb</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_ACT</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_ACT</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>SARB_WAIT_REQ</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SARB</span> <span id=t_cns>2'b11</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_sendPktArb</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_sendPktArb</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// hostController/SOFTransmit mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>muxSOFNotHC</span> <span id=t_kwd>or</span> <span id=t_idt>SOF_SP_WEn</span> <span id=t_kwd>or</span> <span id=t_idt>HC_SP_WEn</span> <span id=t_kwd>or</span> <span id=t_idt>HC_PID</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>muxSOFNotHC</span>  == <span id=t_cns>1'b1</span>)
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>sendPacketWEnable</span> &lt;= <span id=t_idt>SOF_SP_WEn</span>;
+        <span id=t_idt>sendPacketPID</span> &lt;= `<span id=t_idt>SOF</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span>
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>sendPacketWEnable</span> &lt;= <span id=t_idt>HC_SP_WEn</span>;
+        <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_idt>HC_PID</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: sendPktArb</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>HCTxReq</span> <span id=t_kwd>or</span> <span id=t_idt>SOFTxReq</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxGnt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFTxGnt</span> <span id=t_kwd>or</span> <span id=t_idt>muxSOFNotHC</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_sendPktArb</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktArb_NextState</span>
+  <span id=t_idt>NextState_sendPktArb</span> &lt;= <span id=t_idt>CurrState_sendPktArb</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_HCTxGnt</span> &lt;= <span id=t_idt>HCTxGnt</span>;
+  <span id=t_idt>next_SOFTxGnt</span> &lt;= <span id=t_idt>SOFTxGnt</span>;
+  <span id=t_idt>next_muxSOFNotHC</span> &lt;= <span id=t_idt>muxSOFNotHC</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_sendPktArb</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>HC_ACT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>SARB_WAIT_REQ</span>;
+      <span id=t_idt>next_HCTxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SOF_ACT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTxReq</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>SARB_WAIT_REQ</span>;
+      <span id=t_idt>next_SOFTxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SARB_WAIT_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTxReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>SOF_ACT</span>;
+      <span id=t_idt>next_SOFTxGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxSOFNotHC</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>HCTxReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>HC_ACT</span>;
+      <span id=t_idt>next_HCTxGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxSOFNotHC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>START_SARB</span>:
+     <span id=t_idt>NextState_sendPktArb</span> &lt;= `<span id=t_idt>SARB_WAIT_REQ</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktArb_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_sendPktArb</span> &lt;= `<span id=t_idt>START_SARB</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_sendPktArb</span> &lt;= <span id=t_idt>NextState_sendPktArb</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sendPktArb_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxSOFNotHC</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SOFTxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxSOFNotHC</span> &lt;= <span id=t_idt>next_muxSOFNotHC</span>;
+   <span id=t_idt>SOFTxGnt</span> &lt;= <span id=t_idt>next_SOFTxGnt</span>;
+   <span id=t_idt>HCTxGnt</span> &lt;= <span id=t_idt>next_HCTxGnt</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketarbiter.asf/sendpacketarbiter.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram95.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram95.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram95.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sendpacketcheckpreamble REG_PKT" alt="sendpacketcheckpreamble REG_PKT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/diagram95.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/sendpacketcheckpreamble.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(396,1432,498,1534,Click32,Over32);
+FUB[1] = new Array(1299,1396,1401,1499,Click95,Over95);
+
+//----------------------------------------------------------------------------
+function Click32(){fubclick('./index32.htm');}
+function Over32(){window.status='Hierarchical State PREAM_PKT';};
+function Click95(){fubclick('./index95.htm');}
+function Over95(){window.status='Hierarchical State REG_PKT';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sendpacketcheckpreamble.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sendpacketcheckpreamble.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sendpacketcheckpreamble.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="softransmit" alt="softransmit"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./softransmit.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./softransmit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm	(revision 264)
@@ -0,0 +1,104 @@
+<html>
+<head>
+<title>hostSlaveMuxBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// hostSlaveMuxBI.v                                             ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:12 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+ <span id=t_kwd>module</span> <span id=t_idt>hostSlaveMuxBI</span> (<span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>, <span id=t_idt>strobe_i</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>hostMode</span>, <span id=t_idt>hostSlaveMuxSel</span>);
+
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostSlaveMuxSel</span>;
+<span id=t_kwd>output</span> <span id=t_idt>hostMode</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSlaveMuxSel</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>hostMode</span>;
+
+<span id=t_com>//internal wire and regs</span>
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_idt>hostMode</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>hostSlaveMuxSel</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span>)
+     <span id=t_idt>hostMode</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>hostMode</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>7'h0</span>, <span id=t_idt>hostMode</span>};
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostSlaveMux/hostSlaveMuxBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/include/usbSlaveControl_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/include/usbSlaveControl_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/include/usbSlaveControl_h.v/index.htm	(revision 264)
@@ -0,0 +1,135 @@
+<html>
+<head>
+<title>usbSlaveControl_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbSlaveControl.v                                            ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:13 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_com>//endPointConstants </span>
+<span id=t_dir>`define</span> <span id=t_idt>NUM_OF_ENDPOINTS</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>NUM_OF_REGISTERS_PER_ENDPOINT</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>BASE_INDEX_FOR_ENDPOINT_REGS</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_CONTROL_REG</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_STATUS_REG</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_TRANSTYPE_STATUS_REG</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK_TRANSTYPE_STATUS_REG</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_CTRL_REG</span> <span id=t_cns>5'h0</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_STS_REG</span> <span id=t_cns>5'h1</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'h2</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_NAK_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'h3</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_CTRL_REG</span> <span id=t_cns>5'h4</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_STS_REG</span> <span id=t_cns>5'h5</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'h6</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_NAK_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'h7</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_CTRL_REG</span> <span id=t_cns>5'h8</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_STS_REG</span> <span id=t_cns>5'h9</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'ha</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_NAK_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'hb</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_CTRL_REG</span> <span id=t_cns>5'hc</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_STS_REG</span> <span id=t_cns>5'hd</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'he</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_NAK_TRAN_TYPE_STS_REG</span> <span id=t_cns>5'hf</span>
+
+
+<span id=t_com>//SCRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>LAST_ENDP_REG</span> = `<span id=t_idt>BASE_INDEX_FOR_ENDPOINT_REGS</span> + (`<span id=t_idt>NUM_OF_REGISTERS_PER_ENDPOINT</span> * `<span id=t_idt>NUM_OF_ENDPOINTS</span>) - <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_CONTROL_REG</span> <span id=t_cns>5'h10</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_LINE_STATUS_REG</span> <span id=t_cns>5'h11</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_INTERRUPT_STATUS_REG</span> <span id=t_cns>5'h12</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_INTERRUPT_MASK_REG</span> <span id=t_cns>5'h13</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_ADDRESS</span> <span id=t_cns>5'h14</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_FRAME_NUM_MSP</span> <span id=t_cns>5'h15</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_FRAME_NUM_LSP</span> <span id=t_cns>5'h16</span>
+<span id=t_dir>`define</span> <span id=t_idt>SCREG_BUFFER_LEN</span> <span id=t_cns>5'h17</span>
+<span id=t_com>//SCRXStatusRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK_SET_MASK</span> <span id=t_cns>8'h10</span>
+<span id=t_com>//`define CRC_ERROR_BIT 0</span>
+<span id=t_com>//`define BIT_STUFF_ERROR_BIT 1</span>
+<span id=t_com>//`define RX_OVERFLOW_BIT 2</span>
+<span id=t_com>//`define RX_TIME_OUT_BIT 3</span>
+<span id=t_com>//`define NAK_SENT_BIT 4</span>
+<span id=t_com>//`define STALL_SENT_BIT 5</span>
+<span id=t_com>//`define ACK_RXED_BIT 6</span>
+<span id=t_com>//`define DATA_SEQUENCE_BIT 7</span>
+<span id=t_com>//SCEndPointControlRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_ENABLE_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_READY_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_OUTDATA_SEQUENCE_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>ENDPOINT_SEND_STALL_BIT</span> <span id=t_cns>3</span>
+<span id=t_com>//SCMasterControlegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_GLOBAL_ENABLE_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_TX_LINE_STATE_LSBIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_TX_LINE_STATE_MSBIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_DIRECT_CONTROL_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_FULL_SPEED_LINE_POLARITY_BIT</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_FULL_SPEED_LINE_RATE_BIT</span> <span id=t_cns>5</span>
+<span id=t_com>//SCinterruptRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>TRANS_DONE_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_INT_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESET_EVENT_BIT</span> <span id=t_cns>2</span>  <span id=t_com>//Line has entered reset state or left reset state</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_RECEIVED_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK_SENT_INT_BIT</span> <span id=t_cns>4</span>
+<span id=t_com>//TXTransactionTypes </span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_SETUP_TRANS</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_IN_TRANS</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_OUTDATA_TRANS</span> <span id=t_cns>2</span>
+<span id=t_com>//timeOuts </span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_RX_PACKET_TOUT</span> <span id=t_cns>18</span>
+       
+
+</pre>
+</body>
+</html>

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+*
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Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm	(revision 264)
@@ -0,0 +1,189 @@
+<html>
+<head>
+<title>softransmit.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SOFTransmit</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:09 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbHostControl_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>SOFTransmit</span> (<span id=t_idt>SOFEnable</span>, <span id=t_idt>SOFSent</span>, <span id=t_idt>SOFSyncEn</span>, <span id=t_idt>SOFTimerClr</span>, <span id=t_idt>SOFTimer</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketArbiterGnt</span>, <span id=t_idt>sendPacketArbiterReq</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>SOFEnable</span>;   <span id=t_com>// After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn</span>
+<span id=t_kwd>input</span>   <span id=t_idt>SOFSyncEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketArbiterGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SOFSent</span>;   <span id=t_com>// single cycle pulse</span>
+<span id=t_kwd>output</span>  <span id=t_idt>SOFTimerClr</span>;   <span id=t_com>// Single cycle pulse</span>
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketArbiterReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFEnable</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFSent</span>, <span id=t_idt>next_SOFSent</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFSyncEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFTimerClr</span>, <span id=t_idt>next_SOFTimerClr</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketArbiterGnt</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketArbiterReq</span>, <span id=t_idt>next_sendPacketArbiterReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>next_sendPacketWEn</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: SOFTx</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_STX</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SOF_NEAR</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SP_GNT</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SOF_NOW</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_FIN</span> <span id=t_cns>3'b100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_SOFTx</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_SOFTx</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: SOFTx</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>SOFTimer</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSyncEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFEnable</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketArbiterGnt</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketArbiterReq</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SOFTimerClr</span> <span id=t_kwd>or</span> <span id=t_idt>SOFSent</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_SOFTx</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SOFTx_NextState</span>
+  <span id=t_idt>NextState_SOFTx</span> &lt;= <span id=t_idt>CurrState_SOFTx</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_idt>sendPacketArbiterReq</span>;
+  <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+  <span id=t_idt>next_SOFTimerClr</span> &lt;= <span id=t_idt>SOFTimerClr</span>;
+  <span id=t_idt>next_SOFSent</span> &lt;= <span id=t_idt>SOFSent</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_SOFTx</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_STX</span>:
+     <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>WAIT_SOF_NEAR</span>;
+   `<span id=t_idt>WAIT_SOF_NEAR</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTimer</span> &gt;= `<span id=t_idt>SOF_TX_TIME</span> - `<span id=t_idt>SOF_TX_MARGIN</span> ||
+      (<span id=t_idt>SOFSyncEn</span> == <span id=t_cns>1'b1</span> &amp;&amp;
+      <span id=t_idt>SOFEnable</span> == <span id=t_cns>1'b1</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>WAIT_SP_GNT</span>;
+      <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_SP_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketArbiterGnt</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>WAIT_SOF_NOW</span>;
+   `<span id=t_idt>WAIT_SOF_NOW</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTimer</span> &gt;= `<span id=t_idt>SOF_TX_TIME</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>SOF_FIN</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SOFTimerClr</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SOFSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SOFEnable</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>SOF_FIN</span>;
+      <span id=t_idt>next_SOFTimerClr</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SOF_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SOFTimerClr</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SOFSent</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SOFTx</span> &lt;= `<span id=t_idt>WAIT_SOF_NEAR</span>;
+     <span id=t_idt>next_sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SOFTx_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_SOFTx</span> &lt;= `<span id=t_idt>START_STX</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_SOFTx</span> &lt;= <span id=t_idt>NextState_SOFTx</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SOFTx_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SOFSent</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SOFTimerClr</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketArbiterReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SOFSent</span> &lt;= <span id=t_idt>next_SOFSent</span>;
+   <span id=t_idt>SOFTimerClr</span> &lt;= <span id=t_idt>next_SOFTimerClr</span>;
+   <span id=t_idt>sendPacketArbiterReq</span> &lt;= <span id=t_idt>next_sendPacketArbiterReq</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_idt>next_sendPacketWEn</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/softransmit.v/index.htm
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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostSlaveMux/hostSlaveMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostSlaveMux/hostSlaveMux.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostSlaveMux/hostSlaveMux.v/index.htm	(revision 264)
@@ -0,0 +1,180 @@
+<html>
+<head>
+<title>hostSlaveMux.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// hostSlaveMux.v                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:12 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>hostSlaveMux</span> (
+  <span id=t_idt>SIEPortCtrlInToSIE</span>,
+  <span id=t_idt>SIEPortCtrlInFromHost</span>,
+  <span id=t_idt>SIEPortCtrlInFromSlave</span>,
+  <span id=t_idt>SIEPortDataInToSIE</span>, 
+  <span id=t_idt>SIEPortDataInFromHost</span>, 
+  <span id=t_idt>SIEPortDataInFromSlave</span>, 
+  <span id=t_idt>SIEPortWEnToSIE</span>, 
+  <span id=t_idt>SIEPortWEnFromHost</span>, 
+  <span id=t_idt>SIEPortWEnFromSlave</span>, 
+  <span id=t_idt>fullSpeedPolarityToSIE</span>,
+  <span id=t_idt>fullSpeedPolarityFromHost</span>,
+  <span id=t_idt>fullSpeedPolarityFromSlave</span>,
+  <span id=t_idt>fullSpeedBitRateToSIE</span>,
+  <span id=t_idt>fullSpeedBitRateFromHost</span>,
+  <span id=t_idt>fullSpeedBitRateFromSlave</span>,
+  <span id=t_idt>dataIn</span>, 
+  <span id=t_idt>dataOut</span>, 
+  <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>,
+  <span id=t_idt>hostSlaveMuxSel</span>  );
+
+
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInToSIE</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromHost</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromSlave</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInToSIE</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromHost</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromSlave</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>SIEPortWEnToSIE</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>SIEPortWEnFromHost</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>SIEPortWEnFromSlave</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPolarityToSIE</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedPolarityFromHost</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedPolarityFromSlave</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedBitRateToSIE</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedBitRateFromHost</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedBitRateFromSlave</span>;
+<span id=t_com>//hostSlaveMuxBI</span>
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostSlaveMuxSel</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInToSIE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromHost</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromSlave</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInToSIE</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromHost</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromSlave</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>SIEPortWEnToSIE</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnFromHost</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnFromSlave</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPolarityToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityFromHost</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityFromSlave</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedBitRateToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateFromHost</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateFromSlave</span>;
+<span id=t_com>//hostSlaveMuxBI</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSlaveMuxSel</span>;
+
+<span id=t_com>//internal wires and regs</span>
+<span id=t_kwd>wire</span> <span id=t_idt>hostMode</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_idt>hostMode</span> <span id=t_kwd>or</span>
+  <span id=t_idt>SIEPortCtrlInFromHost</span> <span id=t_kwd>or</span>
+  <span id=t_idt>SIEPortCtrlInFromSlave</span> <span id=t_kwd>or</span>
+  <span id=t_idt>SIEPortDataInFromHost</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SIEPortDataInFromSlave</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SIEPortWEnFromHost</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>SIEPortWEnFromSlave</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>fullSpeedPolarityFromHost</span> <span id=t_kwd>or</span>
+  <span id=t_idt>fullSpeedPolarityFromSlave</span> <span id=t_kwd>or</span>
+  <span id=t_idt>fullSpeedBitRateFromHost</span> <span id=t_kwd>or</span>
+  <span id=t_idt>fullSpeedBitRateFromSlave</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>hostMode</span> == <span id=t_cns>1'b1</span>) 
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>SIEPortCtrlInToSIE</span> &lt;= <span id=t_idt>SIEPortCtrlInFromHost</span>;
+    <span id=t_idt>SIEPortDataInToSIE</span> &lt;=  <span id=t_idt>SIEPortDataInFromHost</span>;
+    <span id=t_idt>SIEPortWEnToSIE</span> &lt;= <span id=t_idt>SIEPortWEnFromHost</span>;
+    <span id=t_idt>fullSpeedPolarityToSIE</span> &lt;= <span id=t_idt>fullSpeedPolarityFromHost</span>;
+    <span id=t_idt>fullSpeedBitRateToSIE</span> &lt;= <span id=t_idt>fullSpeedBitRateFromHost</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>SIEPortCtrlInToSIE</span> &lt;= <span id=t_idt>SIEPortCtrlInFromSlave</span>;
+    <span id=t_idt>SIEPortDataInToSIE</span> &lt;=  <span id=t_idt>SIEPortDataInFromSlave</span>;
+    <span id=t_idt>SIEPortWEnToSIE</span> &lt;= <span id=t_idt>SIEPortWEnFromSlave</span>;
+    <span id=t_idt>fullSpeedPolarityToSIE</span> &lt;= <span id=t_idt>fullSpeedPolarityFromSlave</span>;
+    <span id=t_idt>fullSpeedBitRateToSIE</span> &lt;= <span id=t_idt>fullSpeedBitRateFromSlave</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>      
+
+<span id=t_idt>hostSlaveMuxBI</span> <span id=t_idt>u_hostSlaveMuxBI</span> (
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>dataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataOut</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>hostMode</span>(<span id=t_idt>hostMode</span>), 
+  .<span id=t_idt>hostSlaveMuxSel</span>(<span id=t_idt>hostSlaveMuxSel</span>)  );
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostSlaveMux/hostSlaveMux.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/include/usbSerialInterfaceEngine_h.v/index.htm	(revision 264)
@@ -0,0 +1,147 @@
+<html>
+<head>
+<title>usbSerialInterfaceEngine_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbSerialInterfaceEngine_h.v                                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:13 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+ <span id=t_com>// Sampling at 'OVER_SAMPLE_RATE' * full speed bit rate</span>
+<span id=t_dir>`define</span> <span id=t_idt>OVER_SAMPLE_RATE</span> <span id=t_cns>4</span>
+
+<span id=t_com>//timeOuts</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PACKET_TOUT</span> <span id=t_cns>18</span>
+
+<span id=t_com>//TXStreamControlTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_DIRECT_CONTROL</span> <span id=t_cns>8'h00</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_RESUME_START</span> <span id=t_cns>8'h01</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_PACKET_START</span> <span id=t_cns>8'h02</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_PACKET_STREAM</span> <span id=t_cns>8'h03</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_PACKET_STOP</span> <span id=t_cns>8'h04</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_IDLE</span> <span id=t_cns>8'h05</span>
+
+<span id=t_com>//RXStreamControlTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PACKET_START</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PACKET_STREAM</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PACKET_STOP</span> <span id=t_cns>2</span>
+
+<span id=t_com>//USBLineStates</span>
+<span id=t_com>// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo</span>
+<span id=t_dir>`define</span> <span id=t_idt>ONE_ZERO</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>ZERO_ONE</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>SE0</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>SE1</span> <span id=t_cns>2'b11</span>
+
+<span id=t_com>//RXStatusIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>CRC_ERROR_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>BIT_STUFF_ERROR_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_OVERFLOW_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK_RXED_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>STALL_RXED_BIT</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>ACK_RXED_BIT</span> <span id=t_cns>5</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_SEQUENCE_BIT</span> <span id=t_cns>6</span>
+
+<span id=t_com>//usbWireControlStates</span>
+<span id=t_dir>`define</span> <span id=t_idt>TRI_STATE</span> <span id=t_cns>1'b0</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRIVE</span> <span id=t_cns>1'b1</span>
+
+<span id=t_com>//limits</span>
+<span id=t_dir>`define</span> <span id=t_idt>MAX_CONSEC_SAME_BITS</span> <span id=t_cns>6</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_WAIT_TIME</span> <span id=t_cns>10</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_WAIT_TIME_MINUS1</span> <span id=t_cns>9</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_LEN</span> <span id=t_cns>20</span>
+<span id=t_dir>`define</span> <span id=t_idt>CONNECT_WAIT_TIME</span> <span id=t_cns>8'd20</span>
+<span id=t_dir>`define</span> <span id=t_idt>DISCONNECT_WAIT_TIME</span> <span id=t_cns>8'd20</span>
+
+<span id=t_com>//RXConnectStates</span>
+<span id=t_dir>`define</span> <span id=t_idt>DISCONNECT</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>LOW_SPEED_CONNECT</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>FULL_SPEED_CONNECT</span> <span id=t_cns>2'b10</span>
+
+<span id=t_com>//TX_RX_InternalStreamTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_START</span> <span id=t_cns>8'h00</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_STOP</span> <span id=t_cns>8'h01</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_STREAM</span> <span id=t_cns>8'h02</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_BIT_STUFF_ERROR</span> <span id=t_cns>8'h03</span>
+
+<span id=t_com>//RXStMach states</span>
+<span id=t_dir>`define</span> <span id=t_idt>DISCONNECT_ST</span> <span id=t_cns>4'h0</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FULL_SPEED_CONN_ST</span> <span id=t_cns>4'h1</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LOW_SPEED_CONN_ST</span> <span id=t_cns>4'h2</span>
+<span id=t_dir>`define</span> <span id=t_idt>CONNECT_LOW_SPEED_ST</span> <span id=t_cns>4'h3</span>
+<span id=t_dir>`define</span> <span id=t_idt>CONNECT_FULL_SPEED_ST</span> <span id=t_cns>4'h4</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LOW_SP_DISCONNECT_ST</span> <span id=t_cns>4'h5</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FULL_SP_DISCONNECT_ST</span> <span id=t_cns>4'h6</span>
+
+<span id=t_com>//RXBitStateMachStates</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_BIT_ST</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RECEIVE_BIT_ST</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_RESUME_ST</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_END_WAIT_ST</span> <span id=t_cns>2'b11</span>
+
+<span id=t_com>//RXByteStateMachStates </span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_BYTE_ST</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHECK_SYNC_ST</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHECK_PID_ST</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>HS_BYTE_ST</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN_BYTE_ST</span> <span id=t_cns>3'b100</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_BYTE_ST</span> <span id=t_cns>3'b101</span>
+
+
+
+
+</pre>
+</body>
+</html>

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+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/sofcontroller.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/sofcontroller.png
___________________________________________________________________
Added: svn:executable
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+*
\ No newline at end of property
Added: svn:mime-type
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+application/octet-stream
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Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/softransmit.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/speedCtrlMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/speedCtrlMux.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/speedCtrlMux.v/index.htm	(revision 264)
@@ -0,0 +1,94 @@
+<html>
+<head>
+<title>speedCtrlMux.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// speedCtrlMux.v                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:09 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+<span id=t_kwd>module</span> <span id=t_idt>speedCtrlMux</span> (<span id=t_idt>directCtrlRate</span>, <span id=t_idt>directCtrlPol</span>, <span id=t_idt>sendPacketRate</span>, <span id=t_idt>sendPacketPol</span>, <span id=t_idt>sendPacketSel</span>, <span id=t_idt>fullSpeedRate</span>, <span id=t_idt>fullSpeedPol</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>directCtrlRate</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCtrlPol</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRate</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketPol</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketSel</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fullSpeedPol</span>;
+
+<span id=t_kwd>wire</span>   <span id=t_idt>directCtrlRate</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>directCtrlPol</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>sendPacketRate</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>sendPacketPol</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>sendPacketSel</span>;
+<span id=t_kwd>reg</span>   <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span>   <span id=t_idt>fullSpeedPol</span>;
+
+
+<span id=t_kwd>always</span> @(<span id=t_idt>directCtrlRate</span> <span id=t_kwd>or</span> <span id=t_idt>directCtrlPol</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRate</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketPol</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketSel</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>sendPacketSel</span> == <span id=t_cns>1'b1</span>) 
+  <span id=t_kwd>begin</span>
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>sendPacketRate</span>;
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>sendPacketPol</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>directCtrlRate</span>;
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>directCtrlPol</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/speedCtrlMux.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/include/usbConstants_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/include/usbConstants_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/include/usbConstants_h.v/index.htm	(revision 264)
@@ -0,0 +1,88 @@
+<html>
+<head>
+<title>usbConstants_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbConstants_h.v                                             ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////  USB global constants as defined by USB spec 1.1</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:12 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_com>//PIDTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUT</span> <span id=t_cns>4'h1</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN</span> <span id=t_cns>4'h9</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF</span> <span id=t_cns>4'h5</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP</span> <span id=t_cns>4'hd</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA0</span> <span id=t_cns>4'h3</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA1</span> <span id=t_cns>4'hb</span>
+<span id=t_dir>`define</span> <span id=t_idt>ACK</span> <span id=t_cns>4'h2</span>
+<span id=t_dir>`define</span> <span id=t_idt>NAK</span> <span id=t_cns>4'ha</span>
+<span id=t_dir>`define</span> <span id=t_idt>STALL</span> <span id=t_cns>4'he</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAMBLE</span> <span id=t_cns>4'hc</span> 
+     
+
+<span id=t_com>//PIDGroups</span>
+<span id=t_dir>`define</span> <span id=t_idt>SPECIAL</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>HANDSHAKE</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA</span> <span id=t_cns>2'b11</span>
+
+<span id=t_com>// start of packet SyncByte</span>
+<span id=t_dir>`define</span> <span id=t_idt>SYNC_BYTE</span> <span id=t_cns>8'h80</span>
+
+       
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/include/usbConstants_h.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/include/wishBoneBus_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/include/wishBoneBus_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/include/wishBoneBus_h.v/index.htm	(revision 264)
@@ -0,0 +1,91 @@
+<html>
+<head>
+<title>wishBoneBus_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// wishBoneBus_h.v                                              ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:14 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+ 
+<span id=t_com>//memoryMap</span>
+<span id=t_dir>`define</span> <span id=t_idt>HCREG_BASE</span> <span id=t_cns>8'h00</span>
+<span id=t_dir>`define</span> <span id=t_idt>HCREG_BASE_PLUS_0X10</span> <span id=t_cns>8'h10</span>
+<span id=t_dir>`define</span> <span id=t_idt>HOST_RX_FIFO_BASE</span> <span id=t_cns>8'h20</span>
+<span id=t_dir>`define</span> <span id=t_idt>HOST_TX_FIFO_BASE</span> <span id=t_cns>8'h30</span>
+<span id=t_dir>`define</span> <span id=t_idt>SCREG_BASE</span> <span id=t_cns>8'h40</span>
+<span id=t_dir>`define</span> <span id=t_idt>SCREG_BASE_PLUS_0X10</span> <span id=t_cns>8'h50</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_RX_FIFO_BASE</span> <span id=t_cns>8'h60</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP0_TX_FIFO_BASE</span> <span id=t_cns>8'h70</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_RX_FIFO_BASE</span> <span id=t_cns>8'h80</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP1_TX_FIFO_BASE</span> <span id=t_cns>8'h90</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_RX_FIFO_BASE</span> <span id=t_cns>8'ha0</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP2_TX_FIFO_BASE</span> <span id=t_cns>8'hb0</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_RX_FIFO_BASE</span> <span id=t_cns>8'hc0</span>
+<span id=t_dir>`define</span> <span id=t_idt>EP3_TX_FIFO_BASE</span> <span id=t_cns>8'hd0</span>
+<span id=t_dir>`define</span> <span id=t_idt>HOST_SLAVE_CONTROL_BASE</span> <span id=t_cns>8'he0</span>
+<span id=t_dir>`define</span> <span id=t_idt>ADDRESS_DECODE_MASK</span> <span id=t_cns>8'hf0</span>
+
+<span id=t_com>//FifoAddresses</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_DATA_REG</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_STATUS_REG</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_DATA_COUNT_MSB</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_DATA_COUNT_LSB</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIFO_CONTROL_REG</span> <span id=t_cns>3'b100</span>
+
+
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/include/wishBoneBus_h.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_BYTE1.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_BYTE1.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_HS.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_HS.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_RES_ST.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_RES_ST.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram16.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram16.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram16.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter RES_ST" alt="SIETransmitter RES_ST"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_CRC.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_CRC.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter SPCL" alt="SIETransmitter SPCL"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram455.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter PID" alt="SIETransmitter PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram609.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter PID" alt="SIETransmitter PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram718.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm	(revision 264)
@@ -0,0 +1,195 @@
+<html>
+<head>
+<title>sofcontroller.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SOFController</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:07 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>SOFController</span> (<span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortGnt</span>, <span id=t_idt>HCTxPortRdy</span>, <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>SOFEnable</span>, <span id=t_idt>SOFTimerClr</span>, <span id=t_idt>SOFTimer</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFEnable</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SOFTimerClr</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>HCTxPortWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCntl</span>, <span id=t_idt>next_HCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>, <span id=t_idt>next_HCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortReq</span>, <span id=t_idt>next_HCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>HCTxPortWEn</span>, <span id=t_idt>next_HCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFEnable</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SOFTimerClr</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>, <span id=t_idt>next_SOFTimer</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: sofCntl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SC</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SOF_EN</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SEND_RESUME</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>INC_TIMER</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SC_WAIT_GNT</span> <span id=t_cns>3'b100</span>
+<span id=t_dir>`define</span> <span id=t_idt>CLR_WEN</span> <span id=t_cns>3'b101</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_sofCntl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_sofCntl</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: sofCntl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>SOFTimerClr</span> <span id=t_kwd>or</span> <span id=t_idt>SOFTimer</span> <span id=t_kwd>or</span> <span id=t_idt>SOFEnable</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>HCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_sofCntl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sofCntl_NextState</span>
+  <span id=t_idt>NextState_sofCntl</span> &lt;= <span id=t_idt>CurrState_sofCntl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_idt>HCTxPortReq</span>;
+  <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_idt>HCTxPortWEn</span>;
+  <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_idt>HCTxPortData</span>;
+  <span id=t_idt>next_HCTxPortCntl</span> &lt;= <span id=t_idt>HCTxPortCntl</span>;
+  <span id=t_idt>next_SOFTimer</span> &lt;= <span id=t_idt>SOFTimer</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_sofCntl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SC</span>:
+     <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>WAIT_SOF_EN</span>;
+   `<span id=t_idt>WAIT_SOF_EN</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFEnable</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>SC_WAIT_GNT</span>;
+      <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_SEND_RESUME</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>CLR_WEN</span>;
+      <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_HCTxPortCntl</span> &lt;= `<span id=t_idt>TX_RESUME_START</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>INC_TIMER</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFTimerClr</span> == <span id=t_cns>1'b1</span>)
+       <span id=t_idt>next_SOFTimer</span> &lt;= <span id=t_cns>16'h0000</span>;
+     <span id=t_kwd>else</span>
+       <span id=t_idt>next_SOFTimer</span> &lt;= <span id=t_idt>SOFTimer</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SOFEnable</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>WAIT_SOF_EN</span>;
+      <span id=t_idt>next_SOFTimer</span> &lt;= <span id=t_cns>16'h0000</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SC_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>HCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>WAIT_SEND_RESUME</span>;
+   `<span id=t_idt>CLR_WEN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_sofCntl</span> &lt;= `<span id=t_idt>INC_TIMER</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sofCntl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_sofCntl</span> &lt;= `<span id=t_idt>START_SC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_sofCntl</span> &lt;= <span id=t_idt>NextState_sofCntl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>sofCntl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SOFTimer</span> &lt;= <span id=t_cns>16'h0000</span>;
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SOFTimer</span> &lt;= <span id=t_idt>next_SOFTimer</span>;
+   <span id=t_idt>HCTxPortCntl</span> &lt;= <span id=t_idt>next_HCTxPortCntl</span>;
+   <span id=t_idt>HCTxPortData</span> &lt;= <span id=t_idt>next_HCTxPortData</span>;
+   <span id=t_idt>HCTxPortWEn</span> &lt;= <span id=t_idt>next_HCTxPortWEn</span>;
+   <span id=t_idt>HCTxPortReq</span> &lt;= <span id=t_idt>next_HCTxPortReq</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/hostController/sofcontroller.asf/sofcontroller.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar213.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram213.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index213.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar465.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram465.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index465.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_IDLE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_IDLE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_SPCL.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_SPCL.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter DIR_CTL" alt="SIETransmitter DIR_CTL"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram213.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter DATA" alt="SIETransmitter DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram465.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter BYTE1" alt="SIETransmitter BYTE1"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram617.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter CRC" alt="SIETransmitter CRC"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram720.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.v/index.htm	(revision 264)
@@ -0,0 +1,717 @@
+<html>
+<head>
+<title>SIETransmitter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SIETransmitter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:02 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>SIETransmitter</span> (<span id=t_idt>CRC16En</span>, <span id=t_idt>CRC16Result</span>, <span id=t_idt>CRC16UpdateRdy</span>, <span id=t_idt>CRC5En</span>, <span id=t_idt>CRC5Result</span>, <span id=t_idt>CRC5UpdateRdy</span>, <span id=t_idt>CRC5_8Bit</span>, <span id=t_idt>CRCData</span>, <span id=t_idt>JBit</span>, <span id=t_idt>KBit</span>, <span id=t_idt>SIEPortCtrlIn</span>, <span id=t_idt>SIEPortDataIn</span>, <span id=t_idt>SIEPortTxRdy</span>, <span id=t_idt>SIEPortWEn</span>, <span id=t_idt>TxByteOutCtrl</span>, <span id=t_idt>TxByteOut</span>, <span id=t_idt>USBWireCtrl</span>, <span id=t_idt>USBWireData</span>, <span id=t_idt>USBWireGnt</span>, <span id=t_idt>USBWireRdy</span>, <span id=t_idt>USBWireReq</span>, <span id=t_idt>USBWireWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>processTxByteRdy</span>, <span id=t_idt>processTxByteWEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>rstCRC</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC16Result</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC16UpdateRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC5Result</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC5UpdateRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlIn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIEPortWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processTxByteRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC16En</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC5En</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC5_8Bit</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SIEPortTxRdy</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteOutCtrl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireCtrl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processTxByteWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>rstCRC</span>;
+
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC16En</span>, <span id=t_idt>next_CRC16En</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC16Result</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>CRC16UpdateRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC5En</span>, <span id=t_idt>next_CRC5En</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC5Result</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>CRC5UpdateRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC5_8Bit</span>, <span id=t_idt>next_CRC5_8Bit</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCData</span>, <span id=t_idt>next_CRCData</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlIn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SIEPortTxRdy</span>, <span id=t_idt>next_SIEPortTxRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIEPortWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteOutCtrl</span>, <span id=t_idt>next_TxByteOutCtrl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteOut</span>, <span id=t_idt>next_TxByteOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireCtrl</span>, <span id=t_idt>next_USBWireCtrl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireData</span>, <span id=t_idt>next_USBWireData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireReq</span>, <span id=t_idt>next_USBWireReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireWEn</span>, <span id=t_idt>next_USBWireWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processTxByteRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processTxByteWEn</span>, <span id=t_idt>next_processTxByteWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>rstCRC</span>, <span id=t_idt>next_rstCRC</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>SIEPortCtrl</span>, <span id=t_idt>next_SIEPortCtrl</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>SIEPortData</span>, <span id=t_idt>next_SIEPortData</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>4</span>:<span id=t_cns>0</span>]<span id=t_idt>i</span>, <span id=t_idt>next_i</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: SIETx</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_CHK_FIN</span> <span id=t_cns>6'b000000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_CHK_FIN</span> <span id=t_cns>6'b000001</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIR_CTL_CHK_FIN</span> <span id=t_cns>6'b000010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_CHK_PID</span> <span id=t_cns>6'b000011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_CHK_STOP</span> <span id=t_cns>6'b000100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_PKT_SENT</span> <span id=t_cns>6'b000101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_PKT_SENT</span> <span id=t_cns>6'b000110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_PID_PKT_SENT</span> <span id=t_cns>6'b000111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_PKT_SENT</span> <span id=t_cns>6'b001000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_PID_PKT_SENT</span> <span id=t_cns>6'b001001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_HS_PKT_SENT</span> <span id=t_cns>6'b001010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT1</span> <span id=t_cns>6'b001011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_PKT_SENT1</span> <span id=t_cns>6'b001100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT2</span> <span id=t_cns>6'b001101</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S1</span> <span id=t_cns>6'b001110</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S3</span> <span id=t_cns>6'b001111</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S4</span> <span id=t_cns>6'b010000</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S5</span> <span id=t_cns>6'b010001</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_S6</span> <span id=t_cns>6'b010010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_SEND_IDLE1</span> <span id=t_cns>6'b010011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_SEND_IDLE2</span> <span id=t_cns>6'b010100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_SEND_IDLE3</span> <span id=t_cns>6'b010101</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SIETX</span> <span id=t_cns>6'b010110</span>
+<span id=t_dir>`define</span> <span id=t_idt>STX_CHK_ST</span> <span id=t_cns>6'b010111</span>
+<span id=t_dir>`define</span> <span id=t_idt>STX_WAIT_BYTE</span> <span id=t_cns>6'b011000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_STX_WAIT_GNT</span> <span id=t_cns>6'b011001</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_STX_WAIT_RDY</span> <span id=t_cns>6'b011010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_UPD_CRC</span> <span id=t_cns>6'b011011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_UPD_CRC</span> <span id=t_cns>6'b011100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_UPD_CRC</span> <span id=t_cns>6'b011101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_WAIT_BYTE</span> <span id=t_cns>6'b011110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_BYTE</span> <span id=t_cns>6'b011111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_WAIT_BYTE</span> <span id=t_cns>6'b100000</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIR_CTL_WAIT_GNT</span> <span id=t_cns>6'b100001</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_WAIT_GNT</span> <span id=t_cns>6'b100010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_HS_WAIT_RDY</span> <span id=t_cns>6'b100011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_PID_WAIT_RDY</span> <span id=t_cns>6'b100100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_WAIT_RDY</span> <span id=t_cns>6'b100101</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_ST_WAIT_RDY</span> <span id=t_cns>6'b100110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_WAIT_RDY</span> <span id=t_cns>6'b100111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_PID_WAIT_RDY</span> <span id=t_cns>6'b101000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_WAIT_RDY</span> <span id=t_cns>6'b101001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_RDY</span> <span id=t_cns>6'b101010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIR_CTL_WAIT_RDY</span> <span id=t_cns>6'b101011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY1</span> <span id=t_cns>6'b101100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY2</span> <span id=t_cns>6'b101101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_WAIT_RDY_PKT</span> <span id=t_cns>6'b101110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_SPCL_WAIT_WIRE</span> <span id=t_cns>6'b101111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_WAIT_RDY_WIRE</span> <span id=t_cns>6'b110000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_WAIT_GNT</span> <span id=t_cns>6'b110001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_CRC_WAIT_CRC_RDY</span> <span id=t_cns>6'b110010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_DATA_DATA_WAIT_CRC_RDY</span> <span id=t_cns>6'b110011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_CRC_RDY</span> <span id=t_cns>6'b110100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>5</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_SIETx</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>5</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_SIETx</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: SIETx</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>SIEPortDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortCtrlIn</span> <span id=t_kwd>or</span> <span id=t_idt>i</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortData</span> <span id=t_kwd>or</span> <span id=t_idt>JBit</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16Result</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5Result</span> <span id=t_kwd>or</span> <span id=t_idt>KBit</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireGnt</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireRdy</span> <span id=t_kwd>or</span> <span id=t_idt>processTxByteRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16UpdateRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5UpdateRdy</span> <span id=t_kwd>or</span> <span id=t_idt>processTxByteWEn</span> <span id=t_kwd>or</span> <span id=t_idt>TxByteOut</span> <span id=t_kwd>or</span> <span id=t_idt>TxByteOutCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireData</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireReq</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireWEn</span> <span id=t_kwd>or</span> <span id=t_idt>rstCRC</span> <span id=t_kwd>or</span> <span id=t_idt>CRCData</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5En</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5_8Bit</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16En</span> <span id=t_kwd>or</span> <span id=t_idt>SIEPortTxRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_SIETx</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SIETx_NextState</span>
+  <span id=t_idt>NextState_SIETx</span> &lt;= <span id=t_idt>CurrState_SIETx</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_idt>processTxByteWEn</span>;
+  <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>TxByteOut</span>;
+  <span id=t_idt>next_TxByteOutCtrl</span> &lt;= <span id=t_idt>TxByteOutCtrl</span>;
+  <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>USBWireData</span>;
+  <span id=t_idt>next_USBWireCtrl</span> &lt;= <span id=t_idt>USBWireCtrl</span>;
+  <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_idt>USBWireReq</span>;
+  <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_idt>USBWireWEn</span>;
+  <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_idt>rstCRC</span>;
+  <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>CRCData</span>;
+  <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_idt>CRC5En</span>;
+  <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_idt>CRC5_8Bit</span>;
+  <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_idt>CRC16En</span>;
+  <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_idt>SIEPortTxRdy</span>;
+  <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortData</span>;
+  <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrl</span>;
+  <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_SIETx</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SIETX</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_TxByteOutCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_i</span> &lt;= <span id=t_cns>5'h0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STX_CHK_ST</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_PACKET_START</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_WAIT_GNT</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_IDLE</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>IDLE_STX_WAIT_GNT</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_DIRECT_CONTROL</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>DIR_CTL_WAIT_GNT</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_RESUME_START</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_WAIT_GNT</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_i</span> &lt;= <span id=t_cns>5'h0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>STX_WAIT_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_CHK_ST</span>;
+      <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortDataIn</span>;
+      <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrlIn</span>;
+      <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DIR_CTL_CHK_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>5'h7</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>DIR_CTL_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DIR_CTL_WAIT_GNT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_i</span> &lt;= <span id=t_cns>5'h0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>DIR_CTL_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DIR_CTL_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>DIR_CTL_CHK_FIN</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>];
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_CHK_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>5'h7</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>IDLE_STX_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_STX_WAIT_GNT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_i</span> &lt;= <span id=t_cns>5'h0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>IDLE_STX_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_STX_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>IDLE_CHK_FIN</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_CHK_PID</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>HANDSHAKE</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_HS_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>TOKEN</span>) 
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_PID_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>SPECIAL</span>) 
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIEPortData</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>DATA</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_PID_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_WAIT_RDY_PKT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_CHK_PID</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= `<span id=t_idt>SYNC_BYTE</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_START</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_WAIT_RDY_WIRE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_WAIT_RDY_PKT</span>;
+      <span id=t_com>//actively drive the first J bit</span>
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_WAIT_RDY_WIRE</span>;
+   `<span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY2</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT1</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= ~<span id=t_idt>CRC16Result</span>[<span id=t_cns>7</span>:<span id=t_cns>0</span>];
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_CRC_PKT_SENT2</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= ~<span id=t_idt>CRC16Result</span>[<span id=t_cns>15</span>:<span id=t_cns>8</span>];
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_CHK_STOP</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortCtrl</span> == `<span id=t_idt>TX_PACKET_STOP</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_CRC_WAIT_RDY1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_CRC_RDY</span>;
+   `<span id=t_idt>PKT_ST_DATA_DATA_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_UPD_CRC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>SIEPortData</span>;
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_CHK_STOP</span>;
+      <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortDataIn</span>;
+      <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrlIn</span>;
+      <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_CRC_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC16UpdateRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_UPD_CRC</span>;
+   `<span id=t_idt>PKT_ST_DATA_PID_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_DATA_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_DATA_PID_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_DATA_PID_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+      <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_HS_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_HS_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_HS_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_WAIT_WIRE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE2</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE3</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE3</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_SPCL_WAIT_WIRE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_SPCL_SEND_IDLE1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_PKT_SENT1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_UPD_CRC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>SIEPortData</span>;
+     <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_CRC_RDY</span>;
+      <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortDataIn</span>;
+      <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrlIn</span>;
+      <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_PKT_SENT1</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_CRC_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC5UpdateRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_UPD_CRC</span>;
+   `<span id=t_idt>PKT_ST_TKN_CRC_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_CRC_UPD_CRC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>SIEPortData</span>;
+     <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>SIEPortWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_CRC_RDY</span>;
+      <span id=t_idt>next_SIEPortData</span> &lt;= <span id=t_idt>SIEPortDataIn</span>;
+      <span id=t_idt>next_SIEPortCtrl</span> &lt;= <span id=t_idt>SIEPortCtrlIn</span>;
+      <span id=t_idt>next_SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= {~<span id=t_idt>CRC5Result</span>, <span id=t_idt>SIEPortData</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>] };
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_CRC_WAIT_CRC_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC5UpdateRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_CRC_UPD_CRC</span>;
+   `<span id=t_idt>PKT_ST_TKN_PID_PKT_SENT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_BYTE1_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_ST_TKN_PID_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processTxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>PKT_ST_TKN_PID_PKT_SENT</span>;
+      <span id=t_idt>next_processTxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_TxByteOut</span> &lt;= <span id=t_idt>SIEPortData</span>;
+      <span id=t_idt>next_TxByteOutCtrl</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+      <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_CHK_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>i</span> == `<span id=t_idt>RESUME_LEN</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S3</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= `<span id=t_idt>SE0</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S3</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S4</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= `<span id=t_idt>SE0</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S4</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S5</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S5</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_S6</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_S6</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>STX_WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_ST_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_WAIT_RDY</span>;
+   `<span id=t_idt>RES_ST_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SIETx</span> &lt;= `<span id=t_idt>RES_ST_CHK_FIN</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>KBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SIETx_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_SIETx</span> &lt;= `<span id=t_idt>START_SIETX</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_SIETx</span> &lt;= <span id=t_idt>NextState_SIETx</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SIETx_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SIEPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>SIEPortCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>i</span> &lt;= <span id=t_cns>5'h0</span>;
+   <span id=t_idt>processTxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>TxByteOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>TxByteOutCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+   <span id=t_idt>USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRCData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SIEPortTxRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SIEPortData</span> &lt;= <span id=t_idt>next_SIEPortData</span>;
+   <span id=t_idt>SIEPortCtrl</span> &lt;= <span id=t_idt>next_SIEPortCtrl</span>;
+   <span id=t_idt>i</span> &lt;= <span id=t_idt>next_i</span>;
+   <span id=t_idt>processTxByteWEn</span> &lt;= <span id=t_idt>next_processTxByteWEn</span>;
+   <span id=t_idt>TxByteOut</span> &lt;= <span id=t_idt>next_TxByteOut</span>;
+   <span id=t_idt>TxByteOutCtrl</span> &lt;= <span id=t_idt>next_TxByteOutCtrl</span>;
+   <span id=t_idt>USBWireData</span> &lt;= <span id=t_idt>next_USBWireData</span>;
+   <span id=t_idt>USBWireCtrl</span> &lt;= <span id=t_idt>next_USBWireCtrl</span>;
+   <span id=t_idt>USBWireReq</span> &lt;= <span id=t_idt>next_USBWireReq</span>;
+   <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_idt>next_USBWireWEn</span>;
+   <span id=t_idt>rstCRC</span> &lt;= <span id=t_idt>next_rstCRC</span>;
+   <span id=t_idt>CRCData</span> &lt;= <span id=t_idt>next_CRCData</span>;
+   <span id=t_idt>CRC5En</span> &lt;= <span id=t_idt>next_CRC5En</span>;
+   <span id=t_idt>CRC5_8Bit</span> &lt;= <span id=t_idt>next_CRC5_8Bit</span>;
+   <span id=t_idt>CRC16En</span> &lt;= <span id=t_idt>next_CRC16En</span>;
+   <span id=t_idt>SIEPortTxRdy</span> &lt;= <span id=t_idt>next_SIEPortTxRdy</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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+++ common/components/usbhostslave/tags/start/doc/html/src/hostController/usbHostControl.v/index.htm	(revision 264)
@@ -0,0 +1,416 @@
+<html>
+<head>
+<title>usbHostControl.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbHostControl.v                                             ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:10 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+<span id=t_kwd>module</span> <span id=t_idt>usbHostControl</span>(
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_com>//sendPacket</span>
+  <span id=t_idt>TxFifoRE</span>, <span id=t_idt>TxFifoData</span>, <span id=t_idt>TxFifoEmpty</span>,
+  <span id=t_com>//getPacket</span>
+  <span id=t_idt>RxFifoWE</span>, <span id=t_idt>RxFifoData</span>, <span id=t_idt>RxFifoFull</span>,
+  <span id=t_idt>RxByteStatus</span>, <span id=t_idt>RxData</span>, <span id=t_idt>RxDataValid</span>,
+  <span id=t_idt>SIERxTimeOut</span>,
+  <span id=t_com>//speedCtrlMux</span>
+  <span id=t_idt>fullSpeedRate</span>, <span id=t_idt>fullSpeedPol</span>,
+  <span id=t_com>//HCTxPortArbiter</span>
+  <span id=t_idt>HCTxPortEn</span>, <span id=t_idt>HCTxPortRdy</span>,
+  <span id=t_idt>HCTxPortData</span>, <span id=t_idt>HCTxPortCtrl</span>,
+  <span id=t_com>//rxStatusMonitor</span>
+  <span id=t_idt>connectStateIn</span>, 
+  <span id=t_idt>resumeDetectedIn</span>,
+  <span id=t_com>//USBHostControlBI </span>
+  <span id=t_idt>busAddress</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>, 
+  <span id=t_idt>busWriteEn</span>,
+  <span id=t_idt>busStrobe_i</span>,
+  <span id=t_idt>SOFSentIntOut</span>, 
+  <span id=t_idt>connEventIntOut</span>, 
+  <span id=t_idt>resumeIntOut</span>, 
+  <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>hostControlSelect</span>
+   );
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>, <span id=t_idt>rst</span>;
+<span id=t_com>//sendPacket</span>
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoRE</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_com>//getPacket</span>
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoWE</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxFifoData</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteStatus</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxData</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxDataValid</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_com>//speedCtrlMux</span>
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>;
+<span id=t_com>//HCTxPortArbiter</span>
+<span id=t_kwd>output</span> <span id=t_idt>HCTxPortEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCtrl</span>;
+<span id=t_com>//rxStatusMonitor</span>
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_com>//USBHostControlBI </span>
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busWriteEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFSentIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>connEventIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>hostControlSelect</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoRE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoWE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxFifoData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteStatus</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxDataValid</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPol</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HCTxPortEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HCTxPortRdy</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortData</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>HCTxPortCtrl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busWriteEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSentIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>connEventIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSelect</span>;
+
+<span id=t_com>//internal wiring</span>
+<span id=t_kwd>wire</span> <span id=t_idt>SOFTimerClr</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>getPacketREn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HCTxGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HCTxReq</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>HC_PID</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>HC_SP_WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFTxGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFTxReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOF_SP_WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFEnable</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFSyncEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPReadyIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPReadyOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCPPIDIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCPPIDOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPWEnIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPWEnOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPFSRate</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPFSPol</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketCPGrabLine</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFCntlData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFCntlGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFCntlReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFCntlWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketWEn</span>;   
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>SOFTimer</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrTxReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDone</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transReq</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>preAmbleEnable</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directLineState</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directLineCtrlEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>TxAddr</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndP</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPktStatus</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCtrlRate</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCtrlPol</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntFromRxStatusMon</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>connectionEventFromRxStatusMon</span>;
+
+<span id=t_idt>USBHostControlBI</span> <span id=t_idt>u_USBHostControlBI</span> 
+  (.<span id=t_idt>address</span>(<span id=t_idt>busAddress</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>busDataOut</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>busWriteEn</span>),
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>busStrobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>SOFSentIntOut</span>(<span id=t_idt>SOFSentIntOut</span>), 
+  .<span id=t_idt>connEventIntOut</span>(<span id=t_idt>connEventIntOut</span>), 
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>resumeIntOut</span>), 
+  .<span id=t_idt>transDoneIntOut</span>(<span id=t_idt>transDoneIntOut</span>),
+  .<span id=t_idt>TxTransTypeReg</span>(<span id=t_idt>transType</span>), 
+  .<span id=t_idt>TxSOFEnableReg</span>(<span id=t_idt>SOFEnable</span>),
+  .<span id=t_idt>TxAddrReg</span>(<span id=t_idt>TxAddr</span>), 
+  .<span id=t_idt>TxEndPReg</span>(<span id=t_idt>TxEndP</span>), 
+  .<span id=t_idt>frameNumIn</span>(<span id=t_idt>frameNum</span>), 
+  .<span id=t_idt>RxPktStatusIn</span>(<span id=t_idt>RxPktStatus</span>), 
+  .<span id=t_idt>RxPIDIn</span>(<span id=t_idt>RxPID</span>),
+  .<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectStateOut</span>),
+  .<span id=t_idt>SOFSentIn</span>(<span id=t_idt>SOFSent</span>), 
+  .<span id=t_idt>connEventIn</span>(<span id=t_idt>connectionEventFromRxStatusMon</span>), 
+  .<span id=t_idt>resumeIntIn</span>(<span id=t_idt>resumeIntFromRxStatusMon</span>), 
+  .<span id=t_idt>transDoneIn</span>(<span id=t_idt>transDone</span>),
+  .<span id=t_idt>hostControlSelect</span>(<span id=t_idt>hostControlSelect</span>),
+  .<span id=t_idt>clrTransReq</span>(<span id=t_idt>clrTxReq</span>),
+  .<span id=t_idt>preambleEn</span>(<span id=t_idt>preAmbleEnable</span>),
+  .<span id=t_idt>SOFSync</span>(<span id=t_idt>SOFSyncEn</span>),
+  .<span id=t_idt>TxLineState</span>(<span id=t_idt>directLineState</span>),
+  .<span id=t_idt>LineDirectControlEn</span>(<span id=t_idt>directLineCtrlEn</span>),
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>directCtrlPol</span>), 
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>directCtrlRate</span>),
+  .<span id=t_idt>transReq</span>(<span id=t_idt>transReq</span>)
+  
+  );
+
+
+<span id=t_idt>hostcontroller</span> <span id=t_idt>u_hostController</span>
+  (.<span id=t_idt>RXStatus</span>(<span id=t_idt>RxPktStatus</span>), 
+  .<span id=t_idt>clearTXReq</span>(<span id=t_idt>clrTxReq</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>getPacketREn</span>(<span id=t_idt>getPacketREn</span>),
+  .<span id=t_idt>getPacketRdy</span>(<span id=t_idt>getPacketRdy</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketArbiterGnt</span>(<span id=t_idt>HCTxGnt</span>),
+  .<span id=t_idt>sendPacketArbiterReq</span>(<span id=t_idt>HCTxReq</span>),
+  .<span id=t_idt>sendPacketPID</span>(<span id=t_idt>HC_PID</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>sendPacketCPReadyOut</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>HC_SP_WEn</span>),
+  .<span id=t_idt>transDone</span>(<span id=t_idt>transDone</span>),
+  .<span id=t_idt>transReq</span>(<span id=t_idt>transReq</span>),
+  .<span id=t_idt>transType</span>(<span id=t_idt>transType</span>) );
+
+<span id=t_idt>SOFController</span> <span id=t_idt>u_SOFController</span>
+  (.<span id=t_idt>HCTxPortCntl</span>(<span id=t_idt>SOFCntlCntl</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>SOFCntlData</span>),
+  .<span id=t_idt>HCTxPortGnt</span>(<span id=t_idt>SOFCntlGnt</span>),
+  .<span id=t_idt>HCTxPortRdy</span>(<span id=t_idt>HCTxPortRdy</span>),
+  .<span id=t_idt>HCTxPortReq</span>(<span id=t_idt>SOFCntlReq</span>),
+  .<span id=t_idt>HCTxPortWEn</span>(<span id=t_idt>SOFCntlWEn</span>),
+  .<span id=t_idt>SOFEnable</span>(<span id=t_idt>SOFEnable</span>),
+  .<span id=t_idt>SOFTimerClr</span>(<span id=t_idt>SOFTimerClr</span>),
+  .<span id=t_idt>SOFTimer</span>(<span id=t_idt>SOFTimer</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>SOFTransmit</span> <span id=t_idt>u_SOFTransmit</span>
+  (.<span id=t_idt>SOFEnable</span>(<span id=t_idt>SOFEnable</span>),
+  .<span id=t_idt>SOFSent</span>(<span id=t_idt>SOFSent</span>),
+  .<span id=t_idt>SOFSyncEn</span>(<span id=t_idt>SOFSyncEn</span>),
+  .<span id=t_idt>SOFTimerClr</span>(<span id=t_idt>SOFTimerClr</span>),
+  .<span id=t_idt>SOFTimer</span>(<span id=t_idt>SOFTimer</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketArbiterGnt</span>(<span id=t_idt>SOFTxGnt</span>),
+  .<span id=t_idt>sendPacketArbiterReq</span>(<span id=t_idt>SOFTxReq</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>sendPacketCPReadyOut</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>SOF_SP_WEn</span>) );  
+
+
+<span id=t_idt>sendPacketArbiter</span> <span id=t_idt>u_sendPacketArbiter</span>
+  (.<span id=t_idt>HCTxGnt</span>(<span id=t_idt>HCTxGnt</span>),
+  .<span id=t_idt>HCTxReq</span>(<span id=t_idt>HCTxReq</span>),
+  .<span id=t_idt>HC_PID</span>(<span id=t_idt>HC_PID</span>),
+  .<span id=t_idt>HC_SP_WEn</span>(<span id=t_idt>HC_SP_WEn</span>),
+  .<span id=t_idt>SOFTxGnt</span>(<span id=t_idt>SOFTxGnt</span>),
+  .<span id=t_idt>SOFTxReq</span>(<span id=t_idt>SOFTxReq</span>),
+  .<span id=t_idt>SOF_SP_WEn</span>(<span id=t_idt>SOF_SP_WEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketPID</span>(<span id=t_idt>sendPacketCPPIDIn</span>),
+  .<span id=t_idt>sendPacketWEnable</span>(<span id=t_idt>sendPacketCPWEnIn</span>) );   
+
+<span id=t_idt>sendPacketCheckPreamble</span> <span id=t_idt>u_sendPacketCheckPreamble</span>
+  (.<span id=t_idt>sendPacketCPPID</span>(<span id=t_idt>sendPacketCPPIDIn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>fullSpeedBitRate</span>(<span id=t_idt>sendPacketCPFSRate</span>),
+  .<span id=t_idt>fullSpeedPolarity</span>(<span id=t_idt>sendPacketCPFSPol</span>),
+  .<span id=t_idt>grabLineControl</span>(<span id=t_idt>sendPacketCPGrabLine</span>),
+  .<span id=t_idt>preAmbleEnable</span>(<span id=t_idt>preAmbleEnable</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketCPReady</span>(<span id=t_idt>sendPacketCPReadyOut</span>),
+  .<span id=t_idt>sendPacketCPWEn</span>(<span id=t_idt>sendPacketCPWEnIn</span>),
+  .<span id=t_idt>sendPacketPID</span>(<span id=t_idt>sendPacketCPPIDOut</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>sendPacketCPReadyIn</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>sendPacketCPWEnOut</span>) );
+
+<span id=t_idt>sendPacket</span> <span id=t_idt>u_sendPacket</span>
+  (.<span id=t_idt>HCTxPortCntl</span>(<span id=t_idt>sendPacketCntl</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>sendPacketData</span>),
+  .<span id=t_idt>HCTxPortGnt</span>(<span id=t_idt>sendPacketGnt</span>),
+  .<span id=t_idt>HCTxPortRdy</span>(<span id=t_idt>HCTxPortRdy</span>),
+  .<span id=t_idt>HCTxPortReq</span>(<span id=t_idt>sendPacketReq</span>),
+  .<span id=t_idt>HCTxPortWEn</span>(<span id=t_idt>sendPacketWEn</span>),
+  .<span id=t_idt>PID</span>(<span id=t_idt>sendPacketCPPIDOut</span>),
+  .<span id=t_idt>TxAddr</span>(<span id=t_idt>TxAddr</span>),
+  .<span id=t_idt>TxEndP</span>(<span id=t_idt>TxEndP</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>fifoData</span>(<span id=t_idt>TxFifoData</span>),
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEmpty</span>),
+  .<span id=t_idt>fifoReadEn</span>(<span id=t_idt>TxFifoRE</span>),
+  .<span id=t_idt>frameNum</span>(<span id=t_idt>frameNum</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>sendPacketCPReadyIn</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>sendPacketCPWEnOut</span>) );
+  
+<span id=t_idt>directControl</span> <span id=t_idt>u_directControl</span>
+  (.<span id=t_idt>HCTxPortCntl</span>(<span id=t_idt>directCntlCntl</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>directCntlData</span>),
+  .<span id=t_idt>HCTxPortGnt</span>(<span id=t_idt>directCntlGnt</span>),
+  .<span id=t_idt>HCTxPortRdy</span>(<span id=t_idt>HCTxPortRdy</span>),
+  .<span id=t_idt>HCTxPortReq</span>(<span id=t_idt>directCntlReq</span>),
+  .<span id=t_idt>HCTxPortWEn</span>(<span id=t_idt>directCntlWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>directControlEn</span>(<span id=t_idt>directLineCtrlEn</span>),
+  .<span id=t_idt>directControlLineState</span>(<span id=t_idt>directLineState</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>HCTxPortArbiter</span> <span id=t_idt>u_HCTxPortArbiter</span>
+  (.<span id=t_idt>HCTxPortCntl</span>(<span id=t_idt>HCTxPortCtrl</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>HCTxPortData</span>),
+  .<span id=t_idt>HCTxPortWEnable</span>(<span id=t_idt>HCTxPortEn</span>),
+  .<span id=t_idt>SOFCntlCntl</span>(<span id=t_idt>SOFCntlCntl</span>),
+  .<span id=t_idt>SOFCntlData</span>(<span id=t_idt>SOFCntlData</span>),
+  .<span id=t_idt>SOFCntlGnt</span>(<span id=t_idt>SOFCntlGnt</span>),
+  .<span id=t_idt>SOFCntlReq</span>(<span id=t_idt>SOFCntlReq</span>),
+  .<span id=t_idt>SOFCntlWEn</span>(<span id=t_idt>SOFCntlWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>directCntlCntl</span>(<span id=t_idt>directCntlCntl</span>),
+  .<span id=t_idt>directCntlData</span>(<span id=t_idt>directCntlData</span>),
+  .<span id=t_idt>directCntlGnt</span>(<span id=t_idt>directCntlGnt</span>),
+  .<span id=t_idt>directCntlReq</span>(<span id=t_idt>directCntlReq</span>),
+  .<span id=t_idt>directCntlWEn</span>(<span id=t_idt>directCntlWEn</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketCntl</span>(<span id=t_idt>sendPacketCntl</span>),
+  .<span id=t_idt>sendPacketData</span>(<span id=t_idt>sendPacketData</span>),
+  .<span id=t_idt>sendPacketGnt</span>(<span id=t_idt>sendPacketGnt</span>),
+  .<span id=t_idt>sendPacketReq</span>(<span id=t_idt>sendPacketReq</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>sendPacketWEn</span>) );   
+
+<span id=t_idt>getPacket</span> <span id=t_idt>u_getPacket</span>
+  (.<span id=t_idt>RXDataIn</span>(<span id=t_idt>RxData</span>),
+  .<span id=t_idt>RXDataValid</span>(<span id=t_idt>RxDataValid</span>),
+  .<span id=t_idt>RXFifoData</span>(<span id=t_idt>RxFifoData</span>),
+  .<span id=t_idt>RXFifoFull</span>(<span id=t_idt>RxFifoFull</span>),
+  .<span id=t_idt>RXFifoWEn</span>(<span id=t_idt>RxFifoWE</span>),
+  .<span id=t_idt>RXPacketRdy</span>(<span id=t_idt>getPacketRdy</span>),
+  .<span id=t_idt>RXPktStatus</span>(<span id=t_idt>RxPktStatus</span>),
+  .<span id=t_idt>RXStreamStatusIn</span>(<span id=t_idt>RxByteStatus</span>),
+  .<span id=t_idt>RxPID</span>(<span id=t_idt>RxPID</span>),
+  .<span id=t_idt>SIERxTimeOut</span>(<span id=t_idt>SIERxTimeOut</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>getPacketEn</span>(<span id=t_idt>getPacketREn</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>speedCtrlMux</span> <span id=t_idt>u_speedCtrlMux</span>
+  (.<span id=t_idt>directCtrlRate</span>(<span id=t_idt>directCtrlRate</span>),
+  .<span id=t_idt>directCtrlPol</span>(<span id=t_idt>directCtrlPol</span>),
+  .<span id=t_idt>sendPacketRate</span>(<span id=t_idt>sendPacketCPFSRate</span>),
+  .<span id=t_idt>sendPacketPol</span>(<span id=t_idt>sendPacketCPFSPol</span>),
+  .<span id=t_idt>sendPacketSel</span>(<span id=t_idt>sendPacketCPGrabLine</span>),
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedRate</span>),
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>fullSpeedPol</span>) );
+
+<span id=t_idt>rxStatusMonitor</span> <span id=t_idt>u_rxStatusMonitor</span>
+  (.<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectStateIn</span>),
+  .<span id=t_idt>connectStateOut</span>(<span id=t_idt>connectStateOut</span>),
+  .<span id=t_idt>resumeDetectedIn</span>(<span id=t_idt>resumeDetectedIn</span>),
+  .<span id=t_idt>connectionEventOut</span>(<span id=t_idt>connectionEventFromRxStatusMon</span>),
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>resumeIntFromRxStatusMon</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>)  );
+
+<span id=t_kwd>endmodule</span>
+
+  
+  
+
+
+
+
+
+</pre>
+</body>
+</html>

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+*
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Index: common/components/usbhostslave/tags/start/doc/html/src/include/usbHostControl_h.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/include/usbHostControl_h.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/include/usbHostControl_h.v/index.htm	(revision 264)
@@ -0,0 +1,124 @@
+<html>
+<head>
+<title>usbHostControl_h.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbHostControl_h.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:13 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_com>//HCRegIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_CONTROL_REG</span> <span id=t_cns>4'h0</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_TRANS_TYPE_REG</span> <span id=t_cns>4'h1</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_LINE_CONTROL_REG</span> <span id=t_cns>4'h2</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_SOF_ENABLE_REG</span> <span id=t_cns>4'h3</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_ADDR_REG</span> <span id=t_cns>4'h4</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_ENDP_REG</span> <span id=t_cns>4'h5</span>
+<span id=t_dir>`define</span> <span id=t_idt>FRAME_NUM_MSB_REG</span> <span id=t_cns>4'h6</span>
+<span id=t_dir>`define</span> <span id=t_idt>FRAME_NUM_LSB_REG</span> <span id=t_cns>4'h7</span>
+<span id=t_dir>`define</span> <span id=t_idt>INTERRUPT_STATUS_REG</span> <span id=t_cns>4'h8</span>
+<span id=t_dir>`define</span> <span id=t_idt>INTERRUPT_MASK_REG</span> <span id=t_cns>4'h9</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_STATUS_REG</span> <span id=t_cns>4'ha</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_PID_REG</span> <span id=t_cns>4'hb</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_ADDR_REG</span> <span id=t_cns>4'hc</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_ENDP_REG</span> <span id=t_cns>4'hd</span>
+<span id=t_dir>`define</span> <span id=t_idt>RX_CONNECT_STATE_REG</span> <span id=t_cns>4'he</span>
+<span id=t_dir>`define</span> <span id=t_idt>HCREG_BUFFER_LEN</span> <span id=t_cns>4'hf</span>
+<span id=t_dir>`define</span> <span id=t_idt>HCREG_MASK</span> <span id=t_cns>4'hf</span>
+
+<span id=t_com>//TXControlRegIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>TRANS_REQ_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_SYNC_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>PREAMBLE_ENABLE_BIT</span> <span id=t_cns>2</span>
+
+<span id=t_com>//interruptRegIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>TRANS_DONE_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>RESUME_INT_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>CONNECTION_EVENT_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_SENT_BIT</span> <span id=t_cns>3</span>
+
+<span id=t_com>//TXTransactionTypes</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_TRANS</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_TRANS</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUTDATA0_TRANS</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>OUTDATA1_TRANS</span> <span id=t_cns>3</span>
+ 
+ <span id=t_com>//TXLineControlIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_LINE_STATE_LSBIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>TX_LINE_STATE_MSBIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>DIRECT_CONTROL_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>FULL_SPEED_LINE_POLARITY_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>FULL_SPEED_LINE_RATE_BIT</span> <span id=t_cns>4</span>
+
+<span id=t_com>//TXSOFEnableIndices</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_EN_BIT</span> <span id=t_cns>0</span>
+
+<span id=t_com>//SOFTimeConstants </span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_TX_TIME</span> <span id=t_cns>80</span>     <span id=t_com>//Fix this. Need correct SOF TX interval</span>
+<span id=t_dir>`define</span> <span id=t_idt>SOF_TX_MARGIN</span> <span id=t_cns>2</span>
+       
+<span id=t_com>//Host RXStatusRegIndices </span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_CRC_ERROR_BIT</span> <span id=t_cns>0</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_BIT_STUFF_ERROR_BIT</span> <span id=t_cns>1</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_RX_OVERFLOW_BIT</span> <span id=t_cns>2</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_RX_TIME_OUT_BIT</span> <span id=t_cns>3</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_NAK_RXED_BIT</span> <span id=t_cns>4</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_STALL_RXED_BIT</span> <span id=t_cns>5</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_ACK_RXED_BIT</span> <span id=t_cns>6</span>
+<span id=t_dir>`define</span> <span id=t_idt>HC_DATA_SEQUENCE_BIT</span> <span id=t_cns>7</span>
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/include/usbHostControl_h.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar617.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram617.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index617.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar720.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram720.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index720.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 216 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar216.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar216.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram216.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index216.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar474.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram474.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index474.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar626.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram626.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index626.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(857,1179,959,1281,Click16,Over16);
+FUB[1] = new Array(864,1384,966,1486,Click359,Over359);
+FUB[2] = new Array(841,912,944,1014,Click216,Over216);
+FUB[3] = new Array(845,1042,948,1144,Click213,Over213);
+
+//----------------------------------------------------------------------------
+function Click16(){fubclick('./index16.htm');}
+function Over16(){window.status='Hierarchical State RES_ST';};
+function Click359(){fubclick('./index359.htm');}
+function Over359(){window.status='Hierarchical State PKT_ST';};
+function Click216(){fubclick('./index216.htm');}
+function Over216(){window.status='Hierarchical State IDLE';};
+function Click213(){fubclick('./index213.htm');}
+function Over213(){window.status='Hierarchical State DIR_CTL';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(990,1164,1092,1266,Click455,Over455);
+FUB[1] = new Array(1010,1864,1112,1966,Click465,Over465);
+FUB[2] = new Array(1005,1606,1107,1708,Click474,Over474);
+FUB[3] = new Array(1007,1335,1110,1437,Click483,Over483);
+
+//----------------------------------------------------------------------------
+function Click455(){fubclick('./index455.htm');}
+function Over455(){window.status='Hierarchical State SPCL';};
+function Click465(){fubclick('./index465.htm');}
+function Over465(){window.status='Hierarchical State DATA';};
+function Click474(){fubclick('./index474.htm');}
+function Over474(){window.status='Hierarchical State HS';};
+function Click483(){fubclick('./index483.htm');}
+function Over483(){window.status='Hierarchical State TKN';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 359 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_PKT_ST.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar359.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_DIR_CTL.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_DIR_CTL.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html	(revision 264)
@@ -0,0 +1,54 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 3;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(847,986,949,1089,Click617,Over617);
+FUB[1] = new Array(829,587,931,690,Click609,Over609);
+FUB[2] = new Array(836,1451,938,1553,Click626,Over626);
+
+//----------------------------------------------------------------------------
+function Click617(){fubclick('./index617.htm');}
+function Over617(){window.status='Hierarchical State BYTE1';};
+function Click609(){fubclick('./index609.htm');}
+function Over609(){window.status='Hierarchical State PID';};
+function Click626(){fubclick('./index626.htm');}
+function Over626(){window.status='Hierarchical State CRC';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 483 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_TKN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar483.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_DATA.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_PKT_ST.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_PKT_ST.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter" alt="SIETransmitter"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram359.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram359.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram359.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter PKT_ST" alt="SIETransmitter PKT_ST"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram359.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram483.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram483.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram483.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter TKN" alt="SIETransmitter TKN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram483.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter DATA" alt="SIETransmitter DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram717.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar16.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram16.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index16.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar455.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram455.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index455.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar609.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram609.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index609.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar718.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram718.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index718.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 213 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_DIR_CTL.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar213.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html	(revision 264)
@@ -0,0 +1,54 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 3;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(848,524,951,626,Click718,Over718);
+FUB[1] = new Array(866,923,969,1025,Click717,Over717);
+FUB[2] = new Array(856,1388,958,1490,Click720,Over720);
+
+//----------------------------------------------------------------------------
+function Click718(){fubclick('./index718.htm');}
+function Over718(){window.status='Hierarchical State PID';};
+function Click717(){fubclick('./index717.htm');}
+function Over717(){window.status='Hierarchical State DATA';};
+function Click720(){fubclick('./index720.htm');}
+function Over720(){window.status='Hierarchical State CRC';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 465 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar465.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 617 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_BYTE1.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar617.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 720 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_CRC.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar720.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit ERROR" alt="processRxBit ERROR"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram115.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit RES_END" alt="processRxBit RES_END"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram42.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar115.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram115.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index115.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_PID.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_PID.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_TKN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/SIETransmitter_TKN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter IDLE" alt="SIETransmitter IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram216.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter HS" alt="SIETransmitter HS"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram474.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="SIETransmitter CRC" alt="SIETransmitter CRC"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/diagram626.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index359.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index359.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index359.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar359.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram359.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index359.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar483.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram483.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index483.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar717.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram717.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/index717.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 16 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_RES_ST.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 455 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_SPCL.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar455.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 609 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar609.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 718 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar718.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit BYTE" alt="processRxBit BYTE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram113.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit RES_RX" alt="processRxBit RES_RX"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar113.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram113.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index113.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 717 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar717.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit" alt="processRxBit"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit DATA_RX" alt="processRxBit DATA_RX"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram24.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 474 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_HS.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar474.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 626 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./SIETransmitter_CRC.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./SIETransmitter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/SIETransmitter.asf/toolbar626.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm	(revision 264)
@@ -0,0 +1,94 @@
+<html>
+<head>
+<title>lineControlUpdate.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// lineControlUpdate.v                                          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:14 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>lineControlUpdate</span>(<span id=t_idt>fullSpeedPolarity</span>, <span id=t_idt>fullSpeedBitRate</span>, <span id=t_idt>JBit</span>, <span id=t_idt>KBit</span>);
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedBitRate</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRate</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+
+
+
+<span id=t_kwd>always</span> @(<span id=t_idt>fullSpeedPolarity</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>fullSpeedPolarity</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+      <span id=t_idt>JBit</span> = `<span id=t_idt>ONE_ZERO</span>;
+      <span id=t_idt>KBit</span> = `<span id=t_idt>ZERO_ONE</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+      <span id=t_idt>JBit</span> = `<span id=t_idt>ZERO_ONE</span>;
+      <span id=t_idt>KBit</span> = `<span id=t_idt>ONE_ZERO</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/lineControlUpdate.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit IDLE" alt="processRxBit IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxBit DATA" alt="processRxBit DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/diagram97.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar42.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram42.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index42.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_BYTE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_BYTE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_IDLE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_IDLE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar33.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram33.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index33.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm	(revision 264)
@@ -0,0 +1,415 @@
+<html>
+<head>
+<title>processRxBit.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// processRxBit</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:23 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>processRxBit</span> (<span id=t_idt>JBit</span>, <span id=t_idt>KBit</span>, <span id=t_idt>RxBitsIn</span>, <span id=t_idt>RxCtrlOut</span>, <span id=t_idt>RxDataOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>processRxBitRdy</span>, <span id=t_idt>processRxBitsWEn</span>, <span id=t_idt>processRxByteRdy</span>, <span id=t_idt>processRxByteWEn</span>, <span id=t_idt>resumeDetected</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processRxBitsWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processRxByteRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processRxBitRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processRxByteWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>resumeDetected</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsIn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>, <span id=t_idt>next_RxCtrlOut</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>, <span id=t_idt>next_RxDataOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processRxBitRdy</span>, <span id=t_idt>next_processRxBitRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processRxBitsWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processRxByteRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processRxByteWEn</span>, <span id=t_idt>next_processRxByteWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>resumeDetected</span>, <span id=t_idt>next_resumeDetected</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>RXBitCount</span>, <span id=t_idt>next_RXBitCount</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>RXBitStMachCurrState</span>, <span id=t_idt>next_RXBitStMachCurrState</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByte</span>, <span id=t_idt>next_RXByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>RXSameBitCount</span>, <span id=t_idt>next_RXSameBitCount</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>RxBits</span>, <span id=t_idt>next_RxBits</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>bitStuffError</span>, <span id=t_idt>next_bitStuffError</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>oldRXBits</span>, <span id=t_idt>next_oldRXBits</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>resumeWaitCnt</span>, <span id=t_idt>next_resumeWaitCnt</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: prRxBit</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_FIRST_BIT</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BITS</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_CHK_KBIT</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_LAST_BIT</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_CHK_SE0</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_DATA_DESTUFF</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_BYTE_SEND2</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_BYTE_WAIT_RDY</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_RX_CHK</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_ERROR_CHK_RES</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>RES_END_CHK1</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_PRB_RDY</span> <span id=t_cns>4'b1100</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_WAIT_PRB_RDY</span> <span id=t_cns>4'b1101</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_RX_ERROR_WAIT_RDY</span> <span id=t_cns>4'b1110</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_prRxBit</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_prRxBit</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: prRxBit</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RxBitsIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxBits</span> <span id=t_kwd>or</span> <span id=t_idt>oldRXBits</span> <span id=t_kwd>or</span> <span id=t_idt>RXSameBitCount</span> <span id=t_kwd>or</span> <span id=t_idt>RXBitCount</span> <span id=t_kwd>or</span> <span id=t_idt>RXByte</span> <span id=t_kwd>or</span> <span id=t_idt>JBit</span> <span id=t_kwd>or</span> <span id=t_idt>KBit</span> <span id=t_kwd>or</span> <span id=t_idt>resumeWaitCnt</span> <span id=t_kwd>or</span> <span id=t_idt>processRxBitsWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXBitStMachCurrState</span> <span id=t_kwd>or</span> <span id=t_idt>processRxByteRdy</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>processRxByteWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RxCtrlOut</span> <span id=t_kwd>or</span> <span id=t_idt>RxDataOut</span> <span id=t_kwd>or</span> <span id=t_idt>resumeDetected</span> <span id=t_kwd>or</span> <span id=t_idt>processRxBitRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_prRxBit</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxBit_NextState</span>
+  <span id=t_idt>NextState_prRxBit</span> &lt;= <span id=t_idt>CurrState_prRxBit</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_idt>processRxByteWEn</span>;
+  <span id=t_idt>next_RxCtrlOut</span> &lt;= <span id=t_idt>RxCtrlOut</span>;
+  <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxDataOut</span>;
+  <span id=t_idt>next_resumeDetected</span> &lt;= <span id=t_idt>resumeDetected</span>;
+  <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= <span id=t_idt>RXBitStMachCurrState</span>;
+  <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBits</span>;
+  <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_idt>RXSameBitCount</span>;
+  <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_idt>RXBitCount</span>;
+  <span id=t_idt>next_oldRXBits</span> &lt;= <span id=t_idt>oldRXBits</span>;
+  <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXByte</span>;
+  <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>bitStuffError</span>;
+  <span id=t_idt>next_resumeWaitCnt</span> &lt;= <span id=t_idt>resumeWaitCnt</span>;
+  <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_idt>processRxBitRdy</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_prRxBit</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxCtrlOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_resumeDetected</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+     <span id=t_idt>next_RxBits</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>next_oldRXBits</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_resumeWaitCnt</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_BITS</span>:
+     <span id=t_kwd>if</span> ((<span id=t_idt>processRxBitsWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXBitStMachCurrState</span> == `<span id=t_idt>WAIT_RESUME_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>RES_RX_CHK</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>processRxBitsWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXBitStMachCurrState</span> == `<span id=t_idt>DATA_RECEIVE_BIT_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_CHK_SE0</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>processRxBitsWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXBitStMachCurrState</span> == `<span id=t_idt>IDLE_BIT_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>IDLE_CHK_KBIT</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>processRxBitsWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXBitStMachCurrState</span> == `<span id=t_idt>RESUME_END_WAIT_ST</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>RES_END_CHK1</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_FIRST_BIT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>DATA_RECEIVE_BIT_ST</span>;
+     <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_cns>4'h1</span>;
+     <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_cns>4'h1</span>;
+     <span id=t_idt>next_oldRXBits</span> &lt;= <span id=t_idt>RxBits</span>;
+     <span id=t_com>//zero is always the first RZ data bit of a new packet</span>
+     <span id=t_idt>next_RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_CHK_KBIT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == <span id=t_idt>KBit</span>)  
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>IDLE_WAIT_PRB_RDY</span>;
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_WAIT_PRB_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>IDLE_FIRST_BIT</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_com>//redundant data</span>
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>DATA_START</span>;
+      <span id=t_com>//start of packet</span>
+      <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_LAST_BIT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_CHK_SE0</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)  
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_WAIT_PRB_RDY</span>;
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_DATA_DESTUFF</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == <span id=t_idt>oldRXBits</span>)                 <span id=t_com>//if the current 'RxBits' are the same as the old 'RxBits', then</span>
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_idt>RXSameBitCount</span> + <span id=t_cns>1'b1</span>;
+          <span id=t_com>//inc 'RXSameBitCount'</span>
+          <span id=t_kwd>if</span> (<span id=t_idt>RXSameBitCount</span> == `<span id=t_idt>MAX_CONSEC_SAME_BITS</span>) <span id=t_com>//if 'RXSameBitCount' == 7 there has been a bit stuff error</span>
+          <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b1</span>;
+              <span id=t_com>//flag 'bitStuffError'</span>
+          <span id=t_kwd>else</span>                                          <span id=t_com>//else no bit stuffing error</span>
+          <span id=t_kwd>begin</span>
+          <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_idt>RXBitCount</span> + <span id=t_cns>1'b1</span>;
+              <span id=t_kwd>if</span> (<span id=t_idt>RXBitCount</span> != <span id=t_cns>4'h7</span>) <span id=t_kwd>begin</span>
+            <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+                  <span id=t_com>//early indication of ready</span>
+         <span id=t_kwd>end</span>
+          <span id=t_idt>next_RXByte</span> &lt;= { <span id=t_cns>1'b1</span>, <span id=t_idt>RXByte</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>]};
+              <span id=t_com>//RZ bit = 1 (ie no change in 'RxBits')</span>
+          <span id=t_kwd>end</span>
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span>                                            <span id=t_com>//else current 'RxBits' are different from old 'RxBits'</span>
+      <span id=t_kwd>begin</span>
+          <span id=t_kwd>if</span> (<span id=t_idt>RXSameBitCount</span> != `<span id=t_idt>MAX_CONSEC_SAME_BITS</span>)  <span id=t_com>//if this is not the RZ 0 bit after 6 consecutive RZ 1s, then</span>
+          <span id=t_kwd>begin</span>
+          <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_idt>RXBitCount</span> + <span id=t_cns>1'b1</span>;
+              <span id=t_kwd>if</span> (<span id=t_idt>RXBitCount</span> != <span id=t_cns>4'h7</span>) <span id=t_kwd>begin</span>
+            <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+                  <span id=t_com>//early indication of ready</span>
+         <span id=t_kwd>end</span>
+          <span id=t_idt>next_RXByte</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>RXByte</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>]};
+              <span id=t_com>//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')</span>
+          <span id=t_kwd>end</span>
+        <span id=t_idt>next_RXSameBitCount</span> &lt;= <span id=t_cns>4'h1</span>;
+          <span id=t_com>//reset 'RXSameBitCount'</span>
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_oldRXBits</span> &lt;= <span id=t_idt>RxBits</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_WAIT_PRB_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_LAST_BIT</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_com>//redundant data</span>
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>DATA_STOP</span>;
+      <span id=t_com>//end of packet</span>
+      <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_DATA_DESTUFF</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXBitCount</span> == <span id=t_cns>4'h8</span> &amp; <span id=t_idt>bitStuffError</span> == <span id=t_cns>1'b0</span>)  
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_BYTE_WAIT_RDY</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>bitStuffError</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_ERROR_WAIT_RDY</span>;
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+      <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_BYTE_SEND2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_BYTE_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_BYTE_SEND2</span>;
+      <span id=t_idt>next_RXBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RXByte</span>;
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>DATA_STREAM</span>;
+      <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_ERROR_CHK_RES</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == <span id=t_idt>JBit</span>)                           <span id=t_com>//if current bit is a JBit, then</span>
+       <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+         <span id=t_com>//next state is idle</span>
+     <span id=t_kwd>else</span>                                          <span id=t_com>//else</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_RESUME_ST</span>;
+         <span id=t_com>//check for resume</span>
+       <span id=t_idt>next_resumeWaitCnt</span> &lt;= <span id=t_cns>0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_RX_ERROR_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxByteRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>DATA_RX_ERROR_CHK_RES</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_com>//redundant data</span>
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>DATA_BIT_STUFF_ERROR</span>;
+      <span id=t_idt>next_processRxByteWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_RX_CHK</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> != <span id=t_idt>KBit</span>)  <span id=t_com>//can only be a resume if line remains in Kbit state</span>
+       <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_resumeWaitCnt</span> &lt;= <span id=t_idt>resumeWaitCnt</span> + <span id=t_cns>1'b1</span>;
+         <span id=t_com>//if we've waited long enough, then</span>
+         <span id=t_kwd>if</span> (<span id=t_idt>resumeWaitCnt</span> == `<span id=t_idt>RESUME_WAIT_TIME_MINUS1</span>)
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>RESUME_END_WAIT_ST</span>;
+         <span id=t_idt>next_resumeDetected</span> &lt;= <span id=t_cns>1'b1</span>;
+             <span id=t_com>//report resume detected</span>
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>RES_END_CHK1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> != <span id=t_idt>KBit</span>)  <span id=t_com>//line must leave KBit state for the end of resume</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+       <span id=t_idt>next_resumeDetected</span> &lt;= <span id=t_cns>1'b0</span>;
+         <span id=t_com>//clear resume detected flag</span>
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_prRxBit</span> &lt;= `<span id=t_idt>WAIT_BITS</span>;
+     <span id=t_idt>next_processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxBit_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_prRxBit</span> &lt;= `<span id=t_idt>START</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_prRxBit</span> &lt;= <span id=t_idt>NextState_prRxBit</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxBit_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXBitStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BIT_ST</span>;
+   <span id=t_idt>RxBits</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>RXSameBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>RXBitCount</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>oldRXBits</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>resumeWaitCnt</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>processRxByteWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RxCtrlOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>resumeDetected</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>processRxBitRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXBitStMachCurrState</span> &lt;= <span id=t_idt>next_RXBitStMachCurrState</span>;
+   <span id=t_idt>RxBits</span> &lt;= <span id=t_idt>next_RxBits</span>;
+   <span id=t_idt>RXSameBitCount</span> &lt;= <span id=t_idt>next_RXSameBitCount</span>;
+   <span id=t_idt>RXBitCount</span> &lt;= <span id=t_idt>next_RXBitCount</span>;
+   <span id=t_idt>oldRXBits</span> &lt;= <span id=t_idt>next_oldRXBits</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_idt>next_RXByte</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_idt>next_bitStuffError</span>;
+   <span id=t_idt>resumeWaitCnt</span> &lt;= <span id=t_idt>next_resumeWaitCnt</span>;
+   <span id=t_idt>processRxByteWEn</span> &lt;= <span id=t_idt>next_processRxByteWEn</span>;
+   <span id=t_idt>RxCtrlOut</span> &lt;= <span id=t_idt>next_RxCtrlOut</span>;
+   <span id=t_idt>RxDataOut</span> &lt;= <span id=t_idt>next_RxDataOut</span>;
+   <span id=t_idt>resumeDetected</span> &lt;= <span id=t_idt>next_resumeDetected</span>;
+   <span id=t_idt>processRxBitRdy</span> &lt;= <span id=t_idt>next_processRxBitRdy</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_ERROR.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_ERROR.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(868,1404,970,1507,Click24,Over24);
+FUB[1] = new Array(862,1179,965,1281,Click16,Over16);
+FUB[2] = new Array(892,1858,994,1961,Click42,Over42);
+FUB[3] = new Array(879,1639,981,1741,Click33,Over33);
+
+//----------------------------------------------------------------------------
+function Click24(){fubclick('./index24.htm');}
+function Over24(){window.status='Hierarchical State DATA_RX';};
+function Click16(){fubclick('./index16.htm');}
+function Over16(){window.status='Hierarchical State IDLE';};
+function Click42(){fubclick('./index42.htm');}
+function Over42(){window.status='Hierarchical State RES_END';};
+function Click33(){fubclick('./index33.htm');}
+function Over33(){window.status='Hierarchical State RES_RX';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar24.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram24.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index24.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA_RX.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA_RX.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_RX.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_RX.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar16.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram16.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index16.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 113 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_BYTE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar113.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 33 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_RES_RX.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte CHK_PID" alt="processRxByte CHK_PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte HSHAKE" alt="processRxByte HSHAKE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram24.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar16.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram16.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index16.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar24.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram24.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index24.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm	(revision 264)
@@ -0,0 +1,499 @@
+<html>
+<head>
+<title>processRxByte.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// processRxByte</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:34 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>processRxByte</span> (<span id=t_idt>CRC16En</span>, <span id=t_idt>CRC16Result</span>, <span id=t_idt>CRC16UpdateRdy</span>, <span id=t_idt>CRC5En</span>, <span id=t_idt>CRC5Result</span>, <span id=t_idt>CRC5UpdateRdy</span>, <span id=t_idt>CRC5_8Bit</span>, <span id=t_idt>CRCData</span>, <span id=t_idt>RxByteIn</span>, <span id=t_idt>RxCtrlIn</span>, <span id=t_idt>RxCtrlOut</span>, <span id=t_idt>RxDataOutWEn</span>, <span id=t_idt>RxDataOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>processRxByteRdy</span>, <span id=t_idt>processRxDataInWEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>rstCRC</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC16Result</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC16UpdateRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC5Result</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC5UpdateRdy</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteIn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processRxDataInWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC16En</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC5En</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRC5_8Bit</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCData</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RxDataOutWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processRxByteRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>rstCRC</span>;
+
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC16En</span>, <span id=t_idt>next_CRC16En</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC16Result</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>CRC16UpdateRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC5En</span>, <span id=t_idt>next_CRC5En</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRC5Result</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>CRC5UpdateRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRC5_8Bit</span>, <span id=t_idt>next_CRC5_8Bit</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCData</span>, <span id=t_idt>next_CRCData</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteIn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlIn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>, <span id=t_idt>next_RxCtrlOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RxDataOutWEn</span>, <span id=t_idt>next_RxDataOutWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>, <span id=t_idt>next_RxDataOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processRxByteRdy</span>, <span id=t_idt>next_processRxByteRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processRxDataInWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>rstCRC</span>, <span id=t_idt>next_rstCRC</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>ACKRxed</span>, <span id=t_idt>next_ACKRxed</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>CRCError</span>, <span id=t_idt>next_CRCError</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>NAKRxed</span>, <span id=t_idt>next_NAKRxed</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteStMachCurrState</span>, <span id=t_idt>next_RXByteStMachCurrState</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>9</span>:<span id=t_cns>0</span>]<span id=t_idt>RXDataByteCnt</span>, <span id=t_idt>next_RXDataByteCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RxByte</span>, <span id=t_idt>next_RxByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RxCtrl</span>, <span id=t_idt>next_RxCtrl</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>RxOverflow</span>, <span id=t_idt>next_RxOverflow</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RxStatus</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>RxTimeOut</span>, <span id=t_idt>next_RxTimeOut</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>Signal1</span>, <span id=t_idt>next_Signal1</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>bitStuffError</span>, <span id=t_idt>next_bitStuffError</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>dataSequence</span>, <span id=t_idt>next_dataSequence</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>stallRxed</span>, <span id=t_idt>next_stallRxed</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: prRxByte</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_ST</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_PRBY</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BYTE</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_CHK_START</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_SYNC_DO</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PID_DO_CHK</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PID_FIRST_BYTE_PROC</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>HSHAKE_FIN</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>HSHAKE_CHK</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN_CHK_STRM</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN_FIN</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_FIN</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_CHK_STRM</span> <span id=t_cns>4'b1100</span>
+<span id=t_dir>`define</span> <span id=t_idt>TOKEN_WAIT_CRC</span> <span id=t_cns>4'b1101</span>
+<span id=t_dir>`define</span> <span id=t_idt>DATA_WAIT_CRC</span> <span id=t_cns>4'b1110</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_prRxByte</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_prRxByte</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_kwd>always</span> @
+(<span id=t_idt>next_CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>next_bitStuffError</span> <span id=t_kwd>or</span>
+  <span id=t_idt>next_RxOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>next_NAKRxed</span> <span id=t_kwd>or</span>
+  <span id=t_idt>next_stallRxed</span> <span id=t_kwd>or</span> <span id=t_idt>next_ACKRxed</span> <span id=t_kwd>or</span>
+  <span id=t_idt>next_dataSequence</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>RxStatus</span> &lt;=
+    {<span id=t_cns>1'b0</span>, <span id=t_idt>next_dataSequence</span>,
+    <span id=t_idt>next_ACKRxed</span>,
+    <span id=t_idt>next_stallRxed</span>, <span id=t_idt>next_NAKRxed</span>,
+    <span id=t_idt>next_RxOverflow</span>,
+    <span id=t_idt>next_bitStuffError</span>, <span id=t_idt>next_CRCError</span> };
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: prRxByte</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RxByteIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxCtrlIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>RxStatus</span> <span id=t_kwd>or</span> <span id=t_idt>RxByte</span> <span id=t_kwd>or</span> <span id=t_idt>RXDataByteCnt</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16Result</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5Result</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteStMachCurrState</span> <span id=t_kwd>or</span> <span id=t_idt>processRxDataInWEn</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16UpdateRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5UpdateRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>RxOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RxTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>NAKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>stallRxed</span> <span id=t_kwd>or</span> <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>dataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>RxDataOut</span> <span id=t_kwd>or</span> <span id=t_idt>RxCtrlOut</span> <span id=t_kwd>or</span> <span id=t_idt>RxDataOutWEn</span> <span id=t_kwd>or</span> <span id=t_idt>rstCRC</span> <span id=t_kwd>or</span> <span id=t_idt>CRCData</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5En</span> <span id=t_kwd>or</span> <span id=t_idt>CRC5_8Bit</span> <span id=t_kwd>or</span> <span id=t_idt>CRC16En</span> <span id=t_kwd>or</span> <span id=t_idt>processRxByteRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_prRxByte</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxByte_NextState</span>
+  <span id=t_idt>NextState_prRxByte</span> &lt;= <span id=t_idt>CurrState_prRxByte</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_RxByte</span> &lt;= <span id=t_idt>RxByte</span>;
+  <span id=t_idt>next_RxCtrl</span> &lt;= <span id=t_idt>RxCtrl</span>;
+  <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= <span id=t_idt>RXByteStMachCurrState</span>;
+  <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>CRCError</span>;
+  <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>bitStuffError</span>;
+  <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_idt>RxOverflow</span>;
+  <span id=t_idt>next_RxTimeOut</span> &lt;= <span id=t_idt>RxTimeOut</span>;
+  <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_idt>NAKRxed</span>;
+  <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_idt>stallRxed</span>;
+  <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>ACKRxed</span>;
+  <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>dataSequence</span>;
+  <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxDataOut</span>;
+  <span id=t_idt>next_RxCtrlOut</span> &lt;= <span id=t_idt>RxCtrlOut</span>;
+  <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_idt>RxDataOutWEn</span>;
+  <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_idt>rstCRC</span>;
+  <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>CRCData</span>;
+  <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_idt>CRC5En</span>;
+  <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_idt>CRC5_8Bit</span>;
+  <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_idt>CRC16En</span>;
+  <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_idt>RXDataByteCnt</span>;
+  <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_idt>processRxByteRdy</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_prRxByte</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>CHK_ST</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>TOKEN_BYTE_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>TOKEN_WAIT_CRC</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>HS_BYTE_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>HSHAKE_CHK</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>CHECK_PID_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>CHK_PID_DO_CHK</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>CHECK_SYNC_ST</span>)  
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>CHK_SYNC_DO</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>IDLE_BYTE_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>IDLE_CHK_START</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByteStMachCurrState</span> == `<span id=t_idt>DATA_BYTE_ST</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>DATA_WAIT_CRC</span>;
+   `<span id=t_idt>START_PRBY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RxByte</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RxCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RxCtrlOut</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRCData</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_cns>10'h00</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_BYTE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxDataInWEn</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>CHK_ST</span>;
+      <span id=t_idt>next_RxByte</span> &lt;= <span id=t_idt>RxByteIn</span>;
+      <span id=t_idt>next_RxCtrl</span> &lt;= <span id=t_idt>RxCtrlIn</span>;
+      <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>HSHAKE_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>HSHAKE_CHK</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>HSHAKE_FIN</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RxCtrl</span> != `<span id=t_idt>DATA_STOP</span>) <span id=t_com>//If more than PID rxed, then report error</span>
+       <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+     <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PID_DO_CHK</span>:
+     <span id=t_kwd>if</span> ((<span id=t_idt>RxByte</span>[<span id=t_cns>7</span>:<span id=t_cns>4</span>] ^ <span id=t_idt>RxByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] ) != <span id=t_cns>4'hf</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+      <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+      <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>CHK_PID_FIRST_BYTE_PROC</span>;
+      <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_RxTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_cns>0</span>;
+      <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxByte</span>;
+      <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_START</span>;
+      <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PID_FIRST_BYTE_PROC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>case</span> (<span id=t_idt>RxByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] )
+         `<span id=t_idt>SPECIAL</span>:                              <span id=t_com>//Special PID.</span>
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         `<span id=t_idt>TOKEN</span>:                                <span id=t_com>//Token PID</span>
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>TOKEN_BYTE_ST</span>;
+         <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_cns>0</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>HANDSHAKE</span>:                            <span id=t_com>//Handshake PID</span>
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>case</span> (<span id=t_idt>RxByte</span>[<span id=t_cns>3</span>:<span id=t_cns>2</span>] )
+                 <span id=t_cns>2'b00</span>:
+             <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b1</span>;
+                 <span id=t_cns>2'b10</span>:
+             <span id=t_idt>next_NAKRxed</span> &lt;= <span id=t_cns>1'b1</span>;
+                 <span id=t_cns>2'b11</span>:
+             <span id=t_idt>next_stallRxed</span> &lt;= <span id=t_cns>1'b1</span>;
+                 <span id=t_kwd>default</span>:
+                 <span id=t_kwd>begin</span>
+                     <span id=t_sys>$display</span> (<span id=t_cns>"Invalid Handshake PID detected in ProcessRXByte\n"</span>);
+                 <span id=t_kwd>end</span>
+             <span id=t_kwd>endcase</span>
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>HS_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA</span>:                                  <span id=t_com>//Data PID</span>
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>case</span> (<span id=t_idt>RxByte</span>[<span id=t_cns>3</span>:<span id=t_cns>2</span>] )
+                 <span id=t_cns>2'b00</span>:
+             <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+                 <span id=t_cns>2'b10</span>:
+             <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b1</span>;
+                 <span id=t_kwd>default</span>:
+                     <span id=t_sys>$display</span> (<span id=t_cns>"Invalid DATA PID detected in ProcessRXByte\n"</span>);
+             <span id=t_kwd>endcase</span>
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>DATA_BYTE_ST</span>;
+         <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_cns>0</span>;
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>endcase</span>
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_CHK_STRM</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_idt>RXDataByteCnt</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>case</span> (<span id=t_idt>RxCtrl</span>)
+         `<span id=t_idt>DATA_STOP</span>:
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>if</span> (<span id=t_idt>CRC16Result</span> != <span id=t_cns>16'hb001</span>)
+           <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA_BIT_STUFF_ERROR</span>:
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA_STREAM</span>:
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxByte</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STREAM</span>;
+         <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>RxByte</span>;
+         <span id=t_idt>next_CRC16En</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>endcase</span>
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>DATA_FIN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DATA_WAIT_CRC</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC16UpdateRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>DATA_CHK_STRM</span>;
+   `<span id=t_idt>TOKEN_CHK_STRM</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXDataByteCnt</span> &lt;= <span id=t_idt>RXDataByteCnt</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>case</span> (<span id=t_idt>RxCtrl</span>)
+         `<span id=t_idt>DATA_STOP</span>:
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>if</span> (<span id=t_idt>CRC5Result</span> != <span id=t_cns>5'h6</span>)
+           <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA_BIT_STUFF_ERROR</span>:
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b1</span>;
+         <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+         <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+         <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+         <span id=t_kwd>end</span>
+         `<span id=t_idt>DATA_STREAM</span>:
+         <span id=t_kwd>begin</span>
+             <span id=t_kwd>if</span> (<span id=t_idt>RXDataByteCnt</span> &gt; <span id=t_cns>10'h2</span>)
+             <span id=t_kwd>begin</span>
+           <span id=t_idt>next_RxOverflow</span> &lt;= <span id=t_cns>1'b1</span>;
+           <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxStatus</span>;
+           <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STOP</span>;
+           <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+             <span id=t_kwd>end</span>
+             <span id=t_kwd>else</span>
+             <span id=t_kwd>begin</span>
+           <span id=t_idt>next_RxDataOut</span> &lt;= <span id=t_idt>RxByte</span>;
+           <span id=t_idt>next_RxCtrlOut</span> &lt;= `<span id=t_idt>RX_PACKET_STREAM</span>;
+           <span id=t_idt>next_CRCData</span> &lt;= <span id=t_idt>RxByte</span>;
+           <span id=t_idt>next_CRC5_8Bit</span> &lt;= <span id=t_cns>1'b1</span>;
+           <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b1</span>;
+             <span id=t_kwd>end</span>
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>endcase</span>
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>TOKEN_FIN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>TOKEN_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>TOKEN_WAIT_CRC</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>CRC5UpdateRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>TOKEN_CHK_STRM</span>;
+   `<span id=t_idt>CHK_SYNC_DO</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxByte</span> == `<span id=t_idt>SYNC_BYTE</span>)
+       <span id=t_idt>next_RXByteStMachCurrState</span> = `<span id=t_idt>CHECK_PID_ST</span>;
+     <span id=t_kwd>else</span>
+       <span id=t_idt>next_RXByteStMachCurrState</span> = `<span id=t_idt>IDLE_BYTE_ST</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_CHK_START</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxCtrl</span> == `<span id=t_idt>DATA_START</span>)
+       <span id=t_idt>next_RXByteStMachCurrState</span> &lt;= `<span id=t_idt>CHECK_SYNC_ST</span>;
+     <span id=t_idt>NextState_prRxByte</span> &lt;= `<span id=t_idt>WAIT_BYTE</span>;
+     <span id=t_idt>next_processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxByte_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_prRxByte</span> &lt;= `<span id=t_idt>START_PRBY</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_prRxByte</span> &lt;= <span id=t_idt>NextState_prRxByte</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prRxByte_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RxByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXByteStMachCurrState</span> &lt;= `<span id=t_idt>IDLE_BYTE_ST</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RxOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RxTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>NAKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>stallRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXDataByteCnt</span> &lt;= <span id=t_cns>10'h00</span>;
+   <span id=t_idt>RxDataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxCtrlOut</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxDataOutWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>rstCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRCData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>CRC5En</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRC5_8Bit</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>CRC16En</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>processRxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RxByte</span> &lt;= <span id=t_idt>next_RxByte</span>;
+   <span id=t_idt>RxCtrl</span> &lt;= <span id=t_idt>next_RxCtrl</span>;
+   <span id=t_idt>RXByteStMachCurrState</span> &lt;= <span id=t_idt>next_RXByteStMachCurrState</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_idt>next_CRCError</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_idt>next_bitStuffError</span>;
+   <span id=t_idt>RxOverflow</span> &lt;= <span id=t_idt>next_RxOverflow</span>;
+   <span id=t_idt>RxTimeOut</span> &lt;= <span id=t_idt>next_RxTimeOut</span>;
+   <span id=t_idt>NAKRxed</span> &lt;= <span id=t_idt>next_NAKRxed</span>;
+   <span id=t_idt>stallRxed</span> &lt;= <span id=t_idt>next_stallRxed</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_idt>next_ACKRxed</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_idt>next_dataSequence</span>;
+   <span id=t_idt>RXDataByteCnt</span> &lt;= <span id=t_idt>next_RXDataByteCnt</span>;
+   <span id=t_idt>RxDataOut</span> &lt;= <span id=t_idt>next_RxDataOut</span>;
+   <span id=t_idt>RxCtrlOut</span> &lt;= <span id=t_idt>next_RxCtrlOut</span>;
+   <span id=t_idt>RxDataOutWEn</span> &lt;= <span id=t_idt>next_RxDataOutWEn</span>;
+   <span id=t_idt>rstCRC</span> &lt;= <span id=t_idt>next_rstCRC</span>;
+   <span id=t_idt>CRCData</span> &lt;= <span id=t_idt>next_CRCData</span>;
+   <span id=t_idt>CRC5En</span> &lt;= <span id=t_idt>next_CRC5En</span>;
+   <span id=t_idt>CRC5_8Bit</span> &lt;= <span id=t_idt>next_CRC5_8Bit</span>;
+   <span id=t_idt>CRC16En</span> &lt;= <span id=t_idt>next_CRC16En</span>;
+   <span id=t_idt>processRxByteRdy</span> &lt;= <span id=t_idt>next_processRxByteRdy</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar24.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar24.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar24.html	(revision 264)
@@ -0,0 +1,54 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 3;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(471,1029,574,1132,Click97,Over97);
+FUB[1] = new Array(274,1611,376,1714,Click113,Over113);
+FUB[2] = new Array(865,1611,967,1714,Click115,Over115);
+
+//----------------------------------------------------------------------------
+function Click97(){fubclick('./index97.htm');}
+function Over97(){window.status='Hierarchical State DATA';};
+function Click113(){fubclick('./index113.htm');}
+function Over113(){window.status='Hierarchical State BYTE';};
+function Click115(){fubclick('./index115.htm');}
+function Over115(){window.status='Hierarchical State ERROR';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 24 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_DATA_RX.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar24.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte" alt="processRxByte"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram216.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram216.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram216.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte IDLE" alt="processRxByte IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram216.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index216.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index216.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index216.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar216.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram216.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index216.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 16 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 97 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar97.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram213.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram213.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram213.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte CHK_SYNC" alt="processRxByte CHK_SYNC"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram213.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_FIRST_BYTE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_FIRST_BYTE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,63 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 6;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(861,1403,963,1505,Click24,Over24);
+FUB[1] = new Array(859,1176,962,1279,Click16,Over16);
+FUB[2] = new Array(883,1858,986,1961,Click42,Over42);
+FUB[3] = new Array(874,1639,976,1741,Click33,Over33);
+FUB[4] = new Array(841,912,944,1014,Click216,Over216);
+FUB[5] = new Array(845,1042,948,1144,Click213,Over213);
+
+//----------------------------------------------------------------------------
+function Click24(){fubclick('./index24.htm');}
+function Over24(){window.status='Hierarchical State HSHAKE';};
+function Click16(){fubclick('./index16.htm');}
+function Over16(){window.status='Hierarchical State CHK_PID';};
+function Click42(){fubclick('./index42.htm');}
+function Over42(){window.status='Hierarchical State DATA';};
+function Click33(){fubclick('./index33.htm');}
+function Over33(){window.status='Hierarchical State TOKEN';};
+function Click216(){fubclick('./index216.htm');}
+function Over216(){window.status='Hierarchical State IDLE';};
+function Click213(){fubclick('./index213.htm');}
+function Over213(){window.status='Hierarchical State CHK_SYNC';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar216.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar216.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar216.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 216 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar216.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_DATA.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram42.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram42.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram42.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte DATA" alt="processRxByte DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram42.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar213.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram213.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index213.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index42.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index42.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index42.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar42.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram42.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index42.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_CHK_SYNC.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_CHK_SYNC.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_IDLE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_IDLE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 18 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_FIRST_BYTE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar18.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processTxByte" alt="processTxByte"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_TOKEN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_TOKEN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar213.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar213.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar213.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 213 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_CHK_SYNC.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar213.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar42.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar42.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar42.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 42 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar42.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index874.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index874.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index874.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar874.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram874.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index874.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm	(revision 264)
@@ -0,0 +1,351 @@
+<html>
+<head>
+<title>processTxByte.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// processTxByte</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:39 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>processTxByte</span> (<span id=t_idt>JBit</span>, <span id=t_idt>KBit</span>, <span id=t_idt>TxByteCtrlIn</span>, <span id=t_idt>TxByteIn</span>, <span id=t_idt>USBWireCtrl</span>, <span id=t_idt>USBWireData</span>, <span id=t_idt>USBWireGnt</span>, <span id=t_idt>USBWireRdy</span>, <span id=t_idt>USBWireReq</span>, <span id=t_idt>USBWireWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>processTxByteRdy</span>, <span id=t_idt>processTxByteWEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteCtrlIn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processTxByteWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireCtrl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processTxByteRdy</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteCtrlIn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireCtrl</span>, <span id=t_idt>next_USBWireCtrl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireData</span>, <span id=t_idt>next_USBWireData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireReq</span>, <span id=t_idt>next_USBWireReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireWEn</span>, <span id=t_idt>next_USBWireWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processTxByteRdy</span>, <span id=t_idt>next_processTxByteRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processTxByteWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>TXLineState</span>, <span id=t_idt>next_TXLineState</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>TXOneCount</span>, <span id=t_idt>next_TXOneCount</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>TxByteCtrl</span>, <span id=t_idt>next_TxByteCtrl</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>TxByte</span>, <span id=t_idt>next_TxByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>i</span>, <span id=t_idt>next_i</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: prcTxB</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_PTBY</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PTBY_WAIT_EN</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_UPDATE_BYTE</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_WAIT_RDY</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_CHK</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_BIT_STUFF</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_WAIT_RDY2</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>SEND_BYTE_CHK_FIN</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PTBY_WAIT_GNT</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_SND_SE0_2</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_SND_SE0_1</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_CHK</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_SND_J</span> <span id=t_cns>4'b1100</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_SND_IDLE</span> <span id=t_cns>4'b1101</span>
+<span id=t_dir>`define</span> <span id=t_idt>STOP_FIN</span> <span id=t_cns>4'b1110</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_prcTxB</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_prcTxB</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: prcTxB</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>TxByteIn</span> <span id=t_kwd>or</span> <span id=t_idt>TxByteCtrlIn</span> <span id=t_kwd>or</span> <span id=t_idt>JBit</span> <span id=t_kwd>or</span> <span id=t_idt>i</span> <span id=t_kwd>or</span> <span id=t_idt>TxByte</span> <span id=t_kwd>or</span> <span id=t_idt>TXOneCount</span> <span id=t_kwd>or</span> <span id=t_idt>TXLineState</span> <span id=t_kwd>or</span> <span id=t_idt>KBit</span> <span id=t_kwd>or</span> <span id=t_idt>processTxByteWEn</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireGnt</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireRdy</span> <span id=t_kwd>or</span> <span id=t_idt>TxByteCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>processTxByteRdy</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireData</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireReq</span> <span id=t_kwd>or</span> <span id=t_idt>USBWireWEn</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_prcTxB</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prcTxB_NextState</span>
+  <span id=t_idt>NextState_prcTxB</span> &lt;= <span id=t_idt>CurrState_prcTxB</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_idt>processTxByteRdy</span>;
+  <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>USBWireData</span>;
+  <span id=t_idt>next_USBWireCtrl</span> &lt;= <span id=t_idt>USBWireCtrl</span>;
+  <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_idt>USBWireReq</span>;
+  <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_idt>USBWireWEn</span>;
+  <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span>;
+  <span id=t_idt>next_TxByte</span> &lt;= <span id=t_idt>TxByte</span>;
+  <span id=t_idt>next_TxByteCtrl</span> &lt;= <span id=t_idt>TxByteCtrl</span>;
+  <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>TXLineState</span>;
+  <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_idt>TXOneCount</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_prcTxB</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_PTBY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_i</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>next_TxByte</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_TxByteCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_cns>2'b0</span>;
+     <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>PTBY_WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PTBY_WAIT_EN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>if</span> ((<span id=t_idt>processTxByteWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>TxByteCtrlIn</span> == `<span id=t_idt>DATA_START</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>PTBY_WAIT_GNT</span>;
+      <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_TxByte</span> &lt;= <span id=t_idt>TxByteIn</span>;
+      <span id=t_idt>next_TxByteCtrl</span> &lt;= <span id=t_idt>TxByteCtrlIn</span>;
+      <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_cns>1</span>;
+      <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>processTxByteWEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>;
+      <span id=t_idt>next_processTxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_TxByte</span> &lt;= <span id=t_idt>TxByteIn</span>;
+      <span id=t_idt>next_TxByteCtrl</span> &lt;= <span id=t_idt>TxByteCtrlIn</span>;
+      <span id=t_idt>next_i</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PTBY_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireGnt</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>;
+      <span id=t_idt>next_i</span> &lt;= <span id=t_cns>4'h0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_TxByte</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>TxByte</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>] };
+     <span id=t_kwd>if</span> (<span id=t_idt>TxByte</span>[<span id=t_cns>0</span>] == <span id=t_cns>1'b1</span>)                      <span id=t_com>//If this bit is 1, then</span>
+       <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_idt>TXOneCount</span> + <span id=t_cns>1'b1</span>;
+         <span id=t_com>//increment 'TXOneCount'</span>
+     <span id=t_kwd>else</span>                                        <span id=t_com>//else this is a zero bit</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_cns>4'h1</span>;
+         <span id=t_com>//reset 'TXOneCount'</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>TXLineState</span> == <span id=t_idt>JBit</span>) <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>KBit</span>;
+         <span id=t_com>//toggle the line state</span>
+       <span id=t_kwd>else</span> <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>JBit</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_CHK</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>TXLineState</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_CHK</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>TXOneCount</span> == <span id=t_cns>4'h6</span>)  
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_BIT_STUFF</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>i</span> != <span id=t_cns>4'h8</span>)  
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_CHK</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_BIT_STUFF</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_TXOneCount</span> &lt;= <span id=t_cns>4'h1</span>;
+     <span id=t_com>//reset 'TXOneCount'</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>TXLineState</span> == <span id=t_idt>JBit</span>) <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>KBit</span>;
+     <span id=t_com>//toggle the line state</span>
+     <span id=t_kwd>else</span> <span id=t_idt>next_TXLineState</span> &lt;= <span id=t_idt>JBit</span>;
+     <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_WAIT_RDY2</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_WAIT_RDY2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_CHK_FIN</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>TXLineState</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SEND_BYTE_CHK_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>4'h8</span>) 
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_CHK</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>SEND_BYTE_UPDATE_BYTE</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_SND_SE0_2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_SND_J</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= `<span id=t_idt>SE0</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_SND_SE0_1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_SND_SE0_2</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= `<span id=t_idt>SE0</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_CHK</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>TxByteCtrl</span> == `<span id=t_idt>DATA_STOP</span>)  
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_SND_SE0_1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>PTBY_WAIT_EN</span>;
+   `<span id=t_idt>STOP_SND_J</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_SND_IDLE</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>DRIVE</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_SND_IDLE</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>USBWireRdy</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>STOP_FIN</span>;
+      <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBWireData</span> &lt;= <span id=t_idt>JBit</span>;
+      <span id=t_idt>next_USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>STOP_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_com>//release the wire</span>
+     <span id=t_idt>NextState_prcTxB</span> &lt;= `<span id=t_idt>PTBY_WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prcTxB_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_prcTxB</span> &lt;= `<span id=t_idt>START_PTBY</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_prcTxB</span> &lt;= <span id=t_idt>NextState_prcTxB</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>prcTxB_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>TxByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>TxByteCtrl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>TXLineState</span> &lt;= <span id=t_cns>2'b0</span>;
+   <span id=t_idt>TXOneCount</span> &lt;= <span id=t_cns>4'h0</span>;
+   <span id=t_idt>processTxByteRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>USBWireData</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>USBWireCtrl</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+   <span id=t_idt>USBWireReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>i</span> &lt;= <span id=t_idt>next_i</span>;
+   <span id=t_idt>TxByte</span> &lt;= <span id=t_idt>next_TxByte</span>;
+   <span id=t_idt>TxByteCtrl</span> &lt;= <span id=t_idt>next_TxByteCtrl</span>;
+   <span id=t_idt>TXLineState</span> &lt;= <span id=t_idt>next_TXLineState</span>;
+   <span id=t_idt>TXOneCount</span> &lt;= <span id=t_idt>next_TXOneCount</span>;
+   <span id=t_idt>processTxByteRdy</span> &lt;= <span id=t_idt>next_processTxByteRdy</span>;
+   <span id=t_idt>USBWireData</span> &lt;= <span id=t_idt>next_USBWireData</span>;
+   <span id=t_idt>USBWireCtrl</span> &lt;= <span id=t_idt>next_USBWireCtrl</span>;
+   <span id=t_idt>USBWireReq</span> &lt;= <span id=t_idt>next_USBWireReq</span>;
+   <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_idt>next_USBWireWEn</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 33 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_TOKEN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processTxByte STOP" alt="processTxByte STOP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram887.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte_SEND_BYTE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte_SEND_BYTE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar887.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar887.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar887.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 887 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processTxByte_STOP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processTxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar887.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram46.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram46.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram46.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver WAIT_FS_CONN" alt="siereceiver WAIT_FS_CONN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram46.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram82.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram82.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram82.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver WAIT_LS_DIS" alt="siereceiver WAIT_LS_DIS"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram82.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar46.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram46.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index46.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar874.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar874.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar874.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 874 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processTxByte_SEND_BYTE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processTxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar874.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram23.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram23.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram23.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver DISCNCT" alt="siereceiver DISCNCT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram23.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram73.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram73.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram73.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver FS_CONN" alt="siereceiver FS_CONN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram73.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index23.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index23.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index23.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar23.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram23.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index23.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index73.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index73.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index73.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar73.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram73.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index73.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar97.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram97.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/index97.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(330,1478,432,1580,Click874,Over874);
+FUB[1] = new Array(342,1793,444,1895,Click887,Over887);
+
+//----------------------------------------------------------------------------
+function Click874(){fubclick('./index874.htm');}
+function Over874(){window.status='Hierarchical State SEND_BYTE';};
+function Click887(){fubclick('./index887.htm');}
+function Over887(){window.status='Hierarchical State STOP';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processTxByte.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processTxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver" alt="siereceiver"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram64.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram64.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram64.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver LS_CONN" alt="siereceiver LS_CONN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram64.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index82.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index82.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index82.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar82.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram82.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index82.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index64.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index64.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index64.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar64.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram64.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index64.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm	(revision 264)
@@ -0,0 +1,371 @@
+<html>
+<head>
+<title>siereceiver.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SIEReceiver</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:47 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>SIEReceiver</span> (<span id=t_idt>RxBitsOut</span>, <span id=t_idt>RxWireDataIn</span>, <span id=t_idt>RxWireDataWEn</span>, <span id=t_idt>SIERxRdyOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>connectState</span>, <span id=t_idt>processRxBitRdyIn</span>, <span id=t_idt>processRxBitsWEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxWireDataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RxWireDataWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>processRxBitRdyIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SIERxRdyOut</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>processRxBitsWEn</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsOut</span>, <span id=t_idt>next_RxBitsOut</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxWireDataIn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RxWireDataWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SIERxRdyOut</span>, <span id=t_idt>next_SIERxRdyOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>, <span id=t_idt>next_connectState</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>processRxBitRdyIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>processRxBitsWEn</span>, <span id=t_idt>next_processRxBitsWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>]<span id=t_idt>RXStMachCurrState</span>, <span id=t_idt>next_RXStMachCurrState</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXWaitCount</span>, <span id=t_idt>next_RXWaitCount</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>RxBits</span>, <span id=t_idt>next_RxBits</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: rcvr</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FS_CONN_CHK_RX_BITS</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LS_CONN_CHK_RX_BITS</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>LS_CONN_CHK_RX_BITS</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DISCNCT_CHK_RXBITS</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BIT</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SRX</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>LS_CONN_PROC_RX_BITS</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>FS_CONN_CHK_RX_BITS1</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LS_DIS_CHK_RX_BITS</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LS_DIS_PROC_RX_BITS</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FS_DIS_PROC_RX_BITS2</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_FS_DIS_CHK_RX_BITS2</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>FS_CONN_PROC_RX_BITS1</span> <span id=t_cns>4'b1100</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_rcvr</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_rcvr</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: rcvr</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RxWireDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>RxBits</span> <span id=t_kwd>or</span> <span id=t_idt>RXWaitCount</span> <span id=t_kwd>or</span> <span id=t_idt>RxWireDataWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXStMachCurrState</span> <span id=t_kwd>or</span> <span id=t_idt>processRxBitRdyIn</span> <span id=t_kwd>or</span> <span id=t_idt>SIERxRdyOut</span> <span id=t_kwd>or</span> <span id=t_idt>connectState</span> <span id=t_kwd>or</span> <span id=t_idt>RxBitsOut</span> <span id=t_kwd>or</span> <span id=t_idt>processRxBitsWEn</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_rcvr</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>rcvr_NextState</span>
+  <span id=t_idt>NextState_rcvr</span> &lt;= <span id=t_idt>CurrState_rcvr</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxBits</span>;
+  <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_idt>SIERxRdyOut</span>;
+  <span id=t_idt>next_RXStMachCurrState</span> &lt;= <span id=t_idt>RXStMachCurrState</span>;
+  <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span>;
+  <span id=t_idt>next_connectState</span> &lt;= <span id=t_idt>connectState</span>;
+  <span id=t_idt>next_RxBitsOut</span> &lt;= <span id=t_idt>RxBitsOut</span>;
+  <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_idt>processRxBitsWEn</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_rcvr</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>WAIT_BIT</span>:
+     <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>WAIT_LOW_SPEED_CONN_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_LS_CONN_CHK_RX_BITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>CONNECT_LOW_SPEED_ST</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>LS_CONN_CHK_RX_BITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>CONNECT_FULL_SPEED_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>FS_CONN_CHK_RX_BITS1</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>WAIT_LOW_SP_DISCONNECT_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_LS_DIS_CHK_RX_BITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>WAIT_FULL_SP_DISCONNECT_ST</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_FS_DIS_CHK_RX_BITS2</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>DISCONNECT_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>DISCNCT_CHK_RXBITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> ((<span id=t_idt>RxWireDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStMachCurrState</span> == `<span id=t_idt>WAIT_FULL_SPEED_CONN_ST</span>)) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_FS_CONN_CHK_RX_BITS</span>;
+      <span id=t_idt>next_RxBits</span> &lt;= <span id=t_idt>RxWireDataIn</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>START_SRX</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>DISCONNECT_ST</span>;
+     <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>8'h00</span>;
+     <span id=t_idt>next_connectState</span> &lt;= `<span id=t_idt>DISCONNECT</span>;
+     <span id=t_idt>next_RxBits</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_RxBitsOut</span> &lt;= <span id=t_cns>2'b00</span>;
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DISCNCT_CHK_RXBITS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>ZERO_ONE</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+      <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_LOW_SPEED_CONN_ST</span>;
+      <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>ONE_ZERO</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+      <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_FULL_SPEED_CONN_ST</span>;
+      <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_FS_CONN_CHK_RX_BITS</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>ONE_ZERO</span>)
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span> + <span id=t_cns>1'b1</span>;
+         <span id=t_kwd>if</span> (<span id=t_idt>RXWaitCount</span> == `<span id=t_idt>CONNECT_WAIT_TIME</span>)
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_connectState</span> &lt;= `<span id=t_idt>FULL_SPEED_CONNECT</span>;
+         <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>CONNECT_FULL_SPEED_ST</span>;
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXStMachCurrState</span> = `<span id=t_idt>DISCONNECT_ST</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_LS_CONN_CHK_RX_BITS</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>ZERO_ONE</span>)
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span> + <span id=t_cns>1'b1</span>;
+         <span id=t_kwd>if</span> (<span id=t_idt>RXWaitCount</span> == `<span id=t_idt>CONNECT_WAIT_TIME</span>)
+         <span id=t_kwd>begin</span>
+         <span id=t_idt>next_connectState</span> &lt;= `<span id=t_idt>LOW_SPEED_CONNECT</span>;
+         <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>CONNECT_LOW_SPEED_ST</span>;
+         <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>next_RXStMachCurrState</span> = `<span id=t_idt>DISCONNECT_ST</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>LS_CONN_CHK_RX_BITS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxBitRdyIn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>LS_CONN_PROC_RX_BITS</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_LOW_SP_DISCONNECT_ST</span>;
+        <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>0</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_RxBitsOut</span> &lt;= <span id=t_idt>RxBits</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>LS_CONN_PROC_RX_BITS</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>FS_CONN_CHK_RX_BITS1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxBitRdyIn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>FS_CONN_PROC_RX_BITS1</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_FULL_SP_DISCONNECT_ST</span>;
+        <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_cns>0</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_RxBitsOut</span> &lt;= <span id=t_idt>RxBits</span>;
+      <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_com>//early indication of ready</span>
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>FS_CONN_PROC_RX_BITS1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_LS_DIS_CHK_RX_BITS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxBitRdyIn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_LS_DIS_PROC_RX_BITS</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span> + <span id=t_cns>1'b1</span>;
+          <span id=t_kwd>if</span> (<span id=t_idt>RXWaitCount</span> == `<span id=t_idt>DISCONNECT_WAIT_TIME</span>)
+          <span id=t_kwd>begin</span>
+          <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>DISCONNECT_ST</span>;
+          <span id=t_idt>next_connectState</span> = `<span id=t_idt>DISCONNECT</span>;
+          <span id=t_kwd>end</span>
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span>
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXStMachCurrState</span> = `<span id=t_idt>CONNECT_LOW_SPEED_ST</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_LS_DIS_PROC_RX_BITS</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_FS_DIS_PROC_RX_BITS2</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_BIT</span>;
+     <span id=t_idt>next_SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_FS_DIS_CHK_RX_BITS2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>processRxBitRdyIn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_rcvr</span> &lt;= `<span id=t_idt>WAIT_FS_DIS_PROC_RX_BITS2</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>RxBits</span> == `<span id=t_idt>SE0</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXWaitCount</span> &lt;= <span id=t_idt>RXWaitCount</span> + <span id=t_cns>1'b1</span>;
+          <span id=t_kwd>if</span> (<span id=t_idt>RXWaitCount</span> == `<span id=t_idt>DISCONNECT_WAIT_TIME</span>)
+          <span id=t_kwd>begin</span>
+          <span id=t_idt>next_RXStMachCurrState</span> &lt;= `<span id=t_idt>DISCONNECT_ST</span>;
+          <span id=t_idt>next_connectState</span> = `<span id=t_idt>DISCONNECT</span>;
+          <span id=t_kwd>end</span>
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span>
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>next_RXStMachCurrState</span> = `<span id=t_idt>CONNECT_FULL_SPEED_ST</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_idt>next_processRxBitsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>rcvr_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_rcvr</span> &lt;= `<span id=t_idt>START_SRX</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_rcvr</span> &lt;= <span id=t_idt>NextState_rcvr</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>rcvr_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXStMachCurrState</span> &lt;= `<span id=t_idt>DISCONNECT_ST</span>;
+   <span id=t_idt>RXWaitCount</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RxBits</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>connectState</span> &lt;= `<span id=t_idt>DISCONNECT</span>;
+   <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>processRxBitsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SIERxRdyOut</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXStMachCurrState</span> &lt;= <span id=t_idt>next_RXStMachCurrState</span>;
+   <span id=t_idt>RXWaitCount</span> &lt;= <span id=t_idt>next_RXWaitCount</span>;
+   <span id=t_idt>RxBits</span> &lt;= <span id=t_idt>next_RxBits</span>;
+   <span id=t_idt>connectState</span> &lt;= <span id=t_idt>next_connectState</span>;
+   <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>next_RxBitsOut</span>;
+   <span id=t_idt>processRxBitsWEn</span> &lt;= <span id=t_idt>next_processRxBitsWEn</span>;
+   <span id=t_idt>SIERxRdyOut</span> &lt;= <span id=t_idt>next_SIERxRdyOut</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_DISCNCT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_DISCNCT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_FS_DIS.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_FS_DIS.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar23.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar23.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar23.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 23 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_DISCNCT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar23.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_FS_CONN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_FS_CONN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_DATA.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,66 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 7;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1080,1893,1182,1996,Click23,Over23);
+FUB[1] = new Array(1073,1755,1175,1857,Click46,Over46);
+FUB[2] = new Array(1062,1607,1164,1709,Click55,Over55);
+FUB[3] = new Array(1045,1312,1147,1414,Click73,Over73);
+FUB[4] = new Array(1051,1466,1154,1569,Click64,Over64);
+FUB[5] = new Array(1025,981,1127,1083,Click91,Over91);
+FUB[6] = new Array(1034,1153,1136,1255,Click82,Over82);
+
+//----------------------------------------------------------------------------
+function Click23(){fubclick('./index23.htm');}
+function Over23(){window.status='Hierarchical State DISCNCT';};
+function Click46(){fubclick('./index46.htm');}
+function Over46(){window.status='Hierarchical State WAIT_FS_CONN';};
+function Click55(){fubclick('./index55.htm');}
+function Over55(){window.status='Hierarchical State WAIT_LS_CONN';};
+function Click73(){fubclick('./index73.htm');}
+function Over73(){window.status='Hierarchical State FS_CONN';};
+function Click64(){fubclick('./index64.htm');}
+function Over64(){window.status='Hierarchical State LS_CONN';};
+function Click91(){fubclick('./index91.htm');}
+function Over91(){window.status='Hierarchical State WAIT_FS_DIS';};
+function Click82(){fubclick('./index82.htm');}
+function Over82(){window.status='Hierarchical State WAIT_LS_DIS';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_LS_CONN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_LS_CONN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_END.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/processRxBit_RES_END.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 115 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_ERROR.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar115.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 42 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxBit_RES_END.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxBit.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxBit.asf/toolbar42.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte FIRST_BYTE" alt="processRxByte FIRST_BYTE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram18.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processRxByte TOKEN" alt="processRxByte TOKEN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar18.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram18.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index18.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar33.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram33.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/index33.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar73.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar73.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar73.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 73 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_FS_CONN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar73.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 64 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_LS_CONN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar64.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm	(revision 264)
@@ -0,0 +1,122 @@
+<html>
+<head>
+<title>updateCRC16.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// updateCRC16.v                                                ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:02 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>updateCRC16</span> (<span id=t_idt>rstCRC</span>, <span id=t_idt>CRCResult</span>, <span id=t_idt>CRCEn</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>ready</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>rstCRC</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRCEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCResult</span>;
+<span id=t_kwd>output</span> <span id=t_idt>ready</span>;
+
+<span id=t_kwd>wire</span>   <span id=t_idt>rstCRC</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>CRCEn</span>;
+<span id=t_kwd>wire</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>    [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCResult</span>;
+<span id=t_kwd>reg</span>    <span id=t_idt>ready</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>doUpdateCRC</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>i</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span> || <span id=t_idt>rstCRC</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>CRCResult</span> &lt;= <span id=t_cns>16'hffff</span>;
+    <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>doUpdateCRC</span> == <span id=t_cns>1'b0</span>)
+    <span id=t_kwd>begin</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>CRCEn</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>doUpdateCRC</span> = <span id=t_cns>1'b1</span>;
+        <span id=t_idt>data</span> &lt;= <span id=t_idt>dataIn</span>;
+        <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+      <span id=t_idt>i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>if</span> ( (<span id=t_idt>CRCResult</span>[<span id=t_cns>0</span>] ^ <span id=t_idt>data</span>[<span id=t_cns>0</span>]) == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>CRCResult</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>CRCResult</span>[<span id=t_cns>15</span>:<span id=t_cns>1</span>]} ^ <span id=t_cns>16'ha001</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+        <span id=t_idt>CRCResult</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>CRCResult</span>[<span id=t_cns>15</span>:<span id=t_cns>1</span>]};
+      <span id=t_kwd>end</span>
+      <span id=t_idt>data</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>data</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>]};
+      <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>4'h7</span>)
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b0</span>; 
+        <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+        <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+   
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/updateCRC16.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_LS_DIS.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_LS_DIS.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar55.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar55.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar55.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 55 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_WAIT_LS_CONN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar55.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 91 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_WAIT_FS_DIS.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar91.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="usbTxWireArbiter" alt="usbTxWireArbiter"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_CHK_PID.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_CHK_PID.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm	(revision 264)
@@ -0,0 +1,129 @@
+<html>
+<head>
+<title>updateCRC5.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// updateCRC5.v                                                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:03 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>updateCRC5</span> (<span id=t_idt>rstCRC</span>, <span id=t_idt>CRCResult</span>, <span id=t_idt>CRCEn</span>, <span id=t_idt>CRC5_8BitIn</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>ready</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>rstCRC</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRCEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>CRC5_8BitIn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCResult</span>;
+<span id=t_kwd>output</span> <span id=t_idt>ready</span>;
+
+<span id=t_kwd>wire</span>   <span id=t_idt>rstCRC</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>CRCEn</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>CRC5_8BitIn</span>;
+<span id=t_kwd>wire</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>    [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CRCResult</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>ready</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>doUpdateCRC</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>loopEnd</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>i</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span> || <span id=t_idt>rstCRC</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>CRCResult</span> &lt;= <span id=t_cns>5'h1f</span>;
+    <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>doUpdateCRC</span> == <span id=t_cns>1'b0</span>) <span id=t_kwd>begin</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>CRCEn</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b0</span>;
+        <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>data</span> &lt;= <span id=t_idt>dataIn</span>;
+        <span id=t_kwd>if</span> (<span id=t_idt>CRC5_8BitIn</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+          <span id=t_idt>loopEnd</span> &lt;= <span id=t_cns>4'h7</span>; 
+        <span id=t_kwd>end</span>
+        <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+         <span id=t_idt>loopEnd</span> &lt;= <span id=t_cns>4'h2</span>;
+        <span id=t_kwd>end</span>
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+      <span id=t_idt>i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>if</span> ( (<span id=t_idt>CRCResult</span>[<span id=t_cns>0</span>] ^ <span id=t_idt>data</span>[<span id=t_cns>0</span>]) == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+       <span id=t_idt>CRCResult</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>CRCResult</span>[<span id=t_cns>4</span>:<span id=t_cns>1</span>]} ^ <span id=t_cns>5'h14</span>;
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+        <span id=t_idt>CRCResult</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>CRCResult</span>[<span id=t_cns>4</span>:<span id=t_cns>1</span>]};
+      <span id=t_kwd>end</span>
+      <span id=t_idt>data</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>data</span>[<span id=t_cns>7</span>:<span id=t_cns>1</span>]};
+      <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_idt>loopEnd</span>) <span id=t_kwd>begin</span>
+        <span id=t_idt>doUpdateCRC</span> &lt;= <span id=t_cns>1'b0</span>; 
+       <span id=t_idt>i</span> &lt;= <span id=t_cns>4'h0</span>;
+        <span id=t_idt>ready</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+   
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/updateCRC5.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./usbTxWireArbiter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./usbTxWireArbiter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/writeUSBWireData.v/index.htm	(revision 264)
@@ -0,0 +1,320 @@
+<html>
+<head>
+<title>writeUSBWireData.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// writeUSBWireData.v                                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:08 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_dir>`define</span> <span id=t_idt>BUFFER_FULL</span>  <span id=t_cns>3'b100</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>writeUSBWireData</span> (
+  <span id=t_idt>TxBitsIn</span>, 
+  <span id=t_idt>TxBitsOut</span>,
+  <span id=t_idt>TxDataOutTick</span>,
+  <span id=t_idt>TxCtrlIn</span>, 
+  <span id=t_idt>TxCtrlOut</span>, 
+  <span id=t_idt>USBWireRdy</span>,
+  <span id=t_idt>USBWireWEn</span>, 
+  <span id=t_idt>disableWireReadOut</span>, 
+  <span id=t_idt>fullSpeedRate</span>, 
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>,
+  <span id=t_idt>noActivityTimeOut</span> );
+  
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>TxCtrlIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxDataOutTick</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>TxCtrlOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>disableWireReadOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>noActivityTimeOut</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsIn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>TxDataOutTick</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>TxCtrlIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>TxCtrlOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>  <span id=t_idt>disableWireReadOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>noActivityTimeOut</span>;
+
+<span id=t_com>// local registers</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer0</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer1</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer2</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer3</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferInIndex</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferOutIndex</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>decBufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>4</span>:<span id=t_cns>0</span>]<span id=t_idt>i</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>incBufferCnt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedTick</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>lowSpeedTick</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>timeOutCnt</span>;
+
+<span id=t_com>// buffer in state machine state codes:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BUFFER_NOT_FULL</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_WRITE_REQ</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>CLR_INC_BUFFER_CNT</span> <span id=t_cns>2'b10</span>
+
+<span id=t_com>// buffer output state machine state codes:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BUFFER_FULL</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_LINE_WRITE</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>LINE_WRITE</span> <span id=t_cns>2'b10</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>bufferInStMachCurrState</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>bufferOutStMachCurrState</span>;
+
+<span id=t_com>// buffer control</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>bufferCnt</span> &lt;= <span id=t_cns>3'b000</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>incBufferCnt</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>decBufferCnt</span> == <span id=t_cns>1'b0</span>)
+      <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>incBufferCnt</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>decBufferCnt</span> == <span id=t_cns>1'b1</span>)
+      <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> - <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//buffer input state machine </span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer0</span> &lt;= <span id=t_cns>3'b000</span>;
+   <span id=t_idt>buffer1</span> &lt;= <span id=t_cns>3'b000</span>;
+   <span id=t_idt>buffer2</span> &lt;= <span id=t_cns>3'b000</span>;
+   <span id=t_idt>buffer3</span> &lt;= <span id=t_cns>3'b000</span>;
+   <span id=t_idt>USBWireRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_NOT_FULL</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>case</span> (<span id=t_idt>bufferInStMachCurrState</span>)
+     `<span id=t_idt>WAIT_BUFFER_NOT_FULL</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span> != `<span id=t_idt>BUFFER_FULL</span>) 
+       <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_WRITE_REQ</span>;
+        <span id=t_idt>USBWireRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+       <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>WAIT_WRITE_REQ</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>USBWireWEn</span> == <span id=t_cns>1'b1</span>)
+       <span id=t_kwd>begin</span>
+        <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>USBWireRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+        <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_idt>bufferInIndex</span> + <span id=t_cns>1'b1</span>;
+        <span id=t_kwd>case</span> (<span id=t_idt>bufferInIndex</span>)
+          <span id=t_cns>2'b00</span> : <span id=t_idt>buffer0</span> &lt;= {<span id=t_idt>TxBitsIn</span>, <span id=t_idt>TxCtrlIn</span>};
+          <span id=t_cns>2'b01</span> : <span id=t_idt>buffer1</span> &lt;= {<span id=t_idt>TxBitsIn</span>, <span id=t_idt>TxCtrlIn</span>};
+          <span id=t_cns>2'b10</span> : <span id=t_idt>buffer2</span> &lt;= {<span id=t_idt>TxBitsIn</span>, <span id=t_idt>TxCtrlIn</span>};
+          <span id=t_cns>2'b11</span> : <span id=t_idt>buffer3</span> &lt;= {<span id=t_idt>TxBitsIn</span>, <span id=t_idt>TxCtrlIn</span>};
+        <span id=t_kwd>endcase</span>
+        <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>CLR_INC_BUFFER_CNT</span>;
+       <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>CLR_INC_BUFFER_CNT</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+       <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span> != (`<span id=t_idt>BUFFER_FULL</span> - <span id=t_cns>1'b1</span>) ) 
+       <span id=t_kwd>begin</span>
+        <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_WRITE_REQ</span>;
+        <span id=t_idt>USBWireRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+       <span id=t_kwd>end</span>
+        <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+         <span id=t_idt>bufferInStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_NOT_FULL</span>;
+        <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+    <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+      
+<span id=t_com>//increment counter used to generate USB bit rate</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>i</span> &lt;= <span id=t_cns>5'b00000</span>;
+    <span id=t_idt>fullSpeedTick</span> &lt;= <span id=t_cns>1'b0</span>;
+    <span id=t_idt>lowSpeedTick</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>if</span> (<span id=t_idt>i</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == <span id=t_cns>2'b00</span>)
+      <span id=t_idt>fullSpeedTick</span> &lt;= <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span>
+      <span id=t_idt>fullSpeedTick</span> &lt;= <span id=t_cns>1'b0</span>; 
+    <span id=t_kwd>if</span> (<span id=t_idt>i</span> == <span id=t_cns>5'b00000</span>)
+      <span id=t_idt>lowSpeedTick</span> &lt;= <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span>
+      <span id=t_idt>lowSpeedTick</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//buffer output state machine</span>
+<span id=t_com>//After reset, waits for the output buffer to become full.</span>
+<span id=t_com>//Once the buffer is full then it is constantly emptied at either</span>
+<span id=t_com>//the full or low speed rate with no under run protection</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>TxCtrlOut</span> &lt;= `<span id=t_idt>TRI_STATE</span>;
+    <span id=t_idt>TxDataOutTick</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_FULL</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+    <span id=t_kwd>case</span> (<span id=t_idt>bufferOutStMachCurrState</span>)
+     `<span id=t_idt>WAIT_BUFFER_FULL</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span> == `<span id=t_idt>BUFFER_FULL</span>)
+        <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_LINE_WRITE</span>;
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>WAIT_LINE_WRITE</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> ((<span id=t_idt>fullSpeedRate</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>fullSpeedTick</span> == <span id=t_cns>1'b1</span>) || (<span id=t_idt>fullSpeedRate</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>lowSpeedTick</span> == <span id=t_cns>1'b1</span>) )
+       <span id=t_kwd>begin</span>
+          <span id=t_idt>TxDataOutTick</span> &lt;= !<span id=t_idt>TxDataOutTick</span>;
+        <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>LINE_WRITE</span>;
+        <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_idt>bufferOutIndex</span> + <span id=t_cns>1'b1</span>;
+        <span id=t_kwd>case</span> (<span id=t_idt>bufferOutIndex</span>)
+          <span id=t_cns>2'b00</span> :
+        <span id=t_kwd>begin</span> 
+          <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_idt>buffer0</span>[<span id=t_cns>2</span>:<span id=t_cns>1</span>];
+          <span id=t_idt>TxCtrlOut</span> &lt;= <span id=t_idt>buffer0</span>[<span id=t_cns>0</span>];
+        <span id=t_kwd>end</span>
+        <span id=t_cns>2'b01</span> : 
+        <span id=t_kwd>begin</span>
+          <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_idt>buffer1</span>[<span id=t_cns>2</span>:<span id=t_cns>1</span>];
+          <span id=t_idt>TxCtrlOut</span> &lt;= <span id=t_idt>buffer1</span>[<span id=t_cns>0</span>];
+        <span id=t_kwd>end</span>
+        <span id=t_cns>2'b10</span> : 
+        <span id=t_kwd>begin</span> 
+          <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_idt>buffer2</span>[<span id=t_cns>2</span>:<span id=t_cns>1</span>];
+          <span id=t_idt>TxCtrlOut</span> &lt;= <span id=t_idt>buffer2</span>[<span id=t_cns>0</span>];
+        <span id=t_kwd>end</span>
+        <span id=t_cns>2'b11</span> : 
+        <span id=t_kwd>begin</span>
+          <span id=t_idt>TxBitsOut</span> &lt;= <span id=t_idt>buffer3</span>[<span id=t_cns>2</span>:<span id=t_cns>1</span>];
+          <span id=t_idt>TxCtrlOut</span> &lt;= <span id=t_idt>buffer3</span>[<span id=t_cns>0</span>];
+        <span id=t_kwd>end</span>
+        <span id=t_kwd>endcase</span>
+       <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>LINE_WRITE</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+       <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_LINE_WRITE</span>;
+     <span id=t_kwd>end</span>
+    <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>// control 'disableWireReadOut' </span>
+<span id=t_kwd>always</span> @(<span id=t_idt>TxCtrlOut</span>)
+<span id=t_kwd>begin</span> 
+  <span id=t_kwd>if</span> (<span id=t_idt>TxCtrlOut</span> == `<span id=t_idt>DRIVE</span>)
+   <span id=t_idt>disableWireReadOut</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>disableWireReadOut</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//generate time out flag if no tx activity for (RX_PACKET_TOUT * OVER_SAMPLE_RATE) ticks</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>timeOutCnt</span> &lt;= <span id=t_cns>16'h0000</span>;
+    <span id=t_idt>noActivityTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>TxCtrlOut</span> == `<span id=t_idt>DRIVE</span>)
+      <span id=t_idt>timeOutCnt</span> &lt;= <span id=t_cns>16'h0000</span>;
+    <span id=t_kwd>else</span> 
+      <span id=t_idt>timeOutCnt</span> &lt;= <span id=t_idt>timeOutCnt</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_com>//if (timeOutCnt == `RX_PACKET_TOUT * `OVER_SAMPLE_RATE)</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>timeOutCnt</span> == <span id=t_cns>16'h200</span>)  <span id=t_com>//temporary fix</span>
+      <span id=t_idt>noActivityTimeOut</span> &lt;= <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span>
+      <span id=t_idt>noActivityTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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Added: svn:executable
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+*
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Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm	(revision 264)
@@ -0,0 +1,215 @@
+<html>
+<head>
+<title>usbTxWireArbiter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBWireTxArbiter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:07 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>USBWireTxArbiter</span> (<span id=t_idt>SIETxCtrl</span>, <span id=t_idt>SIETxData</span>, <span id=t_idt>SIETxGnt</span>, <span id=t_idt>SIETxReq</span>, <span id=t_idt>SIETxWEn</span>, <span id=t_idt>TxBits</span>, <span id=t_idt>TxCtl</span>, <span id=t_idt>USBWireRdyIn</span>, <span id=t_idt>USBWireRdyOut</span>, <span id=t_idt>USBWireWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>prcTxByteCtrl</span>, <span id=t_idt>prcTxByteData</span>, <span id=t_idt>prcTxByteGnt</span>, <span id=t_idt>prcTxByteReq</span>, <span id=t_idt>prcTxByteWEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>SIETxCtrl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>SIETxData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIETxReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIETxWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>USBWireRdyIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>prcTxByteCtrl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>prcTxByteData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>prcTxByteReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>prcTxByteWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SIETxGnt</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBits</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>TxCtl</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireRdyOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>prcTxByteGnt</span>;
+
+<span id=t_kwd>wire</span>    <span id=t_idt>SIETxCtrl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>SIETxData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SIETxGnt</span>, <span id=t_idt>next_SIETxGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIETxReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIETxWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBits</span>, <span id=t_idt>next_TxBits</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>TxCtl</span>, <span id=t_idt>next_TxCtl</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>USBWireRdyIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireRdyOut</span>, <span id=t_idt>next_USBWireRdyOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>USBWireWEn</span>, <span id=t_idt>next_USBWireWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>prcTxByteCtrl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>prcTxByteData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>prcTxByteGnt</span>, <span id=t_idt>next_prcTxByteGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>prcTxByteReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>prcTxByteWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>muxSIENotPTXB</span>, <span id=t_idt>next_muxSIENotPTXB</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: txWireArb</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_TARB</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>TARB_WAIT_REQ</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>PTXB_ACT</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>SIE_TX_ACT</span> <span id=t_cns>2'b11</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_txWireArb</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_txWireArb</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// processTxByte/SIETransmitter mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>USBWireRdyIn</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>USBWireRdyOut</span> &lt;= <span id=t_idt>USBWireRdyIn</span>;
+<span id=t_kwd>end</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>muxSIENotPTXB</span> <span id=t_kwd>or</span> <span id=t_idt>SIETxWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SIETxData</span> <span id=t_kwd>or</span>
+<span id=t_idt>SIETxCtrl</span> <span id=t_kwd>or</span> <span id=t_idt>prcTxByteWEn</span> <span id=t_kwd>or</span> <span id=t_idt>prcTxByteData</span> <span id=t_kwd>or</span> <span id=t_idt>prcTxByteCtrl</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>muxSIENotPTXB</span>  == <span id=t_cns>1'b1</span>)
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_idt>SIETxWEn</span>;
+        <span id=t_idt>TxBits</span> &lt;= <span id=t_idt>SIETxData</span>;
+        <span id=t_idt>TxCtl</span> &lt;= <span id=t_idt>SIETxCtrl</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_kwd>else</span>
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>USBWireWEn</span> &lt;= <span id=t_idt>prcTxByteWEn</span>;
+        <span id=t_idt>TxBits</span> &lt;= <span id=t_idt>prcTxByteData</span>;
+        <span id=t_idt>TxCtl</span> &lt;= <span id=t_idt>prcTxByteCtrl</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: txWireArb</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>prcTxByteReq</span> <span id=t_kwd>or</span> <span id=t_idt>SIETxReq</span> <span id=t_kwd>or</span> <span id=t_idt>prcTxByteGnt</span> <span id=t_kwd>or</span> <span id=t_idt>muxSIENotPTXB</span> <span id=t_kwd>or</span> <span id=t_idt>SIETxGnt</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_txWireArb</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>txWireArb_NextState</span>
+  <span id=t_idt>NextState_txWireArb</span> &lt;= <span id=t_idt>CurrState_txWireArb</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_prcTxByteGnt</span> &lt;= <span id=t_idt>prcTxByteGnt</span>;
+  <span id=t_idt>next_muxSIENotPTXB</span> &lt;= <span id=t_idt>muxSIENotPTXB</span>;
+  <span id=t_idt>next_SIETxGnt</span> &lt;= <span id=t_idt>SIETxGnt</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_txWireArb</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_TARB</span>:
+     <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>TARB_WAIT_REQ</span>;
+   `<span id=t_idt>TARB_WAIT_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>prcTxByteReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>PTXB_ACT</span>;
+      <span id=t_idt>next_prcTxByteGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxSIENotPTXB</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>SIETxReq</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>SIE_TX_ACT</span>;
+      <span id=t_idt>next_SIETxGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxSIENotPTXB</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PTXB_ACT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>prcTxByteReq</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>TARB_WAIT_REQ</span>;
+      <span id=t_idt>next_prcTxByteGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SIE_TX_ACT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SIETxReq</span> == <span id=t_cns>1'b0</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_txWireArb</span> &lt;= `<span id=t_idt>TARB_WAIT_REQ</span>;
+      <span id=t_idt>next_SIETxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>txWireArb_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_txWireArb</span> &lt;= `<span id=t_idt>START_TARB</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_txWireArb</span> &lt;= <span id=t_idt>NextState_txWireArb</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>txWireArb_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxSIENotPTXB</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>prcTxByteGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SIETxGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxSIENotPTXB</span> &lt;= <span id=t_idt>next_muxSIENotPTXB</span>;
+   <span id=t_idt>prcTxByteGnt</span> &lt;= <span id=t_idt>next_prcTxByteGnt</span>;
+   <span id=t_idt>SIETxGnt</span> &lt;= <span id=t_idt>next_SIETxGnt</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_HSHAKE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/processRxByte_HSHAKE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar16.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar16.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar16.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(808,925,911,1027,Click18,Over18);
+
+//----------------------------------------------------------------------------
+function Click18(){fubclick('./index18.htm');}
+function Over18(){window.status='Hierarchical State FIRST_BYTE';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 16 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_CHK_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar16.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar24.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar24.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar24.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 24 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./processRxByte_HSHAKE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./processRxByte.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processRxByte.asf/toolbar24.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram874.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram874.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram874.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="processTxByte SEND_BYTE" alt="processTxByte SEND_BYTE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/diagram874.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar887.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram887.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/index887.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte_STOP.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/processTxByte.asf/processTxByte_STOP.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm	(revision 264)
@@ -0,0 +1,210 @@
+<html>
+<head>
+<title>readUSBWireData.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// readUSBWireData.v                                            ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 03:59:39 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>readUSBWireData</span> (<span id=t_idt>RxBitsIn</span>, <span id=t_idt>RxDataInTick</span>, <span id=t_idt>RxBitsOut</span>, <span id=t_idt>SIERxRdyIn</span>, <span id=t_idt>SIERxWEn</span>, <span id=t_idt>fullSpeedRate</span>, <span id=t_idt>disableWireRead</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsIn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RxDataInTick</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIERxRdyIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>disableWireRead</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SIERxWEn</span>;
+
+<span id=t_kwd>wire</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsIn</span>;
+<span id=t_kwd>reg</span>    <span id=t_idt>RxDataInTick</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>SIERxRdyIn</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>wire</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsOut</span>;
+<span id=t_kwd>reg</span>    <span id=t_idt>SIERxWEn</span>;
+
+<span id=t_com>// local registers</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer0</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer1</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer2</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>buffer3</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>2</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferInIndex</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>bufferOutIndex</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>decBufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>4</span>:<span id=t_cns>0</span>]<span id=t_idt>i</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>incBufferCnt</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>oldRxBitsIn</span>;
+
+<span id=t_com>// buffer output state machine state codes:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_BUFFER_NOT_EMPTY</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_SIE_RX_READY</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>SIE_RX_WRITE</span> <span id=t_cns>2'b10</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>bufferOutStMachCurrState</span>;
+
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>bufferCnt</span> &lt;= <span id=t_cns>3'b000</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>incBufferCnt</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>decBufferCnt</span> == <span id=t_cns>1'b0</span>)
+      <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>incBufferCnt</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>decBufferCnt</span> == <span id=t_cns>1'b1</span>)
+      <span id=t_idt>bufferCnt</span> &lt;= <span id=t_idt>bufferCnt</span> - <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+
+<span id=t_com>//Perform line rate clock recovery</span>
+<span id=t_com>//Recover the wire data, and store data to buffer</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+    <span id=t_idt>i</span> &lt;= <span id=t_cns>5'b00000</span>;
+    <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer0</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer1</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer2</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>buffer3</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>RxDataInTick</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;         <span id=t_com>//default value</span>
+    <span id=t_idt>oldRxBitsIn</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+    <span id=t_kwd>if</span> (<span id=t_idt>oldRxBitsIn</span> != <span id=t_idt>RxBitsIn</span>)  <span id=t_com>//if edge detected then</span>
+     <span id=t_idt>i</span> &lt;= <span id=t_cns>5'b00000</span>;              <span id=t_com>//reset the counter</span>
+    <span id=t_kwd>else</span>
+     <span id=t_idt>i</span> &lt;= <span id=t_idt>i</span> + <span id=t_cns>1'b1</span>;
+    <span id=t_kwd>if</span> ( (<span id=t_idt>fullSpeedRate</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>i</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == <span id=t_cns>2'b10</span>) || (<span id=t_idt>fullSpeedRate</span> == <span id=t_cns>1'b0</span> &amp;&amp; <span id=t_idt>i</span> == <span id=t_cns>5'b10000</span>) )
+    <span id=t_kwd>begin</span>
+      <span id=t_idt>RxDataInTick</span> &lt;= !<span id=t_idt>RxDataInTick</span>;
+      <span id=t_kwd>if</span> (<span id=t_idt>disableWireRead</span> != <span id=t_cns>1'b1</span>)  <span id=t_com>//do not read wire data when transmitter is active</span>
+      <span id=t_kwd>begin</span>
+        <span id=t_idt>incBufferCnt</span> &lt;= <span id=t_cns>1'b1</span>;
+       <span id=t_idt>bufferInIndex</span> &lt;= <span id=t_idt>bufferInIndex</span> + <span id=t_cns>1'b1</span>;
+       <span id=t_kwd>case</span> (<span id=t_idt>bufferInIndex</span>)
+         <span id=t_cns>2'b00</span> : <span id=t_idt>buffer0</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+         <span id=t_cns>2'b01</span> : <span id=t_idt>buffer1</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+         <span id=t_cns>2'b10</span> : <span id=t_idt>buffer2</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+         <span id=t_cns>2'b11</span> : <span id=t_idt>buffer3</span> &lt;= <span id=t_idt>RxBitsIn</span>;
+       <span id=t_kwd>endcase</span>
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+      
+
+<span id=t_com>//read from buffer, and output to SIEReceiver</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>) <span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>SIERxWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_NOT_EMPTY</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>case</span> (<span id=t_idt>bufferOutStMachCurrState</span>)
+     `<span id=t_idt>WAIT_BUFFER_NOT_EMPTY</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>bufferCnt</span> != <span id=t_cns>3'b000</span>)
+        <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_SIE_RX_READY</span>;
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>WAIT_SIE_RX_READY</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_kwd>if</span> (<span id=t_idt>SIERxRdyIn</span> == <span id=t_cns>1'b1</span>)
+       <span id=t_kwd>begin</span> 
+        <span id=t_idt>SIERxWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>SIE_RX_WRITE</span>;
+        <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b1</span>;
+        <span id=t_idt>bufferOutIndex</span> &lt;= <span id=t_idt>bufferOutIndex</span> + <span id=t_cns>1'b1</span>;
+        <span id=t_kwd>case</span> (<span id=t_idt>bufferOutIndex</span>)
+           <span id=t_cns>2'b00</span> :  <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>buffer0</span>;
+          <span id=t_cns>2'b01</span> : <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>buffer1</span>;
+          <span id=t_cns>2'b10</span> : <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>buffer2</span>;
+          <span id=t_cns>2'b11</span> : <span id=t_idt>RxBitsOut</span> &lt;= <span id=t_idt>buffer3</span>;
+        <span id=t_kwd>endcase</span>
+       <span id=t_kwd>end</span>
+     <span id=t_kwd>end</span>
+     `<span id=t_idt>SIE_RX_WRITE</span>:
+     <span id=t_kwd>begin</span>
+       <span id=t_idt>SIERxWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+       <span id=t_idt>decBufferCnt</span> &lt;= <span id=t_cns>1'b0</span>;
+       <span id=t_idt>bufferOutStMachCurrState</span> &lt;= `<span id=t_idt>WAIT_BUFFER_NOT_EMPTY</span>;
+     <span id=t_kwd>end</span>
+    <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+     
+
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/readUSBWireData.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver WAIT_LS_CONN" alt="siereceiver WAIT_LS_CONN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram55.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram91.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram91.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram91.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="siereceiver WAIT_FS_DIS" alt="siereceiver WAIT_FS_DIS"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/diagram91.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar55.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram55.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index55.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar91.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram91.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/index91.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_FS_CONN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_FS_CONN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_LS_CONN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/siereceiver_WAIT_LS_CONN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar46.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar46.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar46.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 46 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_WAIT_FS_CONN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar46.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 82 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./siereceiver_WAIT_LS_DIS.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./siereceiver.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/siereceiver.asf/toolbar82.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm	(revision 264)
@@ -0,0 +1,388 @@
+<html>
+<head>
+<title>usbSerialInterfaceEngine.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbSerialInterfaceEngine.v                                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:05 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>usbSerialInterfaceEngine</span>(
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_com>//readUSBWireData</span>
+  <span id=t_idt>USBWireDataIn</span>,
+  <span id=t_idt>USBWireDataInTick</span>,
+  <span id=t_com>//writeUSBWireData</span>
+  <span id=t_idt>USBWireDataOut</span>,
+  <span id=t_idt>USBWireCtrlOut</span>,
+  <span id=t_idt>USBWireDataOutTick</span>,
+  <span id=t_com>//SIEReceiver</span>
+  <span id=t_idt>connectState</span>,
+  <span id=t_com>//processRxBit</span>
+  <span id=t_idt>resumeDetected</span>,
+  <span id=t_com>//processRxByte</span>
+  <span id=t_idt>RxCtrlOut</span>, 
+  <span id=t_idt>RxDataOutWEn</span>, 
+  <span id=t_idt>RxDataOut</span>, 
+    <span id=t_com>//SIETransmitter</span>
+  <span id=t_idt>SIEPortCtrlIn</span>,
+  <span id=t_idt>SIEPortDataIn</span>, 
+  <span id=t_idt>SIEPortTxRdy</span>, 
+  <span id=t_idt>SIEPortWEn</span>, 
+    <span id=t_com>//lineControlUpdate</span>
+  <span id=t_idt>fullSpeedPolarity</span>,
+  <span id=t_idt>fullSpeedBitRate</span>,
+  <span id=t_idt>noActivityTimeOut</span>
+);
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>, <span id=t_idt>rst</span>;
+<span id=t_com>//readUSBWireData</span>
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireDataInTick</span>;
+
+<span id=t_com>//writeUSBWireData</span>
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireCtrlOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>noActivityTimeOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireDataOutTick</span>;
+
+<span id=t_com>//SIEReceiver</span>
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>;
+<span id=t_com>//processRxBit</span>
+<span id=t_kwd>output</span> <span id=t_idt>resumeDetected</span>;
+<span id=t_com>//processRxByte</span>
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>RxDataOutWEn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>; 
+<span id=t_com>//SIETransmitter</span>
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlIn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataIn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SIEPortTxRdy</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>SIEPortWEn</span>;
+<span id=t_com>//lineControlUpdate</span>
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>input</span> <span id=t_idt>fullSpeedBitRate</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>, <span id=t_idt>rst</span>;
+<span id=t_com>//readUSBWireData</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataInTick</span>;
+<span id=t_com>//writeUSBWireData</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireCtrlOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>noActivityTimeOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataOutTick</span>;
+<span id=t_com>//SIEReceiver</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>;
+<span id=t_com>//processRxBit</span>
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetected</span>;
+<span id=t_com>//processRxByte</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RxDataOutWEn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataOut</span>; 
+<span id=t_com>//SIETransmitter</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortTxRdy</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEn</span>;
+<span id=t_com>//lineControlUpdate</span>
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarity</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRate</span>;
+
+<span id=t_com>//internal wiring</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxBitsFromSIERxToPrRxBit</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>processRxBitsWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>processRxBitRdy</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>RxWireDataFromWireRxToSIERx</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxWireDataWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIERxRdyOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>disableWireRead</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxBitsFromArbToWire</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxCtrlFromArbToWire</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireReadyFromTxArb</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>prcTxByteCtrl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>prcTxByteData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>prcTxByteGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>prcTxByteReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>prcTxByteWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIETxCtrl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>SIETxData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIETxGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIETxReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIETxWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxByteFromSIEToPrcTxByte</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxCtrlFromSIEToPrcTxByte</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>JBit</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>KBit</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>processRxByteWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataFromPrcRxBitToPrcRxByte</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlFromPrcRxBitToPrcRxByte</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>processRxByteRdy</span>;
+<span id=t_com>//Rx CRC</span>
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC16En</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCRC16Result</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC16UpdateRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC5En</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCRC5Result</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC5_8Bit</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCRCData</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RxRstCRC</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxCRC5UpdateRdy</span>;
+<span id=t_com>//Tx CRC</span>
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC16En</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>15</span>:<span id=t_cns>0</span>] <span id=t_idt>TxCRC16Result</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC16UpdateRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC5En</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>TxCRC5Result</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC5_8Bit</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxCRCData</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>TxRstCRC</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>TxCRC5UpdateRdy</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>processTxByteRdy</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>processTxByteWEn</span>; 
+
+<span id=t_idt>lineControlUpdate</span> <span id=t_idt>u_lineControlUpdate</span>
+  (.<span id=t_idt>fullSpeedPolarity</span>(<span id=t_idt>fullSpeedPolarity</span>),
+  .<span id=t_idt>fullSpeedBitRate</span>(<span id=t_idt>fullSpeedBitRate</span>),
+  .<span id=t_idt>JBit</span>(<span id=t_idt>JBit</span>),
+  .<span id=t_idt>KBit</span>(<span id=t_idt>KBit</span>) );
+
+<span id=t_idt>SIEReceiver</span> <span id=t_idt>u_SIEReceiver</span>
+  (.<span id=t_idt>RxBitsOut</span>(<span id=t_idt>RxBitsFromSIERxToPrRxBit</span>),
+  .<span id=t_idt>RxWireDataIn</span>(<span id=t_idt>RxWireDataFromWireRxToSIERx</span>), 
+  .<span id=t_idt>RxWireDataWEn</span>(<span id=t_idt>RxWireDataWEn</span>), 
+  .<span id=t_idt>SIERxRdyOut</span>(<span id=t_idt>SIERxRdyOut</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>connectState</span>(<span id=t_idt>connectState</span>),
+  .<span id=t_idt>processRxBitRdyIn</span>(<span id=t_idt>processRxBitRdy</span>), 
+  .<span id=t_idt>processRxBitsWEn</span>(<span id=t_idt>processRxBitsWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) );
+  
+<span id=t_idt>processRxBit</span> <span id=t_idt>u_processRxBit</span>
+  (.<span id=t_idt>JBit</span>(<span id=t_idt>JBit</span>), 
+  .<span id=t_idt>KBit</span>(<span id=t_idt>KBit</span>), 
+  .<span id=t_idt>RxBitsIn</span>(<span id=t_idt>RxBitsFromSIERxToPrRxBit</span>), 
+  .<span id=t_idt>RxCtrlOut</span>(<span id=t_idt>RxCtrlFromPrcRxBitToPrcRxByte</span>), 
+  .<span id=t_idt>RxDataOut</span>(<span id=t_idt>RxDataFromPrcRxBitToPrcRxByte</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>processRxBitRdy</span>(<span id=t_idt>processRxBitRdy</span>), 
+  .<span id=t_idt>processRxBitsWEn</span>(<span id=t_idt>processRxBitsWEn</span>), 
+  .<span id=t_idt>processRxByteWEn</span>(<span id=t_idt>processRxByteWEn</span>), 
+  .<span id=t_idt>resumeDetected</span>(<span id=t_idt>resumeDetected</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>processRxByteRdy</span>(<span id=t_idt>processRxByteRdy</span>) );
+  
+<span id=t_idt>processRxByte</span> <span id=t_idt>u_processRxByte</span>
+  (.<span id=t_idt>CRC16En</span>(<span id=t_idt>RxCRC16En</span>), 
+  .<span id=t_idt>CRC16Result</span>(<span id=t_idt>RxCRC16Result</span>), 
+  .<span id=t_idt>CRC16UpdateRdy</span>(<span id=t_idt>RxCRC16UpdateRdy</span>),
+  .<span id=t_idt>CRC5En</span>(<span id=t_idt>RxCRC5En</span>), 
+  .<span id=t_idt>CRC5Result</span>(<span id=t_idt>RxCRC5Result</span>), 
+  .<span id=t_idt>CRC5_8Bit</span>(<span id=t_idt>RxCRC5_8Bit</span>),
+  .<span id=t_idt>CRC5UpdateRdy</span>(<span id=t_idt>RxCRC5UpdateRdy</span>),
+  .<span id=t_idt>CRCData</span>(<span id=t_idt>RxCRCData</span>), 
+  .<span id=t_idt>RxByteIn</span>(<span id=t_idt>RxDataFromPrcRxBitToPrcRxByte</span>), 
+  .<span id=t_idt>RxCtrlIn</span>(<span id=t_idt>RxCtrlFromPrcRxBitToPrcRxByte</span>), 
+  .<span id=t_idt>RxCtrlOut</span>(<span id=t_idt>RxCtrlOut</span>), 
+  .<span id=t_idt>RxDataOutWEn</span>(<span id=t_idt>RxDataOutWEn</span>), 
+  .<span id=t_idt>RxDataOut</span>(<span id=t_idt>RxDataOut</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>processRxDataInWEn</span>(<span id=t_idt>processRxByteWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>rstCRC</span>(<span id=t_idt>RxRstCRC</span>),
+  .<span id=t_idt>processRxByteRdy</span>(<span id=t_idt>processRxByteRdy</span>) ); 
+  
+  
+<span id=t_idt>updateCRC5</span> <span id=t_idt>RxUpdateCRC5</span>
+  (.<span id=t_idt>rstCRC</span>(<span id=t_idt>RxRstCRC</span>), 
+  .<span id=t_idt>CRCResult</span>(<span id=t_idt>RxCRC5Result</span>), 
+  .<span id=t_idt>CRCEn</span>(<span id=t_idt>RxCRC5En</span>), 
+  .<span id=t_idt>CRC5_8BitIn</span>(<span id=t_idt>RxCRC5_8Bit</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>RxCRCData</span>), 
+  .<span id=t_idt>ready</span>(<span id=t_idt>RxCRC5UpdateRdy</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) );  
+  
+<span id=t_idt>updateCRC16</span> <span id=t_idt>RxUpdateCRC16</span>
+  (.<span id=t_idt>rstCRC</span>(<span id=t_idt>RxRstCRC</span>), 
+  .<span id=t_idt>CRCResult</span>(<span id=t_idt>RxCRC16Result</span>), 
+  .<span id=t_idt>CRCEn</span>(<span id=t_idt>RxCRC16En</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>RxCRCData</span>), 
+  .<span id=t_idt>ready</span>(<span id=t_idt>RxCRC16UpdateRdy</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+  
+<span id=t_idt>SIETransmitter</span> <span id=t_idt>u_SIETransmitter</span>
+  (.<span id=t_idt>CRC16En</span>(<span id=t_idt>TxCRC16En</span>), 
+  .<span id=t_idt>CRC16Result</span>(<span id=t_idt>TxCRC16Result</span>), 
+  .<span id=t_idt>CRC5En</span>(<span id=t_idt>TxCRC5En</span>), 
+  .<span id=t_idt>CRC5Result</span>(<span id=t_idt>TxCRC5Result</span>), 
+  .<span id=t_idt>CRC5_8Bit</span>(<span id=t_idt>TxCRC5_8Bit</span>), 
+  .<span id=t_idt>CRCData</span>(<span id=t_idt>TxCRCData</span>),
+  .<span id=t_idt>CRC5UpdateRdy</span>(<span id=t_idt>TxCRC5UpdateRdy</span>),
+  .<span id=t_idt>CRC16UpdateRdy</span>(<span id=t_idt>TxCRC16UpdateRdy</span>),
+  .<span id=t_idt>JBit</span>(<span id=t_idt>JBit</span>), 
+  .<span id=t_idt>KBit</span>(<span id=t_idt>KBit</span>), 
+  .<span id=t_idt>SIEPortCtrlIn</span>(<span id=t_idt>SIEPortCtrlIn</span>),
+  .<span id=t_idt>SIEPortDataIn</span>(<span id=t_idt>SIEPortDataIn</span>), 
+  .<span id=t_idt>SIEPortTxRdy</span>(<span id=t_idt>SIEPortTxRdy</span>), 
+  .<span id=t_idt>SIEPortWEn</span>(<span id=t_idt>SIEPortWEn</span>), 
+  .<span id=t_idt>TxByteOutCtrl</span>(<span id=t_idt>TxCtrlFromSIEToPrcTxByte</span>), 
+  .<span id=t_idt>TxByteOut</span>(<span id=t_idt>TxByteFromSIEToPrcTxByte</span>), 
+  .<span id=t_idt>USBWireCtrl</span>(<span id=t_idt>SIETxCtrl</span>), 
+  .<span id=t_idt>USBWireData</span>(<span id=t_idt>SIETxData</span>), 
+  .<span id=t_idt>USBWireGnt</span>(<span id=t_idt>SIETxGnt</span>), 
+  .<span id=t_idt>USBWireRdy</span>(<span id=t_idt>USBWireReadyFromTxArb</span>), 
+  .<span id=t_idt>USBWireReq</span>(<span id=t_idt>SIETxReq</span>), 
+  .<span id=t_idt>USBWireWEn</span>(<span id=t_idt>SIETxWEn</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>processTxByteRdy</span>(<span id=t_idt>processTxByteRdy</span>), 
+  .<span id=t_idt>processTxByteWEn</span>(<span id=t_idt>processTxByteWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>rstCRC</span>(<span id=t_idt>TxRstCRC</span>) );   
+
+<span id=t_idt>updateCRC5</span> <span id=t_idt>TxUpdateCRC5</span>
+  (.<span id=t_idt>rstCRC</span>(<span id=t_idt>TxRstCRC</span>), 
+  .<span id=t_idt>CRCResult</span>(<span id=t_idt>TxCRC5Result</span>), 
+  .<span id=t_idt>CRCEn</span>(<span id=t_idt>TxCRC5En</span>), 
+  .<span id=t_idt>CRC5_8BitIn</span>(<span id=t_idt>TxCRC5_8Bit</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>TxCRCData</span>),
+  .<span id=t_idt>ready</span>(<span id=t_idt>TxCRC5UpdateRdy</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) );  
+  
+<span id=t_idt>updateCRC16</span> <span id=t_idt>TxUpdateCRC16</span>
+  (.<span id=t_idt>rstCRC</span>(<span id=t_idt>TxRstCRC</span>), 
+  .<span id=t_idt>CRCResult</span>(<span id=t_idt>TxCRC16Result</span>), 
+  .<span id=t_idt>CRCEn</span>(<span id=t_idt>TxCRC16En</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>TxCRCData</span>), 
+  .<span id=t_idt>ready</span>(<span id=t_idt>TxCRC16UpdateRdy</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>processTxByte</span> <span id=t_idt>u_processTxByte</span>
+  (.<span id=t_idt>JBit</span>(<span id=t_idt>JBit</span>), 
+  .<span id=t_idt>KBit</span>(<span id=t_idt>KBit</span>), 
+  .<span id=t_idt>TxByteCtrlIn</span>(<span id=t_idt>TxCtrlFromSIEToPrcTxByte</span>), 
+  .<span id=t_idt>TxByteIn</span>(<span id=t_idt>TxByteFromSIEToPrcTxByte</span>), 
+  .<span id=t_idt>USBWireCtrl</span>(<span id=t_idt>prcTxByteCtrl</span>), 
+  .<span id=t_idt>USBWireData</span>(<span id=t_idt>prcTxByteData</span>), 
+  .<span id=t_idt>USBWireGnt</span>(<span id=t_idt>prcTxByteGnt</span>), 
+  .<span id=t_idt>USBWireRdy</span>(<span id=t_idt>USBWireReadyFromTxArb</span>), 
+  .<span id=t_idt>USBWireReq</span>(<span id=t_idt>prcTxByteReq</span>), 
+  .<span id=t_idt>USBWireWEn</span>(<span id=t_idt>prcTxByteWEn</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>processTxByteRdy</span>(<span id=t_idt>processTxByteRdy</span>), 
+  .<span id=t_idt>processTxByteWEn</span>(<span id=t_idt>processTxByteWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+  
+<span id=t_idt>USBWireTxArbiter</span> <span id=t_idt>u_USBWireTxArbiter</span>
+  (.<span id=t_idt>SIETxCtrl</span>(<span id=t_idt>SIETxCtrl</span>), 
+  .<span id=t_idt>SIETxData</span>(<span id=t_idt>SIETxData</span>), 
+  .<span id=t_idt>SIETxGnt</span>(<span id=t_idt>SIETxGnt</span>), 
+  .<span id=t_idt>SIETxReq</span>(<span id=t_idt>SIETxReq</span>), 
+  .<span id=t_idt>SIETxWEn</span>(<span id=t_idt>SIETxWEn</span>), 
+  .<span id=t_idt>TxBits</span>(<span id=t_idt>TxBitsFromArbToWire</span>), 
+  .<span id=t_idt>TxCtl</span>(<span id=t_idt>TxCtrlFromArbToWire</span>), 
+  .<span id=t_idt>USBWireRdyIn</span>(<span id=t_idt>USBWireRdy</span>), 
+  .<span id=t_idt>USBWireRdyOut</span>(<span id=t_idt>USBWireReadyFromTxArb</span>), 
+  .<span id=t_idt>USBWireWEn</span>(<span id=t_idt>USBWireWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>prcTxByteCtrl</span>(<span id=t_idt>prcTxByteCtrl</span>), 
+  .<span id=t_idt>prcTxByteData</span>(<span id=t_idt>prcTxByteData</span>), 
+  .<span id=t_idt>prcTxByteGnt</span>(<span id=t_idt>prcTxByteGnt</span>), 
+  .<span id=t_idt>prcTxByteReq</span>(<span id=t_idt>prcTxByteReq</span>), 
+  .<span id=t_idt>prcTxByteWEn</span>(<span id=t_idt>prcTxByteWEn</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+  
+<span id=t_idt>writeUSBWireData</span> <span id=t_idt>u_writeUSBWireData</span>
+  (.<span id=t_idt>TxBitsIn</span>(<span id=t_idt>TxBitsFromArbToWire</span>), 
+  .<span id=t_idt>TxBitsOut</span>(<span id=t_idt>USBWireDataOut</span>), 
+  .<span id=t_idt>TxDataOutTick</span>(<span id=t_idt>USBWireDataOutTick</span>),
+  .<span id=t_idt>TxCtrlIn</span>(<span id=t_idt>TxCtrlFromArbToWire</span>), 
+  .<span id=t_idt>TxCtrlOut</span>(<span id=t_idt>USBWireCtrlOut</span>), 
+  .<span id=t_idt>USBWireRdy</span>(<span id=t_idt>USBWireRdy</span>), 
+  .<span id=t_idt>USBWireWEn</span>(<span id=t_idt>USBWireWEn</span>),
+  .<span id=t_idt>disableWireReadOut</span>(<span id=t_idt>disableWireRead</span>),
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedBitRate</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>noActivityTimeOut</span>(<span id=t_idt>noActivityTimeOut</span>) );  
+  
+<span id=t_idt>readUSBWireData</span> <span id=t_idt>u_readUSBWireData</span>
+  (.<span id=t_idt>RxBitsIn</span>(<span id=t_idt>USBWireDataIn</span>), 
+  .<span id=t_idt>RxDataInTick</span>(<span id=t_idt>USBWireDataInTick</span>),
+  .<span id=t_idt>RxBitsOut</span>(<span id=t_idt>RxWireDataFromWireRxToSIERx</span>), 
+  .<span id=t_idt>SIERxRdyIn</span>(<span id=t_idt>SIERxRdyOut</span>), 
+  .<span id=t_idt>SIERxWEn</span>(<span id=t_idt>RxWireDataWEn</span>), 
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedBitRate</span>), 
+  .<span id=t_idt>disableWireRead</span>(<span id=t_idt>disableWireRead</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) );
+
+
+<span id=t_kwd>endmodule</span>
+
+  
+  
+
+
+
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbSerialInterfaceEngine.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm	(revision 264)
@@ -0,0 +1,406 @@
+<html>
+<head>
+<title>USBSlaveControlBI.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// USBSlaveControlBI.v                                          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:43 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbSlaveControl_h.v"</span>
+ 
+<span id=t_kwd>module</span> <span id=t_idt>USBSlaveControlBI</span> (<span id=t_idt>address</span>, <span id=t_idt>dataIn</span>, <span id=t_idt>dataOut</span>, <span id=t_idt>writeEn</span>,
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_idt>SOFRxedIntOut</span>, <span id=t_idt>resetEventIntOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>transDoneIntOut</span>, <span id=t_idt>NAKSentIntOut</span>,
+  <span id=t_idt>endP0TransTypeReg</span>, <span id=t_idt>endP0NAKTransTypeReg</span>,
+  <span id=t_idt>endP1TransTypeReg</span>, <span id=t_idt>endP1NAKTransTypeReg</span>,
+  <span id=t_idt>endP2TransTypeReg</span>, <span id=t_idt>endP2NAKTransTypeReg</span>,
+  <span id=t_idt>endP3TransTypeReg</span>, <span id=t_idt>endP3NAKTransTypeReg</span>,
+  <span id=t_idt>endP0ControlReg</span>,
+  <span id=t_idt>endP1ControlReg</span>,
+  <span id=t_idt>endP2ControlReg</span>,
+  <span id=t_idt>endP3ControlReg</span>,
+  <span id=t_idt>EP0StatusReg</span>,
+  <span id=t_idt>EP1StatusReg</span>,
+  <span id=t_idt>EP2StatusReg</span>,
+  <span id=t_idt>EP3StatusReg</span>,
+  <span id=t_idt>SCAddrReg</span>, <span id=t_idt>frameNum</span>,
+  <span id=t_idt>connectStateIn</span>,
+  <span id=t_idt>SOFRxedIn</span>, <span id=t_idt>resetEventIn</span>, <span id=t_idt>resumeIntIn</span>, <span id=t_idt>transDoneIn</span>, <span id=t_idt>NAKSentIn</span>,
+  <span id=t_idt>slaveControlSelect</span>,
+  <span id=t_idt>clrEP0Ready</span>, <span id=t_idt>clrEP1Ready</span>, <span id=t_idt>clrEP2Ready</span>, <span id=t_idt>clrEP3Ready</span>,
+  <span id=t_idt>TxLineState</span>,
+  <span id=t_idt>LineDirectControlEn</span>,
+  <span id=t_idt>fullSpeedPol</span>, 
+  <span id=t_idt>fullSpeedRate</span>,
+  <span id=t_idt>SCGlobalEn</span>
+  );
+<span id=t_kwd>input</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFRxedIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resetEventIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>NAKSentIntOut</span>;
+
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP0StatusReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP1StatusReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP2StatusReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP3StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>SCAddrReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SOFRxedIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resetEventIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>NAKSentIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>slaveControlSelect</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEP0Ready</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEP1Ready</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEP2Ready</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEP3Ready</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>output</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SCGlobalEn</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>address</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataOut</span>;
+
+<span id=t_kwd>reg</span> <span id=t_idt>SOFRxedIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resetEventIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>NAKSentIntOut</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP0StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP1StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP2StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>EP3StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>SCAddrReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>TxEndPReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>SOFRxedIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resetEventIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>NAKSentIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP0Ready</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP1Ready</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP2Ready</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP3Ready</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>TxLineState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>LineDirectControlEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedPol</span>; 
+<span id=t_kwd>reg</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SCGlobalEn</span>;
+
+<span id=t_com>//internal wire and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>5</span>:<span id=t_cns>0</span>] <span id=t_idt>SCControlReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrNAKReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrSOFReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResetReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrResInReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrTransDoneReq</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>SOFRxedInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resetEventInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>transDoneInt</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>NAKSentInt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>interruptMaskReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0SetReady</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1SetReady</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2SetReady</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3SetReady</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0SendStall</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1SendStall</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2SendStall</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3SendStall</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0DataSequence</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1DataSequence</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2DataSequence</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3DataSequence</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0Enable</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1Enable</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2Enable</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3Enable</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP0Ready</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP1Ready</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP2Ready</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>EP3Ready</span>;
+
+
+<span id=t_com>//sync write demux</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>clrNAKReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResetReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrResInReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>EP0SetReady</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>EP1SetReady</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>EP2SetReady</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_idt>EP3SetReady</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>if</span> (<span id=t_idt>writeEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>strobe_i</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>slaveControlSelect</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+      `<span id=t_idt>EP0_CTRL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>EP0SendStall</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>EP0DataSequence</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>EP0SetReady</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>EP0Enable</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+      `<span id=t_idt>EP1_CTRL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>EP1SendStall</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>EP1DataSequence</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>EP1SetReady</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>EP1Enable</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+      `<span id=t_idt>EP2_CTRL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>EP2SendStall</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>EP2DataSequence</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>EP2SetReady</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>EP2Enable</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+      `<span id=t_idt>EP3_CTRL_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>EP3SendStall</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>EP3DataSequence</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>EP3SetReady</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>EP3Enable</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>SC_CONTROL_REG</span> : <span id=t_idt>SCControlReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>5</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>SC_ADDRESS</span> : <span id=t_idt>SCAddrReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+     `<span id=t_idt>SC_INTERRUPT_STATUS_REG</span> : <span id=t_kwd>begin</span>
+        <span id=t_idt>clrNAKReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>];
+        <span id=t_idt>clrSOFReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>3</span>];
+        <span id=t_idt>clrResetReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>2</span>];
+        <span id=t_idt>clrResInReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>1</span>];
+        <span id=t_idt>clrTransDoneReq</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>0</span>];
+      <span id=t_kwd>end</span>
+     `<span id=t_idt>SC_INTERRUPT_MASK_REG</span> : <span id=t_idt>interruptMaskReg</span> &lt;= <span id=t_idt>dataIn</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>];
+   <span id=t_kwd>endcase</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//interrupt control </span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>NAKSentIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>NAKSentInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrNAKReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>NAKSentInt</span> &lt;= <span id=t_cns>1'b0</span>; 
+    
+  <span id=t_kwd>if</span> (<span id=t_idt>SOFRxedIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFRxedInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrSOFReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>SOFRxedInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resetEventIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resetEventInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResetReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resetEventInt</span> &lt;= <span id=t_cns>1'b0</span>;
+   
+  <span id=t_kwd>if</span> (<span id=t_idt>resumeIntIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrResInReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>resumeInt</span> &lt;= <span id=t_cns>1'b0</span>;  
+
+  <span id=t_kwd>if</span> (<span id=t_idt>transDoneIn</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrTransDoneReq</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>transDoneInt</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//mask interrupts</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>resetEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFRxedInt</span> <span id=t_kwd>or</span> <span id=t_idt>NAKSentInt</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>transDoneIntOut</span> &lt;= <span id=t_idt>transDoneInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>TRANS_DONE_BIT</span>];
+  <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_idt>resumeInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESUME_INT_BIT</span>];
+  <span id=t_idt>resetEventIntOut</span> &lt;= <span id=t_idt>resetEventInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>RESET_EVENT_BIT</span>];
+  <span id=t_idt>SOFRxedIntOut</span> &lt;= <span id=t_idt>SOFRxedInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>SOF_RECEIVED_BIT</span>];
+  <span id=t_idt>NAKSentIntOut</span> &lt;= <span id=t_idt>NAKSentInt</span> &amp; <span id=t_idt>interruptMaskReg</span>[`<span id=t_idt>NAK_SENT_INT_BIT</span>];
+<span id=t_kwd>end</span>  
+
+<span id=t_com>//end point ready, set/clear</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>EP0SetReady</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP0Ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrEP0Ready</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP0Ready</span> &lt;= <span id=t_cns>1'b0</span>;
+    
+  <span id=t_kwd>if</span> (<span id=t_idt>EP1SetReady</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP1Ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrEP1Ready</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP1Ready</span> &lt;= <span id=t_cns>1'b0</span>;
+    
+  <span id=t_kwd>if</span> (<span id=t_idt>EP2SetReady</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP2Ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrEP2Ready</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP2Ready</span> &lt;= <span id=t_cns>1'b0</span>;
+    
+  <span id=t_kwd>if</span> (<span id=t_idt>EP3SetReady</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP3Ready</span> &lt;= <span id=t_cns>1'b1</span>;
+  <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>clrEP3Ready</span> == <span id=t_cns>1'b1</span>)
+   <span id=t_idt>EP3Ready</span> &lt;= <span id=t_cns>1'b0</span>;
+<span id=t_kwd>end</span>  
+  
+<span id=t_com>//break out control signals</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>SCControlReg</span>) <span id=t_kwd>begin</span>
+  <span id=t_idt>SCGlobalEn</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_GLOBAL_ENABLE_BIT</span>];
+  <span id=t_idt>TxLineState</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_TX_LINE_STATE_MSBIT</span>:`<span id=t_idt>SC_TX_LINE_STATE_LSBIT</span>];
+  <span id=t_idt>LineDirectControlEn</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_DIRECT_CONTROL_BIT</span>];
+  <span id=t_idt>fullSpeedPol</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_FULL_SPEED_LINE_POLARITY_BIT</span>]; 
+  <span id=t_idt>fullSpeedRate</span> &lt;= <span id=t_idt>SCControlReg</span>[`<span id=t_idt>SC_FULL_SPEED_LINE_RATE_BIT</span>];
+<span id=t_kwd>end</span>
+
+<span id=t_com>//combine endpoint control signals </span>
+<span id=t_kwd>always</span> @(<span id=t_idt>EP0SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP0Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP0DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP0Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP1SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP1Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP1DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP1Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP2SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP2Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP2DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP2Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP3SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP3Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP3DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP3Enable</span>) 
+<span id=t_kwd>begin</span>
+  <span id=t_idt>endP0ControlReg</span> &lt;= {<span id=t_idt>EP0SendStall</span>, <span id=t_idt>EP0DataSequence</span>, <span id=t_idt>EP0Ready</span>, <span id=t_idt>EP0Enable</span>};
+  <span id=t_idt>endP1ControlReg</span> &lt;= {<span id=t_idt>EP1SendStall</span>, <span id=t_idt>EP1DataSequence</span>, <span id=t_idt>EP1Ready</span>, <span id=t_idt>EP1Enable</span>};
+  <span id=t_idt>endP2ControlReg</span> &lt;= {<span id=t_idt>EP2SendStall</span>, <span id=t_idt>EP2DataSequence</span>, <span id=t_idt>EP2Ready</span>, <span id=t_idt>EP2Enable</span>};
+  <span id=t_idt>endP3ControlReg</span> &lt;= {<span id=t_idt>EP3SendStall</span>, <span id=t_idt>EP3DataSequence</span>, <span id=t_idt>EP3Ready</span>, <span id=t_idt>EP3Enable</span>};
+<span id=t_kwd>end</span>
+      
+      
+      <span id=t_com>// async read mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>address</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP0SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP0Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP0DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP0Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP1SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP1Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP1DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP1Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP2SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP2Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP2DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP2Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP3SendStall</span> <span id=t_kwd>or</span> <span id=t_idt>EP3Ready</span> <span id=t_kwd>or</span> <span id=t_idt>EP3DataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>EP3Enable</span> <span id=t_kwd>or</span>
+  <span id=t_idt>EP0StatusReg</span> <span id=t_kwd>or</span> <span id=t_idt>EP1StatusReg</span> <span id=t_kwd>or</span> <span id=t_idt>EP2StatusReg</span> <span id=t_kwd>or</span> <span id=t_idt>EP3StatusReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>endP0ControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP1ControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP2ControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP3ControlReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>endP0NAKTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP1NAKTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP2NAKTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP3NAKTransTypeReg</span> <span id=t_kwd>or</span> 
+  <span id=t_idt>endP0TransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP1TransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP2TransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endP3TransTypeReg</span> <span id=t_kwd>or</span>
+  <span id=t_idt>SCControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>connectStateIn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>NAKSentInt</span> <span id=t_kwd>or</span> <span id=t_idt>SOFRxedInt</span> <span id=t_kwd>or</span> <span id=t_idt>resetEventInt</span> <span id=t_kwd>or</span> <span id=t_idt>resumeInt</span> <span id=t_kwd>or</span> <span id=t_idt>transDoneInt</span> <span id=t_kwd>or</span>
+  <span id=t_idt>interruptMaskReg</span> <span id=t_kwd>or</span> <span id=t_idt>SCAddrReg</span> <span id=t_kwd>or</span> <span id=t_idt>frameNum</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>address</span>)
+      `<span id=t_idt>EP0_CTRL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP0ControlReg</span>;
+      `<span id=t_idt>EP0_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>EP0StatusReg</span>;
+      `<span id=t_idt>EP0_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP0TransTypeReg</span>;
+      `<span id=t_idt>EP0_NAK_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP0NAKTransTypeReg</span>;
+      `<span id=t_idt>EP1_CTRL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP1ControlReg</span>;
+      `<span id=t_idt>EP1_STS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>EP1StatusReg</span>;
+      `<span id=t_idt>EP1_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP1TransTypeReg</span>;
+      `<span id=t_idt>EP1_NAK_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP1NAKTransTypeReg</span>;
+      `<span id=t_idt>EP2_CTRL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP2ControlReg</span>;
+      `<span id=t_idt>EP2_STS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>EP2StatusReg</span>;
+      `<span id=t_idt>EP2_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP2TransTypeReg</span>;
+      `<span id=t_idt>EP2_NAK_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP2NAKTransTypeReg</span>;
+      `<span id=t_idt>EP3_CTRL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP3ControlReg</span>;
+      `<span id=t_idt>EP3_STS_REG</span> :  <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>EP3StatusReg</span>;
+      `<span id=t_idt>EP3_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP3TransTypeReg</span>;
+      `<span id=t_idt>EP3_NAK_TRAN_TYPE_STS_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>endP3NAKTransTypeReg</span>;
+     `<span id=t_idt>SC_CONTROL_REG</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>SCControlReg</span>;
+     `<span id=t_idt>SC_LINE_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>connectStateIn</span>}; 
+     `<span id=t_idt>SC_INTERRUPT_STATUS_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>NAKSentInt</span>, <span id=t_idt>SOFRxedInt</span>, <span id=t_idt>resetEventInt</span>, <span id=t_idt>resumeInt</span>, <span id=t_idt>transDoneInt</span>};
+     `<span id=t_idt>SC_INTERRUPT_MASK_REG</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>3'b000</span>, <span id=t_idt>interruptMaskReg</span>};
+     `<span id=t_idt>SC_ADDRESS</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>1'b0</span>, <span id=t_idt>SCAddrReg</span>};
+     `<span id=t_idt>SC_FRAME_NUM_MSP</span> : <span id=t_idt>dataOut</span> &lt;= <span id=t_idt>frameNum</span>[<span id=t_cns>10</span>:<span id=t_cns>3</span>];
+     `<span id=t_idt>SC_FRAME_NUM_LSP</span> : <span id=t_idt>dataOut</span> &lt;= {<span id=t_cns>5'b00000</span>, <span id=t_idt>frameNum</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]};
+      <span id=t_kwd>default</span>: <span id=t_idt>dataOut</span> &lt;= <span id=t_cns>8'h00</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/USBSlaveControlBI.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveDirectcontrol" alt="slaveDirectcontrol"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index127.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index127.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index127.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar127.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram127.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index127.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_DRCT_CNTL.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_DRCT_CNTL.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 78 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveDirectcontrol_DRCT_CNTL.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveDirectcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar78.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="sctxportarbiter" alt="sctxportarbiter"
+				width=2040 height=2640 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 3400 ;
+var PageY = 4400 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 2040;
+var h = 2640;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./sctxportarbiter.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./sctxportarbiter.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm	(revision 264)
@@ -0,0 +1,210 @@
+<html>
+<head>
+<title>slaveDirectcontrol.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveDirectControl</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:26 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>slaveDirectControl</span> (<span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>SCTxPortData</span>, <span id=t_idt>SCTxPortGnt</span>, <span id=t_idt>SCTxPortRdy</span>, <span id=t_idt>SCTxPortReq</span>, <span id=t_idt>SCTxPortWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>directControlEn</span>, <span id=t_idt>directControlLineState</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directControlEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directControlLineState</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortWEn</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>next_SCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>, <span id=t_idt>next_SCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortReq</span>, <span id=t_idt>next_SCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortWEn</span>, <span id=t_idt>next_SCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directControlEn</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directControlLineState</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: slvDrctCntl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SDC</span> <span id=t_cns>3'b000</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_DRCT_CNTL</span> <span id=t_cns>3'b001</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_WAIT_GNT</span> <span id=t_cns>3'b010</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_CHK_LOOP</span> <span id=t_cns>3'b011</span>
+<span id=t_dir>`define</span> <span id=t_idt>DRCT_CNTL_WAIT_RDY</span> <span id=t_cns>3'b100</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_FIN</span> <span id=t_cns>3'b101</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_GNT</span> <span id=t_cns>3'b110</span>
+<span id=t_dir>`define</span> <span id=t_idt>IDLE_WAIT_RDY</span> <span id=t_cns>3'b111</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_slvDrctCntl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>2</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_slvDrctCntl</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// diagram ACTION</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: slvDrctCntl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>directControlLineState</span> <span id=t_kwd>or</span> <span id=t_idt>directControlEn</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_slvDrctCntl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvDrctCntl_NextState</span>
+  <span id=t_idt>NextState_slvDrctCntl</span> &lt;= <span id=t_idt>CurrState_slvDrctCntl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_idt>SCTxPortReq</span>;
+  <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_idt>SCTxPortWEn</span>;
+  <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_idt>SCTxPortData</span>;
+  <span id=t_idt>next_SCTxPortCntl</span> &lt;= <span id=t_idt>SCTxPortCntl</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_slvDrctCntl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SDC</span>:
+     <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+   `<span id=t_idt>CHK_DRCT_CNTL</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>directControlEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_GNT</span>;
+      <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>IDLE_WAIT_GNT</span>;
+      <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>DRCT_CNTL_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>;
+   `<span id=t_idt>DRCT_CNTL_CHK_LOOP</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>directControlEn</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+      <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>DRCT_CNTL_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>DRCT_CNTL_CHK_LOOP</span>;
+      <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SCTxPortData</span> &lt;= {<span id=t_cns>6'b000000</span>, <span id=t_idt>directControlLineState</span>};
+      <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_DIRECT_CONTROL</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>CHK_DRCT_CNTL</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IDLE_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>IDLE_WAIT_RDY</span>;
+   `<span id=t_idt>IDLE_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvDrctCntl</span> &lt;= `<span id=t_idt>IDLE_FIN</span>;
+      <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_IDLE</span>;
+     <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvDrctCntl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_slvDrctCntl</span> &lt;= `<span id=t_idt>START_SDC</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_slvDrctCntl</span> &lt;= <span id=t_idt>NextState_slvDrctCntl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvDrctCntl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_idt>next_SCTxPortCntl</span>;
+   <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_idt>next_SCTxPortData</span>;
+   <span id=t_idt>SCTxPortWEn</span> &lt;= <span id=t_idt>next_SCTxPortWEn</span>;
+   <span id=t_idt>SCTxPortReq</span> &lt;= <span id=t_idt>next_SCTxPortReq</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 127 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveDirectcontrol_IDLE.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveDirectcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/serialInterfaceEngine/usbTxWireArbiter.asf/usbTxWireArbiter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveGetpacket DATA" alt="slaveGetpacket DATA"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram58.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/fifoMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/fifoMux.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/fifoMux.v/index.htm	(revision 264)
@@ -0,0 +1,229 @@
+<html>
+<head>
+<title>fifoMux.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// fifoMux.v                                                    ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:09 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>fifoMux</span> (
+  <span id=t_idt>currEndP</span>,
+  <span id=t_com>//TxFifo</span>
+  <span id=t_idt>TxFifoREn</span>,
+  <span id=t_idt>TxFifoEP0REn</span>,
+  <span id=t_idt>TxFifoEP1REn</span>,
+  <span id=t_idt>TxFifoEP2REn</span>,
+  <span id=t_idt>TxFifoEP3REn</span>,
+  <span id=t_idt>TxFifoData</span>,
+  <span id=t_idt>TxFifoEP0Data</span>,
+  <span id=t_idt>TxFifoEP1Data</span>,
+  <span id=t_idt>TxFifoEP2Data</span>,
+  <span id=t_idt>TxFifoEP3Data</span>,
+  <span id=t_idt>TxFifoEmpty</span>,
+  <span id=t_idt>TxFifoEP0Empty</span>,
+  <span id=t_idt>TxFifoEP1Empty</span>,
+  <span id=t_idt>TxFifoEP2Empty</span>,
+  <span id=t_idt>TxFifoEP3Empty</span>,
+  <span id=t_com>//RxFifo</span>
+  <span id=t_idt>RxFifoWEn</span>,
+  <span id=t_idt>RxFifoEP0WEn</span>,
+  <span id=t_idt>RxFifoEP1WEn</span>,
+  <span id=t_idt>RxFifoEP2WEn</span>,
+  <span id=t_idt>RxFifoEP3WEn</span>,
+  <span id=t_idt>RxFifoFull</span>,
+  <span id=t_idt>RxFifoEP0Full</span>,
+  <span id=t_idt>RxFifoEP1Full</span>,
+  <span id=t_idt>RxFifoEP2Full</span>,
+  <span id=t_idt>RxFifoEP3Full</span>
+    );
+
+
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_com>//TxFifo</span>
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoREn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP3Empty</span>;
+  <span id=t_com>//RxFifo</span>
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoWEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP3Full</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_com>//TxFifo</span>
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoREn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3Empty</span>;
+  <span id=t_com>//RxFifo</span>
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoWEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3Full</span>;
+
+<span id=t_com>//internal wires and regs</span>
+
+<span id=t_com>//combinatorially mux TX and RX fifos for end points 0 through 3</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>currEndP</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoREn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoWEn</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP0Data</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP1Data</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP2Data</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP3Data</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP0Empty</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP1Empty</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP2Empty</span> <span id=t_kwd>or</span>
+  <span id=t_idt>TxFifoEP3Empty</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoEP0Full</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoEP1Full</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoEP2Full</span> <span id=t_kwd>or</span>
+  <span id=t_idt>RxFifoEP3Full</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>currEndP</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>])
+    <span id=t_cns>2'b00</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>TxFifoEP0REn</span> &lt;= <span id=t_idt>TxFifoREn</span>;
+      <span id=t_idt>TxFifoEP1REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP2REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP3REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoData</span> &lt;= <span id=t_idt>TxFifoEP0Data</span>;
+      <span id=t_idt>TxFifoEmpty</span> &lt;= <span id=t_idt>TxFifoEP0Empty</span>;
+      <span id=t_idt>RxFifoEP0WEn</span> &lt;= <span id=t_idt>RxFifoWEn</span>;
+      <span id=t_idt>RxFifoEP1WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP2WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP3WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoFull</span> &lt;= <span id=t_idt>RxFifoEP0Full</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b01</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>TxFifoEP0REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP1REn</span> &lt;= <span id=t_idt>TxFifoREn</span>;
+      <span id=t_idt>TxFifoEP2REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP3REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoData</span> &lt;= <span id=t_idt>TxFifoEP1Data</span>;
+      <span id=t_idt>TxFifoEmpty</span> &lt;= <span id=t_idt>TxFifoEP1Empty</span>;
+      <span id=t_idt>RxFifoEP0WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP1WEn</span> &lt;= <span id=t_idt>RxFifoWEn</span>;
+      <span id=t_idt>RxFifoEP2WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP3WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoFull</span> &lt;= <span id=t_idt>RxFifoEP1Full</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b10</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>TxFifoEP0REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP1REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP2REn</span> &lt;= <span id=t_idt>TxFifoREn</span>;
+      <span id=t_idt>TxFifoEP3REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoData</span> &lt;= <span id=t_idt>TxFifoEP2Data</span>;
+      <span id=t_idt>TxFifoEmpty</span> &lt;= <span id=t_idt>TxFifoEP2Empty</span>;
+      <span id=t_idt>RxFifoEP0WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP1WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP2WEn</span> &lt;= <span id=t_idt>RxFifoWEn</span>;
+      <span id=t_idt>RxFifoEP3WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoFull</span> &lt;= <span id=t_idt>RxFifoEP2Full</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b11</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>TxFifoEP0REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP1REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP2REn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>TxFifoEP3REn</span> &lt;= <span id=t_idt>TxFifoREn</span>;
+      <span id=t_idt>TxFifoData</span> &lt;= <span id=t_idt>TxFifoEP3Data</span>;
+      <span id=t_idt>TxFifoEmpty</span> &lt;= <span id=t_idt>TxFifoEP3Empty</span>;
+      <span id=t_idt>RxFifoEP0WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP1WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP2WEn</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>RxFifoEP3WEn</span> &lt;= <span id=t_idt>RxFifoWEn</span>;
+      <span id=t_idt>RxFifoFull</span> &lt;= <span id=t_idt>RxFifoEP3Full</span>;
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>  
+<span id=t_kwd>end</span>      
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

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+*
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--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm	(revision 264)
@@ -0,0 +1,216 @@
+<html>
+<head>
+<title>sctxportarbiter.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// SCTxPortArbiter</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:12 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>SCTxPortArbiter</span> (<span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>SCTxPortData</span>, <span id=t_idt>SCTxPortRdyIn</span>, <span id=t_idt>SCTxPortRdyOut</span>, <span id=t_idt>SCTxPortWEnable</span>, <span id=t_idt>clk</span>, <span id=t_idt>directCntlCntl</span>, <span id=t_idt>directCntlData</span>, <span id=t_idt>directCntlGnt</span>, <span id=t_idt>directCntlReq</span>, <span id=t_idt>directCntlWEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketCntl</span>, <span id=t_idt>sendPacketData</span>, <span id=t_idt>sendPacketGnt</span>, <span id=t_idt>sendPacketReq</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortRdyIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortRdyOut</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortWEnable</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>directCntlGnt</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketGnt</span>;
+
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>next_SCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>, <span id=t_idt>next_SCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortRdyIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortRdyOut</span>, <span id=t_idt>next_SCTxPortRdyOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortWEnable</span>, <span id=t_idt>next_SCTxPortWEnable</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>directCntlGnt</span>, <span id=t_idt>next_directCntlGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketGnt</span>, <span id=t_idt>next_sendPacketGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  <span id=t_idt>muxDCEn</span>, <span id=t_idt>next_muxDCEn</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: SCTxArb</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>SARB1_WAIT_REQ</span> <span id=t_cns>2'b00</span>
+<span id=t_dir>`define</span> <span id=t_idt>SARB_SEND_PACKET</span> <span id=t_cns>2'b01</span>
+<span id=t_dir>`define</span> <span id=t_idt>SARB_DC</span> <span id=t_cns>2'b10</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SARB</span> <span id=t_cns>2'b11</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_SCTxArb</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_SCTxArb</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_com>// SOFController/directContol/sendPacket mux</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>SCTxPortRdyIn</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>SCTxPortRdyOut</span> = <span id=t_idt>SCTxPortRdyIn</span>;
+<span id=t_kwd>end</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>muxDCEn</span> <span id=t_kwd>or</span>
+        <span id=t_idt>directCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlCntl</span> <span id=t_kwd>or</span>
+                  <span id=t_idt>directCntlWEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlData</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlCntl</span> <span id=t_kwd>or</span>
+          <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketData</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketCntl</span>)
+<span id=t_kwd>begin</span>
+<span id=t_kwd>if</span> (<span id=t_idt>muxDCEn</span> == <span id=t_cns>1'b1</span>)
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>SCTxPortWEnable</span> &lt;= <span id=t_idt>directCntlWEn</span>;
+        <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_idt>directCntlData</span>;
+        <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_idt>directCntlCntl</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>else</span>
+    <span id=t_kwd>begin</span>
+        <span id=t_idt>SCTxPortWEnable</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+        <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_idt>sendPacketData</span>;
+        <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_idt>sendPacketCntl</span>;
+    <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: SCTxArb</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>sendPacketReq</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlReq</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketGnt</span> <span id=t_kwd>or</span> <span id=t_idt>muxDCEn</span> <span id=t_kwd>or</span> <span id=t_idt>directCntlGnt</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_SCTxArb</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SCTxArb_NextState</span>
+  <span id=t_idt>NextState_SCTxArb</span> &lt;= <span id=t_idt>CurrState_SCTxArb</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_idt>sendPacketGnt</span>;
+  <span id=t_idt>next_muxDCEn</span> &lt;= <span id=t_idt>muxDCEn</span>;
+  <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_idt>directCntlGnt</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_SCTxArb</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>SARB1_WAIT_REQ</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketReq</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB_SEND_PACKET</span>;
+      <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxDCEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>directCntlReq</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB_DC</span>;
+      <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_muxDCEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SARB_SEND_PACKET</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB1_WAIT_REQ</span>;
+      <span id=t_idt>next_sendPacketGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SARB_DC</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>directCntlReq</span> == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB1_WAIT_REQ</span>;
+      <span id=t_idt>next_directCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>START_SARB</span>:
+     <span id=t_idt>NextState_SCTxArb</span> &lt;= `<span id=t_idt>SARB1_WAIT_REQ</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SCTxArb_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_SCTxArb</span> &lt;= `<span id=t_idt>START_SARB</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_SCTxArb</span> &lt;= <span id=t_idt>NextState_SCTxArb</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>SCTxArb_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxDCEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>directCntlGnt</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>muxDCEn</span> &lt;= <span id=t_idt>next_muxDCEn</span>;
+   <span id=t_idt>sendPacketGnt</span> &lt;= <span id=t_idt>next_sendPacketGnt</span>;
+   <span id=t_idt>directCntlGnt</span> &lt;= <span id=t_idt>next_directCntlGnt</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveDirectcontrol DRCT_CNTL" alt="slaveDirectcontrol DRCT_CNTL"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram78.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(488,1130,591,1232,Click78,Over78);
+FUB[1] = new Array(1112,1183,1215,1285,Click127,Over127);
+
+//----------------------------------------------------------------------------
+function Click78(){fubclick('./index78.htm');}
+function Over78(){window.status='Hierarchical State DRCT_CNTL';};
+function Click127(){fubclick('./index127.htm');}
+function Over127(){window.status='Hierarchical State IDLE';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveDirectcontrol.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveDirectcontrol.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar58.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram58.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index58.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram112.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram112.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram112.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveGetpacket LOOP" alt="slaveGetpacket LOOP"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram112.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveGetpacket PROC_PKT" alt="slaveGetpacket PROC_PKT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index112.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index112.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index112.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar112.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram112.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index112.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_LOOP.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_LOOP.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1244,949,1347,1051,Click58,Over58);
+
+//----------------------------------------------------------------------------
+function Click58(){fubclick('./index58.htm');}
+function Over58(){window.status='Hierarchical State DATA';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 33 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveGetpacket_PROC_PKT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveGetpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar33.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar33.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram33.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index33.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm	(revision 264)
@@ -0,0 +1,351 @@
+<html>
+<head>
+<title>slaveGetpacket.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveGetPacket</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:35 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>slaveGetPacket</span> (<span id=t_idt>ACKRxed</span>, <span id=t_idt>CRCError</span>, <span id=t_idt>RXDataIn</span>, <span id=t_idt>RXDataValid</span>, <span id=t_idt>RXFifoData</span>, <span id=t_idt>RXFifoFull</span>, <span id=t_idt>RXFifoWEn</span>, <span id=t_idt>RXOverflow</span>, <span id=t_idt>RXPacketRdy</span>, <span id=t_idt>RXStreamStatusIn</span>, <span id=t_idt>RXTimeOut</span>, <span id=t_idt>RxPID</span>, <span id=t_idt>SIERxTimeOut</span>, <span id=t_idt>bitStuffError</span>, <span id=t_idt>clk</span>, <span id=t_idt>dataSequence</span>, <span id=t_idt>getPacketEn</span>, <span id=t_idt>rst</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXDataIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RXDataValid</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RXFifoFull</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStreamStatusIn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SIERxTimeOut</span>;   <span id=t_com>// Single cycle pulse</span>
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>getPacketEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>ACKRxed</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>CRCError</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXFifoData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXFifoWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXOverflow</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXPacketRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>RXTimeOut</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>dataSequence</span>;
+
+<span id=t_kwd>reg</span>     <span id=t_idt>ACKRxed</span>, <span id=t_idt>next_ACKRxed</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>CRCError</span>, <span id=t_idt>next_CRCError</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXDataIn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RXDataValid</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXFifoData</span>, <span id=t_idt>next_RXFifoData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RXFifoFull</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXFifoWEn</span>, <span id=t_idt>next_RXFifoWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXOverflow</span>, <span id=t_idt>next_RXOverflow</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXPacketRdy</span>, <span id=t_idt>next_RXPacketRdy</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RXStreamStatusIn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>RXTimeOut</span>, <span id=t_idt>next_RXTimeOut</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>, <span id=t_idt>next_RxPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>bitStuffError</span>, <span id=t_idt>next_bitStuffError</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>dataSequence</span>, <span id=t_idt>next_dataSequence</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>getPacketEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteOld</span>, <span id=t_idt>next_RXByteOld</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByteOldest</span>, <span id=t_idt>next_RXByteOldest</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXByte</span>, <span id=t_idt>next_RXByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>RXStreamStatus</span>, <span id=t_idt>next_RXStreamStatus</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: slvGetPkt</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_CHK_PID</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_HS</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D1</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D1</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D2</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_FIN</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D2</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_W_D3</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_CHK_D3</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_GP</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_PKT</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PKT_START</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_EN</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>PKT_RDY</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span> <span id=t_cns>5'b10001</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_slvGetPkt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_slvGetPkt</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: slvGetPkt</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RXDataIn</span> <span id=t_kwd>or</span> <span id=t_idt>RXStreamStatusIn</span> <span id=t_kwd>or</span> <span id=t_idt>RXByte</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteOldest</span> <span id=t_kwd>or</span> <span id=t_idt>RXByteOld</span> <span id=t_kwd>or</span> <span id=t_idt>RXDataValid</span> <span id=t_kwd>or</span> <span id=t_idt>RXStreamStatus</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoFull</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>RXOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RXTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>dataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>RxPID</span> <span id=t_kwd>or</span> <span id=t_idt>RXPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RXFifoData</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_slvGetPkt</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvGetPkt_NextState</span>
+  <span id=t_idt>NextState_slvGetPkt</span> &lt;= <span id=t_idt>CurrState_slvGetPkt</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>CRCError</span>;
+  <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>bitStuffError</span>;
+  <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_idt>RXOverflow</span>;
+  <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_idt>RXTimeOut</span>;
+  <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>ACKRxed</span>;
+  <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>dataSequence</span>;
+  <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXByte</span>;
+  <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatus</span>;
+  <span id=t_idt>next_RxPID</span> &lt;= <span id=t_idt>RxPID</span>;
+  <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_idt>RXPacketRdy</span>;
+  <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByteOldest</span>;
+  <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByteOld</span>;
+  <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_idt>RXFifoWEn</span>;
+  <span id=t_idt>next_RXFifoData</span> &lt;= <span id=t_idt>RXFifoData</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_slvGetPkt</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_GP</span>:
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>WAIT_EN</span>;
+   `<span id=t_idt>WAIT_PKT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>CHK_PKT_START</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PKT_START</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_START</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_CHK_PID</span>;
+      <span id=t_idt>next_RxPID</span> &lt;= <span id=t_idt>RXByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>];
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXTimeOut</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>WAIT_EN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketEn</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>WAIT_PKT</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PKT_RDY</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>WAIT_EN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_CHK_PID</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>HANDSHAKE</span>) 
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_HS</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>DATA</span>) 
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D1</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+   `<span id=t_idt>PROC_PKT_HS</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+      <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>RX_OVERFLOW_BIT</span>];
+      <span id=t_idt>next_ACKRxed</span> &lt;= <span id=t_idt>RXDataIn</span>[`<span id=t_idt>ACK_RXED_BIT</span>];
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_W_D1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D1</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D1</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D2</span>;
+      <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_W_D2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D2</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_CRCError</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>CRC_ERROR_BIT</span>];
+     <span id=t_idt>next_bitStuffError</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>BIT_STUFF_ERROR_BIT</span>];
+     <span id=t_idt>next_dataSequence</span> &lt;= <span id=t_idt>RXByte</span>[`<span id=t_idt>DATA_SEQUENCE_BIT</span>];
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PKT_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D2</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_W_D3</span>;
+      <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_W_D3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_CHK_D3</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+      <span id=t_idt>next_RXStreamStatus</span> &lt;= <span id=t_idt>RXStreamStatusIn</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_CHK_D3</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXStreamStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>) 
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RXFifoFull</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span>;
+      <span id=t_idt>next_RXOverflow</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>;
+      <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_RXFifoData</span> &lt;= <span id=t_idt>RXByteOldest</span>;
+      <span id=t_idt>next_RXByteOldest</span> &lt;= <span id=t_idt>RXByteOld</span>;
+      <span id=t_idt>next_RXByteOld</span> &lt;= <span id=t_idt>RXByte</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_FIFO_FULL</span>:
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>;
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_W_D</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_RXFifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> ((<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RXStreamStatusIn</span> == `<span id=t_idt>RX_PACKET_STREAM</span>))  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RXDataValid</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_FIN</span>;
+      <span id=t_idt>next_RXByte</span> &lt;= <span id=t_idt>RXDataIn</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>PROC_PKT_DATA_LOOP_DELAY</span>:
+     <span id=t_idt>NextState_slvGetPkt</span> &lt;= `<span id=t_idt>PROC_PKT_DATA_LOOP_CHK_FIFO</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvGetPkt_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_slvGetPkt</span> &lt;= `<span id=t_idt>START_GP</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_slvGetPkt</span> &lt;= <span id=t_idt>NextState_slvGetPkt</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvGetPkt_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXByteOld</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXByteOldest</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXStreamStatus</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>RXPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXFifoWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXFifoData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXOverflow</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RXTimeOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>RxPID</span> &lt;= <span id=t_cns>4'h0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>RXByteOld</span> &lt;= <span id=t_idt>next_RXByteOld</span>;
+   <span id=t_idt>RXByteOldest</span> &lt;= <span id=t_idt>next_RXByteOldest</span>;
+   <span id=t_idt>RXByte</span> &lt;= <span id=t_idt>next_RXByte</span>;
+   <span id=t_idt>RXStreamStatus</span> &lt;= <span id=t_idt>next_RXStreamStatus</span>;
+   <span id=t_idt>RXPacketRdy</span> &lt;= <span id=t_idt>next_RXPacketRdy</span>;
+   <span id=t_idt>RXFifoWEn</span> &lt;= <span id=t_idt>next_RXFifoWEn</span>;
+   <span id=t_idt>RXFifoData</span> &lt;= <span id=t_idt>next_RXFifoData</span>;
+   <span id=t_idt>CRCError</span> &lt;= <span id=t_idt>next_CRCError</span>;
+   <span id=t_idt>bitStuffError</span> &lt;= <span id=t_idt>next_bitStuffError</span>;
+   <span id=t_idt>RXOverflow</span> &lt;= <span id=t_idt>next_RXOverflow</span>;
+   <span id=t_idt>RXTimeOut</span> &lt;= <span id=t_idt>next_RXTimeOut</span>;
+   <span id=t_idt>ACKRxed</span> &lt;= <span id=t_idt>next_ACKRxed</span>;
+   <span id=t_idt>dataSequence</span> &lt;= <span id=t_idt>next_dataSequence</span>;
+   <span id=t_idt>RxPID</span> &lt;= <span id=t_idt>next_RxPID</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(1061,1577,1163,1679,Click33,Over33);
+
+//----------------------------------------------------------------------------
+function Click33(){fubclick('./index33.htm');}
+function Over33(){window.status='Hierarchical State PROC_PKT';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveGetpacket.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveGetpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm	(revision 264)
@@ -0,0 +1,112 @@
+<html>
+<head>
+<title>slaveRxStatusMonitor.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveRxStatusMonitor.v                                       ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:36 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>slaveRxStatusMonitor</span>(<span id=t_idt>connectStateIn</span>, <span id=t_idt>connectStateOut</span>, <span id=t_idt>resumeDetectedIn</span>, <span id=t_idt>resetEventOut</span>, <span id=t_idt>resumeIntOut</span>, <span id=t_idt>clk</span>, <span id=t_idt>rst</span>);
+
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resetEventOut</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>;
+
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resetEventOut</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>resumeIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>oldConnectState</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>oldResumeDetected</span>;
+
+<span id=t_kwd>always</span> @(<span id=t_idt>connectStateIn</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>connectStateOut</span> &lt;= <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span> == <span id=t_cns>1'b1</span>)
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>oldConnectState</span> &lt;= <span id=t_idt>connectStateIn</span>;
+   <span id=t_idt>oldResumeDetected</span> &lt;= <span id=t_idt>resumeDetectedIn</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span>
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>oldConnectState</span> &lt;= <span id=t_idt>connectStateIn</span>;
+   <span id=t_idt>oldResumeDetected</span> &lt;= <span id=t_idt>resumeDetectedIn</span>;
+   <span id=t_kwd>if</span> (<span id=t_idt>oldConnectState</span> != <span id=t_idt>connectStateIn</span>)
+     <span id=t_idt>resetEventOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>else</span>
+     <span id=t_idt>resetEventOut</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>if</span> (<span id=t_idt>resumeDetectedIn</span> == <span id=t_cns>1'b1</span> &amp;&amp; <span id=t_idt>oldResumeDetected</span> == <span id=t_cns>1'b0</span>)
+     <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_kwd>else</span> 
+     <span id=t_idt>resumeIntOut</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveRxStatusMonitor.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveSendpacket SP_SEND_PID" alt="slaveSendpacket SP_SEND_PID"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram21.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index45.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index45.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index45.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar45.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram45.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index45.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_SEND_PID.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_SEND_PID.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller" alt="slavecontroller"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_DATA.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_DATA.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 112 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveGetpacket_LOOP.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveGetpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar112.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveSendpacket" alt="slaveSendpacket"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar21.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram21.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index21.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_D0_D1.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket_SP_D0_D1.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 45 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveSendpacket_SP_D0_D1.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveSendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram551.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram551.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram551.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller SETUP_OUT" alt="slavecontroller SETUP_OUT"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram551.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index376.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index376.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index376.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar376.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram376.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index376.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram580.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram580.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram580.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller IN" alt="slavecontroller IN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram580.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm	(revision 264)
@@ -0,0 +1,265 @@
+<html>
+<head>
+<title>slaveSendpacket.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveSendPacket</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:41 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>slaveSendPacket</span> (<span id=t_idt>PID</span>, <span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>SCTxPortData</span>, <span id=t_idt>SCTxPortGnt</span>, <span id=t_idt>SCTxPortRdy</span>, <span id=t_idt>SCTxPortReq</span>, <span id=t_idt>SCTxPortWEn</span>, <span id=t_idt>clk</span>, <span id=t_idt>fifoData</span>, <span id=t_idt>fifoEmpty</span>, <span id=t_idt>fifoReadEn</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>);
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>PID</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortGnt</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoData</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortReq</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SCTxPortWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>fifoReadEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketRdy</span>;
+
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>PID</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCntl</span>, <span id=t_idt>next_SCTxPortCntl</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>, <span id=t_idt>next_SCTxPortData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortGnt</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortReq</span>, <span id=t_idt>next_SCTxPortReq</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SCTxPortWEn</span>, <span id=t_idt>next_SCTxPortWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>fifoData</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>fifoEmpty</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>fifoReadEn</span>, <span id=t_idt>next_fifoReadEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>next_sendPacketRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketWEn</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>PIDNotPID</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: slvSndPkt</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_SP1</span> <span id=t_cns>4'b0000</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_WAIT_ENABLE</span> <span id=t_cns>4'b0001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP1_WAIT_GNT</span> <span id=t_cns>4'b0010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_SEND_PID_WAIT_RDY</span> <span id=t_cns>4'b0011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_SEND_PID_FIN</span> <span id=t_cns>4'b0100</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIN_SP1</span> <span id=t_cns>4'b0101</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_READ_FIFO</span> <span id=t_cns>4'b0110</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_WAIT_READ_FIFO</span> <span id=t_cns>4'b0111</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_FIFO_EMPTY</span> <span id=t_cns>4'b1000</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_FIN</span> <span id=t_cns>4'b1001</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_TERM_BYTE</span> <span id=t_cns>4'b1010</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_NOT_DATA</span> <span id=t_cns>4'b1011</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_CLR_WEN</span> <span id=t_cns>4'b1100</span>
+<span id=t_dir>`define</span> <span id=t_idt>SP_D0_D1_CLR_REN</span> <span id=t_cns>4'b1101</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_slvSndPkt</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_slvSndPkt</span>;
+
+<span id=t_com>// Diagram actions (continuous assignments allowed only: assign ...)</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>PID</span>)
+<span id=t_kwd>begin</span>
+    <span id=t_idt>PIDNotPID</span> &lt;=  { (<span id=t_idt>PID</span> ^ <span id=t_cns>4'hf</span>), <span id=t_idt>PID</span> };
+<span id=t_kwd>end</span>
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: slvSndPkt</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>PIDNotPID</span> <span id=t_kwd>or</span> <span id=t_idt>fifoData</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortGnt</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortRdy</span> <span id=t_kwd>or</span> <span id=t_idt>PID</span> <span id=t_kwd>or</span> <span id=t_idt>fifoEmpty</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortReq</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortWEn</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortData</span> <span id=t_kwd>or</span> <span id=t_idt>SCTxPortCntl</span> <span id=t_kwd>or</span> <span id=t_idt>fifoReadEn</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_slvSndPkt</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvSndPkt_NextState</span>
+  <span id=t_idt>NextState_slvSndPkt</span> &lt;= <span id=t_idt>CurrState_slvSndPkt</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_idt>sendPacketRdy</span>;
+  <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_idt>SCTxPortReq</span>;
+  <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_idt>SCTxPortWEn</span>;
+  <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_idt>SCTxPortData</span>;
+  <span id=t_idt>next_SCTxPortCntl</span> &lt;= <span id=t_idt>SCTxPortCntl</span>;
+  <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_idt>fifoReadEn</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_slvSndPkt</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>START_SP1</span>:
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_WAIT_ENABLE</span>;
+   `<span id=t_idt>SP_WAIT_ENABLE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketWEn</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP1_WAIT_GNT</span>;
+      <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+      <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP1_WAIT_GNT</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortGnt</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_SEND_PID_WAIT_RDY</span>;
+   `<span id=t_idt>FIN_SP1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_WAIT_ENABLE</span>;
+     <span id=t_idt>next_sendPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_NOT_DATA</span>:
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>FIN_SP1</span>;
+   `<span id=t_idt>SP_SEND_PID_WAIT_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_SEND_PID_FIN</span>;
+      <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_idt>PIDNotPID</span>;
+      <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_START</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_SEND_PID_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>PID</span> == `<span id=t_idt>DATA0</span> || <span id=t_idt>PID</span> == `<span id=t_idt>DATA1</span>)  
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_FIFO_EMPTY</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_NOT_DATA</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_READ_FIFO</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_idt>fifoData</span>;
+     <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STREAM</span>;
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_CLR_WEN</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_WAIT_READ_FIFO</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_CLR_REN</span>;
+      <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_FIFO_EMPTY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>fifoEmpty</span> == <span id=t_cns>1'b0</span>) 
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_WAIT_READ_FIFO</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_TERM_BYTE</span>;
+   `<span id=t_idt>SP_D0_D1_FIN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>FIN_SP1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_TERM_BYTE</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>SCTxPortRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_FIN</span>;
+      <span id=t_com>//Last byte is not valid data,</span>
+      <span id=t_com>//but the 'TX_PACKET_STOP' flag is required</span>
+      <span id=t_com>//by the SIE state machine to detect end of data packet</span>
+      <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_SCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+      <span id=t_idt>next_SCTxPortCntl</span> &lt;= `<span id=t_idt>TX_PACKET_STOP</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_CLR_WEN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_FIFO_EMPTY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SP_D0_D1_CLR_REN</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_fifoReadEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvSndPkt</span> &lt;= `<span id=t_idt>SP_D0_D1_READ_FIFO</span>;
+   <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvSndPkt_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_slvSndPkt</span> &lt;= `<span id=t_idt>START_SP1</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_slvSndPkt</span> &lt;= <span id=t_idt>NextState_slvSndPkt</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvSndPkt_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+   <span id=t_idt>SCTxPortReq</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SCTxPortWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>fifoReadEn</span> &lt;= <span id=t_cns>1'b0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>sendPacketRdy</span> &lt;= <span id=t_idt>next_sendPacketRdy</span>;
+   <span id=t_idt>SCTxPortReq</span> &lt;= <span id=t_idt>next_SCTxPortReq</span>;
+   <span id=t_idt>SCTxPortWEn</span> &lt;= <span id=t_idt>next_SCTxPortWEn</span>;
+   <span id=t_idt>SCTxPortData</span> &lt;= <span id=t_idt>next_SCTxPortData</span>;
+   <span id=t_idt>SCTxPortCntl</span> &lt;= <span id=t_idt>next_SCTxPortCntl</span>;
+   <span id=t_idt>fifoReadEn</span> &lt;= <span id=t_idt>next_fifoReadEn</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 21 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveSendpacket_SP_SEND_PID.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveSendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar21.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram376.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram376.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram376.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller GET_TOKEN" alt="slavecontroller GET_TOKEN"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram376.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index15.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index15.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index15.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar15.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram15.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index15.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/endpMux.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/endpMux.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/endpMux.v/index.htm	(revision 264)
@@ -0,0 +1,277 @@
+<html>
+<head>
+<title>endpMux.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// endpMux.v                                                    ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:08 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_dir>`include</span> <span id=t_cns>"usbSlaveControl_h.v"</span> 
+
+<span id=t_kwd>module</span> <span id=t_idt>endpMux</span> (
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>,
+  <span id=t_idt>currEndP</span>,
+  <span id=t_idt>NAKSent</span>,
+  <span id=t_idt>stallSent</span>,
+  <span id=t_idt>CRCError</span>,
+  <span id=t_idt>bitStuffError</span>,
+  <span id=t_idt>RxOverflow</span>,
+  <span id=t_idt>RxTimeOut</span>,
+  <span id=t_idt>dataSequence</span>,
+  <span id=t_idt>ACKRxed</span>,
+  <span id=t_idt>transType</span>,
+  <span id=t_idt>transTypeNAK</span>,
+  <span id=t_idt>endPControlReg</span>,
+  <span id=t_idt>clrEPRdy</span>,
+  <span id=t_idt>endPMuxErrorsWEn</span>,
+  <span id=t_idt>endP0ControlReg</span>,
+  <span id=t_idt>endP1ControlReg</span>,
+  <span id=t_idt>endP2ControlReg</span>,
+  <span id=t_idt>endP3ControlReg</span>,
+  <span id=t_idt>endP0StatusReg</span>,
+  <span id=t_idt>endP1StatusReg</span>,
+  <span id=t_idt>endP2StatusReg</span>,
+  <span id=t_idt>endP3StatusReg</span>,
+  <span id=t_idt>endP0TransTypeReg</span>,
+  <span id=t_idt>endP1TransTypeReg</span>,
+  <span id=t_idt>endP2TransTypeReg</span>,
+  <span id=t_idt>endP3TransTypeReg</span>,
+  <span id=t_idt>endP0NAKTransTypeReg</span>,
+  <span id=t_idt>endP1NAKTransTypeReg</span>,
+  <span id=t_idt>endP2NAKTransTypeReg</span>,
+  <span id=t_idt>endP3NAKTransTypeReg</span>,
+  <span id=t_idt>clrEP0Rdy</span>,
+  <span id=t_idt>clrEP1Rdy</span>,
+  <span id=t_idt>clrEP2Rdy</span>,
+  <span id=t_idt>clrEP3Rdy</span>);
+
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_kwd>input</span> <span id=t_idt>NAKSent</span>;
+<span id=t_kwd>input</span> <span id=t_idt>stallSent</span>;
+<span id=t_kwd>input</span> <span id=t_idt>CRCError</span>;
+<span id=t_kwd>input</span> <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxOverflow</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxTimeOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>dataSequence</span>;
+<span id=t_kwd>input</span> <span id=t_idt>ACKRxed</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transTypeNAK</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endPControlReg</span>;
+<span id=t_kwd>input</span> <span id=t_idt>clrEPRdy</span>;
+<span id=t_kwd>input</span> <span id=t_idt>endPMuxErrorsWEn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3StatusReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>output</span> <span id=t_idt>clrEP0Rdy</span>;
+<span id=t_kwd>output</span> <span id=t_idt>clrEP1Rdy</span>;
+<span id=t_kwd>output</span> <span id=t_idt>clrEP2Rdy</span>;
+<span id=t_kwd>output</span> <span id=t_idt>clrEP3Rdy</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>NAKSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>stallSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>CRCError</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxOverflow</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxTimeOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>dataSequence</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>ACKRxed</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transTypeNAK</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endPControlReg</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEPRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>endPMuxErrorsWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3StatusReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrEP0Rdy</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrEP1Rdy</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrEP2Rdy</span>;
+<span id=t_kwd>reg</span> <span id=t_idt>clrEP3Rdy</span>;
+
+<span id=t_com>//internal wires and regs</span>
+<span id=t_kwd>reg</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endPStatusCombine</span>;
+
+<span id=t_com>//mux endPControlReg and clrEPRdy</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>case</span> (<span id=t_idt>currEndP</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>])
+    <span id=t_cns>2'b00</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>endPControlReg</span> &lt;= <span id=t_idt>endP0ControlReg</span>;
+      <span id=t_idt>clrEP0Rdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b01</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>endPControlReg</span> &lt;= <span id=t_idt>endP1ControlReg</span>;
+      <span id=t_idt>clrEP1Rdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b10</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>endPControlReg</span> &lt;= <span id=t_idt>endP2ControlReg</span>;
+      <span id=t_idt>clrEP2Rdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+    <span id=t_kwd>end</span>
+    <span id=t_cns>2'b11</span>: <span id=t_kwd>begin</span>
+      <span id=t_idt>endPControlReg</span> &lt;= <span id=t_idt>endP3ControlReg</span>;
+      <span id=t_idt>clrEP3Rdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>endcase</span>  
+<span id=t_kwd>end</span>      
+
+<span id=t_com>//mux endPNAKTransType, endPTransType, endPStatusReg</span>
+<span id=t_com>//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.</span>
+<span id=t_com>//else update the entire status reg</span>
+<span id=t_kwd>always</span> @(<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) <span id=t_kwd>begin</span>
+    <span id=t_idt>endP0NAKTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP1NAKTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP2NAKTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP3NAKTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP0TransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP1TransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP2TransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP3TransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+    <span id=t_idt>endP0StatusReg</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>endP1StatusReg</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>endP2StatusReg</span> &lt;= <span id=t_cns>4'h0</span>;
+    <span id=t_idt>endP3StatusReg</span> &lt;= <span id=t_cns>4'h0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+    <span id=t_kwd>if</span> (<span id=t_idt>endPMuxErrorsWEn</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+      <span id=t_kwd>if</span> (<span id=t_idt>NAKSent</span> == <span id=t_cns>1'b1</span>) <span id=t_kwd>begin</span>
+        <span id=t_kwd>case</span> (<span id=t_idt>currEndP</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>])
+          <span id=t_cns>2'b00</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP0NAKTransTypeReg</span> &lt;= <span id=t_idt>transTypeNAK</span>;
+            <span id=t_idt>endP0StatusReg</span> &lt;= <span id=t_idt>endP0StatusReg</span> | `<span id=t_idt>NAK_SET_MASK</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b01</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP1NAKTransTypeReg</span> &lt;= <span id=t_idt>transTypeNAK</span>;
+            <span id=t_idt>endP1StatusReg</span> &lt;= <span id=t_idt>endP1StatusReg</span> | `<span id=t_idt>NAK_SET_MASK</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b10</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP2NAKTransTypeReg</span> &lt;= <span id=t_idt>transTypeNAK</span>;
+            <span id=t_idt>endP2StatusReg</span> &lt;= <span id=t_idt>endP2StatusReg</span> | `<span id=t_idt>NAK_SET_MASK</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b11</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP3NAKTransTypeReg</span> &lt;= <span id=t_idt>transTypeNAK</span>;
+            <span id=t_idt>endP3StatusReg</span> &lt;= <span id=t_idt>endP3StatusReg</span> | `<span id=t_idt>NAK_SET_MASK</span>; 
+          <span id=t_kwd>end</span>
+        <span id=t_kwd>endcase</span>
+      <span id=t_kwd>end</span>
+      <span id=t_kwd>else</span> <span id=t_kwd>begin</span>
+        <span id=t_kwd>case</span> (<span id=t_idt>currEndP</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>])
+          <span id=t_cns>2'b00</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP0TransTypeReg</span> &lt;= <span id=t_idt>transType</span>;
+            <span id=t_idt>endP0StatusReg</span> &lt;= <span id=t_idt>endPStatusCombine</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b01</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP1TransTypeReg</span> &lt;= <span id=t_idt>transType</span>;
+            <span id=t_idt>endP1StatusReg</span> &lt;= <span id=t_idt>endPStatusCombine</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b10</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP2TransTypeReg</span> &lt;= <span id=t_idt>transType</span>;
+            <span id=t_idt>endP2StatusReg</span> &lt;= <span id=t_idt>endPStatusCombine</span>; 
+          <span id=t_kwd>end</span>
+          <span id=t_cns>2'b11</span>: <span id=t_kwd>begin</span>
+            <span id=t_idt>endP3TransTypeReg</span> &lt;= <span id=t_idt>transType</span>;
+            <span id=t_idt>endP3StatusReg</span> &lt;= <span id=t_idt>endPStatusCombine</span>; 
+          <span id=t_kwd>end</span>
+        <span id=t_kwd>endcase</span>
+      <span id=t_kwd>end</span>
+    <span id=t_kwd>end</span>
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+        
+
+<span id=t_com>//combine status bits into a single word</span>
+<span id=t_kwd>always</span> @(<span id=t_idt>dataSequence</span> <span id=t_kwd>or</span> <span id=t_idt>ACKRxed</span> <span id=t_kwd>or</span> <span id=t_idt>stallSent</span> <span id=t_kwd>or</span> <span id=t_idt>RxTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>RxOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span>)
+<span id=t_kwd>begin</span>
+  <span id=t_idt>endPStatusCombine</span> &lt;= {<span id=t_idt>dataSequence</span>, <span id=t_idt>ACKRxed</span>, <span id=t_idt>stallSent</span>, <span id=t_cns>1'b0</span>, <span id=t_idt>RxTimeOut</span>, <span id=t_idt>RxOverflow</span>, <span id=t_idt>bitStuffError</span>, <span id=t_idt>CRCError</span>};
+<span id=t_kwd>end</span>
+
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/endpMux.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/sctxportarbiter.asf/sctxportarbiter.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveDirectcontrol IDLE" alt="slaveDirectcontrol IDLE"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/diagram127.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar78.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram78.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/index78.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_IDLE.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveDirectcontrol.asf/slaveDirectcontrol_IDLE.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index551.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index551.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index551.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar551.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram551.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index551.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm	(revision 264)
@@ -0,0 +1,449 @@
+<html>
+<head>
+<title>slavecontroller.v</title>
+<link rel="stylesheet" href="./../../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// slaveController</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// http://www.opencores.org/cores/????/                         ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from http://www.opencores.org/lgpl.shtml                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:21 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+
+<span id=t_dir>`timescale</span> <span id=t_cns>1</span><span id=t_idt>ns</span> / <span id=t_cns>1</span><span id=t_idt>ps</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSerialInterfaceEngine_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbSlaveControl_h.v"</span>
+<span id=t_dir>`include</span> <span id=t_cns>"usbConstants_h.v"</span>
+
+
+<span id=t_kwd>module</span> <span id=t_idt>slavecontroller</span> (<span id=t_idt>CRCError</span>, <span id=t_idt>NAKSent</span>, <span id=t_idt>RxByte</span>, <span id=t_idt>RxDataWEn</span>, <span id=t_idt>RxOverflow</span>, <span id=t_idt>RxStatus</span>, <span id=t_idt>RxTimeOut</span>, <span id=t_idt>SCGlobalEn</span>, <span id=t_idt>SOFRxed</span>, <span id=t_idt>USBEndPControlReg</span>, <span id=t_idt>USBEndPNakTransTypeReg</span>, <span id=t_idt>USBEndPTransTypeReg</span>, <span id=t_idt>USBEndP</span>, <span id=t_idt>USBTgtAddress</span>, <span id=t_idt>bitStuffError</span>, <span id=t_idt>clk</span>, <span id=t_idt>clrEPRdy</span>, <span id=t_idt>endPMuxErrorsWEn</span>, <span id=t_idt>frameNum</span>, <span id=t_idt>getPacketREn</span>, <span id=t_idt>getPacketRdy</span>, <span id=t_idt>rst</span>, <span id=t_idt>sendPacketPID</span>, <span id=t_idt>sendPacketRdy</span>, <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>stallSent</span>, <span id=t_idt>transDone</span>);
+<span id=t_kwd>input</span>   <span id=t_idt>CRCError</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByte</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RxDataWEn</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RxOverflow</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxStatus</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>RxTimeOut</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>SCGlobalEn</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPControlReg</span>;
+<span id=t_kwd>input</span>   [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>USBTgtAddress</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span>   <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>NAKSent</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>SOFRxed</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPNakTransTypeReg</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPTransTypeReg</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndP</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>clrEPRdy</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>endPMuxErrorsWEn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>getPacketREn</span>;
+<span id=t_kwd>output</span>  [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>sendPacketWEn</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>stallSent</span>;
+<span id=t_kwd>output</span>  <span id=t_idt>transDone</span>;
+
+<span id=t_kwd>wire</span>    <span id=t_idt>CRCError</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>NAKSent</span>, <span id=t_idt>next_NAKSent</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByte</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RxDataWEn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RxOverflow</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxStatus</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>RxTimeOut</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>SCGlobalEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>SOFRxed</span>, <span id=t_idt>next_SOFRxed</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPControlReg</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPNakTransTypeReg</span>, <span id=t_idt>next_USBEndPNakTransTypeReg</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndPTransTypeReg</span>, <span id=t_idt>next_USBEndPTransTypeReg</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>USBEndP</span>, <span id=t_idt>next_USBEndP</span>;
+<span id=t_kwd>wire</span>    [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>USBTgtAddress</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>bitStuffError</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>clk</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>clrEPRdy</span>, <span id=t_idt>next_clrEPRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>endPMuxErrorsWEn</span>, <span id=t_idt>next_endPMuxErrorsWEn</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>, <span id=t_idt>next_frameNum</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>getPacketREn</span>, <span id=t_idt>next_getPacketREn</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>rst</span>;
+<span id=t_kwd>reg</span>     [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketPID</span>, <span id=t_idt>next_sendPacketPID</span>;
+<span id=t_kwd>wire</span>    <span id=t_idt>sendPacketRdy</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>sendPacketWEn</span>, <span id=t_idt>next_sendPacketWEn</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>stallSent</span>, <span id=t_idt>next_stallSent</span>;
+<span id=t_kwd>reg</span>     <span id=t_idt>transDone</span>, <span id=t_idt>next_transDone</span>;
+
+<span id=t_com>// diagram signals declarations</span>
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>PIDByte</span>, <span id=t_idt>next_PIDByte</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>6</span>:<span id=t_cns>0</span>]<span id=t_idt>USBAddress</span>, <span id=t_idt>next_USBAddress</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>addrEndPTemp</span>, <span id=t_idt>next_addrEndPTemp</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>7</span>:<span id=t_cns>0</span>]<span id=t_idt>endpCRCTemp</span>, <span id=t_idt>next_endpCRCTemp</span>;
+<span id=t_kwd>reg</span>  [<span id=t_cns>1</span>:<span id=t_cns>0</span>]<span id=t_idt>tempUSBEndPTransTypeReg</span>, <span id=t_idt>next_tempUSBEndPTransTypeReg</span>;
+
+<span id=t_com>// BINARY ENCODED state machine: slvCntrl</span>
+<span id=t_com>// State codes definitions:</span>
+<span id=t_dir>`define</span> <span id=t_idt>WAIT_RX1</span> <span id=t_cns>5'b00000</span>
+<span id=t_dir>`define</span> <span id=t_idt>FIN_SC</span> <span id=t_cns>5'b00001</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_WAIT_CRC</span> <span id=t_cns>5'b00010</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_WAIT_ADDR</span> <span id=t_cns>5'b00011</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_WAIT_STOP</span> <span id=t_cns>5'b00100</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_PID</span> <span id=t_cns>5'b00101</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_CHK_SOF</span> <span id=t_cns>5'b00110</span>
+<span id=t_dir>`define</span> <span id=t_idt>PID_ERROR</span> <span id=t_cns>5'b00111</span>
+<span id=t_dir>`define</span> <span id=t_idt>CHK_RDY</span> <span id=t_cns>5'b01000</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_NAK_STALL</span> <span id=t_cns>5'b01001</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_CHK_RDY</span> <span id=t_cns>5'b01010</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_DATA</span> <span id=t_cns>5'b01011</span>
+<span id=t_dir>`define</span> <span id=t_idt>IN_GET_RESP</span> <span id=t_cns>5'b01100</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_OUT_CHK</span> <span id=t_cns>5'b01101</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_OUT_SEND</span> <span id=t_cns>5'b01110</span>
+<span id=t_dir>`define</span> <span id=t_idt>SETUP_OUT_GET_PKT</span> <span id=t_cns>5'b01111</span>
+<span id=t_dir>`define</span> <span id=t_idt>START_S1</span> <span id=t_cns>5'b10000</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_DELAY</span> <span id=t_cns>5'b10001</span>
+<span id=t_dir>`define</span> <span id=t_idt>GET_TOKEN_CHK_ADDR</span> <span id=t_cns>5'b10010</span>
+
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>CurrState_slvCntrl</span>;
+<span id=t_kwd>reg</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>NextState_slvCntrl</span>;
+
+
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>// Machine: slvCntrl</span>
+<span id=t_com>//--------------------------------------------------------------------</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// NextState logic (combinatorial)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_idt>RxByte</span> <span id=t_kwd>or</span> <span id=t_idt>tempUSBEndPTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>endpCRCTemp</span> <span id=t_kwd>or</span> <span id=t_idt>addrEndPTemp</span> <span id=t_kwd>or</span> <span id=t_idt>RxDataWEn</span> <span id=t_kwd>or</span> <span id=t_idt>RxStatus</span> <span id=t_kwd>or</span> <span id=t_idt>PIDByte</span> <span id=t_kwd>or</span> <span id=t_idt>USBEndPControlReg</span> <span id=t_kwd>or</span> <span id=t_idt>NAKSent</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketRdy</span> <span id=t_kwd>or</span> <span id=t_idt>CRCError</span> <span id=t_kwd>or</span> <span id=t_idt>bitStuffError</span> <span id=t_kwd>or</span> <span id=t_idt>RxOverflow</span> <span id=t_kwd>or</span> <span id=t_idt>RxTimeOut</span> <span id=t_kwd>or</span> <span id=t_idt>USBEndP</span> <span id=t_kwd>or</span> <span id=t_idt>USBAddress</span> <span id=t_kwd>or</span> <span id=t_idt>USBTgtAddress</span> <span id=t_kwd>or</span> <span id=t_idt>SCGlobalEn</span> <span id=t_kwd>or</span> <span id=t_idt>stallSent</span> <span id=t_kwd>or</span> <span id=t_idt>SOFRxed</span> <span id=t_kwd>or</span> <span id=t_idt>transDone</span> <span id=t_kwd>or</span> <span id=t_idt>clrEPRdy</span> <span id=t_kwd>or</span> <span id=t_idt>endPMuxErrorsWEn</span> <span id=t_kwd>or</span> <span id=t_idt>getPacketREn</span> <span id=t_kwd>or</span> <span id=t_idt>USBEndPTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>USBEndPNakTransTypeReg</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketWEn</span> <span id=t_kwd>or</span> <span id=t_idt>sendPacketPID</span> <span id=t_kwd>or</span> <span id=t_idt>frameNum</span> <span id=t_kwd>or</span> <span id=t_idt>CurrState_slvCntrl</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvCntrl_NextState</span>
+  <span id=t_idt>NextState_slvCntrl</span> &lt;= <span id=t_idt>CurrState_slvCntrl</span>;
+  <span id=t_com>// Set default values for outputs and signals</span>
+  <span id=t_idt>next_stallSent</span> &lt;= <span id=t_idt>stallSent</span>;
+  <span id=t_idt>next_NAKSent</span> &lt;= <span id=t_idt>NAKSent</span>;
+  <span id=t_idt>next_SOFRxed</span> &lt;= <span id=t_idt>SOFRxed</span>;
+  <span id=t_idt>next_PIDByte</span> &lt;= <span id=t_idt>PIDByte</span>;
+  <span id=t_idt>next_transDone</span> &lt;= <span id=t_idt>transDone</span>;
+  <span id=t_idt>next_clrEPRdy</span> &lt;= <span id=t_idt>clrEPRdy</span>;
+  <span id=t_idt>next_endPMuxErrorsWEn</span> &lt;= <span id=t_idt>endPMuxErrorsWEn</span>;
+  <span id=t_idt>next_tempUSBEndPTransTypeReg</span> &lt;= <span id=t_idt>tempUSBEndPTransTypeReg</span>;
+  <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_idt>getPacketREn</span>;
+  <span id=t_idt>next_USBEndPTransTypeReg</span> &lt;= <span id=t_idt>USBEndPTransTypeReg</span>;
+  <span id=t_idt>next_USBEndPNakTransTypeReg</span> &lt;= <span id=t_idt>USBEndPNakTransTypeReg</span>;
+  <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_idt>sendPacketWEn</span>;
+  <span id=t_idt>next_sendPacketPID</span> &lt;= <span id=t_idt>sendPacketPID</span>;
+  <span id=t_idt>next_endpCRCTemp</span> &lt;= <span id=t_idt>endpCRCTemp</span>;
+  <span id=t_idt>next_addrEndPTemp</span> &lt;= <span id=t_idt>addrEndPTemp</span>;
+  <span id=t_idt>next_frameNum</span> &lt;= <span id=t_idt>frameNum</span>;
+  <span id=t_idt>next_USBAddress</span> &lt;= <span id=t_idt>USBAddress</span>;
+  <span id=t_idt>next_USBEndP</span> &lt;= <span id=t_idt>USBEndP</span>;
+  <span id=t_kwd>case</span> (<span id=t_idt>CurrState_slvCntrl</span>) <span id=t_com>// synopsys parallel_case full_case</span>
+   `<span id=t_idt>WAIT_RX1</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_stallSent</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_NAKSent</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_SOFRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> == `<span id=t_idt>RX_PACKET_START</span> &amp;&amp; 
+      <span id=t_idt>RxByte</span>[<span id=t_cns>1</span>:<span id=t_cns>0</span>] == `<span id=t_idt>TOKEN</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_WAIT_ADDR</span>;
+      <span id=t_idt>next_PIDByte</span> &lt;= <span id=t_idt>RxByte</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>FIN_SC</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_transDone</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_clrEPRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>next_endPMuxErrorsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>CHK_PID</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>PIDByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] == `<span id=t_idt>SETUP</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_GET_PKT</span>;
+      <span id=t_idt>next_tempUSBEndPTransTypeReg</span> &lt;= `<span id=t_idt>SC_SETUP_TRANS</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>PIDByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] == `<span id=t_idt>OUT</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_GET_PKT</span>;
+      <span id=t_idt>next_tempUSBEndPTransTypeReg</span> &lt;= `<span id=t_idt>SC_OUTDATA_TRANS</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>PIDByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] == `<span id=t_idt>IN</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_CHK_RDY</span>;
+      <span id=t_idt>next_tempUSBEndPTransTypeReg</span> &lt;= `<span id=t_idt>SC_IN_TRANS</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>PID_ERROR</span>;
+   `<span id=t_idt>PID_ERROR</span>:
+     <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>CHK_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_READY_BIT</span>] == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>FIN_SC</span>;
+      <span id=t_idt>next_transDone</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_clrEPRdy</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_USBEndPTransTypeReg</span> &lt;= <span id=t_idt>tempUSBEndPTransTypeReg</span>;
+      <span id=t_idt>next_endPMuxErrorsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>NAKSent</span> == <span id=t_cns>1'b1</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>FIN_SC</span>;
+      <span id=t_idt>next_USBEndPNakTransTypeReg</span> &lt;= <span id=t_idt>tempUSBEndPTransTypeReg</span>;
+      <span id=t_idt>next_endPMuxErrorsWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>FIN_SC</span>;
+   `<span id=t_idt>SETUP_OUT_CHK</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_READY_BIT</span>] == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_SEND</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>NAK</span>;
+      <span id=t_idt>next_NAKSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_SEND_STALL_BIT</span>] == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_SEND</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>STALL</span>;
+      <span id=t_idt>next_stallSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_SEND</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>ACK</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_OUT_SEND</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>SETUP_OUT_GET_PKT</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> ((<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>CRCError</span> == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>bitStuffError</span> == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RxOverflow</span> == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RxTimeOut</span> == <span id=t_cns>1'b0</span>)) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>SETUP_OUT_CHK</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_NAK_STALL</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_CHK_RDY</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_READY_BIT</span>] == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_NAK_STALL</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>NAK</span>;
+      <span id=t_idt>next_NAKSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_SEND_STALL_BIT</span>] == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_NAK_STALL</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>STALL</span>;
+      <span id=t_idt>next_stallSent</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>USBEndPControlReg</span> [`<span id=t_idt>ENDPOINT_OUTDATA_SEQUENCE_BIT</span>] == <span id=t_cns>1'b0</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_DATA</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA0</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_DATA</span>;
+      <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b1</span>;
+      <span id=t_idt>next_sendPacketPID</span> &lt;= `<span id=t_idt>DATA1</span>;
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_DATA</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>sendPacketRdy</span> == <span id=t_cns>1'b1</span>) 
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>IN_GET_RESP</span>;
+      <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>IN_GET_RESP</span>:
+   <span id=t_kwd>begin</span>
+     <span id=t_idt>next_getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+     <span id=t_kwd>if</span> (<span id=t_idt>getPacketRdy</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_RDY</span>;
+   <span id=t_kwd>end</span>
+   `<span id=t_idt>START_S1</span>:
+     <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>GET_TOKEN_WAIT_CRC</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_WAIT_STOP</span>;
+      <span id=t_idt>next_endpCRCTemp</span> &lt;= <span id=t_idt>RxByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> != `<span id=t_idt>RX_PACKET_STREAM</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>GET_TOKEN_WAIT_ADDR</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> == `<span id=t_idt>RX_PACKET_STREAM</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_WAIT_CRC</span>;
+      <span id=t_idt>next_addrEndPTemp</span> &lt;= <span id=t_idt>RxByte</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span> &amp;&amp; 
+      <span id=t_idt>RxStatus</span> != `<span id=t_idt>RX_PACKET_STREAM</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>GET_TOKEN_WAIT_STOP</span>:
+     <span id=t_kwd>if</span> ((<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span>) &amp;&amp; (<span id=t_idt>RxByte</span>[`<span id=t_idt>CRC_ERROR_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RxByte</span>[`<span id=t_idt>BIT_STUFF_ERROR_BIT</span>] == <span id=t_cns>1'b0</span> &amp;&amp;
+      <span id=t_idt>RxByte</span> [`<span id=t_idt>RX_OVERFLOW_BIT</span>] == <span id=t_cns>1'b0</span>)) 
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_CHK_SOF</span>;
+     <span id=t_kwd>else</span> <span id=t_kwd>if</span> (<span id=t_idt>RxDataWEn</span> == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+   `<span id=t_idt>GET_TOKEN_CHK_SOF</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>PIDByte</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>] == `<span id=t_idt>SOF</span>)  
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+      <span id=t_idt>next_frameNum</span> &lt;= {<span id=t_idt>endpCRCTemp</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>],<span id=t_idt>addrEndPTemp</span>};
+      <span id=t_idt>next_SOFRxed</span> &lt;= <span id=t_cns>1'b1</span>;
+     <span id=t_kwd>end</span>
+     <span id=t_kwd>else</span>
+     <span id=t_kwd>begin</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_DELAY</span>;
+      <span id=t_idt>next_USBAddress</span> &lt;= <span id=t_idt>addrEndPTemp</span>[<span id=t_cns>6</span>:<span id=t_cns>0</span>];
+      <span id=t_idt>next_USBEndP</span> &lt;= { <span id=t_idt>endpCRCTemp</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>], <span id=t_idt>addrEndPTemp</span>[<span id=t_cns>7</span>]};
+     <span id=t_kwd>end</span>
+   `<span id=t_idt>GET_TOKEN_DELAY</span>:   <span id=t_com>// Insert delay to allow USBEndPControlReg to update</span>
+     <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>GET_TOKEN_CHK_ADDR</span>;
+   `<span id=t_idt>GET_TOKEN_CHK_ADDR</span>:
+     <span id=t_kwd>if</span> (<span id=t_idt>USBEndP</span> &lt; `<span id=t_idt>NUM_OF_ENDPOINTS</span>  &amp;&amp;
+      <span id=t_idt>USBAddress</span> == <span id=t_idt>USBTgtAddress</span> &amp;&amp;
+      <span id=t_idt>SCGlobalEn</span> == <span id=t_cns>1'b1</span> &amp;&amp;
+      <span id=t_idt>USBEndPControlReg</span>[`<span id=t_idt>ENDPOINT_ENABLE_BIT</span>] == <span id=t_cns>1'b1</span>)  
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>CHK_PID</span>;
+     <span id=t_kwd>else</span>
+      <span id=t_idt>NextState_slvCntrl</span> &lt;= `<span id=t_idt>WAIT_RX1</span>;
+  <span id=t_kwd>endcase</span>
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Current State Logic (sequential)</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvCntrl_CurrentState</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+   <span id=t_idt>CurrState_slvCntrl</span> &lt;= `<span id=t_idt>START_S1</span>;
+  <span id=t_kwd>else</span>
+   <span id=t_idt>CurrState_slvCntrl</span> &lt;= <span id=t_idt>NextState_slvCntrl</span>;
+<span id=t_kwd>end</span>
+
+<span id=t_com>//----------------------------------</span>
+<span id=t_com>// Registered outputs logic</span>
+<span id=t_com>//----------------------------------</span>
+<span id=t_kwd>always</span> @ (<span id=t_kwd>posedge</span> <span id=t_idt>clk</span>)
+<span id=t_kwd>begin</span> : <span id=t_idt>slvCntrl_RegOutput</span>
+  <span id=t_kwd>if</span> (<span id=t_idt>rst</span>) 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>tempUSBEndPTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>addrEndPTemp</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>endpCRCTemp</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>USBAddress</span> &lt;= <span id=t_cns>7'b0000000</span>;
+   <span id=t_idt>PIDByte</span> &lt;= <span id=t_cns>8'h00</span>;
+   <span id=t_idt>transDone</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>getPacketREn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_cns>4'b0</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>clrEPRdy</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>USBEndPTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>USBEndPNakTransTypeReg</span> &lt;= <span id=t_cns>2'b00</span>;
+   <span id=t_idt>NAKSent</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>stallSent</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>SOFRxed</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>endPMuxErrorsWEn</span> &lt;= <span id=t_cns>1'b0</span>;
+   <span id=t_idt>frameNum</span> &lt;= <span id=t_cns>11'b00000000000</span>;
+   <span id=t_idt>USBEndP</span> &lt;= <span id=t_cns>4'h0</span>;
+  <span id=t_kwd>end</span>
+  <span id=t_kwd>else</span> 
+  <span id=t_kwd>begin</span>
+   <span id=t_idt>tempUSBEndPTransTypeReg</span> &lt;= <span id=t_idt>next_tempUSBEndPTransTypeReg</span>;
+   <span id=t_idt>addrEndPTemp</span> &lt;= <span id=t_idt>next_addrEndPTemp</span>;
+   <span id=t_idt>endpCRCTemp</span> &lt;= <span id=t_idt>next_endpCRCTemp</span>;
+   <span id=t_idt>USBAddress</span> &lt;= <span id=t_idt>next_USBAddress</span>;
+   <span id=t_idt>PIDByte</span> &lt;= <span id=t_idt>next_PIDByte</span>;
+   <span id=t_idt>transDone</span> &lt;= <span id=t_idt>next_transDone</span>;
+   <span id=t_idt>getPacketREn</span> &lt;= <span id=t_idt>next_getPacketREn</span>;
+   <span id=t_idt>sendPacketPID</span> &lt;= <span id=t_idt>next_sendPacketPID</span>;
+   <span id=t_idt>sendPacketWEn</span> &lt;= <span id=t_idt>next_sendPacketWEn</span>;
+   <span id=t_idt>clrEPRdy</span> &lt;= <span id=t_idt>next_clrEPRdy</span>;
+   <span id=t_idt>USBEndPTransTypeReg</span> &lt;= <span id=t_idt>next_USBEndPTransTypeReg</span>;
+   <span id=t_idt>USBEndPNakTransTypeReg</span> &lt;= <span id=t_idt>next_USBEndPNakTransTypeReg</span>;
+   <span id=t_idt>NAKSent</span> &lt;= <span id=t_idt>next_NAKSent</span>;
+   <span id=t_idt>stallSent</span> &lt;= <span id=t_idt>next_stallSent</span>;
+   <span id=t_idt>SOFRxed</span> &lt;= <span id=t_idt>next_SOFRxed</span>;
+   <span id=t_idt>endPMuxErrorsWEn</span> &lt;= <span id=t_idt>next_endPMuxErrorsWEn</span>;
+   <span id=t_idt>frameNum</span> &lt;= <span id=t_idt>next_frameNum</span>;
+   <span id=t_idt>USBEndP</span> &lt;= <span id=t_idt>next_USBEndP</span>;
+  <span id=t_kwd>end</span>
+<span id=t_kwd>end</span>
+
+<span id=t_kwd>endmodule</span>
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram1.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveGetpacket" alt="slaveGetpacket"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/diagram1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_GET_TOKEN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_GET_TOKEN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_PROC_PKT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/slaveGetpacket_PROC_PKT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar58.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar58.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar58.html	(revision 264)
@@ -0,0 +1,48 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 1;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(662,1601,764,1703,Click112,Over112);
+
+//----------------------------------------------------------------------------
+function Click112(){fubclick('./index112.htm');}
+function Over112(){window.status='Hierarchical State LOOP';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 58 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveGetpacket_DATA.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveGetpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveGetpacket.asf/toolbar58.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram45.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram45.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram45.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slaveSendpacket SP_D0_D1" alt="slaveSendpacket SP_D0_D1"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/diagram45.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,57 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 4;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(828,652,930,755,Click15,Over15);
+FUB[1] = new Array(449,1580,551,1683,Click551,Over551);
+FUB[2] = new Array(1339,1543,1441,1645,Click580,Over580);
+FUB[3] = new Array(949,1090,1051,1193,Click376,Over376);
+
+//----------------------------------------------------------------------------
+function Click15(){fubclick('./index15.htm');}
+function Over15(){window.status='Hierarchical State START';};
+function Click551(){fubclick('./index551.htm');}
+function Over551(){window.status='Hierarchical State SETUP_OUT';};
+function Click580(){fubclick('./index580.htm');}
+function Over580(){window.status='Hierarchical State IN';};
+function Click376(){fubclick('./index376.htm');}
+function Over376(){window.status='Hierarchical State GET_TOKEN';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/slaveSendpacket.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html	(revision 264)
@@ -0,0 +1,51 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 2;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+FUB[0] = new Array(844,1410,946,1513,Click21,Over21);
+FUB[1] = new Array(1383,1786,1485,1889,Click45,Over45);
+
+//----------------------------------------------------------------------------
+function Click21(){fubclick('./index21.htm');}
+function Over21(){window.status='Hierarchical State SP_SEND_PID';};
+function Click45(){fubclick('./index45.htm');}
+function Over45(){window.status='Hierarchical State SP_D0_D1';};
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 1 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slaveSendpacket.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slaveSendpacket.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slaveSendpacket.asf/toolbar1.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram15.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram15.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram15.html	(revision 264)
@@ -0,0 +1,70 @@
+<html>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+
+<script language="JavaScript">
+//----------------------------------------------------------------------------
+	function XNotify() {parent.SchemOn();}
+	function Mapper(arg) {if(GetMouseXY(arg)==0)return;parent.Mapper(MouseX,MouseY);}
+	function MapperOver(arg) {if(GetMouseXY(arg)==0)return;parent.MapperOver(MouseX,MouseY);}
+//----------------------------------------------------------------------------
+if(!ie)
+{
+	document.captureEvents(Event.MOUSEMOVE | Event.CLICK | Event.ONLOAD);
+	document.onmousemove = MapperOver;
+	document.onclick = Mapper;
+	document.onload = XNotify;
+}
+//----------------------------------------------------------------------------
+var MouseX=0;
+var MouseY=0;
+//----------------------------------------------------------------------------
+function GetMouseXY(arg) 
+{
+	var x;var y;var flag=1;
+	if(!nn & !ie){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(nn){
+		x = arg.pageX - document.images["DIAGRAM"].x;
+		y = arg.pageY - document.images["DIAGRAM"].y;
+		if(!x || !y)
+			flag=0; // Refresh in NN6
+	}
+	if(ie){
+		x = event.offsetX;
+		y = event.offsetY;
+	}
+	if(flag==0)
+		return 0;
+	MouseX=x;
+	MouseY=y;
+	return 1;
+}
+
+</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0"
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+
+<table width="100%" height="100%"  border="0" cellspacing="0" cellpadding="0" valign="center" align="center" background="silver">
+
+<tr background="silver" align="absmiddle" >
+       <td background="silver" align="middle">
+	   	   <img	id="ME" name="DIAGRAM" background="silver"  
+				longdesc="slavecontroller START" alt="slavecontroller START"
+				width=1020 height=1320 
+				hspace="0" vspace="0" border="0" 
+				align="absmiddle"
+				onClick="Mapper(this)" onMouseMove="MapperOver(this)"				
+			>
+	   </td>
+</tr>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/diagram15.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar1.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram1.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index580.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index580.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index580.htm	(revision 264)
@@ -0,0 +1,31 @@
+<html>
+
+<head>
+	<meta http-equiv="Content-Type" content="text/html; charset=windows-1251">
+	<title></title>
+	<meta name="GENERATOR" content="Aldec.FSM">
+	<meta name="ProgId" content="Aldec.FSM">
+</head>
+
+<script>
+	var m_tools = 0;
+	var m_schem = 0;
+	function ToolsOn() {m_tools=1;StartIt();}
+	function SchemOn() {m_schem=1;StartIt();}
+	function Plugged() {return (m_tools==1 && m_schem==1)?1:0;}
+	function StartIt() {if(Plugged()) frames["tools"].Init();}
+	function Mapper(MouseX,MouseY) {if(Plugged())frames["tools"].Mapper(MouseX,MouseY);}
+	function MapperOver(MouseX,MouseY) {if(Plugged())frames["tools"].MapperOver(MouseX,MouseY);}
+</script>
+
+<frameset rows="22,*" border="0" frameborder="0" framespacing="0" title="FSM">
+	<frame name="tools" scrolling="no" noresize="noresize" src="./toolbar580.html" marginwidth="0" marginheight="0">
+	<frame name="xschem" scrolling="auto" noresize="resize" src="./diagram580.html" marginwidth="0" marginheight="0">
+	<noframes>
+		<body>
+			<p>This page uses frames, but your browser doesn't support them. <br></p>
+		</body>
+	</noframes>
+</frameset>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/index580.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_IN.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_IN.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar580.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar580.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar580.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 580 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller_IN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar580.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/struct/bdetools.js
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/struct/bdetools.js	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/struct/bdetools.js	(revision 264)
@@ -0,0 +1,467 @@
+var zoo = 100;
+var pzoo = 100;
+var zoom_inc = 2; //or 4
+var SCHEM = "DDT"
+var ViewX=w;
+var ViewY=h;
+var DEBUG_MODE = 1;
+var koef=2/(4400/w);
+//----------------------------------------------------------------------------
+IRoot = RootProject + "images/bde/";
+OV = "over.gif";
+OD = "down.gif";
+//----------------------------------------------------------------------------
+function CodeView(){
+window.parent.location = SchemCode;
+}
+//----------------------------------------------------------------------------
+function GotoPage(){
+	if(PageNext==-1){
+		alert("no page");
+		return;
+	}
+window.parent.location = "./content"+PageNext+".html"
+}
+//----------------------------------------------------------------------------
+function fubclick(lnk){
+	if(lnk!="")
+		window.parent.parent.location = lnk;
+}
+//----------------------------------------------------------------------------
+function DUMP() { 
+	var dump_msg;
+	dump_msg= "w.........."+w+"\n";
+	dump_msg+="h.........."+h+"\n";
+	dump_msg+="zoo........"+zoo+"\n";
+	dump_msg+="pzoo......."+pzoo+"\n";
+	dump_msg+="zoo_inc...."+zoom_inc+"\n";
+	dump_msg+="schem......"+SCHEM+"\n";
+	dump_msg+="viewx......"+ViewX+"\n";
+	dump_msg+="viewy......"+ViewY+"\n";
+	dump_msg+="pagex......"+PageX+"\n";
+	dump_msg+="pagey......"+PageY+"\n";
+	dump_msg+="IE........."+ie+"\n";
+	dump_msg+="NN........."+nn+"\n";
+	alert(dump_msg);
+}
+function alertd(msg) {
+	if(DEBUG_MODE==1)
+		alert(msg)
+}
+//----------------------------------------------------------------------------
+var MyImage;
+var MyDoc;
+var MyWindow;
+//----------------------------------------------------------------------------
+function Init(){
+MyImage = window.parent.frames["xschem"].window.document.images[SCHEM];
+MyImage.src = SchemImage.src;
+MyDoc = window.parent.frames["xschem"].window.document;
+MyWindow =  window.parent.frames["xschem"].window;
+//zoomfull();
+//�������� - � ��, �᫨ ��࠭�� �� ����㦥��?
+//alert("init")
+}
+//----------------------------------------------------------------------------
+function ZRefresh(){
+	ViewX = w*zoo/100;
+	ViewY = h*zoo/100;
+
+	if(ViewX<=0 || ViewY<=0 || ViewX==NaN || ViewY==NaN){
+		alertd("Z-Error: " + ViewX + "##" + ViewY + "##" + zoo + "##" + pzoo);
+		DUMP();
+		ViewX=w;
+		ViewX=h;
+		zoo=100;
+		pzoo=100;		
+	}
+
+//	if ((ViewX>(w/koef)) || (ViewY>(h/koef))){
+//		ViewX=w/koef;
+//		ViewY=h/koef;
+//	}
+
+	MyImage.width  = ViewX;
+	MyImage.height = ViewY;
+
+	if(!ie&&!nn) //NN6
+		MyImage.src = SchemImage.src;
+	if(ie){
+		window.top.resizeBy(1, 1);  
+		window.top.resizeBy(-1, -1);
+	}
+}
+function zoomin(){
+	pzoo=zoo;
+	zoo*=zoom_inc;
+	ZRefresh();
+}
+function zoomout(){
+	if(zoo<=zoom_inc) return;
+	pzoo=zoo;
+	zoo/=zoom_inc;
+	ZRefresh();
+}
+function zoomfit(){	
+	pw=w;ph=h;
+	var cw;var ch;
+	if(ie || nn){
+		if(!MyDoc.body.clientWidth) {
+
+			if (self.screen) { // for NN4 and IE4 
+				cw = screen.width/1.5 ; // What can I do for Opera
+				ch = screen.height/1.5; // What can I do for Opera
+			} else if (self.java) { // for NN3 with enabled Java 
+				var jkit = java.awt.Toolkit.getDefaultToolkit(); 
+				var scrsize = jkit.getScreenSize(); 
+				cw = scrsize.width; 
+				ch = scrsize.height; 
+			} else
+				{
+					cw = w;
+					ch = h
+				} 
+		} 
+
+		else //FOR TRUE IE!!! with clientWidth
+		{	
+			cw=MyDoc.body.clientWidth;
+			ch=MyDoc.body.clientHeight;
+
+			if (Math.round(ViewY)>ch) ch=ch+16;
+			if (Math.round(ViewX)>cw) cw=cw+16;
+			
+		}
+	} else { //for TRUE NN :-) cheak It!!!
+		//alertd("nn"); //NN6 use it		
+		cw=MyWindow.innerWidth*95/100;
+		ch=MyWindow.innerHeight*95/100;
+		//alertd("cw"+cw);
+		//alertd(""ch);
+	}
+
+	fw=100*(cw/pw);
+	fh=100*(ch/ph);
+	xzoo=fh;
+	if(fw<fh)
+		xzoo=fw;
+	if(xzoo==zoo)
+		return;
+	pzoo=zoo;
+	zoo=xzoo;
+	ZRefresh();
+}
+function zoomfull(){
+	pzoo=zoo;
+	zoo=100;
+	ZRefresh();
+}
+function zoomprev(){
+	tmp=zoo;
+	zoo=pzoo;
+	pzoo=tmp;
+	ZRefresh();
+}
+//----------------------------------------------------------------------------
+// Buttons of ToolBar
+//----------------------------------------------------------------------------
+BT_TITL = 0
+BT_ZMIN = 1
+BT_ZOUT = 2
+BT_ZFIT = 3
+BT_FULL = 4
+BT_PREV = 5
+BT_CODE = 6
+BT_PAGE = 7
+BT_PMOD = 8
+BT_ZMOD = 9
+BT_SMOD =10
+BT_OBJV =11
+BT_POPP =12 
+BT_PRNT =13
+BT_NEWW =14
+BT_SYSB =15
+//----------------------------------------------------------------------------
+NRM = 0;
+OVR = 1;
+DWN = 2;
+MES = 3;
+//----------------------------------------------------------------------------
+BT_NUMBER = 16;
+//----------------------------------------------------------------------------
+IMRES = new Array()//0..15 images is here
+Present = new Array(1,1,1,0,1, 1,0,0,0,0, 0,0,0,0,1, 1)//{1/0} boolean of visibility
+//----------------------------------------------------------------------------
+function mClick(i){
+	switch(i)
+	{
+		case BT_TITL: return;
+		case BT_ZMIN: zoomin();return;
+		case BT_ZOUT: zoomout();return;
+		case BT_ZFIT: zoomfit();return;
+		case BT_FULL: zoomfull();return;
+		case BT_PREV: zoomprev();return;
+		case BT_CODE: CodeView();return;
+		case BT_PAGE: GotoPage();return;
+		case BT_PMOD: Grosser(window.top);//Grosser();
+						window.top.resizeBy(1, 1);window.resizeBy(-1, -1); //!!!
+					  return;
+		case BT_ZMOD: return;
+		case BT_SMOD: view_source();return;
+		case BT_OBJV: DUMP();return;
+		case BT_SYSB: if (ie) {window.parent.close();void(0);}
+				if (!ie) {
+if (window.parent.parent.parent.document.title=="") {window.parent.close();void(0);}}
+					  return;
+		case BT_NEWW: fullScreen2(window.parent.location);
+						//window.parent.frames["xschem"].window.document.images[SCHEM].src = SchemImage.src;
+						return;
+		case BT_PRNT: printit();return;
+		case BT_POPP: alert(":-(");return;
+	}
+}
+//----------------------------------------------------------------------------
+function mOver(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][OVR].src;
+	SetStatus(IMRES[i][MES]);
+}
+//----------------------------------------------------------------------------
+function mOut(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][NRM].src;
+	SetStatus("");
+}
+//----------------------------------------------------------------------------
+function mDown(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][DWN].src;
+	SetStatus(IMRES[i][MES]);
+}
+//----------------------------------------------------------------------------
+function mUp(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][OVR].src;
+}
+//----------------------------------------------------------------------------
+function GetBod(i)
+	{
+	switch(i)
+	{	case BT_TITL: return "bar"
+		case BT_ZMIN: return "zoomin"
+		case BT_ZOUT: return "zoomout"
+		case BT_ZFIT: return "fit"
+		case BT_FULL: return "full"
+		case BT_CODE: return "code"
+		case BT_PREV: return "prev"
+		case BT_PAGE: return "goto"
+		case BT_PMOD: return "panmode"
+		case BT_ZMOD: return "zoommode"
+		case BT_SMOD: return "selectmode"
+		case BT_OBJV: return "tbl"
+		case BT_SYSB: return "frame"
+		case BT_NEWW: return "newwindow"
+		case BT_PRNT: return "print"
+		case BT_POPP: return "pop"
+	}
+	return "blank"
+}
+//----------------------------------------------------------------------------
+function GetFile(i, mode)
+	{
+	var bod = GetBod(i)
+	var end; 
+	switch(mode)
+	{	case NRM: end=".gif";break;
+		case OVR: end=OV;break;
+		case DWN: end=OD;
+	}
+	return IRoot + bod + end; 
+}
+//----------------------------------------------------------------------------
+function GetIMessage(i){
+	switch(i)
+	{
+		case BT_ZMIN: return "Zooms in view"
+		case BT_ZOUT: return "Zooms out view"
+		case BT_ZFIT: return "Zooms to fit"
+		case BT_FULL: return "Displays full page"
+		case BT_CODE: return "View generated code"
+		case BT_PREV: return "Displays previously visible area"
+		case BT_PAGE: return "Go to page"
+		case BT_PMOD: return "Enter panning mode"
+		case BT_ZMOD: return "Enter zoom mode"
+		case BT_SMOD: return "Enter select mode"
+		case BT_OBJV: return "Show Objects Window"
+		case BT_NEWW: return "Open in new window"
+		case BT_SYSB: return "Close newly opened window"
+		case BT_PRNT: return "Print"
+		case BT_POPP: return "Enters an upper hierarchical level"
+	}
+	return ""
+}
+//----------------------------------------------------------------------------
+for(i=0;i<BT_NUMBER;i++){
+	IMRES[i] = new Array(new Image(),new Image(),new Image(),"");
+}
+//----------------------------------------------------------------------------
+for(i=0;i<BT_NUMBER;i++){
+	IMRES[i][NRM].src = GetFile(i,NRM);
+	IMRES[i][OVR].src = GetFile(i,OVR);
+	IMRES[i][DWN].src = GetFile(i,DWN);
+	IMRES[i][MES]     = GetIMessage(i);
+//	IMRES[i][HNT]     = GetIHint(i);
+}
+//----------------------------------------------------------------------------
+function GetToolBar(){
+	var tools;
+	var open = '<table align="left" border="0" cellspacing="0" cellpadding="0" valign="center" align="center"> <tr bgcolor="silver" background="silver" bordercolordark="silver" >';
+	var close = '</tr></table>';
+
+	var std0 = '<td ><img hspace="0" vspace="0" border="0" align="absmiddle" ';
+	var std1= 'width=24 height=22 ';
+	var std2 = '></td>';
+
+	tools = open;
+	for(i=0;i<BT_NUMBER;i++){
+		if(Present[i]){
+			tools+=std0;
+			if(i!=BT_SYSB && i!=BT_TITL)
+				tools+=std1;
+			//tools+='src='+ GetINorm(i) + ' ';
+			tools+='src="'+ IMRES[i][NRM].src + '" ';
+			tools+=	'onClick="mClick('    + i + ')" ';
+			tools+=	'onMouseDown="mDown(' + i + ')" ';
+			tools+=	'onMouseUp="mUp(' + i + ')" ';
+			tools+=	'onMouseOver="mOver(' + i + ')" ';
+			tools+=	'onMouseOut="mOut('   + i + ')" ';	//	tools+='name="btn_' + i +'" '
+			tools+=	'name="btn_' + i +'" ';
+			tools+= 'alt="'+GetIMessage(i)+'" ';
+			tools+=std2;								
+		}
+	}
+	tools += close;
+
+	return tools;
+}
+//----------------------------------------------------------------------------
+var NIL = -1;
+//----------------------------------------------------------------------------
+function InRect(x,y,left,top,right,bottom) {
+	if(x>=left && x<=right && y>=top  && y<=bottom)
+		return 1;
+	return 0;	
+}
+//----------------------------------------------------------------------------
+function GetSender(x,y) {
+	for(i=0;i<FUBSNUMBER;i++) {
+		var left  = FUB[i][0];
+		var top   = FUB[i][1];
+		var right = FUB[i][2];
+		var bottom= FUB[i][3];
+
+	factor = PageX / ViewX;
+
+	xx = x*factor;
+	yy = y*factor;
+
+		if(InRect(xx,yy,left,top,right,bottom))
+			return i;
+	}
+	return NIL;
+}
+//----------------------------------------------------------------------------
+function Mapper(MouseX,MouseY) {
+	var SENDER = GetSender(MouseX,MouseY);
+	if(SENDER != NIL){
+		FUB[SENDER][4]();		
+	}
+}
+//----------------------------------------------------------------------------
+function MapperOver(MouseX,MouseY) {
+	var SENDER = GetSender(MouseX,MouseY);
+	if(SENDER != NIL){
+		FUB[SENDER][5]();
+		SetCursor("hand");
+	}
+	else {
+		SetStatus("");
+		SetCursor("default");
+	}
+	
+}
+//----------------------------------------------------------------------------
+function SetStatus(status){
+	if(window.top.status!=status){
+		window.top.status=status;
+		}
+}
+//----------------------------------------------------------------------------
+function SetCursor(cursor){
+	if(ie){
+		if(MyImage.style.cursor!=cursor)
+			MyImage.style.cursor=cursor;
+	} else {
+		; 
+	}
+}
+//----------------------------------------------------------------------------
+function Grosser(Who) { //in Opera - MDI - some bugs :-( but Ok . IE - nok. NN6 - ok
+	//window.moveTo(0,0);
+//	window.resizeTo(screen.availWidth,screen.availHeight);
+	Who.moveTo(0,0);
+	Who.resizeTo(screen.availWidth,screen.availHeight);
+}
+//----------------------------------------------------------------------------
+function fullScreen2(theURL) {
+	window.open(theURL, '', 'fullscreen=yes,scrollbars=yes,status=yes,resizable=yes,location=yes');
+}
+//----------------------------------------------------------------------------
+function boom(n){
+	if (window.top.moveBy)
+	{
+		for (i = 10; i > 0; i--){
+			for (j = n; j > 0; j--){
+				window.top.moveBy(0,i);
+				window.top.moveBy(i,0);
+				window.top.moveBy(0,-i);
+				window.top.moveBy(-i,0);
+			}//for
+		}//for
+	}//if
+}
+//----------------------------------------------------------------------------
+function view_source(){ //Opera - nok; IE - ok. NN6 - ok.
+MyWindow.location = "view-source:" + MyWindow.location.href;
+} 
+//----------------------------------------------------------------------------
+function printit(){
+	var browser_name = navigator.appName;
+	if (browser_name == "Netscape") {
+    	MyWindow.print() ;
+	} else {
+    	var WebBrowser = '<object id="WebBrowser1" width=0 height=0 classid="clsid:8856F961-340A-11D0-A96B-00C04FD705A2"></object>';
+	    document.body.insertAdjacentHTML('beforeEnd', WebBrowser);
+    	WebBrowser1.ExecWB(6, 2);
+	}
+}
+
+
+
+

Property changes on: common/components/usbhostslave/tags/start/doc/html/struct/bdetools.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/struct/map.js
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/struct/map.js	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/struct/map.js	(revision 264)
@@ -0,0 +1,249 @@
+
+// styles definition
+
+document.writeln ('<style>');
+document.writeln ('body    { font-size: 12px }');
+document.writeln ('#tree   { font-size: 12px }');
+document.writeln ('#folder { cursor: hand }');
+document.writeln ('a { color: #000080; text-decoration: none }');
+document.writeln ('</style>');
+
+// paths
+
+if ((ie) || (nn))
+{
+	var TreePath = "./images/tree/";
+	var ExtPath = "./images/ext/";
+	var DocPath = "./../src/";
+}
+if ((!ie) && (!nn))
+{
+	var TreePath = "./../images/tree/";
+	var ExtPath = "./../images/ext/";
+	var DocPath = "./../src/";
+}
+
+
+// preloading images
+
+Empty = new Image ();
+
+Join = new Image ();
+JoinBottom = new Image ();
+JoinTop = new Image ();
+JoinLeft = new Image ();
+
+Line = new Image ();
+
+Minus = new Image ();
+MinusBottom = new Image ();
+MinusOnly = new Image ();
+MinusTop = new Image ();
+
+Plus = new Image ();
+PlusBottom = new Image ();
+PlusOnly = new Image ();
+PlusTop = new Image ();
+
+FolderOpened = new Image ();
+FolderClosed = new Image ();
+
+Project = new Image ();
+
+VHD = new Image ();VHDL = new Image ();//VHDL Source cod
+V = new Image (); //Verilog Source cod
+EDN = new Image (); //edif...
+BDE = new Image ();
+AWF = new Image ();
+ASF = new Image (); //"State diagram"
+LST = new Image ();
+TXT = new Image ();
+PL = new Image ();
+TCL = new Image ();
+DO = new Image ();
+CPP = new Image ();
+SDF = new Image (); //"SDF File"
+
+XNF = new Image (); //"XNF Netlist"
+VLS = new Image (); //"ViewLogic Schematic"
+VTB = new Image (); //"VHDL Test bench"  || "Verilog Test bench"
+HTM = new Image ();HTML = new Image ();   //"HTML Document"
+BAS = new Image ();
+UND = new Image (); //undefined        || "External File"
+
+CONF = new Image (); //"Configuration file"
+DRW = new Image (); //"Drawing" ????
+SYMB = new Image (); //"Symbol Sheet" ????
+
+ACP = new Image (); //Active-CAD Project
+AHW = new Image (); //Active-HDL Workspace
+
+///////////////////////////////////////////
+Empty.src = TreePath + "empty.gif";
+
+Join.src = TreePath + "join.gif";
+JoinBottom.src = TreePath + "join_b.gif";
+JoinTop.src = TreePath + "join_t.gif";
+JoinLeft.src = TreePath + "join_l.gif";
+
+Line.src = TreePath + "line.gif";
+
+Minus.src = TreePath + "minus.gif";
+MinusBottom.src = TreePath + "minus_b.gif";
+MinusOnly.src = TreePath + "minus_o.gif";
+MinusTop.src = TreePath + "minus_t.gif";
+
+Plus.src = TreePath + "plus.gif";
+PlusBottom.src = TreePath + "plus_b.gif";
+PlusOnly.src = TreePath + "plus_o.gif";
+
+FolderOpened.src = TreePath + "folder_o.gif";
+FolderClosed.src = TreePath + "folder_c.gif";
+///////////////////////////////////////////
+Project.src = TreePath + "project.gif";
+///////////////////////////////////////////
+VHD.src = ExtPath + "vhd.gif";
+V.src = ExtPath + "v.gif";
+EDN.src = ExtPath + "edn.gif";
+BDE.src = ExtPath + "bde.gif";
+AWF.src = ExtPath + "awf.gif";
+ASF.src = ExtPath + "asf.gif";
+LST.src = ExtPath + "lst.gif";
+TXT.src = ExtPath + "txt.gif";
+PL.src = ExtPath + "pl.gif";
+TCL.src = ExtPath + "tcl.gif";
+DO.src = ExtPath + "do.gif";
+CPP.src = ExtPath + "cpp.gif";
+SDF.src = ExtPath + "sdf.gif";
+
+XNF.src = ExtPath + "xnf.gif";
+VLS.src = ExtPath + "vls.gif"; 
+VTB.src = ExtPath + "vtb.gif"; 
+HTM.src = ExtPath + "htm.gif"; HTML.src = HTM.src;
+BAS.src = ExtPath + "bas.gif"; 
+UND.src = ExtPath + "und.gif"; 
+
+CONF.src = ExtPath + "conf.gif"; 
+DRW.src = ExtPath + "drw.gif"; 
+SYMB.src = ExtPath + "symb.gif"; 
+
+ACP.src = ExtPath + "acp.gif"; 
+AHW.src = ExtPath + "ahw.gif"; 
+
+// working with tree
+
+function BeginTree ()
+ {
+  return '<table width="95%" cellspacing="0" cellpadding="0" border="0"><tbody align="left" valign="middle">';
+ }
+
+function EndTree ()
+ {
+  return '</table>';
+ }
+
+function FirstCreateTree()
+{
+  window.frames["Map"].document.writeln(DrawMapTree());
+}
+
+function CreateTree ()
+ {
+  if (!ie)
+  {
+  window.frames["Map"].document.open();
+  window.frames["Map"].document.writeln("<html>");
+  window.frames["Map"].document.writeln ('<style>');
+  window.frames["Map"].document.writeln ('body    { font-size: 12px }');
+  window.frames["Map"].document.writeln ('#tree   { font-size: 12px }');
+  window.frames["Map"].document.writeln ('#folder { cursor: hand }');
+  window.frames["Map"].document.writeln ('a { color: #000080; text-decoration: none }');
+  window.frames["Map"].document.writeln ('</style>');
+  window.frames["Map"].document.writeln("<body background=\"./../images/aldec.gif\" bgproperties=\"fixed\">");
+  window.frames["Map"].document.writeln("<script language=\"JavaScript\">");
+  window.frames["Map"].document.writeln("<!--");
+  for(i=0;i<Expanded.length;++i)
+    window.frames["Map"].document.writeln("parent.Expanded["+i+"]="+Expanded[i]+";");  
+  window.frames["Map"].document.writeln("//-->");
+  window.frames["Map"].document.writeln("</script>");
+  window.frames["Map"].document.writeln(DrawMapTree());
+  window.frames["Map"].document.writeln("</body>");
+  window.frames["Map"].document.writeln("</html>");
+  window.frames["Map"].document.close();
+  }
+  else
+    window.frames["Map"].document.body.innerHTML = DrawMapTree ();
+ }
+
+ function CollapseIt ()
+ {
+  for(i=0;i<Expanded.length;++i)
+   Expanded[i]=false;  
+  CreateTree();
+ }
+
+ function ExpandIt ()
+ {
+  for(i=0;i<Expanded.length;++i)
+   Expanded[i]=true;  
+  CreateTree();
+ }
+
+ function NormalIt ()
+ {
+  for(i=0;i<Expanded.length;++i)
+   Expanded[i]=false;
+  Expanded[0]=true;
+  CreateTree();
+ }
+
+// working with group
+
+function Invert (Number)
+ {
+   Expanded[Number] = ! Expanded[Number];
+   CreateTree ();
+ }
+
+function BR ()
+ {
+  return '<tr><td id=tree><nobr>';
+ }
+
+function ER ()
+ {
+  return '</nobr></td></tr>';
+ }
+
+// working with elements
+
+function Ver (ImgName,Number)
+ {
+  if (Number != -1)
+    return '<a href="#"  onClick="parent.Invert('+Number+');"><img border=0 src="' + ImgName.src + '" width=18 height=20 align=left hspace=0 vspace=0></a>';
+  else
+  return '<img src="' + ImgName.src + '" width=18 height=20 align=left hspace=0 vspace=0>';
+ }
+
+function Ext (ImgName)
+ {
+  return '<img src="' + ImgName.src + '" width=18 height=16 align=left hspace=0 vspace=0>';
+ }
+
+function Tit (Name, URL, Type)
+ {
+  if (Type != "folder")
+   {
+    var URL_doc = DocPath + URL;
+    if ((Type != "project")&&(Type != "HTM"))
+     URL_doc += "/index.htm";
+    if (Type=="project")
+    return ' <a href=' + "./../info/index.htm"+ ' class=k target="Information">' + Name + '</a>';
+    
+    if ((Type!="project")&&(URL==""))
+     return '<font color="#888888"> '+Name;
+    else
+     return ' <a href=' + URL_doc + ' class=k target="Information">' + Name + '</a>';
+   }
+  return Name;
+ }

Property changes on: common/components/usbhostslave/tags/start/doc/html/struct/map.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_START.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_START.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar551.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar551.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar551.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 551 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller_SETUP_OUT.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar551.html
___________________________________________________________________
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/struct/aldec.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/struct/aldec.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/struct/aldec.htm	(revision 264)
@@ -0,0 +1,6 @@
+<html>
+<body bgcolor=blue background="./../images/logoback.bmp" leftmargin="0" topmargin="0" rightmargin="0"
+bottommargin="0" marhinheight=0 marginwidth=0 bgproperties="">
+<a href="http://www.aldec.com" target="_blank"><img hspace="0" vspace="0" src="./../images/logo.gif" alt="ALDEC logo" width="231" height="51" align="left" border="0"></a>
+</body>
+</html>
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/doc/html/struct/aldec.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/struct/map.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/struct/map.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/struct/map.htm	(revision 264)
@@ -0,0 +1,17 @@
+<html>
+<style>
+body    { font-size: 12px }
+#tree   { font-size: 12px }
+#folder { cursor: hand }
+a { color: #000080; text-decoration: none }'
+</style>
+<body background="./../images/aldec.gif" bgproperties="fixed">
+
+<script language="JavaScript">
+<!--
+parent.FirstCreateTree ();
+//-->
+</script>
+
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/struct/map.htm
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Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/struct/settings.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/struct/settings.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/struct/settings.htm	(revision 264)
@@ -0,0 +1,29 @@
+<html>
+<script language="JavaScript">
+function XNotify(){}
+function LoadExp(){window.parent.frames["Map"].window.location.href="./map_e.htm";}
+function LoadColl(){window.parent.frames["Map"].window.location.href="./map_c.htm";}
+if(!document.all){
+	document.captureEvents(Event.CLICK | Event.ONLOAD);
+	document.images["COLL"].onclick = LoadColl;
+	document.images["EXP"].onclick = LoadExp;
+	document.onload = XNotify;
+}
+</script>
+
+<body leftmargin="4" topmargin="2" rightmargin="0" bottommargin="2" marhinheight="0" marginwidth="0" 
+bgcolor="white" background="./../images/aldec.gif"
+onLoad="XNotify()"
+>
+<table align="left" border="0" cellspacing="0" cellpadding="0" valign="center" align="center" height="100%">
+ <tr>
+  <td>
+	<img onClick="LoadColl()" name="COLL" src="./../images/set/coll.gif" alt="Load collapsed tree" width="18" height="16"></a>
+  </td>
+  <td>
+	<img onClick="LoadExp()" name="EXP"  src="./../images/set/exp.gif" alt="Load expanded tree" width="18" height="16">
+  </td>
+ </tr>
+</table>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/struct/settings.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/syn/Altera/db/usbHostSlave.db_info
===================================================================
--- common/components/usbhostslave/tags/start/syn/Altera/db/usbHostSlave.db_info	(nonexistent)
+++ common/components/usbhostslave/tags/start/syn/Altera/db/usbHostSlave.db_info	(revision 264)
@@ -0,0 +1,3 @@
+Quartus_Version = Version 4.1 Build 208 09/10/2004 Service Pack 2 SJ Web Edition
+Version_Index = 53250
+Creation_Time = Sat Oct 02 05:36:22 2004

Property changes on: common/components/usbhostslave/tags/start/syn/Altera/db/usbHostSlave.db_info
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qws
===================================================================
--- common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qws	(nonexistent)
+++ common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qws	(revision 264)
@@ -0,0 +1,23 @@
+[ProjectWorkspace]
+ptn_Child1=Frames
+ptn_Child2=Workmode
+ptn_Child3=ActionPoints
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
+[ProjectWorkspace.Frames.ChildFrames]
+ptn_Child1=Document-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
+DocPathName=../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
+InCompileMode=True
+InSimulateMode=False
+InFirmwareMode=False
+WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPGBAAAAAANBAAAAAACGCAAAAAGHBAAAAA
+IsActiveChildFrame=True
+ptn_Child1=StateMap
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
+AFC_IN_REPORT=False
+[ProjectWorkspace.Workmode]
+CurrentWorkmode=0

Property changes on: common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qws
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/buffers/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/buffers/TxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/buffers/TxFifoBI.v	(revision 264)
@@ -0,0 +1,149 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+  address, writeEn, strobe_i,
+  busClk, 
+  usbClk, 
+  rstSyncToBusClk, 
+  fifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoWEn,
+  forceEmptySyncToUsbClk,
+  forceEmptySyncToBusClk,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoWEn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+reg fifoWEn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg forceEmptyReg;
+reg forceEmpty;
+reg forceEmptyToggle;
+reg [2:0] forceEmptyToggleSyncToUsbClk;
+
+//sync write
+always @(posedge busClk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+//detect rising edge of 'forceEmpty', and generate toggle signal
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) begin
+    forceEmptyReg <= 1'b0;
+    forceEmptyToggle <= 1'b0;
+  end
+  else begin
+    if (forceEmpty == 1'b1)
+      forceEmptyReg <= 1'b1;
+    else
+      forceEmptyReg <= 1'b0;
+    if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0)
+      forceEmptyToggle <= ~forceEmptyToggle;
+  end
+end
+assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0;
+
+// double sync across clock domains to generate 'forceEmptySyncToUsbClk'
+always @(posedge usbClk) begin
+    forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle};
+end
+assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1];
+
+// async read mux
+assign busDataOut = 8'h00;
+//always @(address or fifoFull or numElementsInFifo)
+//begin
+//  case (address)
+//      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+//      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+//      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+//      default: busDataOut <= 8'h00;
+//  endcase
+//end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoWEn <= 1'b1;
+  else
+    fifoWEn <= 1'b0;
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/buffers/TxFifoBI.v
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+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/USBHostControlBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/USBHostControlBI.v	(revision 264)
@@ -0,0 +1,479 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBHostControlBI.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostControl_h.v"
+ 
+module USBHostControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  SOFSentIntOut, connEventIntOut, resumeIntOut, transDoneIntOut,
+  TxTransTypeReg, TxSOFEnableReg,
+  TxAddrReg, TxEndPReg, frameNumIn, 
+  RxPktStatusIn, RxPIDIn,
+  connectStateIn,
+  SOFSentIn, connEventIn, resumeIntIn, transDoneIn,
+  hostControlSelect,
+  clrTransReq,
+  preambleEn,
+  SOFSync,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  transReq,
+  isoEn,
+  SOFTimer
+  );
+input [3:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFSentIntOut;
+output connEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+
+output [1:0] TxTransTypeReg;
+output TxSOFEnableReg;
+output [6:0] TxAddrReg;
+output [3:0] TxEndPReg;
+input [10:0] frameNumIn;
+input [7:0] RxPktStatusIn;
+input [3:0] RxPIDIn;
+input [1:0] connectStateIn;
+input SOFSentIn;
+input connEventIn;
+input resumeIntIn;
+input transDoneIn;
+input hostControlSelect;
+input clrTransReq;
+output preambleEn;
+output SOFSync;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output transReq;
+output isoEn;     //enable isochronous mode
+input [15:0] SOFTimer;
+
+wire [3:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFSentIntOut;
+reg connEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+
+reg [1:0] TxTransTypeReg;
+reg [1:0] TxTransTypeReg_reg1;
+reg TxSOFEnableReg;
+reg TxSOFEnableReg_reg1;
+reg [6:0] TxAddrReg;
+reg [6:0] TxAddrReg_reg1;
+reg [3:0] TxEndPReg;
+reg [3:0] TxEndPReg_reg1;
+wire [10:0] frameNumIn;
+wire [7:0] RxPktStatusIn;
+wire [3:0] RxPIDIn;
+wire [1:0] connectStateIn;
+
+wire SOFSentIn;
+wire connEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire hostControlSelect;
+wire clrTransReq;
+reg preambleEn;
+reg preambleEn_reg1;
+reg SOFSync;
+reg SOFSync_reg1;
+reg [1:0] TxLineState;
+reg [1:0] TxLineState_reg1;
+reg LineDirectControlEn;
+reg LineDirectControlEn_reg1;
+reg fullSpeedPol; 
+reg fullSpeedPol_reg1; 
+reg fullSpeedRate;
+reg fullSpeedRate_reg1;
+reg transReq;
+reg transReq_reg1;
+reg isoEn;
+reg isoEn_reg1;
+wire [15:0] SOFTimer;
+
+//internal wire and regs
+reg [1:0] TxControlReg;
+reg [4:0] TxLineControlReg;
+reg clrSOFReq;
+reg clrConnEvtReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFSentInt;
+reg connEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg [3:0] interruptMaskReg;
+reg setTransReq;
+reg [2:0] resumeIntInExtend;
+reg [2:0] transDoneInExtend;
+reg [2:0] connEventInExtend;
+reg [2:0] SOFSentInExtend;
+reg [2:0] clrTransReqExtend;
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [1:0] TxTransTypeRegSTB;
+reg TxSOFEnableRegSTB;
+reg [6:0] TxAddrRegSTB;
+reg [3:0] TxEndPRegSTB;
+reg preambleEnSTB;
+reg SOFSyncSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB; 
+reg fullSpeedRateSTB;
+reg transReqSTB;
+reg isoEnSTB;   
+reg [10:0] frameNumInSTB;
+reg [10:0] frameNumInSTB_reg1;
+reg [7:0] RxPktStatusInSTB;
+reg [7:0] RxPktStatusInSTB_reg1;
+reg [3:0] RxPIDInSTB;
+reg [3:0] RxPIDInSTB_reg1;
+reg [1:0] connectStateInSTB;
+reg [1:0] connectStateInSTB_reg1;
+reg [2:0] SOFSentInSTB;
+reg [2:0] connEventInSTB;
+reg [2:0] resumeIntInSTB;
+reg [2:0] transDoneInSTB;
+reg [2:0] clrTransReqSTB;
+reg [15:0] SOFTimerSTB;
+reg [15:0] SOFTimerSTB_reg1;
+
+  
+//sync write demux
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    isoEnSTB <= 1'b0;
+    preambleEnSTB <= 1'b0;
+    SOFSyncSTB <= 1'b0;
+    TxTransTypeRegSTB <= 2'b00;
+    TxLineControlReg <= 5'h00;
+    TxSOFEnableRegSTB <= 1'b0;
+    TxAddrRegSTB <= 7'h00;
+    TxEndPRegSTB <= 4'h0;
+    interruptMaskReg <= 4'h0;
+  end
+  else begin
+    clrSOFReq <= 1'b0;
+    clrConnEvtReq <= 1'b0;
+    clrResInReq <= 1'b0;
+    clrTransDoneReq <= 1'b0;
+    setTransReq <= 1'b0;
+    if (writeEn == 1'b1 && strobe_i == 1'b1 && hostControlSelect == 1'b1)
+    begin
+      case (address)
+        `TX_CONTROL_REG : begin
+          isoEnSTB <= dataIn[`ISO_ENABLE_BIT];
+          preambleEnSTB <= dataIn[`PREAMBLE_ENABLE_BIT];
+          SOFSyncSTB <= dataIn[`SOF_SYNC_BIT];
+          setTransReq <= dataIn[`TRANS_REQ_BIT];
+        end
+        `TX_TRANS_TYPE_REG : TxTransTypeRegSTB <= dataIn[1:0];
+        `TX_LINE_CONTROL_REG : TxLineControlReg <= dataIn[4:0];
+        `TX_SOF_ENABLE_REG : TxSOFEnableRegSTB <= dataIn[`SOF_EN_BIT];
+        `TX_ADDR_REG : TxAddrRegSTB <= dataIn[6:0];
+        `TX_ENDP_REG : TxEndPRegSTB <= dataIn[3:0];
+        `INTERRUPT_STATUS_REG :  begin
+          clrSOFReq <= dataIn[`SOF_SENT_BIT];
+          clrConnEvtReq <= dataIn[`CONNECTION_EVENT_BIT];
+          clrResInReq <= dataIn[`RESUME_INT_BIT];
+          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+        end
+        `INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[3:0];
+      endcase
+    end 
+  end
+end
+
+//interrupt control
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    SOFSentInt <= 1'b0;
+    connEventInt <= 1'b0;
+    resumeInt <= 1'b0;
+    transDoneInt <= 1'b0;
+  end
+  else begin
+    if (SOFSentInSTB[1] == 1'b1 && SOFSentInSTB[0] == 1'b0)
+      SOFSentInt <= 1'b1;
+    else if (clrSOFReq == 1'b1)
+      SOFSentInt <= 1'b0;
+    
+    if (connEventInSTB[1] == 1'b1 && connEventInSTB[0] == 1'b0)
+      connEventInt <= 1'b1;
+    else if (clrConnEvtReq == 1'b1)
+      connEventInt <= 1'b0;
+    
+    if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
+      resumeInt <= 1'b1;
+    else if (clrResInReq == 1'b1)
+      resumeInt <= 1'b0;  
+
+    if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
+      transDoneInt <= 1'b1;
+    else if (clrTransDoneReq == 1'b1)
+      transDoneInt <= 1'b0;
+  end
+end
+
+//mask interrupts
+always @(*) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  connEventIntOut <= connEventInt & interruptMaskReg[`CONNECTION_EVENT_BIT];
+  SOFSentIntOut <= SOFSentInt & interruptMaskReg[`SOF_SENT_BIT];
+end  
+  
+//transaction request set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'setTransReq' must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the transaction request is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'transReq' and sampling of related control signals.
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    transReqSTB <= 1'b0;
+  end
+  else begin
+    if (setTransReq == 1'b1)
+      transReqSTB <= 1'b1;
+    else if (clrTransReqSTB[1] == 1'b1 && clrTransReqSTB[0] == 1'b0)
+      transReqSTB <= 1'b0;
+  end
+end  
+  
+//break out control signals
+always @(*) begin
+  TxLineStateSTB <= TxLineControlReg[`TX_LINE_STATE_MSBIT:`TX_LINE_STATE_LSBIT];
+  LineDirectControlEnSTB <= TxLineControlReg[`DIRECT_CONTROL_BIT];
+  fullSpeedPolSTB <= TxLineControlReg[`FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRateSTB <= TxLineControlReg[`FULL_SPEED_LINE_RATE_BIT];
+end
+  
+// async read mux
+always @(*)
+begin
+  case (address)
+      `TX_CONTROL_REG : dataOut <= {4'b0000, isoEnSTB, preambleEnSTB, SOFSyncSTB, transReqSTB} ;
+      `TX_TRANS_TYPE_REG : dataOut <= {6'b000000, TxTransTypeRegSTB};
+      `TX_LINE_CONTROL_REG : dataOut <= {3'b000, TxLineControlReg};
+      `TX_SOF_ENABLE_REG : dataOut <= {7'b0000000, TxSOFEnableRegSTB};
+      `TX_ADDR_REG : dataOut <= {1'b0, TxAddrRegSTB};
+      `TX_ENDP_REG : dataOut <= {4'h0, TxEndPRegSTB};
+      `FRAME_NUM_MSB_REG : dataOut <= {5'b00000, frameNumInSTB[10:8]};
+      `FRAME_NUM_LSB_REG : dataOut <= frameNumInSTB[7:0];
+      `INTERRUPT_STATUS_REG :  dataOut <= {4'h0, SOFSentInt, connEventInt, resumeInt, transDoneInt};
+      `INTERRUPT_MASK_REG  : dataOut <= {4'h0, interruptMaskReg};
+      `RX_STATUS_REG  : dataOut <= RxPktStatusInSTB;
+      `RX_PID_REG  : dataOut <= {4'b0000, RxPIDInSTB};
+      `RX_CONNECT_STATE_REG : dataOut <= {6'b000000, connectStateInSTB};
+      `HOST_SOF_TIMER_MSB_REG : dataOut <= SOFTimerSTB[15:8];
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+//re-sync from busClk to usbClk. 
+always @(posedge usbClk) begin
+  if (rstSyncToUsbClk == 1'b1) begin
+    isoEn <= 1'b0;
+    isoEn_reg1 <= 1'b0;
+    preambleEn <= 1'b0;
+    preambleEn_reg1 <= 1'b0;
+    SOFSync <= 1'b0;
+    SOFSync_reg1 <= 1'b0;
+    TxTransTypeReg <= 2'b00;
+    TxTransTypeReg_reg1 <= 2'b00;
+    TxSOFEnableReg <= 1'b0;
+    TxSOFEnableReg_reg1 <= 1'b0;
+    TxAddrReg <= {7{1'b0}};
+    TxAddrReg_reg1 <= {7{1'b0}};
+    TxEndPReg <= 4'h0;
+    TxEndPReg_reg1 <= 4'h0;
+    TxLineState <= 2'b00;
+    TxLineState_reg1 <= 2'b00;
+    LineDirectControlEn <= 1'b0;
+    LineDirectControlEn_reg1 <= 1'b0;
+    fullSpeedPol <= 1'b0; 
+    fullSpeedPol_reg1 <= 1'b0; 
+    fullSpeedRate <= 1'b0;
+    fullSpeedRate_reg1 <= 1'b0;
+    transReq <= 1'b0;
+    transReq_reg1 <= 1'b0;
+  end
+  else begin
+    isoEn_reg1 <= isoEnSTB;     
+    isoEn <= isoEn_reg1;     
+    preambleEn_reg1 <= preambleEnSTB;
+    preambleEn <= preambleEn_reg1;
+    SOFSync_reg1 <= SOFSyncSTB;
+    SOFSync <= SOFSync_reg1;
+    TxTransTypeReg_reg1 <= TxTransTypeRegSTB;
+    TxTransTypeReg <= TxTransTypeReg_reg1;
+    TxSOFEnableReg_reg1 <= TxSOFEnableRegSTB;
+    TxSOFEnableReg <= TxSOFEnableReg_reg1;
+    TxAddrReg_reg1 <= TxAddrRegSTB;
+    TxAddrReg <= TxAddrReg_reg1;
+    TxEndPReg_reg1 <= TxEndPRegSTB;
+    TxEndPReg <= TxEndPReg_reg1;
+    TxLineState_reg1 <= TxLineStateSTB;
+    TxLineState <= TxLineState_reg1;
+    LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
+    LineDirectControlEn <= LineDirectControlEn_reg1;
+    fullSpeedPol_reg1 <= fullSpeedPolSTB; 
+    fullSpeedPol <= fullSpeedPol_reg1; 
+    fullSpeedRate_reg1 <= fullSpeedRateSTB;
+    fullSpeedRate <= fullSpeedRate_reg1;
+    transReq_reg1 <= transReqSTB;
+    transReq <= transReq_reg1;
+  end
+end
+
+//Extend  resumeIntIn etc from 1 tick to 3 ticks
+always @(posedge usbClk) begin
+  if (rstSyncToUsbClk == 1'b1) begin
+    resumeIntInExtend <= 3'b000;
+    transDoneInExtend <= 3'b000;
+    connEventInExtend <= 3'b000;
+    SOFSentInExtend <= 3'b000;
+    clrTransReqExtend <= 3'b000;
+  end
+  else begin
+    if (resumeIntIn == 1'b1)
+      resumeIntInExtend <= 3'b111;
+    else
+      resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
+    if (transDoneIn == 1'b1)
+      transDoneInExtend <= 3'b111;
+    else
+      transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
+    if (connEventIn == 1'b1)
+      connEventInExtend <= 3'b111;
+    else
+      connEventInExtend <= {1'b0, connEventInExtend[2:1]};
+    if (SOFSentIn == 1'b1)
+      SOFSentInExtend <= 3'b111;
+    else
+      SOFSentInExtend <= {1'b0, SOFSentInExtend[2:1]};
+    if (clrTransReq == 1'b1)
+      clrTransReqExtend <= 3'b111;
+    else
+      clrTransReqExtend <= {1'b0, clrTransReqExtend[2:1]};
+  end
+end
+
+//re-sync from usbClk to busClk. Since 'clrTransReq', 'transDoneIn' etc are only asserted 
+//for 3 'usbClk' ticks, busClk freq must be greater than or equal to usbClk/3 freq
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) begin
+    SOFSentInSTB <= 3'b000;
+    connEventInSTB <= 3'b000;
+    resumeIntInSTB <= 3'b000;
+    transDoneInSTB <= 3'b000;
+    clrTransReqSTB <= 3'b000;
+    frameNumInSTB <= {11{1'b0}};
+    frameNumInSTB_reg1 <= {11{1'b0}};
+    RxPktStatusInSTB <= 8'h00;
+    RxPktStatusInSTB_reg1 <= 8'h00;
+    RxPIDInSTB <= 4'h0;
+    RxPIDInSTB_reg1 <= 4'h0;
+    connectStateInSTB <= 2'b00;
+    connectStateInSTB_reg1 <= 2'b00;
+    SOFTimerSTB <= 16'h0000;
+    SOFTimerSTB_reg1 <= 16'h0000;
+  end
+  else begin
+    frameNumInSTB_reg1 <= frameNumIn;
+    frameNumInSTB <= frameNumInSTB_reg1;
+    RxPktStatusInSTB_reg1 <= RxPktStatusIn;
+    RxPktStatusInSTB <= RxPktStatusInSTB_reg1;
+    RxPIDInSTB_reg1 <= RxPIDIn;
+    RxPIDInSTB <= RxPIDInSTB_reg1;
+    connectStateInSTB_reg1 <= connectStateIn;
+    connectStateInSTB <= connectStateInSTB_reg1;
+    SOFSentInSTB <= {SOFSentInExtend[0], SOFSentInSTB[2:1]};
+    connEventInSTB <= {connEventInExtend[0], connEventInSTB[2:1]};
+    resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
+    transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
+    clrTransReqSTB <= {clrTransReqExtend[0], clrTransReqSTB[2:1]};
+    //FIXME. It is not safe to pass 'SOFTimer' multi-bit signal between clock domains this way
+    //All the other multi-bit signals will be static at the time that they are
+    //read, but 'SOFTimer' will not be static.
+    SOFTimerSTB_reg1 <= SOFTimer; 
+    SOFTimerSTB <= SOFTimerSTB_reg1; 
+  end
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/USBHostControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
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Index: common/components/usbhostslave/tags/start/syn/Altera/db/usbHostSlave.project.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/syn/Altera/db/usbHostSlave.project.hdb
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/buffers/RxFifo.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/buffers/RxFifo.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/buffers/RxFifo.v	(revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo read access via bus interface, fifo write access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module RxFifo(
+  busClk,
+  usbClk,
+  rstSyncToBusClk, 
+  rstSyncToUsbClk, 
+  fifoWEn, 
+  fifoFull,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataIn  );
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input busClk; 
+input usbClk; 
+input rstSyncToBusClk; 
+input rstSyncToUsbClk; 
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire busClk; 
+wire usbClk; 
+wire rstSyncToBusClk; 
+wire rstSyncToUsbClk; 
+wire fifoWEn; 
+wire fifoFull;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmptySyncToBusClk;
+wire forceEmptySyncToUsbClk;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;   //not used
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .wrClk(usbClk), 
+  .rdClk(busClk), 
+  .rstSyncToWrClk(rstSyncToUsbClk), 
+  .rstSyncToRdClk(rstSyncToBusClk), 
+  .dataIn(fifoDataIn), 
+  .dataOut(dataFromFifoToBus), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmptySyncToWrClk(forceEmptySyncToUsbClk), 
+  .forceEmptySyncToRdClk(forceEmptySyncToBusClk), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+RxfifoBI u_RxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .fifoSelect(busFifoSelect),
+  .fifoDataIn(dataFromFifoToBus),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoREn(fifoREn),
+  .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+  .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/buffers/RxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/buffers/dpMem_dc.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/buffers/dpMem_dc.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/buffers/dpMem_dc.v	(revision 264)
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// dpMem_dc.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Synchronous dual port memory with dual clocks
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module dpMem_dc(  addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input wrClk;
+input rdClk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire wrClk;
+wire rdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge rdClk) begin
+  dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge wrClk) begin
+  if (writeEn == 1'b1)
+    buffer[addrIn] <= dataIn;
+end                  
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/buffers/dpMem_dc.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/directcontrol.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/directcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/directcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="directcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="directControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// directControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
+BUNDLES
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+S 11 6 4096 ELLIPSE "States" | 102500,176200 6500 6500
+L 10 11 0 TEXT "State Labels" | 102500,176200 1 0 0 "CHK_DRCT_CNTL\n/1/"
+S 9 6 0 ELLIPSE "States" | 100900,212200 6500 6500
+L 8 9 0 TEXT "State Labels" | 100900,212200 1 0 0 "START_DC\n/0/"
+L 7 6 0 TEXT "Labels" | 18700,230700 1 0 0 "drctCntl"
+F 6 0 671089152 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,233700
+A 5 0 1 TEXT "Actions" | 17700,253700 1 0 0 "// diagram ACTION"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: directControl"
+C 28 27 0 TEXT "Conditions" | 80136,160617 1 0 0 "directControlEn == 1'b1"
+W 27 6 8193 11 78 BEZIER "Transitions" | 99393,170493 94693,161093 75357,144887 70657,135487
+W 26 6 0 9 11 BEZIER "Transitions" | 100525,205718 101125,199618 101292,188766 101892,182666
+I 21 0 2 Builtin InPort | 57252,239123 "" ""
+L 20 21 0 TEXT "Labels" | 63252,239123 1 0 0 "directControlEn"
+C 19 14 0 TEXT "Conditions" | 76744,213569 1 0 0 "rst"
+I 18 0 2 Builtin InPort | 181500,257400 "" ""
+L 17 18 0 TEXT "Labels" | 187500,257400 1 0 0 "rst"
+I 16 0 3 Builtin InPort | 181300,263800 "" ""
+W 51 6 8194 11 127 BEZIER "Transitions" | 108159,173005 122851,164817 139855,136277 144754,128309
+H 79 78 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 78 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 68590,129326 6500 6500
+L 77 78 0 TEXT "State Labels" | 68590,129326 1 0 0 "DRCT_CNTL"
+W 95 79 0 102 93 BEZIER "Transitions" | 65496,102474 65896,97574 67230,81067 67630,76167
+A 94 93 4 TEXT "Actions" | 87021,72145 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 93 79 16384 ELLIPSE "States" | 68621,69745 6500 6500
+W 92 79 8194 93 102 BEZIER "Transitions" | 62907,72842 59107,76242 50421,81945 48421,85645\
+                                           46421,89345 46021,97345 47471,100295 48921,103245\
+                                           55748,105011 58848,106911
+L 91 90 0 TEXT "State Labels" | 62621,146145 1 0 0 "WAIT_GNT\n/2/"
+S 90 79 12288 ELLIPSE "States" | 62621,146145 6500 6500
+W 88 79 4096 124 90 BEZIER "Transitions" | 105569,175900 100869,166500 70569,161175 65869,151775
+L 103 102 0 TEXT "State Labels" | 65021,108945 1 0 0 "WAIT_RDY\n/4/"
+S 102 79 20480 ELLIPSE "States" | 65021,108945 6500 6500
+C 100 99 0 TEXT "Conditions" | 62221,136545 1 0 0 "HCTxPortGnt == 1'b1"
+W 99 79 0 90 102 BEZIER "Transitions" | 62834,139649 63234,133449 64005,121613 64405,115413
+L 98 93 0 TEXT "State Labels" | 68621,69745 1 0 0 "CHK_LOOP\n/3/"
+C 97 95 0 TEXT "Conditions" | 67437,101104 1 0 0 "HCTxPortRdy == 1'b1"
+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= {6'b000000, directControlLineState}; \nHCTxPortCntl <= `TX_DIRECT_CONTROL;"
+S 127 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147819,122579 6500 6500
+L 126 127 0 TEXT "State Labels" | 147819,122579 1 0 0 "IDLE"
+W 125 6 0 78 11 BEZIER "Transitions" | 62548,131721 58511,135864 49941,141807 48613,147491\
+                                       47285,153175 50048,167625 56316,171290 62585,174956\
+                                       84856,175714 96012,175820
+I 124 79 0 Builtin Entry | 109800,175900
+I 122 79 0 Builtin Exit | 138103,36586
+S 143 128 32768 ELLIPSE "States" | 110104,152646 6500 6500
+A 142 137 4 TEXT "Actions" | 130303,68109 1 0 0 "HCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;"
+A 141 139 16 TEXT "Actions" | 109766,100293 1 0 0 "HCTxPortWEn <= 1'b1; \nHCTxPortData <= 8'h00; \nHCTxPortCntl <= `TX_IDLE;"
+C 140 139 0 TEXT "Conditions" | 114907,107589 1 0 0 "HCTxPortRdy == 1'b1"
+W 139 128 0 146 137 BEZIER "Transitions" | 112979,108975 113379,104075 114551,87365 114951,82465
+L 138 137 0 TEXT "State Labels" | 115898,76040 1 0 0 "FIN\n/5/"
+S 137 128 28672 ELLIPSE "States" | 115898,76040 6500 6500
+C 136 135 0 TEXT "Conditions" | 109704,143046 1 0 0 "HCTxPortGnt == 1'b1"
+W 135 128 0 143 146 BEZIER "Transitions" | 110317,146150 110717,139950 111488,128114 111888,121914
+H 128 127 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 159 158 0 TEXT "Labels" | 115163,245109 1 0 0 "HCTxPortWEn"
+I 158 0 2 Builtin OutPort | 109163,245109 "" ""
+L 157 156 0 TEXT "Labels" | 115440,251139 1 0 0 "HCTxPortData[7:0]"
+I 156 0 130 Builtin OutPort | 109440,251139 "" ""
+L 155 154 0 TEXT "Labels" | 114837,257571 1 0 0 "HCTxPortCntl[7:0]"
+I 154 0 130 Builtin OutPort | 108837,257571 "" ""
+W 153 6 0 127 11 BEZIER "Transitions" | 152988,126518 159136,134574 171720,147536 171773,153843\
+                                        171826,160150 159742,169266 150997,171704 142252,174142\
+                                        120424,175336 108976,175654
+I 151 128 0 Builtin Exit | 67380,61048
+I 150 128 0 Builtin Entry | 67068,204814
+A 148 145 16 TEXT "Actions" | 91825,176461 1 0 0 "HCTxPortReq <= 1'b1;"
+L 147 146 0 TEXT "State Labels" | 112504,115446 1 0 0 "WAIT_RDY\n/7/"
+S 146 128 36864 ELLIPSE "States" | 112504,115446 6500 6500
+W 145 128 4096 150 143 BEZIER "Transitions" | 71299,204814 85991,196626 102015,166277 106914,158309
+L 144 143 0 TEXT "State Labels" | 110104,152646 1 0 0 "WAIT_GNT\n/6/"
+W 173 128 0 137 151 BEZIER "Transitions" | 109732,73984 99784,70853 80467,64179 70519,61048
+A 167 88 16 TEXT "Actions" | 75140,165538 1 0 0 "HCTxPortReq <= 1'b1;"
+A 166 9 2 TEXT "Actions" | 121180,221292 1 0 0 "HCTxPortCntl <= 8'h00;\nHCTxPortData <= 8'h00;\nHCTxPortWEn <= 1'b0;   \nHCTxPortReq <= 1'b0;"
+L 165 164 0 TEXT "Labels" | 166587,239893 1 0 0 "HCTxPortReq"
+I 164 0 2 Builtin OutPort | 160587,239893 "" ""
+L 163 162 0 TEXT "Labels" | 168999,244717 1 0 0 "HCTxPortGnt"
+I 162 0 2 Builtin InPort | 162999,244717 "" ""
+L 161 160 0 TEXT "Labels" | 117543,239893 1 0 0 "HCTxPortRdy"
+I 160 0 2 Builtin InPort | 111543,239893 "" ""
+W 174 79 8193 93 122 BEZIER "Transitions" | 74339,66657 90586,60011 118717,43232 134964,36586
+C 175 174 0 TEXT "Conditions" | 95181,61437 1 0 0 "directControlEn == 1'b0"
+A 177 174 16 TEXT "Actions" | 102566,47300 1 0 0 "HCTxPortReq <= 1'b0;"
+L 178 179 0 TEXT "Labels" | 63352,249414 1 0 0 "directControlLineState[1:0]"
+I 179 0 130 Builtin InPort | 57352,249414 "" ""
+END

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/directcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/hctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/hctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/hctxportarbiter.asf	(revision 264)
@@ -0,0 +1,130 @@
+VERSION=1.15
+HEADER
+FILE="hctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="HCTxPortArbiter"
+FRAMES=ON
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hctxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 431800,558800
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,543100 1 0 0 "Module: HCTxPortArbiter"
+F 6 0 671089152 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,277900 323180,412945
+L 7 6 0 TEXT "Labels" | 153720,399520 1 0 0 "HCTxArb"
+S 8 6 0 ELLIPSE "States" | 225591,395370 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,395370 1 0 0 "START_HARB\n/0/"
+S 10 6 4096 ELLIPSE "States" | 224972,365039 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,363653 1 0 0 "WAIT_REQ\n/1/"
+S 12 6 8192 ELLIPSE "States" | 191859,293613 6500 6500
+L 13 12 0 TEXT "State Labels" | 191859,293613 1 0 0 "SEND_SOF\n/2/"
+S 14 6 12288 ELLIPSE "States" | 269063,296392 6500 6500
+L 15 14 0 TEXT "State Labels" | 269063,296392 1 0 0 "SEND_PACKET\n/3/"
+I 16 6 0 Builtin Reset | 178237,395710
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,395710 187522,391937 210052,391894 219337,393602
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,388894 225070,384414 224938,376011 224784,371531
+W 19 6 2 10 14 BEZIER "Transitions" | 229757,360641 236477,355079 258220,315910 265438,301787
+W 20 6 1 10 12 BEZIER "Transitions" | 219884,360995 214322,355742 203672,314353 193976,299756
+C 21 20 0 TEXT "Conditions" | 185611,358255 1 0 0 "SOFCntlReq == 1'b1"
+C 22 19 0 TEXT "Conditions" | 235353,358515 1 0 0 "sendPacketReq == 1'b1"
+A 23 19 16 TEXT "Actions" | 233291,339940 1 0 0 "sendPacketGnt <= 1'b1;\nmuxCntl <= `SEND_PACKET_MUX;"
+A 24 20 16 TEXT "Actions" | 172116,340566 1 0 0 "SOFCntlGnt <= 1'b1;\nmuxCntl <= `SOF_CTRL_MUX;"
+A 25 8 2 TEXT "Actions" | 255918,407981 1 0 0 "SOFCntlGnt <= 1'b0;\nsendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxCntl <= 2'b00;"
+C 26 17 0 TEXT "Conditions" | 201742,391978 1 0 0 "rst"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,302121 294143,322021 288020,346232 288403,352802\
+                                      288786,359372 287077,371461 282417,376909 277757,382357\
+                                      274547,381487 268775,381564 263003,381642 254872,381366\
+                                      248267,378971 241663,376577 234289,371557 230118,369008
+W 28 6 0 12 10 BEZIER "Transitions" | 186560,297376 167155,311353 168429,333163 167686,340659\
+                                      166944,348155 168507,364217 173450,370590 178394,376963\
+                                      186275,384997 193806,383684 201338,382371 213515,373400\
+                                      220004,369229
+A 29 28 16 TEXT "Actions" | 161739,369899 1 0 0 "SOFCntlGnt <= 1'b0;"
+C 30 28 0 TEXT "Conditions" | 155052,298962 1 0 0 "SOFCntlReq == 1'b0"
+C 31 27 0 TEXT "Conditions" | 272024,315171 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,371179 1 0 0 "sendPacketGnt <= 1'b0;"
+I 33 0 2 Builtin OutPort | 117425,484940 "" ""
+L 34 33 0 TEXT "Labels" | 123425,484940 1 0 0 "SOFCntlGnt"
+I 37 0 2 Builtin OutPort | 164033,485851 "" ""
+L 38 37 0 TEXT "Labels" | 170033,485851 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 197412,542480 "" ""
+L 40 39 0 TEXT "Labels" | 203412,542480 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 197495,536936 "" ""
+I 44 0 130 Builtin InPort | 166169,499499 "" ""
+L 45 44 0 TEXT "Labels" | 172169,499499 1 0 0 "sendPacketData[7:0]"
+L 36 35 0 TEXT "Labels" | 170373,457796 1 0 0 "HCTxPortWEnable"
+I 35 0 2 Builtin OutPort | 164373,457796 "" ""
+I 48 0 2 Builtin InPort | 120008,489821 "" ""
+L 49 48 0 TEXT "Labels" | 126008,489821 1 0 0 "SOFCntlWEn"
+I 52 0 2 Builtin InPort | 165981,490639 "" ""
+L 53 52 0 TEXT "Labels" | 171981,490639 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 25211,394555 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\ncase (muxCntl)\n  `SOF_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= SOFCntlWEn;\n    HCTxPortData <= SOFCntlData;\n    HCTxPortCntl <= SOFCntlCntl;\n  end\n  `DIRECT_CTRL_MUX :\n  begin  \n    HCTxPortWEnable <= directCntlWEn;\n    HCTxPortData <= directCntlData;\n    HCTxPortCntl <= directCntlCntl;\n  end\n  `SEND_PACKET_MUX :\n  begin  \n    HCTxPortWEnable <= sendPacketWEn;\n    HCTxPortData <= sendPacketData;\n    HCTxPortCntl <= sendPacketCntl;\n  end\n  default :\n  begin  \n    HCTxPortWEnable <= 1'b0;\n    HCTxPortData <= 8'h00;\n    HCTxPortCntl <= 8'h00;\n  end\nendcase	\nend"
+I 55 0 2 Builtin InPort | 119812,480347 "" ""
+I 56 0 2 Builtin InPort | 166286,481063 "" ""
+L 57 56 0 TEXT "Labels" | 172286,481063 1 0 0 "sendPacketReq"
+L 60 55 0 TEXT "Labels" | 125812,480347 1 0 0 "SOFCntlReq"
+L 61 41 0 TEXT "Labels" | 203495,536936 1 0 0 "clk"
+I 62 0 130 Builtin InPort | 166256,495120 "" ""
+L 63 62 0 TEXT "Labels" | 172256,495120 1 0 0 "sendPacketCntl[7:0]"
+L 59 58 0 TEXT "Labels" | 170296,453278 1 0 0 "HCTxPortData[7:0]"
+I 58 0 130 Builtin OutPort | 164296,453278 "" ""
+I 68 0 130 Builtin InPort | 119837,494606 "" ""
+L 69 68 0 TEXT "Labels" | 125837,494606 1 0 0 "SOFCntlCntl[7:0]"
+I 70 0 130 Builtin InPort | 119737,499229 "" ""
+L 71 70 0 TEXT "Labels" | 125737,499229 1 0 0 "SOFCntlData[7:0]"
+L 72 73 0 TEXT "Labels" | 144050,542882 1 0 0 "SEND_PACKET_MUX=2'b00"
+I 73 0 263 Builtin Constant | 141050,542882 "" I "" ""
+L 74 75 0 TEXT "Labels" | 144050,538259 1 0 0 "SOF_CTRL_MUX=2'b01"
+I 75 0 263 Builtin Constant | 141050,538259 "" I "" ""
+I 76 0 263 Builtin Constant | 140950,533626 "" I "" ""
+L 77 76 0 TEXT "Labels" | 143950,533626 1 0 0 "DIRECT_CTRL_MUX=2'b10"
+I 78 0 2 Builtin OutPort | 117944,457060 "" ""
+L 79 78 0 TEXT "Labels" | 123944,457060 1 0 0 "directCntlGnt"
+L 67 66 0 TEXT "Labels" | 170124,471556 1 0 0 "HCTxPortCntl[7:0]"
+I 66 0 130 Builtin OutPort | 164124,471556 "" ""
+I 80 0 2 Builtin InPort | 120331,452467 "" ""
+L 81 80 0 TEXT "Labels" | 126331,452467 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,461941 "" ""
+L 83 82 0 TEXT "Labels" | 126527,461941 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,471349 "" ""
+L 85 84 0 TEXT "Labels" | 126256,471349 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,466726 "" ""
+L 87 86 0 TEXT "Labels" | 126356,466726 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,528812 1 0 0 "muxCntl[1:0]"
+I 89 0 130 Builtin Signal | 141050,528812 "" ""
+L 90 91 0 TEXT "State Labels" | 230314,289948 1 0 0 "DIRECT_CONTROL\n/4/"
+S 91 6 16384 ELLIPSE "States" | 230314,289948 6500 6500
+W 92 6 8195 10 91 BEZIER "Transitions" | 225187,358573 226192,342895 228547,312073 229552,296395
+C 94 92 0 TEXT "Conditions" | 216646,319294 1 0 0 "directCntlReq == 1'b1"
+A 95 92 16 TEXT "Actions" | 205993,310852 1 0 0 "directCntlGnt <= 1'b1;\nmuxCntl <= `DIRECT_CTRL_MUX;"
+W 96 6 0 91 10 BEZIER "Transitions" | 235538,286081 238258,285074 242316,283075 251081,282571\
+                                      259846,282068 289467,282068 298484,284234 307501,286400\
+                                      313949,295065 315460,307759 316972,320453 316568,362568\
+                                      311430,375060 306292,387553 286404,388600 275724,388298\
+                                      265045,387996 242215,385739 236069,382112 229924,378486\
+                                      228216,373858 227209,371138
+C 97 96 0 TEXT "Conditions" | 246245,286904 1 0 0 "directCntlReq == 1'b0"
+A 98 96 16 TEXT "Actions" | 290172,290128 1 0 0 "directCntlGnt <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/hctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/rxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/rxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/rxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// rxStatusMonitor.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output connectionEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg connectionEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      connectionEventOut <= 1'b1;
+    else
+      connectionEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/rxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_SETUP_OUT.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/slavecontroller_SETUP_OUT.png
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar376.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar376.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar376.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 376 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller_GET_TOKEN.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar376.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/wrapper/usbHostSlave.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/wrapper/usbHostSlave.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/wrapper/usbHostSlave.v/index.htm	(revision 264)
@@ -0,0 +1,528 @@
+<html>
+<head>
+<title>usbHostSlave.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbHostSlave.v                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>////   Top level module</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:45 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>usbHostSlave</span>(
+  <span id=t_idt>clk</span>, 
+  <span id=t_idt>rst</span>,
+  <span id=t_idt>address_i</span>, 
+  <span id=t_idt>data_i</span>, 
+  <span id=t_idt>data_o</span>, 
+  <span id=t_idt>writeEn</span>, 
+  <span id=t_idt>strobe_i</span>,
+  <span id=t_idt>ack_o</span>,
+  <span id=t_idt>hostSOFSentIntOut</span>, 
+  <span id=t_idt>hostConnEventIntOut</span>, 
+  <span id=t_idt>hostResumeIntOut</span>, 
+  <span id=t_idt>hostTransDoneIntOut</span>,
+  <span id=t_idt>slaveNAKSentIntOut</span>,
+  <span id=t_idt>slaveSOFRxedIntOut</span>, 
+  <span id=t_idt>slaveResetEventIntOut</span>, 
+  <span id=t_idt>slaveResumeIntOut</span>, 
+  <span id=t_idt>slaveTransDoneIntOut</span>,
+  <span id=t_idt>USBWireDataIn</span>,
+  <span id=t_idt>USBWireDataInTick</span>,
+  <span id=t_idt>USBWireDataOut</span>,
+  <span id=t_idt>USBWireDataOutTick</span>,
+  <span id=t_idt>USBWireCtrlOut</span>
+   );
+  <span id=t_kwd>parameter</span> <span id=t_idt>HOST_FIFO_DEPTH</span> = <span id=t_cns>64</span>; <span id=t_com>//HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2</span>
+  <span id=t_kwd>parameter</span> <span id=t_idt>HOST_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP0_FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP0_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP1_FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP1_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP2_FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP2_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP3_FIFO_DEPTH</span> = <span id=t_cns>64</span>; 
+  <span id=t_kwd>parameter</span> <span id=t_idt>EP3_FIFO_ADDR_WIDTH</span> = <span id=t_cns>6</span>;   
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>input</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>address_i</span>; 
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data_i</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data_o</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>output</span> <span id=t_idt>ack_o</span>;
+<span id=t_kwd>output</span> <span id=t_idt>hostSOFSentIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>hostConnEventIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>hostResumeIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>hostTransDoneIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>slaveSOFRxedIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>slaveResetEventIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>slaveResumeIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>slaveTransDoneIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>slaveNAKSentIntOut</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireDataOutTick</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireDataInTick</span>;
+<span id=t_kwd>output</span> <span id=t_idt>USBWireCtrlOut</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>address_i</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data_i</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>data_o</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>writeEn</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>strobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>ack_o</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSOFSentIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostConnEventIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostResumeIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostTransDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveSOFRxedIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>slaveResetEventIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>slaveResumeIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>slaveTransDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveNAKSentIntOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>USBWireDataOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataOutTick</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireDataInTick</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>USBWireCtrlOut</span>;
+
+<span id=t_com>//internal wiring</span>
+<span id=t_kwd>wire</span> <span id=t_idt>hostControlSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControlSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostRxFifoSel</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostTxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostSlaveMuxSel</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostControl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromSlaveControl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostRxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostTxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromHostSlaveMux</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostTxFifoRE</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>hostTxFifoData</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostTxFifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>hostRxFifoWE</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>hostRxFifoData</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>hostRxFifoFull</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxCtrlOut</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxDataFromSIE</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RxDataOutWEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateFromHost</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateFromSlave</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityFromHost</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityFromSlave</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnFromHost</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnFromSlave</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortTxRdy</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromHost</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInFromSlave</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromHost</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInFromSlave</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectState</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetected</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortDataInToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIEPortWEnToSIE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SIEPortCtrlInToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPolarityToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedBitRateToSIE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>noActivityTimeOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3Full</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>slaveRxFifoData</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP0RxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP1RxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP2RxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP3RxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP0TxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP1TxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP2TxFifo</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>dataFromEP3TxFifo</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP0RxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP1RxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP2RxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP3RxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP0TxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP1TxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP2TxFifoSel</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveEP3TxFifoSel</span>;
+
+<span id=t_idt>usbHostControl</span> <span id=t_idt>u_usbHostControl</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>TxFifoRE</span>(<span id=t_idt>hostTxFifoRE</span>), 
+  .<span id=t_idt>TxFifoData</span>(<span id=t_idt>hostTxFifoData</span>), 
+  .<span id=t_idt>TxFifoEmpty</span>(<span id=t_idt>hostTxFifoEmpty</span>),
+  .<span id=t_idt>RxFifoWE</span>(<span id=t_idt>hostRxFifoWE</span>), 
+  .<span id=t_idt>RxFifoData</span>(<span id=t_idt>hostRxFifoData</span>), 
+  .<span id=t_idt>RxFifoFull</span>(<span id=t_idt>hostRxFifoFull</span>),
+  .<span id=t_idt>RxByteStatus</span>(<span id=t_idt>RxCtrlOut</span>), 
+  .<span id=t_idt>RxData</span>(<span id=t_idt>RxDataFromSIE</span>), 
+  .<span id=t_idt>RxDataValid</span>(<span id=t_idt>RxDataOutWEn</span>),
+  .<span id=t_idt>SIERxTimeOut</span>(<span id=t_idt>noActivityTimeOut</span>),
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedBitRateFromHost</span>), 
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>fullSpeedPolarityFromHost</span>),
+  .<span id=t_idt>HCTxPortEn</span>(<span id=t_idt>SIEPortWEnFromHost</span>), 
+  .<span id=t_idt>HCTxPortRdy</span>(<span id=t_idt>SIEPortTxRdy</span>),
+  .<span id=t_idt>HCTxPortData</span>(<span id=t_idt>SIEPortDataInFromHost</span>), 
+  .<span id=t_idt>HCTxPortCtrl</span>(<span id=t_idt>SIEPortCtrlInFromHost</span>),
+  .<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectState</span>), 
+  .<span id=t_idt>resumeDetectedIn</span>(<span id=t_idt>resumeDetected</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>3</span>:<span id=t_cns>0</span>]),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromHostControl</span>), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>),
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>SOFSentIntOut</span>(<span id=t_idt>hostSOFSentIntOut</span>), 
+  .<span id=t_idt>connEventIntOut</span>(<span id=t_idt>hostConnEventIntOut</span>), 
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>hostResumeIntOut</span>), 
+  .<span id=t_idt>transDoneIntOut</span>(<span id=t_idt>hostTransDoneIntOut</span>),
+  .<span id=t_idt>hostControlSelect</span>(<span id=t_idt>hostControlSel</span>) );
+  
+
+<span id=t_idt>usbSlaveControl</span> <span id=t_idt>u_usbSlaveControl</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>RxByteStatus</span>(<span id=t_idt>RxCtrlOut</span>), 
+  .<span id=t_idt>RxData</span>(<span id=t_idt>RxDataFromSIE</span>), 
+  .<span id=t_idt>RxDataValid</span>(<span id=t_idt>RxDataOutWEn</span>),
+  .<span id=t_idt>SIERxTimeOut</span>(<span id=t_idt>noActivityTimeOut</span>), 
+  .<span id=t_idt>RxFifoData</span>(<span id=t_idt>slaveRxFifoData</span>),
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedBitRateFromSlave</span>), 
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>fullSpeedPolarityFromSlave</span>),
+  .<span id=t_idt>SCTxPortEn</span>(<span id=t_idt>SIEPortWEnFromSlave</span>), 
+  .<span id=t_idt>SCTxPortRdy</span>(<span id=t_idt>SIEPortTxRdy</span>),
+  .<span id=t_idt>SCTxPortData</span>(<span id=t_idt>SIEPortDataInFromSlave</span>), 
+  .<span id=t_idt>SCTxPortCtrl</span>(<span id=t_idt>SIEPortCtrlInFromSlave</span>),
+  .<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectState</span>), 
+  .<span id=t_idt>resumeDetectedIn</span>(<span id=t_idt>resumeDetected</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>4</span>:<span id=t_cns>0</span>]),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromSlaveControl</span>), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>),
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>SOFRxedIntOut</span>(<span id=t_idt>slaveSOFRxedIntOut</span>), 
+  .<span id=t_idt>resetEventIntOut</span>(<span id=t_idt>slaveResetEventIntOut</span>), 
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>slaveResumeIntOut</span>), 
+  .<span id=t_idt>transDoneIntOut</span>(<span id=t_idt>slaveTransDoneIntOut</span>),
+  .<span id=t_idt>NAKSentIntOut</span>(<span id=t_idt>slaveNAKSentIntOut</span>),
+  .<span id=t_idt>slaveControlSelect</span>(<span id=t_idt>slaveControlSel</span>),
+  .<span id=t_idt>TxFifoEP0REn</span>(<span id=t_idt>TxFifoEP0REn</span>),
+  .<span id=t_idt>TxFifoEP1REn</span>(<span id=t_idt>TxFifoEP1REn</span>),
+  .<span id=t_idt>TxFifoEP2REn</span>(<span id=t_idt>TxFifoEP2REn</span>),
+  .<span id=t_idt>TxFifoEP3REn</span>(<span id=t_idt>TxFifoEP3REn</span>),
+  .<span id=t_idt>TxFifoEP0Data</span>(<span id=t_idt>TxFifoEP0Data</span>),
+  .<span id=t_idt>TxFifoEP1Data</span>(<span id=t_idt>TxFifoEP1Data</span>),
+  .<span id=t_idt>TxFifoEP2Data</span>(<span id=t_idt>TxFifoEP2Data</span>),
+  .<span id=t_idt>TxFifoEP3Data</span>(<span id=t_idt>TxFifoEP3Data</span>),
+  .<span id=t_idt>TxFifoEP0Empty</span>(<span id=t_idt>TxFifoEP0Empty</span>),
+  .<span id=t_idt>TxFifoEP1Empty</span>(<span id=t_idt>TxFifoEP1Empty</span>),
+  .<span id=t_idt>TxFifoEP2Empty</span>(<span id=t_idt>TxFifoEP2Empty</span>),
+  .<span id=t_idt>TxFifoEP3Empty</span>(<span id=t_idt>TxFifoEP3Empty</span>),
+  .<span id=t_idt>RxFifoEP0WEn</span>(<span id=t_idt>RxFifoEP0WEn</span>),
+  .<span id=t_idt>RxFifoEP1WEn</span>(<span id=t_idt>RxFifoEP1WEn</span>),
+  .<span id=t_idt>RxFifoEP2WEn</span>(<span id=t_idt>RxFifoEP2WEn</span>),
+  .<span id=t_idt>RxFifoEP3WEn</span>(<span id=t_idt>RxFifoEP3WEn</span>),
+  .<span id=t_idt>RxFifoEP0Full</span>(<span id=t_idt>RxFifoEP0Full</span>),
+  .<span id=t_idt>RxFifoEP1Full</span>(<span id=t_idt>RxFifoEP1Full</span>),
+  .<span id=t_idt>RxFifoEP2Full</span>(<span id=t_idt>RxFifoEP2Full</span>),
+  .<span id=t_idt>RxFifoEP3Full</span>(<span id=t_idt>RxFifoEP3Full</span>)
+  );
+
+<span id=t_idt>wishBoneBI</span> <span id=t_idt>u_wishBoneBI</span> (
+  .<span id=t_idt>address</span>(<span id=t_idt>address_i</span>), 
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>data_o</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>ack_o</span>(<span id=t_idt>ack_o</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>hostControlSel</span>(<span id=t_idt>hostControlSel</span>), 
+  .<span id=t_idt>hostRxFifoSel</span>(<span id=t_idt>hostRxFifoSel</span>), 
+  .<span id=t_idt>hostTxFifoSel</span>(<span id=t_idt>hostTxFifoSel</span>),
+  .<span id=t_idt>slaveControlSel</span>(<span id=t_idt>slaveControlSel</span>),
+  .<span id=t_idt>slaveEP0RxFifoSel</span>(<span id=t_idt>slaveEP0RxFifoSel</span>), 
+  .<span id=t_idt>slaveEP1RxFifoSel</span>(<span id=t_idt>slaveEP1RxFifoSel</span>), 
+  .<span id=t_idt>slaveEP2RxFifoSel</span>(<span id=t_idt>slaveEP2RxFifoSel</span>), 
+  .<span id=t_idt>slaveEP3RxFifoSel</span>(<span id=t_idt>slaveEP3RxFifoSel</span>), 
+  .<span id=t_idt>slaveEP0TxFifoSel</span>(<span id=t_idt>slaveEP0TxFifoSel</span>), 
+  .<span id=t_idt>slaveEP1TxFifoSel</span>(<span id=t_idt>slaveEP1TxFifoSel</span>), 
+  .<span id=t_idt>slaveEP2TxFifoSel</span>(<span id=t_idt>slaveEP2TxFifoSel</span>), 
+  .<span id=t_idt>slaveEP3TxFifoSel</span>(<span id=t_idt>slaveEP3TxFifoSel</span>), 
+  .<span id=t_idt>hostSlaveMuxSel</span>(<span id=t_idt>hostSlaveMuxSel</span>),
+  .<span id=t_idt>dataFromHostControl</span>(<span id=t_idt>dataFromHostControl</span>),
+  .<span id=t_idt>dataFromHostRxFifo</span>(<span id=t_idt>dataFromHostRxFifo</span>),
+  .<span id=t_idt>dataFromHostTxFifo</span>(<span id=t_idt>dataFromHostTxFifo</span>),
+  .<span id=t_idt>dataFromSlaveControl</span>(<span id=t_idt>dataFromSlaveControl</span>),
+  .<span id=t_idt>dataFromEP0RxFifo</span>(<span id=t_idt>dataFromEP0RxFifo</span>), 
+  .<span id=t_idt>dataFromEP1RxFifo</span>(<span id=t_idt>dataFromEP1RxFifo</span>), 
+  .<span id=t_idt>dataFromEP2RxFifo</span>(<span id=t_idt>dataFromEP2RxFifo</span>), 
+  .<span id=t_idt>dataFromEP3RxFifo</span>(<span id=t_idt>dataFromEP3RxFifo</span>),
+  .<span id=t_idt>dataFromEP0TxFifo</span>(<span id=t_idt>dataFromEP0TxFifo</span>), 
+  .<span id=t_idt>dataFromEP1TxFifo</span>(<span id=t_idt>dataFromEP1TxFifo</span>), 
+  .<span id=t_idt>dataFromEP2TxFifo</span>(<span id=t_idt>dataFromEP2TxFifo</span>), 
+  .<span id=t_idt>dataFromEP3TxFifo</span>(<span id=t_idt>dataFromEP3TxFifo</span>),
+  .<span id=t_idt>dataFromHostSlaveMux</span>(<span id=t_idt>dataFromHostSlaveMux</span>)
+   );
+
+<span id=t_idt>hostSlaveMux</span> <span id=t_idt>u_hostSlaveMux</span>(
+  .<span id=t_idt>SIEPortCtrlInToSIE</span>(<span id=t_idt>SIEPortCtrlInToSIE</span>),
+  .<span id=t_idt>SIEPortCtrlInFromHost</span>(<span id=t_idt>SIEPortCtrlInFromHost</span>),
+  .<span id=t_idt>SIEPortCtrlInFromSlave</span>(<span id=t_idt>SIEPortCtrlInFromSlave</span>),
+  .<span id=t_idt>SIEPortDataInToSIE</span>(<span id=t_idt>SIEPortDataInToSIE</span>), 
+  .<span id=t_idt>SIEPortDataInFromHost</span>(<span id=t_idt>SIEPortDataInFromHost</span>), 
+  .<span id=t_idt>SIEPortDataInFromSlave</span>(<span id=t_idt>SIEPortDataInFromSlave</span>), 
+  .<span id=t_idt>SIEPortWEnToSIE</span>(<span id=t_idt>SIEPortWEnToSIE</span>), 
+  .<span id=t_idt>SIEPortWEnFromHost</span>(<span id=t_idt>SIEPortWEnFromHost</span>), 
+  .<span id=t_idt>SIEPortWEnFromSlave</span>(<span id=t_idt>SIEPortWEnFromSlave</span>), 
+  .<span id=t_idt>fullSpeedPolarityToSIE</span>(<span id=t_idt>fullSpeedPolarityToSIE</span>),
+  .<span id=t_idt>fullSpeedPolarityFromHost</span>(<span id=t_idt>fullSpeedPolarityFromHost</span>),
+  .<span id=t_idt>fullSpeedPolarityFromSlave</span>(<span id=t_idt>fullSpeedPolarityFromSlave</span>),
+  .<span id=t_idt>fullSpeedBitRateToSIE</span>(<span id=t_idt>fullSpeedBitRateToSIE</span>),
+  .<span id=t_idt>fullSpeedBitRateFromHost</span>(<span id=t_idt>fullSpeedBitRateFromHost</span>),
+  .<span id=t_idt>fullSpeedBitRateFromSlave</span>(<span id=t_idt>fullSpeedBitRateFromSlave</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>dataFromHostSlaveMux</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>writeEn</span>),
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>hostSlaveMuxSel</span>(<span id=t_idt>hostSlaveMuxSel</span>)  );
+
+<span id=t_idt>usbSerialInterfaceEngine</span> <span id=t_idt>u_usbSerialInterfaceEngine</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>USBWireDataIn</span>(<span id=t_idt>USBWireDataIn</span>),
+  .<span id=t_idt>USBWireDataOut</span>(<span id=t_idt>USBWireDataOut</span>),
+  .<span id=t_idt>USBWireDataInTick</span>(<span id=t_idt>USBWireDataInTick</span>),
+  .<span id=t_idt>USBWireDataOutTick</span>(<span id=t_idt>USBWireDataOutTick</span>),
+  .<span id=t_idt>USBWireCtrlOut</span>(<span id=t_idt>USBWireCtrlOut</span>),
+  .<span id=t_idt>connectState</span>(<span id=t_idt>connectState</span>),
+  .<span id=t_idt>resumeDetected</span>(<span id=t_idt>resumeDetected</span>),
+  .<span id=t_idt>RxCtrlOut</span>(<span id=t_idt>RxCtrlOut</span>), 
+  .<span id=t_idt>RxDataOutWEn</span>(<span id=t_idt>RxDataOutWEn</span>), 
+  .<span id=t_idt>RxDataOut</span>(<span id=t_idt>RxDataFromSIE</span>), 
+  .<span id=t_idt>SIEPortCtrlIn</span>(<span id=t_idt>SIEPortCtrlInToSIE</span>),
+  .<span id=t_idt>SIEPortDataIn</span>(<span id=t_idt>SIEPortDataInToSIE</span>), 
+  .<span id=t_idt>SIEPortTxRdy</span>(<span id=t_idt>SIEPortTxRdy</span>), 
+  .<span id=t_idt>SIEPortWEn</span>(<span id=t_idt>SIEPortWEnToSIE</span>), 
+  .<span id=t_idt>fullSpeedPolarity</span>(<span id=t_idt>fullSpeedPolarityToSIE</span>),
+  .<span id=t_idt>fullSpeedBitRate</span>(<span id=t_idt>fullSpeedBitRateToSIE</span>),
+  .<span id=t_idt>noActivityTimeOut</span>(<span id=t_idt>noActivityTimeOut</span>)
+);
+
+<span id=t_com>//---Host fifos</span>
+<span id=t_idt>TxFifo</span> #(<span id=t_idt>HOST_FIFO_DEPTH</span>, <span id=t_idt>HOST_FIFO_ADDR_WIDTH</span>) <span id=t_idt>HostTxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>hostTxFifoRE</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>hostTxFifoEmpty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>hostTxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromHostTxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>hostTxFifoData</span>) );
+
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>HOST_FIFO_DEPTH</span>, <span id=t_idt>HOST_FIFO_ADDR_WIDTH</span>) <span id=t_idt>HostRxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>hostRxFifoWE</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>hostRxFifoFull</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>hostRxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromHostRxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>hostRxFifoData</span>)  );
+
+<span id=t_com>//---Slave fifos</span>
+
+<span id=t_idt>TxFifo</span> #(<span id=t_idt>EP0_FIFO_DEPTH</span>, <span id=t_idt>EP0_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP0TxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>TxFifoEP0REn</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEP0Empty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP0TxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP0TxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>TxFifoEP0Data</span>) );
+
+<span id=t_idt>TxFifo</span> #(<span id=t_idt>EP1_FIFO_DEPTH</span>, <span id=t_idt>EP1_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP1TxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>TxFifoEP1REn</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEP1Empty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP1TxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP1TxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>TxFifoEP1Data</span>) );
+
+  <span id=t_idt>TxFifo</span> #(<span id=t_idt>EP2_FIFO_DEPTH</span>, <span id=t_idt>EP2_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP2TxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>TxFifoEP2REn</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEP2Empty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP2TxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP2TxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>TxFifoEP2Data</span>) );
+
+  <span id=t_idt>TxFifo</span> #(<span id=t_idt>EP3_FIFO_DEPTH</span>, <span id=t_idt>EP3_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP3TxFifo</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoREn</span>(<span id=t_idt>TxFifoEP3REn</span>), 
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEP3Empty</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP3TxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP3TxFifo</span>),
+  .<span id=t_idt>fifoDataOut</span>(<span id=t_idt>TxFifoEP3Data</span>) );
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>EP0_FIFO_DEPTH</span>, <span id=t_idt>EP0_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP0RxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>RxFifoEP0WEn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>RxFifoEP0Full</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP0RxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP0RxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>slaveRxFifoData</span>)  );
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>EP1_FIFO_DEPTH</span>, <span id=t_idt>EP1_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP1RxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>RxFifoEP1WEn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>RxFifoEP1Full</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP1RxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP1RxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>slaveRxFifoData</span>)  );
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>EP2_FIFO_DEPTH</span>, <span id=t_idt>EP2_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP2RxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>RxFifoEP2WEn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>RxFifoEP2Full</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP2RxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP2RxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>slaveRxFifoData</span>)  );
+
+<span id=t_idt>RxFifo</span> #(<span id=t_idt>EP3_FIFO_DEPTH</span>, <span id=t_idt>EP3_FIFO_ADDR_WIDTH</span>) <span id=t_idt>EP3RxFifo</span>(
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>fifoWEn</span>(<span id=t_idt>RxFifoEP3WEn</span>), 
+  .<span id=t_idt>fifoFull</span>(<span id=t_idt>RxFifoEP3Full</span>),
+  .<span id=t_idt>busAddress</span>(<span id=t_idt>address_i</span>[<span id=t_cns>2</span>:<span id=t_cns>0</span>]), 
+  .<span id=t_idt>busWriteEn</span>(<span id=t_idt>writeEn</span>), 
+  .<span id=t_idt>busStrobe_i</span>(<span id=t_idt>strobe_i</span>),
+  .<span id=t_idt>busFifoSelect</span>(<span id=t_idt>slaveEP3RxFifoSel</span>),
+  .<span id=t_idt>busDataIn</span>(<span id=t_idt>data_i</span>), 
+  .<span id=t_idt>busDataOut</span>(<span id=t_idt>dataFromEP3RxFifo</span>),
+  .<span id=t_idt>fifoDataIn</span>(<span id=t_idt>slaveRxFifoData</span>)  );
+
+<span id=t_kwd>endmodule</span>
+
+  
+  
+
+
+
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/wrapper/usbHostSlave.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/struct/is.js
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/struct/is.js	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/struct/is.js	(revision 264)
@@ -0,0 +1,3 @@
+
+var nn = (document.layers) ? 1:0;
+var ie = (document.all) ? 1:0;

Property changes on: common/components/usbhostslave/tags/start/doc/html/struct/is.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/struct/noexport.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/struct/noexport.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/struct/noexport.htm	(revision 264)
@@ -0,0 +1 @@
+Appropriate file was not exported
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/doc/html/struct/noexport.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/syn/Altera/cmp_state.ini
===================================================================
--- common/components/usbhostslave/tags/start/syn/Altera/cmp_state.ini	(nonexistent)
+++ common/components/usbhostslave/tags/start/syn/Altera/cmp_state.ini	(revision 264)
@@ -0,0 +1 @@
+35
\ No newline at end of file

Property changes on: common/components/usbhostslave/tags/start/syn/Altera/cmp_state.ini
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qsf
===================================================================
--- common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qsf	(nonexistent)
+++ common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qsf	(revision 264)
@@ -0,0 +1,93 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+# support information,  device programming or simulation file,  and any other
+# associated  documentation or information  provided by  Altera  or a partner
+# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+# other  use  of such  megafunction  design,  netlist,  support  information,
+# device programming or simulation file,  or any other  related documentation
+# or information  is prohibited  for  any  other purpose,  including, but not
+# limited to  modification,  reverse engineering,  de-compiling, or use  with
+# any other  silicon devices,  unless such use is  explicitly  licensed under
+# a separate agreement with  Altera  or a megafunction partner.  Title to the
+# intellectual property,  including patents,  copyrights,  trademarks,  trade
+# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+# support  information,  device programming or simulation file,  or any other
+# related documentation or information provided by  Altera  or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+# The default values for assignments are stored in the file
+#		usbHostSlave_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.1 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "05:36:22  OCTOBER 02, 2004"
+set_global_assignment -name LAST_QUARTUS_VERSION "4.1 SP2"
+set_global_assignment -name VERILOG_FILE ../../RTL/wrapper/usbHostSlave.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/USBSlaveControlBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/endpMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/fifoMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/sctxportarbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slavecontroller.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveDirectcontrol.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveGetpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveRxStatusMonitor.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/slaveSendpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/slaveController/usbSlaveControl.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/writeUSBWireData.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/lineControlUpdate.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/processRxBit.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/processRxByte.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/processTxByte.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/readUSBWireData.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/siereceiver.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/SIETransmitter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/updateCRC5.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/updateCRC16.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+set_global_assignment -name VERILOG_FILE ../../RTL/serialInterfaceEngine/usbTxWireArbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostSlaveMux/hostSlaveMuxBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostSlaveMux/hostSlaveMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/USBHostControlBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/directcontrol.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/getpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/hctxportarbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/hostcontroller.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/rxStatusMonitor.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sendpacket.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sendpacketarbiter.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sendpacketcheckpreamble.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/sofcontroller.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/softransmit.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/speedCtrlMux.v
+set_global_assignment -name VERILOG_FILE ../../RTL/hostController/usbHostControl.v
+set_global_assignment -name VERILOG_FILE ../../RTL/busInterface/wishBoneBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/TxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/fifoMem.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/fifoRTL.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/RxFifo.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/RxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/simFifoMem.v
+set_global_assignment -name VERILOG_FILE ../../RTL/buffers/TxFifo.v
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name TOP_LEVEL_ENTITY usbHostSlave
+set_global_assignment -name USER_LIBRARIES "c:\\projects\\usbhostslaveforoc\\rtl\\include/"
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP1C20F400C6

Property changes on: common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/buffers/TxFifo.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/buffers/TxFifo.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/buffers/TxFifo.v	(revision 264)
@@ -0,0 +1,132 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo write access via bus interface, fifo read access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module TxFifo(
+  busClk,
+  usbClk,
+  rstSyncToBusClk, 
+  rstSyncToUsbClk, 
+  fifoREn, 
+  fifoEmpty,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn,
+  busDataOut,
+  fifoDataOut ); 
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input busClk; 
+input usbClk; 
+input rstSyncToBusClk; 
+input rstSyncToUsbClk; 
+input fifoREn; 
+output fifoEmpty;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+output [7:0] fifoDataOut;
+
+wire busClk; 
+wire usbClk; 
+wire rstSyncToBusClk; 
+wire rstSyncToUsbClk; 
+wire fifoREn; 
+wire fifoEmpty;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .wrClk(busClk), 
+  .rdClk(usbClk), 
+  .rstSyncToWrClk(rstSyncToBusClk), 
+  .rstSyncToRdClk(rstSyncToUsbClk), 
+  .dataIn(busDataIn), 
+  .dataOut(fifoDataOut), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmptySyncToWrClk(forceEmptySyncToBusClk), 
+  .forceEmptySyncToRdClk(forceEmptySyncToUsbClk), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+TxfifoBI u_TxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .fifoSelect(busFifoSelect),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut), 
+  .fifoWEn(fifoWEn),
+  .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+  .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/buffers/TxFifo.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v	(revision 264)
@@ -0,0 +1,245 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBI.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "wishBoneBus_h.v"
+
+ 
+module wishBoneBI (
+  address, dataIn, dataOut, writeEn, 
+  strobe_i,
+  ack_o,
+  clk, rst,
+  hostControlSel, 
+  hostRxFifoSel, hostTxFifoSel,
+  slaveControlSel,
+  slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, 
+  slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, 
+  hostSlaveMuxSel,
+  dataFromHostControl,
+  dataFromHostRxFifo,
+  dataFromHostTxFifo,
+  dataFromSlaveControl,
+  dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+  dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+  dataFromHostSlaveMux
+   );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+  dataFromHostControl or
+  dataFromHostRxFifo or
+  dataFromHostTxFifo or
+  dataFromSlaveControl or
+  dataFromEP0RxFifo or 
+  dataFromEP1RxFifo or
+  dataFromEP2RxFifo or
+  dataFromEP3RxFifo or
+  dataFromHostSlaveMux or 
+  dataFromEP0TxFifo or
+  dataFromEP1TxFifo or
+  dataFromEP2TxFifo or
+  dataFromEP3TxFifo)
+begin
+  hostControlSel <= 1'b0;
+  hostRxFifoSel <= 1'b0;
+  hostTxFifoSel <= 1'b0;
+  slaveControlSel <= 1'b0;
+  slaveEP0RxFifoSel <= 1'b0;
+  slaveEP0TxFifoSel <= 1'b0;
+  slaveEP1RxFifoSel <= 1'b0;
+  slaveEP1TxFifoSel <= 1'b0;
+  slaveEP2RxFifoSel <= 1'b0;
+  slaveEP2TxFifoSel <= 1'b0;
+  slaveEP3RxFifoSel <= 1'b0;
+  slaveEP3TxFifoSel <= 1'b0;
+  hostSlaveMuxSel <= 1'b0;
+  case (address & `ADDRESS_DECODE_MASK)
+    `HCREG_BASE : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HCREG_BASE_PLUS_0X10 : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HOST_RX_FIFO_BASE : begin
+      hostRxFifoSel <= 1'b1;
+      dataOut <= dataFromHostRxFifo;
+    end
+    `HOST_TX_FIFO_BASE : begin
+      hostTxFifoSel <= 1'b1;
+      dataOut <= dataFromHostTxFifo;
+    end
+    `SCREG_BASE : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `SCREG_BASE_PLUS_0X10 : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `EP0_RX_FIFO_BASE : begin
+      slaveEP0RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0RxFifo;
+    end
+    `EP0_TX_FIFO_BASE : begin
+      slaveEP0TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0TxFifo;
+    end
+    `EP1_RX_FIFO_BASE : begin
+      slaveEP1RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1RxFifo;
+    end
+    `EP1_TX_FIFO_BASE : begin
+      slaveEP1TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1TxFifo;
+    end
+    `EP2_RX_FIFO_BASE : begin
+      slaveEP2RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2RxFifo;
+    end
+    `EP2_TX_FIFO_BASE : begin
+      slaveEP2TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2TxFifo;
+    end
+    `EP3_RX_FIFO_BASE : begin
+      slaveEP3RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3RxFifo;
+    end
+    `EP3_TX_FIFO_BASE : begin
+      slaveEP3TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3TxFifo;
+    end
+    `HOST_SLAVE_CONTROL_BASE : begin
+      hostSlaveMuxSel <= 1'b1; 
+      dataOut <= dataFromHostSlaveMux;
+    end
+    default: 
+      dataOut <= 8'h00;
+  endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+  ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+  ack_immediate <= strobe_i;
+end 
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+  if (writeEn == 1'b0 &&
+      (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+  begin
+    ack_o <= ack_delayed & ack_immediate;
+  end
+  else
+  begin
+    ack_o <= ack_immediate;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html	(revision 264)
@@ -0,0 +1,45 @@
+<html>
+<script language="JavaScript">
+var RootProject = "../../../";
+//----------------------------------------------------------------------------
+FUBSNUMBER = 0;
+//----------------------------------------------------------------------------
+FUB = new Array();
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+var PageX = 1700 ;
+var PageY = 2200 ;
+var PageNumber= 15 ; //current page number
+var PagePrev  = -1   ; // if(PagePrev == -1) absent
+var PageNext  = -1   ; // if(PagePrev == -1) absent
+//----------------------------------------------------------------------------
+var w = 1020;
+var h = 1320;
+//----------------------------------------------------------------------------
+SchemImage = new Image();
+SchemImage.src = "./slavecontroller_START.png" ; //Caching image
+//----------------------------------------------------------------------------
+SchemCode = "./slavecontroller.v/index.htm";
+//----------------------------------------------------------------------------
+</script>
+
+<script language="JavaScript" src="./../../../struct/is.js"></script>
+<script language="JavaScript" src="./../../../struct/fsmtools.js"></script>
+<script language="JavaScript">function XNotify(){parent.ToolsOn();}</script>
+
+<body leftmargin="0" topmargin="0" rightmargin="0" bottommargin="0" marhinheight="0" marginwidth="0" 
+bgcolor="silver" background="./../../../images/fsm/back.gif"
+onLoad="XNotify()"
+>
+<script language="JavaScript">
+<!--
+document.writeln(GetToolBar());
+//-->
+</script>
+
+</body>
+
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/slavecontroller.asf/toolbar15.html
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/src/slaveController/usbSlaveControl.v/index.htm
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/src/slaveController/usbSlaveControl.v/index.htm	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/src/slaveController/usbSlaveControl.v/index.htm	(revision 264)
@@ -0,0 +1,511 @@
+<html>
+<head>
+<title>usbSlaveControl.v</title>
+<link rel="stylesheet" href="./../../../css/hde.css">
+<meta name="Author" content="Steve, Base2Designs">
+<meta name="Generator" content="Active-HDL, Version 6.3.1444, Expiration Date: September 30, 2004\n\nCopyright � ALDEC, Inc. All rights reserved.">
+</head>
+<body>
+<pre>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// usbSlaveControl.v                                            ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This file is part of the usbhostslave opencores effort.</span>
+<span id=t_com>//// &lt;http://www.opencores.org/cores//&gt;                           ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Module Description:                                          ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// To Do:                                                       ////</span>
+<span id=t_com>//// </span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Author(s):                                                   ////</span>
+<span id=t_com>//// - Steve Fielding, sfielding@base2designs.com                 ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file may be used and distributed without         ////</span>
+<span id=t_com>//// restriction provided that this copyright statement is not    ////</span>
+<span id=t_com>//// removed from the file and that any derivative work contains  ////</span>
+<span id=t_com>//// the original copyright notice and the associated disclaimer. ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source file is free software; you can redistribute it   ////</span>
+<span id=t_com>//// and/or modify it under the terms of the GNU Lesser General   ////</span>
+<span id=t_com>//// Public License as published by the Free Software Foundation; ////</span>
+<span id=t_com>//// either version 2.1 of the License, or (at your option) any   ////</span>
+<span id=t_com>//// later version.                                               ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// This source is distributed in the hope that it will be       ////</span>
+<span id=t_com>//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////</span>
+<span id=t_com>//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////</span>
+<span id=t_com>//// PURPOSE. See the GNU Lesser General Public License for more  ////</span>
+<span id=t_com>//// details.                                                     ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//// You should have received a copy of the GNU Lesser General    ////</span>
+<span id=t_com>//// Public License along with this source; if not, download it   ////</span>
+<span id=t_com>//// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////</span>
+<span id=t_com>////                                                              ////</span>
+<span id=t_com>//////////////////////////////////////////////////////////////////////</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Id: index.htm,v 1.1.1.1 2004-10-11 04:00:42 sfielding Exp $</span>
+<span id=t_com>//</span>
+<span id=t_com>// CVS Revision History</span>
+<span id=t_com>//</span>
+<span id=t_com>// $Log: not supported by cvs2svn $</span>
+<span id=t_com>//</span>
+
+<span id=t_kwd>module</span> <span id=t_idt>usbSlaveControl</span>(
+  <span id=t_idt>clk</span>, <span id=t_idt>rst</span>,
+  <span id=t_com>//getPacket</span>
+  <span id=t_idt>RxByteStatus</span>, <span id=t_idt>RxData</span>, <span id=t_idt>RxDataValid</span>,
+  <span id=t_idt>SIERxTimeOut</span>, <span id=t_idt>RxFifoData</span>,
+  <span id=t_com>//speedCtrlMux</span>
+  <span id=t_idt>fullSpeedRate</span>, <span id=t_idt>fullSpeedPol</span>,
+  <span id=t_com>//SCTxPortArbiter</span>
+  <span id=t_idt>SCTxPortEn</span>, <span id=t_idt>SCTxPortRdy</span>,
+  <span id=t_idt>SCTxPortData</span>, <span id=t_idt>SCTxPortCtrl</span>,
+  <span id=t_com>//rxStatusMonitor</span>
+  <span id=t_idt>connectStateIn</span>, 
+  <span id=t_idt>resumeDetectedIn</span>,
+  <span id=t_com>//USBHostControlBI </span>
+  <span id=t_idt>busAddress</span>,
+  <span id=t_idt>busDataIn</span>, 
+  <span id=t_idt>busDataOut</span>, 
+  <span id=t_idt>busWriteEn</span>,
+  <span id=t_idt>busStrobe_i</span>,
+  <span id=t_idt>SOFRxedIntOut</span>, 
+  <span id=t_idt>resetEventIntOut</span>, 
+  <span id=t_idt>resumeIntOut</span>, 
+  <span id=t_idt>transDoneIntOut</span>,
+  <span id=t_idt>NAKSentIntOut</span>,
+  <span id=t_idt>slaveControlSelect</span>,
+  <span id=t_com>//fifoMux</span>
+  <span id=t_idt>TxFifoEP0REn</span>,
+  <span id=t_idt>TxFifoEP1REn</span>,
+  <span id=t_idt>TxFifoEP2REn</span>,
+  <span id=t_idt>TxFifoEP3REn</span>,
+  <span id=t_idt>TxFifoEP0Data</span>,
+  <span id=t_idt>TxFifoEP1Data</span>,
+  <span id=t_idt>TxFifoEP2Data</span>,
+  <span id=t_idt>TxFifoEP3Data</span>,
+  <span id=t_idt>TxFifoEP0Empty</span>,
+  <span id=t_idt>TxFifoEP1Empty</span>,
+  <span id=t_idt>TxFifoEP2Empty</span>,
+  <span id=t_idt>TxFifoEP3Empty</span>,
+  <span id=t_idt>RxFifoEP0WEn</span>,
+  <span id=t_idt>RxFifoEP1WEn</span>,
+  <span id=t_idt>RxFifoEP2WEn</span>,
+  <span id=t_idt>RxFifoEP3WEn</span>,
+  <span id=t_idt>RxFifoEP0Full</span>,
+  <span id=t_idt>RxFifoEP1Full</span>,
+  <span id=t_idt>RxFifoEP2Full</span>,
+  <span id=t_idt>RxFifoEP3Full</span>
+   );
+
+<span id=t_kwd>input</span> <span id=t_idt>clk</span>, <span id=t_idt>rst</span>;
+<span id=t_com>//getPacket</span>
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteStatus</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxData</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxDataValid</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxFifoData</span>;
+<span id=t_com>//speedCtrlMux</span>
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>output</span> <span id=t_idt>fullSpeedPol</span>;
+<span id=t_com>//HCTxPortArbiter</span>
+<span id=t_kwd>output</span> <span id=t_idt>SCTxPortEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>SCTxPortRdy</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCtrl</span>;
+<span id=t_com>//rxStatusMonitor</span>
+<span id=t_kwd>input</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_com>//USBHostControlBI </span>
+<span id=t_kwd>input</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>output</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>; 
+<span id=t_kwd>input</span> <span id=t_idt>busWriteEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>output</span> <span id=t_idt>SOFRxedIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>resetEventIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>resumeIntOut</span>; 
+<span id=t_kwd>output</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>output</span> <span id=t_idt>NAKSentIntOut</span>;
+<span id=t_kwd>input</span> <span id=t_idt>slaveControlSelect</span>;
+<span id=t_com>//fifoMux</span>
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>input</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>input</span> <span id=t_idt>TxFifoEP3Empty</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>output</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>input</span> <span id=t_idt>RxFifoEP3Full</span>;
+
+<span id=t_kwd>wire</span> <span id=t_idt>clk</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>rst</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxByteStatus</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxDataValid</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SIERxTimeOut</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>RxFifoData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedRate</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>fullSpeedPol</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortData</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>SCTxPortCtrl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeDetectedIn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>4</span>:<span id=t_cns>0</span>] <span id=t_idt>busAddress</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataIn</span>; 
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>busDataOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>busWriteEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>busStrobe_i</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFRxedIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>resetEventIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>transDoneIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>NAKSentIntOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControlSelect</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2REn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3REn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP0Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP1Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP2Data</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoEP3Data</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP0Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP1Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP2Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEP3Empty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3WEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP0Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP1Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP2Full</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoEP3Full</span>;
+
+<span id=t_com>//internal wiring</span>
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>directCntlData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directCntlWEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketCntl</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>sendPacketData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketGnt</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketReq</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>sendPacketWEn</span>;   
+<span id=t_kwd>wire</span> <span id=t_idt>SCTxPortArbRdyOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>transDone</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>directLineState</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>directLineCtrlEn</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>RxPID</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>connectStateOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resumeIntFromRxStatusMon</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3TransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3NAKTransTypeReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3ControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP0StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP1StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP2StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>endP3StatusReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>6</span>:<span id=t_cns>0</span>] <span id=t_idt>USBTgtAddress</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>10</span>:<span id=t_cns>0</span>] <span id=t_idt>frameNum</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP0Rdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP1Rdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP2Rdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEP3Rdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SCGlobalEn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>ACKRxed</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>CRCError</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RXOverflow</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>RXTimeOut</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>bitStuffError</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>dataSequence</span>; 
+<span id=t_kwd>wire</span> <span id=t_idt>stallSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>NAKSent</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>SOFRxed</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>endPControlReg</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transTypeNAK</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>1</span>:<span id=t_cns>0</span>] <span id=t_idt>transType</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>currEndP</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>getPacketREn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>getPacketRdy</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>3</span>:<span id=t_cns>0</span>] <span id=t_idt>slaveControllerPIDOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControllerReadyIn</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>slaveControllerWEnOut</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoRE</span>;
+<span id=t_kwd>wire</span> [<span id=t_cns>7</span>:<span id=t_cns>0</span>] <span id=t_idt>TxFifoData</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>TxFifoEmpty</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoWE</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>RxFifoFull</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>resetEventFromRxStatusMon</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>clrEPRdy</span>;
+<span id=t_kwd>wire</span> <span id=t_idt>endPMuxErrorsWEn</span>;
+
+<span id=t_idt>USBSlaveControlBI</span> <span id=t_idt>u_USBSlaveControlBI</span>
+  (.<span id=t_idt>address</span>(<span id=t_idt>busAddress</span>),
+  .<span id=t_idt>dataIn</span>(<span id=t_idt>busDataIn</span>), 
+  .<span id=t_idt>dataOut</span>(<span id=t_idt>busDataOut</span>), 
+  .<span id=t_idt>writeEn</span>(<span id=t_idt>busWriteEn</span>),
+  .<span id=t_idt>strobe_i</span>(<span id=t_idt>busStrobe_i</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>SOFRxedIntOut</span>(<span id=t_idt>SOFRxedIntOut</span>), 
+  .<span id=t_idt>resetEventIntOut</span>(<span id=t_idt>resetEventIntOut</span>), 
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>resumeIntOut</span>), 
+  .<span id=t_idt>transDoneIntOut</span>(<span id=t_idt>transDoneIntOut</span>),
+  .<span id=t_idt>NAKSentIntOut</span>(<span id=t_idt>NAKSentIntOut</span>),
+  .<span id=t_idt>endP0TransTypeReg</span>(<span id=t_idt>endP0TransTypeReg</span>), 
+  .<span id=t_idt>endP0NAKTransTypeReg</span>(<span id=t_idt>endP0NAKTransTypeReg</span>),
+  .<span id=t_idt>endP1TransTypeReg</span>(<span id=t_idt>endP1TransTypeReg</span>), 
+  .<span id=t_idt>endP1NAKTransTypeReg</span>(<span id=t_idt>endP1NAKTransTypeReg</span>),
+  .<span id=t_idt>endP2TransTypeReg</span>(<span id=t_idt>endP2TransTypeReg</span>), 
+  .<span id=t_idt>endP2NAKTransTypeReg</span>(<span id=t_idt>endP2NAKTransTypeReg</span>),
+  .<span id=t_idt>endP3TransTypeReg</span>(<span id=t_idt>endP3TransTypeReg</span>), 
+  .<span id=t_idt>endP3NAKTransTypeReg</span>(<span id=t_idt>endP3NAKTransTypeReg</span>),
+  .<span id=t_idt>endP0ControlReg</span>(<span id=t_idt>endP0ControlReg</span>),
+  .<span id=t_idt>endP1ControlReg</span>(<span id=t_idt>endP1ControlReg</span>),
+  .<span id=t_idt>endP2ControlReg</span>(<span id=t_idt>endP2ControlReg</span>),
+  .<span id=t_idt>endP3ControlReg</span>(<span id=t_idt>endP3ControlReg</span>),
+  .<span id=t_idt>EP0StatusReg</span>(<span id=t_idt>endP0StatusReg</span>),
+  .<span id=t_idt>EP1StatusReg</span>(<span id=t_idt>endP1StatusReg</span>),
+  .<span id=t_idt>EP2StatusReg</span>(<span id=t_idt>endP2StatusReg</span>),
+  .<span id=t_idt>EP3StatusReg</span>(<span id=t_idt>endP3StatusReg</span>),
+  .<span id=t_idt>SCAddrReg</span>(<span id=t_idt>USBTgtAddress</span>), 
+  .<span id=t_idt>frameNum</span>(<span id=t_idt>frameNum</span>),
+  .<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectStateOut</span>),
+  .<span id=t_idt>SOFRxedIn</span>(<span id=t_idt>SOFRxed</span>), 
+  .<span id=t_idt>resetEventIn</span>(<span id=t_idt>resetEventFromRxStatusMon</span>), 
+  .<span id=t_idt>resumeIntIn</span>(<span id=t_idt>resumeIntFromRxStatusMon</span>), 
+  .<span id=t_idt>transDoneIn</span>(<span id=t_idt>transDone</span>),
+  .<span id=t_idt>NAKSentIn</span>(<span id=t_idt>NAKSent</span>),
+  .<span id=t_idt>slaveControlSelect</span>(<span id=t_idt>slaveControlSelect</span>),
+  .<span id=t_idt>clrEP0Ready</span>(<span id=t_idt>clrEP0Rdy</span>), 
+  .<span id=t_idt>clrEP1Ready</span>(<span id=t_idt>clrEP1Rdy</span>), 
+  .<span id=t_idt>clrEP2Ready</span>(<span id=t_idt>clrEP2Rdy</span>), 
+  .<span id=t_idt>clrEP3Ready</span>(<span id=t_idt>clrEP3Rdy</span>),
+  .<span id=t_idt>TxLineState</span>(<span id=t_idt>directLineState</span>),
+  .<span id=t_idt>LineDirectControlEn</span>(<span id=t_idt>directLineCtrlEn</span>),
+  .<span id=t_idt>fullSpeedPol</span>(<span id=t_idt>fullSpeedPol</span>), 
+  .<span id=t_idt>fullSpeedRate</span>(<span id=t_idt>fullSpeedRate</span>),
+  .<span id=t_idt>SCGlobalEn</span>(<span id=t_idt>SCGlobalEn</span>)
+  );
+
+<span id=t_idt>slavecontroller</span> <span id=t_idt>u_slavecontroller</span>
+  (.<span id=t_idt>CRCError</span>(<span id=t_idt>CRCError</span>), 
+  .<span id=t_idt>NAKSent</span>(<span id=t_idt>NAKSent</span>), 
+  .<span id=t_idt>RxByte</span>(<span id=t_idt>RxData</span>), 
+  .<span id=t_idt>RxDataWEn</span>(<span id=t_idt>RxDataValid</span>), 
+  .<span id=t_idt>RxOverflow</span>(<span id=t_idt>RXOverflow</span>), 
+  .<span id=t_idt>RxStatus</span>(<span id=t_idt>RxByteStatus</span>), 
+  .<span id=t_idt>RxTimeOut</span>(<span id=t_idt>RXTimeOut</span>), 
+  .<span id=t_idt>SCGlobalEn</span>(<span id=t_idt>SCGlobalEn</span>), 
+  .<span id=t_idt>SOFRxed</span>(<span id=t_idt>SOFRxed</span>), 
+  .<span id=t_idt>USBEndPControlReg</span>(<span id=t_idt>endPControlReg</span>), 
+  .<span id=t_idt>USBEndPNakTransTypeReg</span>(<span id=t_idt>transTypeNAK</span>), 
+  .<span id=t_idt>USBEndPTransTypeReg</span>(<span id=t_idt>transType</span>), 
+  .<span id=t_idt>USBEndP</span>(<span id=t_idt>currEndP</span>), 
+  .<span id=t_idt>USBTgtAddress</span>(<span id=t_idt>USBTgtAddress</span>),
+  .<span id=t_idt>bitStuffError</span>(<span id=t_idt>bitStuffError</span>), 
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>clrEPRdy</span>(<span id=t_idt>clrEPRdy</span>), 
+  .<span id=t_idt>endPMuxErrorsWEn</span>(<span id=t_idt>endPMuxErrorsWEn</span>), 
+  .<span id=t_idt>frameNum</span>(<span id=t_idt>frameNum</span>), 
+  .<span id=t_idt>getPacketREn</span>(<span id=t_idt>getPacketREn</span>), 
+  .<span id=t_idt>getPacketRdy</span>(<span id=t_idt>getPacketRdy</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>), 
+  .<span id=t_idt>sendPacketPID</span>(<span id=t_idt>slaveControllerPIDOut</span>), 
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>slaveControllerReadyIn</span>), 
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>slaveControllerWEnOut</span>), 
+  .<span id=t_idt>stallSent</span>(<span id=t_idt>stallSent</span>), 
+  .<span id=t_idt>transDone</span>(<span id=t_idt>transDone</span>) 
+    );
+
+
+<span id=t_idt>endpMux</span> <span id=t_idt>u_endpMux</span> (
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>), 
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>currEndP</span>(<span id=t_idt>currEndP</span>),
+  .<span id=t_idt>NAKSent</span>(<span id=t_idt>NAKSent</span>),
+  .<span id=t_idt>stallSent</span>(<span id=t_idt>stallSent</span>),
+  .<span id=t_idt>CRCError</span>(<span id=t_idt>CRCError</span>),
+  .<span id=t_idt>bitStuffError</span>(<span id=t_idt>bitStuffError</span>),
+  .<span id=t_idt>RxOverflow</span>(<span id=t_idt>RXOverflow</span>),
+  .<span id=t_idt>RxTimeOut</span>(<span id=t_idt>RXTimeOut</span>),
+  .<span id=t_idt>dataSequence</span>(<span id=t_idt>dataSequence</span>),
+  .<span id=t_idt>ACKRxed</span>(<span id=t_idt>ACKRxed</span>),
+  .<span id=t_idt>transType</span>(<span id=t_idt>transType</span>),
+  .<span id=t_idt>transTypeNAK</span>(<span id=t_idt>transTypeNAK</span>),
+  .<span id=t_idt>endPControlReg</span>(<span id=t_idt>endPControlReg</span>),
+  .<span id=t_idt>clrEPRdy</span>(<span id=t_idt>clrEPRdy</span>),
+  .<span id=t_idt>endPMuxErrorsWEn</span>(<span id=t_idt>endPMuxErrorsWEn</span>),
+  .<span id=t_idt>endP0ControlReg</span>(<span id=t_idt>endP0ControlReg</span>),
+  .<span id=t_idt>endP1ControlReg</span>(<span id=t_idt>endP1ControlReg</span>),
+  .<span id=t_idt>endP2ControlReg</span>(<span id=t_idt>endP2ControlReg</span>),
+  .<span id=t_idt>endP3ControlReg</span>(<span id=t_idt>endP3ControlReg</span>),
+  .<span id=t_idt>endP0StatusReg</span>(<span id=t_idt>endP0StatusReg</span>),
+  .<span id=t_idt>endP1StatusReg</span>(<span id=t_idt>endP1StatusReg</span>),
+  .<span id=t_idt>endP2StatusReg</span>(<span id=t_idt>endP2StatusReg</span>),
+  .<span id=t_idt>endP3StatusReg</span>(<span id=t_idt>endP3StatusReg</span>),
+  .<span id=t_idt>endP0TransTypeReg</span>(<span id=t_idt>endP0TransTypeReg</span>),
+  .<span id=t_idt>endP1TransTypeReg</span>(<span id=t_idt>endP1TransTypeReg</span>),
+  .<span id=t_idt>endP2TransTypeReg</span>(<span id=t_idt>endP2TransTypeReg</span>),
+  .<span id=t_idt>endP3TransTypeReg</span>(<span id=t_idt>endP3TransTypeReg</span>),
+  .<span id=t_idt>endP0NAKTransTypeReg</span>(<span id=t_idt>endP0NAKTransTypeReg</span>),
+  .<span id=t_idt>endP1NAKTransTypeReg</span>(<span id=t_idt>endP1NAKTransTypeReg</span>),
+  .<span id=t_idt>endP2NAKTransTypeReg</span>(<span id=t_idt>endP2NAKTransTypeReg</span>),
+  .<span id=t_idt>endP3NAKTransTypeReg</span>(<span id=t_idt>endP3NAKTransTypeReg</span>),
+  .<span id=t_idt>clrEP0Rdy</span>(<span id=t_idt>clrEP0Rdy</span>),
+  .<span id=t_idt>clrEP1Rdy</span>(<span id=t_idt>clrEP1Rdy</span>),
+  .<span id=t_idt>clrEP2Rdy</span>(<span id=t_idt>clrEP2Rdy</span>),
+  .<span id=t_idt>clrEP3Rdy</span>(<span id=t_idt>clrEP3Rdy</span>)
+    );
+
+<span id=t_idt>slaveSendPacket</span> <span id=t_idt>u_slaveSendPacket</span>
+  (.<span id=t_idt>PID</span>(<span id=t_idt>slaveControllerPIDOut</span>), 
+  .<span id=t_idt>SCTxPortCntl</span>(<span id=t_idt>sendPacketCntl</span>),
+  .<span id=t_idt>SCTxPortData</span>(<span id=t_idt>sendPacketData</span>),
+  .<span id=t_idt>SCTxPortGnt</span>(<span id=t_idt>sendPacketGnt</span>),
+  .<span id=t_idt>SCTxPortRdy</span>(<span id=t_idt>SCTxPortArbRdyOut</span>),
+  .<span id=t_idt>SCTxPortReq</span>(<span id=t_idt>sendPacketReq</span>),
+  .<span id=t_idt>SCTxPortWEn</span>(<span id=t_idt>sendPacketWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>fifoData</span>(<span id=t_idt>TxFifoData</span>),
+  .<span id=t_idt>fifoEmpty</span>(<span id=t_idt>TxFifoEmpty</span>),
+  .<span id=t_idt>fifoReadEn</span>(<span id=t_idt>TxFifoRE</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketRdy</span>(<span id=t_idt>slaveControllerReadyIn</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>slaveControllerWEnOut</span>) );
+
+<span id=t_idt>slaveDirectControl</span> <span id=t_idt>u_slaveDirectControl</span>
+  (.<span id=t_idt>SCTxPortCntl</span>(<span id=t_idt>directCntlCntl</span>),
+  .<span id=t_idt>SCTxPortData</span>(<span id=t_idt>directCntlData</span>),
+  .<span id=t_idt>SCTxPortGnt</span>(<span id=t_idt>directCntlGnt</span>),
+  .<span id=t_idt>SCTxPortRdy</span>(<span id=t_idt>SCTxPortArbRdyOut</span>),
+  .<span id=t_idt>SCTxPortReq</span>(<span id=t_idt>directCntlReq</span>),
+  .<span id=t_idt>SCTxPortWEn</span>(<span id=t_idt>directCntlWEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>directControlEn</span>(<span id=t_idt>directLineCtrlEn</span>),
+  .<span id=t_idt>directControlLineState</span>(<span id=t_idt>directLineState</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>SCTxPortArbiter</span> <span id=t_idt>u_SCTxPortArbiter</span>
+  (.<span id=t_idt>SCTxPortCntl</span>(<span id=t_idt>SCTxPortCtrl</span>),
+  .<span id=t_idt>SCTxPortData</span>(<span id=t_idt>SCTxPortData</span>),
+  .<span id=t_idt>SCTxPortRdyIn</span>(<span id=t_idt>SCTxPortRdy</span>),
+  .<span id=t_idt>SCTxPortRdyOut</span>(<span id=t_idt>SCTxPortArbRdyOut</span>),
+  .<span id=t_idt>SCTxPortWEnable</span>(<span id=t_idt>SCTxPortEn</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>directCntlCntl</span>(<span id=t_idt>directCntlCntl</span>),
+  .<span id=t_idt>directCntlData</span>(<span id=t_idt>directCntlData</span>),
+  .<span id=t_idt>directCntlGnt</span>(<span id=t_idt>directCntlGnt</span>),
+  .<span id=t_idt>directCntlReq</span>(<span id=t_idt>directCntlReq</span>),
+  .<span id=t_idt>directCntlWEn</span>(<span id=t_idt>directCntlWEn</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>),
+  .<span id=t_idt>sendPacketCntl</span>(<span id=t_idt>sendPacketCntl</span>),
+  .<span id=t_idt>sendPacketData</span>(<span id=t_idt>sendPacketData</span>),
+  .<span id=t_idt>sendPacketGnt</span>(<span id=t_idt>sendPacketGnt</span>),
+  .<span id=t_idt>sendPacketReq</span>(<span id=t_idt>sendPacketReq</span>),
+  .<span id=t_idt>sendPacketWEn</span>(<span id=t_idt>sendPacketWEn</span>) );   
+
+
+<span id=t_idt>slaveGetPacket</span> <span id=t_idt>u_slaveGetPacket</span>
+  (.<span id=t_idt>ACKRxed</span>(<span id=t_idt>ACKRxed</span>), 
+  .<span id=t_idt>CRCError</span>(<span id=t_idt>CRCError</span>), 
+  .<span id=t_idt>RXDataIn</span>(<span id=t_idt>RxData</span>),
+  .<span id=t_idt>RXDataValid</span>(<span id=t_idt>RxDataValid</span>),
+  .<span id=t_idt>RXFifoData</span>(<span id=t_idt>RxFifoData</span>),
+  .<span id=t_idt>RXFifoFull</span>(<span id=t_idt>RxFifoFull</span>),
+  .<span id=t_idt>RXFifoWEn</span>(<span id=t_idt>RxFifoWE</span>),
+  .<span id=t_idt>RXPacketRdy</span>(<span id=t_idt>getPacketRdy</span>),
+  .<span id=t_idt>RXStreamStatusIn</span>(<span id=t_idt>RxByteStatus</span>),
+  .<span id=t_idt>RxPID</span>(<span id=t_idt>RxPID</span>),
+  .<span id=t_idt>SIERxTimeOut</span>(<span id=t_idt>SIERxTimeOut</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>RXOverflow</span>(<span id=t_idt>RXOverflow</span>), 
+  .<span id=t_idt>RXTimeOut</span>(<span id=t_idt>RXTimeOut</span>), 
+  .<span id=t_idt>bitStuffError</span>(<span id=t_idt>bitStuffError</span>), 
+  .<span id=t_idt>dataSequence</span>(<span id=t_idt>dataSequence</span>), 
+  .<span id=t_idt>getPacketEn</span>(<span id=t_idt>getPacketREn</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>) ); 
+
+<span id=t_idt>slaveRxStatusMonitor</span>  <span id=t_idt>u_slaveRxStatusMonitor</span>
+  (.<span id=t_idt>connectStateIn</span>(<span id=t_idt>connectStateIn</span>),
+  .<span id=t_idt>connectStateOut</span>(<span id=t_idt>connectStateOut</span>),
+  .<span id=t_idt>resumeDetectedIn</span>(<span id=t_idt>resumeDetectedIn</span>),
+  .<span id=t_idt>resetEventOut</span>(<span id=t_idt>resetEventFromRxStatusMon</span>),
+  .<span id=t_idt>resumeIntOut</span>(<span id=t_idt>resumeIntFromRxStatusMon</span>),
+  .<span id=t_idt>clk</span>(<span id=t_idt>clk</span>),
+  .<span id=t_idt>rst</span>(<span id=t_idt>rst</span>)  );    
+  
+<span id=t_idt>fifoMux</span> <span id=t_idt>u_fifoMux</span> (
+  .<span id=t_idt>currEndP</span>(<span id=t_idt>currEndP</span>),
+  <span id=t_com>//TxFifo</span>
+  .<span id=t_idt>TxFifoREn</span>(<span id=t_idt>TxFifoRE</span>),
+  .<span id=t_idt>TxFifoEP0REn</span>(<span id=t_idt>TxFifoEP0REn</span>),
+  .<span id=t_idt>TxFifoEP1REn</span>(<span id=t_idt>TxFifoEP1REn</span>),
+  .<span id=t_idt>TxFifoEP2REn</span>(<span id=t_idt>TxFifoEP2REn</span>),
+  .<span id=t_idt>TxFifoEP3REn</span>(<span id=t_idt>TxFifoEP3REn</span>),
+  .<span id=t_idt>TxFifoData</span>(<span id=t_idt>TxFifoData</span>),
+  .<span id=t_idt>TxFifoEP0Data</span>(<span id=t_idt>TxFifoEP0Data</span>),
+  .<span id=t_idt>TxFifoEP1Data</span>(<span id=t_idt>TxFifoEP1Data</span>),
+  .<span id=t_idt>TxFifoEP2Data</span>(<span id=t_idt>TxFifoEP2Data</span>),
+  .<span id=t_idt>TxFifoEP3Data</span>(<span id=t_idt>TxFifoEP3Data</span>),
+  .<span id=t_idt>TxFifoEmpty</span>(<span id=t_idt>TxFifoEmpty</span>),
+  .<span id=t_idt>TxFifoEP0Empty</span>(<span id=t_idt>TxFifoEP0Empty</span>),
+  .<span id=t_idt>TxFifoEP1Empty</span>(<span id=t_idt>TxFifoEP1Empty</span>),
+  .<span id=t_idt>TxFifoEP2Empty</span>(<span id=t_idt>TxFifoEP2Empty</span>),
+  .<span id=t_idt>TxFifoEP3Empty</span>(<span id=t_idt>TxFifoEP3Empty</span>),
+  <span id=t_com>//RxFifo</span>
+  .<span id=t_idt>RxFifoWEn</span>(<span id=t_idt>RxFifoWE</span>),
+  .<span id=t_idt>RxFifoEP0WEn</span>(<span id=t_idt>RxFifoEP0WEn</span>),
+  .<span id=t_idt>RxFifoEP1WEn</span>(<span id=t_idt>RxFifoEP1WEn</span>),
+  .<span id=t_idt>RxFifoEP2WEn</span>(<span id=t_idt>RxFifoEP2WEn</span>),
+  .<span id=t_idt>RxFifoEP3WEn</span>(<span id=t_idt>RxFifoEP3WEn</span>),
+  .<span id=t_idt>RxFifoFull</span>(<span id=t_idt>RxFifoFull</span>),
+  .<span id=t_idt>RxFifoEP0Full</span>(<span id=t_idt>RxFifoEP0Full</span>),
+  .<span id=t_idt>RxFifoEP1Full</span>(<span id=t_idt>RxFifoEP1Full</span>),
+  .<span id=t_idt>RxFifoEP2Full</span>(<span id=t_idt>RxFifoEP2Full</span>),
+  .<span id=t_idt>RxFifoEP3Full</span>(<span id=t_idt>RxFifoEP3Full</span>)
+    );
+
+<span id=t_kwd>endmodule</span>
+
+  
+  
+
+
+
+
+
+</pre>
+</body>
+</html>

Property changes on: common/components/usbhostslave/tags/start/doc/html/src/slaveController/usbSlaveControl.v/index.htm
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/struct/fsmtools.js
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/struct/fsmtools.js	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/struct/fsmtools.js	(revision 264)
@@ -0,0 +1,461 @@
+
+var zoo = 100;
+var pzoo = 100;
+var zoom_inc = 2; //or 50
+var SCHEM = "DIAGRAM"
+var ViewX=w;
+var ViewY=h;
+var DEBUG_MODE = 1;
+//----------------------------------------------------------------------------
+IRoot = RootProject + "images/fsm/";
+OV = "over.gif";
+OD = "down.gif";
+//----------------------------------------------------------------------------
+function CodeView(){
+window.parent.location = SchemCode;
+}
+//----------------------------------------------------------------------------
+function GotoPage(){
+	if(PageNext==-1){
+		alert("no page");
+		return;
+	}
+window.parent.location = "./content"+PageNext+".html"
+}
+//----------------------------------------------------------------------------
+function fubclick(lnk){
+	if(lnk!="")
+		window.parent.location = lnk;
+}
+//----------------------------------------------------------------------------
+function DUMP() { 
+	var dump_msg;
+	dump_msg= "w.........."+w+"\n";
+	dump_msg+="h.........."+h+"\n";
+	dump_msg+="zoo........"+zoo+"\n";
+	dump_msg+="pzoo......."+pzoo+"\n";
+	dump_msg+="zoo_inc...."+zoom_inc+"\n";
+	dump_msg+="schem......"+SCHEM+"\n";
+	dump_msg+="viewx......"+ViewX+"\n";
+	dump_msg+="viewy......"+ViewY+"\n";
+	dump_msg+="pagex......"+PageX+"\n";
+	dump_msg+="pagey......"+PageY+"\n";
+	dump_msg+="IE........."+ie+"\n";
+	dump_msg+="NN........."+nn+"\n";
+	alert(dump_msg);
+}
+function alertd(msg) {
+	if(DEBUG_MODE==1)
+		alert(msg)
+}
+//----------------------------------------------------------------------------
+var MyImage;
+var MyDoc;
+var MyWindow;
+//----------------------------------------------------------------------------
+function Init(){
+MyImage = window.parent.frames["xschem"].window.document.images[SCHEM];
+MyImage.src = SchemImage.src;
+MyDoc = window.parent.frames["xschem"].window.document;
+MyWindow =  window.parent.frames["xschem"].window;
+//zoomfit();
+//�������� - � ��, �᫨ ��࠭�� �� ����㦥��?
+//alert("init")
+}
+//----------------------------------------------------------------------------
+function ZRefresh(){
+	ViewX = w*zoo/100;
+	ViewY = h*zoo/100;
+
+	if(ViewX<=0 || ViewY<=0 || ViewX==NaN || ViewY==NaN){
+		alertd("Z-Error: " + ViewX + "##" + ViewY + "##" + zoo + "##" + pzoo);
+		DUMP();
+		ViewX=w;
+		ViewX=h;
+		zoo=100;
+		pzoo=100;		
+	}
+
+	MyImage.width  = ViewX;
+	MyImage.height = ViewY;
+
+	if(!ie&&!nn) //NN6
+		MyImage.src = SchemImage.src;
+	if(ie){
+		window.top.resizeBy(1, 1);  
+		window.top.resizeBy(-1, -1);
+	}
+}
+function zoomin(){
+	pzoo=zoo;
+	zoo*=zoom_inc;
+	ZRefresh();
+}
+function zoomout(){
+	if(zoo<=zoom_inc) return;
+	pzoo=zoo;
+	zoo/=zoom_inc;
+	ZRefresh();
+}
+function zoomfit(){	
+	pw=w;ph=h;
+	var cw;var ch;
+	if(ie || nn){
+		if(!MyDoc.body.clientWidth) {
+
+			if (self.screen) { // for NN4 and IE4 
+				cw = screen.width/1.5 ; // What can I do for Opera
+				ch = screen.height/1.5; // What can I do for Opera
+			} else if (self.java) { // for NN3 with enabled Java 
+				var jkit = java.awt.Toolkit.getDefaultToolkit(); 
+				var scrsize = jkit.getScreenSize(); 
+				cw = scrsize.width; 
+				ch = scrsize.height; 
+			} else
+				{
+					cw = w;
+					ch = h
+				} 
+		} 
+
+		else //FOR TRUE IE!!! with clientWidth
+		{	
+			cw=MyDoc.body.clientWidth;
+			ch=MyDoc.body.clientHeight;
+
+			if (Math.round(ViewY)>ch) ch=ch+16;
+			if (Math.round(ViewX)>cw) cw=cw+16;
+			
+		}
+	} else { //for TRUE NN :-) cheak It!!!
+		//alertd("nn"); //NN6 use it
+		
+		cw=MyWindow.innerWidth*95/100;
+		ch=MyWindow.innerHeight*95/100;
+		//alertd("cw"+cw);
+		//alertd(""ch);
+	}
+
+	fw=100*(cw/pw);
+	fh=100*(ch/ph);
+	xzoo=fh;
+	if(fw<fh)
+		xzoo=fw;
+	if(xzoo==zoo)
+		return;
+	pzoo=zoo;
+	zoo=xzoo;
+	ZRefresh();
+}
+function zoomfull(){
+	pzoo=zoo;
+	zoo=100;
+	ZRefresh();
+}
+function zoomprev(){
+	tmp=zoo;
+	zoo=pzoo;
+	pzoo=tmp;
+	ZRefresh();
+}
+//----------------------------------------------------------------------------
+// Buttons of ToolBar
+//----------------------------------------------------------------------------
+BT_TITL = 0
+BT_ZMIN = 1
+BT_ZOUT = 2
+BT_ZFIT = 3
+BT_FULL = 4
+BT_PREV = 5
+BT_CODE = 6
+BT_PAGE = 7
+BT_PMOD = 8
+BT_ZMOD = 9
+BT_SMOD =10
+BT_OBJV =11
+BT_POPP =12 
+BT_PRNT =13
+BT_NEWW =14
+BT_SYSB =15
+//----------------------------------------------------------------------------
+NRM = 0;
+OVR = 1;
+DWN = 2;
+MES = 3;
+//----------------------------------------------------------------------------
+BT_NUMBER = 16;
+//----------------------------------------------------------------------------
+IMRES = new Array()//0..15 images is here
+Present = new Array(1,1,1,0,1, 1,0,0,0,0, 0,0,0,0,1, 1)//{1/0} boolean of visibility
+//----------------------------------------------------------------------------
+function mClick(i){
+	switch(i)
+	{
+		case BT_TITL: return;
+		case BT_ZMIN: zoomin();return;
+		case BT_ZOUT: zoomout();return;
+		case BT_ZFIT: zoomfit();return;
+		case BT_FULL: zoomfull();return;
+		case BT_PREV: zoomprev();return;
+		case BT_CODE: CodeView();return;
+		case BT_PAGE: GotoPage();return;
+		case BT_PMOD: Grosser(window.top);//Grosser();
+						window.top.resizeBy(1, 1);window.resizeBy(-1, -1); //!!!
+					  return;
+		case BT_ZMOD: return;
+		case BT_SMOD: view_source();return;
+		case BT_OBJV: DUMP();return;
+		case BT_SYSB: window.parent.close();void(0);
+					  return;
+		case BT_NEWW: fullScreen2(window.parent.location);
+						//window.parent.frames["xschem"].window.document.images[SCHEM].src = SchemImage.src;
+						return;
+		case BT_PRNT: printit();return;
+		case BT_POPP: alert(":-(");return;
+	}
+}
+//----------------------------------------------------------------------------
+function mOver(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][OVR].src;
+	SetStatus(IMRES[i][MES]);
+}
+//----------------------------------------------------------------------------
+function mOut(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][NRM].src;
+	SetStatus("");
+}
+//----------------------------------------------------------------------------
+function mDown(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][DWN].src;
+	SetStatus(IMRES[i][MES]);
+}
+//----------------------------------------------------------------------------
+function mUp(i){
+	switch(i)
+	{	case BT_TITL:
+		case BT_SYSB: return;
+	}
+	var btn = "btn_"+i;
+	window.document.images[btn].src=IMRES[i][OVR].src;
+}
+//----------------------------------------------------------------------------
+function GetBod(i)
+	{
+	switch(i)
+	{	case BT_TITL: return "bar"
+		case BT_ZMIN: return "zoomin"
+		case BT_ZOUT: return "zoomout"
+		case BT_ZFIT: return "fit"
+		case BT_FULL: return "full"
+		case BT_CODE: return "code"
+		case BT_PREV: return "prev"
+		case BT_PAGE: return "goto"
+		case BT_PMOD: return "panmode"
+		case BT_ZMOD: return "zoommode"
+		case BT_SMOD: return "selectmode"
+		case BT_OBJV: return "tbl"
+		case BT_SYSB: return "frame"
+		case BT_NEWW: return "newwindow"
+		case BT_PRNT: return "print"
+		case BT_POPP: return "pop"
+	}
+	return "blank"
+}
+//----------------------------------------------------------------------------
+function GetFile(i, mode)
+	{
+	var bod = GetBod(i)
+	var end; 
+	switch(mode)
+	{	case NRM: end=".gif";break;
+		case OVR: end=OV;break;
+		case DWN: end=OD;
+	}
+	return IRoot + bod + end; 
+}
+//----------------------------------------------------------------------------
+function GetIMessage(i){
+	switch(i)
+	{
+		case BT_ZMIN: return "Zooms in view"
+		case BT_ZOUT: return "Zooms out view"
+		case BT_ZFIT: return "Zooms to fit"
+		case BT_FULL: return "Displays full page"
+		case BT_CODE: return "View generated code"
+		case BT_PREV: return "Displays previously visible area"
+		case BT_PAGE: return "Go to page"
+		case BT_PMOD: return "Enter panning mode"
+		case BT_ZMOD: return "Enter zoom mode"
+		case BT_SMOD: return "Enter select mode"
+		case BT_OBJV: return "Show Objects Window"
+		case BT_NEWW: return "Open in new window"
+		case BT_SYSB: return "Close newly opened window"
+		case BT_PRNT: return "Print"
+		case BT_POPP: return "Enters an upper hierarchical level"
+	}
+	return ""
+}
+//----------------------------------------------------------------------------
+for(i=0;i<BT_NUMBER;i++){
+	IMRES[i] = new Array(new Image(),new Image(),new Image(),"");
+}
+//----------------------------------------------------------------------------
+for(i=0;i<BT_NUMBER;i++){
+	IMRES[i][NRM].src = GetFile(i,NRM);
+	IMRES[i][OVR].src = GetFile(i,OVR);
+	IMRES[i][DWN].src = GetFile(i,DWN);
+	IMRES[i][MES]     = GetIMessage(i);
+//	IMRES[i][HNT]     = GetIHint(i);
+}
+//----------------------------------------------------------------------------
+function GetToolBar(){
+	var tools;
+	var open = '<table align="left" border="0" cellspacing="0" cellpadding="0" valign="center" align="center"> <tr bgcolor="silver" background="silver" bordercolordark="silver" >';
+	var close = '</tr></table>';
+
+	var std0 = '<td ><img hspace="0" vspace="0" border="0" align="absmiddle" ';
+	var std1= 'width=24 height=22 ';
+	var std2 = '></td>';
+
+	tools = open;
+	for(i=0;i<BT_NUMBER;i++){
+		if(Present[i]){
+			tools+=std0;
+			if(i!=BT_SYSB && i!=BT_TITL)
+				tools+=std1;
+			//tools+='src='+ GetINorm(i) + ' ';
+			tools+='src="'+ IMRES[i][NRM].src + '" ';
+			tools+=	'onClick="mClick('    + i + ')" ';
+			tools+=	'onMouseDown="mDown(' + i + ')" ';
+			tools+=	'onMouseUp="mUp(' + i + ')" ';
+			tools+=	'onMouseOver="mOver(' + i + ')" ';
+			tools+=	'onMouseOut="mOut('   + i + ')" ';	//	tools+='name="btn_' + i +'" '
+			tools+=	'name="btn_' + i +'" ';
+			tools+= 'alt="'+GetIMessage(i)+'" ';
+			tools+=std2;								
+		}
+	}
+	tools += close;
+
+	return tools;
+}
+//----------------------------------------------------------------------------
+var NIL = -1;
+//----------------------------------------------------------------------------
+function InRect(x,y,left,top,right,bottom) {
+	if(x>=left && x<=right && y>=top  && y<=bottom)
+		return 1;
+	return 0;	
+}
+//----------------------------------------------------------------------------
+function GetSender(x,y) {
+	for(i=0;i<FUBSNUMBER;i++) {
+		var left  = FUB[i][0];
+		var top   = FUB[i][1];
+		var right = FUB[i][2];
+		var bottom= FUB[i][3];
+
+	factor = PageX / ViewX;
+
+	xx = x*factor;
+	yy = y*factor;
+
+		if(InRect(xx,yy,left,top,right,bottom))
+			return i;
+	}
+	return NIL;
+}
+//----------------------------------------------------------------------------
+function Mapper(MouseX,MouseY) {
+	var SENDER = GetSender(MouseX,MouseY);
+	if(SENDER != NIL){
+		FUB[SENDER][4]();		
+	}
+}
+//----------------------------------------------------------------------------
+function MapperOver(MouseX,MouseY) {
+	var SENDER = GetSender(MouseX,MouseY);
+	if(SENDER != NIL){
+		FUB[SENDER][5]();
+		SetCursor("hand");
+	}
+	else {
+		SetStatus("");
+		SetCursor("default");
+	}
+	
+}
+//----------------------------------------------------------------------------
+function SetStatus(status){
+	if(window.top.status!=status){
+		window.top.status=status;
+		}
+}
+//----------------------------------------------------------------------------
+function SetCursor(cursor){
+	if(ie){
+		if(MyImage.style.cursor!=cursor)
+			MyImage.style.cursor=cursor;
+	} else {
+		; 
+	}
+}
+//----------------------------------------------------------------------------
+function Grosser(Who) { //in Opera - MDI - some bugs :-( but Ok . IE - nok. NN6 - ok
+	//window.moveTo(0,0);
+//	window.resizeTo(screen.availWidth,screen.availHeight);
+	Who.moveTo(0,0);
+	Who.resizeTo(screen.availWidth,screen.availHeight);
+}
+//----------------------------------------------------------------------------
+function fullScreen2(theURL) {
+	window.open(theURL, '', 'fullscreen=yes,scrollbars=yes,status=yes,resizable=yes,location=yes');
+}
+//----------------------------------------------------------------------------
+function boom(n){
+	if (window.top.moveBy)
+	{
+		for (i = 10; i > 0; i--){
+			for (j = n; j > 0; j--){
+				window.top.moveBy(0,i);
+				window.top.moveBy(i,0);
+				window.top.moveBy(0,-i);
+				window.top.moveBy(-i,0);
+			}//for
+		}//for
+	}//if
+}
+//----------------------------------------------------------------------------
+function view_source(){ //Opera - nok; IE - ok. NN6 - ok.
+MyWindow.location = "view-source:" + MyWindow.location.href;
+} 
+//----------------------------------------------------------------------------
+function printit(){
+	var browser_name = navigator.appName;
+	if (browser_name == "Netscape") {
+    	MyWindow.print() ;
+	} else {
+    	var WebBrowser = '<object id="WebBrowser1" width=0 height=0 classid="clsid:8856F961-340A-11D0-A96B-00C04FD705A2"></object>';
+	    document.body.insertAdjacentHTML('beforeEnd', WebBrowser);
+    	WebBrowser1.ExecWB(6, 2);
+	}
+}
+
+
+
+

Property changes on: common/components/usbhostslave/tags/start/doc/html/struct/fsmtools.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/doc/html/struct/navig.js
===================================================================
--- common/components/usbhostslave/tags/start/doc/html/struct/navig.js	(nonexistent)
+++ common/components/usbhostslave/tags/start/doc/html/struct/navig.js	(revision 264)
@@ -0,0 +1,178 @@
+
+// styles definition
+
+document.writeln ('<style>');
+document.writeln ('body { margin: 0px}');
+document.writeln ('#tabs { margin: 0px; border-width: 0px }');
+document.writeln ('</style>');
+
+// paths
+
+var TreePath = "./" + RootProject + "images/tree/";
+var TabsPath = "./" + RootProject + "images/tab/";
+if (DownTabs == 1)
+ TabsPath = "./" + RootProject + "images/itab/";
+var ExtPath = "./" + RootProject + "images/ext/";
+
+// preloading images
+
+LeftNot = new Image ();
+RightNot = new Image ();
+
+LeftSel = new Image ();
+RightSel = new Image ();
+
+SelNot = new Image ();
+NotSel = new Image ();
+NotNot = new Image ();
+
+TabNot = new Image ();
+TabSel = new Image ();
+
+Project = new Image ();
+VHD = new Image ();
+V = new Image ();
+EDN = new Image ();
+BDE = new Image ();
+AWF = new Image ();
+ASF = new Image ();
+LST = new Image ();
+TXT = new Image ();
+PL = new Image ();
+TCL = new Image ();
+DO = new Image ();
+CPP = new Image ();
+UNDEF = new Image ();
+
+Empty = new Image ();
+
+LeftNot.src = TabsPath + "left_n.bmp";
+RightNot.src = TabsPath + "right_n.bmp";
+
+LeftSel.src = TabsPath + "left_s.bmp";
+RightSel.src = TabsPath + "right_s.bmp";
+
+SelNot.src = TabsPath + "s_n.bmp";
+NotSel.src = TabsPath + "n_s.bmp";
+NotNot.src = TabsPath + "n_n.bmp";
+
+TabNot.src = TabsPath + "tab_n.bmp";
+TabSel.src = TabsPath + "tab_s.bmp";
+
+Project.src = TreePath + "project.bmp";
+
+VHD.src = ExtPath + "vhd.gif";
+V.src = ExtPath + "v.gif";
+EDN.src = ExtPath + "edn.gif";
+BDE.src = ExtPath + "bde.gif";
+AWF.src = ExtPath + "awf.gif";
+ASF.src = ExtPath + "asf.gif";
+LST.src = ExtPath + "lst.gif";
+TXT.src = ExtPath + "txt.gif";
+PL.src = ExtPath + "pl.gif";
+TCL.src = ExtPath + "tcl.gif";
+DO.src = ExtPath + "do.gif";
+CPP.src = ExtPath + "cpp.gif";
+UNDEF.src = ExtPath + "undef.gif";
+
+Empty.src = TabsPath + "empty.gif";
+
+// working with tab
+
+var ID = 0;
+
+function SetTab (Type, Name, URL)
+ {
+  var str;
+  str = '<td id=tab background="' + TabNot.src + '" valign="middle"><nobr>';
+  str += '<a style="text-decoration: none; font-size: 12px" href="' + URL + '" target=' + Target + ' onClick="ChangeButtons(\'' + ID + '\')">';         ChangeButtons
+  str += '&nbsp;<img hspace="0" vspace="0" border="0" align="absmiddle" width="18" height="16" src="' + Type.src + '">&nbsp;';
+  str += '&nbsp;' + Name + '&nbsp;';
+  str += '</a>';
+  str += '</td>';
+  this.document.writeln (str);
+  ++ID;
+ }
+
+// working with limiters
+
+function SetLeft ()
+ {
+  this.document.writeln ('<td><img width="7" height="21" src="' + LeftNot.src + '"></td>');
+ }
+
+function SetRight ()
+ {
+  this.document.writeln ('<td><img width="7" height="21" src="' + RightNot.src + '"></td>');
+ }
+
+function SetBTab ()
+ {
+  this.document.writeln ('<td><img width="7" height="21" src="' + NotNot.src + '"></td>');
+ }
+
+var CurTab = 1;
+
+function ChangeButtons (ID)
+ {
+
+  var off = 1 - DownTabs;
+
+  if (CurTab == ID)
+   return;
+
+  if (CurTab == 0)
+   {
+    this.document.images(off+0).src = LeftNot.src;
+    this.document.images(off+2).src = NotNot.src;
+   }
+  if (CurTab == (ColTabs - 1))
+   {
+    this.document.images(off+ColTabs*2 - 2).src = NotNot.src;
+    this.document.images(off+ColTabs*2).src = RightNot.src;
+   }
+  if (CurTab > 0 && CurTab < (ColTabs - 1))
+   {
+    this.document.images(off+CurTab*2).src = NotNot.src;
+    this.document.images(off+CurTab*2 + 2).src = NotNot.src;
+   }
+  if(ColTabs!=1)
+  this.document.all ('tab', CurTab).background = TabNot.src;
+
+  CurTab = ID;
+
+  if (CurTab == 0)
+   {
+    this.document.images(off+0).src = LeftSel.src;
+    this.document.images(off+2).src = SelNot.src;
+   }
+  if (CurTab == (ColTabs - 1))
+   {
+    this.document.images(off+ColTabs*2 - 2).src = NotSel.src;
+    this.document.images(off+ColTabs*2).src = RightSel.src;
+   }
+  if (CurTab > 0 && CurTab < (ColTabs - 1))
+   {
+    this.document.images(off+CurTab*2).src = NotSel.src;
+    this.document.images(off+CurTab*2 + 2).src = SelNot.src;
+   }
+
+  this.document.all ('tab', CurTab).background = TabSel.src;
+
+ }
+
+// working with tabs
+
+function BeginTabs ()
+ {
+  if (!DownTabs)
+   this.document.writeln ('<img height="4" src="' + Empty.src + '"><br>');
+  this.document.writeln ('<table id=tabs cellspacing="0" cellpadding="0"><tr>');
+ }
+
+function EndTabs ()
+ {
+  document.writeln ('</tr></table>');
+  ChangeButtons (0);
+ }
+

Property changes on: common/components/usbhostslave/tags/start/doc/html/struct/navig.js
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/syn/Altera/README.txt
===================================================================
--- common/components/usbhostslave/tags/start/syn/Altera/README.txt	(nonexistent)
+++ common/components/usbhostslave/tags/start/syn/Altera/README.txt	(revision 264)
@@ -0,0 +1,5 @@
+USBHostSlave has been successfully compiled using Quartus 4.1
+However, you will need to set the path to the include files before you get it to compile.
+Assignments>>EDA Tool Settings>>User Libraries.
+Remove the existing library mapping, and add absolute path to USBHostSlave/rtl/include
+

Property changes on: common/components/usbhostslave/tags/start/syn/Altera/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qpf
===================================================================
--- common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qpf	(nonexistent)
+++ common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qpf	(revision 264)
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+# support information,  device programming or simulation file,  and any other
+# associated  documentation or information  provided by  Altera  or a partner
+# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+# other  use  of such  megafunction  design,  netlist,  support  information,
+# device programming or simulation file,  or any other  related documentation
+# or information  is prohibited  for  any  other purpose,  including, but not
+# limited to  modification,  reverse engineering,  de-compiling, or use  with
+# any other  silicon devices,  unless such use is  explicitly  licensed under
+# a separate agreement with  Altera  or a megafunction partner.  Title to the
+# intellectual property,  including patents,  copyrights,  trademarks,  trade
+# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+# support  information,  device programming or simulation file,  or any other
+# related documentation or information provided by  Altera  or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.1"
+DATE = "05:38:41  October 04, 2004"
+
+
+# Revisions
+
+PROJECT_REVISION = "usbHostSlave"

Property changes on: common/components/usbhostslave/tags/start/syn/Altera/usbHostSlave.qpf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/buffers/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/buffers/RxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/buffers/RxFifoBI.v	(revision 264)
@@ -0,0 +1,154 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+  address, 
+  writeEn, 
+  strobe_i,
+  busClk, 
+  usbClk, 
+  rstSyncToBusClk, 
+  fifoSelect,
+  fifoDataIn,
+  busDataIn, 
+  busDataOut,
+  fifoREn,
+  forceEmptySyncToUsbClk,
+  forceEmptySyncToBusClk,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoREn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoREn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg forceEmptyReg;
+reg forceEmpty;
+reg forceEmptyToggle;
+reg [2:0] forceEmptyToggleSyncToUsbClk;
+
+//sync write
+always @(posedge busClk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+    address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+//detect rising edge of 'forceEmpty', and generate toggle signal
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) begin
+    forceEmptyReg <= 1'b0;
+    forceEmptyToggle <= 1'b0;
+  end
+  else begin
+    if (forceEmpty == 1'b1)
+      forceEmptyReg <= 1'b1;
+    else
+      forceEmptyReg <= 1'b0;
+    if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0)
+      forceEmptyToggle <= ~forceEmptyToggle;
+  end
+end
+assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0;
+
+
+// double sync across clock domains to generate 'forceEmptySyncToUsbClk'
+always @(posedge usbClk) begin
+    forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle};
+end
+assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1];
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo)
+begin
+  case (address)
+      `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00; 
+  endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b0 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoREn <= 1'b1;
+  else
+    fifoREn <= 1'b0;
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/buffers/RxFifoBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/buffers/fifoRTL.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/buffers/fifoRTL.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/buffers/fifoRTL.v	(revision 264)
@@ -0,0 +1,164 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoRTL.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized dual clock domain fifo. 
+////  fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn, 
+  dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty,
+  forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+
+// Two clock domains within this module
+// These ports are within 'wrClk' domain
+input wrClk;
+input rstSyncToWrClk;
+input [FIFO_WIDTH-1:0] dataIn;
+input fifoWEn;
+input forceEmptySyncToWrClk;
+output fifoFull;
+
+// These ports are within 'rdClk' domain
+input rdClk;
+input rstSyncToRdClk;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoREn;
+input forceEmptySyncToRdClk;
+output fifoEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire wrClk;
+wire rdClk;
+wire rstSyncToWrClk;
+wire rstSyncToRdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg  [15:0]numElementsInFifo;
+
+
+// local registers
+reg  [ADDR_WIDTH:0]bufferInIndex; 
+reg  [ADDR_WIDTH:0]bufferInIndexSyncToRdClk;
+reg  [ADDR_WIDTH:0]bufferOutIndex;
+reg  [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk;
+reg  [ADDR_WIDTH-1:0]bufferInIndexToMem;
+reg  [ADDR_WIDTH-1:0]bufferOutIndexToMem;
+reg  [ADDR_WIDTH:0]bufferCnt;
+reg  fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge wrClk)
+begin
+  bufferOutIndexSyncToWrClk <= bufferOutIndex;
+  if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1)
+  begin
+    fifoFull <= 1'b0;
+    bufferInIndex <= 0;
+  end
+    else
+    begin
+      if (fifoWEn == 1'b1) begin
+        bufferInIndex <= bufferInIndex + 1'b1;
+      end 
+      if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
+          (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
+        fifoFull <= 1'b1;
+      else
+        fifoFull <= 1'b0;
+    end
+end
+
+always @(bufferInIndexSyncToRdClk or bufferOutIndex) 
+  bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
+
+always @(posedge rdClk)
+begin
+  numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes
+  bufferInIndexSyncToRdClk <= bufferInIndex;
+  if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1)
+  begin
+    fifoEmpty <= 1'b1;
+    bufferOutIndex <= 0;
+    fifoREnDelayed <= 1'b0;
+  end
+    else
+    begin
+      fifoREnDelayed <= fifoREn;
+      if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        dataOut <= dataFromMem;
+        bufferOutIndex <= bufferOutIndex + 1'b1;
+      end
+      if (bufferInIndexSyncToRdClk == bufferOutIndex) 
+        fifoEmpty <= 1'b1;
+      else
+        fifoEmpty <= 1'b0;
+    end
+end
+
+
+always @(bufferInIndex or bufferOutIndex) begin
+  bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
+  bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
+end
+
+dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_dpMem_dc (
+  .addrIn(bufferInIndexToMem),
+  .addrOut(bufferOutIndexToMem),
+  .wrClk(wrClk),
+  .rdClk(rdClk),
+  .dataIn(dataIn),
+  .writeEn(fifoWEn),
+  .readEn(fifoREn),
+  .dataOut(dataFromMem));
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/buffers/fifoRTL.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/directcontrol.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/directcontrol.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/directcontrol.v	(revision 264)
@@ -0,0 +1,196 @@
+
+// File        : ../RTL/hostController/directcontrol.v
+// Generated   : 11/10/06 05:37:19
+// From        : ../RTL/hostController/directcontrol.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// directControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+module directControl (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, clk, directControlEn, directControlLineState, rst);
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   clk;
+input   directControlEn;
+input   [1:0] directControlLineState;
+input   rst;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    clk;
+wire    directControlEn;
+wire    [1:0] directControlLineState;
+wire    rst;
+
+// BINARY ENCODED state machine: drctCntl
+// State codes definitions:
+`define START_DC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0] CurrState_drctCntl;
+reg [2:0] NextState_drctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// diagram ACTION
+
+//--------------------------------------------------------------------
+// Machine: drctCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (directControlLineState or directControlEn or HCTxPortGnt or HCTxPortRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_drctCntl)
+begin : drctCntl_NextState
+  NextState_drctCntl <= CurrState_drctCntl;
+  // Set default values for outputs and signals
+  next_HCTxPortReq <= HCTxPortReq;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  case (CurrState_drctCntl)
+    `START_DC:
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    `CHK_DRCT_CNTL:
+      if (directControlEn == 1'b1)	
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_drctCntl <= `IDLE_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    `DRCT_CNTL_WAIT_GNT:
+      if (HCTxPortGnt == 1'b1)	
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)	
+      begin
+        NextState_drctCntl <= `CHK_DRCT_CNTL;
+        next_HCTxPortReq <= 1'b0;
+      end
+      else
+        NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
+    end
+    `DRCT_CNTL_WAIT_RDY:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {6'b000000, directControlLineState};
+        next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    `IDLE_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_HCTxPortReq <= 1'b0;
+      NextState_drctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+      if (HCTxPortGnt == 1'b1)	
+        NextState_drctCntl <= `IDLE_WAIT_RDY;
+    `IDLE_WAIT_RDY:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_drctCntl <= `IDLE_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_IDLE;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : drctCntl_CurrentState
+  if (rst)	
+    CurrState_drctCntl <= `START_DC;
+  else
+    CurrState_drctCntl <= NextState_drctCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : drctCntl_RegOutput
+  if (rst)	
+  begin
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/directcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/hctxportarbiter.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/hctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/hctxportarbiter.v	(revision 264)
@@ -0,0 +1,239 @@
+
+// File        : ../RTL/hostController/hctxportarbiter.v
+// Generated   : 11/10/06 05:37:22
+// From        : ../RTL/hostController/hctxportarbiter.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hctxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module HCTxPortArbiter (HCTxPortCntl, HCTxPortData, HCTxPortWEnable, SOFCntlCntl, SOFCntlData, SOFCntlGnt, SOFCntlReq, SOFCntlWEn, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   [7:0] SOFCntlCntl;
+input   [7:0] SOFCntlData;
+input   SOFCntlReq;
+input   SOFCntlWEn;
+input   clk;
+input   [7:0] directCntlCntl;
+input   [7:0] directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0] sendPacketCntl;
+input   [7:0] sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortWEnable;
+output  SOFCntlGnt;
+output  directCntlGnt;
+output  sendPacketGnt;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+reg     HCTxPortWEnable, next_HCTxPortWEnable;
+wire    [7:0] SOFCntlCntl;
+wire    [7:0] SOFCntlData;
+reg     SOFCntlGnt, next_SOFCntlGnt;
+wire    SOFCntlReq;
+wire    SOFCntlWEn;
+wire    clk;
+wire    [7:0] directCntlCntl;
+wire    [7:0] directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+wire    [7:0] sendPacketCntl;
+wire    [7:0] sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+
+// Constants
+`define DIRECT_CTRL_MUX 2'b10
+`define SEND_PACKET_MUX 2'b00
+`define SOF_CTRL_MUX 2'b01
+// diagram signals declarations
+reg  [1:0]muxCntl, next_muxCntl;
+
+// BINARY ENCODED state machine: HCTxArb
+// State codes definitions:
+`define START_HARB 3'b000
+`define WAIT_REQ 3'b001
+`define SEND_SOF 3'b010
+`define SEND_PACKET 3'b011
+`define DIRECT_CONTROL 3'b100
+
+reg [2:0] CurrState_HCTxArb;
+reg [2:0] NextState_HCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// SOFController/directContol/sendPacket mux
+always @(muxCntl or SOFCntlWEn or SOFCntlData or SOFCntlCntl or
+		 		 directCntlWEn or directCntlData or directCntlCntl or
+                  directCntlWEn or directCntlData or directCntlCntl or
+ 		  		 sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+case (muxCntl)
+    `SOF_CTRL_MUX :
+    begin
+        HCTxPortWEnable <= SOFCntlWEn;
+        HCTxPortData <= SOFCntlData;
+        HCTxPortCntl <= SOFCntlCntl;
+    end
+    `DIRECT_CTRL_MUX :
+    begin
+        HCTxPortWEnable <= directCntlWEn;
+        HCTxPortData <= directCntlData;
+        HCTxPortCntl <= directCntlCntl;
+    end
+    `SEND_PACKET_MUX :
+    begin
+        HCTxPortWEnable <= sendPacketWEn;
+        HCTxPortData <= sendPacketData;
+        HCTxPortCntl <= sendPacketCntl;
+    end
+    default :
+    begin
+        HCTxPortWEnable <= 1'b0;
+        HCTxPortData <= 8'h00;
+        HCTxPortCntl <= 8'h00;
+    end
+endcase
+end
+
+//--------------------------------------------------------------------
+// Machine: HCTxArb
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (SOFCntlReq or sendPacketReq or directCntlReq or SOFCntlGnt or muxCntl or sendPacketGnt or directCntlGnt or CurrState_HCTxArb)
+begin : HCTxArb_NextState
+  NextState_HCTxArb <= CurrState_HCTxArb;
+  // Set default values for outputs and signals
+  next_SOFCntlGnt <= SOFCntlGnt;
+  next_muxCntl <= muxCntl;
+  next_sendPacketGnt <= sendPacketGnt;
+  next_directCntlGnt <= directCntlGnt;
+  case (CurrState_HCTxArb)
+    `START_HARB:
+      NextState_HCTxArb <= `WAIT_REQ;
+    `WAIT_REQ:
+      if (SOFCntlReq == 1'b1)	
+      begin
+        NextState_HCTxArb <= `SEND_SOF;
+        next_SOFCntlGnt <= 1'b1;
+        next_muxCntl <= `SOF_CTRL_MUX;
+      end
+      else if (sendPacketReq == 1'b1)	
+      begin
+        NextState_HCTxArb <= `SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxCntl <= `SEND_PACKET_MUX;
+      end
+      else if (directCntlReq == 1'b1)	
+      begin
+        NextState_HCTxArb <= `DIRECT_CONTROL;
+        next_directCntlGnt <= 1'b1;
+        next_muxCntl <= `DIRECT_CTRL_MUX;
+      end
+    `SEND_SOF:
+      if (SOFCntlReq == 1'b0)	
+      begin
+        NextState_HCTxArb <= `WAIT_REQ;
+        next_SOFCntlGnt <= 1'b0;
+      end
+    `SEND_PACKET:
+      if (sendPacketReq == 1'b0)	
+      begin
+        NextState_HCTxArb <= `WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    `DIRECT_CONTROL:
+      if (directCntlReq == 1'b0)	
+      begin
+        NextState_HCTxArb <= `WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : HCTxArb_CurrentState
+  if (rst)	
+    CurrState_HCTxArb <= `START_HARB;
+  else
+    CurrState_HCTxArb <= NextState_HCTxArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : HCTxArb_RegOutput
+  if (rst)	
+  begin
+    muxCntl <= 2'b00;
+    SOFCntlGnt <= 1'b0;
+    sendPacketGnt <= 1'b0;
+    directCntlGnt <= 1'b0;
+  end
+  else 
+  begin
+    muxCntl <= next_muxCntl;
+    SOFCntlGnt <= next_SOFCntlGnt;
+    sendPacketGnt <= next_sendPacketGnt;
+    directCntlGnt <= next_directCntlGnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/hctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/sendpacket.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/sendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/sendpacket.asf	(revision 264)
@@ -0,0 +1,285 @@
+VERSION=1.15
+HEADER
+FILE="sendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="sendPacket"
+FRAMES=ON
+FREEOID=260
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 41
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 43
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 227
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 236
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP_WAIT_GNT\n/2/"
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+I 12 6 0 Builtin Reset | 74872,202290
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: sendPacket"
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "sndPkt"
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP\n/0/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "WAIT_ENABLE\n/1/"
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+W 30 25 0 28 26 BEZIER "Transitions" | 52150,256695 56357,246454 59660,235429 67946,223821
+I 29 25 0 Builtin Exit | 144780,121920
+I 28 25 0 Builtin Entry | 48013,256695
+L 27 26 0 TEXT "State Labels" | 71510,219091 1 0 0 "WAIT_RDY\n/3/"
+S 26 25 16384 ELLIPSE "States" | 71510,218388 6500 6500
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+C 23 22 0 TEXT "Conditions" | 129137,121283 1 0 0 "HCTxPortGnt == 1'b1"
+W 22 6 0 16 227 BEZIER "Transitions" | 115535,117920 120401,115274 154207,112243 162751,111806
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114027,93994 6500 6500
+L 20 21 0 TEXT "State Labels" | 114027,93994 1 0 0 "SEND_PID"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nHCTxPortReq <= 1'b1;"
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+S 47 6 36864 ELLIPSE "States" | 115848,16910 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP\n/5/"
+S 45 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,46294 6500 6500
+L 44 45 0 TEXT "State Labels" | 182202,46294 1 0 0 "DATA0_DATA1"
+S 43 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116148,48718 6500 6500
+L 42 43 0 TEXT "State Labels" | 116148,48718 1 0 0 "SEND_SOF"
+S 41 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 61608,50536 6500 6500
+L 40 41 0 TEXT "State Labels" | 61608,50536 1 0 0 "OUT_IN_SETUP"
+W 39 25 0 33 29 BEZIER "Transitions" | 78151,174526 94720,161687 125355,134759 141924,121920
+A 38 33 4 TEXT "Actions" | 92403,180647 1 0 0 "HCTxPortWEn <= 1'b0;"
+A 37 34 16 TEXT "Actions" | 66378,203896 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= PIDNotPID;\nHCTxPortCntl <= `TX_PACKET_START;"
+C 36 34 0 TEXT "Conditions" | 74012,211530 1 0 0 "HCTxPortRdy == 1'b1"
+W 34 25 0 26 33 BEZIER "Transitions" | 71729,211913 72078,205195 72736,192521 73085,185803
+S 33 25 20480 ELLIPSE "States" | 73797,179351 6500 6500
+L 32 33 0 TEXT "State Labels" | 73797,179351 1 0 0 "FIN\n/4/"
+H 58 43 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,5152 212900,250284
+H 51 41 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 50 6 8193 21 45 BEZIER "Transitions" | 119411,90353 134284,80236 162142,60327 177015,50210
+W 49 6 8194 21 43 BEZIER "Transitions" | 114327,87507 114704,79202 115453,63508 115830,55203
+W 48 6 8195 21 41 BEZIER "Transitions" | 108751,90198 97879,81365 77125,63914 66253,55081
+C 79 48 0 TEXT "Conditions" | 70608,88862 1 0 0 "PID == `OUT || \nPID == `IN || \nPID == `SETUP"
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nHCTxPortReq <= 1'b0;"
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+W 74 6 0 41 47 BEZIER "Transitions" | 66723,46527 78274,40563 99268,27192 110071,19888
+W 73 6 0 45 47 BEZIER "Transitions" | 176597,43004 162177,38021 135904,25306 121888,19311
+W 72 6 0 43 47 BEZIER "Transitions" | 115763,42237 115763,37783 115825,29310 115340,23379
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+L 93 88 0 TEXT "State Labels" | 81976,170168 1 0 0 "WAIT_RDY2\n/7/"
+C 92 90 0 TEXT "Conditions" | 78320,216241 1 0 0 "HCTxPortRdy == 1'b1"
+A 91 90 16 TEXT "Actions" | 45540,205901 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {TxEndP[0], TxAddr[6:0]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+W 90 51 0 85 208 BEZIER "Transitions" | 78120,217817 68387,204329 58654,190839 48921,177351
+S 88 51 45056 ELLIPSE "States" | 81668,170476 6500 6500
+L 86 85 0 TEXT "State Labels" | 77841,225000 1 0 0 "WAIT_RDY1\n/6/"
+S 85 51 40960 ELLIPSE "States" | 77841,224297 6500 6500
+I 84 51 0 Builtin Entry | 48374,241112
+I 83 51 0 Builtin Exit | 161275,73621
+W 82 51 0 84 85 BEZIER "Transitions" | 52254,241112 59748,237410 67242,233708 74736,230006
+C 81 50 0 TEXT "Conditions" | 135398,83918 1 0 0 "PID == `DATA0 || PID == `DATA1"
+C 80 49 0 TEXT "Conditions" | 97108,72364 1 0 0 "PID == `SOF"
+S 94 51 49152 ELLIPSE "States" | 132321,97444 6500 6500
+L 96 94 0 TEXT "State Labels" | 132013,98984 1 0 0 "FIN\n/8/"
+W 97 51 0 88 94 BEZIER "Transitions" | 84875,164825 96194,149040 116971,118326 128290,102541
+C 102 97 0 TEXT "Conditions" | 92020,160276 1 0 0 "HCTxPortRdy == 1'b1"
+A 103 97 16 TEXT "Actions" | 101568,139948 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, TxEndP[3:1]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+A 106 94 4 TEXT "Actions" | 149924,100216 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 107 51 0 94 83 BEZIER "Transitions" | 136592,92546 142367,87926 152913,78241 158688,73621
+S 108 58 53248 ELLIPSE "States" | 147250,59594 6500 6500
+W 109 58 0 111 112 BEZIER "Transitions" | 74001,225148 80276,214907 83479,203781 89697,192173
+I 110 58 0 Builtin Exit | 176204,35771
+I 111 58 0 Builtin Entry | 69864,225148
+S 112 58 57344 ELLIPSE "States" | 92770,186447 6500 6500
+L 113 112 0 TEXT "State Labels" | 92770,187150 1 0 0 "WAIT_RDY3\n/10/"
+S 114 58 61440 ELLIPSE "States" | 96597,132626 6500 6500
+W 116 58 0 112 212 BEZIER "Transitions" | 93049,179967 76928,166181 60805,152395 44684,138609
+A 117 116 16 TEXT "Actions" | 41323,167693 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= frameNum[7:0];\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 118 116 0 TEXT "Conditions" | 57123,179898 1 0 0 "HCTxPortRdy == 1'b1"
+L 119 114 0 TEXT "State Labels" | 96905,132318 1 0 0 "WAIT_RDY4\n/11/"
+W 120 58 0 108 110 BEZIER "Transitions" | 151521,54696 157296,50076 167573,40391 173348,35771
+A 121 108 4 TEXT "Actions" | 164853,62366 1 0 0 "HCTxPortWEn <= 1'b0;\nframeNum <= frameNum + 1'b1;"
+W 122 58 0 114 108 BEZIER "Transitions" | 99804,126975 111123,111190 131900,80476 143219,64691
+A 123 122 16 TEXT "Actions" | 116497,102098 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= {5'b00000, frameNum[10:8]};\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+C 124 122 0 TEXT "Conditions" | 106949,122426 1 0 0 "HCTxPortRdy == 1'b1"
+L 125 108 0 TEXT "State Labels" | 146942,61134 1 0 0 "FIN1\n/9/"
+I 126 65 0 Builtin Entry | 68558,236856
+I 127 65 0 Builtin Exit | 176933,37229
+W 128 65 0 126 145 BEZIER "Transitions" | 73112,236856 77923,244915 98191,234153 107520,226388
+S 136 65 65536 ELLIPSE "States" | 97326,133352 6500 6500
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/12/"
+W 138 65 0 142 221 BEZIER "Transitions" | 93778,181425 88750,173188 83721,164951 78693,156714
+C 139 138 0 TEXT "Conditions" | 93893,178439 1 0 0 "HCTxPortRdy == 1'b1"
+A 140 138 16 TEXT "Actions" | 77442,167531 1 0 0 "fifoReadEn <= 1'b1;"
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "HCTxPortWEn <= 1'b1;	 \nHCTxPortData <= fifoData;\nHCTxPortCntl <= `TX_PACKET_STREAM;"
+S 142 65 69632 ELLIPSE "States" | 93499,187905 6500 6500
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/13/"
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/14/"
+S 145 65 73728 ELLIPSE "States" | 112500,222212 6500 6500
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+S 152 65 77824 ELLIPSE "States" | 63416,66086 6500 6500
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/15/"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "HCTxPortRdy == 1'b1"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nHCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_PACKET_STOP;"
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 158 65 81920 ELLIPSE "States" | 59589,119907 6500 6500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/16/"
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170179,37688 173765,37229
+L 163 164 0 TEXT "Labels" | 107978,225284 1 0 0 "fifoEmpty"
+I 164 0 2 Builtin InPort | 101978,225284 "" ""
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "HCTxPortReq"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "HCTxPortGnt"
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "HCTxPortWEn"
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "HCTxPortRdy"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "HCTxPortData[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "HCTxPortCntl[7:0]"
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+A 192 9 2 TEXT "Actions" | 127618,200894 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= 8'h00;\nHCTxPortWEn <= 1'b0;\nHCTxPortReq <= 1'b0;\nframeNum <= 11'h000;"
+L 198 199 0 TEXT "Labels" | 107972,241240 1 0 0 "TxEndP[3:0]"
+I 199 0 130 Builtin InPort | 101972,241240 "" ""
+L 200 201 0 TEXT "Labels" | 107760,245904 1 0 0 "TxAddr[6:0]"
+I 201 0 130 Builtin InPort | 101760,245904 "" ""
+L 202 203 0 TEXT "Labels" | 108204,236768 1 0 0 "frameNum[10:0]"
+I 203 0 130 Builtin OutPort | 102204,236768 "" ""
+W 206 6 8196 21 47 BEZIER "Transitions" | 107587,94872 93331,94377 65340,95755 56776,92141\
+                                          48213,88528 42471,75064 41184,67490 39897,59917\
+                                          40491,43087 47668,36800 54846,30514 82962,22198\
+                                          91674,19921 100386,17644 105983,17263 109349,16867
+L 207 208 0 TEXT "State Labels" | 49136,170872 1 0 0 "CLR_WEN1\n/17/"
+W 219 65 0 216 145 BEZIER "Transitions" | 169535,125660 177050,126578 189941,130186 195034,132816\
+                                          200128,135446 205472,144130 205681,151728 205890,159327\
+                                          201380,181037 194241,189595 187102,198154 163054,210680\
+                                          152909,214312 142764,217944 127179,220153 118913,221155
+W 218 65 0 136 216 BEZIER "Transitions" | 103645,131833 117756,130581 143219,125185 157330,123933
+A 217 216 4 TEXT "Actions" | 149694,110062 1 0 0 "HCTxPortWEn <= 1'b0;"
+S 216 65 94208 ELLIPSE "States" | 163722,122754 6500 6500
+L 215 216 0 TEXT "State Labels" | 163722,122754 1 0 0 "CLR_WEN\n/19/"
+S 208 51 86016 ELLIPSE "States" | 49136,170872 6500 6500
+W 209 51 0 208 88 BEZIER "Transitions" | 55635,170844 60887,170743 69917,170662 75169,170561
+A 210 208 4 TEXT "Actions" | 32522,149110 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 44590,132116 1 0 0 "CLR_WEN1\n/18/"
+S 212 58 90112 ELLIPSE "States" | 44590,132116 6500 6500
+W 213 58 0 212 114 BEZIER "Transitions" | 51053,131425 61250,131326 79973,131757 90170,131658
+A 214 212 4 TEXT "Actions" | 31918,111920 1 0 0 "HCTxPortWEn <= 1'b0;"
+L 220 221 0 TEXT "State Labels" | 78550,150235 1 0 0 "CLR_REN\n/20/"
+S 221 65 98304 ELLIPSE "States" | 78550,150235 6500 6500
+A 222 221 4 TEXT "Actions" | 87635,159320 1 0 0 "fifoReadEn <= 1'b0;"
+W 224 65 0 221 136 BEZIER "Transitions" | 83283,145781 86048,143806 89994,139951 92759,137976
+H 229 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 227 6 102420 ELLIPSE "Junction" | 165212,109319 3500 3500
+L 228 227 0 TEXT "State Labels" | 165212,109319 1 0 0 "J1"
+I 230 229 0 Builtin Entry | 86360,167640
+I 231 229 0 Builtin Exit | 129540,111760
+W 232 229 0 230 231 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+L 233 234 0 TEXT "Labels" | 162660,245408 1 0 0 "fullSpeedPolarity"
+I 234 0 2 Builtin InPort | 156660,245408 "" ""
+L 235 236 0 TEXT "State Labels" | 198623,87106 1 0 0 "LS_EOP"
+S 236 6 106500 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 198623,87106 6500 6500
+W 237 6 1 227 236 BEZIER "Transitions" | 168384,107842 175000,104995 188420,97278 193251,90764
+W 238 6 2 227 21 BEZIER "Transitions" | 161819,108462 150848,105699 131009,99230 120038,96467
+W 239 6 0 236 47 BEZIER "Transitions" | 199566,80679 201782,68823 204064,53250 203352,44331\
+                                        202640,35412 197280,23183 191376,19540 185472,15898\
+                                        167213,13552 158043,13342 148873,13133 131482,15160\
+                                        122270,15913
+C 240 237 0 TEXT "Conditions" | 144637,101038 1 0 0 "PID == `SOF && fullSpeedPolarity == 1'b0"
+H 241 236 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 248 241 110592 ELLIPSE "States" | 84074,210161 6500 6500
+L 249 248 0 TEXT "State Labels" | 84074,210864 1 0 0 "WAIT_RDY\n/21/"
+I 250 241 0 Builtin Entry | 60577,248468
+I 251 241 0 Builtin Exit | 157344,113693
+W 252 241 0 250 248 BEZIER "Transitions" | 64714,248468 68921,238227 72224,227202 80510,215594
+S 253 241 114688 ELLIPSE "States" | 86361,171124 6500 6500
+L 254 253 0 TEXT "State Labels" | 86361,171124 1 0 0 "FIN\n/22/"
+W 255 241 0 248 253 BEZIER "Transitions" | 84293,203686 84642,196968 85300,184294 85649,177576
+C 256 255 0 TEXT "Conditions" | 86576,203303 1 0 0 "HCTxPortRdy == 1'b1"
+A 257 255 16 TEXT "Actions" | 78942,195669 1 0 0 "HCTxPortWEn <= 1'b1;\nHCTxPortData <= 8'h00;\nHCTxPortCntl <= `TX_LS_KEEP_ALIVE;"
+A 258 253 4 TEXT "Actions" | 104967,172420 1 0 0 "HCTxPortWEn <= 1'b0;"
+W 259 241 0 253 251 BEZIER "Transitions" | 90715,166299 107284,153460 137919,126532 154488,113693
+END

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/sendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/sendpacketarbiter.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/sendpacketarbiter.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/sendpacketarbiter.v	(revision 264)
@@ -0,0 +1,182 @@
+
+// File        : ../RTL/hostController/sendpacketarbiter.v
+// Generated   : 11/10/06 05:37:20
+// From        : ../RTL/hostController/sendpacketarbiter.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketarbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbConstants_h.v"
+
+module sendPacketArbiter (HCTxGnt, HCTxReq, HC_PID, HC_SP_WEn, SOFTxGnt, SOFTxReq, SOF_SP_WEn, clk, rst, sendPacketPID, sendPacketWEnable);
+input   HCTxReq;
+input   [3:0] HC_PID;
+input   HC_SP_WEn;
+input   SOFTxReq;
+input   SOF_SP_WEn;
+input   clk;
+input   rst;
+output  HCTxGnt;
+output  SOFTxGnt;
+output  [3:0] sendPacketPID;
+output  sendPacketWEnable;
+
+reg     HCTxGnt, next_HCTxGnt;
+wire    HCTxReq;
+wire    [3:0] HC_PID;
+wire    HC_SP_WEn;
+reg     SOFTxGnt, next_SOFTxGnt;
+wire    SOFTxReq;
+wire    SOF_SP_WEn;
+wire    clk;
+wire    rst;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+reg     sendPacketWEnable, next_sendPacketWEnable;
+
+// diagram signals declarations
+reg  muxSOFNotHC, next_muxSOFNotHC;
+
+// BINARY ENCODED state machine: sendPktArb
+// State codes definitions:
+`define HC_ACT 2'b00
+`define SOF_ACT 2'b01
+`define SARB_WAIT_REQ 2'b10
+`define START_SARB 2'b11
+
+reg [1:0] CurrState_sendPktArb;
+reg [1:0] NextState_sendPktArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// hostController/SOFTransmit mux
+always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
+begin
+    if (muxSOFNotHC  == 1'b1)
+    begin
+        sendPacketWEnable <= SOF_SP_WEn;
+        sendPacketPID <= `SOF;
+    end
+    else
+    begin
+        sendPacketWEnable <= HC_SP_WEn;
+        sendPacketPID <= HC_PID;
+    end
+end
+
+//--------------------------------------------------------------------
+// Machine: sendPktArb
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
+begin : sendPktArb_NextState
+  NextState_sendPktArb <= CurrState_sendPktArb;
+  // Set default values for outputs and signals
+  next_HCTxGnt <= HCTxGnt;
+  next_SOFTxGnt <= SOFTxGnt;
+  next_muxSOFNotHC <= muxSOFNotHC;
+  case (CurrState_sendPktArb)
+    `HC_ACT:
+      if (HCTxReq == 1'b0)	
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_HCTxGnt <= 1'b0;
+      end
+    `SOF_ACT:
+      if (SOFTxReq == 1'b0)	
+      begin
+        NextState_sendPktArb <= `SARB_WAIT_REQ;
+        next_SOFTxGnt <= 1'b0;
+      end
+    `SARB_WAIT_REQ:
+      if (SOFTxReq == 1'b1)	
+      begin
+        NextState_sendPktArb <= `SOF_ACT;
+        next_SOFTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b1;
+      end
+      else if (HCTxReq == 1'b1)	
+      begin
+        NextState_sendPktArb <= `HC_ACT;
+        next_HCTxGnt <= 1'b1;
+        next_muxSOFNotHC <= 1'b0;
+      end
+    `START_SARB:
+      NextState_sendPktArb <= `SARB_WAIT_REQ;
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktArb_CurrentState
+  if (rst)	
+    CurrState_sendPktArb <= `START_SARB;
+  else
+    CurrState_sendPktArb <= NextState_sendPktArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktArb_RegOutput
+  if (rst)	
+  begin
+    muxSOFNotHC <= 1'b0;
+    SOFTxGnt <= 1'b0;
+    HCTxGnt <= 1'b0;
+  end
+  else 
+  begin
+    muxSOFNotHC <= next_muxSOFNotHC;
+    SOFTxGnt <= next_SOFTxGnt;
+    HCTxGnt <= next_HCTxGnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/sendpacketarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/sofcontroller.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/sofcontroller.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/sofcontroller.v	(revision 264)
@@ -0,0 +1,181 @@
+
+// File        : ../RTL/hostController/sofcontroller.v
+// Generated   : 11/10/06 05:37:21
+// From        : ../RTL/hostController/sofcontroller.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sofcontroller
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+module SOFController (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, SOFEnable, SOFTimerClr, SOFTimer, clk, rst);
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   SOFEnable;
+input   SOFTimerClr;
+input   clk;
+input   rst;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  [15:0] SOFTimer;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    SOFEnable;
+wire    SOFTimerClr;
+reg     [15:0] SOFTimer, next_SOFTimer;
+wire    clk;
+wire    rst;
+
+// BINARY ENCODED state machine: sofCntl
+// State codes definitions:
+`define START_SC 3'b000
+`define WAIT_SOF_EN 3'b001
+`define WAIT_SEND_RESUME 3'b010
+`define INC_TIMER 3'b011
+`define SC_WAIT_GNT 3'b100
+`define CLR_WEN 3'b101
+
+reg [2:0] CurrState_sofCntl;
+reg [2:0] NextState_sofCntl;
+
+
+//--------------------------------------------------------------------
+// Machine: sofCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (SOFTimerClr or SOFTimer or SOFEnable or HCTxPortRdy or HCTxPortGnt or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_sofCntl)
+begin : sofCntl_NextState
+  NextState_sofCntl <= CurrState_sofCntl;
+  // Set default values for outputs and signals
+  next_HCTxPortReq <= HCTxPortReq;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_SOFTimer <= SOFTimer;
+  case (CurrState_sofCntl)
+    `START_SC:
+      NextState_sofCntl <= `WAIT_SOF_EN;
+    `WAIT_SOF_EN:
+      if (SOFEnable == 1'b1)	
+      begin
+        NextState_sofCntl <= `SC_WAIT_GNT;
+        next_HCTxPortReq <= 1'b1;
+      end
+    `WAIT_SEND_RESUME:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_sofCntl <= `CLR_WEN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_RESUME_START;
+      end
+    `INC_TIMER:
+    begin
+      next_HCTxPortReq <= 1'b0;
+      if (SOFTimerClr == 1'b1)
+        next_SOFTimer <= 16'h0000;
+      else
+        next_SOFTimer <= SOFTimer + 1'b1;
+      if (SOFEnable == 1'b0)	
+      begin
+        NextState_sofCntl <= `WAIT_SOF_EN;
+        next_SOFTimer <= 16'h0000;
+      end
+    end
+    `SC_WAIT_GNT:
+      if (HCTxPortGnt == 1'b1)	
+        NextState_sofCntl <= `WAIT_SEND_RESUME;
+    `CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sofCntl <= `INC_TIMER;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sofCntl_CurrentState
+  if (rst)	
+    CurrState_sofCntl <= `START_SC;
+  else
+    CurrState_sofCntl <= NextState_sofCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sofCntl_RegOutput
+  if (rst)	
+  begin
+    SOFTimer <= 16'h0000;
+    HCTxPortCntl <= 8'h00;
+    HCTxPortData <= 8'h00;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SOFTimer <= next_SOFTimer;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortReq <= next_HCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/sofcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/usbHostControl.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/usbHostControl.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/usbHostControl.v	(revision 264)
@@ -0,0 +1,398 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostControl.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbHostControl(
+  busClk, rstSyncToBusClk,
+  usbClk, rstSyncToUsbClk,
+  //sendPacket
+  TxFifoRE, TxFifoData, TxFifoEmpty,
+  //getPacket
+  RxFifoWE, RxFifoData, RxFifoFull,
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut, SIERxTimeOutEn,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  //HCTxPortArbiter
+  HCTxPortEn, HCTxPortRdy,
+  HCTxPortData, HCTxPortCtrl,
+  //rxStatusMonitor
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFSentIntOut, 
+  connEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  hostControlSelect
+    );
+
+input busClk;
+input rstSyncToBusClk;
+input usbClk;
+input rstSyncToUsbClk;
+//sendPacket
+output TxFifoRE;
+input [7:0] TxFifoData;
+input TxFifoEmpty;
+//getPacket
+output RxFifoWE;
+output [7:0] RxFifoData;
+input RxFifoFull;
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut;
+output SIERxTimeOutEn;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+//HCTxPortArbiter
+output HCTxPortEn;
+input HCTxPortRdy;
+output [7:0] HCTxPortData;
+output [7:0] HCTxPortCtrl;
+//rxStatusMonitor
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [3:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFSentIntOut; 
+output connEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+input hostControlSelect;
+
+wire busClk;
+wire rstSyncToBusClk;
+wire usbClk;
+wire rstSyncToUsbClk;
+wire [10:0] frameNum;
+wire SOFSent;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire [7:0] RxFifoData;
+wire RxFifoFull;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire SIERxTimeOutEn;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire HCTxPortEn;
+wire HCTxPortRdy;
+wire [7:0] HCTxPortData;
+wire [7:0] HCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [3:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFSentIntOut; 
+wire connEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire hostControlSelect;
+
+//internal wiring
+wire SOFTimerClr;
+wire getPacketREn;
+wire getPacketRdy;
+wire HCTxGnt;
+wire HCTxReq;
+wire [3:0] HC_PID;
+wire HC_SP_WEn;
+wire SOFTxGnt;
+wire SOFTxReq;
+wire SOF_SP_WEn;
+wire SOFEnable;
+wire SOFSyncEn;
+wire sendPacketCPReadyIn;
+wire sendPacketCPReadyOut;
+wire [3:0] sendPacketCPPIDIn;
+wire [3:0] sendPacketCPPIDOut;
+wire sendPacketCPWEnIn;
+wire sendPacketCPWEnOut;
+wire [7:0] SOFCntlCntl;
+wire [7:0] SOFCntlData;
+wire SOFCntlGnt;
+wire SOFCntlReq;
+wire SOFCntlWEn;
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire [15:0] SOFTimer;
+wire clrTxReq;
+wire transDone;
+wire transReq;
+wire isoEn;
+wire [1:0] transType;
+wire preAmbleEnable;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [6:0] TxAddr;
+wire [3:0] TxEndP;
+wire [7:0] RxPktStatus;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire connectionEventFromRxStatusMon;
+
+USBHostControlBI u_USBHostControlBI 
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .SOFSentIntOut(SOFSentIntOut), 
+  .connEventIntOut(connEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .TxTransTypeReg(transType), 
+  .TxSOFEnableReg(SOFEnable),
+  .TxAddrReg(TxAddr), 
+  .TxEndPReg(TxEndP), 
+  .frameNumIn(frameNum), 
+  .RxPktStatusIn(RxPktStatus), 
+  .RxPIDIn(RxPID),
+  .connectStateIn(connectStateOut),
+  .SOFSentIn(SOFSent), 
+  .connEventIn(connectionEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .hostControlSelect(hostControlSelect),
+  .clrTransReq(clrTxReq),
+  .preambleEn(preAmbleEnable),
+  .SOFSync(SOFSyncEn),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .transReq(transReq),
+  .isoEn(isoEn),
+  .SOFTimer(SOFTimer)
+  );
+
+
+hostcontroller u_hostController
+  (.RXStatus(RxPktStatus), 
+  .clearTXReq(clrTxReq),
+  .clk(usbClk),
+  .getPacketREn(getPacketREn),
+  .getPacketRdy(getPacketRdy),
+  .rst(rstSyncToUsbClk),
+  .sendPacketArbiterGnt(HCTxGnt),
+  .sendPacketArbiterReq(HCTxReq),
+  .sendPacketPID(HC_PID),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(HC_SP_WEn),
+  .transDone(transDone),
+  .transReq(transReq),
+  .transType(transType),
+  .isoEn(isoEn) );
+
+SOFController u_SOFController
+  (.HCTxPortCntl(SOFCntlCntl),
+  .HCTxPortData(SOFCntlData),
+  .HCTxPortGnt(SOFCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(SOFCntlReq),
+  .HCTxPortWEn(SOFCntlWEn),
+  .SOFEnable(SOFEnable),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk) ); 
+
+SOFTransmit u_SOFTransmit
+  (.SOFEnable(SOFEnable),
+  .SOFSent(SOFSent),
+  .SOFSyncEn(SOFSyncEn),
+  .SOFTimerClr(SOFTimerClr),
+  .SOFTimer(SOFTimer),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk),
+  .sendPacketArbiterGnt(SOFTxGnt),
+  .sendPacketArbiterReq(SOFTxReq),
+  .sendPacketRdy(sendPacketCPReadyOut),
+  .sendPacketWEn(SOF_SP_WEn),
+  .fullSpeedRate(fullSpeedRate) );  
+
+
+sendPacketArbiter u_sendPacketArbiter
+  (.HCTxGnt(HCTxGnt),
+  .HCTxReq(HCTxReq),
+  .HC_PID(HC_PID),
+  .HC_SP_WEn(HC_SP_WEn),
+  .SOFTxGnt(SOFTxGnt),
+  .SOFTxReq(SOFTxReq),
+  .SOF_SP_WEn(SOF_SP_WEn),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk),
+  .sendPacketPID(sendPacketCPPIDIn),
+  .sendPacketWEnable(sendPacketCPWEnIn) );    
+
+sendPacketCheckPreamble u_sendPacketCheckPreamble
+  (.sendPacketCPPID(sendPacketCPPIDIn),
+  .clk(usbClk),
+  .preAmbleEnable(preAmbleEnable),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCPReady(sendPacketCPReadyOut),
+  .sendPacketCPWEn(sendPacketCPWEnIn),
+  .sendPacketPID(sendPacketCPPIDOut),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut) );
+
+sendPacket u_sendPacket
+  (.HCTxPortCntl(sendPacketCntl),
+  .HCTxPortData(sendPacketData),
+  .HCTxPortGnt(sendPacketGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(sendPacketReq),
+  .HCTxPortWEn(sendPacketWEn),
+  .PID(sendPacketCPPIDOut),
+  .TxAddr(TxAddr),
+  .TxEndP(TxEndP),
+  .clk(usbClk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .frameNum(frameNum),
+  .rst(rstSyncToUsbClk),
+  .sendPacketRdy(sendPacketCPReadyIn),
+  .sendPacketWEn(sendPacketCPWEnOut),
+  .fullSpeedPolarity(fullSpeedPol) );
+  
+directControl u_directControl
+  (.HCTxPortCntl(directCntlCntl),
+  .HCTxPortData(directCntlData),
+  .HCTxPortGnt(directCntlGnt),
+  .HCTxPortRdy(HCTxPortRdy),
+  .HCTxPortReq(directCntlReq),
+  .HCTxPortWEn(directCntlWEn),
+  .clk(usbClk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rstSyncToUsbClk) ); 
+
+HCTxPortArbiter u_HCTxPortArbiter
+  (.HCTxPortCntl(HCTxPortCtrl),
+  .HCTxPortData(HCTxPortData),
+  .HCTxPortWEnable(HCTxPortEn),
+  .SOFCntlCntl(SOFCntlCntl),
+  .SOFCntlData(SOFCntlData),
+  .SOFCntlGnt(SOFCntlGnt),
+  .SOFCntlReq(SOFCntlReq),
+  .SOFCntlWEn(SOFCntlWEn),
+  .clk(usbClk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+getPacket u_getPacket
+  (.RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXPktStatus(RxPktStatus),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .SIERxTimeOutEn(SIERxTimeOutEn),
+  .clk(usbClk),
+  .getPacketEn(getPacketREn),
+  .rst(rstSyncToUsbClk) ); 
+
+rxStatusMonitor  u_rxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .connectionEventOut(connectionEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/usbHostControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/getpacket.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/getpacket.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/getpacket.v	(revision 264)
@@ -0,0 +1,375 @@
+
+// File        : ../RTL/hostController/getpacket.v
+// Generated   : 11/10/06 05:37:20
+// From        : ../RTL/hostController/getpacket.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// getpacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, SIERxTimeOutEn, clk, getPacketEn, rst);
+input   [7:0] RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0] RXStreamStatusIn;
+input   SIERxTimeOut;		// Single cycle pulse
+input   clk;
+input   getPacketEn;
+input   rst;
+output  [7:0] RXFifoData;
+output  RXFifoWEn;
+output  RXPacketRdy;
+output  [7:0] RXPktStatus;
+output  [3:0] RxPID;
+output  SIERxTimeOutEn;
+
+wire    [7:0] RXDataIn;
+wire    RXDataValid;
+reg     [7:0] RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXPacketRdy, next_RXPacketRdy;
+reg     [7:0] RXPktStatus;
+wire    [7:0] RXStreamStatusIn;
+reg     [3:0] RxPID, next_RxPID;
+wire    SIERxTimeOut;
+reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
+wire    clk;
+wire    getPacketEn;
+wire    rst;
+
+// diagram signals declarations
+reg  ACKRxed, next_ACKRxed;
+reg  CRCError, next_CRCError;
+reg  NAKRxed, next_NAKRxed;
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXByte, next_RXByte;
+reg  RXOverflow, next_RXOverflow;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+reg  RXTimeOut, next_RXTimeOut;
+reg  bitStuffError, next_bitStuffError;
+reg  dataSequence, next_dataSequence;
+reg  stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: getPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+
+reg [4:0] CurrState_getPkt;
+reg [4:0] NextState_getPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+always @
+(CRCError or bitStuffError or
+  RXOverflow or RXTimeOut or
+  NAKRxed or stallRxed or
+  ACKRxed or dataSequence)
+begin
+    RXPktStatus <= {
+    dataSequence, ACKRxed,
+    stallRxed, NAKRxed,
+    RXTimeOut, RXOverflow,
+    bitStuffError, CRCError};
+end
+
+//--------------------------------------------------------------------
+// Machine: getPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)
+begin : getPkt_NextState
+  NextState_getPkt <= CurrState_getPkt;
+  // Set default values for outputs and signals
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RXOverflow <= RXOverflow;
+  next_RXTimeOut <= RXTimeOut;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_SIERxTimeOutEn <= SIERxTimeOutEn;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RxPID <= RxPID;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXByteOldest <= RXByteOldest;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  case (CurrState_getPkt)
+    `START_GP:
+      NextState_getPkt <= `WAIT_EN;
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b1;
+      if (SIERxTimeOut == 1'b1)	
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+      else if (RXDataValid == 1'b1)	
+      begin
+        NextState_getPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `CHK_PKT_START:
+      if (RXStreamStatus == `RX_PACKET_START)	
+      begin
+        NextState_getPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b0;
+      if (getPacketEn == 1'b1)	
+        NextState_getPkt <= `WAIT_PKT;
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_getPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+      if (RXByte[1:0] == `HANDSHAKE)	
+        NextState_getPkt <= `PROC_PKT_HS;
+      else if (RXByte[1:0] == `DATA)	
+        NextState_getPkt <= `PROC_PKT_DATA_W_D1;
+      else
+        NextState_getPkt <= `PKT_RDY;
+    `PROC_PKT_HS:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_getPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
+        next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    `PROC_PKT_DATA_W_D1:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    `PROC_PKT_DATA_CHK_D1:
+      if (RXStreamStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+    `PROC_PKT_DATA_W_D2:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_getPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+      if (RXStreamStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+    `PROC_PKT_DATA_W_D3:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    `PROC_PKT_DATA_CHK_D3:
+      if (RXStreamStatus == `RX_PACKET_STREAM)	
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      else
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+      if (RXFifoFull == 1'b1)	
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))	
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (RXDataValid == 1'b1)	
+      begin
+        NextState_getPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+      NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : getPkt_CurrentState
+  if (rst)	
+    CurrState_getPkt <= `START_GP;
+  else
+    CurrState_getPkt <= NextState_getPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : getPkt_RegOutput
+  if (rst)	
+  begin
+    RXByteOld <= 8'h00;
+    RXByteOldest <= 8'h00;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RXOverflow <= 1'b0;
+    RXTimeOut <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    RxPID <= 4'h0;
+    SIERxTimeOutEn <= 1'b0;
+  end
+  else 
+  begin
+    RXByteOld <= next_RXByteOld;
+    RXByteOldest <= next_RXByteOldest;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RXOverflow <= next_RXOverflow;
+    RXTimeOut <= next_RXTimeOut;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXPacketRdy <= next_RXPacketRdy;
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    RxPID <= next_RxPID;
+    SIERxTimeOutEn <= next_SIERxTimeOutEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/getpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/hostcontroller.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/hostcontroller.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/hostcontroller.v	(revision 264)
@@ -0,0 +1,386 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostControl_h.v"
+`include "usbConstants_h.v"
+
+
+module hostcontroller (RXStatus, clearTXReq, clk, getPacketREn, getPacketRdy, isoEn, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketPID, sendPacketRdy, sendPacketWEn, transDone, transReq, transType);
+input   [7:0] RXStatus;
+input   clk;
+input   getPacketRdy;
+input   isoEn;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+input   transReq;
+input   [1:0] transType;
+output  clearTXReq;
+output  getPacketREn;
+output  sendPacketArbiterReq;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+output  transDone;
+
+wire    [7:0] RXStatus;
+reg     clearTXReq, next_clearTXReq;
+wire    clk;
+reg     getPacketREn, next_getPacketREn;
+wire    getPacketRdy;
+wire    isoEn;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     transDone, next_transDone;
+wire    transReq;
+wire    [1:0] transType;
+
+// diagram signals declarations
+reg  [3:0]delCnt, next_delCnt;
+
+// BINARY ENCODED state machine: hstCntrl
+// State codes definitions:
+`define START_HC 6'b000000
+`define TX_REQ 6'b000001
+`define CHK_TYPE 6'b000010
+`define FLAG 6'b000011
+`define IN_WAIT_DATA_RXED 6'b000100
+`define IN_CHK_FOR_ERROR 6'b000101
+`define IN_CLR_SP_WEN2 6'b000110
+`define SETUP_CLR_SP_WEN1 6'b000111
+`define SETUP_CLR_SP_WEN2 6'b001000
+`define FIN 6'b001001
+`define WAIT_GNT 6'b001010
+`define SETUP_WAIT_PKT_RXED 6'b001011
+`define IN_WAIT_IN_SENT 6'b001100
+`define OUT0_WAIT_RX_DATA 6'b001101
+`define OUT0_WAIT_DATA0_SENT 6'b001110
+`define OUT0_WAIT_OUT_SENT 6'b001111
+`define SETUP_HC_WAIT_RDY 6'b010000
+`define IN_WAIT_SP_RDY1 6'b010001
+`define IN_WAIT_SP_RDY2 6'b010010
+`define OUT0_WAIT_SP_RDY1 6'b010011
+`define SETUP_WAIT_SETUP_SENT 6'b010100
+`define SETUP_WAIT_DATA_SENT 6'b010101
+`define IN_CLR_SP_WEN1 6'b010110
+`define IN_WAIT_ACK_SENT 6'b010111
+`define OUT0_CLR_WEN1 6'b011000
+`define OUT0_CLR_WEN2 6'b011001
+`define OUT1_WAIT_RX_DATA 6'b011010
+`define OUT1_WAIT_OUT_SENT 6'b011011
+`define OUT1_WAIT_DATA1_SENT 6'b011100
+`define OUT1_WAIT_SP_RDY1 6'b011101
+`define OUT1_CLR_WEN1 6'b011110
+`define OUT1_CLR_WEN2 6'b011111
+`define OUT0_CHK_ISO 6'b100000
+
+reg [5:0] CurrState_hstCntrl;
+reg [5:0] NextState_hstCntrl;
+
+
+//--------------------------------------------------------------------
+// Machine: hstCntrl
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (delCnt or transReq or transType or sendPacketArbiterGnt or getPacketRdy or sendPacketRdy or isoEn or RXStatus or sendPacketArbiterReq or transDone or clearTXReq or sendPacketWEn or getPacketREn or sendPacketPID or CurrState_hstCntrl)
+begin : hstCntrl_NextState
+  NextState_hstCntrl <= CurrState_hstCntrl;
+  // Set default values for outputs and signals
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_transDone <= transDone;
+  next_clearTXReq <= clearTXReq;
+  next_delCnt <= delCnt;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_getPacketREn <= getPacketREn;
+  next_sendPacketPID <= sendPacketPID;
+  case (CurrState_hstCntrl) // synopsys parallel_case full_case
+    `START_HC:
+      NextState_hstCntrl <= `TX_REQ;
+    `TX_REQ:
+      if (transReq == 1'b1)	
+      begin
+        NextState_hstCntrl <= `WAIT_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    `CHK_TYPE:
+      if (transType == `IN_TRANS)	
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY1;
+      else if (transType == `OUTDATA0_TRANS)	
+        NextState_hstCntrl <= `OUT0_WAIT_SP_RDY1;
+      else if (transType == `OUTDATA1_TRANS)	
+        NextState_hstCntrl <= `OUT1_WAIT_SP_RDY1;
+      else if (transType == `SETUP_TRANS)	
+        NextState_hstCntrl <= `SETUP_HC_WAIT_RDY;
+    `FLAG:
+    begin
+      next_transDone <= 1'b1;
+      next_clearTXReq <= 1'b1;
+      next_sendPacketArbiterReq <= 1'b0;
+      next_delCnt <= 4'h0;
+      NextState_hstCntrl <= `FIN;
+    end
+    `FIN:
+    begin
+      next_clearTXReq <= 1'b0;
+      next_transDone <= 1'b0;
+      next_delCnt <= delCnt + 1'b1;
+      //now wait for 'transReq' to clear
+      if (delCnt == 4'hf)	
+        NextState_hstCntrl <= `TX_REQ;
+    end
+    `WAIT_GNT:
+      if (sendPacketArbiterGnt == 1'b1)	
+        NextState_hstCntrl <= `CHK_TYPE;
+    `SETUP_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_SETUP_SENT;
+    end
+    `SETUP_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `SETUP_WAIT_DATA_SENT;
+    end
+    `SETUP_WAIT_PKT_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)	
+        NextState_hstCntrl <= `FLAG;
+    end
+    `SETUP_HC_WAIT_RDY:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `SETUP;
+      end
+    `SETUP_WAIT_SETUP_SENT:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `SETUP_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    `SETUP_WAIT_DATA_SENT:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `SETUP_WAIT_PKT_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    `IN_WAIT_DATA_RXED:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)	
+        NextState_hstCntrl <= `IN_CHK_FOR_ERROR;
+    end
+    `IN_CHK_FOR_ERROR:
+      if (isoEn == 1'b1)	
+        NextState_hstCntrl <= `FLAG;
+      else if (RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&
+        RXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&
+        RXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0)	
+        NextState_hstCntrl <= `IN_WAIT_SP_RDY2;
+      else
+        NextState_hstCntrl <= `FLAG;
+    `IN_CLR_SP_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_ACK_SENT;
+    end
+    `IN_WAIT_IN_SENT:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `IN_WAIT_DATA_RXED;
+        next_getPacketREn <= 1'b1;
+      end
+    `IN_WAIT_SP_RDY1:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `IN;
+      end
+    `IN_WAIT_SP_RDY2:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `IN_CLR_SP_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    `IN_CLR_SP_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `IN_WAIT_IN_SENT;
+    end
+    `IN_WAIT_ACK_SENT:
+      if (sendPacketRdy == 1'b1)	
+        NextState_hstCntrl <= `FLAG;
+    `OUT0_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)	
+        NextState_hstCntrl <= `FLAG;
+    end
+    `OUT0_WAIT_DATA0_SENT:
+      if (sendPacketRdy == 1'b1)	
+        NextState_hstCntrl <= `OUT0_CHK_ISO;
+    `OUT0_WAIT_OUT_SENT:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+    `OUT0_WAIT_SP_RDY1:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `OUT0_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    `OUT0_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_OUT_SENT;
+    end
+    `OUT0_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT0_WAIT_DATA0_SENT;
+    end
+    `OUT0_CHK_ISO:
+      if (isoEn == 1'b0)	
+      begin
+        NextState_hstCntrl <= `OUT0_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+      else
+        NextState_hstCntrl <= `FLAG;
+    `OUT1_WAIT_RX_DATA:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)	
+        NextState_hstCntrl <= `FLAG;
+    end
+    `OUT1_WAIT_OUT_SENT:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN2;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    `OUT1_WAIT_DATA1_SENT:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `OUT1_WAIT_RX_DATA;
+        next_getPacketREn <= 1'b1;
+      end
+    `OUT1_WAIT_SP_RDY1:
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_hstCntrl <= `OUT1_CLR_WEN1;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `OUT;
+      end
+    `OUT1_CLR_WEN1:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_OUT_SENT;
+    end
+    `OUT1_CLR_WEN2:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_hstCntrl <= `OUT1_WAIT_DATA1_SENT;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : hstCntrl_CurrentState
+  if (rst)	
+    CurrState_hstCntrl <= `START_HC;
+  else
+    CurrState_hstCntrl <= NextState_hstCntrl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : hstCntrl_RegOutput
+  if (rst)	
+  begin
+    delCnt <= 4'h0;
+    transDone <= 1'b0;
+    clearTXReq <= 1'b0;
+    getPacketREn <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+  end
+  else 
+  begin
+    delCnt <= next_delCnt;
+    transDone <= next_transDone;
+    clearTXReq <= next_clearTXReq;
+    getPacketREn <= next_getPacketREn;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/hostcontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/sendpacketarbiter.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/sendpacketarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/sendpacketarbiter.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketarbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="sendPacketArbiter"
+FRAMES=ON
+FREEOID=98
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketarbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
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+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
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+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 0 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "HC_ACT\n/0/"
+S 13 6 4096 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "SOF_ACT\n/1/"
+S 11 6 8192 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "SARB_WAIT_REQ\n/2/"
+S 9 6 12288 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_SARB\n/3/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "sendPktArb"
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+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "HCTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b0;"
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+C 29 24 0 TEXT "Conditions" | 88369,77278 1 0 0 "SOFTxReq == 1'b1"
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+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 114611,125692 123896,121919
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 134973,143961 1 0 0 "SOFTxGnt <= 1'b0;\nHCTxGnt <= 1'b0; \nmuxSOFNotHC <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "SOFTxGnt <= 1'b1;\nmuxSOFNotHC <= 1'b1;"
+L 40 41 0 TEXT "Labels" | 42274,157869 1 0 0 "HCTxGnt"
+I 41 0 2 Builtin OutPort | 36274,157869 "" ""
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+I 43 0 2 Builtin OutPort | 162738,158202 "" ""
+L 44 45 0 TEXT "Labels" | 168661,153684 1 0 0 "sendPacketPID[3:0]"
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+I 47 0 2 Builtin OutPort | 89651,157673 "" ""
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+I 49 0 2 Builtin InPort | 92038,153080 "" ""
+L 50 51 0 TEXT "Labels" | 44527,153081 1 0 0 "HCTxReq"
+I 51 0 2 Builtin InPort | 38527,153081 "" ""
+L 52 53 0 TEXT "Labels" | 44410,162874 1 0 0 "HC_PID[3:0]"
+I 53 0 130 Builtin InPort | 38410,162874 "" ""
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
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+                                      200193,83454 202194,93721 199799,97969 197405,102218\
+                                      189371,107780 182843,108050 176316,108321 158239,103840\
+                                      151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 184576,32757 1 0 0 "HCTxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 30647,247164 1 0 0 "// hostController/SOFTransmit mux\nalways @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)  \nbegin\n  if (muxSOFNotHC  == 1'b1)  \n  begin\n    sendPacketWEnable <= SOF_SP_WEn;\n    sendPacketPID <= `SOF;\n  end\n  else\n  begin\n    sendPacketWEnable <= HC_SP_WEn;\n    sendPacketPID <= HC_PID;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 58419,21436 1 0 0 "SOFTxReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "SOFTxGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+                                      70311,70629 71874,86691 76817,93064 81761,99437\
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+                                      123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "HCTxGnt <= 1'b0;"
+I 85 0 2 Builtin InPort | 38222,167883 "" ""
+L 86 85 0 TEXT "Labels" | 44222,167883 1 0 0 "HC_SP_WEn"
+I 89 0 2 Builtin InPort | 92234,162554 "" ""
+L 90 89 0 TEXT "Labels" | 98234,162554 1 0 0 "SOF_SP_WEn"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSOFNotHC"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+END

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/sendpacketarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/sofcontroller.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/sofcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/sofcontroller.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="sofcontroller.asf"
+FID=407b9607
+LANGUAGE=VERILOG
+ENTITY="SOFController"
+FRAMES=ON
+FREEOID=65
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sofcontroller\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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Property changes on: common/components/usbhostslave/trunk/RTL/hostController/sofcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/speedCtrlMux.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/speedCtrlMux.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/speedCtrlMux.v	(revision 264)
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// speedCtrlMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
+input   directCtrlRate;
+input   directCtrlPol;
+input   sendPacketRate;
+input   sendPacketPol;
+input   sendPacketSel;
+output  fullSpeedRate;
+output  fullSpeedPol;
+
+wire   directCtrlRate;
+wire   directCtrlPol;
+wire   sendPacketRate;
+wire   sendPacketPol;
+wire   sendPacketSel;
+reg   fullSpeedRate;
+reg   fullSpeedPol;
+
+
+always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
+begin
+  if (sendPacketSel == 1'b1) 
+  begin
+  fullSpeedRate <= sendPacketRate;
+  fullSpeedPol <= sendPacketPol;
+  end
+  else
+  begin
+  fullSpeedRate <= directCtrlRate;
+  fullSpeedPol <= directCtrlPol;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/speedCtrlMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/getpacket.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/getpacket.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/getpacket.asf	(revision 264)
@@ -0,0 +1,287 @@
+VERSION=1.21
+HEADER
+FILE="getpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="getPacket"
+FREEOID=261
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// getpacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,No Title"
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+END
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+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 109 72 8194 100 97 BEZIER "Transitions" | 75612,157154 66950,155917 49612,152612 44747,149322\
+                                            39882,146032 37743,135343 38221,127384 38700,119425\
+                                            42750,98275 45281,87925 47812,77575 53888,57325\
+                                            56840,51109 59793,44894 65013,39901 67881,37595
+S 110 72 36864 ELLIPSE "States" | 88335,98360 6500 6500
+L 111 110 0 TEXT "State Labels" | 88335,98360 1 0 0 "CHK_D3\n/8/"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 123 120 0 Builtin Entry | 33260,254940
+I 124 120 0 Builtin Exit | 117012,100084
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+C 133 131 0 TEXT "Conditions" | 102150,147411 1 0 0 "RXDataValid == 1'b1"
+A 135 131 16 TEXT "Actions" | 89016,140748 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+W 143 120 8193 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 145 120 8194 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+W 154 120 8193 245 257 BEZIER "Transitions" | 96734,122505 60508,122661 51147,137892 46430,164500
+C 156 154 0 TEXT "Conditions" | 30965,119453 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177616,25344 184028,27160
+I 169 6 0 Builtin Reset | 40672,195051
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,195051 50149,193519 60549,191261 70258,188917
+A 173 40 4 TEXT "Actions" | 128094,33024 1 0 0 "RXPacketRdy <= 1'b1;"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176799,72082 177196,72140
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+L 178 179 0 TEXT "Labels" | 126132,235196 1 0 0 "getPacketEn"
+I 179 0 2 Builtin InPort | 120132,235196 "" ""
+L 180 181 0 TEXT "Labels" | 123932,239896 1 0 0 "RXPacketRdy"
+I 181 0 2 Builtin OutPort | 117932,239896 "" ""
+L 182 183 0 TEXT "Labels" | 120228,217946 1 0 0 "RXDataValid"
+I 183 0 2 Builtin InPort | 114228,217946 "" ""
+L 184 185 0 TEXT "Labels" | 146253,252499 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 140253,252499 "" ""
+L 186 187 0 TEXT "Labels" | 146242,247212 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,247212 "" ""
+C 188 170 0 TEXT "Conditions" | 56486,189866 1 0 0 "rst"
+L 189 190 0 TEXT "Labels" | 120408,208554 1 0 0 "RXStreamStatusIn[7:0]"
+I 190 0 130 Builtin InPort | 114408,208554 "" ""
+I 191 0 130 Builtin InPort | 114421,213294 "" ""
+L 192 191 0 TEXT "Labels" | 120421,213294 1 0 0 "RXDataIn[7:0]"
+L 193 194 0 TEXT "Labels" | 85500,224348 1 0 0 "SIERxTimeOut"
+I 194 0 2 Builtin InPort | 79500,224348 "" ""
+K 195 194 0 TEXT "Comments" | 107584,224332 1 0 0 "Single cycle pulse"
+L 196 197 0 TEXT "Labels" | 22204,208708 1 0 0 "RXByte[7:0]"
+I 197 0 130 Builtin Signal | 19204,208708 "" ""
+L 198 199 0 TEXT "Labels" | 22068,231640 1 0 0 "RXOverflow"
+I 199 0 2 Builtin Signal | 19068,231640 "" ""
+L 200 201 0 TEXT "Labels" | 22380,226836 1 0 0 "NAKRxed"
+I 201 0 2 Builtin Signal | 19380,226836 "" ""
+L 202 203 0 TEXT "Labels" | 22840,218056 1 0 0 "stallRxed"
+I 203 0 2 Builtin Signal | 19840,218056 "" ""
+L 204 205 0 TEXT "Labels" | 22880,221704 1 0 0 "ACKRxed"
+I 205 0 2 Builtin Signal | 19416,222168 "" ""
+L 206 207 0 TEXT "Labels" | 83404,214212 1 0 0 "RXPktStatus[7:0]"
+I 207 0 128 Builtin OutPort | 77404,214212 "" ""
+L 208 209 0 TEXT "Labels" | 22024,236540 1 0 0 "RXTimeOut"
+I 209 0 2 Builtin Signal | 19024,236540 "" ""
+L 210 211 0 TEXT "Labels" | 21792,241180 1 0 0 "CRCError"
+I 211 0 2 Builtin Signal | 18792,241180 "" ""
+L 212 213 0 TEXT "Labels" | 22024,245588 1 0 0 "bitStuffError"
+I 213 0 2 Builtin Signal | 19024,245588 "" ""
+L 214 215 0 TEXT "Labels" | 22024,250228 1 0 0 "dataSequence"
+I 215 0 2 Builtin Signal | 19024,250228 "" ""
+I 216 0 130 Builtin Signal | 19488,213484 "" ""
+L 217 216 0 TEXT "Labels" | 22488,213484 1 0 0 "RXStreamStatus[7:0]"
+A 219 9 2 TEXT "Actions" | 18096,180744 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;\nSIERxTimeOutEn <= 1'b0;"
+A 220 11 4 TEXT "Actions" | 125976,168296 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nSIERxTimeOutEn <= 1'b1;"
+L 221 222 0 TEXT "Labels" | 55956,247152 1 0 0 "RXByteOld[7:0]"
+I 222 0 130 Builtin Signal | 52956,247152 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136204,55740 129157,46692 116484,29855 109437,20807
+I 238 0 130 Builtin OutPort | 77500,209104 "" ""
+L 237 238 0 TEXT "Labels" | 83500,209104 1 0 0 "RxPID[3:0]"
+A 236 34 16 TEXT "Actions" | 139444,78256 1 0 0 "RxPID <= RXByte[3:0];"
+I 225 0 130 Builtin Signal | 52956,252400 "" ""
+L 226 225 0 TEXT "Labels" | 55956,252400 1 0 0 "RXByteOldest[7:0]"
+L 227 228 0 TEXT "Labels" | 85868,240540 1 0 0 "RXFifoFull"
+I 228 0 2 Builtin InPort | 79868,240540 "" ""
+L 229 230 0 TEXT "Labels" | 83548,235552 1 0 0 "RXFifoWEn"
+I 230 0 2 Builtin OutPort | 77548,235552 "" ""
+L 231 232 0 TEXT "Labels" | 83780,229752 1 0 0 "RXFifoData[7:0]"
+I 232 0 130 Builtin OutPort | 77780,229752 "" ""
+A 235 0 1 TEXT "Actions" | 156850,252790 1 0 0 "always @\n(CRCError or bitStuffError or\n RXOverflow or RXTimeOut or\n NAKRxed or stallRxed or\n ACKRxed or dataSequence)\nbegin\n  RXPktStatus <= { \n  dataSequence, ACKRxed, \n  stallRxed, NAKRxed,\n  RXTimeOut, RXOverflow, \n  bitStuffError, CRCError};\nend"
+W 255 252 0 253 254 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 254 252 0 Builtin Exit | 129540,111760
+I 253 252 0 Builtin Entry | 86360,167640
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+W 249 246 0 247 248 BEZIER "Transitions" | 90833,167640 103003,150317 114258,129084 126428,111760
+I 248 246 0 Builtin Exit | 129540,111760
+I 247 246 0 Builtin Entry | 86360,167640
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,15739 96139,18958 88201,22665 84938,28363\
+                                       81676,34062 76804,50418 74237,60292 71671,70167\
+                                       66277,93309 65842,105315 65407,117321 69061,142203\
+                                       71671,150468 74281,158733 81067,166911 84373,169042\
+                                       87679,171174 93835,171446 97054,171620
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+L 256 257 0 TEXT "State Labels" | 45141,170869 1 0 0 "DELAY\n/17/"
+S 257 120 90112 ELLIPSE "States" | 45141,170869 6500 6500
+W 258 120 0 257 137 BEZIER "Transitions" | 45666,177344 46444,185513 47864,201600 52775,208115\
+                                           57686,214631 75382,223396 84426,228258
+L 259 260 0 TEXT "Labels" | 83376,219744 1 0 0 "SIERxTimeOutEn"
+I 260 0 2 Builtin OutPort | 77376,219744 "" ""
+END

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/getpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/hostcontroller.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/hostcontroller.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/hostcontroller.asf	(revision 264)
@@ -0,0 +1,301 @@
+VERSION=1.21
+HEADER
+FILE="hostcontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="hostcontroller"
+FREEOID=459
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// hostController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbHostControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,No Title"
+BLOCKTABLE_FILE=""
+BLOCKTABLE_TEMPL="0"
+BLOCKTABLE_VISIBLE="1"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3125 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3125 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+B T "Alias" 0,128,0 0 0 1 255,255,255 0 3527 1480 0000 0 "Arial" 0
+B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,0
+END
+INSTHEADER 45
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,0
+END
+INSTHEADER 47
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,0
+END
+INSTHEADER 49
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,0
+END
+INSTHEADER 51
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,0
+END
+OBJECTS
+C 285 97 0 TEXT "Conditions" | 92604,187877 1 0 0 "rst"
+I 284 0 2 Builtin InPort | 194131,244906 "" ""
+L 283 284 0 TEXT "Labels" | 200131,244906 1 0 0 "rst"
+I 282 0 3 Builtin InPort | 194091,250840 "" ""
+L 281 282 0 TEXT "Labels" | 202539,250534 1 0 0 "clk"
+L 274 273 0 TEXT "Labels" | 159907,218602 1 0 0 "getPacketRdy"
+I 273 0 130 Builtin InPort | 152377,218908 "" ""
+L 272 271 0 TEXT "Labels" | 156136,213642 1 0 0 "getPacketREn"
+S 15 6 0 ELLIPSE "States" | 111713,189976 6500 6500
+L 14 15 0 TEXT "State Labels" | 111713,189976 1 0 0 "START_HC\n/0/"
+L 7 6 0 TEXT "Labels" | 30788,196844 1 0 0 "hstCntrl"
+F 6 0 671089152 282 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,202584
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 110650,251000 1 0 0 "Module: hostcontroller"
+L 303 304 0 TEXT "State Labels" | 192420,160790 1 0 0 "WAIT_GNT\n/10/"
+A 302 83 16 TEXT "Actions" | 127391,163104 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 301 300 0 TEXT "Labels" | 38804,222186 1 0 0 "sendPacketRdy"
+I 300 0 130 Builtin InPort | 31274,222492 "" ""
+L 299 298 0 TEXT "Labels" | 34751,217674 1 0 0 "sendPacketWEn"
+I 298 0 2 Builtin OutPort | 29102,217674 "" ""
+A 296 294 4 TEXT "Actions" | 137744,29936 1 0 0 "clearTXReq <= 1'b0;\ntransDone <= 1'b0;\ndelCnt <= delCnt + 1'b1;\n//now wait for 'transReq' to clear"
+W 295 6 0 81 294 BEZIER "Transitions" | 118859,46885 118878,43940 119066,38166 119085,35221
+S 294 6 53248 ELLIPSE "States" | 119561,28750 6500 6500
+L 293 294 0 TEXT "State Labels" | 119561,28750 1 0 0 "FIN\n/9/"
+A 291 81 4 TEXT "Actions" | 137367,55613 1 0 0 "transDone <= 1'b1;\nclearTXReq <= 1'b1;\nsendPacketArbiterReq <= 1'b0;\ndelCnt <= 4'h0;"
+A 288 15 2 TEXT "Actions" | 133652,198047 1 0 0 "transDone <= 1'b0;\nclearTXReq <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\ndelCnt <= 4'h0;"
+S 319 59 65536 ELLIPSE "States" | 151472,194918 6500 6500
+L 318 319 0 TEXT "State Labels" | 151472,194918 1 0 0 "WAIT_IN_SENT\n/12/"
+A 311 308 4 TEXT "Actions" | 123760,87560 1 0 0 "getPacketREn <= 1'b0;"
+W 310 52 0 404 308 BEZIER "Transitions" | 144157,124978 133481,112866 122805,100754 112129,88642
+A 309 110 4 TEXT "Actions" | 44904,115868 1 0 0 "sendPacketWEn <= 1'b0;"
+S 308 52 61440 ELLIPSE "States" | 107020,84625 6500 6500
+L 307 308 0 TEXT "State Labels" | 107020,84625 1 0 0 "WAIT_PKT_RXED\n/11/"
+C 306 305 0 TEXT "Conditions" | 164748,145291 1 0 0 "sendPacketArbiterGnt == 1'b1"
+W 305 6 0 304 43 BEZIER "Transitions" | 191002,154450 189652,152125 187950,148225 179100,146987\
+                                        170250,145750 137550,145450 128737,144962 119925,144475\
+                                        117963,142662 116688,141837
+S 304 6 57344 ELLIPSE "States" | 192420,160790 6500 6500
+L 40 41 0 TEXT "State Labels" | 112713,167263 1 0 0 "TX_REQ\n/1/"
+S 41 6 4096 ELLIPSE "States" | 112713,167568 6500 6500
+L 42 43 0 TEXT "State Labels" | 112976,136504 1 0 0 "CHK_TYPE\n/2/"
+S 43 6 8192 ELLIPSE "States" | 112976,136504 6500 6500
+L 44 45 0 TEXT "State Labels" | 49893,95313 1 0 0 "SETUP"
+S 45 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49893,95313 6500 6500
+L 46 47 0 TEXT "State Labels" | 99705,96376 1 0 0 "IN"
+S 47 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 99705,96376 6500 6500
+A 322 320 16 TEXT "Actions" | 162913,159521 1 0 0 "getPacketREn <= 1'b1;"
+W 320 59 0 319 150 BEZIER "Transitions" | 155623,189917 168842,179244 176612,152490 174355,142767
+H 59 47 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3709 212900,251709
+I 56 52 0 Builtin Exit | 155694,46048
+I 55 52 0 Builtin Entry | 88756,239499
+H 52 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,249826
+S 51 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 186458,96146 6500 6500
+L 50 51 0 TEXT "State Labels" | 186458,96146 1 0 0 "OUT1"
+L 48 49 0 TEXT "State Labels" | 129168,96024 1 0 0 "OUT0"
+S 49 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 129168,96024 6500 6500
+W 327 66 0 215 390 BEZIER "Transitions" | 55251,240683 83254,240866 100464,243201 128467,243384
+L 330 331 0 TEXT "State Labels" | 96476,72804 1 0 0 "WAIT_RX_DATA\n/13/"
+S 331 66 69632 ELLIPSE "States" | 96476,72804 6500 6500
+W 332 66 0 220 435 BEZIER "Transitions" | 82899,126626 83372,118876 55983,116868 40261,109385
+C 333 332 0 TEXT "Conditions" | 54763,123556 1 0 0 "sendPacketRdy == 1'b1"
+H 73 51 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+H 66 49 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,251397
+A 336 331 4 TEXT "Actions" | 111860,73393 1 0 0 "getPacketREn <= 1'b0;"
+C 337 310 0 TEXT "Conditions" | 139571,117930 1 0 0 "sendPacketRdy == 1'b1"
+A 338 310 16 TEXT "Actions" | 120456,106130 1 0 0 "getPacketREn <= 1'b1;"
+W 339 52 0 308 56 BEZIER "Transitions" | 110024,78864 116338,69316 134242,47951 152734,46048
+C 340 339 0 TEXT "Conditions" | 118224,73426 1 0 0 "getPacketRdy == 1'b1"
+A 341 166 4 TEXT "Actions" | 157079,24225 1 0 0 "sendPacketWEn <= 1'b0;"
+W 344 66 0 331 216 BEZIER "Transitions" | 97868,66457 100908,59161 105520,44696 108123,41048\
+                                          110726,37400 115182,37514 117348,37514
+C 345 344 0 TEXT "Conditions" | 101416,62024 1 0 0 "getPacketRdy == 1'b1"
+W 346 73 0 362 349 BEZIER "Transitions" | 101068,125025 104071,112705 109895,89766 112898,77446
+A 347 346 16 TEXT "Actions" | 105590,103736 1 0 0 "getPacketREn <= 1'b1;"
+C 348 346 0 TEXT "Conditions" | 66474,121908 1 0 0 "sendPacketRdy == 1'b1"
+S 349 73 122880 ELLIPSE "States" | 114830,71242 6500 6500
+L 350 349 0 TEXT "State Labels" | 114830,71242 1 0 0 "WAIT_RX_DATA\n/26/"
+W 351 73 0 366 396 BEZIER "Transitions" | 70318,247790 89018,242122 119720,257393 138420,251725
+W 94 6 0 51 81 BEZIER "Transitions" | 181493,91952 168874,83012 133822,65627 123950,57460
+W 93 6 0 49 81 BEZIER "Transitions" | 127993,89635 125750,82007 122658,67311 120415,59683
+W 92 6 0 47 81 BEZIER "Transitions" | 101355,90092 105711,82326 111806,66998 115844,59100
+W 91 6 0 45 81 BEZIER "Transitions" | 54416,90646 64112,75509 98704,56843 113153,56395
+W 87 6 0 43 51 BEZIER "Transitions" | 118220,132664 143150,136241 175043,109266 180818,99376
+W 86 6 0 43 49 BEZIER "Transitions" | 115060,130351 118111,123351 123579,109006 126630,102006
+W 85 6 0 43 47 BEZIER "Transitions" | 110447,130519 108204,123339 103740,109788 101162,102706
+W 84 6 0 43 45 BEZIER "Transitions" | 107812,132557 93901,134173 58104,123053 54921,99430
+W 83 6 0 41 304 BEZIER "Transitions" | 117910,163666 130378,160682 185875,165903 188529,165995
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 112026,179538 111533,178559 112240,174040
+S 81 6 28672 ELLIPSE "States" | 118903,53366 6500 6500
+L 80 81 0 TEXT "State Labels" | 119262,53366 1 0 0 "FLAG\n/3/"
+W 356 73 0 349 365 BEZIER "Transitions" | 116222,64895 119262,57599 123874,43134 126477,39486\
+                                          129080,35838 133536,35952 135702,35952
+C 357 356 0 TEXT "Conditions" | 119770,60462 1 0 0 "getPacketRdy == 1'b1"
+S 358 73 126976 ELLIPSE "States" | 111590,212057 6500 6500
+A 360 349 4 TEXT "Actions" | 131462,81560 1 0 0 "getPacketREn <= 1'b0;"
+W 361 73 0 358 428 BEZIER "Transitions" | 116309,207589 134815,192456 138465,176391 156971,161258
+S 362 73 131072 ELLIPSE "States" | 99809,131397 6500 6500
+L 363 362 0 TEXT "State Labels" | 99809,131397 1 0 0 "WAIT_DATA1_SENT\n/28/"
+I 365 73 0 Builtin Exit | 138662,35952
+I 366 73 0 Builtin Entry | 66816,246531
+L 367 358 0 TEXT "State Labels" | 111590,212057 1 0 0 "WAIT_OUT_SENT\n/27/"
+W 371 59 3 152 411 BEZIER "Transitions" | 77326,102234 70334,100866 48368,97525 44264,93687\
+                                          40160,89849 37728,77233 37462,69633 37196,62033\
+                                          38564,44249 44378,36953 50192,29657 72080,18257\
+                                          79528,15331 86976,12405 94012,13028 97964,12876
+S 110 52 49152 ELLIPSE "States" | 73617,129595 6500 6500
+L 109 110 0 TEXT "State Labels" | 73617,129595 1 0 0 "CLR_SP_WEN2\n/8/"
+S 108 52 45056 ELLIPSE "States" | 174498,176772 6500 6500
+L 107 108 0 TEXT "State Labels" | 176450,177268 1 0 0 "CLR_SP_WEN1\n/7/"
+C 102 85 0 TEXT "Conditions" | 79876,119480 1 0 0 "transType == `IN_TRANS"
+C 101 86 0 TEXT "Conditions" | 113164,112165 1 0 0 "transType == `OUTDATA0_TRANS"
+C 100 84 0 TEXT "Conditions" | 49457,132403 1 0 0 "transType == `SETUP_TRANS"
+C 99 87 0 TEXT "Conditions" | 141093,129174 1 0 0 "transType == `OUTDATA1_TRANS"
+C 98 83 0 TEXT "Conditions" | 119681,168185 1 0 0 "transReq == 1'b1"
+W 97 6 0 96 15 BEZIER "Transitions" | 67359,192312 76513,189960 96079,191824 105233,189472
+I 96 6 0 Builtin Reset | 67359,192312
+A 369 361 16 TEXT "Actions" | 126920,183824 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+C 370 361 0 TEXT "Conditions" | 86834,198917 1 0 0 "sendPacketRdy == 1'b1"
+L 372 373 0 TEXT "State Labels" | 179395,223686 1 0 0 "HC_WAIT_RDY\n/16/"
+S 373 52 81920 ELLIPSE "States" | 179395,223686 6500 6500
+W 375 52 0 373 108 BEZIER "Transitions" | 178623,217239 177647,208722 175975,191756 174999,183239
+C 376 375 0 TEXT "Conditions" | 177072,208441 1 0 0 "sendPacketRdy == 1'b1"
+A 377 375 16 TEXT "Actions" | 157108,200846 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `SETUP;"
+C 378 116 0 TEXT "Conditions" | 53258,169344 1 0 0 "sendPacketRdy == 1'b1"
+L 379 380 0 TEXT "State Labels" | 153043,229722 1 0 0 "WAIT_SP_RDY1\n/17/"
+S 380 59 86016 ELLIPSE "States" | 153043,229722 6500 6500
+W 381 59 0 380 407 BEZIER "Transitions" | 147002,227324 124981,219947 108460,208500 86439,201123
+A 382 381 16 TEXT "Actions" | 89435,216617 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `IN;"
+C 383 381 0 TEXT "Conditions" | 106090,231041 1 0 0 "sendPacketRdy == 1'b1"
+W 116 52 0 401 110 BEZIER "Transitions" | 84052,173279 81052,160831 78050,148381 75050,135933
+W 115 52 0 55 373 BEZIER "Transitions" | 93011,239499 120749,236025 148029,232551 175767,229077
+L 384 385 0 TEXT "State Labels" | 186620,71948 1 0 0 "WAIT_SP_RDY2\n/18/"
+S 385 59 90112 ELLIPSE "States" | 186620,71948 6500 6500
+W 386 59 0 385 166 BEZIER "Transitions" | 183486,66256 181045,60723 176976,50941 174535,45408
+C 387 386 0 TEXT "Conditions" | 146475,66957 1 0 0 "sendPacketRdy == 1'b1"
+A 388 386 16 TEXT "Actions" | 170128,59796 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+L 389 390 0 TEXT "State Labels" | 131725,237760 1 0 0 "WAIT_SP_RDY1\n/19/"
+S 390 66 94208 ELLIPSE "States" | 131725,237760 6500 6500
+W 391 66 0 390 416 BEZIER "Transitions" | 137913,235773 147939,230044 168013,221734 178039,216005
+C 392 391 0 TEXT "Conditions" | 141274,239102 1 0 0 "sendPacketRdy == 1'b1"
+A 394 391 16 TEXT "Actions" | 145667,230012 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+L 395 396 0 TEXT "State Labels" | 139675,245351 1 0 0 "WAIT_SP_RDY1\n/29/"
+S 396 73 135168 ELLIPSE "States" | 139675,245351 6500 6500
+W 397 73 0 396 424 BEZIER "Transitions" | 145412,242298 162962,235383 162946,223497 180496,216582
+A 398 397 16 TEXT "Actions" | 151875,232674 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `OUT;"
+C 399 397 0 TEXT "Conditions" | 153292,243294 1 0 0 "sendPacketRdy == 1'b1"
+L 415 416 0 TEXT "State Labels" | 184376,214561 1 0 0 "CLR_WEN1\n/24/"
+C 414 413 0 TEXT "Conditions" | 77700,36125 1 0 0 "sendPacketRdy == 1'b1"
+W 413 59 0 410 411 BEZIER "Transitions" | 116936,37395 112774,31799 108046,18472 103884,12876
+A 412 407 4 TEXT "Actions" | 63480,178936 1 0 0 "sendPacketWEn <= 1'b0;"
+I 411 59 0 Builtin Exit | 100924,12876
+S 410 59 110592 ELLIPSE "States" | 120564,42788 6500 6500
+L 409 410 0 TEXT "State Labels" | 120564,42788 1 0 0 "WAIT_ACK_SENT\n/23/"
+W 408 59 0 407 319 BEZIER "Transitions" | 91076,194837 104710,194652 131341,194917 144975,194732
+S 407 59 106496 ELLIPSE "States" | 84577,194898 6500 6500
+L 406 407 0 TEXT "State Labels" | 84577,194898 1 0 0 "CLR_SP_WEN1\n/22/"
+W 405 52 0 110 404 BEZIER "Transitions" | 80112,129363 96294,128712 126507,129297 142689,128646
+S 404 52 102400 ELLIPSE "States" | 149172,129112 6500 6500
+L 403 404 0 TEXT "State Labels" | 149172,129112 1 0 0 "WAIT_DATA_SENT\n/21/"
+W 402 52 0 108 401 BEZIER "Transitions" | 167999,176830 148562,177853 110448,178550 91011,179573
+S 401 52 98304 ELLIPSE "States" | 84514,179756 6500 6500
+L 400 401 0 TEXT "State Labels" | 84514,179756 1 0 0 "WAIT_SETUP_SENT\n/20/"
+A 128 116 16 TEXT "Actions" | 50284,154444 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 431 428 4 TEXT "Actions" | 145169,147310 1 0 0 "sendPacketWEn <= 1'b0;"
+W 429 73 0 428 362 BEZIER "Transitions" | 155810,154454 142213,150199 119040,138892 105443,134637
+S 428 73 143360 ELLIPSE "States" | 161819,156930 6500 6500
+L 427 428 0 TEXT "State Labels" | 161819,156930 1 0 0 "CLR_WEN2\n/31/"
+W 426 73 0 424 358 BEZIER "Transitions" | 179954,211885 169687,210775 150256,207250 142255,207157\
+                                          134254,207065 123583,209376 117848,210301
+A 425 424 4 TEXT "Actions" | 171069,199110 1 0 0 "sendPacketWEn <= 1'b0;"
+S 424 73 139264 ELLIPSE "States" | 186239,213540 6500 6500
+L 423 424 0 TEXT "State Labels" | 186239,213540 1 0 0 "CLR_WEN1\n/30/"
+W 422 66 0 420 220 BEZIER "Transitions" | 146017,155476 130385,151129 102866,140281 87234,135934
+A 421 420 4 TEXT "Actions" | 133015,141020 1 0 0 "sendPacketWEn <= 1'b0;"
+S 420 66 118784 ELLIPSE "States" | 152255,157300 6500 6500
+L 419 420 0 TEXT "State Labels" | 152255,157300 1 0 0 "CLR_WEN2\n/25/"
+W 418 66 0 416 213 BEZIER "Transitions" | 177907,213929 158066,213883 119562,213232 99721,213186
+A 417 416 4 TEXT "Actions" | 170200,200035 1 0 0 "sendPacketWEn <= 1'b0;"
+S 416 66 114688 ELLIPSE "States" | 184376,214561 6500 6500
+I 147 59 0 Builtin Entry | 48274,244510
+S 152 59 36864 ELLIPSE "States" | 83733,103326 6500 6500
+L 153 152 0 TEXT "State Labels" | 83733,103326 1 0 0 "CHK_FOR_ERROR\n/5/"
+W 155 59 0 150 152 BEZIER "Transitions" | 164444,143068 113233,163825 88034,130762 85264,109640
+W 154 59 0 147 380 BEZIER "Transitions" | 52529,244510 85659,241682 118331,238852 151461,236024
+L 151 150 0 TEXT "State Labels" | 169272,138718 1 0 0 "WAIT_DATA_RXED\n/4/"
+S 150 59 32768 ELLIPSE "States" | 169272,138718 6500 6500
+C 444 320 0 TEXT "Conditions" | 127768,183900 1 0 0 "sendPacketRdy == 1'b1"
+C 442 441 0 TEXT "Conditions" | 70632,78432 1 0 0 "isoEn == 1'b1"
+W 441 59 1 152 411 BEZIER "Transitions" | 80207,97867 74663,87703 63240,68436 60930,60120\
+                                          58620,51804 60468,38868 64038,33660 67608,28452\
+                                          80040,20556 84492,18330 88944,16104 95212,13380\
+                                          97900,12876
+W 440 66 2 435 216 BEZIER "Transitions" | 37283,96930 37450,86034 36933,64502 39250,56716\
+                                          41567,48930 50502,39578 58559,36864 66617,34151\
+                                          89914,32647 97658,32793 105403,32939 113545,36471\
+                                          117386,37514
+C 439 436 0 TEXT "Conditions" | 45200,98446 1 0 0 "isoEn == 1'b0"
+A 437 436 16 TEXT "Actions" | 45964,81812 1 0 0 "getPacketREn <= 1'b1;"
+W 436 66 1 435 331 BEZIER "Transitions" | 43135,99848 51564,83991 80050,72911 89986,72452
+S 435 66 147456 ELLIPSE "States" | 37700,103412 6500 6500
+L 434 435 0 TEXT "State Labels" | 37700,103412 1 0 0 "CHK_ISO\n/32/"
+I 433 0 2 Builtin InPort | 150555,227440 "" ""
+L 432 433 0 TEXT "Labels" | 156555,227440 1 0 0 "isoEn"
+C 161 155 0 TEXT "Conditions" | 100044,154159 1 0 0 "getPacketRdy == 1'b1"
+A 164 150 4 TEXT "Actions" | 168621,121248 1 0 0 "getPacketREn <= 1'b0;"
+L 165 166 0 TEXT "State Labels" | 172827,39140 1 0 0 "CLR_SP_WEN2\n/6/"
+S 166 59 40960 ELLIPSE "States" | 172827,39140 6500 6500
+W 167 59 2 152 385 BEZIER "Transitions" | 90058,101832 121384,93858 152710,85883 184036,77909
+W 169 59 0 166 410 BEZIER "Transitions" | 166354,39725 153254,40876 140152,42028 127052,43179
+C 171 167 0 TEXT "Conditions" | 127655,112448 1 0 0 "RXStatus [`HC_CRC_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRXStatus [`HC_RX_OVERFLOW_BIT] == 1'b0 &&\nRXStatus [`HC_NAK_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_STALL_RXED_BIT] == 1'b0 &&\nRXStatus [`HC_RX_TIME_OUT_BIT] == 1'b0"
+W 455 6 0 294 41 BEZIER "Transitions" | 113108,29526 99069,31142 72011,34324 62012,39273\
+                                        52013,44222 40095,60786 37368,72855 34641,84925\
+                                        35651,116639 37115,130223 38580,143808 43428,166432\
+                                        52518,171128 61608,175825 90617,170916 106373,168997
+L 456 457 0 TEXT "Labels" | 190656,222568 1 0 0 "delCnt[3:0]"
+I 457 0 130 Builtin Signal | 187656,222568 "" ""
+C 458 455 0 TEXT "Conditions" | 77768,36546 1 0 0 "delCnt == 4'hf"
+A 192 108 4 TEXT "Actions" | 170431,157698 1 0 0 "sendPacketWEn <= 1'b0;"
+S 213 66 77824 ELLIPSE "States" | 93236,213619 6500 6500
+L 214 213 0 TEXT "State Labels" | 93236,213619 1 0 0 "WAIT_OUT_SENT\n/15/"
+I 215 66 0 Builtin Entry | 50996,240683
+I 216 66 0 Builtin Exit | 120308,37514
+S 220 66 73728 ELLIPSE "States" | 81455,132959 6500 6500
+L 221 220 0 TEXT "State Labels" | 81455,132959 1 0 0 "WAIT_DATA0_SENT\n/14/"
+W 223 66 0 213 420 BEZIER "Transitions" | 98275,209515 120430,193417 124908,177307 147063,161209
+C 229 223 0 TEXT "Conditions" | 70326,202505 1 0 0 "sendPacketRdy == 1'b1"
+A 230 223 16 TEXT "Actions" | 103561,186464 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+L 255 256 0 TEXT "Labels" | 159868,208391 1 0 0 "RXStatus[7:0]"
+I 271 0 2 Builtin OutPort | 150487,213642 "" ""
+I 270 0 130 Builtin OutPort | 29066,227064 "" ""
+L 269 270 0 TEXT "Labels" | 35066,227064 1 0 0 "sendPacketPID[3:0]"
+I 268 0 2 Builtin OutPort | 29318,212721 "" ""
+L 267 268 0 TEXT "Labels" | 35669,212721 1 0 0 "sendPacketArbiterReq"
+I 266 0 2 Builtin OutPort | 85109,222528 "" ""
+L 265 266 0 TEXT "Labels" | 90758,222528 1 0 0 "transDone"
+I 264 0 2 Builtin OutPort | 85109,212721 "" ""
+L 263 264 0 TEXT "Labels" | 90758,212721 1 0 0 "clearTXReq"
+I 261 0 130 Builtin InPort | 31358,207795 "" ""
+L 262 261 0 TEXT "Labels" | 39500,207489 1 0 0 "sendPacketArbiterGnt"
+L 260 259 0 TEXT "Labels" | 95246,217263 1 0 0 "transType[1:0]"
+I 259 0 130 Builtin InPort | 86798,217875 "" ""
+L 258 257 0 TEXT "Labels" | 96158,207688 1 0 0 "transReq"
+I 257 0 130 Builtin InPort | 87557,207994 "" ""
+I 256 0 130 Builtin InPort | 152950,208697 "" ""
+END

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/hostcontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/include/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/include/usbConstants_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/include/usbConstants_h.v	(revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v                                             
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc 
+     
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined       
+

Property changes on: common/components/usbhostslave/trunk/RTL/include/usbConstants_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v	(revision 264)
@@ -0,0 +1,86 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v                                           
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants 
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices 
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices 
+`define NAK_SET_MASK 8'h10
+`define SC_CRC_ERROR_BIT 0
+`define SC_BIT_STUFF_ERROR_BIT 1
+`define SC_RX_OVERFLOW_BIT 2
+`define SC_RX_TIME_OUT_BIT 3
+`define SC_NAK_SENT_BIT 4
+`define SC_STALL_SENT_BIT 5
+`define SC_ACK_RXED_BIT 6
+`define SC_DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices 
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+`define ENDPOINT_ISO_ENABLE_BIT 4
+//SCMasterControlegIndices 
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+`define SC_CONNECT_TO_HOST_BIT 6
+//SCinterruptRegIndices 
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+`define VBUS_DET_INT_BIT 5
+//TXTransactionTypes 
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts 
+`define SC_RX_PACKET_TOUT 18
+
+//line status reg
+`define VBUS_PRES_BIT 2
+
+`endif //usbSlaveControl_h_vdefined  

Property changes on: common/components/usbhostslave/trunk/RTL/include/usbSlaveControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/lineControlUpdate.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/lineControlUpdate.v	(revision 264)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// lineControlUpdate.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+    if (fullSpeedPolarity == 1'b1)
+  begin
+      JBit = `ONE_ZERO;
+      KBit = `ZERO_ONE;
+    end
+    else
+  begin
+      JBit = `ZERO_ONE;
+      KBit = `ONE_ZERO;
+    end
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/lineControlUpdate.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.asf	(revision 264)
@@ -0,0 +1,146 @@
+VERSION=1.15
+HEADER
+FILE="sendpacketcheckpreamble.asf"
+FID=4061fc61
+LANGUAGE=VERILOG
+ENTITY="sendPacketCheckPreamble"
+FRAMES=ON
+FREEOID=161
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// sendpacketcheckpreamble\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
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+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
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+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
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+END
+INSTHEADER 32
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+END
+INSTHEADER 95
+PAGE 25400,0 215900,279400
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+END
+OBJECTS
+W 15 6 0 14 9 BEZIER "Transitions" | 71492,195262 80777,191644 101181,191110 110466,187492
+I 14 6 0 Builtin Reset | 71492,195262
+S 13 6 4096 ELLIPSE "States" | 115726,124058 6500 6500
+L 12 13 0 TEXT "State Labels" | 116053,124712 1 0 0 "CHK_PREAM\n/2/"
+S 11 6 0 ELLIPSE "States" | 116345,155008 6500 6500
+L 10 11 0 TEXT "State Labels" | 116345,155008 1 0 0 "SPC_WAIT_EN\n/0/"
+L 7 6 0 TEXT "Labels" | 30898,204697 1 0 0 "sendPktCP"
+F 6 0 671089152 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,207642
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 99275,247750 1 0 0 "Module: sendPacketCheckPreamble"
+L 8 9 0 TEXT "State Labels" | 116345,184720 1 0 0 "START_SPC\n/1/"
+S 9 6 0 ELLIPSE "States" | 116345,184720 6500 6500
+L 31 32 0 TEXT "State Labels" | 57151,91032 1 0 0 "PREAM_PKT"
+C 22 21 0 TEXT "Conditions" | 65936,121144 1 0 0 "preAmbleEnable == 1'b1"
+W 21 6 8193 13 32 BEZIER "Transitions" | 110607,120054 106899,116733 72529,98135 62376,94411
+C 18 17 0 TEXT "Conditions" | 117735,147915 1 0 0 "sendPacketCPWEn == 1'b1"
+W 17 6 0 11 13 BEZIER "Transitions" | 116183,148530 115952,143895 116120,135190 115889,130555
+W 16 6 0 9 11 BEZIER "Transitions" | 116203,178222 116126,173974 116185,165745 116108,161497
+L 47 42 0 TEXT "State Labels" | 88281,184091 1 0 0 "SND_PREAM\n/3/"
+C 46 44 0 TEXT "Conditions" | 90495,228129 1 0 0 "sendPacketRdy == 1'b1"
+W 44 33 0 51 42 BEZIER "Transitions" | 84887,226737 85645,222776 87076,194213 87756,190564
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+W 38 33 0 36 51 BEZIER "Transitions" | 63477,258101 69037,250316 70846,246959 79547,237634
+I 37 33 0 Builtin Exit | 189069,45293
+I 36 33 0 Builtin Entry | 59261,258101
+H 33 32 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 32 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 56824,91032 6500 6500
+C 63 62 0 TEXT "Conditions" | 70466,115662 1 0 0 "sendPacketRdy == 1'b1"
+W 62 33 0 156 60 BEZIER "Transitions" | 58983,118146 59059,114780 91699,99435 91452,95786
+L 61 60 0 TEXT "State Labels" | 91408,89327 1 0 0 "SND_PID\n/6/"
+S 60 33 24576 ELLIPSE "States" | 91408,89327 6500 6500
+A 57 42 4 TEXT "Actions" | 105975,186050 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `PREAMBLE;"
+W 56 33 0 42 55 BEZIER "Transitions" | 88167,177623 88080,173073 88319,164339 88052,159633
+S 55 33 20480 ELLIPSE "States" | 88319,153150 6500 6500
+L 54 55 0 TEXT "State Labels" | 88319,153150 1 0 0 "PREAM_SENT\n/5/"
+L 52 51 0 TEXT "State Labels" | 84300,233201 1 0 0 "WAIT_RDY1\n/4/"
+S 51 33 16384 ELLIPSE "States" | 84300,233201 6500 6500
+L 69 68 0 TEXT "State Labels" | 91777,58386 1 0 0 "PID_SENT\n/7/"
+S 68 33 28672 ELLIPSE "States" | 91777,58386 6500 6500
+A 67 60 4 TEXT "Actions" | 109102,91286 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 65 33 0 60 68 BEZIER "Transitions" | 91294,82859 91207,78309 91509,69422 91422,64872
+C 73 39 0 TEXT "Conditions" | 145852,37243 1 0 0 "sendPacketRdy == 1'b1"
+L 84 85 0 TEXT "Labels" | 37234,242140 1 0 0 "sendPacketCPWEn"
+I 85 0 2 Builtin InPort | 31234,242140 "" ""
+L 86 87 0 TEXT "Labels" | 37564,247430 1 0 0 "sendPacketCPPID[3:0]"
+I 87 0 130 Builtin InPort | 31564,247430 "" ""
+L 90 91 0 TEXT "Labels" | 145129,219071 1 0 0 "sendPacketWEn"
+I 91 0 2 Builtin OutPort | 139129,219071 "" ""
+L 92 93 0 TEXT "Labels" | 145050,213623 1 0 0 "sendPacketPID[3:0]"
+I 93 0 130 Builtin OutPort | 139050,213623 "" ""
+L 94 95 0 TEXT "State Labels" | 171474,95500 1 0 0 "REG_PKT"
+S 95 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 171474,95500 6500 6500
+L 88 89 0 TEXT "Labels" | 35117,236671 1 0 0 "sendPacketCPReady"
+I 89 0 2 Builtin OutPort | 29117,236671 "" ""
+W 96 6 8194 13 95 BEZIER "Transitions" | 121433,120948 133123,115553 154096,104038 165786,98643
+H 98 95 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 105 98 0 Builtin Entry | 69392,262686
+I 106 98 0 Builtin Exit | 199200,49878
+W 107 98 0 105 114 BEZIER "Transitions" | 73608,262686 79168,254901 80977,251544 89678,242219
+S 109 98 36864 ELLIPSE "States" | 98412,188676 6500 6500
+W 110 98 0 114 109 BEZIER "Transitions" | 95018,231322 95776,227361 97207,198798 97887,195149
+C 112 110 0 TEXT "Conditions" | 100626,232714 1 0 0 "sendPacketRdy == 1'b1"
+L 113 109 0 TEXT "State Labels" | 98412,188676 1 0 0 "SEND_PID\n/8/"
+S 114 98 40960 ELLIPSE "States" | 94431,237786 6500 6500
+L 115 114 0 TEXT "State Labels" | 94431,237786 1 0 0 "WAIT_RDY1\n/9/"
+S 116 98 45056 ELLIPSE "States" | 98781,157735 6500 6500
+L 117 116 0 TEXT "State Labels" | 98781,157735 1 0 0 "WAIT_RDY\n/10/"
+W 118 98 0 109 116 BEZIER "Transitions" | 98298,182208 98211,177658 98513,168771 98426,164221
+A 119 109 4 TEXT "Actions" | 116106,190635 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= sendPacketCPPID;"
+W 123 98 0 116 106 BEZIER "Transitions" | 99210,151256 92796,151029 166679,67985 196072,49878
+A 133 17 16 TEXT "Actions" | 115300,141513 1 0 0 "sendPacketCPReady <= 1'b0;"
+L 134 135 0 TEXT "State Labels" | 115950,65625 1 0 0 "READY\n/11/"
+S 135 6 49152 ELLIPSE "States" | 116600,65625 6500 6500
+A 136 135 4 TEXT "Actions" | 135450,67738 1 0 0 "sendPacketCPReady <= 1'b1;"
+W 137 6 0 32 135 BEZIER "Transitions" | 62376,87653 75051,82778 97748,72523 110423,67648
+W 138 6 0 95 135 BEZIER "Transitions" | 165830,92278 154699,86672 133369,74464 122238,68858
+W 139 6 0 135 11 BEZIER "Transitions" | 114963,59339 113907,57389 112456,53925 103681,52747\
+                                        94907,51569 61918,50756 52575,52503 43232,54250\
+                                        38843,62050 37706,72734 36569,83418 36406,118357\
+                                        40062,129609 43718,140862 58507,150938 67687,153172\
+                                        76868,155407 98883,155302 109851,154734
+L 140 141 0 TEXT "Labels" | 199053,251257 1 0 0 "clk"
+I 141 0 3 Builtin InPort | 193053,251257 "" ""
+L 142 143 0 TEXT "Labels" | 198551,245909 1 0 0 "rst"
+I 143 0 2 Builtin InPort | 192551,245909 "" ""
+I 151 0 2 Builtin InPort | 34428,222262 "" ""
+L 150 151 0 TEXT "Labels" | 40428,222262 1 0 0 "preAmbleEnable"
+L 148 147 0 TEXT "Labels" | 147295,224322 1 0 0 "sendPacketRdy"
+I 147 0 2 Builtin InPort | 141295,224322 "" ""
+C 144 15 0 TEXT "Conditions" | 95870,191427 1 0 0 "rst"
+A 145 9 2 TEXT "Actions" | 136081,193747 1 0 0 "sendPacketWEn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketCPReady <= 1'b1;"
+A 152 116 4 TEXT "Actions" | 116610,159800 1 0 0 "sendPacketWEn <= 1'b0;"
+A 153 55 4 TEXT "Actions" | 107648,155030 1 0 0 "sendPacketWEn <= 1'b0;"
+A 154 68 4 TEXT "Actions" | 110643,60458 1 0 0 "sendPacketWEn <= 1'b0;"
+L 155 156 0 TEXT "State Labels" | 56256,124044 1 0 0 "WAIT_RDY2\n/12/"
+S 156 33 53248 ELLIPSE "States" | 56256,124044 6500 6500
+L 157 158 0 TEXT "State Labels" | 111700,39052 1 0 0 "WAIT_RDY3\n/13/"
+S 158 33 57344 ELLIPSE "States" | 111700,39052 6500 6500
+W 159 33 0 55 156 BEZIER "Transitions" | 82977,149448 77086,144036 66423,134323 60447,129011
+W 160 33 0 68 158 BEZIER "Transitions" | 95503,53062 98906,50738 103474,45732 106877,43408
+END

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/softransmit.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/softransmit.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/softransmit.asf	(revision 264)
@@ -0,0 +1,110 @@
+VERSION=1.15
+HEADER
+FILE="softransmit.asf"
+FID=405c2645
+LANGUAGE=VERILOG
+ENTITY="SOFTransmit"
+FRAMES=ON
+FREEOID=95
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// softransmit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbHostControl_h.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
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+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
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+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: SOFTransmit"
+F 6 0 671089152 54 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28222,2382 211664,199561
+L 7 6 0 TEXT "Labels" | 56120,190808 1 0 0 "SOFTx"
+L 8 9 0 TEXT "State Labels" | 118204,174817 1 0 0 "START_STX\n/0/"
+S 9 6 0 ELLIPSE "States" | 118204,174817 6500 6500
+L 10 11 0 TEXT "State Labels" | 120061,145105 1 0 0 "WAIT_SOF_NEAR\n/1/"
+S 11 6 4096 ELLIPSE "States" | 120061,145105 6500 6500
+L 12 13 0 TEXT "State Labels" | 121510,105827 1 0 0 "WAIT_SP_GNT\n/2/"
+S 13 6 8192 ELLIPSE "States" | 121510,105827 6500 6500
+L 14 15 0 TEXT "State Labels" | 122537,67111 1 0 0 "WAIT_SOF_NOW\n/3/"
+S 15 6 12288 ELLIPSE "States" | 122537,67111 6500 6500
+I 31 0 130 Builtin InPort | 86106,205240 "" ""
+L 30 31 0 TEXT "Labels" | 92106,205240 1 0 0 "SOFTimer[15:0]"
+I 16 6 0 Builtin Reset | 76112,190530
+W 17 6 0 16 9 BEZIER "Transitions" | 76112,190530 85242,187531 103162,180515 112292,177516
+W 18 6 0 9 11 BEZIER "Transitions" | 118406,168343 118715,164010 119133,156247 119287,154003\
+                                     119442,151760 119430,151725 119430,151571
+W 19 6 0 11 13 BEZIER "Transitions" | 120145,138606 120299,132262 120897,118647 121051,112303
+W 20 6 0 13 15 BEZIER "Transitions" | 121100,99349 121564,91767 121564,81165 122028,73583
+C 22 19 0 TEXT "Conditions" | 121150,136806 1 0 0 "SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||\n(SOFSyncEn == 1'b1 &&\nSOFEnable == 1'b1)"
+C 23 20 0 TEXT "Conditions" | 123101,97583 1 0 0 "sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1"
+L 25 26 0 TEXT "State Labels" | 123851,14954 1 0 0 "SOF_FIN\n/4/"
+S 26 6 16384 ELLIPSE "States" | 123851,14954 6500 6500
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+C 28 27 0 TEXT "Conditions" | 141873,64536 1 0 0 "SOFTimer >= `SOF_TX_TIME"
+A 29 27 16 TEXT "Actions" | 136781,44343 1 0 0 "sendPacketWEn <= 1'b1;\nSOFTimerClr <= 1'b1;\nSOFSent <= 1'b1;"
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+L 46 47 0 TEXT "Labels" | 89987,210042 1 0 0 "SOFTimerClr"
+A 45 9 2 TEXT "Actions" | 136108,187846 1 0 0 "SOFSent <= 1'b0;\nSOFTimerClr <= 1'b0;\nsendPacketArbiterReq <= 1'b0;\nsendPacketWEn <= 1'b0;\ni <= 8'h00;"
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+I 58 0 2 Builtin InPort | 32035,210006 "" ""
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+I 56 0 130 Builtin InPort | 200475,245251 "" ""
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+K 49 47 0 TEXT "Comments" | 111272,209575 1 0 0 "Single cycle pulse"
+S 79 6 24576 ELLIPSE "States" | 54655,123733 6500 6500
+L 78 79 0 TEXT "State Labels" | 54655,123733 1 0 0 "DLY_SOF_CHK2\n/6/"
+A 72 70 16 TEXT "Actions" | 88430,42600 1 0 0 "SOFTimerClr <= 1'b1;"
+C 71 70 0 TEXT "Conditions" | 81824,61424 1 0 0 "SOFEnable == 1'b0"
+W 70 6 8194 15 26 BEZIER "Transitions" | 117343,63205 114476,60245 108317,54810 106883,51064\
+                                         105450,47318 105450,38252 107207,34228 108965,30205\
+                                         115846,23167 119361,19652
+A 68 19 16 TEXT "Actions" | 101850,122190 1 0 0 "sendPacketArbiterReq <= 1'b1;"
+L 65 64 0 TEXT "Labels" | 38202,219273 1 0 0 "sendPacketArbiterGnt"
+I 64 0 2 Builtin InPort | 32202,219273 "" ""
+K 69 60 0 TEXT "Comments" | 78222,224799 1 0 0 "After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn"
+L 73 74 0 TEXT "State Labels" | 63408,80448 1 0 0 "DLY_SOF_CHK1\n/5/"
+S 74 6 20480 ELLIPSE "States" | 63408,80448 6500 6500
+W 75 6 0 26 74 BEZIER "Transitions" | 117387,14280 106719,14616 86172,13920 78234,17868\
+                                      70296,21816 59880,36936 57948,44622 56016,52308\
+                                      59778,66554 61122,74366
+A 76 75 16 TEXT "Actions" | 55404,31002 1 0 0 "i <= 8'h00;"
+C 94 92 0 TEXT "Conditions" | 68357,136883 1 0 0 "i==8'hff"
+A 93 79 4 TEXT "Actions" | 72777,123623 1 0 0 "i <= i + 1'b1;"
+W 92 6 0 79 11 BEZIER "Transitions" | 60486,126602 74574,130193 99716,139754 113804,143345
+A 91 82 16 TEXT "Actions" | 49949,109037 1 0 0 "sendPacketArbiterReq <= 1'b0;\ni <= 8'h00;"
+C 90 82 0 TEXT "Conditions" | 61793,96219 1 0 0 "i==8'hff"
+A 88 74 4 TEXT "Actions" | 81838,80970 1 0 0 "i <= i + 1'b1;"
+I 87 0 130 Builtin Signal | 47362,241979 "" ""
+L 86 87 0 TEXT "Labels" | 50362,241979 1 0 0 "i[7:0]"
+C 85 75 0 TEXT "Conditions" | 66368,14007 1 0 0 "sendPacketRdy == 1'b1"
+W 82 6 0 74 79 BEZIER "Transitions" | 61272,86583 60002,89345 56169,113512 55585,117302
+END

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/softransmit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostSlaveMux/hostSlaveMux.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostSlaveMux/hostSlaveMux.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostSlaveMux/hostSlaveMux.v	(revision 264)
@@ -0,0 +1,197 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMux.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Controls the select line for the mux that enables the sharing
+//// of a single SerialInterfaceEgine between the hostController
+//// and slaveController
+//// Also a dumping area for any features common to host and slave 
+//// operation. That is reset control and version number report.
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module hostSlaveMux (
+  SIEPortCtrlInToSIE,
+  SIEPortCtrlInFromHost,
+  SIEPortCtrlInFromSlave,
+  SIEPortDataInToSIE, 
+  SIEPortDataInFromHost, 
+  SIEPortDataInFromSlave, 
+  SIEPortWEnToSIE, 
+  SIEPortWEnFromHost, 
+  SIEPortWEnFromSlave, 
+  fullSpeedPolarityToSIE,
+  fullSpeedPolarityFromHost,
+  fullSpeedPolarityFromSlave,
+  fullSpeedBitRateToSIE,
+  fullSpeedBitRateFromHost,
+  fullSpeedBitRateFromSlave,
+  noActivityTimeOutEnableToSIE,
+  noActivityTimeOutEnableFromHost,
+  noActivityTimeOutEnableFromSlave,
+  dataIn, 
+  dataOut,
+  address,
+  writeEn,
+  strobe_i,
+  busClk, 
+  usbClk, 
+  hostSlaveMuxSel,
+  rstFromWire,
+  rstSyncToBusClkOut,
+  rstSyncToUsbClkOut
+);
+
+
+output [7:0] SIEPortCtrlInToSIE;
+input [7:0] SIEPortCtrlInFromHost;
+input [7:0] SIEPortCtrlInFromSlave;
+output [7:0] SIEPortDataInToSIE; 
+input [7:0] SIEPortDataInFromHost; 
+input [7:0] SIEPortDataInFromSlave; 
+output SIEPortWEnToSIE; 
+input SIEPortWEnFromHost; 
+input SIEPortWEnFromSlave; 
+output fullSpeedPolarityToSIE;
+input fullSpeedPolarityFromHost;
+input fullSpeedPolarityFromSlave;
+output fullSpeedBitRateToSIE;
+input fullSpeedBitRateFromHost;
+input fullSpeedBitRateFromSlave;
+output noActivityTimeOutEnableToSIE;
+input noActivityTimeOutEnableFromHost;
+input noActivityTimeOutEnableFromSlave;
+//hostSlaveMuxBI
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+
+reg [7:0] SIEPortCtrlInToSIE;
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+reg [7:0] SIEPortDataInToSIE; 
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+reg SIEPortWEnToSIE; 
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+reg fullSpeedPolarityToSIE;
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+reg fullSpeedBitRateToSIE;
+wire fullSpeedBitRateFromHost;
+wire fullSpeedBitRateFromSlave;
+reg noActivityTimeOutEnableToSIE;
+wire noActivityTimeOutEnableFromHost;
+wire noActivityTimeOutEnableFromSlave;
+//hostSlaveMuxBI
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClkOut;
+wire rstSyncToUsbClkOut;
+wire rstFromWire;
+wire [7:0] dataOut;
+wire hostSlaveMuxSel;
+
+//internal wires and regs
+wire hostMode;
+
+always @(hostMode or
+  SIEPortCtrlInFromHost or
+  SIEPortCtrlInFromSlave or
+  SIEPortDataInFromHost or 
+  SIEPortDataInFromSlave or 
+  SIEPortWEnFromHost or 
+  SIEPortWEnFromSlave or 
+  fullSpeedPolarityFromHost or
+  fullSpeedPolarityFromSlave or
+  fullSpeedBitRateFromHost or
+  fullSpeedBitRateFromSlave or
+  noActivityTimeOutEnableFromHost or
+  noActivityTimeOutEnableFromSlave)
+begin
+  if (hostMode == 1'b1) 
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromHost;
+    SIEPortDataInToSIE <=  SIEPortDataInFromHost;
+    SIEPortWEnToSIE <= SIEPortWEnFromHost;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromHost;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromHost;
+    noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromHost;
+  end
+  else
+  begin
+    SIEPortCtrlInToSIE <= SIEPortCtrlInFromSlave;
+    SIEPortDataInToSIE <=  SIEPortDataInFromSlave;
+    SIEPortWEnToSIE <= SIEPortWEnFromSlave;
+    fullSpeedPolarityToSIE <= fullSpeedPolarityFromSlave;
+    fullSpeedBitRateToSIE <= fullSpeedBitRateFromSlave;
+    noActivityTimeOutEnableToSIE <= noActivityTimeOutEnableFromSlave;
+  end
+end      
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(dataIn), 
+  .dataOut(dataOut),
+  .address(address),
+  .writeEn(writeEn), 
+  .strobe_i(strobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .hostMode(hostMode), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),  
+  .rstFromWire(rstFromWire),
+  .rstSyncToBusClkOut(rstSyncToBusClkOut),
+  .rstSyncToUsbClkOut(rstSyncToUsbClkOut) );
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/hostSlaveMux/hostSlaveMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxByte.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxByte.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxByte.v	(revision 264)
@@ -0,0 +1,493 @@
+
+// File        : ../RTL/serialInterfaceEngine/processRxByte.v
+// Generated   : 11/10/06 05:37:22
+// From        : ../RTL/serialInterfaceEngine/processRxByte.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processRxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC);
+input   [15:0] CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0] CRC5Result;
+input   CRC5UpdateRdy;
+input   [7:0] RxByteIn;
+input   [7:0] RxCtrlIn;
+input   clk;
+input   processRxDataInWEn;
+input   rst;
+output  CRC16En;
+output  CRC5En;
+output  CRC5_8Bit;
+output  [7:0] CRCData;
+output  [7:0] RxCtrlOut;
+output  RxDataOutWEn;
+output  [7:0] RxDataOut;
+output  processRxByteRdy;
+output  rstCRC;
+
+reg     CRC16En, next_CRC16En;
+wire    [15:0] CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5En, next_CRC5En;
+wire    [4:0] CRC5Result;
+wire    CRC5UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     [7:0] CRCData, next_CRCData;
+wire    [7:0] RxByteIn;
+wire    [7:0] RxCtrlIn;
+reg     [7:0] RxCtrlOut, next_RxCtrlOut;
+reg     RxDataOutWEn, next_RxDataOutWEn;
+reg     [7:0] RxDataOut, next_RxDataOut;
+wire    clk;
+reg     processRxByteRdy, next_processRxByteRdy;
+wire    processRxDataInWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+
+// diagram signals declarations
+reg  ACKRxed, next_ACKRxed;
+reg  CRCError, next_CRCError;
+reg  NAKRxed, next_NAKRxed;
+reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg  [7:0]RxByte, next_RxByte;
+reg  [7:0]RxCtrl, next_RxCtrl;
+reg  RxOverflow, next_RxOverflow;
+reg  [7:0]RxStatus;
+reg  RxTimeOut, next_RxTimeOut;
+reg  Signal1, next_Signal1;
+reg  bitStuffError, next_bitStuffError;
+reg  dataSequence, next_dataSequence;
+reg  stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0] CurrState_prRxByte;
+reg [3:0] NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+always @
+(next_CRCError or next_bitStuffError or
+  next_RxOverflow or next_NAKRxed or
+  next_stallRxed or next_ACKRxed or
+  next_dataSequence)
+begin
+    RxStatus <=
+    {1'b0, next_dataSequence,
+    next_ACKRxed,
+    next_stallRxed, next_NAKRxed,
+    next_RxOverflow,
+    next_bitStuffError, next_CRCError };
+end
+
+//--------------------------------------------------------------------
+// Machine: prRxByte
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin : prRxByte_NextState
+  NextState_prRxByte <= CurrState_prRxByte;
+  // Set default values for outputs and signals
+  next_RxByte <= RxByte;
+  next_RxCtrl <= RxCtrl;
+  next_RXByteStMachCurrState <= RXByteStMachCurrState;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RxOverflow <= RxOverflow;
+  next_RxTimeOut <= RxTimeOut;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_RxDataOut <= RxDataOut;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOutWEn <= RxDataOutWEn;
+  next_rstCRC <= rstCRC;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_RXDataByteCnt <= RXDataByteCnt;
+  next_processRxByteRdy <= processRxByteRdy;
+  case (CurrState_prRxByte)
+    `CHK_ST:
+      if (RXByteStMachCurrState == `HS_BYTE_ST)	
+        NextState_prRxByte <= `HSHAKE_CHK;
+      else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)	
+        NextState_prRxByte <= `TOKEN_WAIT_CRC;
+      else if (RXByteStMachCurrState == `DATA_BYTE_ST)	
+        NextState_prRxByte <= `DATA_WAIT_CRC;
+      else if (RXByteStMachCurrState == `IDLE_BYTE_ST)	
+        NextState_prRxByte <= `IDLE_CHK_START;
+      else if (RXByteStMachCurrState == `CHECK_SYNC_ST)	
+        NextState_prRxByte <= `CHK_SYNC_DO;
+      else if (RXByteStMachCurrState == `CHECK_PID_ST)	
+        NextState_prRxByte <= `CHK_PID_DO_CHK;
+    `START_PRBY:
+    begin
+      next_RxByte <= 8'h00;
+      next_RxCtrl <= 8'h00;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RxOverflow <= 1'b0;
+      next_RxTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_RxDataOut <= 8'h00;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOutWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_RXDataByteCnt <= 10'h00;
+      next_processRxByteRdy <= 1'b1;
+      NextState_prRxByte <= `WAIT_BYTE;
+    end
+    `WAIT_BYTE:
+      if (processRxDataInWEn == 1'b1)	
+      begin
+        NextState_prRxByte <= `CHK_ST;
+        next_RxByte <= RxByteIn;
+        next_RxCtrl <= RxCtrlIn;
+        next_processRxByteRdy <= 1'b0;
+      end
+    `HSHAKE_FIN:
+    begin
+      next_RxDataOutWEn <= 1'b0;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `HSHAKE_CHK:
+    begin
+      NextState_prRxByte <= `HSHAKE_FIN;
+      if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+        next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RxDataOutWEn <= 1'b1;
+    end
+    `CHK_PID_DO_CHK:
+      if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)	
+      begin
+        NextState_prRxByte <= `WAIT_BYTE;
+        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+        next_processRxByteRdy <= 1'b1;
+      end
+      else
+      begin
+        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+        next_CRCError <= 1'b0;
+        next_bitStuffError <= 1'b0;
+        next_RxOverflow <= 1'b0;
+        next_NAKRxed <= 1'b0;
+        next_stallRxed <= 1'b0;
+        next_ACKRxed <= 1'b0;
+        next_dataSequence <= 1'b0;
+        next_RxTimeOut <= 1'b0;
+        next_RXDataByteCnt <= 10'h000;
+        next_RxDataOut <= RxByte;
+        next_RxCtrlOut <= `RX_PACKET_START;
+        next_RxDataOutWEn <= 1'b1;
+        next_rstCRC <= 1'b1;
+      end
+    `CHK_PID_FIRST_BYTE_PROC:
+    begin
+      next_rstCRC <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      case (RxByte[1:0] )
+          `SPECIAL:                              //Special PID.
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          `TOKEN:                                //Token PID
+          begin
+          next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+          next_RXDataByteCnt <= 0;
+          end
+          `HANDSHAKE:                            //Handshake PID
+          begin
+              case (RxByte[3:2] )
+                  2'b00:
+              next_ACKRxed <= 1'b1;
+                  2'b10:
+              next_NAKRxed <= 1'b1;
+                  2'b11:
+              next_stallRxed <= 1'b1;
+                  default:
+                  begin
+                      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+                  end
+              endcase
+          next_RXByteStMachCurrState <= `HS_BYTE_ST;
+          end
+          `DATA:                                  //Data PID
+          begin
+              case (RxByte[3:2] )
+                  2'b00:
+              next_dataSequence <= 1'b0;
+                  2'b10:
+              next_dataSequence <= 1'b1;
+                  default:
+                      $display ("Invalid DATA PID detected in ProcessRXByte\n");
+              endcase
+          next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+          next_RXDataByteCnt <= 0;
+          end
+      endcase
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_FIN:
+    begin
+      next_CRC16En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+          `DATA_STOP:
+          begin
+              if (CRC16Result != 16'hb001)
+            next_CRCError <= 1'b1;
+          next_RxDataOut <= RxStatus;
+          next_RxCtrlOut <= `RX_PACKET_STOP;
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+          `DATA_BIT_STUFF_ERROR:
+          begin
+          next_bitStuffError <= 1'b1;
+          next_RxDataOut <= RxStatus;
+          next_RxCtrlOut <= `RX_PACKET_STOP;
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+          `DATA_STREAM:
+          begin
+          next_RxDataOut <= RxByte;
+          next_RxCtrlOut <= `RX_PACKET_STREAM;
+          next_CRCData <= RxByte;
+          next_CRC16En <= 1'b1;
+          end
+          default:
+          begin
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `DATA_FIN;
+    end
+    `DATA_WAIT_CRC:
+      if (CRC16UpdateRdy == 1'b1)	
+        NextState_prRxByte <= `DATA_CHK_STRM;
+    `TOKEN_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+          `DATA_STOP:
+          begin
+              if (CRC5Result != 5'h6)
+            next_CRCError <= 1'b1;
+          next_RxDataOut <= RxStatus;
+          next_RxCtrlOut <= `RX_PACKET_STOP;
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+          `DATA_BIT_STUFF_ERROR:
+          begin
+          next_bitStuffError <= 1'b1;
+          next_RxDataOut <= RxStatus;
+          next_RxCtrlOut <= `RX_PACKET_STOP;
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+          `DATA_STREAM:
+          begin
+              if (RXDataByteCnt > 10'h2)
+              begin
+            next_RxOverflow <= 1'b1;
+            next_RxDataOut <= RxStatus;
+            next_RxCtrlOut <= `RX_PACKET_STOP;
+            next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+              end
+              else
+              begin
+            next_RxDataOut <= RxByte;
+            next_RxCtrlOut <= `RX_PACKET_STREAM;
+            next_CRCData <= RxByte;
+            next_CRC5_8Bit <= 1'b1;
+            next_CRC5En <= 1'b1;
+              end
+          end
+          default:
+          begin
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `TOKEN_FIN;
+    end
+    `TOKEN_FIN:
+    begin
+      next_CRC5En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `TOKEN_WAIT_CRC:
+      if (CRC5UpdateRdy == 1'b1)	
+        NextState_prRxByte <= `TOKEN_CHK_STRM;
+    `CHK_SYNC_DO:
+    begin
+      if (RxByte == `SYNC_BYTE)
+        next_RXByteStMachCurrState <= `CHECK_PID_ST;
+      else
+        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `IDLE_CHK_START:
+    begin
+      if (RxCtrl == `DATA_START)
+        next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prRxByte_CurrentState
+  if (rst)	
+    CurrState_prRxByte <= `START_PRBY;
+  else
+    CurrState_prRxByte <= NextState_prRxByte;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prRxByte_RegOutput
+  if (rst)	
+  begin
+    RxByte <= 8'h00;
+    RxCtrl <= 8'h00;
+    RXByteStMachCurrState <= `IDLE_BYTE_ST;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RxOverflow <= 1'b0;
+    RxTimeOut <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    RXDataByteCnt <= 10'h00;
+    RxDataOut <= 8'h00;
+    RxCtrlOut <= 8'h00;
+    RxDataOutWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    processRxByteRdy <= 1'b1;
+  end
+  else 
+  begin
+    RxByte <= next_RxByte;
+    RxCtrl <= next_RxCtrl;
+    RXByteStMachCurrState <= next_RXByteStMachCurrState;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RxOverflow <= next_RxOverflow;
+    RxTimeOut <= next_RxTimeOut;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    RXDataByteCnt <= next_RXDataByteCnt;
+    RxDataOut <= next_RxDataOut;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOutWEn <= next_RxDataOutWEn;
+    rstCRC <= next_rstCRC;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    processRxByteRdy <= next_processRxByteRdy;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/siereceiver.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/siereceiver.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/siereceiver.asf	(revision 264)
@@ -0,0 +1,241 @@
+VERSION=1.21
+HEADER
+FILE="siereceiver.asf"
+FID=408ab644
+LANGUAGE=VERILOG
+ENTITY="SIEReceiver"
+FREEOID=262
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIEReceiver\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,No Title"
+BLOCKTABLE_FILE=""
+BLOCKTABLE_TEMPL="0"
+BLOCKTABLE_VISIBLE="1"
+END
+BUNDLES
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+B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
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+W 204 99 0 201 199 BEZIER "Transitions" | 75683,156094 76364,148603 119799,32127 120480,24636
+I 219 0 130 Builtin Signal | 20132,240754 "" ""
+L 218 219 0 TEXT "Labels" | 23132,240754 1 0 0 "RXWaitCount[7:0]"
+I 215 0 130 Builtin Signal | 20439,246180 "" ""
+L 214 215 0 TEXT "Labels" | 23439,246180 1 0 0 "RXStMachCurrState[3:0]"
+L 208 209 0 TEXT "Labels" | 83032,232182 1 0 0 "RxWireDataIn[1:0]"
+I 209 0 130 Builtin InPort | 77032,232182 "" ""
+L 212 213 0 TEXT "Labels" | 82921,227792 1 0 0 "RxWireDataWEn"
+I 213 0 2 Builtin InPort | 76921,227792 "" ""
+I 233 0 130 Builtin Signal | 19714,230494 "" ""
+L 232 233 0 TEXT "Labels" | 22714,230494 1 0 0 "RxBits[1:0]"
+C 231 17 0 TEXT "Conditions" | 33631,208784 1 0 0 "rst"
+L 230 229 0 TEXT "Labels" | 184517,243951 1 0 0 "rst"
+I 229 0 2 Builtin InPort | 178517,243951 "" ""
+I 228 0 3 Builtin InPort | 178182,250843 "" ""
+L 227 228 0 TEXT "Labels" | 184182,250843 1 0 0 "clk"
+A 226 9 4 TEXT "Actions" | 91342,218617 1 0 0 "RXStMachCurrState <= `DISCONNECT_ST;\nRXWaitCount <= 8'h00;\nconnectState <= `DISCONNECT;\nRxBits <= 2'b00;"
+L 234 235 0 TEXT "State Labels" | 170150,83440 1 0 0 "J1"
+S 235 6 65556 ELLIPSE "Junction" | 170150,83440 3500 3500
+H 236 235 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 237 236 0 Builtin Entry | 86360,167640
+I 238 236 0 Builtin Exit | 129540,111760
+W 239 236 0 237 238 BEZIER "Transitions" | 90868,167640 103038,150317 114242,129084 126412,111760
+A 255 194 16 TEXT "Actions" | 77086,121516 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState <= `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;\nend"
+A 252 204 16 TEXT "Actions" | 71150,119778 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXWaitCount <= RXWaitCount + 1'b1;\n  if (RXWaitCount == `DISCONNECT_WAIT_TIME)  \n  begin\n    RXStMachCurrState <= `DISCONNECT_ST;\n    connectState <= `DISCONNECT;\n  end\nend\nelse\nbegin\n  RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;\nend"
+L 240 241 0 TEXT "State Labels" | 55410,143308 1 0 0 "J2"
+S 241 6 69652 ELLIPSE "Junction" | 55410,143308 3500 3500
+H 242 241 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 243 242 0 Builtin Entry | 86360,167640
+I 244 242 0 Builtin Exit | 129540,111760
+W 245 242 0 243 244 BEZIER "Transitions" | 90868,167640 103009,150334 114271,129067 126412,111760
+A 259 169 16 TEXT "Actions" | 77229,121214 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+A 258 183 16 TEXT "Actions" | 76648,132819 1 0 0 "if (RxBits == `SE0)\nbegin\n  RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;\n  RXWaitCount <= 0;\nend"
+L 260 261 0 TEXT "Labels" | 80654,241105 1 0 0 "connectState[1:0]"
+I 261 0 130 Builtin OutPort | 74654,241105 "" ""
+END

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/siereceiver.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/include/timescale.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/include/timescale.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/include/timescale.v	(revision 264)
@@ -0,0 +1,5 @@
+//////////////////////////////////////////////////////////////////////
+// timescale.v                                              
+//////////////////////////////////////////////////////////////////////
+`timescale 1ns / 1ps
+
Index: common/components/usbhostslave/trunk/RTL/include/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/include/usbSerialInterfaceEngine_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/include/usbSerialInterfaceEngine_h.v	(revision 264)
@@ -0,0 +1,109 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v                                
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+`define RX_EDGE_DET_TOUT 7
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+`define TX_LS_KEEP_ALIVE 8'h06
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+// RESUME_RX_WAIT_TIME defines the time period for resume detection
+// The resume counter is incremented at the bit rate, so
+// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
+// and 30 * 1/1.5MHz =  20uS at low speed, both of which are within the USB spec of 
+// 2.5uS <= resumeDetectTime <= 100uS
+`define RESUME_RX_WAIT_TIME 5'd29
+//`define RESUME_WAIT_TIME_MINUS1 9
+// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate 
+`ifdef SIM_COMPILE 
+`define HOST_TX_RESUME_TIME 16'd10
+`else
+`define HOST_TX_RESUME_TIME 16'd30000  //Host sends resume for 30000 * 1/1.5MHz = 20mS
+`endif
+//`define CONNECT_WAIT_TIME 8'd20
+`define CONNECT_WAIT_TIME 8'd120      //Device connect detected after 120 * 1/48MHz = 2.5uS
+//`define DISCONNECT_WAIT_TIME 8'd20   
+`define DISCONNECT_WAIT_TIME 8'd120   //Device disconnect detected after 120 * 1/48MHz = 2.5uS
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+`define DATA_STOP_PRE 8'h04
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates 
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+

Property changes on: common/components/usbhostslave/trunk/RTL/include/usbSerialInterfaceEngine_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.v	(revision 264)
@@ -0,0 +1,717 @@
+
+// File        : ../RTL/serialInterfaceEngine/SIETransmitter.v
+// Generated   : 10/15/06 20:31:22
+// From        : ../RTL/serialInterfaceEngine/SIETransmitter.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIETransmitter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC);
+input   [15:0] CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0] CRC5Result;
+input   CRC5UpdateRdy;
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [7:0] SIEPortCtrlIn;
+input   [7:0] SIEPortDataIn;
+input   SIEPortWEn;
+input   USBWireGnt;
+input   USBWireRdy;
+input   clk;
+input   fullSpeedRateIn;
+input   processTxByteRdy;
+input   rst;
+output  CRC16En;
+output  CRC5En;
+output  CRC5_8Bit;
+output  [7:0] CRCData;
+output  SIEPortTxRdy;
+output  [7:0] TxByteOutCtrl;
+output  TxByteOutFullSpeedRate;
+output  [7:0] TxByteOut;
+output  USBWireCtrl;
+output  [1:0] USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+output  processTxByteWEn;
+output  rstCRC;
+
+reg     CRC16En, next_CRC16En;
+wire    [15:0] CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5En, next_CRC5En;
+wire    [4:0] CRC5Result;
+wire    CRC5UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     [7:0] CRCData, next_CRCData;
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [7:0] SIEPortCtrlIn;
+wire    [7:0] SIEPortDataIn;
+reg     SIEPortTxRdy, next_SIEPortTxRdy;
+wire    SIEPortWEn;
+reg     [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
+reg     TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
+reg     [7:0] TxByteOut, next_TxByteOut;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0] USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+wire    fullSpeedRateIn;
+wire    processTxByteRdy;
+reg     processTxByteWEn, next_processTxByteWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+
+// diagram signals declarations
+reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg  [7:0]SIEPortData, next_SIEPortData;
+reg  [2:0]i, next_i;
+reg  [15:0]resumeCnt, next_resumeCnt;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define DIR_CTL_CHK_FIN 6'b000000
+`define RES_ST_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
+`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
+`define PKT_ST_HS_PKT_SENT 6'b000111
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
+`define PKT_ST_SPCL_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_SND_J_1 6'b001110
+`define RES_ST_SND_J_2 6'b001111
+`define RES_ST_SND_SE0_1 6'b010000
+`define RES_ST_SND_SE0_2 6'b010001
+`define START_SIETX 6'b010010
+`define STX_CHK_ST 6'b010011
+`define STX_WAIT_BYTE 6'b010100
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011001
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011010
+`define DIR_CTL_WAIT_GNT 6'b011011
+`define RES_ST_WAIT_GNT 6'b011100
+`define PKT_ST_HS_WAIT_RDY 6'b011101
+`define DIR_CTL_WAIT_RDY 6'b011110
+`define PKT_ST_SPCL_WAIT_RDY 6'b011111
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100010
+`define RES_ST_WAIT_RDY 6'b100011
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100101
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111
+`define PKT_ST_WAIT_RDY_PKT 6'b101000
+`define RES_ST_W_RDY1 6'b101001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
+`define TX_LS_EOP_WAIT_GNT1 6'b101101
+`define TX_LS_EOP_SND_SE0_2 6'b101110
+`define TX_LS_EOP_SND_SE0_1 6'b101111
+`define TX_LS_EOP_W_RDY1 6'b110000
+`define TX_LS_EOP_SND_J 6'b110001
+`define TX_LS_EOP_W_RDY2 6'b110010
+`define TX_LS_EOP_W_RDY3 6'b110011
+`define RES_ST_DELAY 6'b110100
+`define RES_ST_W_RDY2 6'b110101
+`define RES_ST_W_RDY3 6'b110110
+`define RES_ST_W_RDY4 6'b110111
+`define DIR_CTL_DELAY 6'b111000
+
+reg [5:0] CurrState_SIETx;
+reg [5:0] NextState_SIETx;
+
+
+//--------------------------------------------------------------------
+// Machine: SIETx
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx)
+begin : SIETx_NextState
+  NextState_SIETx <= CurrState_SIETx;
+  // Set default values for outputs and signals
+  next_processTxByteWEn <= processTxByteWEn;
+  next_TxByteOut <= TxByteOut;
+  next_TxByteOutCtrl <= TxByteOutCtrl;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_USBWireReq <= USBWireReq;
+  next_USBWireWEn <= USBWireWEn;
+  next_rstCRC <= rstCRC;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_SIEPortTxRdy <= SIEPortTxRdy;
+  next_SIEPortData <= SIEPortData;
+  next_SIEPortCtrl <= SIEPortCtrl;
+  next_i <= i;
+  next_resumeCnt <= resumeCnt;
+  next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  case (CurrState_SIETx)
+    `IDLE:
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    `START_SIETX:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_TxByteOut <= 8'h00;
+      next_TxByteOutCtrl <= 8'h00;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_SIEPortTxRdy <= 1'b0;
+      next_SIEPortData <= 8'h00;
+      next_SIEPortCtrl <= 8'h00;
+      next_i <= 3'h0;
+      next_resumeCnt <= 16'h0000;
+      next_TxByteOutFullSpeedRate <= 1'b0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `STX_CHK_ST:
+      if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))	
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+        next_TxByteOutFullSpeedRate <= 1'b1;
+        //SOF and PRE always at full speed
+      end
+      else if (SIEPortCtrl == `TX_PACKET_START)	
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+      else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)	
+      begin
+        NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)	
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_IDLE)	
+        NextState_SIETx <= `IDLE;
+      else if (SIEPortCtrl == `TX_RESUME_START)	
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+        next_resumeCnt <= 16'h0000;
+        next_USBWireFullSpeedRate <= 1'b0;
+        //resume always uses low speed timing
+      end
+    `STX_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)	
+      begin
+        NextState_SIETx <= `STX_CHK_ST;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+        next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
+        next_USBWireFullSpeedRate <= fullSpeedRateIn;
+      end
+    end
+    `DIR_CTL_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_i <= i + 1'b1;
+      if (i == 3'h7)	
+      begin
+        NextState_SIETx <= `STX_WAIT_BYTE;
+        next_USBWireReq <= 1'b0;
+      end
+      else
+        NextState_SIETx <= `DIR_CTL_DELAY;
+    end
+    `DIR_CTL_WAIT_GNT:
+    begin
+      next_i <= 3'h0;
+      if (USBWireGnt == 1'b1)	
+        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+    end
+    `DIR_CTL_WAIT_RDY:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `DIR_CTL_CHK_FIN;
+        next_USBWireData <= SIEPortData[1:0];
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `DIR_CTL_DELAY:
+      NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+    `PKT_ST_CHK_PID:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      if (SIEPortData[1:0] == `TOKEN)	
+        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+      else if (SIEPortData[1:0] == `HANDSHAKE)	
+        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+      else if (SIEPortData[1:0] == `DATA)	
+        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+      else if (SIEPortData[1:0] == `SPECIAL)	
+        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+    end
+    `PKT_ST_WAIT_RDY_PKT:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_CHK_PID;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= `SYNC_BYTE;
+        next_TxByteOutCtrl <= `DATA_START;
+      end
+    `PKT_ST_DATA_CRC_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT2:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY1:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[7:0];
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    `PKT_ST_DATA_CRC_WAIT_RDY2:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[15:8];
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    `PKT_ST_DATA_DATA_CHK_STOP:
+      if (SIEPortCtrl == `TX_PACKET_STOP)	
+        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+      else
+        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+    `PKT_ST_DATA_DATA_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_DATA_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC16En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+    end
+    `PKT_ST_DATA_DATA_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_RDY:
+    begin
+      next_CRC16En <= 1'b0;
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+      if (CRC16UpdateRdy == 1'b1)	
+        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+    `PKT_ST_DATA_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_PID_WAIT_RDY:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    `PKT_ST_HS_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_HS_WAIT_RDY:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    `PKT_ST_SPCL_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_SPCL_WAIT_RDY:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        if (SIEPortData[3:0] == `PREAMBLE)
+          next_TxByteOutCtrl <= `DATA_STOP_PRE;
+        else
+          next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    `PKT_ST_TKN_BYTE1_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_BYTE1_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+      if (CRC5UpdateRdy == 1'b1)	
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+    `PKT_ST_TKN_CRC_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_CRC_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+    end
+    `PKT_ST_TKN_CRC_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+      if (CRC5UpdateRdy == 1'b1)	
+        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+    `PKT_ST_TKN_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_PID_WAIT_RDY:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    `RES_ST_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (resumeCnt == `HOST_TX_RESUME_TIME)	
+        NextState_SIETx <= `RES_ST_W_RDY1;
+      else
+        NextState_SIETx <= `RES_ST_DELAY;
+    end
+    `RES_ST_SND_J_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY4;
+    end
+    `RES_ST_SND_J_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+      next_USBWireFullSpeedRate <= fullSpeedRateIn;
+    end
+    `RES_ST_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY2;
+    end
+    `RES_ST_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY3;
+    end
+    `RES_ST_WAIT_GNT:
+      if (USBWireGnt == 1'b1)	
+        NextState_SIETx <= `RES_ST_WAIT_RDY;
+    `RES_ST_WAIT_RDY:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_CHK_FIN;
+        next_USBWireData <= KBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+        next_resumeCnt <= resumeCnt  + 1'b1;
+      end
+    `RES_ST_W_RDY1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `RES_ST_DELAY:
+      NextState_SIETx <= `RES_ST_WAIT_RDY;
+    `RES_ST_W_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `RES_ST_W_RDY3:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `RES_ST_W_RDY4:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_2;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `TX_LS_EOP_WAIT_GNT1:
+      if (USBWireGnt == 1'b1)	
+        NextState_SIETx <= `TX_LS_EOP_W_RDY1;
+    `TX_LS_EOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY3;
+    end
+    `TX_LS_EOP_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY2;
+    end
+    `TX_LS_EOP_W_RDY1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `TX_LS_EOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `TX_LS_EOP_W_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `TX_LS_EOP_W_RDY3:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_J;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SIETx_CurrentState
+  if (rst)	
+    CurrState_SIETx <= `START_SIETX;
+  else
+    CurrState_SIETx <= NextState_SIETx;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SIETx_RegOutput
+  if (rst)	
+  begin
+    SIEPortData <= 8'h00;
+    SIEPortCtrl <= 8'h00;
+    i <= 3'h0;
+    resumeCnt <= 16'h0000;
+    processTxByteWEn <= 1'b0;
+    TxByteOut <= 8'h00;
+    TxByteOutCtrl <= 8'h00;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    USBWireReq <= 1'b0;
+    USBWireWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    SIEPortTxRdy <= 1'b0;
+    TxByteOutFullSpeedRate <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+  end
+  else 
+  begin
+    SIEPortData <= next_SIEPortData;
+    SIEPortCtrl <= next_SIEPortCtrl;
+    i <= next_i;
+    resumeCnt <= next_resumeCnt;
+    processTxByteWEn <= next_processTxByteWEn;
+    TxByteOut <= next_TxByteOut;
+    TxByteOutCtrl <= next_TxByteOutCtrl;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    USBWireReq <= next_USBWireReq;
+    USBWireWEn <= next_USBWireWEn;
+    rstCRC <= next_rstCRC;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    SIEPortTxRdy <= next_SIEPortTxRdy;
+    TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxByte.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxByte.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxByte.asf	(revision 264)
@@ -0,0 +1,297 @@
+VERSION=1.21
+HEADER
+FILE="processRxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxByte"
+FREEOID=384
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processRxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,No Title"
+BLOCKTABLE_FILE=""
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+END
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+A 287 286 4 TEXT "Actions" | 73518,95877 1 0 0 "CRC16En <= 1'b0;\nRxDataOutWEn <= 1'b0;"
+L 303 304 0 TEXT "Labels" | 84462,230495 1 0 0 "RxByteIn[7:0]"
+I 302 0 2 Builtin OutPort | 76139,237545 "" ""
+L 301 302 0 TEXT "Labels" | 82139,237545 1 0 0 "RxDataOutWEn"
+I 300 0 130 Builtin OutPort | 76848,242565 "" ""
+L 299 300 0 TEXT "Labels" | 82848,242565 1 0 0 "RxCtrlOut[7:0]"
+I 298 0 130 Builtin OutPort | 76848,247579 "" ""
+L 297 298 0 TEXT "Labels" | 82848,247579 1 0 0 "RxDataOut[7:0]"
+A 296 0 1 TEXT "Actions" | 13933,252227 1 0 0 "always @\n(next_CRCError or next_bitStuffError or\n next_RxOverflow or next_NAKRxed or \n next_stallRxed or next_ACKRxed or \n next_dataSequence)\nbegin	\n  RxStatus <= \n  {1'b0, next_dataSequence, \n  next_ACKRxed, \n  next_stallRxed, next_NAKRxed, \n  next_RxOverflow, \n  next_bitStuffError, next_CRCError };\nend"
+L 25 24 0 TEXT "State Labels" | 115892,81996 1 0 0 "HSHAKE"
+S 24 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115892,81996 6500 6500
+I 21 17 0 Builtin Exit | 89220,92674
+I 20 17 0 Builtin Entry | 45216,248076
+L 19 18 0 TEXT "State Labels" | 109233,155402 1 0 0 "FIRST_BYTE"
+S 18 17 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 109233,155402 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 16 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115714,110762 6500 6500
+W 288 50 0 293 286 BEZIER "Transitions" | 76852,151619 72082,138383 61585,113663 56815,100427
+L 289 286 0 TEXT "State Labels" | 54701,94283 1 0 0 "FIN\n/11/"
+I 291 50 0 Builtin Exit | 90483,62922
+I 292 50 0 Builtin Entry | 33692,252435
+S 293 50 77824 ELLIPSE "States" | 79792,157415 6500 6500
+L 294 293 0 TEXT "State Labels" | 79792,157415 1 0 0 "CHK_STRM\n/12/"
+A 295 293 4 TEXT "Actions" | 114075,218259 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC16Result != 16'hb001)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    RxDataOut <= RxByte;\n    RxCtrlOut <= `RX_PACKET_STREAM;\n    CRCData <= RxByte;\n    CRC16En <= 1'b1;\n  end\n  default:\n  begin\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 319 320 0 TEXT "Labels" | 130127,218643 1 0 0 "CRC16En"
+I 318 0 2 Builtin OutPort | 123866,228310 "" ""
+L 317 318 0 TEXT "Labels" | 129866,228310 1 0 0 "CRC5_8Bit"
+I 316 0 2 Builtin OutPort | 123509,232929 "" ""
+L 315 316 0 TEXT "Labels" | 129509,232929 1 0 0 "CRC5En"
+I 314 0 130 Builtin InPort | 125655,237903 "" ""
+L 313 314 0 TEXT "Labels" | 131655,237903 1 0 0 "CRC5Result[4:0]"
+I 312 0 130 Builtin OutPort | 123156,242520 "" ""
+L 311 312 0 TEXT "Labels" | 129156,242520 1 0 0 "CRCData[7:0]"
+I 310 0 2 Builtin OutPort | 123515,247488 "" ""
+L 309 310 0 TEXT "Labels" | 129515,247488 1 0 0 "rstCRC"
+I 308 0 2 Builtin InPort | 78462,219728 "" ""
+L 307 308 0 TEXT "Labels" | 85176,219728 1 0 0 "processRxDataInWEn"
+I 306 0 130 Builtin InPort | 78465,225472 "" ""
+L 305 306 0 TEXT "Labels" | 84465,225472 1 0 0 "RxCtrlIn[7:0]"
+I 304 0 130 Builtin InPort | 78462,230495 "" ""
+L 43 42 0 TEXT "State Labels" | 118750,24108 1 0 0 "DATA"
+S 42 6 16388 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118750,24108 6500 6500
+S 40 41 65536 ELLIPSE "States" | 74595,193068 6500 6500
+L 39 40 0 TEXT "State Labels" | 74595,193068 1 0 0 "CHK_STRM\n/9/"
+I 38 41 0 Builtin Entry | 30541,258592
+I 37 41 0 Builtin Exit | 85286,98575
+W 36 41 0 38 371 BEZIER "Transitions" | 34549,258592 38576,254357 47806,246433 31745,235718
+L 34 33 0 TEXT "State Labels" | 117500,51980 1 0 0 "TOKEN"
+S 33 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 117500,51980 6500 6500
+H 41 33 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 32 24 0 RECT 0,0,0 0 0 1 255,255,255 0 | 17144,15700 201644,263700
+L 335 336 0 TEXT "Labels" | 175074,230643 1 0 0 "ACKRxed"
+I 334 0 2 Builtin Signal | 172074,234927 "" ""
+L 333 334 0 TEXT "Labels" | 175074,234927 1 0 0 "stallRxed"
+I 332 0 2 Builtin Signal | 171717,239568 "" ""
+L 331 332 0 TEXT "Labels" | 174717,239568 1 0 0 "NAKRxed"
+I 330 0 2 Builtin Signal | 172074,243852 "" ""
+L 329 330 0 TEXT "Labels" | 175074,243852 1 0 0 "RxTimeOut"
+I 328 0 2 Builtin Signal | 172074,248136 "" ""
+L 327 328 0 TEXT "Labels" | 175074,248136 1 0 0 "RxOverflow"
+I 326 0 2 Builtin Signal | 172074,252420 "" ""
+L 325 326 0 TEXT "Labels" | 175074,252420 1 0 0 "bitStuffError"
+I 324 0 130 Builtin InPort | 126267,223603 "" ""
+L 323 324 0 TEXT "Labels" | 132267,223603 1 0 0 "CRC16Result[15:0]"
+I 320 0 2 Builtin OutPort | 124127,218643 "" ""
+S 63 6 24576 ELLIPSE "States" | 112744,160479 6500 6500
+L 62 63 0 TEXT "State Labels" | 113731,159652 1 0 0 "WAIT_BYTE\n/2/"
+C 58 54 0 TEXT "Conditions" | 46403,18824 1 0 0 "RXByteStMachCurrState == `DATA_BYTE_ST"
+C 57 53 0 TEXT "Conditions" | 45420,45726 1 0 0 "RXByteStMachCurrState == `TOKEN_BYTE_ST"
+C 56 52 0 TEXT "Conditions" | 45596,78180 1 0 0 "RXByteStMachCurrState == `HS_BYTE_ST"
+C 55 51 0 TEXT "Conditions" | 43455,108692 1 0 0 "RXByteStMachCurrState == `CHECK_PID_ST"
+W 54 6 0 11 42 BEZIER "Transitions" | 41669,156431 42607,127755 43130,57608 44403,42064\
+                                      45676,26520 48892,21696 57535,20691 66178,19686\
+                                      96662,22630 112340,23032
+W 53 6 0 11 33 BEZIER "Transitions" | 41642,156408 42044,133896 42058,76100 43264,64442\
+                                      44470,52784 48490,51176 56999,50774 65508,50372\
+                                      95524,50372 103095,50372 110666,50372 111053,50434\
+                                      111187,50434
+W 52 6 0 11 24 BEZIER "Transitions" | 41273,156415 41809,142881 41924,101426 42929,93654\
+                                      43934,85882 46882,81862 55190,80924 63498,79986\
+                                      93782,80254 101420,80321 109058,80388 109445,80450\
+                                      109579,80450
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,156419 41353,150657 41254,124742 41790,120856\
+                                      42326,116970 44202,112950 52711,111811 61220,110672\
+                                      93136,110915 109216,110647
+H 50 42 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 340 0 128 Builtin Signal | 172498,216552 "" ""
+L 339 340 0 TEXT "Labels" | 175498,216552 1 0 0 "RxStatus[7:0]"
+W 351 6 0 357 63 BEZIER "Transitions" | 165899,75618 165621,78724 166582,88726 164321,92532\
+                                        162060,96338 152965,99917 149770,102482 146575,105047\
+                                        142560,111540 140625,118020 138690,124500 135270,144660\
+                                        132480,150150 129690,155640 122852,157755 118982,158655
+A 349 9 4 TEXT "Actions" | 143783,194927 1 0 0 "RxByte <= 8'h00;\nRxCtrl <= 8'h00;\nRXByteStMachCurrState <= `IDLE_BYTE_ST;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nRxTimeOut <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxDataOut <= 8'h00;\nRxCtrlOut <= 8'h00;\nRxDataOutWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nRXDataByteCnt <= 10'h00;\nprocessRxByteRdy <= 1'b1;"
+I 346 0 130 Builtin Signal | 116382,203511 "" ""
+L 345 346 0 TEXT "Labels" | 119382,203511 1 0 0 "RXByteStMachCurrState[2:0]"
+I 344 0 130 Builtin Signal | 172286,208921 "" ""
+L 343 344 0 TEXT "Labels" | 175286,208921 1 0 0 "RxCtrl[7:0]"
+I 342 0 130 Builtin Signal | 171929,203923 "" ""
+L 341 342 0 TEXT "Labels" | 174929,203923 1 0 0 "RxByte[7:0]"
+I 338 0 2 Builtin Signal | 172074,226002 "" ""
+L 337 338 0 TEXT "Labels" | 175074,226002 1 0 0 "dataSequence"
+I 336 0 2 Builtin Signal | 172074,230643 "" ""
+A 78 65 16 TEXT "Actions" | 51039,169927 1 0 0 "RxByte <= RxByteIn;\nRxCtrl <= RxCtrlIn;\nprocessRxByteRdy <= 1'b0;"
+W 76 17 8194 75 18 BEZIER "Transitions" | 69849,207737 75657,200807 99461,167483 105269,160553
+S 75 17 45056 ELLIPSE "States" | 65748,212778 6500 6500
+L 74 75 0 TEXT "State Labels" | 65748,212778 1 0 0 "DO_CHK\n/5/"
+W 72 6 0 42 357 BEZIER "Transitions" | 123133,28907 132448,39032 153635,59470 162950,69595
+W 71 6 0 33 357 BEZIER "Transitions" | 123360,54790 132540,58705 152828,67124 162008,71039
+W 69 6 0 24 357 BEZIER "Transitions" | 122281,80803 131596,78778 152599,74997 161914,72972
+W 68 6 0 16 357 BEZIER "Transitions" | 120926,106881 130781,99051 152663,82096 162518,74266
+C 66 65 0 TEXT "Conditions" | 62843,155863 1 0 0 "processRxDataInWEn == 1'b1"
+W 65 6 0 63 11 BEZIER "Transitions" | 106255,160115 94419,158098 59763,166047 47927,164030
+W 64 6 0 9 63 BEZIER "Transitions" | 48012,184711 59579,183097 95649,168804 106856,163230
+I 367 0 2 Builtin Signal | 77453,208858 "" ""
+L 366 367 0 TEXT "Labels" | 80453,208858 1 0 0 "Signal1"
+I 355 0 130 Builtin Signal | 77612,203504 "" ""
+L 354 355 0 TEXT "Labels" | 80612,203504 1 0 0 "RXDataByteCnt[9:0]"
+I 353 0 2 Builtin Signal | 172356,221968 "" ""
+L 352 353 0 TEXT "Labels" | 175356,221968 1 0 0 "CRCError"
+W 81 17 0 20 75 BEZIER "Transitions" | 49078,248076 53138,241189 58262,225186 62322,218299
+W 82 17 4097 75 21 BEZIER "Transitions" | 63199,206800 60009,197085 40708,156469 41288,147696\
+                                          41868,138924 51896,113272 59871,108777 67846,104282\
+                                          74994,97474 86594,92674
+L 356 357 0 TEXT "State Labels" | 165320,72170 1 0 0 "J1"
+S 357 6 81940 ELLIPSE "Junction" | 165320,72170 3500 3500
+H 358 357 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 359 358 0 Builtin Entry | 86360,167640
+I 360 358 0 Builtin Exit | 129540,111760
+W 361 358 0 359 360 BEZIER "Transitions" | 90523,167640 102693,150317 114474,129084 126644,111760
+C 380 379 0 TEXT "Conditions" | 39560,213610 1 0 0 "CRC16UpdateRdy == 1'b1"
+W 379 50 0 377 293 BEZIER "Transitions" | 76802,222169 77769,207119 78297,178932 79264,163882
+W 378 50 0 292 377 BEZIER "Transitions" | 37700,252435 46407,247168 62458,237581 71165,232314
+S 377 50 90112 ELLIPSE "States" | 76540,228660 6500 6500
+L 376 377 0 TEXT "State Labels" | 76540,228660 1 0 0 "WAIT_CRC\n/14/"
+I 375 0 2 Builtin InPort | 126404,209416 "" ""
+L 374 375 0 TEXT "Labels" | 132404,209416 1 0 0 "CRC16UpdateRdy"
+C 373 372 0 TEXT "Conditions" | 40381,225556 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 372 41 0 371 40 BEZIER "Transitions" | 35330,224745 46935,215765 58540,206785 70145,197805
+S 371 41 86016 ELLIPSE "States" | 30702,229308 6500 6500
+L 370 371 0 TEXT "State Labels" | 30702,229308 1 0 0 "WAIT_CRC\n/13/"
+I 369 0 2 Builtin InPort | 126404,214168 "" ""
+L 368 369 0 TEXT "Labels" | 132404,214168 1 0 0 "CRC5UpdateRdy"
+L 381 382 0 TEXT "Labels" | 84990,214964 1 0 0 "processRxByteRdy"
+I 382 0 2 Builtin OutPort | 78990,214964 "" ""
+A 383 351 16 TEXT "Actions" | 154286,95504 1 0 0 "processRxByteRdy <= 1'b1;"
+A 162 40 4 TEXT "Actions" | 109188,255837 1 0 0 "RXDataByteCnt <= RXDataByteCnt + 1'b1;\ncase (RxCtrl)\n  `DATA_STOP:\n  begin\n    if (CRC5Result != 5'h6)\n      CRCError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_BIT_STUFF_ERROR:\n  begin\n    bitStuffError <= 1'b1;\n    RxDataOut <= RxStatus;\n    RxCtrlOut <= `RX_PACKET_STOP;\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\n  `DATA_STREAM:\n  begin\n    if (RXDataByteCnt > 10'h2) \n    begin\n      RxOverflow <= 1'b1;\n      RxDataOut <= RxStatus;\n      RxCtrlOut <= `RX_PACKET_STOP;\n      RXByteStMachCurrState <= `IDLE_BYTE_ST;\n    end\n    else \n    begin\n      RxDataOut <= RxByte;\n      RxCtrlOut <= `RX_PACKET_STREAM;\n      CRCData <= RxByte;\n      CRC5_8Bit <= 1'b1;\n      CRC5En <= 1'b1;\n    end\n  end \n  default:\n  begin\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  end\nendcase\nRxDataOutWEn <= 1'b1;"
+L 184 185 0 TEXT "Labels" | 161048,252716 1 0 0 "clk"
+I 185 0 3 Builtin InPort | 155048,252716 "" ""
+L 186 187 0 TEXT "Labels" | 160691,247662 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 154691,247662 "" ""
+C 188 13 0 TEXT "Conditions" | 25531,188745 1 0 0 "rst"
+W 223 217 4096 218 221 BEZIER "Transitions" | 111743,134422 116788,127400 128768,96077 133814,89055
+W 222 217 0 220 218 BEZIER "Transitions" | 90523,167640 95262,160652 99562,152068 104302,145079
+I 221 217 0 Builtin Exit | 136710,89055
+I 220 217 0 Builtin Entry | 86360,167640
+L 219 218 0 TEXT "State Labels" | 107950,139700 1 0 0 "CHK_START\n/3/"
+S 218 217 36864 ELLIPSE "States" | 107950,139700 6500 6500
+H 217 216 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 216 6 32772 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113402,144340 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,144340 1 0 0 "IDLE"
+S 213 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,127848 6500 6500
+L 212 213 0 TEXT "State Labels" | 113934,129450 1 0 0 "CHK_SYNC"
+W 236 6 0 213 357 BEZIER "Transitions" | 118353,123082 128966,111334 152340,86494 162953,74746
+W 235 6 0 216 357 BEZIER "Transitions" | 117419,139231 129033,122944 151793,91387 163407,75100
+C 234 231 0 TEXT "Conditions" | 42504,140676 1 0 0 "RXByteStMachCurrState == `IDLE_BYTE_ST"
+C 233 232 0 TEXT "Conditions" | 41970,122520 1 0 0 "RXByteStMachCurrState == `CHECK_SYNC_ST"
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,156411 41443,149937 41370,137271 41770,133433\
+                                        42170,129596 43639,127192 51882,126624 60126,126057\
+                                        91699,127301 107452,127367
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,156431 41386,153761 41370,148419 41770,146583\
+                                        42170,144748 43639,142745 51849,142311 60059,141877\
+                                        91249,143561 106935,143694
+W 230 224 0 225 228 BEZIER "Transitions" | 111743,134422 116788,127400 121803,118782 126849,111760
+W 229 224 0 227 225 BEZIER "Transitions" | 90396,167640 95135,160652 99562,152068 104302,145079
+I 228 224 0 Builtin Exit | 129540,111760
+I 227 224 0 Builtin Entry | 86360,167640
+L 226 225 0 TEXT "State Labels" | 107950,139700 1 0 0 "DO\n/4/"
+S 225 224 40960 ELLIPSE "States" | 107950,139700 6500 6500
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 255 248 0 249 253 BEZIER "Transitions" | 60789,195800 65743,188968 70713,179952 75668,173120
+W 254 248 0 252 249 BEZIER "Transitions" | 39547,229000 44083,222216 48824,213248 53361,206463
+I 253 248 0 Builtin Exit | 78564,173120
+I 252 248 0 Builtin Entry | 35384,229000
+A 251 249 4 TEXT "Actions" | 92522,232212 1 0 0 "rstCRC <= 1'b0;\nRxDataOutWEn <= 1'b0;\ncase (RxByte[1:0] )\n  `SPECIAL:                              //Special PID.\n    RXByteStMachCurrState <= `IDLE_BYTE_ST;\n  `TOKEN:                                //Token PID\n  begin\n    RXByteStMachCurrState <= `TOKEN_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\n  `HANDSHAKE:                            //Handshake PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        ACKRxed <= 1'b1;\n      2'b10:\n        NAKRxed <= 1'b1;\n      2'b11:\n        stallRxed <= 1'b1;\n      default:\n      begin\n        $display (\"Invalid Handshake PID detected in ProcessRXByte\\n\");\n      end\n    endcase\n    RXByteStMachCurrState <= `HS_BYTE_ST;\n  end\n  `DATA:                                  //Data PID\n  begin\n    case (RxByte[3:2] )\n      2'b00:\n        dataSequence <= 1'b0;\n      2'b10:\n        dataSequence <= 1'b1;\n      default:\n        $display (\"Invalid DATA PID detected in ProcessRXByte\\n\");\n    endcase\n    RXByteStMachCurrState <= `DATA_BYTE_ST;\n    RXDataByteCnt <= 0;\n  end\nendcase"
+L 250 249 0 TEXT "State Labels" | 56974,201060 1 0 0 "PROC\n/6/"
+S 249 248 53248 ELLIPSE "States" | 56974,201060 6500 6500
+H 248 18 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+A 245 76 16 TEXT "Actions" | 83312,221127 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0;\nRxOverflow <= 1'b0;\nNAKRxed <= 1'b0;\nstallRxed <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxTimeOut <= 1'b0;\nRXDataByteCnt <= 10'h000;\nRxDataOut <= RxByte;\nRxCtrlOut <= `RX_PACKET_START;\nRxDataOutWEn <= 1'b1;\nrstCRC <= 1'b1;"
+A 244 82 16 TEXT "Actions" | 20263,162000 1 0 0 "RXByteStMachCurrState <= `IDLE_BYTE_ST ;"
+C 243 82 0 TEXT "Conditions" | 20905,184375 1 0 0 "(RxByte[7:4] ^ RxByte[3:0] ) != 4'hf"
+A 242 218 4 TEXT "Actions" | 127244,141208 1 0 0 "if (RxCtrl == `DATA_START)\n  RXByteStMachCurrState <= `CHECK_SYNC_ST;"
+A 240 225 4 TEXT "Actions" | 124532,142082 1 0 0 "if (RxByte == `SYNC_BYTE)\n  RXByteStMachCurrState <= `CHECK_PID_ST;\nelse\n  RXByteStMachCurrState <= `IDLE_BYTE_ST;"
+W 256 17 0 18 21 BEZIER "Transitions" | 106988,149304 107171,135945 97823,112446 93593,107407\
+                                        89364,102368 89220,95212 89220,94846
+S 257 32 57344 ELLIPSE "States" | 129646,141752 5778 5778
+L 258 257 0 TEXT "State Labels" | 129668,142146 1 0 0 "FIN\n/7/"
+I 259 32 0 Builtin Entry | 66351,233704
+I 260 32 0 Builtin Exit | 110355,78302
+S 261 32 61440 ELLIPSE "States" | 86883,198406 6500 6500
+L 262 261 0 TEXT "State Labels" | 86883,198406 1 0 0 "CHK\n/8/"
+W 263 32 4096 261 257 BEZIER "Transitions" | 90984,193365 96792,186435 120426,153343 126234,146413
+W 265 32 0 259 261 BEZIER "Transitions" | 70514,233704 74574,226817 79397,210814 83457,203927
+A 268 263 16 TEXT "Actions" | 100115,177875 1 0 0 "if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error\n  RxOverflow <= 1'b1;\nRxDataOut <= RxStatus;\nRxCtrlOut <= `RX_PACKET_STOP;\nRxDataOutWEn <= 1'b1;"
+W 269 32 0 257 260 BEZIER "Transitions" | 128387,136115 128570,122756 118958,98074 114728,93035\
+                                          110499,87996 110355,80840 110355,80474
+END

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/readUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/readUSBWireData.v	(revision 264)
@@ -0,0 +1,274 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// readUSBWireData.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////      This module reads data from the differential USB data lines
+////      and writes into a 4 entry FIFO. The data is read from
+////      the fifo and output from the module when the higher level
+////      state machine is ready to receive the data.
+////      This module must recover the clock phase from the incoming
+////      USB data. 'sampleCnt' is reset to zero whenever a RX data
+////      edge is detected. Note that due to metastability the data
+////      at the edge may not be registered correctly, but this does
+////      not matter. All that matters is that an edge was detected. The
+////      data will be accurately sampled in the middle of the USB bit 
+////      period without metastability issues. 
+////      After the edge detect, 'sampleCnt' is incremented at every clock
+////      tick, and when it indicates the middle of a USB bit period
+////      the RX data is sampled and written to the input buffer.
+////      Single clock tick adjustments to 'sampleCnt' can be made at 
+////      every RX data edge detect without double sampling the incoming
+////      data. However, the first RX data bit in a packet may cause 
+////      'sampleCnt' to be adjusted by a value greater than a single 
+////      clock tick, and this can result in double sampling of the 
+////      first data bit a RX packet. This 
+////      double sampled data must be rejected by the higher level module.
+////      This is achieved by 
+////      qualifying the outgoing data with 'RxWireActive'. Thus 
+////      the first data bit in a RX packet may be double sampled
+////      as the clock recovery mechanism synchronizes to 'RxBitsIn'
+////      but the double sampled data will be rejected by the higher 
+////      level module.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable);
+input   [1:0] RxBitsIn;
+output  RxDataInTick;
+input   SIERxRdyIn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+input   TxWireActiveDrive;
+output  [1:0] RxBitsOut;
+output  SIERxWEn;
+output noActivityTimeOut;
+output RxWireActive;
+input  noActivityTimeOutEnable;
+
+wire   [1:0] RxBitsIn;
+reg    RxDataInTick;
+wire   SIERxRdyIn;
+wire   clk;
+wire   fullSpeedRate;
+wire   rst;
+reg    [1:0] RxBitsOut;
+reg    SIERxWEn;
+reg    noActivityTimeOut;
+reg    RxWireActive;
+wire   noActivityTimeOutEnable;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]sampleCnt;
+reg incBufferCnt;
+reg  [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg [7:0] rxActiveCnt;
+reg RxWireEdgeDetect;
+reg RxWireActiveReg;
+reg RxWireActiveReg2;
+reg [1:0] RxBitsInSyncReg1;
+reg [1:0] RxBitsInSyncReg2;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+// re-synchronize incoming bits
+always @(posedge clk) begin
+  RxBitsInSyncReg1 <= RxBitsIn;
+  RxBitsInSyncReg2 <= RxBitsInSyncReg1;
+end
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    sampleCnt <= 5'b00000;
+    incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    RxDataInTick <= 1'b0;
+    RxWireEdgeDetect <= 1'b0;
+    RxWireActiveReg <= 1'b0;
+    RxWireActiveReg2 <= 1'b0;
+  end
+  else begin
+    RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
+    RxBitsInReg <= RxBitsInSyncReg2;    
+    oldRxBitsIn <= RxBitsInReg;
+    incBufferCnt <= 1'b0;         //default value
+    if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin  //if edge detected then
+      sampleCnt <= 5'b00000;        
+      RxWireEdgeDetect <= 1'b1;   // flag receive activity 
+      RxWireActiveReg <= 1'b1;
+      rxActiveCnt <= 8'h00;
+    end
+    else begin
+      sampleCnt <= sampleCnt + 1'b1;
+      RxWireEdgeDetect <= 1'b0;
+      rxActiveCnt <= rxActiveCnt + 1'b1;
+      //clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods 
+      if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE)
+        || (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) ) 
+        RxWireActiveReg <= 1'b0;
+    end
+    if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) )
+    begin
+      RxDataInTick <= !RxDataInTick;
+      if (TxWireActiveDrive != 1'b1)  //do not read wire data when transmitter is active
+      begin
+        incBufferCnt <= 1'b1;
+        bufferInIndex <= bufferInIndex + 1'b1;
+        case (bufferInIndex)
+          2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn}; 
+          2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn};
+          2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn};
+          2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn};
+        endcase
+      end
+    end
+  end
+end
+
+        
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    decBufferCnt <= 1'b0;
+    bufferOutIndex <= 2'b00;
+    RxBitsOut <= 2'b00;
+    SIERxWEn <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+  end
+  else begin
+    case (bufferOutStMachCurrState)
+      `WAIT_BUFFER_NOT_EMPTY:
+      begin
+        if (bufferCnt != 3'b000)
+          bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+      end
+      `WAIT_SIE_RX_READY:
+      begin
+        if (SIERxRdyIn == 1'b1)
+        begin 
+          SIERxWEn <= 1'b1;
+          bufferOutStMachCurrState <= `SIE_RX_WRITE;
+          decBufferCnt <= 1'b1;
+          bufferOutIndex <= bufferOutIndex + 1'b1;
+          case (bufferOutIndex)
+            2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
+            2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
+            2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
+            2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
+          endcase
+        end
+      end
+      `SIE_RX_WRITE:
+      begin
+        SIERxWEn <= 1'b0;
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+      end
+    endcase
+  end
+end
+
+//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods
+//'noActivityTimeOut'  pulse can only be generated when the host or slave getPacket
+//process enables via 'noActivityTimeOutEnable' signal
+//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if 
+//there has been a response time out.
+always @(posedge clk) begin
+  if (rst) begin
+    timeOutCnt <= 16'h0000;
+    noActivityTimeOut <= 1'b0;
+  end
+  else begin
+    if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0)
+      timeOutCnt <= 16'h0000;
+    else
+      timeOutCnt <= timeOutCnt + 1'b1;
+    if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+      || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) ) 
+      noActivityTimeOut <= 1'b1; 
+    else 
+      noActivityTimeOut <= 1'b0;
+  end
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/readUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/updateCRC5.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/updateCRC5.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/updateCRC5.v	(revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC5.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   CRC5_8BitIn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [4:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   CRC5_8BitIn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 5'h1f;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0) begin
+      if (CRCEn == 1'b1) begin
+        ready <= 1'b0;
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        if (CRC5_8BitIn == 1'b1) begin
+          loopEnd <= 4'h7; 
+        end
+        else begin
+          loopEnd <= 4'h2;
+        end
+      end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[4:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == loopEnd) begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/updateCRC5.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/writeUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/writeUSBWireData.v	(revision 264)
@@ -0,0 +1,289 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// writeUSBWireData.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL  3'b100
+
+module writeUSBWireData (
+  TxBitsIn, 
+  TxBitsOut,
+   TxDataOutTick,
+  TxCtrlIn, 
+  TxCtrlOut, 
+  USBWireRdy,
+  USBWireWEn, 
+  TxWireActiveDrive, 
+  fullSpeedRate, 
+  clk, 
+  rst
+   );
+  
+input   [1:0] TxBitsIn;
+input   TxCtrlIn;
+input   USBWireWEn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+output  [1:0] TxBitsOut;
+output TxDataOutTick;
+output  TxCtrlOut;
+output  USBWireRdy;
+output  TxWireActiveDrive;
+
+wire    [1:0] TxBitsIn;
+reg     [1:0] TxBitsOut;
+reg     TxDataOutTick;
+wire    TxCtrlIn;
+reg     TxCtrlOut;
+reg     USBWireRdy;
+wire    USBWireWEn;
+wire    clk;
+wire    fullSpeedRate;
+wire    rst;
+reg     TxWireActiveDrive;
+
+// local registers
+reg  [3:0]buffer0;
+reg  [3:0]buffer1;
+reg  [3:0]buffer2;
+reg  [3:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+reg fullSpeedRate_reg;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else
+  begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+//buffer input state machine 
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+     incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 4'b0000;
+    buffer1 <= 4'b0000;
+    buffer2 <= 4'b0000;
+    buffer3 <= 4'b0000;
+    USBWireRdy <= 1'b0;
+    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+  end
+  else begin
+    case (bufferInStMachCurrState)
+      `WAIT_BUFFER_NOT_FULL:
+      begin
+        if (bufferCnt != `BUFFER_FULL)  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+      end
+      `WAIT_WRITE_REQ:
+      begin
+        if (USBWireWEn == 1'b1)
+        begin
+          incBufferCnt <= 1'b1;
+          USBWireRdy <= 1'b0;
+          bufferInIndex <= bufferInIndex + 1'b1;
+          case (bufferInIndex)
+            2'b00 : buffer0 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
+            2'b01 : buffer1 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
+            2'b10 : buffer2 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
+            2'b11 : buffer3 <= {fullSpeedRate, TxBitsIn, TxCtrlIn};
+          endcase
+          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+        end
+      end
+      `CLR_INC_BUFFER_CNT:
+      begin
+        incBufferCnt <= 1'b0;
+        if (bufferCnt != (`BUFFER_FULL - 1'b1) )  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+        else begin
+          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+        end
+      end
+    endcase
+  end
+end
+        
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    fullSpeedTick <= 1'b0;
+    lowSpeedTick <= 1'b0;
+  end
+  else
+  begin
+    i <= i + 1'b1;
+    if (i[1:0] == 2'b00)
+      fullSpeedTick <= 1'b1;
+    else
+      fullSpeedTick <= 1'b0; 
+    if (i == 5'b00000)
+      lowSpeedTick <= 1'b1;
+    else
+      lowSpeedTick <= 1'b0;
+  end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferOutIndex <= 2'b00;
+    decBufferCnt <= 1'b0;
+    TxBitsOut <= 2'b00;
+    TxCtrlOut <= `TRI_STATE;
+    TxDataOutTick <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+    fullSpeedRate_reg <= 1'b0;
+  end
+  else
+  begin
+    case (bufferOutIndex)
+      2'b00: fullSpeedRate_reg <= buffer0[3];
+      2'b01: fullSpeedRate_reg <= buffer1[3];
+      2'b10: fullSpeedRate_reg <= buffer2[3];
+      2'b11: fullSpeedRate_reg <= buffer3[3];
+    endcase
+    case (bufferOutStMachCurrState)
+      `WAIT_LINE_WRITE:
+      begin
+        if ((fullSpeedRate_reg == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate_reg == 1'b0 && lowSpeedTick == 1'b1) )
+        begin
+          TxDataOutTick <= !TxDataOutTick;
+          if (bufferCnt == 0) begin
+            TxBitsOut <= 2'b00;
+            TxCtrlOut <= `TRI_STATE;
+          end
+          else begin
+            bufferOutStMachCurrState <= `LINE_WRITE;
+            decBufferCnt <= 1'b1;
+            bufferOutIndex <= bufferOutIndex + 1'b1;
+            case (bufferOutIndex)
+              2'b00 :
+            begin 
+              TxBitsOut <= buffer0[2:1];
+              TxCtrlOut <= buffer0[0];
+            end
+            2'b01 : 
+            begin
+              TxBitsOut <= buffer1[2:1];
+              TxCtrlOut <= buffer1[0];
+            end
+            2'b10 : 
+            begin 
+              TxBitsOut <= buffer2[2:1];
+              TxCtrlOut <= buffer2[0];
+            end
+            2'b11 : 
+            begin
+              TxBitsOut <= buffer3[2:1];
+              TxCtrlOut <= buffer3[0];
+            end
+            endcase
+          end
+        end
+      end
+      `LINE_WRITE:
+      begin
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+      end
+    endcase
+  end
+end
+
+// control 'TxWireActiveDrive' 
+always @(TxCtrlOut)
+begin  
+  if (TxCtrlOut == `DRIVE)
+    TxWireActiveDrive <= 1'b1;
+  else
+    TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/writeUSBWireData.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/sctxportarbiter.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/sctxportarbiter.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/sctxportarbiter.asf	(revision 264)
@@ -0,0 +1,115 @@
+VERSION=1.21
+HEADER
+FILE="sctxportarbiter.asf"
+FID=405ea588
+LANGUAGE=VERILOG
+ENTITY="SCTxPortArbiter"
+FREEOID=101
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SCTxPortArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,No Title"
+BLOCKTABLE_FILE=""
+BLOCKTABLE_TEMPL="0"
+BLOCKTABLE_VISIBLE="1"
+END
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+B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0
+END
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+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 97950,530400 1 0 0 "Module: SCTxPortArbiter"
+F 6 0 671089152 41 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 138680,265200 323180,400245
+L 7 6 0 TEXT "Labels" | 153720,386820 1 0 0 "SCTxArb"
+S 8 6 12288 ELLIPSE "States" | 225591,382670 6500 6500
+L 9 8 0 TEXT "State Labels" | 225591,382670 1 0 0 "START_SARB\n/3/"
+S 10 6 0 ELLIPSE "States" | 224972,352339 6500 6500
+L 11 10 0 TEXT "State Labels" | 224972,350953 1 0 0 "SARB1_WAIT_REQ\n/0/"
+S 14 6 4096 ELLIPSE "States" | 269063,283692 6500 6500
+L 15 14 0 TEXT "State Labels" | 269063,283692 1 0 0 "SARB_SEND_PACKET\n/1/"
+I 16 6 0 Builtin Reset | 178237,383010
+W 17 6 0 16 8 BEZIER "Transitions" | 178237,383010 187522,379237 210185,378778 219470,380486
+W 18 6 0 8 10 BEZIER "Transitions" | 225224,376194 225070,371714 224938,363311 224784,358831
+W 19 6 4097 10 14 BEZIER "Transitions" | 229757,347941 236477,342379 258220,303210 265438,289087
+C 22 19 0 TEXT "Conditions" | 235353,345815 1 0 0 "sendPacketReq == 1'b1"
+A 23 19 16 TEXT "Actions" | 233291,327240 1 0 0 "sendPacketGnt <= 1'b1;\nmuxDCEn <= 1'b0;"
+A 25 8 2 TEXT "Actions" | 234434,398687 1 0 0 "sendPacketGnt <= 1'b0;\ndirectCntlGnt <= 1'b0;\nmuxDCEn <= 1'b0;"
+C 26 17 0 TEXT "Conditions" | 202073,378708 1 0 0 "rst"
+W 27 6 0 14 10 BEZIER "Transitions" | 272129,289421 294143,309321 288020,333532 288403,340102\
+                                      288786,346672 287077,358761 282417,364209 277757,369657\
+                                      274547,368787 268775,368864 263003,368942 254872,368666\
+                                      248267,366271 241663,363877 234289,358857 230118,356308
+C 31 27 0 TEXT "Conditions" | 272024,302471 1 0 0 "sendPacketReq == 1'b0"
+A 32 27 16 TEXT "Actions" | 268756,358479 1 0 0 "sendPacketGnt <= 1'b0;"
+I 35 0 2 Builtin OutPort | 164373,445096 "" ""
+L 36 35 0 TEXT "Labels" | 170373,445096 1 0 0 "SCTxPortWEnable"
+I 37 0 2 Builtin OutPort | 164033,473151 "" ""
+L 38 37 0 TEXT "Labels" | 170033,473151 1 0 0 "sendPacketGnt"
+I 39 0 2 Builtin InPort | 189447,529426 "" ""
+L 40 39 0 TEXT "Labels" | 195447,529426 1 0 0 "rst"
+I 41 0 3 Builtin InPort | 190061,523882 "" ""
+I 42 0 2 Builtin InPort | 166566,450081 "" ""
+L 43 42 0 TEXT "Labels" | 172566,450081 1 0 0 "SCTxPortRdyIn"
+I 44 0 130 Builtin InPort | 166169,486799 "" ""
+L 45 44 0 TEXT "Labels" | 172169,486799 1 0 0 "sendPacketData[7:0]"
+I 52 0 2 Builtin InPort | 165981,477939 "" ""
+L 53 52 0 TEXT "Labels" | 171981,477939 1 0 0 "sendPacketWEn"
+A 54 0 1 TEXT "Actions" | 21871,406257 1 0 0 "// SOFController/directContol/sendPacket mux\nalways @(SCTxPortRdyIn)\nbegin\n  SCTxPortRdyOut <= SCTxPortRdyIn;\nend\n	  \nalways @(muxDCEn or\n		 directCntlWEn or directCntlData or directCntlCntl or\n         directCntlWEn or directCntlData or directCntlCntl or\n 		 sendPacketWEn or sendPacketData or sendPacketCntl)\nbegin\nif (muxDCEn == 1'b1)\n  begin  \n    SCTxPortWEnable <= directCntlWEn;\n    SCTxPortData <= directCntlData;\n    SCTxPortCntl <= directCntlCntl;\n  end\nelse\n  begin  \n    SCTxPortWEnable <= sendPacketWEn;\n    SCTxPortData <= sendPacketData;\n    SCTxPortCntl <= sendPacketCntl;\n  end\nend"
+I 56 0 2 Builtin InPort | 166286,468363 "" ""
+L 57 56 0 TEXT "Labels" | 172286,468363 1 0 0 "sendPacketReq"
+I 58 0 130 Builtin OutPort | 164296,440578 "" ""
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+L 61 41 0 TEXT "Labels" | 196061,523882 1 0 0 "clk"
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+L 63 62 0 TEXT "Labels" | 172256,482420 1 0 0 "sendPacketCntl[7:0]"
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+L 65 64 0 TEXT "Labels" | 170048,454434 1 0 0 "SCTxPortRdyOut"
+I 66 0 130 Builtin OutPort | 164124,458856 "" ""
+L 67 66 0 TEXT "Labels" | 170124,458856 1 0 0 "SCTxPortCntl[7:0]"
+I 78 0 2 Builtin OutPort | 117944,444360 "" ""
+L 79 78 0 TEXT "Labels" | 123944,444360 1 0 0 "directCntlGnt"
+I 80 0 2 Builtin InPort | 120331,439767 "" ""
+L 81 80 0 TEXT "Labels" | 126331,439767 1 0 0 "directCntlReq"
+I 82 0 2 Builtin InPort | 120527,449241 "" ""
+L 83 82 0 TEXT "Labels" | 126527,449241 1 0 0 "directCntlWEn"
+I 84 0 130 Builtin InPort | 120256,458649 "" ""
+L 85 84 0 TEXT "Labels" | 126256,458649 1 0 0 "directCntlData[7:0]"
+I 86 0 130 Builtin InPort | 120356,454026 "" ""
+L 87 86 0 TEXT "Labels" | 126356,454026 1 0 0 "directCntlCntl[7:0]"
+L 88 89 0 TEXT "Labels" | 144050,516112 1 0 0 "muxDCEn"
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+A 98 96 16 TEXT "Actions" | 290172,277428 1 0 0 "directCntlGnt <= 1'b0;"
+END

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/sctxportarbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/slaveGetpacket.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/slaveGetpacket.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/slaveGetpacket.asf	(revision 264)
@@ -0,0 +1,292 @@
+VERSION=1.15
+HEADER
+FILE="slaveGetpacket.asf"
+FID=406f8b6a
+LANGUAGE=VERILOG
+ENTITY="slaveGetPacket"
+FRAMES=ON
+FREEOID=294
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveGetPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
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+END
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+END
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+                                           58879,216350 75631,224113 84458,228187
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+S 15 6 65536 ELLIPSE "States" | 139950,113336 6500 6500
+L 14 15 0 TEXT "State Labels" | 139950,113336 1 0 0 "CHK_PKT_START\n/14/"
+S 11 6 61440 ELLIPSE "States" | 103150,148136 6500 6500
+L 10 11 0 TEXT "State Labels" | 103150,148136 1 0 0 "WAIT_PKT\n/13/"
+S 9 6 57344 ELLIPSE "States" | 74582,196764 6500 6500
+L 8 9 0 TEXT "State Labels" | 74582,196764 1 0 0 "START_GP\n/12/"
+L 7 6 0 TEXT "Labels" | 19389,212093 1 0 0 "slvGetPkt"
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+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 97950,263700 1 0 0 "Module: slaveGetPacket"
+L 284 285 0 TEXT "Labels" | 166910,243470 1 0 0 "endPointReady"
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+S 287 120 94208 ELLIPSE "States" | 167860,243800 6500 6500
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+A 30 23 4 TEXT "Actions" | 121604,190544 1 0 0 "RXPacketRdy <= 1'b0;\nSIERxTimeOutEn <= 1'b0;"
+C 26 25 0 TEXT "Conditions" | 87910,175600 1 0 0 "getPacketEn == 1'b1"
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+A 108 104 16 TEXT "Actions" | 70336,179814 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 107 105 0 TEXT "Conditions" | 86926,150786 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 106 104 0 TEXT "Conditions" | 83294,185177 1 0 0 "RXDataValid == 1'b1"
+W 105 72 8193 100 102 BEZIER "Transitions" | 82387,152177 82612,147893 83278,140540 83503,136256
+W 104 72 0 91 100 BEZIER "Transitions" | 78991,183628 79329,179569 80970,169186 81308,165127
+L 103 102 0 TEXT "State Labels" | 84190,129796 1 0 0 "W_D3\n/7/"
+S 102 72 32768 ELLIPSE "States" | 84190,129796 6500 6500
+L 101 100 0 TEXT "State Labels" | 81935,158660 1 0 0 "CHK_D2\n/6/"
+S 100 72 28672 ELLIPSE "States" | 81935,158660 6500 6500
+A 99 92 16 TEXT "Actions" | 65099,238365 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+L 96 97 0 TEXT "State Labels" | 72160,32703 1 0 0 "FIN\n/5/"
+S 97 72 24576 ELLIPSE "States" | 72160,32703 6500 6500
+W 98 72 8194 89 97 BEZIER "Transitions" | 69883,217517 58947,215375 37094,210735 31682,199460\
+                                          26270,188186 26497,147369 28526,126511 30555,105653\
+                                          38448,63032 43352,51475 48257,39919 60065,36353\
+                                          65928,34549
+I 124 120 0 Builtin Exit | 117012,100084
+I 123 120 0 Builtin Entry | 33260,254940
+H 120 112 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 119 72 8194 110 97 BEZIER "Transitions" | 81900,97446 75007,95299 61133,92159 58082,88882\
+                                            55031,85605 56613,76791 58364,71028 60116,65265\
+                                            65540,51027 67235,46846 68930,42665 69902,40249\
+                                            70580,39006
+A 118 114 16 TEXT "Actions" | 76583,119322 1 0 0 "RXByte <= RXDataIn;\nRXStreamStatus <= RXStreamStatusIn;"
+C 117 115 0 TEXT "Conditions" | 93326,90938 1 0 0 "RXStreamStatus == `RX_PACKET_STREAM"
+C 116 114 0 TEXT "Conditions" | 89464,124470 1 0 0 "RXDataValid == 1'b1"
+W 115 72 8193 110 112 BEZIER "Transitions" | 88787,91877 89012,87593 89678,80240 89903,75956
+W 114 72 0 102 110 BEZIER "Transitions" | 84969,123346 85307,119287 87370,108886 87708,104827
+L 113 112 0 TEXT "State Labels" | 90590,69496 1 0 0 "LOOP"
+S 112 72 40964 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 90590,69496 6500 6500
+W 143 120 8194 137 142 BEZIER "Transitions" | 96691,229500 102906,228257 113837,225951 118244,222730\
+                                              122651,219510 150577,206851 153176,201653
+S 142 120 49152 ELLIPSE "States" | 158244,197584 6500 6500
+L 141 142 0 TEXT "State Labels" | 158244,197584 1 0 0 "FIFO_FULL\n/10/"
+W 140 120 0 123 137 BEZIER "Transitions" | 37733,254940 42422,250307 79990,238736 84679,234103
+S 137 120 45056 ELLIPSE "States" | 90351,230929 6500 6500
+L 136 137 0 TEXT "State Labels" | 90351,230929 1 0 0 "CHK_FIFO\n/9/"
+A 135 131 16 TEXT "Actions" | 89016,138242 1 0 0 "RXByte <= RXDataIn;"
+C 133 131 0 TEXT "Conditions" | 102150,145171 1 0 0 "RXDataValid == 1'b1"
+W 131 120 0 150 245 BEZIER "Transitions" | 98038,146091 98376,140997 99442,128853 99780,125829
+W 159 72 0 112 97 BEZIER "Transitions" | 87959,63554 84795,57000 78577,44883 75413,38329
+A 158 150 4 TEXT "Actions" | 115287,153927 1 0 0 "RXFifoWEn <= 1'b0;"
+W 157 120 8194 245 124 BEZIER "Transitions" | 102288,119530 105695,116239 110493,103375 113900,100084
+C 156 154 0 TEXT "Conditions" | 23220,122661 1 0 0 "RXStreamStatusIn == `RX_PACKET_STREAM"
+W 154 120 8193 245 278 BEZIER "Transitions" | 96734,122505 61148,129409 49991,142018 45914,162537
+W 152 120 0 142 150 BEZIER "Transitions" | 155717,191596 153885,185528 149630,173716 143103,169022\
+                                           136577,164328 115116,157816 103895,154496
+S 150 120 53248 ELLIPSE "States" | 97690,152564 6500 6500
+L 149 150 0 TEXT "State Labels" | 97690,152564 1 0 0 "W_D\n/11/"
+A 147 143 16 TEXT "Actions" | 138187,216811 1 0 0 "RXOverflow <= 1'b1;"
+A 146 145 16 TEXT "Actions" | 79219,190029 1 0 0 "RXFifoWEn <= 1'b1;\nRXFifoData <= RXByteOldest;\nRXByteOldest <= RXByteOld;\nRXByteOld <= RXByte;"
+W 145 120 8195 137 150 BEZIER "Transitions" | 90837,224456 91407,218984 95945,164426 96515,158954
+C 144 143 0 TEXT "Conditions" | 107923,229678 1 0 0 "RXFifoFull == 1'b1"
+W 175 46 0 251 50 BEZIER "Transitions" | 120677,87962 123728,84233 127725,73445 133205,71354\
+                                         138686,69264 146640,68588 151838,68757 157036,68927\
+                                         164174,70167 165417,70562 166660,70958 172486,71065\
+                                         172450,70926 172415,70788 176807,72082 177204,72140
+A 173 40 4 TEXT "Actions" | 128094,45724 1 0 0 "RXPacketRdy <= 1'b1;"
+W 170 6 0 169 9 BEZIER "Transitions" | 40672,207751 50149,206219 60549,203961 70258,201617
+I 169 6 0 Builtin Reset | 40672,207751
+W 164 72 0 97 76 BEZIER "Transitions" | 73991,26470 75920,25222 78202,22776 88955,21953\
+                                        99709,21131 138868,20336 151863,21045 164858,21755\
+                                        177624,25344 184036,27160
+A 162 105 16 TEXT "Actions" | 77440,144748 1 0 0 "RXByteOld <= RXByte;"
+A 161 97 4 TEXT "Actions" | 87384,48020 1 0 0 "CRCError <= RXByte[`CRC_ERROR_BIT];\nbitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];\ndataSequence <= RXByte[`DATA_SEQUENCE_BIT];"
+I 191 0 130 Builtin InPort | 114421,225994 "" ""
+I 190 0 130 Builtin InPort | 114408,221254 "" ""
+L 189 190 0 TEXT "Labels" | 120408,221254 1 0 0 "RXStreamStatusIn[7:0]"
+C 188 170 0 TEXT "Conditions" | 56486,202566 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 140242,259912 "" ""
+L 186 187 0 TEXT "Labels" | 146242,259912 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 140253,265199 "" ""
+L 184 185 0 TEXT "Labels" | 146253,265199 1 0 0 "clk"
+I 183 0 2 Builtin InPort | 114228,230646 "" ""
+L 182 183 0 TEXT "Labels" | 120228,230646 1 0 0 "RXDataValid"
+I 181 0 2 Builtin OutPort | 117932,252596 "" ""
+L 180 181 0 TEXT "Labels" | 123932,252596 1 0 0 "RXPacketRdy"
+I 179 0 2 Builtin InPort | 120132,247896 "" ""
+L 178 179 0 TEXT "Labels" | 126132,247896 1 0 0 "getPacketEn"
+W 177 46 8195 54 251 BEZIER "Transitions" | 108942,219837 124822,217895 156122,213249 166404,209593\
+                                            176686,205938 186055,195197 188340,185143 190625,175090\
+                                            190396,145613 187654,132589 184913,119565 174172,96942\
+                                            167317,90830 160463,84718 143756,82720 138170,83176\
+                                            132585,83633 124984,88032 122129,89345
+W 176 46 0 58 251 BEZIER "Transitions" | 162954,146013 160327,135160 154521,114308 149780,107568\
+                                         145039,100828 129179,95043 122324,92416
+I 197 0 130 Builtin Signal | 19204,221408 "" ""
+L 196 197 0 TEXT "Labels" | 22204,221408 1 0 0 "RXByte[7:0]"
+K 195 194 0 TEXT "Comments" | 107584,237032 1 0 0 "Single cycle pulse"
+I 194 0 2 Builtin InPort | 79500,237048 "" ""
+L 193 194 0 TEXT "Labels" | 85500,237048 1 0 0 "SIERxTimeOut"
+L 192 191 0 TEXT "Labels" | 120421,225994 1 0 0 "RXDataIn[7:0]"
+I 222 0 130 Builtin Signal | 52956,259852 "" ""
+L 221 222 0 TEXT "Labels" | 55956,259852 1 0 0 "RXByteOld[7:0]"
+A 220 11 4 TEXT "Actions" | 125976,177552 1 0 0 "CRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nSIERxTimeOutEn <= 1'b1;"
+A 219 9 2 TEXT "Actions" | 18096,193444 1 0 0 "RXPacketRdy <= 1'b0;\nRXFifoWEn <= 1'b0;\nRXFifoData <= 8'h00;\nRXByteOld <= 8'h00;\nRXByteOldest <= 8'h00;\nCRCError <= 1'b0;\nbitStuffError <= 1'b0; \nRXOverflow <= 1'b0; \nRXTimeOut <= 1'b0;\nACKRxed <= 1'b0;\ndataSequence <= 1'b0;\nRxPID <= 4'h0;\nRXByte <= 8'h00;\nRXStreamStatus <= 8'h00;\nSIERxTimeOutEn <= 1'b0;"
+L 217 216 0 TEXT "Labels" | 22488,226184 1 0 0 "RXStreamStatus[7:0]"
+I 216 0 130 Builtin Signal | 19488,226184 "" ""
+I 232 0 130 Builtin OutPort | 77780,242452 "" ""
+L 231 232 0 TEXT "Labels" | 83780,242452 1 0 0 "RXFifoData[7:0]"
+I 230 0 2 Builtin OutPort | 77548,248252 "" ""
+L 229 230 0 TEXT "Labels" | 83548,248252 1 0 0 "RXFifoWEn"
+I 228 0 2 Builtin InPort | 79868,253240 "" ""
+L 227 228 0 TEXT "Labels" | 85868,253240 1 0 0 "RXFifoFull"
+L 226 225 0 TEXT "Labels" | 55956,265100 1 0 0 "RXByteOldest[7:0]"
+I 225 0 130 Builtin Signal | 52956,265100 "" ""
+A 236 34 16 TEXT "Actions" | 139592,90533 1 0 0 "RxPID <= RXByte[3:0];"
+L 237 238 0 TEXT "Labels" | 83500,221804 1 0 0 "RxPID[3:0]"
+I 238 0 130 Builtin OutPort | 77500,221804 "" ""
+W 239 6 0 33 40 BEZIER "Transitions" | 136428,68218 129381,59170 116484,42555 109437,33507
+A 243 93 16 TEXT "Actions" | 70474,205339 1 0 0 "RXByteOldest <= RXByte;"
+W 240 6 0 40 23 BEZIER "Transitions" | 100228,28439 96139,31658 88201,35365 84938,41063\
+                                       81676,46762 76804,63118 74237,72992 71671,82867\
+                                       66277,106009 65842,118015 65407,130021 69061,154903\
+                                       71671,163168 74281,171433 81067,179611 84373,181742\
+                                       87679,183874 93835,184146 97054,184320
+L 244 245 0 TEXT "State Labels" | 100230,122360 1 0 0 "J1"
+S 245 120 81940 ELLIPSE "Junction" | 100230,122360 3500 3500
+H 246 245 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 247 246 0 Builtin Entry | 86360,167640
+I 248 246 0 Builtin Exit | 129540,111760
+W 249 246 0 247 248 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+L 250 251 0 TEXT "State Labels" | 119090,91080 1 0 0 "J2"
+S 251 46 86036 ELLIPSE "Junction" | 119090,91080 3500 3500
+H 252 251 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 253 252 0 Builtin Entry | 86360,167640
+I 254 252 0 Builtin Exit | 129540,111760
+W 255 252 0 253 254 BEZIER "Transitions" | 90822,167640 102992,150317 114266,129084 126436,111760
+I 267 0 2 Builtin OutPort | 16484,242180 "" ""
+L 266 267 0 TEXT "Labels" | 22484,242180 1 0 0 "ACKRxed"
+I 265 0 2 Builtin OutPort | 16484,246788 "" ""
+L 264 265 0 TEXT "Labels" | 22484,246788 1 0 0 "RXOverflow"
+I 263 0 2 Builtin OutPort | 16484,251396 "" ""
+L 262 263 0 TEXT "Labels" | 22484,251396 1 0 0 "RXTimeOut"
+I 261 0 2 Builtin OutPort | 16740,255748 "" ""
+L 260 261 0 TEXT "Labels" | 22740,255748 1 0 0 "CRCError"
+I 259 0 2 Builtin OutPort | 16740,260356 "" ""
+L 258 259 0 TEXT "Labels" | 22740,260356 1 0 0 "bitStuffError"
+I 257 0 2 Builtin OutPort | 16740,264964 "" ""
+L 256 257 0 TEXT "Labels" | 22740,264964 1 0 0 "dataSequence"
+END

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/slaveGetpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/slaveSendpacket.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/slaveSendpacket.v	(revision 264)
@@ -0,0 +1,252 @@
+
+// File        : ../RTL/slaveController/slaveSendpacket.v
+// Generated   : 11/10/06 05:37:26
+// From        : ../RTL/slaveController/slaveSendpacket.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveSendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn);
+input   [3:0] PID;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   clk;
+input   [7:0] fifoData;
+input   fifoEmpty;
+input   rst;
+input   sendPacketWEn;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+output  fifoReadEn;
+output  sendPacketRdy;
+
+wire    [3:0] PID;
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+wire    clk;
+wire    [7:0] fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0] CurrState_slvSndPkt;
+reg [3:0] NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+always @(PID)
+begin
+    PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+//--------------------------------------------------------------------
+// Machine: slvSndPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt)
+begin : slvSndPkt_NextState
+  NextState_slvSndPkt <= CurrState_slvSndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_SCTxPortReq <= SCTxPortReq;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_fifoReadEn <= fifoReadEn;
+  case (CurrState_slvSndPkt)
+    `START_SP1:
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+    `SP_WAIT_ENABLE:
+      if (sendPacketWEn == 1'b1)	
+      begin
+        NextState_slvSndPkt <= `SP1_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_SCTxPortReq <= 1'b1;
+      end
+    `SP1_WAIT_GNT:
+      if (SCTxPortGnt == 1'b1)	
+        NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+    `FIN_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_SCTxPortReq <= 1'b0;
+    end
+    `SP_NOT_DATA:
+      NextState_slvSndPkt <= `FIN_SP1;
+    `SP_SEND_PID_WAIT_RDY:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= PIDNotPID;
+        next_SCTxPortCntl <= `TX_PACKET_START;
+      end
+    `SP_SEND_PID_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)	
+        NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+      else
+        NextState_slvSndPkt <= `SP_NOT_DATA;
+    end
+    `SP_D0_D1_READ_FIFO:
+    begin
+      next_SCTxPortWEn <= 1'b1;
+      next_SCTxPortData <= fifoData;
+      next_SCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+    end
+    `SP_D0_D1_WAIT_READ_FIFO:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    `SP_D0_D1_FIFO_EMPTY:
+      if (fifoEmpty == 1'b0)	
+        NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+      else
+        NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+    `SP_D0_D1_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_D0_D1_TERM_BYTE:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    `SP_D0_D1_CLR_WEN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+    end
+    `SP_D0_D1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvSndPkt_CurrentState
+  if (rst)	
+    CurrState_slvSndPkt <= `START_SP1;
+  else
+    CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvSndPkt_RegOutput
+  if (rst)	
+  begin
+    sendPacketRdy <= 1'b1;
+    SCTxPortReq <= 1'b0;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortData <= 8'h00;
+    SCTxPortCntl <= 8'h00;
+    fifoReadEn <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    SCTxPortReq <= next_SCTxPortReq;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortCntl <= next_SCTxPortCntl;
+    fifoReadEn <= next_fifoReadEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/slaveSendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/wrapper/usbHost.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/wrapper/usbHost.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/wrapper/usbHost.v	(revision 264)
@@ -0,0 +1,320 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHost.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbHost(
+  clk_i,
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  usbClk,
+  hostSOFSentIntOut, 
+  hostConnEventIntOut, 
+  hostResumeIntOut, 
+  hostTransDoneIntOut,
+  USBWireDataIn,
+  USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+  USBWireCtrlOut,
+  USBFullSpeed
+   );
+  parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = 2^HOST_ADDR_WIDTH
+  parameter HOST_FIFO_ADDR_WIDTH = 6;   
+  
+
+input clk_i;               //Wishbone bus clock. Maximum 5*usbClk=240MHz
+input rst_i;               //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
+input [7:0] address_i;     //Wishbone bus address in
+input [7:0] data_i;        //Wishbone bus data in
+output [7:0] data_o;       //Wishbone bus data out
+input we_i;                //Wishbone bus write enable in
+input strobe_i;            //Wishbone bus strobe in
+output ack_o;              //Wishbone bus acknowledge out
+input usbClk;              //usb clock. 48Mhz +/-0.25%
+output hostSOFSentIntOut; 
+output hostConnEventIntOut; 
+output hostResumeIntOut; 
+output hostTransDoneIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire we_i; 
+wire strobe_i;
+wire ack_o;
+wire usbClk;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel; 
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE; 
+wire [7:0] hostTxFifoData; 
+wire hostTxFifoEmpty;
+wire hostRxFifoWE; 
+wire [7:0] hostRxFifoData; 
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost; 
+wire fullSpeedPolarityFromHost;
+wire SIEPortWEnFromHost; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortCtrlInFromHost;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+wire noActivityTimeOutEnableToSIE;
+wire noActivityTimeOutEnableFromHost;
+
+// This is not a bug.
+// USBFullSpeed controls the PHY edge speed.
+// The only time that the PHY needs to operate with low speed edge rate is
+// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
+// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
+// but according to spec edge speed must be full rate edge speed. 
+assign USBFullSpeed = fullSpeedPolarityToSIE;
+//assign USBFullSpeed = fullSpeedBitRateToSIE;
+
+usbHostControl u_usbHostControl(
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .TxFifoRE(hostTxFifoRE), 
+  .TxFifoData(hostTxFifoData), 
+  .TxFifoEmpty(hostTxFifoEmpty),
+  .RxFifoWE(hostRxFifoWE), 
+  .RxFifoData(hostRxFifoData), 
+  .RxFifoFull(hostRxFifoFull),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut),
+  .SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
+  .fullSpeedRate(fullSpeedBitRateFromHost), 
+  .fullSpeedPol(fullSpeedPolarityFromHost),
+  .HCTxPortEn(SIEPortWEnFromHost), 
+  .HCTxPortRdy(SIEPortTxRdy),
+  .HCTxPortData(SIEPortDataInFromHost), 
+  .HCTxPortCtrl(SIEPortCtrlInFromHost),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[3:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostControl), 
+  .busWriteEn(we_i),
+  .busStrobe_i(strobe_i),
+  .SOFSentIntOut(hostSOFSentIntOut), 
+  .connEventIntOut(hostConnEventIntOut), 
+  .resumeIntOut(hostResumeIntOut), 
+  .transDoneIntOut(hostTransDoneIntOut),
+  .hostControlSelect(hostControlSel) );
+
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(we_i), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk_i), 
+  .rst(rstSyncToBusClk),
+  .hostControlSel(hostControlSel), 
+  .hostRxFifoSel(hostRxFifoSel), 
+  .hostTxFifoSel(hostTxFifoSel),
+  .slaveControlSel(),
+  .slaveEP0RxFifoSel(), 
+  .slaveEP1RxFifoSel(),
+  .slaveEP2RxFifoSel(), 
+  .slaveEP3RxFifoSel(), 
+  .slaveEP0TxFifoSel(), 
+  .slaveEP1TxFifoSel(), 
+  .slaveEP2TxFifoSel(), 
+  .slaveEP3TxFifoSel(), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(dataFromHostControl),
+  .dataFromHostRxFifo(dataFromHostRxFifo),
+  .dataFromHostTxFifo(dataFromHostTxFifo),
+  .dataFromSlaveControl(8'h00),
+  .dataFromEP0RxFifo(8'h00), 
+  .dataFromEP1RxFifo(8'h00), 
+  .dataFromEP2RxFifo(8'h00), 
+  .dataFromEP3RxFifo(8'h00),
+  .dataFromEP0TxFifo(8'h00), 
+  .dataFromEP1TxFifo(8'h00), 
+  .dataFromEP2TxFifo(8'h00), 
+  .dataFromEP3TxFifo(8'h00),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+   );
+
+
+assign SIEPortCtrlInToSIE = SIEPortCtrlInFromHost;
+assign SIEPortDataInToSIE = SIEPortDataInFromHost;
+assign SIEPortWEnToSIE = SIEPortWEnFromHost;
+assign fullSpeedPolarityToSIE = fullSpeedPolarityFromHost;
+assign fullSpeedBitRateToSIE = fullSpeedBitRateFromHost;
+assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromHost;
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux),
+  .address(address_i[0]),
+  .writeEn(we_i),
+  .strobe_i(strobe_i),
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .hostMode(hostMode), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),  
+  .rstFromWire(rst_i),
+  .rstSyncToBusClkOut(rstSyncToBusClk),
+  .rstSyncToUsbClkOut(rstSyncToUsbClk)
+);
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .connectState(connectState),
+  .resumeDetected(resumeDetected),
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataFromSIE), 
+  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+  .SIEPortDataIn(SIEPortDataInToSIE), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEnToSIE), 
+  .fullSpeedPolarity(fullSpeedPolarityToSIE),
+  .fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut),
+  .noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
+);
+
+
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(hostTxFifoRE), 
+  .fifoEmpty(hostTxFifoEmpty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostTxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostTxFifo),
+  .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i),
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(hostRxFifoWE), 
+  .fifoFull(hostRxFifoFull),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostRxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostRxFifo),
+  .fifoDataIn(hostRxFifoData)  );
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v	(revision 264)
@@ -0,0 +1,396 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine.v                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbSerialInterfaceEngine(
+  clk, rst,
+  //readUSBWireData
+  USBWireDataIn,
+  USBWireDataInTick,
+  //writeUSBWireData
+  USBWireDataOut,
+  USBWireCtrlOut,
+  USBWireDataOutTick,
+  //SIEReceiver
+  connectState,
+  //processRxBit
+  resumeDetected,
+  //processRxByte
+  RxCtrlOut, 
+  RxDataOutWEn, 
+  RxDataOut, 
+    //SIETransmitter
+  SIEPortCtrlIn,
+  SIEPortDataIn, 
+  SIEPortTxRdy, 
+  SIEPortWEn, 
+    //lineControlUpdate
+  fullSpeedPolarity,
+  fullSpeedBitRate,
+  noActivityTimeOut,
+  noActivityTimeOutEnable
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+output noActivityTimeOut;
+input noActivityTimeOutEnable;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut; 
+output RxDataOutWEn; 
+output [7:0] RxDataOut; 
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy; 
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut; 
+wire RxDataOutWEn; 
+wire [7:0] RxDataOut; 
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy; 
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En; 
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En; 
+wire [4:0] RxCRC5Result; 
+wire RxCRC5_8Bit; 
+wire [7:0] RxCRCData; 
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En; 
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En; 
+wire [4:0] TxCRC5Result; 
+wire TxCRC5_8Bit; 
+wire [7:0] TxCRCData; 
+wire TxRstCRC; 
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy; 
+wire processTxByteWEn; 
+
+wire SIEFsRate;
+wire TxFSRateFromSIETxToPrcTxByte;
+wire prcTxByteFSRate;
+wire FSRateFromArbiterToWire;
+
+wire RxWireActive;
+
+lineControlUpdate u_lineControlUpdate
+  (.fullSpeedPolarity(fullSpeedPolarity),
+  .fullSpeedBitRate(fullSpeedBitRate),
+  .JBit(JBit),
+  .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+  (
+  .RxWireDataIn(RxWireDataFromWireRx), 
+  .RxWireDataWEn(RxWireDataWEn), 
+  .clk(clk),
+  .connectState(connectState),
+  .rst(rst) );
+
+  
+processRxBit u_processRxBit
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .RxBitsIn(RxWireDataFromWireRx), 
+  .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxDataOut(RxDataFromPrcRxBitToPrcRxByte), 
+  .clk(clk), 
+  .processRxBitRdy(processRxBitRdy), 
+  .processRxBitsWEn(RxWireDataWEn), 
+  .processRxByteWEn(processRxByteWEn), 
+  .resumeDetected(resumeDetected), 
+  .rst(rst),
+  .processRxByteRdy(processRxByteRdy),
+  .RxWireActive(RxWireActive),
+  .fullSpeedBitRate(fullSpeedBitRate)
+
+  );
+  
+processRxByte u_processRxByte
+  (.CRC16En(RxCRC16En), 
+  .CRC16Result(RxCRC16Result), 
+  .CRC16UpdateRdy(RxCRC16UpdateRdy),
+  .CRC5En(RxCRC5En), 
+  .CRC5Result(RxCRC5Result), 
+  .CRC5_8Bit(RxCRC5_8Bit),
+  .CRC5UpdateRdy(RxCRC5UpdateRdy),
+  .CRCData(RxCRCData), 
+  .RxByteIn(RxDataFromPrcRxBitToPrcRxByte), 
+  .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataOut), 
+  .clk(clk), 
+  .processRxDataInWEn(processRxByteWEn), 
+  .rst(rst), 
+  .rstCRC(RxRstCRC),
+  .processRxByteRdy(processRxByteRdy) ); 
+  
+  
+updateCRC5 RxUpdateCRC5
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC5Result), 
+  .CRCEn(RxCRC5En), 
+  .CRC5_8BitIn(RxCRC5_8Bit), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 RxUpdateCRC16
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC16Result), 
+  .CRCEn(RxCRC16En), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+SIETransmitter u_SIETransmitter
+  (.CRC16En(TxCRC16En), 
+  .CRC16Result(TxCRC16Result), 
+  .CRC5En(TxCRC5En), 
+  .CRC5Result(TxCRC5Result), 
+  .CRC5_8Bit(TxCRC5_8Bit), 
+  .CRCData(TxCRCData),
+  .CRC5UpdateRdy(TxCRC5UpdateRdy),
+  .CRC16UpdateRdy(TxCRC16UpdateRdy),
+  .JBit(JBit), 
+  .KBit(KBit), 
+  .SIEPortCtrlIn(SIEPortCtrlIn),
+  .SIEPortDataIn(SIEPortDataIn), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEn), 
+  .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteOut(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(SIETxCtrl), 
+  .USBWireData(SIETxData), 
+  .USBWireGnt(SIETxGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(SIETxReq), 
+  .USBWireWEn(SIETxWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst), 
+  .rstCRC(TxRstCRC),
+  .USBWireFullSpeedRate(SIEFsRate),
+  .TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
+  .fullSpeedRateIn(fullSpeedBitRate)
+  );    
+
+updateCRC5 TxUpdateCRC5
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC5Result), 
+  .CRCEn(TxCRC5En), 
+  .CRC5_8BitIn(TxCRC5_8Bit), 
+  .dataIn(TxCRCData),
+  .ready(TxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 TxUpdateCRC16
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC16Result), 
+  .CRCEn(TxCRC16En), 
+  .dataIn(TxCRCData), 
+  .ready(TxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+
+processTxByte u_processTxByte
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteIn(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(prcTxByteCtrl), 
+  .USBWireData(prcTxByteData), 
+  .USBWireGnt(prcTxByteGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(prcTxByteReq), 
+  .USBWireWEn(prcTxByteWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst),
+  .USBWireFullSpeedRate(prcTxByteFSRate),
+  .TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
+  ); 
+  
+USBTxWireArbiter u_USBTxWireArbiter
+  (.SIETxCtrl(SIETxCtrl), 
+  .SIETxData(SIETxData), 
+  .SIETxGnt(SIETxGnt), 
+  .SIETxReq(SIETxReq), 
+  .SIETxWEn(SIETxWEn), 
+  .TxBits(TxBitsFromArbToWire), 
+  .TxCtl(TxCtrlFromArbToWire), 
+  .USBWireRdyIn(USBWireRdy), 
+  .USBWireRdyOut(USBWireReadyFromTxArb), 
+  .USBWireWEn(USBWireWEn),
+  .clk(clk), 
+  .prcTxByteCtrl(prcTxByteCtrl), 
+  .prcTxByteData(prcTxByteData), 
+  .prcTxByteGnt(prcTxByteGnt), 
+  .prcTxByteReq(prcTxByteReq), 
+  .prcTxByteWEn(prcTxByteWEn), 
+  .rst(rst),
+  .SIETxFSRate(SIEFsRate),
+  .prcTxByteFSRate(prcTxByteFSRate),
+  .TxFSRate(FSRateFromArbiterToWire)
+  ); 
+  
+writeUSBWireData u_writeUSBWireData
+  (.TxBitsIn(TxBitsFromArbToWire), 
+  .TxBitsOut(USBWireDataOut), 
+  .TxDataOutTick(USBWireDataOutTick),
+  .TxCtrlIn(TxCtrlFromArbToWire), 
+  .TxCtrlOut(USBWireCtrlOut), 
+  .USBWireRdy(USBWireRdy), 
+  .USBWireWEn(USBWireWEn),
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .fullSpeedRate(FSRateFromArbiterToWire), 
+  .clk(clk),
+  .rst(rst)
+   );  
+
+  
+  
+readUSBWireData u_readUSBWireData
+  (.RxBitsIn(USBWireDataIn), 
+  .RxDataInTick(USBWireDataInTick),
+  .RxBitsOut(RxWireDataFromWireRx), 
+  .SIERxRdyIn(processRxBitRdy), 
+  .SIERxWEn(RxWireDataWEn), 
+  .fullSpeedRate(fullSpeedBitRate), 
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .clk(clk),
+  .rst(rst),
+  .noActivityTimeOut(noActivityTimeOut),
+  .RxWireActive(RxWireActive),
+  .noActivityTimeOutEnable(noActivityTimeOutEnable)
+  );
+
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v	(revision 264)
@@ -0,0 +1,714 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBSlaveControlBI.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////       
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSlaveControl_h.v"
+ 
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut, vBusDetIntOut,
+  endP0TransTypeReg, endP0NAKTransTypeReg,
+  endP1TransTypeReg, endP1NAKTransTypeReg,
+  endP2TransTypeReg, endP2NAKTransTypeReg,
+  endP3TransTypeReg, endP3NAKTransTypeReg,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  EP0StatusReg,
+  EP1StatusReg,
+  EP2StatusReg,
+  EP3StatusReg,
+  SCAddrReg, frameNum,
+  connectStateIn,
+  vBusDetectIn,
+  SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+  slaveControlSelect,
+  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  connectSlaveToHost,
+  SCGlobalEn
+  );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+output vBusDetIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg; 
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg; 
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg; 
+input [1:0] endP3NAKTransTypeReg;
+output [4:0] endP0ControlReg;
+output [4:0] endP1ControlReg;
+output [4:0] endP2ControlReg;
+output [4:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input vBusDetectIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output connectSlaveToHost;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+reg vBusDetIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg; 
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg; 
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg; 
+wire [1:0] endP3NAKTransTypeReg;
+reg [4:0] endP0ControlReg;
+reg [4:0] endP0ControlReg1;
+reg [4:0] endP1ControlReg;
+reg [4:0] endP1ControlReg1;
+reg [4:0] endP2ControlReg;
+reg [4:0] endP2ControlReg1;
+reg [4:0] endP3ControlReg;
+reg [4:0] endP3ControlReg1;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg [1:0] TxLineState_reg1;
+reg LineDirectControlEn;
+reg LineDirectControlEn_reg1;
+reg fullSpeedPol; 
+reg fullSpeedPol_reg1; 
+reg fullSpeedRate;
+reg fullSpeedRate_reg1;
+reg connectSlaveToHost;
+reg connectSlaveToHost_reg1;
+reg SCGlobalEn;
+reg SCGlobalEn_reg1;
+
+//internal wire and regs
+reg [6:0] SCControlReg;
+reg clrVBusDetReq;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg vBusDetInt;
+reg NAKSentInt;
+reg [5:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0IsoEn;
+reg EP1IsoEn;
+reg EP2IsoEn;
+reg EP3IsoEn;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+reg [2:0] SOFRxedInExtend;
+reg [2:0] resetEventInExtend;
+reg [2:0] resumeIntInExtend;
+reg [2:0] transDoneInExtend;
+reg [2:0] NAKSentInExtend;
+reg [2:0] clrEP0ReadyExtend;
+reg [2:0] clrEP1ReadyExtend;
+reg [2:0] clrEP2ReadyExtend;
+reg [2:0] clrEP3ReadyExtend;
+
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [4:0] endP0ControlRegSTB;
+reg [4:0] endP1ControlRegSTB;
+reg [4:0] endP2ControlRegSTB;
+reg [4:0] endP3ControlRegSTB;
+reg [2:0] NAKSentInSTB;
+reg [2:0] SOFRxedInSTB;
+reg [2:0] resetEventInSTB;
+reg [2:0] resumeIntInSTB;
+reg [2:0] transDoneInSTB;
+reg [2:0] clrEP0ReadySTB;
+reg [2:0] clrEP1ReadySTB;
+reg [2:0] clrEP2ReadySTB;
+reg [2:0] clrEP3ReadySTB;
+reg SCGlobalEnSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB; 
+reg fullSpeedRateSTB;
+reg connectSlaveToHostSTB;
+reg [7:0] EP0StatusRegSTB;
+reg [7:0] EP0StatusRegSTB_reg1;
+reg [7:0] EP1StatusRegSTB;
+reg [7:0] EP1StatusRegSTB_reg1;
+reg [7:0] EP2StatusRegSTB;
+reg [7:0] EP2StatusRegSTB_reg1;
+reg [7:0] EP3StatusRegSTB;
+reg [7:0] EP3StatusRegSTB_reg1;
+reg [1:0] endP0TransTypeRegSTB;
+reg [1:0] endP0TransTypeRegSTB_reg1;
+reg [1:0] endP0NAKTransTypeRegSTB;
+reg [1:0] endP0NAKTransTypeRegSTB_reg1;
+reg [1:0] endP1TransTypeRegSTB; 
+reg [1:0] endP1TransTypeRegSTB_reg1; 
+reg [1:0] endP1NAKTransTypeRegSTB;
+reg [1:0] endP1NAKTransTypeRegSTB_reg1;
+reg [1:0] endP2TransTypeRegSTB; 
+reg [1:0] endP2TransTypeRegSTB_reg1; 
+reg [1:0] endP2NAKTransTypeRegSTB;
+reg [1:0] endP2NAKTransTypeRegSTB_reg1;
+reg [1:0] endP3TransTypeRegSTB; 
+reg [1:0] endP3TransTypeRegSTB_reg1; 
+reg [1:0] endP3NAKTransTypeRegSTB;
+reg [1:0] endP3NAKTransTypeRegSTB_reg1;
+reg [10:0] frameNumSTB;
+reg [10:0] frameNumSTB_reg1;
+reg [2:0] vBusDetectInSTB;
+reg [1:0] connectStateInSTB;
+reg [1:0] connectStateInSTB_reg1;
+
+  
+//sync write demux
+always @(posedge busClk)
+begin   
+  if (rstSyncToBusClk == 1'b1) begin
+    EP0IsoEn <= 1'b0;
+    EP0SendStall <= 1'b0;
+    EP0DataSequence <= 1'b0;
+    EP0Enable <= 1'b0;
+    EP1IsoEn <= 1'b0;
+    EP1SendStall <= 1'b0;
+    EP1DataSequence <= 1'b0;
+    EP1Enable <= 1'b0;
+    EP2IsoEn <= 1'b0;
+    EP2SendStall <= 1'b0;
+    EP2DataSequence <= 1'b0;
+    EP2Enable <= 1'b0;
+    EP3IsoEn <= 1'b0;
+    EP3SendStall <= 1'b0;
+    EP3DataSequence <= 1'b0;
+    EP3Enable <= 1'b0;
+    SCControlReg <= 7'h00;
+    SCAddrReg <= 7'h00;
+    interruptMaskReg <= 6'h00;
+  end
+  else begin
+    clrVBusDetReq <= 1'b0;
+    clrNAKReq <= 1'b0;
+    clrSOFReq <= 1'b0;
+    clrResetReq <= 1'b0;
+    clrResInReq <= 1'b0;
+    clrTransDoneReq <= 1'b0;
+    EP0SetReady <= 1'b0;
+    EP1SetReady <= 1'b0;
+    EP2SetReady <= 1'b0;
+    EP3SetReady <= 1'b0;
+    if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+    begin
+      case (address)
+        `EP0_CTRL_REG : begin
+          EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP1_CTRL_REG : begin
+          EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP2_CTRL_REG : begin
+          EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP3_CTRL_REG : begin
+          EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `SC_CONTROL_REG : SCControlReg <= dataIn[6:0];
+        `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+        `SC_INTERRUPT_STATUS_REG : begin
+          clrVBusDetReq <= dataIn[`VBUS_DET_INT_BIT];
+          clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
+          clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
+          clrResetReq <= dataIn[`RESET_EVENT_BIT];
+          clrResInReq <= dataIn[`RESUME_INT_BIT];
+          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+        end
+        `SC_INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[5:0];
+      endcase
+    end
+  end
+end
+
+//interrupt control 
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    vBusDetInt <= 1'b0;
+    NAKSentInt <= 1'b0;
+    SOFRxedInt <= 1'b0;
+    resetEventInt <= 1'b0;
+    resumeInt <= 1'b0;
+    transDoneInt <= 1'b0;
+  end
+  else begin
+    if (vBusDetectInSTB[0] != vBusDetectInSTB[1])
+      vBusDetInt <= 1'b1;
+    else if (clrVBusDetReq == 1'b1)
+      vBusDetInt <= 1'b0; 
+
+    if (NAKSentInSTB[1] == 1'b1 && NAKSentInSTB[0] == 1'b0)
+      NAKSentInt <= 1'b1;
+    else if (clrNAKReq == 1'b1)
+      NAKSentInt <= 1'b0; 
+    
+    if (SOFRxedInSTB[1] == 1'b1 && SOFRxedInSTB[0] == 1'b0)
+      SOFRxedInt <= 1'b1;
+    else if (clrSOFReq == 1'b1)
+      SOFRxedInt <= 1'b0;
+    
+    if (resetEventInSTB[1] == 1'b1 && resetEventInSTB[0] == 1'b0)
+      resetEventInt <= 1'b1;
+    else if (clrResetReq == 1'b1)
+      resetEventInt <= 1'b0;
+    
+    if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
+      resumeInt <= 1'b1;
+    else if (clrResInReq == 1'b1)
+      resumeInt <= 1'b0;
+
+    if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
+      transDoneInt <= 1'b1;
+    else if (clrTransDoneReq == 1'b1)
+      transDoneInt <= 1'b0;
+  end
+end
+
+//mask interrupts
+always @(*) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+  vBusDetIntOut <= vBusDetInt & interruptMaskReg[`VBUS_DET_INT_BIT];
+end  
+
+//end point ready, set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'EP0SetReady' etc must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the ready is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'EP0Ready' and sampling of related control signals.
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    EP0Ready <= 1'b0;
+    EP1Ready <= 1'b0;
+    EP2Ready <= 1'b0;
+    EP3Ready <= 1'b0;
+  end
+  else begin
+    if (EP0SetReady == 1'b1)
+      EP0Ready <= 1'b1;
+    else if (clrEP0ReadySTB[1] == 1'b1 && clrEP0ReadySTB[0] == 1'b0)
+      EP0Ready <= 1'b0;
+    
+    if (EP1SetReady == 1'b1)
+      EP1Ready <= 1'b1;
+    else if (clrEP1ReadySTB[1] == 1'b1 && clrEP1ReadySTB[0] == 1'b0)
+      EP1Ready <= 1'b0;
+    
+    if (EP2SetReady == 1'b1)
+      EP2Ready <= 1'b1;
+    else if (clrEP2ReadySTB[1] == 1'b1 && clrEP2ReadySTB[0] == 1'b0)
+      EP2Ready <= 1'b0;
+    
+    if (EP3SetReady == 1'b1)
+      EP3Ready <= 1'b1;
+    else if (clrEP3ReadySTB[1] == 1'b1 && clrEP3ReadySTB[0] == 1'b0)
+      EP3Ready <= 1'b0;
+  end
+end  
+  
+//break out control signals
+always @(SCControlReg) begin
+  SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+  TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+  LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+  fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+  connectSlaveToHostSTB <= SCControlReg[`SC_CONNECT_TO_HOST_BIT];
+end
+
+//combine endpoint control signals 
+always @(*) 
+begin
+  endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+  endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+  endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+  endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+      
+      
+// async read mux
+always @(*)
+begin
+  case (address)
+      `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
+      `EP0_STS_REG : dataOut <= EP0StatusRegSTB;
+      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
+      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
+      `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
+      `EP1_STS_REG :  dataOut <= EP1StatusRegSTB;
+      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
+      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
+      `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
+      `EP2_STS_REG :  dataOut <= EP2StatusRegSTB;
+      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
+      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
+      `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
+      `EP3_STS_REG :  dataOut <= EP3StatusRegSTB;
+      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
+      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
+      `SC_CONTROL_REG : dataOut <= SCControlReg;
+      `SC_LINE_STATUS_REG : dataOut <= {5'b00000, vBusDetectInSTB[0], connectStateInSTB}; 
+      `SC_INTERRUPT_STATUS_REG :  dataOut <= {2'b00, vBusDetInt, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+      `SC_INTERRUPT_MASK_REG  : dataOut <= {2'b00, interruptMaskReg};
+      `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+      `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
+      `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+
+//Extend SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn from 1 tick
+//pulses to 3 tick pulses
+always @(posedge usbClk) begin
+  if (rstSyncToUsbClk == 1'b1) begin
+    SOFRxedInExtend <= 3'b000;
+    resetEventInExtend <= 3'b000;
+    resumeIntInExtend <= 3'b000;
+    transDoneInExtend <= 3'b000;
+    NAKSentInExtend <= 3'b000;
+    clrEP0ReadyExtend <= 3'b000;
+    clrEP1ReadyExtend <= 3'b000;
+    clrEP2ReadyExtend <= 3'b000;
+    clrEP3ReadyExtend <= 3'b000;
+  end
+  else begin
+    if (SOFRxedIn == 1'b1)
+      SOFRxedInExtend <= 3'b111;
+    else
+      SOFRxedInExtend <= {1'b0, SOFRxedInExtend[2:1]};
+    if (resetEventIn == 1'b1)
+      resetEventInExtend <= 3'b111;
+    else
+      resetEventInExtend <= {1'b0, resetEventInExtend[2:1]};
+    if (resumeIntIn == 1'b1)
+      resumeIntInExtend <= 3'b111;
+    else
+      resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
+    if (transDoneIn == 1'b1)
+      transDoneInExtend <= 3'b111;
+    else
+      transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
+    if (NAKSentIn == 1'b1)
+      NAKSentInExtend <= 3'b111;
+    else
+      NAKSentInExtend <= {1'b0, NAKSentInExtend[2:1]};
+    if (clrEP0Ready == 1'b1)
+      clrEP0ReadyExtend <= 3'b111;
+    else
+      clrEP0ReadyExtend <= {1'b0, clrEP0ReadyExtend[2:1]};
+    if (clrEP1Ready == 1'b1)
+      clrEP1ReadyExtend <= 3'b111;
+    else
+      clrEP1ReadyExtend <= {1'b0, clrEP1ReadyExtend[2:1]};
+    if (clrEP2Ready == 1'b1)
+      clrEP2ReadyExtend <= 3'b111;
+    else
+      clrEP2ReadyExtend <= {1'b0, clrEP2ReadyExtend[2:1]};
+    if (clrEP3Ready == 1'b1)
+      clrEP3ReadyExtend <= 3'b111;
+    else
+      clrEP3ReadyExtend <= {1'b0, clrEP3ReadyExtend[2:1]};
+  end
+end
+
+//re-sync from busClk to usbClk. 
+always @(posedge usbClk) begin
+  if (rstSyncToUsbClk == 1'b1) begin
+    endP0ControlReg <= {5{1'b0}};
+    endP0ControlReg1 <= {5{1'b0}};
+    endP1ControlReg <= {5{1'b0}};
+    endP1ControlReg1 <= {5{1'b0}};
+    endP2ControlReg <= {5{1'b0}};
+    endP2ControlReg1 <= {5{1'b0}};
+    endP3ControlReg <= {5{1'b0}};
+    endP3ControlReg1 <= {5{1'b0}};
+    SCGlobalEn <= 1'b0;
+    SCGlobalEn_reg1 <= 1'b0;
+    TxLineState <= 2'b00;
+    TxLineState_reg1 <= 2'b00;
+    LineDirectControlEn <= 1'b0;
+    LineDirectControlEn_reg1 <= 1'b0;
+    fullSpeedPol <= 1'b0;
+    fullSpeedPol_reg1 <= 1'b0;
+    fullSpeedRate <= 1'b0;
+    fullSpeedRate_reg1 <= 1'b0;
+    connectSlaveToHost <= 1'b0;
+    connectSlaveToHost_reg1 <= 1'b0;
+  end
+  else begin
+    endP0ControlReg1 <= endP0ControlRegSTB;
+    endP0ControlReg <= endP0ControlReg1;
+    endP1ControlReg1 <= endP1ControlRegSTB;
+    endP1ControlReg <= endP1ControlReg1;
+    endP2ControlReg1 <= endP2ControlRegSTB;
+    endP2ControlReg <= endP2ControlReg1;
+    endP3ControlReg1 <= endP3ControlRegSTB;
+    endP3ControlReg <= endP3ControlReg1;
+    SCGlobalEn_reg1 <= SCGlobalEnSTB;
+    SCGlobalEn <= SCGlobalEn_reg1;
+    TxLineState_reg1 <= TxLineStateSTB;
+    TxLineState <= TxLineState_reg1;
+    LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
+    LineDirectControlEn <= LineDirectControlEn_reg1;
+    fullSpeedPol_reg1 <= fullSpeedPolSTB; 
+    fullSpeedPol <= fullSpeedPol_reg1; 
+    fullSpeedRate_reg1 <= fullSpeedRateSTB;
+    fullSpeedRate <= fullSpeedRate_reg1;
+    connectSlaveToHost_reg1 <= connectSlaveToHostSTB;
+    connectSlaveToHost <= connectSlaveToHost_reg1;
+  end
+end
+
+//re-sync from usbClk and async inputs to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc 
+//are only asserted for 3 usbClk ticks
+//busClk freq must be greater than usbClk/3 (plus some allowance for setup and hold) freq
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) begin
+    vBusDetectInSTB <= 3'b000;
+    NAKSentInSTB <= 3'b000;
+    SOFRxedInSTB <= 3'b000;
+    resetEventInSTB <= 3'b000;
+    resumeIntInSTB <= 3'b000;
+    transDoneInSTB <= 3'b000;
+    clrEP0ReadySTB <= 3'b000;
+    clrEP1ReadySTB <= 3'b000;
+    clrEP2ReadySTB <= 3'b000;
+    clrEP3ReadySTB <= 3'b000;
+    EP0StatusRegSTB <= 8'h00;
+    EP0StatusRegSTB_reg1 <= 8'h00;
+    EP1StatusRegSTB <= 8'h00;
+    EP1StatusRegSTB_reg1 <= 8'h00;
+    EP2StatusRegSTB <= 8'h00;
+    EP2StatusRegSTB_reg1 <= 8'h00;
+    EP3StatusRegSTB <= 8'h00;
+    EP3StatusRegSTB_reg1 <= 8'h00;
+    endP0TransTypeRegSTB <= 2'b00;
+    endP0TransTypeRegSTB_reg1 <= 2'b00;
+    endP1TransTypeRegSTB <= 2'b00;
+    endP1TransTypeRegSTB_reg1 <= 2'b00;
+    endP2TransTypeRegSTB <= 2'b00;
+    endP2TransTypeRegSTB_reg1 <= 2'b00;
+    endP3TransTypeRegSTB <= 2'b00;
+    endP3TransTypeRegSTB_reg1 <= 2'b00;
+    endP0NAKTransTypeRegSTB <= 2'b00;
+    endP0NAKTransTypeRegSTB_reg1 <= 2'b00;
+    endP1NAKTransTypeRegSTB <= 2'b00;
+    endP1NAKTransTypeRegSTB_reg1 <= 2'b00;
+    endP2NAKTransTypeRegSTB <= 2'b00;
+    endP2NAKTransTypeRegSTB_reg1 <= 2'b00;
+    endP3NAKTransTypeRegSTB <= 2'b00;
+    endP3NAKTransTypeRegSTB_reg1 <= 2'b00;
+    frameNumSTB <= {11{1'b0}};
+    frameNumSTB_reg1 <= {11{1'b0}};
+    connectStateInSTB <= 2'b00;
+    connectStateInSTB_reg1 <= 2'b00;
+  end
+  else begin
+    vBusDetectInSTB <= {vBusDetectIn, vBusDetectInSTB[2:1]};
+    NAKSentInSTB <= {NAKSentInExtend[0], NAKSentInSTB[2:1]};
+    SOFRxedInSTB <= {SOFRxedInExtend[0], SOFRxedInSTB[2:1]};
+    resetEventInSTB <= {resetEventInExtend[0], resetEventInSTB[2:1]};
+    resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
+    transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
+    clrEP0ReadySTB <= {clrEP0ReadyExtend[0], clrEP0ReadySTB[2:1]};
+    clrEP1ReadySTB <= {clrEP1ReadyExtend[0], clrEP1ReadySTB[2:1]};
+    clrEP2ReadySTB <= {clrEP2ReadyExtend[0], clrEP2ReadySTB[2:1]};
+    clrEP3ReadySTB <= {clrEP3ReadyExtend[0], clrEP3ReadySTB[2:1]};
+    EP0StatusRegSTB_reg1 <= EP0StatusReg;
+    EP0StatusRegSTB <= EP0StatusRegSTB_reg1;
+    EP1StatusRegSTB_reg1 <= EP1StatusReg;
+    EP1StatusRegSTB <= EP1StatusRegSTB_reg1;
+    EP2StatusRegSTB_reg1 <= EP2StatusReg;
+    EP2StatusRegSTB <= EP2StatusRegSTB_reg1;
+    EP3StatusRegSTB_reg1 <= EP3StatusReg;
+    EP3StatusRegSTB <= EP3StatusRegSTB_reg1;
+    endP0TransTypeRegSTB_reg1 <= endP0TransTypeReg;
+    endP0TransTypeRegSTB <= endP0TransTypeRegSTB_reg1;
+    endP1TransTypeRegSTB_reg1 <= endP1TransTypeReg;
+    endP1TransTypeRegSTB <= endP1TransTypeRegSTB_reg1;
+    endP2TransTypeRegSTB_reg1 <= endP2TransTypeReg;
+    endP2TransTypeRegSTB <= endP2TransTypeRegSTB_reg1;
+    endP3TransTypeRegSTB_reg1 <= endP3TransTypeReg;
+    endP3TransTypeRegSTB <= endP3TransTypeRegSTB_reg1;
+    endP0NAKTransTypeRegSTB_reg1 <= endP0NAKTransTypeReg;
+    endP0NAKTransTypeRegSTB <= endP0NAKTransTypeRegSTB_reg1;
+    endP1NAKTransTypeRegSTB_reg1 <= endP1NAKTransTypeReg;
+    endP1NAKTransTypeRegSTB <= endP1NAKTransTypeRegSTB_reg1;
+    endP2NAKTransTypeRegSTB_reg1 <= endP2NAKTransTypeReg;
+    endP2NAKTransTypeRegSTB <= endP2NAKTransTypeRegSTB_reg1;
+    endP3NAKTransTypeRegSTB_reg1 <= endP3NAKTransTypeReg;
+    endP3NAKTransTypeRegSTB <= endP3NAKTransTypeRegSTB_reg1;
+    frameNumSTB_reg1 <= frameNum;
+    frameNumSTB <= frameNumSTB_reg1;
+    connectStateInSTB_reg1 <= connectStateIn;
+    connectStateInSTB <= connectStateInSTB_reg1;
+  end
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/USBSlaveControlBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/sctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/sctxportarbiter.v	(revision 264)
@@ -0,0 +1,202 @@
+
+// File        : ../RTL/slaveController/sctxportarbiter.v
+// Generated   : 11/10/06 05:37:24
+// From        : ../RTL/slaveController/sctxportarbiter.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SCTxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module SCTxPortArbiter (SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   SCTxPortRdyIn;
+input   clk;
+input   [7:0] directCntlCntl;
+input   [7:0] directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0] sendPacketCntl;
+input   [7:0] sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortRdyOut;
+output  SCTxPortWEnable;
+output  directCntlGnt;
+output  sendPacketGnt;
+
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortRdyIn;
+reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg     SCTxPortWEnable, next_SCTxPortWEnable;
+wire    clk;
+wire    [7:0] directCntlCntl;
+wire    [7:0] directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+wire    [7:0] sendPacketCntl;
+wire    [7:0] sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0] CurrState_SCTxArb;
+reg [1:0] NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+    SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+		 		 directCntlWEn or directCntlData or directCntlCntl or
+                  directCntlWEn or directCntlData or directCntlCntl or
+ 		  		 sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+    begin
+        SCTxPortWEnable <= directCntlWEn;
+        SCTxPortData <= directCntlData;
+        SCTxPortCntl <= directCntlCntl;
+    end
+else
+    begin
+        SCTxPortWEnable <= sendPacketWEn;
+        SCTxPortData <= sendPacketData;
+        SCTxPortCntl <= sendPacketCntl;
+    end
+end
+
+//--------------------------------------------------------------------
+// Machine: SCTxArb
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin : SCTxArb_NextState
+  NextState_SCTxArb <= CurrState_SCTxArb;
+  // Set default values for outputs and signals
+  next_sendPacketGnt <= sendPacketGnt;
+  next_muxDCEn <= muxDCEn;
+  next_directCntlGnt <= directCntlGnt;
+  case (CurrState_SCTxArb)
+    `SARB1_WAIT_REQ:
+      if (sendPacketReq == 1'b1)	
+      begin
+        NextState_SCTxArb <= `SARB_SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxDCEn <= 1'b0;
+      end
+      else if (directCntlReq == 1'b1)	
+      begin
+        NextState_SCTxArb <= `SARB_DC;
+        next_directCntlGnt <= 1'b1;
+        next_muxDCEn <= 1'b1;
+      end
+    `SARB_SEND_PACKET:
+      if (sendPacketReq == 1'b0)	
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    `SARB_DC:
+      if (directCntlReq == 1'b0)	
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    `START_SARB:
+      NextState_SCTxArb <= `SARB1_WAIT_REQ;
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_CurrentState
+  if (rst)	
+    CurrState_SCTxArb <= `START_SARB;
+  else
+    CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_RegOutput
+  if (rst)	
+  begin
+    muxDCEn <= 1'b0;
+    sendPacketGnt <= 1'b0;
+    directCntlGnt <= 1'b0;
+  end
+  else 
+  begin
+    muxDCEn <= next_muxDCEn;
+    sendPacketGnt <= next_sendPacketGnt;
+    directCntlGnt <= next_directCntlGnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/sctxportarbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v	(revision 264)
@@ -0,0 +1,357 @@
+
+// File        : ../RTL/slaveController/slaveGetpacket.v
+// Generated   : 11/10/06 05:37:25
+// From        : ../RTL/slaveController/slaveGetpacket.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveGetPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst);
+input   [7:0] RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0] RXStreamStatusIn;
+input   SIERxTimeOut;		// Single cycle pulse
+input   clk;
+input   endPointReady;
+input   getPacketEn;
+input   rst;
+output  ACKRxed;
+output  CRCError;
+output  [7:0] RXFifoData;
+output  RXFifoWEn;
+output  RXOverflow;
+output  RXPacketRdy;
+output  RXTimeOut;
+output  [3:0] RxPID;
+output  SIERxTimeOutEn;
+output  bitStuffError;
+output  dataSequence;
+
+reg     ACKRxed, next_ACKRxed;
+reg     CRCError, next_CRCError;
+wire    [7:0] RXDataIn;
+wire    RXDataValid;
+reg     [7:0] RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXOverflow, next_RXOverflow;
+reg     RXPacketRdy, next_RXPacketRdy;
+wire    [7:0] RXStreamStatusIn;
+reg     RXTimeOut, next_RXTimeOut;
+reg     [3:0] RxPID, next_RxPID;
+wire    SIERxTimeOut;
+reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
+reg     bitStuffError, next_bitStuffError;
+wire    clk;
+reg     dataSequence, next_dataSequence;
+wire    endPointReady;
+wire    getPacketEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
+
+reg [4:0] CurrState_slvGetPkt;
+reg [4:0] NextState_slvGetPkt;
+
+
+//--------------------------------------------------------------------
+// Machine: slvGetPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
+begin : slvGetPkt_NextState
+  NextState_slvGetPkt <= CurrState_slvGetPkt;
+  // Set default values for outputs and signals
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RXOverflow <= RXOverflow;
+  next_RXTimeOut <= RXTimeOut;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_SIERxTimeOutEn <= SIERxTimeOutEn;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RxPID <= RxPID;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXByteOldest <= RXByteOldest;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  case (CurrState_slvGetPkt)
+    `START_GP:
+      NextState_slvGetPkt <= `WAIT_EN;
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b1;
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (SIERxTimeOut == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `CHK_PKT_START:
+      if (RXStreamStatus == `RX_PACKET_START)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b0;
+      if (getPacketEn == 1'b1)	
+        NextState_slvGetPkt <= `WAIT_PKT;
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+      if (RXByte[1:0] == `HANDSHAKE)	
+        NextState_slvGetPkt <= `PROC_PKT_HS;
+      else if (RXByte[1:0] == `DATA)	
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+      else
+        NextState_slvGetPkt <= `PKT_RDY;
+    `PROC_PKT_HS:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    `PROC_PKT_DATA_W_D1:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    `PROC_PKT_DATA_CHK_D1:
+      if (RXStreamStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+    `PROC_PKT_DATA_W_D2:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_slvGetPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+      if (RXStreamStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+    `PROC_PKT_DATA_W_D3:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    `PROC_PKT_DATA_CHK_D3:
+      if (RXStreamStatus == `RX_PACKET_STREAM)	
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      else
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+      if (endPointReady == 1'b0)	
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
+      else if (RXFifoFull == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+      end
+      else if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    `PROC_PKT_DATA_LOOP_EP_N_RDY:    // Discard data
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_CurrentState
+  if (rst)	
+    CurrState_slvGetPkt <= `START_GP;
+  else
+    CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_RegOutput
+  if (rst)	
+  begin
+    RXByteOld <= 8'h00;
+    RXByteOldest <= 8'h00;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RXOverflow <= 1'b0;
+    RXTimeOut <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    SIERxTimeOutEn <= 1'b0;
+    RxPID <= 4'h0;
+  end
+  else 
+  begin
+    RXByteOld <= next_RXByteOld;
+    RXByteOldest <= next_RXByteOldest;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXPacketRdy <= next_RXPacketRdy;
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RXOverflow <= next_RXOverflow;
+    RXTimeOut <= next_RXTimeOut;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    SIERxTimeOutEn <= next_SIERxTimeOutEn;
+    RxPID <= next_RxPID;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/slaveGetpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/slavecontroller.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/slavecontroller.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/slavecontroller.asf	(revision 264)
@@ -0,0 +1,408 @@
+VERSION=1.15
+HEADER
+FILE="slavecontroller.asf"
+FID=403fbdc7
+LANGUAGE=VERILOG
+ENTITY="slavecontroller"
+FRAMES=ON
+FREEOID=863
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveController\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+END
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+C 614 612 0 TEXT "Conditions" | 62794,182643 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+A 615 612 16 TEXT "Actions" | 138346,155279 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+L 616 617 0 TEXT "State Labels" | 50796,174902 1 0 0 "J2"
+S 617 589 57364 ELLIPSE "Junction" | 50796,174902 3500 3500
+H 618 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 619 618 0 Builtin Entry | 96520,152400
+I 620 618 0 Builtin Exit | 144780,101600
+W 621 618 0 619 620 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+L 80 81 0 TEXT "State Labels" | 63570,37922 1 0 0 "FIN_SC\n/1/"
+S 81 6 4096 ELLIPSE "States" | 63211,37922 6500 6500
+W 82 6 0 15 41 BEZIER "Transitions" | 111847,183487 114548,179878 117251,176267 119952,172658
+W 83 6 0 41 376 BEZIER "Transitions" | 122170,161331 124629,151114 122118,150575 124577,140358
+W 630 589 8193 617 820 BEZIER "Transitions" | 48004,172793 44616,170945 44594,164562 42823,162021\
+                                              41052,159480 41752,153900 40959,141711 40167,129522\
+                                              46701,89176 50135,78506 53570,67837 54978,65340\
+                                              57981,65109 60984,64878 60458,64813 61074,64659
+W 631 589 8194 617 820 BEZIER "Transitions" | 54078,173688 59930,171532 83885,163128 122946,146882\
+                                              162008,130636 151291,117855 140238,106874 129185,95894\
+                                              77774,78896 71279,71294
+C 636 630 0 TEXT "Conditions" | 35003,128975 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0"
+A 637 630 16 TEXT "Actions" | 47297,102245 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA0;"
+A 638 631 16 TEXT "Actions" | 117990,107831 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `DATA1;"
+I 96 722 0 Builtin Reset | 76296,129336
+W 97 722 0 96 723 BEZIER "Transitions" | 76296,129336 85450,126984 105102,130518 114256,128166
+C 98 83 0 TEXT "Conditions" | 135898,150246 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_START && \nRxByte[1:0] == `TOKEN"
+L 375 376 0 TEXT "State Labels" | 127082,135048 1 0 0 "GET_TOKEN"
+S 376 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 127085,134364 6500 6500
+H 377 376 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 380 377 0 Builtin Entry | 48940,236580
+I 381 377 0 Builtin Exit | 206487,14249
+I 649 559 0 Builtin Entry | 37971,243103
+I 650 559 0 Builtin Exit | 194044,45058
+W 651 559 8193 654 656 BEZIER "Transitions" | 98921,152700 206574,151900 173740,105072 113816,89949
+C 652 651 0 TEXT "Conditions" | 116707,136533 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0"
+W 653 559 8192 649 690 BEZIER "Transitions" | 42267,243103 56803,242798 88976,238518 92493,238212
+S 654 559 61440 ELLIPSE "States" | 92422,152802 6500 6500
+L 655 654 0 TEXT "State Labels" | 92422,152802 1 0 0 "CHK\n/11/"
+S 384 377 12288 ELLIPSE "States" | 116864,202628 6500 6500
+L 385 384 0 TEXT "State Labels" | 117245,202194 1 0 0 "WAIT_ADDR\n/3/"
+W 388 377 8193 384 392 BEZIER "Transitions" | 117619,196179 118049,188396 118224,180484 118654,172701
+C 389 388 0 TEXT "Conditions" | 120725,194517 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+S 392 377 8192 ELLIPSE "States" | 120690,166529 6500 6500
+L 393 392 0 TEXT "State Labels" | 120066,166529 1 0 0 "WAIT_CRC\n/2/"
+A 394 388 16 TEXT "Actions" | 109989,182895 1 0 0 "addrEndPTemp <= RxByte;"
+L 398 399 0 TEXT "Labels" | 56547,17304 1 0 0 "WAIT_RX1"
+I 399 377 0 Builtin Link | 54419,17564
+S 656 559 65536 ELLIPSE "States" | 109789,85208 5889 6500
+A 657 656 4 TEXT "Actions" | 131151,85140 1 0 0 "sendPacketWEn <= 1'b0;"
+W 658 559 8192 656 650 BEZIER "Transitions" | 115135,82483 143029,70601 162928,56940 190822,45058
+A 659 651 16 TEXT "Actions" | 154655,125925 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `NAK;\nNAKSent <= 1'b1;"
+L 661 656 0 TEXT "State Labels" | 110208,84806 1 0 0 "SEND\n/12/"
+W 664 559 8194 654 656 BEZIER "Transitions" | 93066,146337 91981,138849 92975,108162 108216,91470
+A 665 664 16 TEXT "Actions" | 80842,130315 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `STALL;\nstallSent <= 1'b1;"
+C 666 664 0 TEXT "Conditions" | 53275,145515 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1"
+C 660 658 0 TEXT "Conditions" | 106335,67684 1 0 0 "sendPacketRdy == 1'b1"
+W 400 377 8194 384 399 BEZIER "Transitions" | 110498,201318 102308,200382 54233,209312 50372,191138\
+                                              46511,172964 33727,90292 34975,71611 36223,52930\
+                                              35724,34993 37785,28932 39847,22872 46307,16188\
+                                              54419,15564
+C 401 400 0 TEXT "Conditions" | 52882,213899 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+L 402 403 0 TEXT "State Labels" | 124030,135117 1 0 0 "WAIT_STOP\n/4/"
+S 403 377 16384 ELLIPSE "States" | 124030,135117 6500 6500
+W 404 377 8193 392 403 BEZIER "Transitions" | 121200,160058 121710,155348 122669,146268 123179,141558
+C 405 404 0 TEXT "Conditions" | 124159,160729 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus == `RX_PACKET_STREAM"
+W 406 377 8194 392 399 BEZIER "Transitions" | 114191,166474 101160,166788 74889,166988 67471,166085\
+                                              60053,165183 57484,160822 55722,148570 53960,136319\
+                                              36935,95064 38880,77714 40826,60365 38327,20823\
+                                              54419,15564
+C 409 406 0 TEXT "Conditions" | 56206,176408 1 0 0 "RxDataWEn == 1'b1 && \nRxStatus != `RX_PACKET_STREAM"
+A 410 404 16 TEXT "Actions" | 120222,150346 1 0 0 "endpCRCTemp <= RxByte;"
+W 416 377 0 380 384 BEZIER "Transitions" | 53236,236580 66436,236340 92720,236440 100440,234920\
+                                           108160,233400 112640,227800 113920,224400 115200,221000\
+                                           116013,213096 116333,209096
+L 419 420 0 TEXT "State Labels" | 125039,108996 1 0 0 "J1"
+S 420 377 20500 ELLIPSE "Junction" | 125039,108996 3500 3500
+H 421 420 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 422 421 0 Builtin Entry | 96520,152400
+I 423 421 0 Builtin Exit | 144780,101600
+W 424 421 0 422 423 BEZIER "Transitions" | 100816,152400 114662,136960 127711,117040 141558,101600
+W 425 377 0 403 420 BEZIER "Transitions" | 125217,128730 124944,123298 124669,117866 124396,112434
+C 426 425 0 TEXT "Conditions" | 126599,128290 1 0 0 "RxDataWEn == 1'b1"
+W 427 377 8194 420 399 BEZIER "Transitions" | 121546,109207 108910,108883 84850,107106 77399,105791\
+                                              69948,104476 47394,95074 43302,84878 39210,74682\
+                                              42917,24960 54419,15564
+W 431 377 8193 420 508 BEZIER "Transitions" | 124244,105590 124829,100936 125414,96281 125999,91627
+A 688 653 16 TEXT "Actions" | 49697,242131 1 0 0 "getPacketREn <= 1'b1;"
+L 689 690 0 TEXT "State Labels" | 98991,238090 1 0 0 "GET_PKT\n/13/"
+S 690 559 69632 ELLIPSE "States" | 98991,238090 6500 6500
+A 691 690 4 TEXT "Actions" | 108619,243631 1 0 0 "getPacketREn <= 1'b0;"
+W 692 559 8194 698 654 BEZIER "Transitions" | 115978,206479 88070,190212 85643,190437 93781,159154
+C 693 692 0 TEXT "Conditions" | 66756,183110 1 0 0 "CRCError == 1'b0 &&\nbitStuffError == 1'b0 && \nRxOverflow == 1'b0 && \nRxTimeOut == 1'b0"
+W 694 559 8195 654 656 BEZIER "Transitions" | 85930,152497 74648,152804 51806,152609 45513,150767\
+                                              39220,148925 36609,140943 36571,133460 36533,125977\
+                                              38989,104026 47738,97617 56488,91209 87662,87731\
+                                              103933,85889
+A 695 694 16 TEXT "Actions" | 32235,126207 1 0 0 "sendPacketWEn <= 1'b1;\nsendPacketPID <= `ACK;"
+W 696 559 8195 698 650 BEZIER "Transitions" | 120484,209499 143962,203805 174018,217078 187161,210058\
+                                              200304,203038 205920,186346 207441,167119 208962,147892\
+                                              209430,87676 208962,71608 208494,55540 206154,51484\
+                                              204438,50041 202722,48598 199528,45916 197266,45058
+L 697 698 0 TEXT "State Labels" | 117000,209824 1 0 0 "J3"
+S 698 559 73748 ELLIPSE "Junction" | 117000,209824 3500 3500
+H 699 698 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+I 700 699 0 Builtin Entry | 96520,152400
+I 701 699 0 Builtin Exit | 144780,101600
+W 702 699 0 700 701 BEZIER "Transitions" | 100816,152400 114718,136923 127655,117078 141558,101600
+W 703 559 0 690 698 BEZIER "Transitions" | 102158,232416 105512,227268 111593,217805 114947,212657
+C 432 431 0 TEXT "Conditions" | 128096,105689 1 0 0 "RxByte[`CRC_ERROR_BIT] == 1'b0 &&\nRxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&\nRxByte [`RX_OVERFLOW_BIT] == 1'b0"
+L 443 444 0 TEXT "State Labels" | 127565,109879 1 0 0 "CHK_PID\n/5/"
+S 444 6 24576 ELLIPSE "States" | 127565,109879 6500 6500
+C 704 703 0 TEXT "Conditions" | 106392,230416 1 0 0 "getPacketRdy == 1'b1"
+W 457 377 8193 462 381 BEZIER "Transitions" | 100978,49712 129304,39439 174939,24522 203265,14249
+W 461 377 8194 508 786 BEZIER "Transitions" | 125260,78741 125862,71938 126464,65135 127066,58332
+S 462 377 94208 ELLIPSE "States" | 94684,51331 6500 6500
+L 463 462 0 TEXT "State Labels" | 94684,51331 1 0 0 "CHK_ADDR\n/16/"
+H 722 15 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 723 722 81920 ELLIPSE "States" | 120650,127000 6500 6500
+L 724 723 0 TEXT "State Labels" | 120650,127000 1 0 0 "S1\n/14/"
+A 725 723 2 TEXT "Actions" | 132523,206729 1 0 0 "transDone <= 1'b0;\nclearEPRdy <= 1'b0;\ngetPacketREn <= 1'b0;\nsendPacketPID <= 4'b0;\nsendPacketWEn <= 1'b0;\nclrEPRdy <= 1'b0\nUSBEndPTransTypeReg <= 2'b00;\nUSBEndPNakTransTypeReg <= 2'b00;\ntempUSBEndPTransTypeReg <= 2'b00;\nNAKSent <= 1'b0;\nstallSent <= 1'b0;\nendPMuxErrorsWEn <= 1'b0;\naddrEndPTemp <= 8'h00;\nendpCRCTemp <= 8'h00;\nUSBAddress <= 7'b0000000;\nUSBEndP <= 4'h0;\nframeNum <= 11'b00000000000;\nSOFRxed <= 1'b0;\nPIDByte <= 8'h00;\nUSBEndPControlRegCopy <= 5'b00000;\nendPointReadyToGetPkt <= 1'b0;"
+I 726 722 0 Builtin Entry | 96520,152400
+I 727 722 0 Builtin Exit | 144780,101600
+W 728 722 0 726 723 BEZIER "Transitions" | 100816,152400 106104,146248 111125,138081 116414,131928
+W 729 722 0 723 727 BEZIER "Transitions" | 125025,122194 130662,116001 135921,107794 141558,101600
+L 730 731 0 TEXT "Labels" | 189218,228230 1 0 0 "CRCError"
+I 731 0 2 Builtin InPort | 183218,228230 "" ""
+L 732 733 0 TEXT "Labels" | 189218,223490 1 0 0 "bitStuffError"
+I 733 0 2 Builtin InPort | 183218,223490 "" ""
+L 734 735 0 TEXT "Labels" | 189218,218987 1 0 0 "RxTimeOut"
+I 735 0 2 Builtin InPort | 183218,218987 "" ""
+C 468 457 0 TEXT "Conditions" | 82804,40533 1 0 0 "USBEndP < `NUM_OF_ENDPOINTS  &&\nUSBAddress == USBTgtAddress &&\nSCGlobalEn == 1'b1 &&\nUSBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1"
+L 736 737 0 TEXT "Labels" | 189455,232970 1 0 0 "RxOverflow"
+I 737 0 2 Builtin InPort | 183455,232970 "" ""
+L 742 743 0 TEXT "Labels" | 125778,227003 1 0 0 "USBEndP[3:0]"
+I 743 0 130 Builtin OutPort | 119778,227003 "" ""
+L 744 745 0 TEXT "Labels" | 35748,252068 1 0 0 "SCGlobalEn"
+I 745 0 2 Builtin InPort | 29748,252068 "" ""
+L 746 747 0 TEXT "Labels" | 35748,247328 1 0 0 "USBTgtAddress[6:0]"
+I 747 0 130 Builtin InPort | 29748,247328 "" ""
+L 748 749 0 TEXT "Labels" | 128043,237048 1 0 0 "USBEndPControlReg[4:0]"
+I 749 0 130 Builtin InPort | 122043,237048 "" ""
+L 750 751 0 TEXT "Labels" | 80282,236074 1 0 0 "NAKSent"
+I 751 0 2 Builtin OutPort | 74282,236074 "" ""
+I 767 0 2 Builtin InPort | 77236,251752 "" ""
+L 766 767 0 TEXT "Labels" | 83236,251752 1 0 0 "RxDataWEn"
+I 765 0 130 Builtin Signal | 120578,208940 "" ""
+L 764 765 0 TEXT "Labels" | 123578,208940 1 0 0 "tempUSBEndPTransTypeReg[1:0]"
+L 752 753 0 TEXT "Labels" | 79882,231167 1 0 0 "stallSent"
+I 753 0 2 Builtin OutPort | 73882,231167 "" ""
+L 754 755 0 TEXT "Labels" | 125826,241925 1 0 0 "USBEndPTransTypeReg[1:0]"
+I 755 0 130 Builtin OutPort | 119826,241925 "" ""
+L 756 757 0 TEXT "Labels" | 125853,246737 1 0 0 "USBEndPNakTransTypeReg[1:0]"
+I 757 0 130 Builtin OutPort | 119853,246737 "" ""
+L 758 759 0 TEXT "Labels" | 125476,231925 1 0 0 "endPMuxErrorsWEn"
+I 759 0 2 Builtin OutPort | 119476,231925 "" ""
+A 763 41 68 TEXT "Actions" | 141963,177130 1 0 0 "stallSent <= 1'b0;\nNAKSent <= 1'b0;\nSOFRxed <= 1'b0;"
+I 783 0 130 Builtin Signal | 83088,208940 "" ""
+L 782 783 0 TEXT "Labels" | 86088,208940 1 0 0 "USBAddress[6:0]"
+I 781 0 2 Builtin OutPort | 28572,224032 "" ""
+L 780 781 0 TEXT "Labels" | 34572,224032 1 0 0 "SOFRxed"
+I 779 0 130 Builtin OutPort | 28880,219720 "" ""
+L 778 779 0 TEXT "Labels" | 34880,219720 1 0 0 "frameNum[10:0]"
+I 777 0 130 Builtin Signal | 120664,221876 "" ""
+L 776 777 0 TEXT "Labels" | 123664,221876 1 0 0 "addrEndPTemp[7:0]"
+I 775 0 130 Builtin Signal | 120664,217872 "" ""
+L 774 775 0 TEXT "Labels" | 123664,217872 1 0 0 "endpCRCTemp[7:0]"
+I 773 0 130 Builtin Signal | 120664,213560 "" ""
+L 772 773 0 TEXT "Labels" | 123664,213560 1 0 0 "PIDByte[7:0]"
+I 771 0 130 Builtin InPort | 76928,242820 "" ""
+L 770 771 0 TEXT "Labels" | 82928,242820 1 0 0 "RxByte[7:0]"
+I 769 0 130 Builtin InPort | 77236,247440 "" ""
+L 768 769 0 TEXT "Labels" | 83236,247440 1 0 0 "RxStatus[7:0]"
+A 502 461 16 TEXT "Actions" | 125613,71590 1 0 0 "USBAddress <= addrEndPTemp[6:0];\nUSBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]} ;"
+L 507 508 0 TEXT "State Labels" | 124896,85224 1 0 0 "CHK_SOF\n/6/"
+S 508 377 28672 ELLIPSE "States" | 124896,85224 6500 6500
+W 509 377 8193 508 399 BEZIER "Transitions" | 118401,84993 100664,84333 64762,83050 55811,78512\
+                                              46860,73975 46530,57145 47396,48771 48262,40398\
+                                              52522,23896 54419,15564
+C 510 509 0 TEXT "Conditions" | 63200,88160 1 0 0 "PIDByte[3:0] == `SOF"
+A 511 509 16 TEXT "Actions" | 43897,75831 1 0 0 "frameNum <= {endpCRCTemp[2:0],addrEndPTemp};\nSOFRxed <= 1'b1;"
+W 784 6 8195 531 81 BEZIER "Transitions" | 199428,57678 201969,56523 206519,54247 207866,48664\
+                                           209214,43082 209522,23062 208983,17094 208444,11127\
+                                           205980,7277 191773,6353 177567,5429 123205,5583\
+                                           106804,9317 90403,13052 79161,27836 75696,31763\
+                                           72231,35690 70888,36159 69579,36621
+W 512 377 8194 462 399 BEZIER "Transitions" | 88426,49577 72698,46423 68764,43598 61315,39137\
+                                              53866,34676 56339,23332 57169,17564
+W 514 6 8193 444 551 BEZIER "Transitions" | 121093,109287 106000,107942 75635,105075 68176,101390\
+                                            60717,97705 62441,84600 62616,78575
+W 515 6 8194 444 551 BEZIER "Transitions" | 125173,103837 123535,98514 118808,88227 112022,84659\
+                                            105236,81091 81842,75191 69908,73378
+W 516 6 8195 444 580 BEZIER "Transitions" | 133157,106567 143277,99957 161264,87392 171384,80782
+W 517 6 0 376 444 BEZIER "Transitions" | 126740,127881 127032,124839 126993,119409 127285,116367
+C 518 514 0 TEXT "Conditions" | 68498,113792 1 0 0 "PIDByte[3:0] == `SETUP"
+C 519 515 0 TEXT "Conditions" | 96466,92704 1 0 0 "PIDByte[3:0] == `OUT"
+A 521 515 16 TEXT "Actions" | 72876,85256 1 0 0 "tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;"
+A 522 514 16 TEXT "Actions" | 34060,103488 1 0 0 "tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;"
+C 523 516 0 TEXT "Conditions" | 138452,109100 1 0 0 "PIDByte[3:0] == `IN"
+L 525 526 0 TEXT "State Labels" | 84644,142808 1 0 0 "PID_ERROR\n/7/"
+S 526 6 32768 ELLIPSE "States" | 84644,142808 6500 6500
+W 527 6 8196 444 526 BEZIER "Transitions" | 122444,113881 113611,119906 98358,132491 89525,138516
+A 524 516 16 TEXT "Actions" | 132740,96932 1 0 0 "tempUSBEndPTransTypeReg <= `SC_IN_TRANS;"
+L 785 786 0 TEXT "State Labels" | 123152,53144 1 0 0 "DELAY\n/15/"
+S 786 377 90112 ELLIPSE "States" | 123152,53144 6500 6500
+W 787 377 0 786 462 BEZIER "Transitions" | 116687,52476 112749,52476 105105,51800 101167,51800
+K 788 786 0 TEXT "Comments" | 122196,51478 1 0 0 "Insert delay to allow USBEndP etc to update"
+W 790 559 1 698 650 BEZIER "Transitions" | 120235,208489 139440,201809 176211,187874 186899,181444\
+                                           197587,175015 201929,162657 202973,147251 204017,131846\
+                                           203849,82580 202847,68719 201846,54859 198970,48147\
+                                           197050,45058
+C 791 790 0 TEXT "Conditions" | 102423,188540 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1"
+L 263 264 0 TEXT "Labels" | 79978,216725 1 0 0 "clrEPRdy"
+I 264 0 2 Builtin OutPort | 74329,216725 "" ""
+L 265 266 0 TEXT "Labels" | 79978,226532 1 0 0 "transDone"
+I 266 0 2 Builtin OutPort | 74329,226532 "" ""
+L 269 270 0 TEXT "Labels" | 34450,240616 1 0 0 "sendPacketPID[3:0]"
+I 270 0 130 Builtin OutPort | 28450,240616 "" ""
+I 271 0 2 Builtin OutPort | 180979,209022 "" ""
+W 529 6 0 526 41 BEZIER "Transitions" | 89828,146728 97140,151466 110862,159936 118174,164674
+L 530 531 0 TEXT "State Labels" | 193752,60844 1 0 0 "CHK_RDY\n/8/"
+S 531 6 36864 ELLIPSE "States" | 193752,60844 6500 6500
+W 532 6 8193 531 81 BEZIER "Transitions" | 187378,59573 161170,57818 95812,40849 69604,39094
+W 533 6 0 580 531 BEZIER "Transitions" | 181097,72204 183278,69441 186374,67510 188555,64747
+W 534 6 0 551 531 BEZIER "Transitions" | 69967,71266 96526,67873 160748,65078 187307,61685
+C 535 532 0 TEXT "Conditions" | 69699,59883 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+A 536 532 16 TEXT "Actions" | 87626,51585 1 0 0 "transDone <= 1'b1;\nclrEPRdy <= 1'b1;\nUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;\nendPMuxErrorsWEn <= 1'b1;"
+H 805 800 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,251000
+S 800 589 98324 ELLIPSE "Junction" | 108538,243174 3500 3500
+L 801 800 0 TEXT "State Labels" | 108538,243174 1 0 0 "J4"
+W 802 805 0 804 803 BEZIER "Transitions" | 100816,152400 114862,136691 127511,117310 141558,101600
+I 803 805 0 Builtin Exit | 144780,101600
+I 804 805 0 Builtin Entry | 96520,152400
+W 807 589 2 800 617 BEZIER "Transitions" | 106097,240666 80398,219718 50449,190675 50573,178391
+W 810 589 3 800 587 BEZIER "Transitions" | 105040,243281 73377,254491 34925,221320 34178,196665\
+                                           33432,172010 34721,79558 53522,54375 72324,29193\
+                                           153226,30396 173104,33029 192983,35662 193169,40577\
+                                           192962,43440
+C 812 807 0 TEXT "Conditions" | 65637,235739 1 0 0 "USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1"
+END

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/slavecontroller.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/wrapper/usbHostCyc2Wrap.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/wrapper/usbHostCyc2Wrap.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/wrapper/usbHostCyc2Wrap.v	(revision 264)
@@ -0,0 +1,147 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostCyc2Wrap.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+
+module usbHostCyc2Wrap(
+  clk_i, 
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  irq, 
+  usbClk,
+  USBWireVP,
+  USBWireVM,
+  USBWireOE_n,
+  USBFullSpeed
+   );
+
+input clk_i;
+input rst_i;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input we_i; 
+input strobe_i;
+output ack_o;
+output irq; 
+input usbClk;
+inout USBWireVP /* synthesis useioff=1 */;
+inout USBWireVM /* synthesis useioff=1 */;
+output USBWireOE_n /* synthesis useioff=1 */;
+output USBFullSpeed /* synthesis useioff=1 */;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire irq;
+wire usbClk;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBFullSpeed;
+
+//internal wiring 
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+             hostResumeIntOut | hostTransDoneIntOut;
+
+assign USBWireDataIn = {USBWireVP, USBWireVM};
+assign {USBWireVP, USBWireVM} = (USBWireCtrlOut == 1'b1) ? USBWireDataOut : 2'bzz;
+assign USBWireOE_n = ~USBWireCtrlOut;
+
+//Parameters declaration: 
+defparam usbHostInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+
+usbHost usbHostInst (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .address_i(address_i),
+  .data_i(data_i),
+  .data_o(data_o),
+  .we_i(we_i),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .usbClk(usbClk),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/RTL/include/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/include/usbHostControl_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/include/usbHostControl_h.v	(revision 264)
@@ -0,0 +1,74 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v                                          
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HOST_SOF_TIMER_MSB_REG 4'hf
+
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+`define ISO_ENABLE_BIT 3
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+ 
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants 
+//Note that 'SOF_TX_TIME' is 48000 - 7. This is to account for the delay in resetting the SOF timer 
+`define SOF_TX_TIME 16'hbb79     //Correct SOF interval for 48MHz clock.
+`define SOF_TX_MARGIN 16'h0c80 //This is the transmission time for 100 bytes at full speed
+`define SOF_TX_MARGIN_LOW_SPEED 16'h6400 //100 bytes at low speed
+       
+//Host RXStatusRegIndices 
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined 

Property changes on: common/components/usbhostslave/trunk/RTL/include/usbHostControl_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/include/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/include/wishBoneBus_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/include/wishBoneBus_h.v	(revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+ 
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+

Property changes on: common/components/usbhostslave/trunk/RTL/include/wishBoneBus_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.asf	(revision 264)
@@ -0,0 +1,315 @@
+VERSION=1.15
+HEADER
+FILE="processRxBit.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processRxBit"
+FRAMES=ON
+FREEOID=258
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processrxbit\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n"
+END
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+L 96 97 0 TEXT "State Labels" | 66418,142124 1 0 0 "DATA"
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+C 121 118 0 TEXT "Conditions" | 90285,92809 1 0 0 "bitStuffError == 1'b1"
+C 120 117 0 TEXT "Conditions" | 17125,90667 1 0 0 "RXBitCount == 4'h8 & bitStuffError == 1'b0"
+W 119 32 8195 227 86 BEZIER "Transitions" | 70866,112476 88554,110332 126022,106808 138752,96624\
+                                            151482,86440 167580,47791 175352,29567
+W 118 32 8194 227 115 BEZIER "Transitions" | 69923,110435 79839,101323 101636,81685 111552,72573
+W 117 32 8193 227 113 BEZIER "Transitions" | 65361,109992 60269,101550 49374,82448 44282,74006
+W 116 32 0 83 86 BEZIER "Transitions" | 88704,188128 110546,183706 152420,173406 164480,164897\
+                                        176540,156388 181096,131196 181431,113977 181766,96758\
+                                        182570,51409 180962,29567
+S 115 32 53252 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116374,68216 6500 6500
+L 114 115 0 TEXT "State Labels" | 116374,68216 1 0 0 "ERROR"
+S 113 32 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 41334,68216 6500 6500
+L 112 113 0 TEXT "State Labels" | 41334,68216 1 0 0 "BYTE"
+L 143 142 0 TEXT "State Labels" | 68810,217727 1 0 0 "WAIT_RDY\n/8/"
+S 142 122 61440 ELLIPSE "States" | 68810,217727 6500 6500
+A 141 136 4 TEXT "Actions" | 98360,168539 1 0 0 "processRxByteWEn <= 1'b0;"
+W 140 122 0 136 139 BEZIER "Transitions" | 87355,157633 92394,150615 96149,127199 101189,120181
+I 139 122 0 Builtin Exit | 103994,120181
+I 138 122 0 Builtin Entry | 32350,235287
+L 137 136 0 TEXT "State Labels" | 83564,162911 1 0 0 "SEND2\n/7/"
+S 136 122 57344 ELLIPSE "States" | 83564,162911 6500 6500
+H 129 115 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 159 129 0 155 251 BEZIER "Transitions" | 47328,237621 58765,237907 69242,234957 80679,235243
+L 156 151 0 TEXT "State Labels" | 70001,162635 1 0 0 "CHK_RES\n/10/"
+I 155 129 0 Builtin Entry | 43437,237621
+I 154 129 0 Builtin Exit | 115081,122515
+W 153 129 0 151 154 BEZIER "Transitions" | 75624,159375 80663,152357 107236,129533 112276,122515
+A 152 151 4 TEXT "Actions" | 94367,174643 1 0 0 "processRxByteWEn <= 1'b0;\nif (RxBits == JBit)                           //if current bit is a JBit, then\n  RXBitStMachCurrState <= `IDLE_BIT_ST;       //next state is idle\nelse                                          //else\nbegin\n  RXBitStMachCurrState <= `WAIT_RESUME_ST;    //check for resume\n  resumeWaitCnt <= 5'h0;                          \nend"
+S 151 129 65536 ELLIPSE "States" | 70001,162635 6500 6500
+A 148 144 16 TEXT "Actions" | 66554,198501 1 0 0 "RXBitCount <= 4'h0;\nRxDataOut <= RXByte;       \nRxCtrlOut <= `DATA_STREAM; \nprocessRxByteWEn <= 1'b1;"
+W 147 122 0 138 142 BEZIER "Transitions" | 36241,235287 40301,228400 58702,226995 62762,220108
+W 144 122 4096 142 136 BEZIER "Transitions" | 70118,211361 75926,204431 73609,174845 79417,167915
+I 175 0 130 Builtin OutPort | 78804,245816 "" ""
+L 174 175 0 TEXT "Labels" | 84804,245816 1 0 0 "RxCtrlOut[7:0]"
+I 173 0 130 Builtin OutPort | 79602,240762 "" ""
+L 172 173 0 TEXT "Labels" | 85602,240762 1 0 0 "RxDataOut[7:0]"
+I 171 0 2 Builtin OutPort | 78239,230321 "" ""
+L 170 171 0 TEXT "Labels" | 84239,230321 1 0 0 "resumeDetected"
+A 169 167 4 TEXT "Actions" | 55436,189333 1 0 0 "if (RxBits != KBit)  //line must leave KBit state for the end of resume\nbegin\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\n  resumeDetected <= 1'b0;   //clear resume detected flag\nend"
+L 168 167 0 TEXT "State Labels" | 117624,117720 1 0 0 "CHK1\n/11/"
+S 167 50 69632 ELLIPSE "States" | 117624,117720 6500 6500
+I 166 50 0 Builtin Entry | 96034,145660
+I 165 50 0 Builtin Exit | 139214,89780
+W 164 50 0 166 167 BEZIER "Transitions" | 99925,145660 104656,138676 109248,130084 113979,123100
+W 163 50 0 167 165 BEZIER "Transitions" | 121415,112442 126454,105424 131369,96798 136409,89780
+A 162 40 4 TEXT "Actions" | 29424,246323 1 0 0 "if (RxBits != KBit)  //can only be a resume if line remains in Kbit state\n  RXBitStMachCurrState <= `IDLE_BIT_ST;\nelse \nbegin\n  resumeWaitCnt <= resumeWaitCnt + 1'b1; \n  //if we've waited long enough, then\n  if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)\n  begin	\n    RXBitStMachCurrState <= `RESUME_END_WAIT_ST; \n    resumeDetected <= 1'b1;  //report resume detected\n  end\nend"
+W 161 32 0 113 86 BEZIER "Transitions" | 45583,63298 57777,53382 79524,32408 93292,27115\
+                                         107061,21822 137747,20482 148467,20415 159187,20348\
+                                         171381,21420 174463,22458 177545,23497 178090,26035\
+                                         178157,27576
+W 160 32 0 115 86 BEZIER "Transitions" | 119806,62698 125032,57070 133928,45540 139522,41252\
+                                         145117,36964 157043,31068 161599,29627 166155,28187\
+                                         172203,29500 175352,29567
+A 191 9 4 TEXT "Actions" | 132502,217743 1 0 0 "processRxByteWEn <= 1'b0;\nRxCtrlOut <= 8'h00;\nRxDataOut <= 8'h00;\nresumeDetected <= 1'b0;\nRXBitStMachCurrState <= `IDLE_BIT_ST;\nRxBits <= 2'b00;\nRXSameBitCount <= 4'h0;\nRXBitCount <= 4'h0;\noldRXBits <= 2'b00;\nRXByte <= 8'h00;\nbitStuffError <= 1'b0;\nresumeWaitCnt <= 5'h0;\nprocessRxBitRdy <= 1'b1;"
+C 188 13 0 TEXT "Conditions" | 26243,187081 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 183608,259648 "" ""
+L 186 187 0 TEXT "Labels" | 189608,259648 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 183608,264702 "" ""
+L 184 185 0 TEXT "Labels" | 189608,264702 1 0 0 "clk"
+I 183 0 130 Builtin InPort | 152486,239964 "" ""
+L 182 183 0 TEXT "Labels" | 158486,239964 1 0 0 "KBit[1:0]"
+I 181 0 2 Builtin InPort | 152486,249540 "" ""
+L 180 181 0 TEXT "Labels" | 158486,249540 1 0 0 "processRxBitsWEn"
+I 179 0 130 Builtin InPort | 152752,245018 "" ""
+L 178 179 0 TEXT "Labels" | 158752,245018 1 0 0 "RxBitsIn[1:0]"
+I 177 0 2 Builtin OutPort | 78272,250604 "" ""
+L 176 177 0 TEXT "Labels" | 84272,250604 1 0 0 "processRxByteWEn"
+I 207 0 2 Builtin Signal | 18806,227486 "" ""
+L 206 207 0 TEXT "Labels" | 21806,227486 1 0 0 "bitStuffError"
+I 205 0 130 Builtin Signal | 18834,232706 "" ""
+L 204 205 0 TEXT "Labels" | 21834,232706 1 0 0 "RXByte[7:0]"
+I 203 0 130 Builtin Signal | 18561,238021 "" ""
+L 202 203 0 TEXT "Labels" | 21561,238021 1 0 0 "oldRXBits[1:0]"
+I 201 0 130 Builtin Signal | 19264,243362 "" ""
+L 200 201 0 TEXT "Labels" | 22264,243362 1 0 0 "RXBitCount[3:0]"
+I 199 0 130 Builtin Signal | 18422,248742 "" ""
+L 198 199 0 TEXT "Labels" | 21422,248742 1 0 0 "RXSameBitCount[3:0]"
+I 197 0 130 Builtin Signal | 18422,253264 "" ""
+L 196 197 0 TEXT "Labels" | 21422,253264 1 0 0 "RxBits[1:0]"
+I 193 0 130 Builtin Signal | 18954,263638 "" ""
+L 192 193 0 TEXT "Labels" | 21954,263638 1 0 0 "RXBitStMachCurrState[1:0]"
+I 211 0 130 Builtin Signal | 78080,259259 "" ""
+L 210 211 0 TEXT "Labels" | 81080,259259 1 0 0 "resumeWaitCnt[4:0]"
+L 209 208 0 TEXT "Labels" | 158667,234292 1 0 0 "JBit[1:0]"
+I 208 0 130 Builtin InPort | 152667,234292 "" ""
+L 212 213 0 TEXT "State Labels" | 42588,157720 1 0 0 "J1"
+S 213 6 73748 ELLIPSE "Junction" | 42588,157720 3500 3500
+H 214 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 215 214 0 Builtin Entry | 86360,167640
+I 216 214 0 Builtin Exit | 129540,111760
+W 217 214 0 215 216 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 218 219 0 TEXT "State Labels" | 164672,85946 1 0 0 "J2"
+S 219 6 77844 ELLIPSE "Junction" | 164672,85946 3500 3500
+H 220 219 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 221 220 0 Builtin Entry | 86360,167640
+I 222 220 0 Builtin Exit | 129540,111760
+W 223 220 0 221 222 BEZIER "Transitions" | 90251,167640 102382,150340 114603,129061 126735,111760
+L 226 227 0 TEXT "State Labels" | 67386,112844 1 0 0 "J3"
+S 227 32 81940 ELLIPSE "Junction" | 67386,112844 3500 3500
+H 228 227 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 229 228 0 Builtin Entry | 86360,167640
+I 230 228 0 Builtin Exit | 129540,111760
+W 231 228 0 229 230 BEZIER "Transitions" | 90251,167640 102488,150092 114497,129309 126735,111760
+L 232 233 0 TEXT "Labels" | 156002,229172 1 0 0 "processRxBitRdy"
+I 233 0 2 Builtin OutPort | 150002,229172 "" ""
+A 234 67 16 TEXT "Actions" | 139445,159206 1 0 0 "processRxBitRdy <= 1'b1;"
+A 237 102 2 TEXT "Actions" | 25628,249822 1 0 0 "if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then\nbegin\n  RXSameBitCount <= RXSameBitCount + 1'b1;  //inc 'RXSameBitCount'\n  if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error\n    bitStuffError <= 1'b1;                         //flag 'bitStuffError'\n  else                                          //else no bit stuffing error\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin\n      processRxBitRdy <= 1'b1;                   //early indication of ready\n	end\n    RXByte <= { 1'b1, RXByte[7:1]};              //RZ bit = 1 (ie no change in 'RxBits')\n  end\nend\nelse                                            //else current 'RxBits' are different from old 'RxBits'\nbegin\n  if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then\n  begin\n    RXBitCount <= RXBitCount + 1'b1;\n    if (RXBitCount != 4'h7) begin\n      processRxBitRdy <= 1'b1;	               //early indication of ready\n	end\n    RXByte <= {1'b0, RXByte[7:1]};             //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')\n  end\n   RXSameBitCount <= 4'h0;                      //reset 'RXSameBitCount'\nend\noldRXBits <= RxBits;"
+L 238 239 0 TEXT "Labels" | 158372,254090 1 0 0 "processRxByteRdy"
+I 239 0 2 Builtin InPort | 152372,254090 "" ""
+L 240 241 0 TEXT "State Labels" | 151892,179359 1 0 0 "WAIT_PRB_RDY\n/12/"
+S 241 17 86016 ELLIPSE "States" | 151892,179359 6500 6500
+W 242 17 8193 75 241 BEZIER "Transitions" | 83767,176813 93495,176723 135677,178559 145432,178646
+C 243 242 0 TEXT "Conditions" | 82407,188660 1 0 0 "(RxBits == KBit) && (RxWireActive == 1'b1)"
+C 244 76 0 TEXT "Conditions" | 137618,163943 1 0 0 "processRxByteRdy == 1'b1"
+L 245 246 0 TEXT "State Labels" | 123442,233426 1 0 0 "WAIT_PRB_RDY\n/13/"
+S 246 32 90112 ELLIPSE "States" | 123442,233426 6500 6500
+W 247 32 8193 89 246 BEZIER "Transitions" | 58283,227149 73079,228913 102192,230896 116988,232660
+C 248 247 0 TEXT "Conditions" | 63893,236141 1 0 0 "RxBits == `SE0"
+C 249 91 0 TEXT "Conditions" | 115810,224225 1 0 0 "processRxByteRdy == 1'b1"
+L 250 251 0 TEXT "State Labels" | 87178,235174 1 0 0 "WAIT_RDY\n/14/"
+S 251 129 94208 ELLIPSE "States" | 87178,235174 6500 6500
+W 252 129 0 251 151 BEZIER "Transitions" | 86179,228754 82949,208010 75931,189290 72701,168546
+C 253 252 0 TEXT "Conditions" | 86956,225452 1 0 0 "processRxByteRdy == 1'b1"
+A 254 252 16 TEXT "Actions" | 67337,205212 1 0 0 "RxDataOut <= 8'h00;       //redundant data\nRxCtrlOut <= `DATA_BIT_STUFF_ERROR; \nprocessRxByteWEn <= 1'b1;"
+C 255 144 0 TEXT "Conditions" | 72542,211451 1 0 0 "processRxByteRdy == 1'b1"
+I 257 0 2 Builtin InPort | 150840,260800 "" ""
+L 256 257 0 TEXT "Labels" | 156840,260800 1 0 0 "RxWireActive"
+END

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.asf	(revision 264)
@@ -0,0 +1,311 @@
+VERSION=1.15
+HEADER
+FILE="processTxByte.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="processTxByte"
+FRAMES=ON
+FREEOID=1126
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// processTxByte\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 12700,12700 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
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+PAGE 12700,12700 215900,279400
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
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+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
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+S 1100 1035 110592 ELLIPSE "States" | 52016,132400 6500 6500
+L 1099 1100 0 TEXT "State Labels" | 52016,132400 1 0 0 "W_RDY1\n/22/"
+W 1093 6 0 1034 874 BEZIER "Transitions" | 107126,38228 93109,49095 67454,69717 53517,80692
+C 1092 1091 0 TEXT "Conditions" | 145670,31298 1 0 0 "TxByteFullSpeedRate  == 1'b0"
+W 1091 6 1 1025 1034 BEZIER "Transitions" | 176852,45724 174332,42574 169925,36810 163940,34881\
+                                            157955,32952 139055,31533 132716,31415 126377,31297\
+                                            121929,32154 118701,32626
+A 1090 1084 4 TEXT "Actions" | 60764,178497 1 0 0 "USBWireWEn <= 1'b0;"
+C 1089 1087 0 TEXT "Conditions" | 68348,136414 1 0 0 "USBWireRdy == 1'b1"
+A 1088 1087 16 TEXT "Actions" | 81756,164067 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+L 7 6 0 TEXT "Labels" | 57079,207538 1 0 0 "prcTxB"
+F 6 0 671089152 185 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,15700 199488,210298
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 93869,266185 1 0 0 "Module: processTxByte"
+L 8 9 0 TEXT "State Labels" | 41526,197822 1 0 0 "START_PTBY\n/0/"
+S 9 6 0 ELLIPSE "States" | 41526,197822 6500 6500
+I 12 6 0 Builtin Reset | 22016,204762
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,204762 26512,204498 31110,200468 35074,198608
+I 816 0 2 Builtin InPort | 123679,253114 "" ""
+L 817 818 0 TEXT "Labels" | 127572,248474 1 0 0 "processTxByteRdy"
+I 818 0 2 Builtin OutPort | 121572,248474 "" ""
+L 819 820 0 TEXT "Labels" | 129679,243601 1 0 0 "TxByteIn[7:0]"
+I 820 0 130 Builtin InPort | 123679,243601 "" ""
+L 821 822 0 TEXT "Labels" | 129679,239194 1 0 0 "TxByteCtrlIn[7:0]"
+I 822 0 130 Builtin InPort | 123679,239194 "" ""
+L 823 824 0 TEXT "Labels" | 21604,240596 1 0 0 "USBWireData[1:0]"
+I 824 0 130 Builtin OutPort | 15604,240596 "" ""
+L 825 826 0 TEXT "Labels" | 21140,235724 1 0 0 "USBWireCtrl"
+I 826 0 2 Builtin OutPort | 15372,236188 "" ""
+L 827 828 0 TEXT "Labels" | 23692,231780 1 0 0 "USBWireGnt"
+I 828 0 2 Builtin InPort | 17692,231780 "" ""
+L 829 830 0 TEXT "Labels" | 21372,227372 1 0 0 "USBWireReq"
+I 830 0 2 Builtin OutPort | 15372,227372 "" ""
+L 831 832 0 TEXT "Labels" | 21372,222732 1 0 0 "USBWireWEn"
+L 1094 1095 0 TEXT "State Labels" | 102676,41870 1 0 0 "FIN\n/21/"
+S 1095 1035 106496 ELLIPSE "States" | 102676,41870 6500 6500
+A 1096 1095 4 TEXT "Actions" | 110058,56736 1 0 0 "USBWireWEn <= 1'b0;"
+I 1097 1035 0 Builtin Exit | 133008,37611
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+W 1119 895 0 942 1113 BEZIER "Transitions" | 81422,174858 96749,175660 126155,175178 141482,175980
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+S 1117 895 135168 ELLIPSE "States" | 157607,86664 6500 6500
+L 1116 1117 0 TEXT "State Labels" | 157607,86664 1 0 0 "W_RDY4\n/28/"
+S 1115 895 131072 ELLIPSE "States" | 152471,133209 6500 6500
+L 1114 1115 0 TEXT "State Labels" | 152471,133209 1 0 0 "W_RDY3\n/27/"
+S 1113 895 126976 ELLIPSE "States" | 147977,176223 6500 6500
+L 1112 1113 0 TEXT "State Labels" | 147977,176223 1 0 0 "W_RDY2\n/26/"
+S 1111 895 122880 ELLIPSE "States" | 129359,218595 6500 6500
+L 1110 1111 0 TEXT "State Labels" | 129359,218595 1 0 0 "W_RDY1\n/25/"
+W 1109 1035 0 1068 1107 BEZIER "Transitions" | 127810,93623 140198,90963 162007,83161 174395,80501
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+L 1106 1107 0 TEXT "State Labels" | 180608,78592 1 0 0 "W_RDY3\n/24/"
+S 1105 1035 114688 ELLIPSE "States" | 175744,133008 6500 6500
+L 1104 1105 0 TEXT "State Labels" | 175744,133008 1 0 0 "W_RDY2\n/23/"
+I 832 0 2 Builtin OutPort | 15372,222732 "" ""
+L 833 834 0 TEXT "Labels" | 23692,218324 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,218324 "" ""
+L 843 844 0 TEXT "Labels" | 72660,223196 1 0 0 "i[3:0]"
+I 844 0 130 Builtin Signal | 69660,223196 "" ""
+L 845 846 0 TEXT "Labels" | 131108,216932 1 0 0 "KBit[1:0]"
+I 846 0 130 Builtin InPort | 125108,216932 "" ""
+I 847 0 130 Builtin InPort | 125241,221252 "" ""
+I 1125 0 2 Builtin OutPort | 17114,248843 "" ""
+L 1124 1125 0 TEXT "Labels" | 23114,248843 1 0 0 "USBWireFullSpeedRate"
+I 1123 0 2 Builtin Signal | 69653,217706 "" ""
+L 1122 1123 0 TEXT "Labels" | 72332,217706 1 0 0 "TxByteFullSpeedRate"
+W 1121 895 0 962 1117 BEZIER "Transitions" | 87535,83532 103906,84093 134787,85298 151158,85859
+W 1120 895 0 956 1115 BEZIER "Transitions" | 84631,133419 97918,132655 128828,133044 145972,133233
+L 848 847 0 TEXT "Labels" | 131241,221252 1 0 0 "JBit[1:0]"
+S 874 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 48799,85161 6500 6500
+L 873 874 0 TEXT "State Labels" | 48799,85161 1 0 0 "SEND_BYTE"
+A 872 865 4 TEXT "Actions" | 55007,174633 1 0 0 "processTxByteRdy <= 1'b1;"
+A 871 869 16 TEXT "Actions" | 38769,162443 1 0 0 "processTxByteRdy <= 1'b0;\nTxByte <= TxByteIn;\nTxByteCtrl <= TxByteCtrlIn;\nTxByteFullSpeedRate <= TxByteFullSpeedRateIn;\nUSBWireFullSpeedRate <= TxByteFullSpeedRateIn;"
+C 870 869 0 TEXT "Conditions" | 45385,167359 1 0 0 "processTxByteWEn == 1'b1"
+W 869 6 0 865 994 BEZIER "Transitions" | 43506,166514 43972,160806 44382,144193 44848,138485
+W 866 6 0 9 865 BEZIER "Transitions" | 41794,191349 41968,188029 42333,182785 42507,179465
+S 865 6 4096 ELLIPSE "States" | 43124,173002 6500 6500
+L 864 865 0 TEXT "State Labels" | 43124,173002 1 0 0 "PTBY_WAIT_EN\n/1/"
+L 888 887 0 TEXT "State Labels" | 49971,45111 1 0 0 "STOP"
+S 887 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 49971,45111 6500 6500
+H 895 887 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 885 880 0 883 901 BEZIER "Transitions" | 42416,248040 47778,233267 52771,218493 58133,203720
+I 884 880 0 Builtin Exit | 178131,23271
+I 883 880 0 Builtin Entry | 38120,248040
+H 880 874 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+C 911 909 0 TEXT "Conditions" | 63744,160236 1 0 0 "USBWireRdy == 1'b1"
+W 909 880 0 904 906 BEZIER "Transitions" | 62562,160798 63190,153505 63227,143345 63855,136052
+W 908 880 0 901 904 BEZIER "Transitions" | 61196,191380 61824,178554 61181,186583 61809,173757
+S 906 880 24576 ELLIPSE "States" | 64960,129650 6500 6500
+L 905 906 0 TEXT "State Labels" | 64960,129650 1 0 0 "CHK\n/4/"
+S 904 880 20480 ELLIPSE "States" | 62200,167285 6500 6500
+L 903 904 0 TEXT "State Labels" | 62200,167285 1 0 0 "WAIT_RDY\n/3/"
+A 902 901 4 TEXT "Actions" | 87131,216544 1 0 0 "i <= i + 1'b1;\nTxByte <= {1'b0, TxByte[7:1] };\nif (TxByte[0] == 1'b1)                      //If this bit is 1, then\n  TXOneCount <= TXOneCount + 1'b1;          //increment 'TXOneCount'\nelse                                        //else this is a zero bit\nbegin\n  TXOneCount <= 4'h0;                            //reset 'TXOneCount'\n  if (TXLineState == JBit) \n    TXLineState <= KBit; //toggle the line state\n  else \n    TXLineState <= JBit;\nend"
+S 901 880 16384 ELLIPSE "States" | 60963,197870 6500 6500
+L 900 901 0 TEXT "State Labels" | 60963,197870 1 0 0 "UPDATE_BYTE\n/2/"
+W 898 6 0 887 865 BEZIER "Transitions" | 43587,46330 39277,46796 30872,48264 28251,49254\
+                                         25630,50244 23766,53274 22950,67894 22135,82515\
+                                         20737,137969 21261,153813 21785,169657 25281,177579\
+                                         27028,179792 28775,182006 32271,182938 33727,182355\
+                                         35183,181773 37321,179186 38486,177555
+W 897 6 0 874 887 BEZIER "Transitions" | 48492,78681 48772,71498 48867,58679 49333,51573
+W 896 6 8194 994 874 BEZIER "Transitions" | 45464,131529 46046,122326 47452,100861 48245,91628
+W 927 880 0 915 917 BEZIER "Transitions" | 67528,97031 67912,94983 68323,91700 68707,89652
+L 926 923 0 TEXT "State Labels" | 72651,39838 1 0 0 "CHK_FIN\n/7/"
+C 925 921 0 TEXT "Conditions" | 71683,75885 1 0 0 "USBWireRdy == 1'b1"
+A 924 923 4 TEXT "Actions" | 91246,42553 1 0 0 "USBWireWEn <= 1'b0;"
+S 923 880 36864 ELLIPSE "States" | 72651,39838 6500 6500
+A 922 921 16 TEXT "Actions" | 67128,66767 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+W 921 880 0 917 923 BEZIER "Transitions" | 70442,76789 71070,69496 71344,53592 71972,46299
+A 920 915 4 TEXT "Actions" | 82970,116161 1 0 0 "TXOneCount <= 4'h0;                                //reset 'TXOneCount'\nif (TXLineState == JBit) \n  TXLineState <= KBit;   //toggle the line state\nelse \n  TXLineState <= JBit;"
+C 919 918 0 TEXT "Conditions" | 67653,122954 1 0 0 "TXOneCount == `MAX_CONSEC_SAME_BITS"
+W 918 880 8193 906 915 BEZIER "Transitions" | 65281,123173 65470,118240 66017,114889 66206,109956
+S 917 880 32768 ELLIPSE "States" | 69840,83253 6500 6500
+L 916 917 0 TEXT "State Labels" | 69840,83253 1 0 0 "WAIT_RDY2\n/6/"
+S 915 880 28672 ELLIPSE "States" | 67031,103511 6500 6500
+L 914 915 0 TEXT "State Labels" | 67031,103511 1 0 0 "BIT_STUFF\n/5/"
+A 913 906 4 TEXT "Actions" | 83555,132365 1 0 0 "USBWireWEn <= 1'b0;"
+A 912 909 16 TEXT "Actions" | 49573,154836 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= TXLineState;\nUSBWireCtrl <= `DRIVE;"
+L 943 942 0 TEXT "State Labels" | 74939,175324 1 0 0 "SND_SE0_2\n/9/"
+S 942 895 45056 ELLIPSE "States" | 74939,175324 6500 6500
+C 941 940 0 TEXT "Conditions" | 159104,107836 1 0 0 "USBWireGnt == 1'b1"
+W 940 6 0 936 1005 BEZIER "Transitions" | 152571,107755 158885,103151 166953,83129 172936,74254
+A 939 937 16 TEXT "Actions" | 80687,127638 1 0 0 "TXOneCount <= 4'h0;       \nTXLineState <= JBit;\nUSBWireReq <= 1'b1;"
+C 938 937 0 TEXT "Conditions" | 56024,136519 1 0 0 "TxByteCtrlIn == `DATA_START"
+W 937 6 8193 994 936 BEZIER "Transitions" | 48651,134144 59369,131814 131883,116838 142601,114508
+S 936 6 40960 ELLIPSE "States" | 148958,113156 6500 6500
+L 935 936 0 TEXT "State Labels" | 148958,113156 1 0 0 "PTBY_WAIT_GNT\n/8/"
+W 930 880 8194 923 901 BEZIER "Transitions" | 66152,39809 60904,40065 50250,40296 45386,41576\
+                                              40522,42856 31562,47464 29098,65320 26634,83176\
+                                              25738,149992 26858,168968 27978,187944 33354,197032\
+                                              36938,198888 40522,200744 49226,198568 51498,198152\
+                                              53770,197736 54409,198230 54473,198230
+C 929 928 0 TEXT "Conditions" | 90570,32872 1 0 0 "i == 4'h8"
+W 928 880 8193 923 884 BEZIER "Transitions" | 77516,35528 81612,32648 88778,27048 101066,25480\
+                                              113354,23912 154429,23527 174909,23271
+A 959 958 16 TEXT "Actions" | 127881,161233 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+W 958 895 0 1113 956 BEZIER "Transitions" | 148099,169766 148727,162473 88842,149177 77593,139316
+L 957 956 0 TEXT "State Labels" | 78157,132848 1 0 0 "SND_J\n/12/"
+S 956 895 57344 ELLIPSE "States" | 78157,132848 6500 6500
+C 954 952 0 TEXT "Conditions" | 70699,244255 1 0 0 "TxByteCtrl == `DATA_STOP"
+W 952 895 8193 951 948 BEZIER "Transitions" | 67478,244015 68286,238818 70288,230349 71096,225152
+S 951 895 53248 ELLIPSE "States" | 66294,250403 6500 6500
+L 950 951 0 TEXT "State Labels" | 66294,250403 1 0 0 "CHK\n/11/"
+L 949 948 0 TEXT "State Labels" | 72128,218739 1 0 0 "SND_SE0_1\n/10/"
+S 948 895 49152 ELLIPSE "States" | 72128,218739 6500 6500
+A 947 944 16 TEXT "Actions" | 109865,203040 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;"
+A 946 942 4 TEXT "Actions" | 92250,183175 1 0 0 "USBWireWEn <= 1'b0;"
+C 945 944 0 TEXT "Conditions" | 128791,211803 1 0 0 "USBWireRdy == 1'b1"
+W 944 895 0 1111 942 BEZIER "Transitions" | 129757,212112 130385,204819 80759,192930 74325,181785
+W 975 895 0 968 974 BEZIER "Transitions" | 85932,37938 86628,34922 87928,30000 89030,28086\
+                                           90132,26172 93257,24084 94765,23272
+I 974 895 0 Builtin Exit | 97904,23272
+C 973 970 0 TEXT "Conditions" | 155824,79891 1 0 0 "USBWireRdy == 1'b1"
+A 972 968 4 TEXT "Actions" | 102564,46846 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0; //release the wire"
+A 971 970 16 TEXT "Actions" | 138904,72921 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 970 895 0 1117 968 BEZIER "Transitions" | 157812,80182 158440,72889 82671,57884 83299,50591
+L 969 968 0 TEXT "State Labels" | 83969,44131 1 0 0 "FIN\n/14/"
+S 968 895 65536 ELLIPSE "States" | 83969,44131 6500 6500
+C 967 964 0 TEXT "Conditions" | 151835,126496 1 0 0 "USBWireRdy == 1'b1"
+A 966 962 4 TEXT "Actions" | 90331,92695 1 0 0 "USBWireWEn <= 1'b0;"
+A 965 964 16 TEXT "Actions" | 130933,116536 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+W 964 895 0 1115 962 BEZIER "Transitions" | 152792,126730 153420,119437 79847,97645 80475,90352
+L 963 962 0 TEXT "State Labels" | 81045,83881 1 0 0 "SND_IDLE\n/13/"
+S 962 895 61440 ELLIPSE "States" | 81045,83881 6500 6500
+C 961 958 0 TEXT "Conditions" | 146391,169184 1 0 0 "USBWireRdy == 1'b1"
+A 960 956 4 TEXT "Actions" | 86480,140378 1 0 0 "USBWireWEn <= 1'b0;"
+I 987 0 130 Builtin Signal | 69201,241421 "" ""
+L 986 987 0 TEXT "Labels" | 72201,241421 1 0 0 "TXOneCount[3:0]"
+I 985 0 130 Builtin Signal | 69201,236994 "" ""
+L 984 985 0 TEXT "Labels" | 72201,236994 1 0 0 "TXLineState[1:0]"
+I 983 0 130 Builtin Signal | 69201,232334 "" ""
+L 982 983 0 TEXT "Labels" | 72201,232334 1 0 0 "TxByteCtrl[7:0]"
+I 981 0 130 Builtin Signal | 69434,227674 "" ""
+L 980 981 0 TEXT "Labels" | 72434,227674 1 0 0 "TxByte[7:0]"
+A 979 9 4 TEXT "Actions" | 127034,208396 1 0 0 "processTxByteRdy <= 1'b0;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\ni <= 4'h0;\nTxByte <= 8'h00;\nTxByteCtrl <= 8'h00;\nTXLineState <= 2'b0;\nTXOneCount <= 4'h0;\nUSBWireFullSpeedRate <= 1'b0;\nTxByteFullSpeedRate <= 1'b0;"
+W 978 895 0 977 951 BEZIER "Transitions" | 38683,259216 44135,257418 54598,254006 60050,252208
+I 977 895 0 Builtin Entry | 34452,259216
+W 976 895 8194 951 974 BEZIER "Transitions" | 61300,246245 53760,240097 39092,228012 35032,223372\
+                                              30972,218732 29812,212468 29638,189094 29464,165720\
+                                              29928,78488 31900,55230 33872,31972 41296,26172\
+                                              49358,24664 57420,23156 82353,23388 94765,23272
+W 989 880 8194 906 901 BEZIER "Transitions" | 58978,127109 55150,125485 47040,121872 44082,121756\
+                                              41124,121640 36948,124424 36020,132602 35092,140780\
+                                              35556,170708 38166,179350 40776,187992 50140,192687\
+                                              55128,195007
+C 990 989 0 TEXT "Conditions" | 32613,121194 1 0 0 "i != 4'h8"
+W 991 880 8195 906 884 BEZIER "Transitions" | 69617,134183 72517,135343 77069,138112 90815,138750\
+                                              104561,139388 153745,139620 168013,138576 182281,137532\
+                                              190169,133124 192141,121582 194113,110040 194113,68280\
+                                              192025,55114 189937,41948 185529,28723 181353,23271
+L 1006 1005 0 TEXT "State Labels" | 178403,71114 1 0 0 "WAIT_RDY_WIRE\n/15/"
+S 1005 6 73728 ELLIPSE "States" | 178403,70739 6500 6500
+A 1001 1000 16 TEXT "Actions" | 97876,75175 1 0 0 "//actively drive the first J bit\nUSBWireData <= JBit;  \nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 1000 6 2 1025 1011 BEZIER "Transitions" | 175446,48001 143324,42707 116663,67496 88157,75929
+C 188 13 0 TEXT "Conditions" | 25531,201445 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,259666 "" ""
+L 186 187 0 TEXT "Labels" | 192243,259666 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,264720 "" ""
+L 184 185 0 TEXT "Labels" | 192136,264720 1 0 0 "clk"
+L 993 994 0 TEXT "State Labels" | 45260,135010 1 0 0 "J1"
+S 994 6 69652 ELLIPSE "Junction" | 45260,135010 3500 3500
+H 995 994 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 996 995 0 Builtin Entry | 86360,167640
+I 997 995 0 Builtin Exit | 129540,111760
+W 998 995 0 996 997 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+A 999 885 16 TEXT "Actions" | 43433,228332 1 0 0 "i <= 4'h0;"
+I 1022 0 2 Builtin InPort | 123637,233935 "" ""
+L 1021 1022 0 TEXT "Labels" | 129637,233935 1 0 0 "TxByteFullSpeedRateIn"
+W 1020 6 0 1011 874 BEZIER "Transitions" | 75467,77142 69580,78790 60425,80424 54545,82123
+L 1013 1011 0 TEXT "State Labels" | 81933,77802 1 0 0 "WAIT_RDY_PKT\n/16/"
+A 1012 1011 4 TEXT "Actions" | 89664,97554 1 0 0 "USBWireWEn <= 1'b0;"
+S 1011 6 77824 ELLIPSE "States" | 81933,77802 6500 6500
+H 1035 1034 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 1034 6 86020 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 112501,34575 6500 6500
+L 1033 1034 0 TEXT "State Labels" | 112501,34575 1 0 0 "LS_START"
+C 1032 1031 0 TEXT "Conditions" | 160740,61840 1 0 0 "USBWireRdy == 1'b1"
+W 1031 6 0 1005 1025 BEZIER "Transitions" | 178252,64280 178492,60600 178502,55716 178742,52036
+W 1030 1027 0 1028 1029 BEZIER "Transitions" | 90591,167640 102761,150317 114231,129084 126401,111760
+I 1029 1027 0 Builtin Exit | 129540,111760
+I 1028 1027 0 Builtin Entry | 86360,167640
+L 1026 1025 0 TEXT "State Labels" | 178900,48560 1 0 0 "J2"
+S 1025 6 81940 ELLIPSE "Junction" | 178900,48560 3500 3500
+H 1027 1025 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 1047 1046 0 TEXT "State Labels" | 118913,145067 1 0 0 "SND_IDLE3\n/17/"
+S 1046 1035 90112 ELLIPSE "States" | 118913,145067 6500 6500
+L 1071 1068 0 TEXT "State Labels" | 121801,96100 1 0 0 "SND_J1\n/18/"
+A 1070 1066 16 TEXT "Actions" | 152238,115920 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+A 1069 1068 4 TEXT "Actions" | 140396,98815 1 0 0 "USBWireWEn <= 1'b0;"
+S 1068 1035 94208 ELLIPSE "States" | 121801,96100 6500 6500
+C 1067 1066 0 TEXT "Conditions" | 172627,126718 1 0 0 "USBWireRdy == 1'b1"
+W 1066 1035 0 1105 1068 BEZIER "Transitions" | 174692,126596 175320,119303 120603,109864 121231,102571
+A 1064 1060 16 TEXT "Actions" | 145913,63353 1 0 0 "//Drive the first JBit\nUSBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;"
+C 1061 1060 0 TEXT "Conditions" | 146295,70754 1 0 0 "USBWireRdy == 1'b1"
+W 1060 1035 0 1107 1095 BEZIER "Transitions" | 176710,73393 172416,69158 96436,74541 101513,48264
+W 1087 1035 0 1100 1046 BEZIER "Transitions" | 56057,127311 71885,129746 98436,147110 112744,147113
+L 1085 1084 0 TEXT "State Labels" | 50985,163622 1 0 0 "SND_IDLE2\n/20/"
+S 1084 1035 102400 ELLIPSE "States" | 50985,163622 6500 6500
+C 1082 1080 0 TEXT "Conditions" | 60959,213403 1 0 0 "USBWireRdy == 1'b1"
+A 1081 1080 16 TEXT "Actions" | 52141,196692 1 0 0 "USBWireWEn <= 1'b1;\nUSBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;"
+W 1080 1035 0 1077 1084 BEZIER "Transitions" | 60047,214302 60675,207009 52849,177084 50437,170095
+W 1079 1035 0 1075 1077 BEZIER "Transitions" | 75208,269307 75836,262014 61041,234231 58933,227242
+L 1078 1077 0 TEXT "State Labels" | 59497,220774 1 0 0 "SND_IDLE1\n/19/"
+S 1077 1035 98304 ELLIPSE "States" | 59497,220774 6500 6500
+I 1075 1035 0 Builtin Entry | 75208,271435
+A 1073 1046 4 TEXT "Actions" | 137508,147782 1 0 0 "USBWireWEn <= 1'b0;"
+L 815 816 0 TEXT "Labels" | 129679,253114 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/siereceiver.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/siereceiver.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/siereceiver.v	(revision 264)
@@ -0,0 +1,283 @@
+
+// File        : ../RTL/serialInterfaceEngine/siereceiver.v
+// Generated   : 11/10/06 05:37:23
+// From        : ../RTL/serialInterfaceEngine/siereceiver.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIEReceiver
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (RxWireDataIn, RxWireDataWEn, clk, connectState, rst);
+input   [1:0] RxWireDataIn;
+input   RxWireDataWEn;
+input   clk;
+input   rst;
+output  [1:0] connectState;
+
+wire    [1:0] RxWireDataIn;
+wire    RxWireDataWEn;
+wire    clk;
+reg     [1:0] connectState, next_connectState;
+wire    rst;
+
+// diagram signals declarations
+reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg  [7:0]RXWaitCount, next_RXWaitCount;
+reg  [1:0]RxBits, next_RxBits;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0] CurrState_rcvr;
+reg [3:0] NextState_rcvr;
+
+
+//--------------------------------------------------------------------
+// Machine: rcvr
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or connectState or CurrState_rcvr)
+begin : rcvr_NextState
+  NextState_rcvr <= CurrState_rcvr;
+  // Set default values for outputs and signals
+  next_RxBits <= RxBits;
+  next_RXStMachCurrState <= RXStMachCurrState;
+  next_RXWaitCount <= RXWaitCount;
+  next_connectState <= connectState;
+  case (CurrState_rcvr)
+    `WAIT_BIT:
+      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))	
+      begin
+        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))	
+      begin
+        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))	
+      begin
+        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))	
+      begin
+        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))	
+      begin
+        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))	
+      begin
+        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))	
+      begin
+        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+    `START_SRX:
+    begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_RXWaitCount <= 8'h00;
+      next_connectState <= `DISCONNECT;
+      next_RxBits <= 2'b00;
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `DISCNCT_CHK_RXBITS:
+      if (RxBits == `ZERO_ONE)	
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else if (RxBits == `ONE_ZERO)	
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else
+        NextState_rcvr <= `WAIT_BIT;
+    `WAIT_FS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ONE_ZERO)
+      begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+          if (RXWaitCount == `CONNECT_WAIT_TIME)
+          begin
+          next_connectState <= `FULL_SPEED_CONNECT;
+          next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+          end
+      end
+      else
+      begin
+        next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `WAIT_LS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+          if (RXWaitCount == `CONNECT_WAIT_TIME)
+          begin
+          next_connectState <= `LOW_SPEED_CONNECT;
+          next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+          end
+      end
+      else
+      begin
+        next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `LS_CONN_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+        next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+        next_RXWaitCount <= 0;
+      end
+    end
+    `FS_CONN_CHK_RX_BITS1:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+        next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+        next_RXWaitCount <= 0;
+      end
+    end
+    `WAIT_LS_DIS_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+          if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+          begin
+          next_RXStMachCurrState <= `DISCONNECT_ST;
+          next_connectState <= `DISCONNECT;
+          end
+      end
+      else
+      begin
+        next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+    end
+    `WAIT_FS_DIS_CHK_RX_BITS2:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+          if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+          begin
+          next_RXStMachCurrState <= `DISCONNECT_ST;
+          next_connectState <= `DISCONNECT;
+          end
+      end
+      else
+      begin
+        next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : rcvr_CurrentState
+  if (rst)	
+    CurrState_rcvr <= `START_SRX;
+  else
+    CurrState_rcvr <= NextState_rcvr;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : rcvr_RegOutput
+  if (rst)	
+  begin
+    RXStMachCurrState <= `DISCONNECT_ST;
+    RXWaitCount <= 8'h00;
+    RxBits <= 2'b00;
+    connectState <= `DISCONNECT;
+  end
+  else 
+  begin
+    RXStMachCurrState <= next_RXStMachCurrState;
+    RXWaitCount <= next_RXWaitCount;
+    RxBits <= next_RxBits;
+    connectState <= next_connectState;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/siereceiver.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbTxWireArbiter.asf	(revision 264)
@@ -0,0 +1,111 @@
+VERSION=1.15
+HEADER
+FILE="usbTxWireArbiter.asf"
+FID=4053e959
+LANGUAGE=VERILOG
+ENTITY="USBTxWireArbiter"
+FRAMES=ON
+FREEOID=134
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// usbTxWireArbiter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbConstants_h.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+S 15 6 12288 ELLIPSE "States" | 172430,18866 6500 6500
+L 14 15 0 TEXT "State Labels" | 172430,18866 1 0 0 "SIE_TX_ACT\n/3/"
+S 13 6 8192 ELLIPSE "States" | 95226,16087 6500 6500
+L 12 13 0 TEXT "State Labels" | 95226,16087 1 0 0 "PTXB_ACT\n/2/"
+S 11 6 4096 ELLIPSE "States" | 128339,87513 6500 6500
+L 10 11 0 TEXT "State Labels" | 128339,86127 1 0 0 "TARB_WAIT_REQ\n/1/"
+S 9 6 0 ELLIPSE "States" | 128958,117844 6500 6500
+L 8 9 0 TEXT "State Labels" | 128958,117844 1 0 0 "START_TARB\n/0/"
+L 7 6 0 TEXT "Labels" | 40741,140742 1 0 0 "txWireArb"
+F 6 0 671089152 59 0 RECT 0,0,0 0 0 1 255,255,255 0 | 30299,2691 211973,147394
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 106825,252275 1 0 0 "Module: USBTxWireArbiter"
+A 31 23 16 TEXT "Actions" | 139723,54159 1 0 0 "SIETxGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b1;"
+C 30 23 0 TEXT "Conditions" | 137571,82115 1 0 0 "SIETxReq == 1'b1"
+C 29 24 0 TEXT "Conditions" | 87204,80074 1 0 0 "prcTxByteReq == 1'b1"
+W 24 6 1 11 13 BEZIER "Transitions" | 123251,83469 117689,78216 107039,36827 97343,22230
+W 23 6 2 11 15 BEZIER "Transitions" | 133124,83115 139844,77553 161587,38384 168805,24261
+W 22 6 0 9 11 BEZIER "Transitions" | 128591,111368 128437,106888 128305,98485 128151,94005
+W 21 6 0 20 9 BEZIER "Transitions" | 86247,136033 95532,132260 113773,124344 123058,120571
+I 20 6 0 Builtin Reset | 86247,136033
+A 39 9 2 TEXT "Actions" | 149469,142310 1 0 0 "prcTxByteGnt <= 1'b0;\nSIETxGnt <= 1'b0;\nmuxSIENotPTXB <= 1'b0;"
+A 32 24 16 TEXT "Actions" | 81513,51784 1 0 0 "prcTxByteGnt <= 1'b1;\nmuxSIENotPTXB <= 1'b0;"
+L 58 59 0 TEXT "Labels" | 206032,246137 1 0 0 "clk"
+I 59 0 3 Builtin InPort | 200032,246137 "" ""
+L 60 61 0 TEXT "Labels" | 205418,251681 1 0 0 "rst"
+I 61 0 2 Builtin InPort | 199418,251681 "" ""
+C 62 21 0 TEXT "Conditions" | 105671,125880 1 0 0 "rst"
+W 65 6 0 15 11 BEZIER "Transitions" | 175496,24595 197510,44495 199427,70314 199810,76884\
+                                      200193,83454 202194,93721 199799,97969 197405,102218\
+                                      189371,107780 182843,108050 176316,108321 158239,103840\
+                                      151634,101445 145030,99051 137656,94031 133485,91482
+C 71 65 0 TEXT "Conditions" | 181780,29029 1 0 0 "SIETxReq == 1'b0"
+A 93 0 1 TEXT "Actions" | 28282,247012 1 0 0 "// processTxByte/SIETransmitter mux\nalways @(USBWireRdyIn)\nbegin\n  USBWireRdyOut <= USBWireRdyIn;\nend\nalways @(muxSIENotPTXB or SIETxWEn or SIETxData or \nSIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or\nSIETxFSRate or prcTxByteFSRate)  \nbegin\n  if (muxSIENotPTXB  == 1'b1)  \n  begin\n    USBWireWEn <= SIETxWEn;\n    TxBits <= SIETxData;\n    TxCtl <= SIETxCtrl;\n    TxFSRate <= SIETxFSRate;\n  end\n  else\n  begin\n    USBWireWEn <= prcTxByteWEn;\n    TxBits <= prcTxByteData;\n    TxCtl <= prcTxByteCtrl;\n    TxFSRate <= prcTxByteFSRate;\n  end\nend"
+C 84 81 0 TEXT "Conditions" | 52594,21436 1 0 0 "prcTxByteReq == 1'b0"
+A 83 81 16 TEXT "Actions" | 65508,92373 1 0 0 "prcTxByteGnt <= 1'b0;"
+W 81 6 0 13 11 BEZIER "Transitions" | 89927,19850 70522,33827 71796,55637 71053,63133\
+                                      70311,70629 71874,86691 76817,93064 81761,99437\
+                                      89642,107471 97173,106158 104705,104845 116882,95874\
+                                      123371,91703
+A 80 65 16 TEXT "Actions" | 183859,95437 1 0 0 "SIETxGnt <= 1'b0;"
+L 94 95 0 TEXT "Labels" | 190475,230225 1 0 0 "muxSIENotPTXB"
+I 95 0 2 Builtin Signal | 187475,230225 "" ""
+I 111 0 2 Builtin OutPort | 173058,181792 "" ""
+L 110 111 0 TEXT "Labels" | 179058,181792 1 0 0 "prcTxByteGnt"
+I 109 0 2 Builtin InPort | 140655,159238 "" ""
+L 108 109 0 TEXT "Labels" | 146655,159238 1 0 0 "SIETxReq"
+I 107 0 2 Builtin InPort | 175368,186412 "" ""
+L 106 107 0 TEXT "Labels" | 181368,186412 1 0 0 "prcTxByteReq"
+I 105 0 2 Builtin OutPort | 138576,154618 "" ""
+L 104 105 0 TEXT "Labels" | 144576,154618 1 0 0 "SIETxGnt"
+I 103 0 2 Builtin OutPort | 142325,212440 "" ""
+L 102 103 0 TEXT "Labels" | 148325,212440 1 0 0 "TxCtl"
+I 101 0 130 Builtin OutPort | 142556,217291 "" ""
+L 100 101 0 TEXT "Labels" | 148556,217291 1 0 0 "TxBits[1:0]"
+I 99 0 2 Builtin OutPort | 142787,221911 "" ""
+L 98 99 0 TEXT "Labels" | 148787,221911 1 0 0 "USBWireWEn"
+I 127 0 2 Builtin OutPort | 141972,231298 "" ""
+L 126 127 0 TEXT "Labels" | 147972,231298 1 0 0 "USBWireRdyOut"
+I 125 0 2 Builtin InPort | 144051,235918 "" ""
+L 124 125 0 TEXT "Labels" | 150051,235918 1 0 0 "USBWireRdyIn"
+I 123 0 2 Builtin InPort | 175137,200041 "" ""
+L 122 123 0 TEXT "Labels" | 181137,200041 1 0 0 "prcTxByteWEn"
+I 121 0 2 Builtin InPort | 175137,195652 "" ""
+L 120 121 0 TEXT "Labels" | 181137,195652 1 0 0 "prcTxByteCtrl"
+I 119 0 130 Builtin InPort | 175137,191032 "" ""
+L 118 119 0 TEXT "Labels" | 181137,191032 1 0 0 "prcTxByteData[1:0]"
+I 117 0 2 Builtin InPort | 140655,173329 "" ""
+L 116 117 0 TEXT "Labels" | 146655,173329 1 0 0 "SIETxWEn"
+I 115 0 2 Builtin InPort | 140655,168940 "" ""
+L 114 115 0 TEXT "Labels" | 146655,168940 1 0 0 "SIETxCtrl"
+I 113 0 130 Builtin InPort | 140655,164089 "" ""
+L 112 113 0 TEXT "Labels" | 146655,164089 1 0 0 "SIETxData[1:0]"
+L 128 129 0 TEXT "Labels" | 146868,178208 1 0 0 "SIETxFSRate"
+I 129 0 2 Builtin InPort | 140868,178208 "" ""
+L 130 131 0 TEXT "Labels" | 181140,205088 1 0 0 "prcTxByteFSRate"
+I 131 0 2 Builtin InPort | 175140,205088 "" ""
+L 132 133 0 TEXT "Labels" | 148212,207440 1 0 0 "TxFSRate"
+I 133 0 2 Builtin OutPort | 142212,207440 "" ""
+END

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbTxWireArbiter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/endpMux.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/endpMux.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/endpMux.v	(revision 264)
@@ -0,0 +1,259 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// endpMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSlaveControl_h.v" 
+
+module endpMux (
+  clk, 
+  rst,
+  currEndP,
+  NAKSent,
+  stallSent,
+  CRCError,
+  bitStuffError,
+  RxOverflow,
+  RxTimeOut,
+  dataSequence,
+  ACKRxed,
+  transType,
+  transTypeNAK,
+  endPControlReg,
+  clrEPRdy,
+  endPMuxErrorsWEn,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  endP0StatusReg,
+  endP1StatusReg,
+  endP2StatusReg,
+  endP3StatusReg,
+  endP0TransTypeReg,
+  endP1TransTypeReg,
+  endP2TransTypeReg,
+  endP3TransTypeReg,
+  endP0NAKTransTypeReg,
+  endP1NAKTransTypeReg,
+  endP2NAKTransTypeReg,
+  endP3NAKTransTypeReg,
+  clrEP0Rdy,
+  clrEP1Rdy,
+  clrEP2Rdy,
+  clrEP3Rdy);
+
+
+input clk; 
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [4:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [4:0] endP0ControlReg;
+input [4:0] endP1ControlReg;
+input [4:0] endP2ControlReg;
+input [4:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk; 
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [4:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      endPControlReg <= endP0ControlReg;
+      clrEP0Rdy <= clrEPRdy;
+    end
+    2'b01: begin
+      endPControlReg <= endP1ControlReg;
+      clrEP1Rdy <= clrEPRdy;
+    end
+    2'b10: begin
+      endPControlReg <= endP2ControlReg;
+      clrEP2Rdy <= clrEPRdy;
+    end
+    2'b11: begin
+      endPControlReg <= endP3ControlReg;
+      clrEP3Rdy <= clrEPRdy;
+    end
+  endcase  
+end      
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+  if (rst) begin
+    endP0NAKTransTypeReg <= 2'b00;
+    endP1NAKTransTypeReg <= 2'b00;
+    endP2NAKTransTypeReg <= 2'b00;
+    endP3NAKTransTypeReg <= 2'b00;
+    endP0TransTypeReg <= 2'b00;
+    endP1TransTypeReg <= 2'b00;
+    endP2TransTypeReg <= 2'b00;
+    endP3TransTypeReg <= 2'b00;
+    endP0StatusReg <= 4'h0;
+    endP1StatusReg <= 4'h0;
+    endP2StatusReg <= 4'h0;
+    endP3StatusReg <= 4'h0;
+  end
+  else begin
+    if (endPMuxErrorsWEn == 1'b1) begin
+      if (NAKSent == 1'b1) begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0NAKTransTypeReg <= transTypeNAK;
+            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; 
+          end
+          2'b01: begin
+            endP1NAKTransTypeReg <= transTypeNAK;
+            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; 
+          end
+          2'b10: begin
+            endP2NAKTransTypeReg <= transTypeNAK;
+            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; 
+          end
+          2'b11: begin
+            endP3NAKTransTypeReg <= transTypeNAK;
+            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; 
+          end
+        endcase
+      end
+      else begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0TransTypeReg <= transType;
+            endP0StatusReg <= endPStatusCombine; 
+          end
+          2'b01: begin
+            endP1TransTypeReg <= transType;
+            endP1StatusReg <= endPStatusCombine; 
+          end
+          2'b10: begin
+            endP2TransTypeReg <= transType;
+            endP2StatusReg <= endPStatusCombine; 
+          end
+          2'b11: begin
+            endP3TransTypeReg <= transType;
+            endP3StatusReg <= endPStatusCombine; 
+          end
+        endcase
+      end
+    end
+  end
+end
+        
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/endpMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/slaveDirectcontrol.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/slaveDirectcontrol.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/slaveDirectcontrol.asf	(revision 264)
@@ -0,0 +1,133 @@
+VERSION=1.15
+HEADER
+FILE="slaveDirectcontrol.asf"
+FID=406ac3b6
+LANGUAGE=VERILOG
+ENTITY="slaveDirectControl"
+FRAMES=ON
+FREEOID=180
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveDirectControl\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n"
+END
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+END
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+A 96 95 16 TEXT "Actions" | 62372,93902 1 0 0 "SCTxPortWEn <= 1'b1; \nSCTxPortData <= {6'b000000, directControlLineState}; \nSCTxPortCntl <= `TX_DIRECT_CONTROL;"
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+END

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/slaveDirectcontrol.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/slaveRxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/slaveRxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveRxStatusMonitor.v                                       ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      resetEventOut <= 1'b1;
+    else
+      resetEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/slaveRxStatusMonitor.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/slavecontroller.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/slavecontroller.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/slavecontroller.v	(revision 264)
@@ -0,0 +1,475 @@
+
+// File        : ../RTL/slaveController/slavecontroller.v
+// Generated   : 11/10/06 05:37:25
+// From        : ../RTL/slaveController/slavecontroller.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (CRCError, NAKSent, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, SOFRxed, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBEndP, USBTgtAddress, bitStuffError, clk, clrEPRdy, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketREn, getPacketRdy, rst, sendPacketPID, sendPacketRdy, sendPacketWEn, stallSent, transDone);
+input   CRCError;
+input   [7:0] RxByte;
+input   RxDataWEn;
+input   RxOverflow;
+input   [7:0] RxStatus;
+input   RxTimeOut;
+input   SCGlobalEn;
+input   [4:0] USBEndPControlReg;
+input   [6:0] USBTgtAddress;
+input   bitStuffError;
+input   clk;
+input   getPacketRdy;
+input   rst;
+input   sendPacketRdy;
+output  NAKSent;
+output  SOFRxed;
+output  [1:0] USBEndPNakTransTypeReg;
+output  [1:0] USBEndPTransTypeReg;
+output  [3:0] USBEndP;
+output  clrEPRdy;
+output  endPMuxErrorsWEn;
+output  endPointReadyToGetPkt;
+output  [10:0] frameNum;
+output  getPacketREn;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+output  stallSent;
+output  transDone;
+
+wire    CRCError;
+reg     NAKSent, next_NAKSent;
+wire    [7:0] RxByte;
+wire    RxDataWEn;
+wire    RxOverflow;
+wire    [7:0] RxStatus;
+wire    RxTimeOut;
+wire    SCGlobalEn;
+reg     SOFRxed, next_SOFRxed;
+wire    [4:0] USBEndPControlReg;
+reg     [1:0] USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg     [1:0] USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+reg     [3:0] USBEndP, next_USBEndP;
+wire    [6:0] USBTgtAddress;
+wire    bitStuffError;
+wire    clk;
+reg     clrEPRdy, next_clrEPRdy;
+reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg     endPointReadyToGetPkt, next_endPointReadyToGetPkt;
+reg     [10:0] frameNum, next_frameNum;
+reg     getPacketREn, next_getPacketREn;
+wire    getPacketRdy;
+wire    rst;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     stallSent, next_stallSent;
+reg     transDone, next_transDone;
+
+// diagram signals declarations
+reg  [7:0]PIDByte, next_PIDByte;
+reg  [6:0]USBAddress, next_USBAddress;
+reg  [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;
+reg  [7:0]addrEndPTemp, next_addrEndPTemp;
+reg  [7:0]endpCRCTemp, next_endpCRCTemp;
+reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define SETUP_OUT_CHK 5'b01011
+`define SETUP_OUT_SEND 5'b01100
+`define SETUP_OUT_GET_PKT 5'b01101
+`define START_S1 5'b01110
+`define GET_TOKEN_DELAY 5'b01111
+`define GET_TOKEN_CHK_ADDR 5'b10000
+`define IN_RESP_GET_RESP 5'b10001
+`define IN_RESP_DATA 5'b10010
+`define IN_RESP_CHK_ISO 5'b10011
+
+reg [4:0] CurrState_slvCntrl;
+reg [4:0] NextState_slvCntrl;
+
+
+//--------------------------------------------------------------------
+// Machine: slvCntrl
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RxByte or tempUSBEndPTransTypeReg or endpCRCTemp or addrEndPTemp or USBEndPControlReg or RxDataWEn or RxStatus or PIDByte or USBEndPControlRegCopy or NAKSent or sendPacketRdy or getPacketRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or getPacketREn or sendPacketWEn or sendPacketPID or USBEndPTransTypeReg or USBEndPNakTransTypeReg or frameNum or endPointReadyToGetPkt or CurrState_slvCntrl)
+begin : slvCntrl_NextState
+  NextState_slvCntrl <= CurrState_slvCntrl;
+  // Set default values for outputs and signals
+  next_stallSent <= stallSent;
+  next_NAKSent <= NAKSent;
+  next_SOFRxed <= SOFRxed;
+  next_PIDByte <= PIDByte;
+  next_transDone <= transDone;
+  next_clrEPRdy <= clrEPRdy;
+  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+  next_getPacketREn <= getPacketREn;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+  next_endpCRCTemp <= endpCRCTemp;
+  next_addrEndPTemp <= addrEndPTemp;
+  next_frameNum <= frameNum;
+  next_USBAddress <= USBAddress;
+  next_USBEndP <= USBEndP;
+  next_USBEndPControlRegCopy <= USBEndPControlRegCopy;
+  next_endPointReadyToGetPkt <= endPointReadyToGetPkt;
+  case (CurrState_slvCntrl)
+    `WAIT_RX1:
+    begin
+      next_stallSent <= 1'b0;
+      next_NAKSent <= 1'b0;
+      next_SOFRxed <= 1'b0;
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_START && 
+        RxByte[1:0] == `TOKEN)	
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+        next_PIDByte <= RxByte;
+      end
+    end
+    `FIN_SC:
+    begin
+      next_transDone <= 1'b0;
+      next_clrEPRdy <= 1'b0;
+      next_endPMuxErrorsWEn <= 1'b0;
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_PID:
+      if (PIDByte[3:0] == `SETUP)	
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if (PIDByte[3:0] == `OUT)	
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))	
+      begin
+        NextState_slvCntrl <= `IN_CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))	
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))	
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+      else if (PIDByte[3:0] == `IN)	
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else
+        NextState_slvCntrl <= `PID_ERROR;
+    `PID_ERROR:
+      NextState_slvCntrl <= `WAIT_RX1;
+    `CHK_RDY:
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)	
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_transDone <= 1'b1;
+        next_clrEPRdy <= 1'b1;
+        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else if (NAKSent == 1'b1)	
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else
+        NextState_slvCntrl <= `FIN_SC;
+    `SETUP_OUT_CHK:
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)	
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)	
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    `SETUP_OUT_SEND:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+    end
+    `SETUP_OUT_GET_PKT:
+    begin
+      next_getPacketREn <= 1'b0;
+      if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))	
+        NextState_slvCntrl <= `CHK_RDY;
+      else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+        bitStuffError == 1'b0 && 
+        RxOverflow == 1'b0 && 
+        RxTimeOut == 1'b0))	
+        NextState_slvCntrl <= `SETUP_OUT_CHK;
+      else if (getPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+    end
+    `IN_NAK_STALL:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+    end
+    `IN_CHK_RDY:
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)	
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)	
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)	
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    `IN_RESP_GET_RESP:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+    end
+    `IN_RESP_DATA:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `IN_RESP_CHK_ISO;
+    end
+    `IN_RESP_CHK_ISO:
+      if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_GET_RESP;
+        next_getPacketREn <= 1'b1;
+      end
+    `START_S1:
+      NextState_slvCntrl <= `WAIT_RX1;
+    `GET_TOKEN_WAIT_CRC:
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+        next_endpCRCTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)	
+        NextState_slvCntrl <= `WAIT_RX1;
+    `GET_TOKEN_WAIT_ADDR:
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+        next_addrEndPTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)	
+        NextState_slvCntrl <= `WAIT_RX1;
+    `GET_TOKEN_WAIT_STOP:
+      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RxByte [`RX_OVERFLOW_BIT] == 1'b0))	
+        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+      else if (RxDataWEn == 1'b1)	
+        NextState_slvCntrl <= `WAIT_RX1;
+    `GET_TOKEN_CHK_SOF:
+      if (PIDByte[3:0] == `SOF)	
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+        next_SOFRxed <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_DELAY;
+        next_USBAddress <= addrEndPTemp[6:0];
+        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+      end
+    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndP etc to update
+      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+    `GET_TOKEN_CHK_ADDR:
+      if (USBEndP < `NUM_OF_ENDPOINTS  &&
+        USBAddress == USBTgtAddress &&
+        SCGlobalEn == 1'b1 &&
+        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)	
+      begin
+        NextState_slvCntrl <= `CHK_PID;
+        next_USBEndPControlRegCopy <= USBEndPControlReg;
+        next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
+      end
+      else
+        NextState_slvCntrl <= `WAIT_RX1;
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_CurrentState
+  if (rst)	
+    CurrState_slvCntrl <= `START_S1;
+  else
+    CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_RegOutput
+  if (rst)	
+  begin
+    tempUSBEndPTransTypeReg <= 2'b00;
+    addrEndPTemp <= 8'h00;
+    endpCRCTemp <= 8'h00;
+    USBAddress <= 7'b0000000;
+    PIDByte <= 8'h00;
+    USBEndPControlRegCopy <= 5'b00000;
+    transDone <= 1'b0;
+    getPacketREn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    sendPacketWEn <= 1'b0;
+    clrEPRdy <= 1'b0;
+    USBEndPTransTypeReg <= 2'b00;
+    USBEndPNakTransTypeReg <= 2'b00;
+    NAKSent <= 1'b0;
+    stallSent <= 1'b0;
+    SOFRxed <= 1'b0;
+    endPMuxErrorsWEn <= 1'b0;
+    frameNum <= 11'b00000000000;
+    USBEndP <= 4'h0;
+    endPointReadyToGetPkt <= 1'b0;
+  end
+  else 
+  begin
+    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+    addrEndPTemp <= next_addrEndPTemp;
+    endpCRCTemp <= next_endpCRCTemp;
+    USBAddress <= next_USBAddress;
+    PIDByte <= next_PIDByte;
+    USBEndPControlRegCopy <= next_USBEndPControlRegCopy;
+    transDone <= next_transDone;
+    getPacketREn <= next_getPacketREn;
+    sendPacketPID <= next_sendPacketPID;
+    sendPacketWEn <= next_sendPacketWEn;
+    clrEPRdy <= next_clrEPRdy;
+    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+    NAKSent <= next_NAKSent;
+    stallSent <= next_stallSent;
+    SOFRxed <= next_SOFRxed;
+    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+    frameNum <= next_frameNum;
+    USBEndP <= next_USBEndP;
+    endPointReadyToGetPkt <= next_endPointReadyToGetPkt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/slavecontroller.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/wrapper/usbHostCyc2Wrap_usb1t11.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/wrapper/usbHostCyc2Wrap_usb1t11.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/wrapper/usbHostCyc2Wrap_usb1t11.v	(revision 264)
@@ -0,0 +1,151 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostCyc2Wrap_usb1t11.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+
+module usbHostCyc2Wrap_usb1t11(
+  clk_i, 
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  irq, 
+  usbClk,
+  USBWireVPin,
+  USBWireVMin,
+  USBWireVPout,
+  USBWireVMout,
+  USBWireOE_n,
+  USBFullSpeed
+   );
+
+input clk_i;
+input rst_i;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input we_i; 
+input strobe_i;
+output ack_o;
+output irq; 
+input usbClk;
+input USBWireVPin /* synthesis useioff=1 */;
+input USBWireVMin /* synthesis useioff=1 */;
+output USBWireVPout /* synthesis useioff=1 */;
+output USBWireVMout /* synthesis useioff=1 */;
+output USBWireOE_n /* synthesis useioff=1 */;
+output USBFullSpeed /* synthesis useioff=1 */;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire irq;
+wire usbClk;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBFullSpeed;
+
+//internal wiring 
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+             hostResumeIntOut | hostTransDoneIntOut;
+
+assign USBWireDataIn = {USBWireVPin, USBWireVMin};
+assign {USBWireVPout, USBWireVMout} = USBWireDataOut;
+assign USBWireOE_n = ~USBWireCtrlOut;
+
+//Parameters declaration: 
+defparam usbHostInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+
+usbHost usbHostInst (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .address_i(address_i),
+  .data_i(data_i),
+  .data_o(data_o),
+  .we_i(we_i),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .usbClk(usbClk),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlaveCyc2Wrap.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlaveCyc2Wrap.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlaveCyc2Wrap.v	(revision 264)
@@ -0,0 +1,170 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlaveCyc2Wrap.v                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+
+module usbHostSlaveCyc2Wrap(
+  clk_i, 
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  irq, 
+  usbClk,
+  USBWireVP,
+  USBWireVM,
+  USBWireOE_n,
+  USBFullSpeed
+   );
+
+input clk_i;
+input rst_i;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input we_i; 
+input strobe_i;
+output ack_o;
+output irq; 
+input usbClk;
+inout USBWireVP /* synthesis useioff=1 */;
+inout USBWireVM /* synthesis useioff=1 */;
+output USBWireOE_n /* synthesis useioff=1 */;
+output USBFullSpeed /* synthesis useioff=1 */;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire irq;
+wire usbClk;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBFullSpeed;
+
+//internal wiring 
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+             hostResumeIntOut | hostTransDoneIntOut |
+             slaveSOFRxedIntOut | slaveResetEventIntOut |
+             slaveResumeIntOut | slaveTransDoneIntOut |
+             slaveNAKSentIntOut;
+
+assign USBWireDataIn = {USBWireVP, USBWireVM};
+assign {USBWireVP, USBWireVM} = (USBWireCtrlOut == 1'b1) ? USBWireDataOut : 2'bzz;
+assign USBWireOE_n = ~USBWireCtrlOut;
+
+//Parameters declaration: 
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .address_i(address_i),
+  .data_i(data_i),
+  .data_o(data_o),
+  .we_i(we_i),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .usbClk(usbClk),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/bench/comboHostSlaveTestHarness.v
===================================================================
--- common/components/usbhostslave/trunk/bench/comboHostSlaveTestHarness.v	(nonexistent)
+++ common/components/usbhostslave/trunk/bench/comboHostSlaveTestHarness.v	(revision 264)
@@ -0,0 +1,238 @@
+`include "timescale.v"
+
+module testHarness(	);
+
+
+// -----------------------------------
+// Local Wires
+// -----------------------------------
+reg clk;
+reg rst;
+reg usbClk;
+wire [8:0] adr;
+wire [7:0] masterDout;
+wire [7:0] masterDin;
+wire [7:0] usbSlaveDout;
+wire [7:0] usbHostDout;
+wire stb;
+wire we;
+wire ack;
+wire host_stb;
+wire slave_stb;
+wire DPlusPullup;
+wire DPlusPullDown;
+wire DMinusPullup;
+wire DMinusPulDown;
+reg USBWireVP;
+reg USBWireVM;
+wire [1:0] hostUSBWireDataIn;
+wire [1:0] hostUSBWireDataOut;
+wire [1:0] slaveUSBWireDataIn;
+wire [1:0] slaveUSBWireDataOut;
+wire hostUSBWireCtrlOut;
+wire slaveUSBWireCtrlOut;
+
+initial begin
+$dumpfile("wave.vcd");
+$dumpvars(0, testHarness); 
+end
+
+pullup(DPlusPullup);
+pulldown(DPlusPullDown);
+pullup(DMinusPullup);
+pulldown(DMinusPullDown);
+
+assign hostUSBWireDataIn = {USBWireVP, USBWireVM};
+assign slaveUSBWireDataIn = {USBWireVP, USBWireVM};
+//always @(hostUSBWireCtrlOut or slaveUSBWireCtrlOut or hostUSBWireDataOut or slaveUSBWireDataOut or
+//  DPlusPullup or DPlusPullDown or DMinusPullup or DMinusPullDown) begin
+always @(*) begin
+  if (hostUSBWireCtrlOut == 1'b1 && slaveUSBWireCtrlOut == 1'b0)
+    {USBWireVP, USBWireVM} <= hostUSBWireDataOut;
+  else if (hostUSBWireCtrlOut == 1'b0 && slaveUSBWireCtrlOut == 1'b1)
+    {USBWireVP, USBWireVM} <= slaveUSBWireDataOut;
+  else if (hostUSBWireCtrlOut == 1'b1 && slaveUSBWireCtrlOut == 1'b1)
+    {USBWireVP, USBWireVM} <= 2'bxx;
+  else if (hostUSBWireCtrlOut == 1'b0 && slaveUSBWireCtrlOut == 1'b0) begin
+    if (USBDPlusPullup == 1'b1)
+      USBWireVP <= DPlusPullup;
+    else
+      USBWireVP <= DPlusPullDown;
+    if (USBDMinusPullup == 1'b1)
+      USBWireVM <= DMinusPullup;
+    else
+      USBWireVM <= DMinusPullDown;
+  end
+end
+
+assign host_stb = ~adr[8] & stb;
+assign slave_stb = adr[8] & stb;
+assign masterDin = host_stb == 1'b1 ? usbHostDout : usbSlaveDout;
+
+//Parameters declaration: 
+defparam u_usbHost.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam u_usbHost.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam u_usbHost.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam u_usbHost.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam u_usbHost.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam u_usbHost.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam u_usbHost.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam u_usbHost.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam u_usbHost.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam u_usbHost.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave u_usbHost (
+  .clk_i(clk),
+  .rst_i(rst),
+  .address_i(adr[7:0]),
+  .data_i(masterDout),
+  .data_o(usbHostDout),
+  .we_i(we),
+  .strobe_i(host_stb),
+  .ack_o(ack),
+  .usbClk(usbClk),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+
+  .slaveSOFRxedIntOut(),
+  .slaveResetEventIntOut(),
+  .slaveResumeIntOut(),
+  .slaveTransDoneIntOut(),
+  .slaveNAKSentIntOut(),
+  .slaveVBusDetIntOut(),
+
+  .USBWireDataIn(hostUSBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(hostUSBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(hostUSBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed),
+  .USBDPlusPullup(),
+  .USBDMinusPullup(),
+  .vBusDetect(1'b1)
+
+
+);
+
+
+
+//Parameters declaration: 
+defparam u_usbSlave.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam u_usbSlave.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam u_usbSlave.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam u_usbSlave.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam u_usbSlave.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam u_usbSlave.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam u_usbSlave.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam u_usbSlave.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam u_usbSlave.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam u_usbSlave.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave u_usbSlave (
+  .clk_i(clk),
+  .rst_i(rst),
+  .address_i(adr[7:0]),
+  .data_i(masterDout),
+  .data_o(usbSlaveDout),
+  .we_i(we),
+  .strobe_i(slave_stb),
+  .ack_o(ack),
+  .usbClk(usbClk),
+
+  .hostSOFSentIntOut(),
+  .hostConnEventIntOut(),
+  .hostResumeIntOut(),
+  .hostTransDoneIntOut(),
+
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .slaveVBusDetIntOut(slaveVBusDetIntOut),
+
+  .USBWireDataIn(slaveUSBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(slaveUSBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(slaveUSBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed),
+  .USBDPlusPullup(USBDPlusPullup),
+  .USBDMinusPullup(USBDMinusPullup),
+  .vBusDetect(1'b1)
+);
+
+
+
+
+wb_master_model #(.dwidth(8), .awidth(9)) u_wb_master_model (
+  .clk(clk), 
+  .rst(rst), 
+  .adr(adr), 
+  .din(masterDin), 
+  .dout(masterDout), 
+  .cyc(), 
+  .stb(stb), 
+  .we(we), 
+  .sel(), 
+  .ack(ack), 
+  .err(1'b0), 
+  .rty(1'b0)
+);
+
+
+//--------------- reset ---------------
+initial begin
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  rst <= 1'b1;
+  @(posedge clk);
+  rst <= 1'b0;
+  @(posedge clk);
+end
+ 
+// ******************************  Clock section  ******************************
+`define CLK_50MHZ_HALF_PERIOD 10
+`define CLK_25MHZ_HALF_PERIOD 20
+
+always begin
+  #`CLK_25MHZ_HALF_PERIOD clk <= 1'b0;
+  #`CLK_25MHZ_HALF_PERIOD clk <= 1'b1;
+end
+
+always begin
+  #`CLK_50MHZ_HALF_PERIOD usbClk <= 1'b0;
+  #`CLK_50MHZ_HALF_PERIOD usbClk <= 1'b1;
+end
+
+
+
+
+endmodule
+
Index: common/components/usbhostslave/trunk/doc/README.txt
===================================================================
--- common/components/usbhostslave/trunk/doc/README.txt	(nonexistent)
+++ common/components/usbhostslave/trunk/doc/README.txt	(revision 264)
@@ -0,0 +1,69 @@
+USBHostSlave has been successfully compiled using Quartus 6.0
+Note, that the component Builder in Quartus 6.0 will not accept include files, so you have to use Quartus to generate a
+single .vqm file, rename this as a .v file, and then import this using component Builder.
+USBHostSlave has been tested in a SystemC simulation, and on a Altera Nios development kit Cyclone edition.
+
+
+Release notes:
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+//             control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect 
+//             time outs, added low speed EOP keep alive. The TX bit rate is now controlled by 
+//             SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+//             speed, and TX resume is always low speed.
+//             Fixed read clock recovery (readUSBWireData.v) issue which was resulting 
+//             in missing receive packets.
+//             Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+//             by adding kludged delay to softranmit. This needs to be fixed properly.
+//             This version has undergone limited testing
+//             with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+//             with uClinux, and is known to work with a full speed USB flash stick.
+//             Moving Opencores project status from Beta to done.
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+//               Modified RX and TX fifo status registers, and removed TX fifo data count
+//               register. Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG.
+//               Fixed slave mode bug which caused receive fifo to
+//               be filled with incoming data when the slave was
+//               responding with a NAK, and the data should have been discarded.
+//             TODO: Test isochronous mode, and low speed mode using uClinux driver
+//                   Add frame period adjustment capability
+//                   Add compilation flags for slave only and host only versions
+//                   Create data bus width options beyond 8-bit              
+// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
+//             Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
+//             there was no detected activity on the USB data lines. This caused an infrequent
+//             misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
+//             the higher level state machines are actively looking for receive packets. 
+//             Modified USB RX data clock recovery, so that data is sampled during the middle
+//             of a USB bit period. Fixed a bug which could result in double sampling
+//             of USB RX data if clock phase adjustments were required in the middle of a 
+//             USB packet.
+// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required
+//             during migration to ActiveHDL 7.1. Released SystemC test bench.
+//             Re-generated .v files using ActiveHDL 7.1
+//             Replaced individual timescale directives with `include "timescale.v
+//             Renamed top level Altera wrapper from 'usbHostSlaveWrap' to 
+//             'usbHostSlaveAvalonWrap'
+// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added
+//             synchronizer to incoming USB wire data to avoid
+//             metastability, and delay hazards. Not entirely sure, but it appears that 
+//             this bug caused more problems with some of the newer low power FPGAs
+//             Maybe because they are more prone to problems with metastable
+//             inputs that feed logic functions causing excessive high speed
+//             toggle activity, and disrupting nearby cicuits.
+// Version 2.0 - June 16th 2008. Added two new top level modules which
+//             allow the instantiation of only host (usbHost.v), or only device
+//             features. Added double sync stages between usbClk, and busClk domains
+//             to fix possible metastability issues. Also modified synchronization to
+//             allow operation with busClk frequency less than usbClk frequency (down to
+//             24MHz). Integrated full support for USB PHY. Prior to this modification
+//             the user would need to instantiate a GPIO module to control USB speed,
+//             D+ and D- pull-up control, and VBUS detect. Fixed bug in bus interface wb_ack.
+//             Modified cross-clock synchronisation of fifo resets
+//             Added usbDevice, a standalone usb device implementation of usbhostslave
+//             no additional hardware or software required
+
+ 
+
+

Property changes on: common/components/usbhostslave/trunk/doc/README.txt
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlaveAvalonWrap.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlaveAvalonWrap.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlaveAvalonWrap.v	(revision 264)
@@ -0,0 +1,195 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlaveAvalonWrap.v                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. Enable connection to Altera Avalon bus
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+
+module usbHostSlaveAvalonWrap(
+  clk, 
+  reset,
+  address, 
+  writedata, 
+  readdata, 
+  write, 
+  read,
+  waitrequest,
+  chipselect,
+  irq, 
+  usbClk,
+  USBWireVPI,
+  USBWireVMI,
+  USBWireDataInTick,
+  USBWireVPO,
+  USBWireVMO,
+  USBWireDataOutTick,
+  USBWireOutEn_n,
+  USBFullSpeed
+   );
+
+input clk;
+input reset;
+input [7:0] address; 
+input [7:0] writedata; 
+output [7:0] readdata; 
+input write; 
+input read;
+output waitrequest;
+input chipselect;
+output irq; 
+input usbClk;
+input USBWireVPI /* synthesis useioff=1 */;
+input USBWireVMI /* synthesis useioff=1 */;
+output USBWireVPO /* synthesis useioff=1 */;
+output USBWireVMO /* synthesis useioff=1 */;
+output USBWireDataOutTick  /* synthesis useioff=1 */;
+output USBWireDataInTick /* synthesis useioff=1 */;
+output USBWireOutEn_n /* synthesis useioff=1 */;
+output USBFullSpeed /* synthesis useioff=1 */;
+
+wire clk;
+wire reset;
+wire [7:0] address; 
+wire [7:0] writedata; 
+wire [7:0] readdata; 
+wire write; 
+wire read;
+wire waitrequest;
+wire chipselect;
+wire irq;
+wire usbClk;
+wire USBWireVPI;
+wire USBWireVMI;
+wire USBWireVPO;
+wire USBWireVMO;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireOutEn_n;
+wire USBFullSpeed;
+
+//internal wiring 
+wire strobe_i;
+wire ack_o;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = hostSOFSentIntOut | hostConnEventIntOut |
+             hostResumeIntOut | hostTransDoneIntOut |
+             slaveSOFRxedIntOut | slaveResetEventIntOut |
+             slaveResumeIntOut | slaveTransDoneIntOut |
+             slaveNAKSentIntOut;
+
+assign strobe_i = chipselect & ( read | write);
+assign waitrequest = ~ack_o;
+
+assign USBWireOutEn_n = ~USBWireCtrlOut; 
+
+assign USBWireDataIn = {USBWireVPI, USBWireVMI};
+assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
+
+//Parameters declaration: 
+defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbHostSlave usbHostSlaveInst (
+  .clk_i(clk),
+  .rst_i(reset),
+  .address_i(address),
+  .data_i(writedata),
+  .data_o(readdata),
+  .we_i(write),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .usbClk(usbClk),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed));
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/RTL/wrapper/usbSlaveCyc2Wrap_usb1t11.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/wrapper/usbSlaveCyc2Wrap_usb1t11.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/wrapper/usbSlaveCyc2Wrap_usb1t11.v	(revision 264)
@@ -0,0 +1,164 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveCyc2Wrap_usb1t11.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+
+module usbSlaveCyc2Wrap_usb1t11(
+  clk_i, 
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  irq, 
+  usbClk,
+  USBWireVPin,
+  USBWireVMin,
+  USBWireVPout,
+  USBWireVMout,
+  USBWireOE_n,
+  USBFullSpeed,
+  USBDPlusPullup,
+  USBDMinusPullup,
+  vBusDetect
+   );
+
+input clk_i;
+input rst_i;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input we_i; 
+input strobe_i;
+output ack_o;
+output irq; 
+input usbClk;
+input USBWireVPin /* synthesis useioff=1 */;
+input USBWireVMin /* synthesis useioff=1 */;
+output USBWireVPout /* synthesis useioff=1 */;
+output USBWireVMout /* synthesis useioff=1 */;
+output USBWireOE_n /* synthesis useioff=1 */;
+output USBFullSpeed /* synthesis useioff=1 */;
+output USBDPlusPullup;
+output USBDMinusPullup;
+input vBusDetect;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire irq;
+wire usbClk;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBFullSpeed;
+
+//internal wiring 
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire slaveVBusDetIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = slaveSOFRxedIntOut | slaveResetEventIntOut |
+             slaveResumeIntOut | slaveTransDoneIntOut |
+             slaveNAKSentIntOut | slaveVBusDetIntOut;
+
+assign USBWireDataIn = {USBWireVPin, USBWireVMin};
+assign {USBWireVPout, USBWireVMout} = USBWireDataOut;
+assign USBWireOE_n = ~USBWireCtrlOut;
+
+//Parameters declaration: 
+defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+usbSlave usbSlaveInst (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .address_i(address_i),
+  .data_i(data_i),
+  .data_o(data_o),
+  .we_i(we_i),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .usbClk(usbClk),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .slaveVBusDetIntOut(slaveVBusDetIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed),
+  .USBDPlusPullup(USBDPlusPullup),
+  .USBDMinusPullup(USBDMinusPullup),
+  .vBusDetect(vBusDetect)
+);
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/bench/usbHostSlaveTB_defines.v
===================================================================
--- common/components/usbhostslave/trunk/bench/usbHostSlaveTB_defines.v	(nonexistent)
+++ common/components/usbhostslave/trunk/bench/usbHostSlaveTB_defines.v	(revision 264)
@@ -0,0 +1,2 @@
+`define SIM_HOST_BASE_ADDR 9'h000
+`define SIM_SLAVE_BASE_ADDR 9'h100
Index: common/components/usbhostslave/trunk/RTL/hostController/sendpacket.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/sendpacket.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/sendpacket.v	(revision 264)
@@ -0,0 +1,345 @@
+
+// File        : ../RTL/hostController/sendpacket.v
+// Generated   : 11/10/06 05:37:20
+// From        : ../RTL/hostController/sendpacket.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+
+module sendPacket (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, PID, TxAddr, TxEndP, clk, fifoData, fifoEmpty, fifoReadEn, frameNum, fullSpeedPolarity, rst, sendPacketRdy, sendPacketWEn);
+input   HCTxPortGnt;
+input   HCTxPortRdy;
+input   [3:0] PID;
+input   [6:0] TxAddr;
+input   [3:0] TxEndP;
+input   clk;
+input   [7:0] fifoData;
+input   fifoEmpty;
+input   fullSpeedPolarity;
+input   rst;
+input   sendPacketWEn;
+output  [7:0] HCTxPortCntl;
+output  [7:0] HCTxPortData;
+output  HCTxPortReq;
+output  HCTxPortWEn;
+output  fifoReadEn;
+output  [10:0] frameNum;
+output  sendPacketRdy;
+
+reg     [7:0] HCTxPortCntl, next_HCTxPortCntl;
+reg     [7:0] HCTxPortData, next_HCTxPortData;
+wire    HCTxPortGnt;
+wire    HCTxPortRdy;
+reg     HCTxPortReq, next_HCTxPortReq;
+reg     HCTxPortWEn, next_HCTxPortWEn;
+wire    [3:0] PID;
+wire    [6:0] TxAddr;
+wire    [3:0] TxEndP;
+wire    clk;
+wire    [7:0] fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+reg     [10:0] frameNum, next_frameNum;
+wire    fullSpeedPolarity;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: sndPkt
+// State codes definitions:
+`define START_SP 5'b00000
+`define WAIT_ENABLE 5'b00001
+`define SP_WAIT_GNT 5'b00010
+`define SEND_PID_WAIT_RDY 5'b00011
+`define SEND_PID_FIN 5'b00100
+`define FIN_SP 5'b00101
+`define OUT_IN_SETUP_WAIT_RDY1 5'b00110
+`define OUT_IN_SETUP_WAIT_RDY2 5'b00111
+`define OUT_IN_SETUP_FIN 5'b01000
+`define SEND_SOF_FIN1 5'b01001
+`define SEND_SOF_WAIT_RDY3 5'b01010
+`define SEND_SOF_WAIT_RDY4 5'b01011
+`define DATA0_DATA1_READ_FIFO 5'b01100
+`define DATA0_DATA1_WAIT_READ_FIFO 5'b01101
+`define DATA0_DATA1_FIFO_EMPTY 5'b01110
+`define DATA0_DATA1_FIN 5'b01111
+`define DATA0_DATA1_TERM_BYTE 5'b10000
+`define OUT_IN_SETUP_CLR_WEN1 5'b10001
+`define SEND_SOF_CLR_WEN1 5'b10010
+`define DATA0_DATA1_CLR_WEN 5'b10011
+`define DATA0_DATA1_CLR_REN 5'b10100
+`define LS_EOP_WAIT_RDY 5'b10101
+`define LS_EOP_FIN 5'b10110
+
+reg [4:0] CurrState_sndPkt;
+reg [4:0] NextState_sndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+always @(PID)
+begin
+    PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+//--------------------------------------------------------------------
+// Machine: sndPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (PIDNotPID or TxEndP or TxAddr or frameNum or fifoData or sendPacketWEn or HCTxPortGnt or PID or fullSpeedPolarity or HCTxPortRdy or fifoEmpty or sendPacketRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or fifoReadEn or CurrState_sndPkt)
+begin : sndPkt_NextState
+  NextState_sndPkt <= CurrState_sndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_HCTxPortReq <= HCTxPortReq;
+  next_HCTxPortWEn <= HCTxPortWEn;
+  next_HCTxPortData <= HCTxPortData;
+  next_HCTxPortCntl <= HCTxPortCntl;
+  next_frameNum <= frameNum;
+  next_fifoReadEn <= fifoReadEn;
+  case (CurrState_sndPkt)
+    `START_SP:
+      NextState_sndPkt <= `WAIT_ENABLE;
+    `WAIT_ENABLE:
+      if (sendPacketWEn == 1'b1)	
+      begin
+        NextState_sndPkt <= `SP_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_HCTxPortReq <= 1'b1;
+      end
+    `SP_WAIT_GNT:
+      if ((HCTxPortGnt == 1'b1) && (PID == `SOF && fullSpeedPolarity == 1'b0))	
+        NextState_sndPkt <= `LS_EOP_WAIT_RDY;
+      else if (HCTxPortGnt == 1'b1)	
+        NextState_sndPkt <= `SEND_PID_WAIT_RDY;
+    `FIN_SP:
+    begin
+      NextState_sndPkt <= `WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_HCTxPortReq <= 1'b0;
+    end
+    `SEND_PID_WAIT_RDY:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_sndPkt <= `SEND_PID_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= PIDNotPID;
+        next_HCTxPortCntl <= `TX_PACKET_START;
+      end
+    `SEND_PID_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)	
+        NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+      else if (PID == `SOF)	
+        NextState_sndPkt <= `SEND_SOF_WAIT_RDY3;
+      else if (PID == `OUT || 
+        PID == `IN || 
+        PID == `SETUP)	
+        NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY1;
+      else
+        NextState_sndPkt <= `FIN_SP;
+    end
+    `OUT_IN_SETUP_WAIT_RDY1:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {TxEndP[0], TxAddr[6:0]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    `OUT_IN_SETUP_WAIT_RDY2:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_sndPkt <= `OUT_IN_SETUP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, TxEndP[3:1]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    `OUT_IN_SETUP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `OUT_IN_SETUP_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `OUT_IN_SETUP_WAIT_RDY2;
+    end
+    `SEND_SOF_FIN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      next_frameNum <= frameNum + 1'b1;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `SEND_SOF_WAIT_RDY3:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_sndPkt <= `SEND_SOF_CLR_WEN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= frameNum[7:0];
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    `SEND_SOF_WAIT_RDY4:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_sndPkt <= `SEND_SOF_FIN1;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= {5'b00000, frameNum[10:8]};
+        next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      end
+    `SEND_SOF_CLR_WEN1:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `SEND_SOF_WAIT_RDY4;
+    end
+    `DATA0_DATA1_READ_FIFO:
+    begin
+      next_HCTxPortWEn <= 1'b1;
+      next_HCTxPortData <= fifoData;
+      next_HCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_sndPkt <= `DATA0_DATA1_CLR_WEN;
+    end
+    `DATA0_DATA1_WAIT_READ_FIFO:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    `DATA0_DATA1_FIFO_EMPTY:
+      if (fifoEmpty == 1'b0)	
+        NextState_sndPkt <= `DATA0_DATA1_WAIT_READ_FIFO;
+      else
+        NextState_sndPkt <= `DATA0_DATA1_TERM_BYTE;
+    `DATA0_DATA1_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+    `DATA0_DATA1_TERM_BYTE:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_sndPkt <= `DATA0_DATA1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    `DATA0_DATA1_CLR_WEN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_FIFO_EMPTY;
+    end
+    `DATA0_DATA1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_sndPkt <= `DATA0_DATA1_READ_FIFO;
+    end
+    `LS_EOP_WAIT_RDY:
+      if (HCTxPortRdy == 1'b1)	
+      begin
+        NextState_sndPkt <= `LS_EOP_FIN;
+        next_HCTxPortWEn <= 1'b1;
+        next_HCTxPortData <= 8'h00;
+        next_HCTxPortCntl <= `TX_LS_KEEP_ALIVE;
+      end
+    `LS_EOP_FIN:
+    begin
+      next_HCTxPortWEn <= 1'b0;
+      NextState_sndPkt <= `FIN_SP;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sndPkt_CurrentState
+  if (rst)	
+    CurrState_sndPkt <= `START_SP;
+  else
+    CurrState_sndPkt <= NextState_sndPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sndPkt_RegOutput
+  if (rst)	
+  begin
+    sendPacketRdy <= 1'b1;
+    HCTxPortReq <= 1'b0;
+    HCTxPortWEn <= 1'b0;
+    HCTxPortData <= 8'h00;
+    HCTxPortCntl <= 8'h00;
+    frameNum <= 11'h000;
+    fifoReadEn <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    HCTxPortReq <= next_HCTxPortReq;
+    HCTxPortWEn <= next_HCTxPortWEn;
+    HCTxPortData <= next_HCTxPortData;
+    HCTxPortCntl <= next_HCTxPortCntl;
+    frameNum <= next_frameNum;
+    fifoReadEn <= next_fifoReadEn;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/sendpacket.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v	(revision 264)
@@ -0,0 +1,205 @@
+
+// File        : ../RTL/hostController/sendpacketcheckpreamble.v
+// Generated   : 11/10/06 05:37:21
+// From        : ../RTL/hostController/sendpacketcheckpreamble.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// sendpacketcheckpreamble
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbConstants_h.v"
+
+module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
+input   clk;
+input   preAmbleEnable;
+input   rst;
+input   [3:0] sendPacketCPPID;
+input   sendPacketCPWEn;
+input   sendPacketRdy;
+output  sendPacketCPReady;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+
+wire    clk;
+wire    preAmbleEnable;
+wire    rst;
+wire    [3:0] sendPacketCPPID;
+reg     sendPacketCPReady, next_sendPacketCPReady;
+wire    sendPacketCPWEn;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+
+// BINARY ENCODED state machine: sendPktCP
+// State codes definitions:
+`define SPC_WAIT_EN 4'b0000
+`define START_SPC 4'b0001
+`define CHK_PREAM 4'b0010
+`define PREAM_PKT_SND_PREAM 4'b0011
+`define PREAM_PKT_WAIT_RDY1 4'b0100
+`define PREAM_PKT_PREAM_SENT 4'b0101
+`define PREAM_PKT_SND_PID 4'b0110
+`define PREAM_PKT_PID_SENT 4'b0111
+`define REG_PKT_SEND_PID 4'b1000
+`define REG_PKT_WAIT_RDY1 4'b1001
+`define REG_PKT_WAIT_RDY 4'b1010
+`define READY 4'b1011
+`define PREAM_PKT_WAIT_RDY2 4'b1100
+`define PREAM_PKT_WAIT_RDY3 4'b1101
+
+reg [3:0] CurrState_sendPktCP;
+reg [3:0] NextState_sendPktCP;
+
+
+//--------------------------------------------------------------------
+// Machine: sendPktCP
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
+begin : sendPktCP_NextState
+  NextState_sendPktCP <= CurrState_sendPktCP;
+  // Set default values for outputs and signals
+  next_sendPacketCPReady <= sendPacketCPReady;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  case (CurrState_sendPktCP)
+    `SPC_WAIT_EN:
+      if (sendPacketCPWEn == 1'b1)	
+      begin
+        NextState_sendPktCP <= `CHK_PREAM;
+        next_sendPacketCPReady <= 1'b0;
+      end
+    `START_SPC:
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    `CHK_PREAM:
+      if (preAmbleEnable == 1'b1 && sendPacketCPPID != `SOF)	
+        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
+      else
+        NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
+    `READY:
+    begin
+      next_sendPacketCPReady <= 1'b1;
+      NextState_sendPktCP <= `SPC_WAIT_EN;
+    end
+    `PREAM_PKT_SND_PREAM:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= `PREAMBLE;
+      NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
+    end
+    `PREAM_PKT_WAIT_RDY1:
+      if (sendPacketRdy == 1'b1)	
+        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
+    `PREAM_PKT_PREAM_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
+    end
+    `PREAM_PKT_SND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
+    end
+    `PREAM_PKT_PID_SENT:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
+    end
+    `PREAM_PKT_WAIT_RDY2:
+      if (sendPacketRdy == 1'b1)	
+        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
+    `PREAM_PKT_WAIT_RDY3:
+      if (sendPacketRdy == 1'b1)	
+        NextState_sendPktCP <= `READY;
+    `REG_PKT_SEND_PID:
+    begin
+      next_sendPacketWEn <= 1'b1;
+      next_sendPacketPID <= sendPacketCPPID;
+      NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
+    end
+    `REG_PKT_WAIT_RDY1:
+      if (sendPacketRdy == 1'b1)	
+        NextState_sendPktCP <= `REG_PKT_SEND_PID;
+    `REG_PKT_WAIT_RDY:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      NextState_sendPktCP <= `READY;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktCP_CurrentState
+  if (rst)	
+    CurrState_sendPktCP <= `START_SPC;
+  else
+    CurrState_sendPktCP <= NextState_sendPktCP;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : sendPktCP_RegOutput
+  if (rst)	
+  begin
+    sendPacketWEn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    sendPacketCPReady <= 1'b1;
+  end
+  else 
+  begin
+    sendPacketWEn <= next_sendPacketWEn;
+    sendPacketPID <= next_sendPacketPID;
+    sendPacketCPReady <= next_sendPacketCPReady;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostController/softransmit.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostController/softransmit.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostController/softransmit.v	(revision 264)
@@ -0,0 +1,209 @@
+
+// File        : ../RTL/hostController/softransmit.v
+// Generated   : 11/10/06 05:37:21
+// From        : ../RTL/hostController/softransmit.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// softransmit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostControl_h.v"
+
+
+module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, fullSpeedRate);
+input   SOFEnable;		// After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
+input   SOFSyncEn;
+input   [15:0] SOFTimer;
+input   clk;
+input   rst;
+input   sendPacketArbiterGnt;
+input   sendPacketRdy;
+output  SOFSent;		// single cycle pulse
+output  SOFTimerClr;		// Single cycle pulse
+output  sendPacketArbiterReq;
+output  sendPacketWEn;
+input   fullSpeedRate;
+
+wire    SOFEnable;
+reg     SOFSent, next_SOFSent;
+wire    SOFSyncEn;
+reg     SOFTimerClr, next_SOFTimerClr;
+wire    [15:0] SOFTimer;
+wire    clk;
+wire    rst;
+wire    sendPacketArbiterGnt;
+reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     [15:0] SOFNearTime;
+
+// diagram signals declarations
+reg  [7:0]i, next_i;
+
+// BINARY ENCODED state machine: SOFTx
+// State codes definitions:
+`define START_STX 3'b000
+`define WAIT_SOF_NEAR 3'b001
+`define WAIT_SP_GNT 3'b010
+`define WAIT_SOF_NOW 3'b011
+`define SOF_FIN 3'b100
+`define DLY_SOF_CHK1 3'b101
+`define DLY_SOF_CHK2 3'b110
+
+reg [2:0] CurrState_SOFTx;
+reg [2:0] NextState_SOFTx;
+
+
+//--------------------------------------------------------------------
+// Machine: SOFTx
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (i or SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
+begin : SOFTx_NextState
+  NextState_SOFTx <= CurrState_SOFTx;
+  // Set default values for outputs and signals
+  next_sendPacketArbiterReq <= sendPacketArbiterReq;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_SOFTimerClr <= SOFTimerClr;
+  next_SOFSent <= SOFSent;
+  next_i <= i;
+  case (CurrState_SOFTx)
+    `START_STX:
+      NextState_SOFTx <= `WAIT_SOF_NEAR;
+    `WAIT_SOF_NEAR:
+      if (SOFTimer >= SOFNearTime  ||
+        (SOFSyncEn == 1'b1 &&
+        SOFEnable == 1'b1))	
+      begin
+        NextState_SOFTx <= `WAIT_SP_GNT;
+        next_sendPacketArbiterReq <= 1'b1;
+      end
+    `WAIT_SP_GNT:
+      if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)	
+        NextState_SOFTx <= `WAIT_SOF_NOW;
+    `WAIT_SOF_NOW:
+      if (SOFTimer >= `SOF_TX_TIME)	
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_sendPacketWEn <= 1'b1;
+        next_SOFTimerClr <= 1'b1;
+        next_SOFSent <= 1'b1;
+      end
+      else if (SOFEnable == 1'b0)	
+      begin
+        NextState_SOFTx <= `SOF_FIN;
+        next_SOFTimerClr <= 1'b1;
+      end
+    `SOF_FIN:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      next_SOFTimerClr <= 1'b0;
+      next_SOFSent <= 1'b0;
+      if (sendPacketRdy == 1'b1)	
+      begin
+        NextState_SOFTx <= `DLY_SOF_CHK1;
+        next_i <= 8'h00;
+      end
+    end
+    `DLY_SOF_CHK1:
+    begin
+      next_i <= i + 1'b1;
+      if (i==8'hff)	
+      begin
+        NextState_SOFTx <= `DLY_SOF_CHK2;
+        next_sendPacketArbiterReq <= 1'b0;
+        next_i <= 8'h00;
+      end
+    end
+    `DLY_SOF_CHK2:
+    begin
+      next_i <= i + 1'b1;
+      if (i==8'hff)	
+        NextState_SOFTx <= `WAIT_SOF_NEAR;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SOFTx_CurrentState
+  if (rst)	
+    CurrState_SOFTx <= `START_STX;
+  else
+    CurrState_SOFTx <= NextState_SOFTx;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SOFTx_RegOutput
+  if (rst)	
+  begin
+    i <= 8'h00;
+    SOFSent <= 1'b0;
+    SOFTimerClr <= 1'b0;
+    sendPacketArbiterReq <= 1'b0;
+    sendPacketWEn <= 1'b0;
+    SOFNearTime <= 16'h0000;
+  end
+  else 
+  begin
+    i <= next_i;
+    SOFSent <= next_SOFSent;
+    SOFTimerClr <= next_SOFTimerClr;
+    sendPacketArbiterReq <= next_sendPacketArbiterReq;
+    sendPacketWEn <= next_sendPacketWEn;
+    if (fullSpeedRate == 1'b1)
+      SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN;
+    else
+      SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN_LOW_SPEED;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/hostController/softransmit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/hostSlaveMux/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/hostSlaveMux/hostSlaveMuxBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/hostSlaveMux/hostSlaveMuxBI.v	(revision 264)
@@ -0,0 +1,124 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMuxBI.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostSlave_h.v"
+
+module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
+  hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+wire rstFromWire;
+reg rstSyncToBusClkOut;
+reg rstSyncToUsbClkOut;
+
+//internal wire and regs
+reg [5:0] rstShift;
+reg rstFromBus;
+reg rstSyncToUsbClkFirst;
+
+//sync write demux
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClkOut == 1'b1)
+    hostMode <= 1'b0;
+  else begin
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+      hostMode <= dataIn[0];
+    end
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
+      rstFromBus <= 1'b1;
+    else
+      rstFromBus <= 1'b0;
+end
+
+// async read mux
+always @(address or hostMode)
+begin
+  case (address)
+    `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+    `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+  endcase
+end
+
+// reset control
+//generate 'rstSyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+  if (rstFromWire == 1'b1 || rstFromBus == 1'b1) 
+    rstShift <= 6'b111111;
+  else
+    rstShift <= {1'b0, rstShift[5:1]};
+end
+
+always @(rstShift)
+  rstSyncToBusClkOut <= rstShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+    rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
+    rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/hostSlaveMux/hostSlaveMuxBI.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/include/usbHostSlave_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/include/usbHostSlave_h.v	(revision 264)
@@ -0,0 +1,92 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+//             control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect 
+//             time outs, added low speed EOP keep alive. The TX bit rate is now controlled by 
+//             SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+//             speed, and TX resume is always low speed.
+//             Fixed read clock recovery (readUSBWireData.v) issue which was resulting 
+//             in missing receive packets.
+//             Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+//             by adding kludged delay to softranmit. This needs to be fixed properly.
+//             This version has undergone limited testing
+//             with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+//             with uClinux, and is known to work with a full speed USB flash stick.
+//             Moving Opencores project status from Beta to done.
+//             TODO: Test isochronous mode, and low speed mode using uClinux driver
+//                   Create a seperate clock domain for the bus interface
+//                   Add frame period adjustment capability
+//                   Add compilation flags for slave only and host only versions
+//                   Create data bus width options beyond 8-bit
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+//             Removed TX and RX fifo status registers, and removed 
+//             TX fifo data count register.
+//             Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG. 
+//             Fixed slave mode bug which caused receive fifo to be filled with 
+//             incoming data when the slave was responding with a NAK, and the 
+//             data should have been discarded.
+// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
+//             Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
+//             there was no detected activity on the USB data lines. This caused an infrequent
+//             misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
+//             the higher level state machines are actively looking for receive packets. 
+//             Modified USB RX data clock recovery, so that data is sampled during the middle
+//             of a USB bit period. Fixed a bug which could result in double sampling
+//             of USB RX data if clock phase adjustments were required in the middle of a 
+//             USB packet.
+// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required
+//             during migration to ActiveHDL 7.1. Released SystemC test bench.
+//             Re-generated .v files using ActiveHDL 7.1
+//             Replaced individual timescale directives with `include "timescale.v
+//             Renamed top level Altera wrapper from 'usbHostSlaveWrap' to 
+//             'usbHostSlaveAvalonWrap'
+// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added
+//             synchronizer to incoming USB wire data to avoid
+//             metastability, and delay hazards. Not entirely sure, but it appears that 
+//             this bug caused more problems with some of the newer low power FPGAs
+//             Maybe because they are more prone to problems with metastable
+//             inputs that feed logic functions causing excessive high speed
+//             toggle activity, and disrupting nearby cicuits.
+// Version 2.0 - June 16th 2008. Added two new top level modules which
+//             allow the instantiation of only host (usbHost.v), or only device
+//             features. Added double sync stages between usbClk, and busClk domains
+//             to fix possible metastability issues. Also modified synchronization to
+//             allow operation with busClk frequency less than usbClk frequency (down to
+//             24MHz). Integrated full support for USB PHY. Prior to this modification
+//             the user would need to instantiate a GPIO module to control USB speed,
+//             D+ and D- pull-up control, and VBUS detect. Fixed bug in bus interface wb_ack.
+//             Modified cross-clock synchronisation of fifo resets
+//             Added usbDevice, a standalone usb device implementation of usbhostslave
+//             no additional hardware or software required
+// Version 2.1 - October 8th 2010. Fixed issues related to accessing low speed device via hub.
+//             Changed USB PHY 'USBFullSpeed' edge rate control pin so that it is wired to
+//             'fullSpeedPolarityToSIE', rather than 'fullSpeedBitRateToSIE'.
+//             Introduced delay into 'fullSpeedRate' in module writeUSBWireData.v. Thus matching
+//             data delay with control delay.
+//             Created new control flow constant DATA_STOP_PRE. This allows PREAMBLE PID to completed
+//             without SEO (EOP), and ensures line state is left at state J. 
+//             Prevented PREAMBLE PID from preceding SOF when PREAMBLE is enabled.
+// Version 2.2 - March 18th 2011. Fixed more issues related to accessing low speed device via hub.
+//             Added 2 bit delay time from detection of low speed SEO (ie end of packet) to notification of
+//             higher level modules. This satisfies USB spec requirement of 2 bit times min turn around time
+//             Fixed SOF transmission to avoid collision with incoming ACK response in low speed mode.
+//             Fixed possible problem for full speed too.
+
+// Most significant nibble corresponds to major revision.
+// Least significant nibble corresponds to minor revision.
+`define USBHOSTSLAVE_VERSION_NUM 8'h22  
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+

Property changes on: common/components/usbhostslave/trunk/RTL/include/usbHostSlave_h.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf	(revision 264)
@@ -0,0 +1,614 @@
+VERSION=1.21
+HEADER
+FILE="SIETransmitter.asf"
+FID=4094ffa4
+LANGUAGE=VERILOG
+ENTITY="SIETransmitter"
+FREEOID=1083
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// SIETransmitter\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n\n"
+MULTIPLEARCHSTATUS=FALSE
+SYNTHESISATTRIBUTES=TRUE
+HEADER_PARAM="AUTHOR,"
+HEADER_PARAM="COMPANY,"
+HEADER_PARAM="CREATIONDATE,"
+HEADER_PARAM="TITLE,No Title"
+BLOCKTABLE_FILE=""
+BLOCKTABLE_TEMPL="0"
+BLOCKTABLE_VISIBLE="1"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Conditions" 236,0,236 0 0 0 255,255,255 0 3333 0 0110 0 "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B T "Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0 "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 0,0,0 0 3333 0 0000 0 "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0 "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0 "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0 "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0 "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0 "Arial" 0
+B T "Alias" 0,128,0 0 0 1 255,255,255 0 3527 1480 0000 0 "Arial" 0
+B F "Delay" 0,0,0 0 0 1 180,180,180 1 3527 1480 0000 0 "Arial" 0
+END
+INSTHEADER 1
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 16
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 213
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 359
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 455
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 465
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 474
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 483
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 609
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 617
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 626
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 718
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 720
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 717
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 911
+PAGE 0,0 215900,279400
+MARGINS 12700,0 0,12700
+END
+INSTHEADER 958
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+INSTHEADER 1073
+PAGE 0,0 215900,279400
+MARGINS 25400,0 0,25400
+END
+OBJECTS
+S 9 6 0 ELLIPSE "States" | 41526,185122 6500 6500
+L 8 9 0 TEXT "State Labels" | 41526,185122 1 0 0 "START_SIETX\n/18/"
+L 7 6 0 TEXT "Labels" | 57079,194838 1 0 0 "SIETx"
+F 6 0 671089152 185 0 "" 0 RECT 0,0,0 0 0 1 255,255,255 0 | 14988,3000 199488,196819
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0 "Arial" 0 | 93869,253485 1 0 0 "Module: SIETransmitter"
+L 10 11 0 TEXT "State Labels" | 41526,162904 1 0 0 "STX_CHK_ST\n/19/"
+S 11 6 0 ELLIPSE "States" | 41526,162904 6500 6500
+I 12 6 0 Builtin Reset | 22016,192062
+W 13 6 0 12 9 BEZIER "Transitions" | 22016,192062 26512,191798 31110,187768 35074,185908
+L 15 16 0 TEXT "State Labels" | 115356,112006 1 0 0 "RES_ST"
+I 816 0 2 Builtin OutPort | 64372,247878 "" ""
+L 817 818 0 TEXT "Labels" | 72692,243238 1 0 0 "processTxByteRdy"
+I 818 0 2 Builtin InPort | 66692,243238 "" ""
+L 819 820 0 TEXT "Labels" | 70372,238598 1 0 0 "TxByteOut[7:0]"
+I 820 0 130 Builtin OutPort | 64372,238598 "" ""
+L 821 822 0 TEXT "Labels" | 70372,233958 1 0 0 "TxByteOutCtrl[7:0]"
+I 822 0 130 Builtin OutPort | 64372,233958 "" ""
+L 823 824 0 TEXT "Labels" | 21604,227896 1 0 0 "USBWireData[1:0]"
+I 824 0 130 Builtin OutPort | 15604,227896 "" ""
+L 825 826 0 TEXT "Labels" | 21140,223024 1 0 0 "USBWireCtrl"
+I 826 0 2 Builtin OutPort | 15372,223488 "" ""
+L 827 828 0 TEXT "Labels" | 23692,219080 1 0 0 "USBWireGnt"
+I 828 0 2 Builtin InPort | 17692,219080 "" ""
+L 829 830 0 TEXT "Labels" | 21372,214672 1 0 0 "USBWireReq"
+I 830 0 2 Builtin OutPort | 15372,214672 "" ""
+L 831 832 0 TEXT "Labels" | 21372,210032 1 0 0 "USBWireWEn"
+A 835 9 4 TEXT "Actions" | 153876,195027 1 0 0 "processTxByteWEn <= 1'b0;\nTxByteOut <= 8'h00;\nTxByteOutCtrl <= 8'h00;\nUSBWireData <= 2'b00;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireReq <= 1'b0;\nUSBWireWEn <= 1'b0;\nrstCRC <= 1'b0;\nCRCData <= 8'h00;\nCRC5En <= 1'b0;\nCRC5_8Bit <= 1'b0;\nCRC16En <= 1'b0;\nSIEPortTxRdy <= 1'b0;\nSIEPortData <= 8'h00;\nSIEPortCtrl <= 8'h00;\ni <= 3'h0;\nresumeCnt <= 16'h0000;\nTxByteOutFullSpeedRate <= 1'b0;\nUSBWireFullSpeedRate <= 1'b0;"
+W 574 458 0 567 540 BEZIER "Transitions" | 44528,153207 48588,141781 61374,54759 65434,43333
+A 573 567 4 TEXT "Actions" | 56696,160909 1 0 0 "processTxByteWEn <= 1'b0;"
+I 572 458 0 Builtin Entry | 44780,253519
+W 571 458 0 572 564 BEZIER "Transitions" | 48542,253519 46980,242300 45702,231079 44140,219860
+C 570 566 0 TEXT "Conditions" | 44385,204992 1 0 0 "processTxByteRdy == 1'b1"
+A 569 566 16 TEXT "Actions" | 23113,191369 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+L 568 567 0 TEXT "State Labels" | 42474,159373 1 0 0 "PKT_SENT\n/6/"
+S 567 458 0 ELLIPSE "States" | 42474,159373 6500 6500
+W 566 458 0 564 567 BEZIER "Transitions" | 43356,206909 43221,193222 43084,179535 42949,165848
+L 565 564 0 TEXT "State Labels" | 43751,213384 1 0 0 "WAIT_RDY\n/34/"
+S 564 458 0 ELLIPSE "States" | 43751,213384 6500 6500
+S 16 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115356,110404 6500 6500
+H 17 16 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 832 0 2 Builtin OutPort | 15372,210032 "" ""
+L 833 834 0 TEXT "Labels" | 23692,205624 1 0 0 "USBWireRdy"
+I 834 0 2 Builtin InPort | 17692,205624 "" ""
+A 836 63 4 TEXT "Actions" | 118825,182282 1 0 0 "SIEPortTxRdy <= 1'b1;"
+L 837 838 0 TEXT "Labels" | 74732,211952 1 0 0 "SIEPortData[7:0]"
+I 838 0 130 Builtin Signal | 71732,211952 "" ""
+L 839 840 0 TEXT "Labels" | 74500,207544 1 0 0 "SIEPortCtrl[7:0]"
+I 840 0 130 Builtin Signal | 71500,207544 "" ""
+L 843 844 0 TEXT "Labels" | 74500,203136 1 0 0 "i[2:0]"
+I 844 0 130 Builtin Signal | 71500,203136 "" ""
+L 845 846 0 TEXT "Labels" | 131108,202306 1 0 0 "KBit[1:0]"
+I 846 0 130 Builtin InPort | 125108,202306 "" ""
+I 847 0 130 Builtin InPort | 124599,206947 "" ""
+L 309 310 0 TEXT "Labels" | 129515,247488 1 0 0 "rstCRC"
+I 310 0 2 Builtin OutPort | 123515,247488 "" ""
+L 311 312 0 TEXT "Labels" | 129156,242520 1 0 0 "CRCData[7:0]"
+I 312 0 130 Builtin OutPort | 123156,242520 "" ""
+L 313 314 0 TEXT "Labels" | 131655,237903 1 0 0 "CRC5Result[4:0]"
+I 314 0 130 Builtin InPort | 125655,237903 "" ""
+L 315 316 0 TEXT "Labels" | 129509,232929 1 0 0 "CRC5En"
+I 316 0 2 Builtin OutPort | 123509,232929 "" ""
+L 317 318 0 TEXT "Labels" | 129866,228310 1 0 0 "CRC5_8Bit"
+I 318 0 2 Builtin OutPort | 123866,228310 "" ""
+L 319 320 0 TEXT "Labels" | 133337,213507 1 0 0 "fullSpeedRateIn"
+L 848 847 0 TEXT "Labels" | 130599,206947 1 0 0 "JBit[1:0]"
+I 872 360 0 Builtin Exit | 188676,86316
+W 51 6 0 11 16 BEZIER "Transitions" | 41219,156419 41353,150657 41254,124742 41790,120856\
+                                      42326,116970 44202,112950 52711,111811 61220,110672\
+                                      92777,110593 108857,110325
+C 55 51 0 TEXT "Conditions" | 43286,108515 1 0 0 "SIEPortCtrl == `TX_RESUME_START"
+L 62 63 0 TEXT "State Labels" | 139687,163978 1 0 0 "STX_WAIT_BYTE\n/20/"
+S 63 6 0 ELLIPSE "States" | 138700,164805 6500 6500
+I 320 0 2 Builtin InPort | 127337,213507 "" ""
+L 323 324 0 TEXT "Labels" | 132267,223282 1 0 0 "CRC16Result[15:0]"
+I 324 0 130 Builtin InPort | 126267,223282 "" ""
+I 599 489 0 Builtin Entry | 29952,254306
+I 606 489 0 Builtin Exit | 101068,51939
+C 894 893 0 TEXT "Conditions" | 109367,115011 1 0 0 "i == 3'h7"
+W 893 224 8193 891 909 BEZIER "Transitions" | 107977,115304 108094,108635 108755,97421 108872,90752
+L 892 891 0 TEXT "State Labels" | 107874,121801 1 0 0 "CHK_FIN\n/0/"
+S 891 224 0 ELLIPSE "States" | 107874,121801 6500 6500
+W 65 6 0 63 11 BEZIER "Transitions" | 132240,164092 119927,158464 59299,161871 47927,164030
+C 66 65 0 TEXT "Conditions" | 70342,152867 1 0 0 "SIEPortWEn == 1'b1"
+W 68 6 0 16 911 BEZIER "Transitions" | 120272,106153 129598,96743 150861,80396 161245,74146
+A 78 65 16 TEXT "Actions" | 53177,174464 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;\nTxByteOutFullSpeedRate <= fullSpeedRateIn;\nUSBWireFullSpeedRate <= fullSpeedRateIn;"
+W 351 6 0 911 63 BEZIER "Transitions" | 165111,75772 164661,79912 166410,89760 164070,92955\
+                                        161730,96150 152965,99917 149770,102482 146575,105047\
+                                        142560,111540 140625,118020 138690,124500 144540,143115\
+                                        141750,148605 138960,154095 141442,152739 137520,158418
+L 608 609 0 TEXT "State Labels" | 74766,198892 1 0 0 "PID"
+S 609 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 74766,198892 6500 6500
+H 610 609 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 617 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 77071,148182 6500 6500
+I 909 224 0 Builtin Exit | 108872,88817
+I 908 224 0 Builtin Entry | 85162,237767
+L 907 906 0 TEXT "State Labels" | 100220,209467 1 0 0 "WAIT_GNT\n/28/"
+S 906 224 0 ELLIPSE "States" | 100220,209467 6500 6500
+A 905 904 16 TEXT "Actions" | 90803,229890 1 0 0 "USBWireReq <= 1'b1;"
+W 904 224 0 908 906 BEZIER "Transitions" | 88924,237767 91942,232360 93569,220262 96587,214855
+C 903 902 0 TEXT "Conditions" | 103902,201102 1 0 0 "USBWireGnt == 1'b1"
+W 902 224 0 906 897 BEZIER "Transitions" | 100017,202983 102891,191758 105765,180532 108639,169307
+A 901 899 16 TEXT "Actions" | 96847,150086 1 0 0 "USBWireData <= SIEPortData[1:0];\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 900 899 0 TEXT "Conditions" | 108372,156319 1 0 0 "USBWireRdy == 1'b1"
+W 899 224 0 897 891 BEZIER "Transitions" | 107878,156386 107816,150199 107756,134472 107694,128285
+L 898 897 0 TEXT "State Labels" | 107943,162854 1 0 0 "WAIT_RDY\n/37/"
+S 897 224 0 ELLIPSE "States" | 107943,162854 6500 6500
+A 896 891 4 TEXT "Actions" | 123784,131321 1 0 0 "USBWireWEn <= 1'b0;\ni <= i + 1'b1;"
+W 367 6 0 11 359 BEZIER "Transitions" | 41599,156432 41831,139227 41618,105313 42489,95839\
+                                        43361,86365 46384,82876 54928,82178 63472,81481\
+                                        94207,83380 109784,83728
+I 363 360 0 Builtin Entry | 26888,244668
+H 360 359 512 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 359 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116250,84388 6500 6500
+L 358 359 0 TEXT "State Labels" | 116250,84388 1 0 0 "PKT_ST"
+W 356 6 0 9 63 BEZIER "Transitions" | 48006,185620 80182,187622 122622,176230 134753,169968
+H 624 617 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 625 617 0 TEXT "State Labels" | 77071,148182 1 0 0 "BYTE1"
+H 633 626 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 626 489 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 75688,89174 6500 6500
+L 634 626 0 TEXT "State Labels" | 75688,89174 1 0 0 "CRC"
+S 635 610 0 ELLIPSE "States" | 97491,195105 6500 6500
+I 636 610 0 Builtin Entry | 71380,236621
+W 637 610 0 636 635 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+W 638 610 0 635 641 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+C 639 638 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+L 910 911 0 TEXT "State Labels" | 164265,72378 1 0 0 "J1"
+S 911 6 4116 ELLIPSE "Junction" | 164265,72378 3500 3500
+A 921 893 16 TEXT "Actions" | 106866,104347 1 0 0 "USBWireReq <= 1'b0;"
+A 916 906 4 TEXT "Actions" | 119076,210436 1 0 0 "i <= 3'h0;"
+C 369 367 0 TEXT "Conditions" | 48825,79738 1 0 0 "SIEPortCtrl == `TX_PACKET_START"
+W 368 6 0 359 911 BEZIER "Transitions" | 122468,82497 131651,79475 151659,76125 160842,73103
+A 640 638 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+S 641 610 0 ELLIPSE "States" | 96214,141555 6500 6500
+L 642 641 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/5/"
+L 643 635 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/31/"
+A 644 641 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+I 645 610 0 Builtin Exit | 114540,97930
+W 647 610 0 641 645 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+W 648 489 0 599 609 BEZIER "Transitions" | 33927,254306 41205,251054 71176,221478 73868,205326
+W 649 489 0 609 617 BEZIER "Transitions" | 74835,192396 75180,182600 76125,164449 76470,154653
+W 650 489 0 617 626 BEZIER "Transitions" | 76796,141693 76220,129592 76063,107757 75487,95656
+W 651 489 0 626 606 BEZIER "Transitions" | 78534,83332 83720,75495 93087,59776 98273,51939
+S 652 624 0 ELLIPSE "States" | 91348,185851 6500 6500
+L 653 652 0 TEXT "State Labels" | 91348,185851 1 0 0 "UPD_CRC\n/23/"
+H 912 911 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 913 912 0 Builtin Entry | 86360,167640
+I 914 912 0 Builtin Exit | 129540,111760
+W 915 912 0 913 914 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+S 656 624 0 ELLIPSE "States" | 88966,234486 6500 6500
+L 657 656 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/26/"
+W 658 624 0 656 952 BEZIER "Transitions" | 89478,228015 72707,215911 56621,202132 39850,190028
+A 659 658 16 TEXT "Actions" | 39361,213175 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+C 660 658 0 TEXT "Conditions" | 52953,228497 1 0 0 "SIEPortWEn == 1'b1"
+A 662 656 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 663 624 0 Builtin Entry | 59190,254840
+W 664 624 0 663 656 BEZIER "Transitions" | 63260,254840 69355,251390 77619,241763 83714,238313
+W 665 624 0 669 672 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+C 666 665 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+S 669 624 0 ELLIPSE "States" | 99353,141110 6500 6500
+W 670 624 0 672 671 BEZIER "Transitions" | 98449,81078 99139,72971 100302,56642 102170,52013\
+                                           104039,47385 110550,45085 113597,43935
+I 671 624 0 Builtin Exit | 116402,43935
+L 938 939 0 TEXT "State Labels" | 39277,179580 1 0 0 "WAIT_CRC_RDY\n/42/"
+S 939 633 8192 ELLIPSE "States" | 39277,179580 6500 6500
+W 940 633 0 939 680 BEZIER "Transitions" | 45698,178573 56873,179224 77330,179808 88505,180459
+C 941 940 0 TEXT "Conditions" | 49910,177844 1 0 0 "CRC5UpdateRdy == 1'b1"
+L 942 943 0 TEXT "Labels" | 171188,213782 1 0 0 "CRC5UpdateRdy"
+I 943 0 2 Builtin InPort | 165188,213782 "" ""
+W 959 6 0 11 958 BEZIER "Transitions" | 41589,156453 41990,133261 42609,87847 43291,74847\
+                                        43973,61847 45899,56228 54485,54824 63072,53420\
+                                        95424,54259 111633,54052
+S 958 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 118124,54386 6500 6500
+L 957 958 0 TEXT "State Labels" | 118124,56306 1 0 0 "TX_LS_EOP"
+W 404 17 0 411 407 BEZIER "Transitions" | 59469,165399 59407,159212 59347,143485 59285,137298
+A 405 404 16 TEXT "Actions" | 48438,159099 1 0 0 "USBWireData <= KBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;	\nresumeCnt  <= resumeCnt  + 1'b1;"
+C 406 404 0 TEXT "Conditions" | 59963,165332 1 0 0 "USBWireRdy == 1'b1"
+S 407 17 0 ELLIPSE "States" | 59465,130814 6500 6500
+L 408 407 0 TEXT "State Labels" | 59465,130814 1 0 0 "CHK_FIN\n/1/"
+W 409 17 0 415 411 BEZIER "Transitions" | 59369,208665 59244,202378 59238,184636 59113,178349
+C 410 409 0 TEXT "Conditions" | 61028,208180 1 0 0 "USBWireGnt == 1'b1"
+S 411 17 0 ELLIPSE "States" | 59534,171867 6500 6500
+L 412 411 0 TEXT "State Labels" | 59534,171867 1 0 0 "WAIT_RDY\n/32/"
+W 413 17 0 417 415 BEZIER "Transitions" | 48348,243455 51366,238048 55001,226201 56011,220543
+A 414 413 16 TEXT "Actions" | 50560,239516 1 0 0 "USBWireReq <= 1'b1;\nresumeCnt  <= 16'h0000;\nUSBWireFullSpeedRate <= 1'b0; //resume always uses low speed timing"
+S 415 17 0 ELLIPSE "States" | 59644,215155 6500 6500
+S 672 624 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 673 672 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+L 674 669 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/30/"
+L 675 672 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT1\n/12/"
+A 676 665 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+A 677 652 4 TEXT "Actions" | 110170,186940 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b1;\nCRC5En <= 1'b1;"
+W 678 624 0 652 669 BEZIER "Transitions" | 91940,179382 93550,171217 96164,155578 97774,147413
+A 679 669 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC5En <= 1'b0;"
+S 680 633 0 ELLIPSE "States" | 94863,181807 6500 6500
+L 681 680 0 TEXT "State Labels" | 94863,181807 1 0 0 "UPD_CRC\n/22/"
+I 682 633 0 Builtin Exit | 119917,39891
+W 683 633 0 699 682 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+S 684 633 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 685 633 0 684 699 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+C 686 685 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 687 633 0 688 689 BEZIER "Transitions" | 66467,250796 72562,247346 81134,237719 87229,234269
+I 944 0 2 Builtin InPort | 165012,209024 "" ""
+L 945 944 0 TEXT "Labels" | 171012,209024 1 0 0 "CRC16UpdateRdy"
+L 946 947 0 TEXT "State Labels" | 160390,197270 1 0 0 "WAIT_CRC_RDY\n/43/"
+S 947 734 12288 ELLIPSE "States" | 160390,197270 6500 6500
+W 948 734 8194 789 947 BEZIER "Transitions" | 96995,194201 111991,195168 138952,197162 153948,198129
+W 949 734 0 947 736 BEZIER "Transitions" | 154483,194558 140347,189882 115269,177738 101133,173062
+C 950 949 0 TEXT "Conditions" | 135665,186735 1 0 0 "CRC16UpdateRdy == 1'b1"
+L 951 952 0 TEXT "State Labels" | 35474,185224 1 0 0 "WAIT_CRC_RDY\n/44/"
+S 952 624 16384 ELLIPSE "States" | 35474,185224 6500 6500
+W 953 624 0 952 652 BEZIER "Transitions" | 41843,183928 52367,184199 74470,184214 84994,184485
+C 954 953 0 TEXT "Conditions" | 44940,182382 1 0 0 "CRC5UpdateRdy == 1'b1"
+W 956 360 0 363 1073 BEZIER "Transitions" | 30725,244668 34469,239130 89108,253575 97764,256633
+C 974 973 0 TEXT "Conditions" | 71910,232073 1 0 0 "USBWireGnt == 1'b1"
+W 973 961 0 979 993 BEZIER "Transitions" | 70323,232853 70198,226566 70679,201498 70554,195211
+H 961 958 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+C 960 959 0 TEXT "Conditions" | 51998,52224 1 0 0 "SIEPortCtrl == `TX_LS_KEEP_ALIVE"
+L 431 432 0 TEXT "State Labels" | 171639,58504 1 0 0 "SND_J_1\n/14/"
+S 430 17 0 ELLIPSE "States" | 62301,61312 6500 6500
+L 429 430 0 TEXT "State Labels" | 62301,61312 1 0 0 "SND_SE0_2\n/17/"
+S 428 17 0 ELLIPSE "States" | 169767,93136 6500 6500
+L 427 428 0 TEXT "State Labels" | 169767,93136 1 0 0 "SND_SE0_1\n/16/"
+C 426 425 0 TEXT "Conditions" | 62970,121537 1 0 0 "resumeCnt == `HOST_TX_RESUME_TIME"
+W 425 17 1 407 424 BEZIER "Transitions" | 59198,124338 59315,117669 59604,105482 59721,98813
+L 416 415 0 TEXT "State Labels" | 59644,215155 1 0 0 "WAIT_GNT\n/27/"
+I 417 17 0 Builtin Entry | 44586,243455
+I 418 17 0 Builtin Exit | 171923,20004
+A 420 407 4 TEXT "Actions" | 77715,133314 1 0 0 "USBWireWEn <= 1'b0;"
+L 423 424 0 TEXT "State Labels" | 60229,92346 1 0 0 "W_RDY1\n/41/"
+S 424 17 0 ELLIPSE "States" | 60229,92346 6500 6500
+I 688 633 0 Builtin Entry | 62705,250796
+S 689 633 0 ELLIPSE "States" | 92481,230442 6500 6500
+A 690 689 4 TEXT "Actions" | 111005,232856 1 0 0 "SIEPortTxRdy <= 1'b1;"
+W 691 633 0 689 939 BEZIER "Transitions" | 92993,223971 75388,211318 57781,198664 40176,186011
+C 692 691 0 TEXT "Conditions" | 56194,223187 1 0 0 "SIEPortWEn == 1'b1"
+A 693 691 16 TEXT "Actions" | 43803,209291 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+L 694 689 0 TEXT "State Labels" | 93468,229615 1 0 0 "WAIT_BYTE\n/24/"
+A 695 684 4 TEXT "Actions" | 120585,140116 1 0 0 "CRC5En <= 1'b0;"
+W 696 633 0 680 684 BEZIER "Transitions" | 95455,175338 97065,167173 99679,151534 101289,143369
+A 697 680 4 TEXT "Actions" | 113685,182896 1 0 0 "CRCData <= SIEPortData;\nCRC5_8Bit <= 1'b0;\nCRC5En <= 1'b1;"
+A 698 685 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= {~CRC5Result, SIEPortData[2:0] };\nTxByteOutCtrl <= `DATA_STOP;"
+S 699 633 0 ELLIPSE "States" | 101591,83516 6500 6500
+L 700 699 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT\n/8/"
+L 701 684 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY\n/33/"
+A 702 699 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+S 703 480 0 ELLIPSE "States" | 69140,212180 6500 6500
+I 990 961 0 Builtin Exit | 202744,115664
+I 989 961 0 Builtin Entry | 55468,267637
+L 988 979 0 TEXT "State Labels" | 70526,239337 1 0 0 "WAIT_GNT1\n/45/"
+L 985 984 0 TEXT "State Labels" | 180649,189534 1 0 0 "SND_SE0_1\n/47/"
+S 984 961 32768 ELLIPSE "States" | 180649,189534 6500 6500
+L 983 982 0 TEXT "State Labels" | 72541,157710 1 0 0 "SND_SE0_2\n/46/"
+S 982 961 28672 ELLIPSE "States" | 72541,157710 6500 6500
+S 979 961 24576 ELLIPSE "States" | 70526,239337 6500 6500
+A 978 977 16 TEXT "Actions" | 61762,259858 1 0 0 "USBWireReq <= 1'b1;"
+W 977 961 0 989 979 BEZIER "Transitions" | 59230,267637 62248,262230 65883,250383 66893,244725
+A 447 438 16 TEXT "Actions" | 100527,44161 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `TRI_STATE;\nUSBWireWEn <= 1'b1;"
+A 446 437 16 TEXT "Actions" | 94027,64120 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+A 445 436 16 TEXT "Actions" | 93935,80043 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 444 438 0 TEXT "Conditions" | 151980,31125 1 0 0 "USBWireRdy == 1'b1"
+C 443 437 0 TEXT "Conditions" | 53546,46742 1 0 0 "USBWireRdy == 1'b1"
+C 442 436 0 TEXT "Conditions" | 142323,77914 1 0 0 "USBWireRdy == 1'b1"
+A 441 428 4 TEXT "Actions" | 154674,106708 1 0 0 "USBWireWEn <= 1'b0;"
+A 440 435 16 TEXT "Actions" | 109454,101542 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+C 439 435 0 TEXT "Conditions" | 69889,97267 1 0 0 "USBWireRdy == 1'b1"
+W 438 17 0 1030 434 BEZIER "Transitions" | 180827,34395 168542,28662 79732,38178 67447,32445
+W 437 17 0 1028 432 BEZIER "Transitions" | 51111,44834 62356,44473 153909,58971 165141,58620
+W 436 17 0 1026 430 BEZIER "Transitions" | 180912,80742 169329,74775 79549,70544 67972,64487
+W 435 17 0 424 428 BEZIER "Transitions" | 66726,92159 77841,92276 152154,92898 163269,93015
+S 434 17 0 ELLIPSE "States" | 61659,29488 6500 6500
+L 433 434 0 TEXT "State Labels" | 61659,29488 1 0 0 "SND_J_2\n/15/"
+S 432 17 0 ELLIPSE "States" | 171639,58504 6500 6500
+L 704 703 0 TEXT "State Labels" | 69140,212180 1 0 0 "WAIT_RDY\n/35/"
+W 705 480 0 703 706 BEZIER "Transitions" | 68745,205705 68610,192018 68473,178331 68338,164644
+S 706 480 0 ELLIPSE "States" | 67863,158169 6500 6500
+L 707 706 0 TEXT "State Labels" | 67863,158169 1 0 0 "PKT_SENT\n/9/"
+A 708 705 16 TEXT "Actions" | 48502,190165 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STOP;"
+C 709 705 0 TEXT "Conditions" | 69774,203788 1 0 0 "processTxByteRdy == 1'b1"
+W 710 480 0 711 703 BEZIER "Transitions" | 43257,251277 41695,240058 56424,226913 65578,217615
+I 711 480 0 Builtin Entry | 43257,253243
+A 712 706 4 TEXT "Actions" | 82085,159705 1 0 0 "processTxByteWEn <= 1'b0;"
+I 713 480 0 Builtin Exit | 85376,122104
+W 714 480 0 706 713 BEZIER "Transitions" | 69635,151918 72955,144404 79365,129618 82685,122104
+I 715 471 0 Builtin Exit | 140592,59380
+I 716 471 0 Builtin Entry | 83616,227615
+S 717 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116595,155623 6500 6500
+S 718 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 114290,206333 6500 6500
+L 719 718 0 TEXT "State Labels" | 114290,206333 1 0 0 "PID"
+C 1007 1005 0 TEXT "Conditions" | 80771,193665 1 0 0 "USBWireRdy == 1'b1"
+A 1006 1005 16 TEXT "Actions" | 120336,197940 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 1005 961 0 993 984 BEZIER "Transitions" | 77608,188557 88723,188674 163036,189296 174151,189413
+A 1004 984 4 TEXT "Actions" | 165556,203106 1 0 0 "USBWireWEn <= 1'b0;"
+C 1003 999 0 TEXT "Conditions" | 156382,176802 1 0 0 "USBWireRdy == 1'b1"
+C 1002 997 0 TEXT "Conditions" | 110626,136953 1 0 0 "USBWireRdy == 1'b1"
+A 1000 999 16 TEXT "Actions" | 104380,176838 1 0 0 "USBWireData <= `SE0;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 999 961 0 1016 982 BEZIER "Transitions" | 191758,179211 180175,173244 89868,166719 78285,160752
+A 998 997 16 TEXT "Actions" | 129506,151946 1 0 0 "USBWireData <= JBit;\nUSBWireCtrl <= `DRIVE;\nUSBWireWEn <= 1'b1;"
+W 997 961 0 1018 1008 BEZIER "Transitions" | 102841,134185 114073,133834 169562,153024 180794,152673
+L 994 993 0 TEXT "State Labels" | 71111,188744 1 0 0 "W_RDY1\n/48/"
+S 993 961 36864 ELLIPSE "States" | 71111,188744 6500 6500
+H 458 455 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 455 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 132272,125032 6500 6500
+L 454 455 0 TEXT "State Labels" | 132272,125032 1 0 0 "SPCL"
+S 453 360 0 ELLIPSE "States" | 46763,217013 6500 6500
+L 452 453 0 TEXT "State Labels" | 46763,217013 1 0 0 "WAIT_RDY_PKT\n/40/"
+W 451 17 0 434 418 BEZIER "Transitions" | 68149,29834 86752,29717 150428,26102 169066,20266
+A 450 434 4 TEXT "Actions" | 48667,24292 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+A 449 430 4 TEXT "Actions" | 34545,73018 1 0 0 "USBWireWEn <= 1'b0;"
+A 448 432 4 TEXT "Actions" | 159702,69949 1 0 0 "USBWireWEn <= 1'b0;"
+C 188 13 0 TEXT "Conditions" | 25531,188745 1 0 0 "rst"
+I 187 0 2 Builtin InPort | 186243,246966 "" ""
+L 186 187 0 TEXT "Labels" | 192243,246966 1 0 0 "rst"
+I 185 0 3 Builtin InPort | 186136,252020 "" ""
+L 184 185 0 TEXT "Labels" | 192136,252020 1 0 0 "clk"
+H 727 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 733 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+H 734 717 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 720 471 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115212,96615 6500 6500
+L 721 720 0 TEXT "State Labels" | 115212,96615 1 0 0 "CRC"
+L 722 717 0 TEXT "State Labels" | 116595,155623 1 0 0 "DATA"
+W 723 471 0 720 715 BEZIER "Transitions" | 118058,90773 123244,82936 132611,67217 137797,59380
+W 724 471 0 717 720 BEZIER "Transitions" | 116320,149134 115744,137033 115587,115198 115011,103097
+W 725 471 0 718 717 BEZIER "Transitions" | 114359,199837 114704,190041 115649,171890 115994,162094
+W 726 471 0 716 718 BEZIER "Transitions" | 87378,227615 94177,223812 102260,213992 109059,210189
+C 728 729 0 TEXT "Conditions" | 98125,186740 1 0 0 "processTxByteRdy == 1'b1"
+W 729 727 0 732 742 BEZIER "Transitions" | 97095,188632 96960,174945 96824,161717 96689,148030
+W 730 727 0 731 732 BEZIER "Transitions" | 71380,234686 69818,223467 90464,208437 97872,201588
+I 731 727 0 Builtin Entry | 71380,236621
+S 732 727 0 ELLIPSE "States" | 97491,195105 6500 6500
+L 735 736 0 TEXT "State Labels" | 95348,170101 1 0 0 "UPD_CRC\n/21/"
+W 1023 17 2 407 1022 BEZIER "Transitions" | 52990,130254 48496,130815 40121,131043 37433,133209\
+                                            34745,135375 33783,142213 32901,145984
+S 1022 17 53248 ELLIPSE "States" | 32738,152469 6500 6500
+L 1021 1022 0 TEXT "State Labels" | 32738,152469 1 0 0 "DELAY\n/52/"
+W 1020 961 0 982 1018 BEZIER "Transitions" | 76114,152281 80446,148557 87065,141183 91397,137459
+W 1019 961 0 984 1016 BEZIER "Transitions" | 186591,186901 188111,186673 190020,185744 191540,185516
+S 1018 961 49152 ELLIPSE "States" | 96400,133312 6500 6500
+L 1017 1018 0 TEXT "State Labels" | 96400,133312 1 0 0 "W_RDY3\n/51/"
+S 1016 961 45056 ELLIPSE "States" | 197328,182560 6500 6500
+L 1015 1016 0 TEXT "State Labels" | 197328,182560 1 0 0 "W_RDY2\n/50/"
+W 1014 6 0 958 911 BEZIER "Transitions" | 124457,55847 133850,60002 151714,66762 161174,70737
+A 1012 982 4 TEXT "Actions" | 80404,154242 1 0 0 "USBWireWEn <= 1'b0;"
+A 1011 1008 4 TEXT "Actions" | 175523,169038 1 0 0 "USBWireWEn <= 1'b0;\nUSBWireReq <= 1'b0;"
+W 1010 961 0 1008 990 BEZIER "Transitions" | 189673,146461 206752,122150 181346,115781 199949,115664
+L 1009 1008 0 TEXT "State Labels" | 187291,152508 1 0 0 "SND_J\n/49/"
+S 1008 961 40960 ELLIPSE "States" | 187291,152508 6500 6500
+S 474 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134154,68885 6500 6500
+L 472 465 0 TEXT "State Labels" | 134778,36136 1 0 0 "DATA"
+S 465 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134778,36136 6500 6500
+H 471 465 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+S 736 734 0 ELLIPSE "States" | 95348,170101 6500 6500
+W 737 727 0 742 738 BEZIER "Transitions" | 96587,135073 97277,126966 98440,110637 100308,106008\
+                                           102177,101380 108698,99080 111745,97930
+I 738 727 0 Builtin Exit | 114540,97930
+A 739 742 4 TEXT "Actions" | 110436,143091 1 0 0 "processTxByteWEn <= 1'b0;\nrstCRC <= 1'b0;"
+L 740 732 0 TEXT "State Labels" | 97491,195105 1 0 0 "WAIT_RDY\n/36/"
+L 741 742 0 TEXT "State Labels" | 96214,141555 1 0 0 "PKT_SENT\n/7/"
+S 742 727 0 ELLIPSE "States" | 96214,141555 6500 6500
+A 743 729 16 TEXT "Actions" | 76852,173362 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;\nrstCRC <= 1'b1;"
+I 744 734 0 Builtin Exit | 116402,43935
+S 746 734 0 ELLIPSE "States" | 99353,141110 6500 6500
+C 747 748 0 TEXT "Conditions" | 99987,132745 1 0 0 "processTxByteRdy == 1'b1"
+W 748 734 0 746 772 BEZIER "Transitions" | 98957,134637 98822,120950 98686,107722 98551,94035
+W 749 734 0 750 756 BEZIER "Transitions" | 62952,254840 69047,251390 77619,241763 83714,238313
+I 750 734 0 Builtin Entry | 59190,254840
+A 751 756 4 TEXT "Actions" | 107490,236900 1 0 0 "SIEPortTxRdy <= 1'b1;"
+I 1039 0 130 Builtin Signal | 71756,218122 "" ""
+L 1038 1039 0 TEXT "Labels" | 74756,218122 1 0 0 "resumeCnt[15:0]"
+W 1037 224 0 1035 897 BEZIER "Transitions" | 64606,146870 74406,150350 91859,157715 101659,161195
+W 1036 224 2 891 1035 BEZIER "Transitions" | 101504,123089 91624,127529 74202,135226 64322,139666
+S 1035 224 69632 ELLIPSE "States" | 59060,143481 6500 6500
+L 1034 1035 0 TEXT "State Labels" | 59060,143481 1 0 0 "DELAY\n/56/"
+W 1033 17 0 432 1030 BEZIER "Transitions" | 175464,53250 177630,50201 181501,44488 183667,41439
+W 1032 17 0 430 1028 BEZIER "Transitions" | 56906,57687 55061,55440 50351,52066 48506,49819
+W 1031 17 0 428 1026 BEZIER "Transitions" | 175312,89747 176917,88865 179480,87397 181085,86515
+S 1030 17 65536 ELLIPSE "States" | 187139,35946 6500 6500
+L 1029 1030 0 TEXT "State Labels" | 187139,35946 1 0 0 "W_RDY4\n/55/"
+S 1028 17 61440 ELLIPSE "States" | 44615,44613 6500 6500
+L 1027 1028 0 TEXT "State Labels" | 44615,44613 1 0 0 "W_RDY3\n/54/"
+S 1026 17 57344 ELLIPSE "States" | 186818,83454 6500 6500
+L 1025 1026 0 TEXT "State Labels" | 186818,83454 1 0 0 "W_RDY2\n/53/"
+W 1024 17 0 1022 411 BEZIER "Transitions" | 33384,158929 34668,162139 36269,168519 38877,170084\
+                                            41485,171649 49107,171706 53039,171626
+W 495 360 0 453 493 BEZIER "Transitions" | 46368,210538 46233,196851 46096,183164 45961,169477
+S 493 360 0 ELLIPSE "States" | 45486,163002 6500 6500
+L 492 493 0 TEXT "State Labels" | 45486,163002 1 0 0 "CHK_PID\n/2/"
+L 490 483 0 TEXT "State Labels" | 134497,103286 1 0 0 "TKN"
+S 483 360 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 134497,103286 6500 6500
+H 489 483 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 481 474 0 TEXT "State Labels" | 134154,68885 1 0 0 "HS"
+H 480 474 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+L 212 213 0 TEXT "State Labels" | 113703,129450 1 0 0 "DIR_CTL"
+S 213 6 4 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113934,127848 6500 6500
+L 215 216 0 TEXT "State Labels" | 113402,144340 1 0 0 "IDLE\n/4/"
+S 216 6 0 ELLIPSE "States" | 113402,144340 6500 6500
+C 752 754 0 TEXT "Conditions" | 92034,227575 1 0 0 "SIEPortWEn == 1'b1"
+A 753 754 16 TEXT "Actions" | 69186,217034 1 0 0 "SIEPortData <= SIEPortDataIn;\nSIEPortCtrl <= SIEPortCtrlIn;\nSIEPortTxRdy <= 1'b0;"
+W 754 734 0 756 789 BEZIER "Transitions" | 89129,228010 89081,216045 90467,210855 90419,198890
+L 755 756 0 TEXT "State Labels" | 89953,233659 1 0 0 "WAIT_BYTE\n/25/"
+S 756 734 0 ELLIPSE "States" | 88966,234486 6500 6500
+C 758 759 0 TEXT "Conditions" | 103502,128701 1 0 0 "processTxByteRdy == 1'b1"
+W 759 733 0 760 776 BEZIER "Transitions" | 102472,130593 102337,116906 102201,103678 102066,89991
+S 760 733 0 ELLIPSE "States" | 102868,137066 6500 6500
+W 761 733 0 776 762 BEZIER "Transitions" | 101964,77034 102654,68927 103817,52598 105685,47969\
+                                           107554,43341 114075,41041 117122,39891
+I 762 733 0 Builtin Exit | 119917,39891
+A 765 746 4 TEXT "Actions" | 117070,144160 1 0 0 "CRC16En <= 1'b0;"
+W 766 734 0 736 746 BEZIER "Transitions" | 95556,163608 97166,155443 96164,155578 97774,147413
+A 767 736 4 TEXT "Actions" | 114170,171190 1 0 0 "CRCData <= SIEPortData;\nCRC16En <= 1'b1;"
+A 1046 451 16 TEXT "Actions" | 91713,26530 1 0 0 "USBWireFullSpeedRate <= fullSpeedRateIn;"
+I 1043 0 2 Builtin OutPort | 21464,232442 "" ""
+L 1042 1043 0 TEXT "Labels" | 27464,232442 1 0 0 "USBWireFullSpeedRate"
+I 1041 0 2 Builtin OutPort | 64301,228439 "" ""
+L 1040 1041 0 TEXT "Labels" | 70301,228439 1 0 0 "TxByteOutFullSpeedRate"
+C 511 507 0 TEXT "Conditions" | 51054,101600 1 0 0 "SIEPortData[1:0] == `TOKEN"
+C 510 506 0 TEXT "Conditions" | 63617,125837 1 0 0 "SIEPortData[1:0] == `SPECIAL"
+W 509 360 0 493 465 BEZIER "Transitions" | 45611,156504 46243,128295 46932,73331 47880,57961\
+                                           48829,42592 51359,37532 61605,36267 71852,35002\
+                                           109061,35775 128289,35775
+W 508 360 0 493 474 BEZIER "Transitions" | 45400,156533 46032,136040 46426,97493 47311,86108\
+                                           48196,74723 50474,70169 60657,69030 70840,67892\
+                                           108432,68626 127660,68626
+W 507 360 0 493 483 BEZIER "Transitions" | 45216,156518 45469,145133 45287,123299 46109,116405\
+                                           46931,109511 49715,104703 60024,103501 70334,102300\
+                                           108774,103037 128002,103037
+W 506 360 0 493 455 BEZIER "Transitions" | 45177,156529 45177,152608 45034,145689 45666,142780\
+                                           46299,139871 48829,136075 59202,135063 69575,134052\
+                                           106314,125693 125795,125567
+A 498 493 4 TEXT "Actions" | 59708,164538 1 0 0 "processTxByteWEn <= 1'b0;"
+A 497 495 16 TEXT "Actions" | 26125,194998 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= `SYNC_BYTE;\nTxByteOutCtrl <= `DATA_START;"
+C 496 495 0 TEXT "Conditions" | 47022,204871 1 0 0 "processTxByteRdy == 1'b1"
+H 224 213 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+W 231 6 0 11 216 BEZIER "Transitions" | 41320,156431 41386,153761 41370,148419 41770,146583\
+                                        42170,144748 43639,142745 51849,142311 60059,141877\
+                                        91249,143561 106935,143694
+W 232 6 0 11 213 BEZIER "Transitions" | 41377,156411 41443,149937 41370,137271 41770,133433\
+                                        42170,129596 43639,127192 51882,126624 60126,126057\
+                                        91699,127301 107452,127367
+C 233 232 0 TEXT "Conditions" | 46155,124845 1 0 0 "SIEPortCtrl == `TX_DIRECT_CONTROL"
+C 234 231 0 TEXT "Conditions" | 59709,140676 1 0 0 "SIEPortCtrl == `TX_IDLE"
+W 235 6 0 216 911 BEZIER "Transitions" | 117419,139231 129033,122944 150867,91676 162481,75389
+W 236 6 0 213 911 BEZIER "Transitions" | 118353,123082 128966,111334 151320,86734 161933,74986
+A 768 748 16 TEXT "Actions" | 78714,119367 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= SIEPortData;\nTxByteOutCtrl <= `DATA_STREAM;"
+L 769 772 0 TEXT "State Labels" | 98076,87560 1 0 0 "PKT_SENT\n/10/"
+L 770 746 0 TEXT "State Labels" | 99353,141110 1 0 0 "WAIT_RDY\n/29/"
+A 771 772 4 TEXT "Actions" | 112298,89096 1 0 0 "processTxByteWEn <= 1'b0;"
+S 772 734 0 ELLIPSE "States" | 98076,87560 6500 6500
+A 773 776 4 TEXT "Actions" | 115813,85052 1 0 0 "processTxByteWEn <= 1'b0;"
+L 774 760 0 TEXT "State Labels" | 102868,137066 1 0 0 "WAIT_RDY2\n/39/"
+L 775 776 0 TEXT "State Labels" | 101591,83516 1 0 0 "PKT_SENT2\n/13/"
+S 776 733 0 ELLIPSE "States" | 101591,83516 6500 6500
+A 777 759 16 TEXT "Actions" | 82229,115323 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[15:8];\nTxByteOutCtrl <= `DATA_STOP;"
+L 1071 1072 0 TEXT "Labels" | 130970,218488 1 0 0 "CRC16En"
+W 517 360 0 465 872 BEZIER "Transitions" | 139358,40747 150851,52494 174388,74569 185881,86316
+W 516 360 0 474 872 BEZIER "Transitions" | 140265,71099 152076,75607 174070,81808 185881,86316
+W 515 360 0 483 872 BEZIER "Transitions" | 140706,101366 152453,97810 174134,89872 185881,86316
+W 514 360 0 455 872 BEZIER "Transitions" | 137766,121560 150783,110638 172864,97238 185881,86316
+C 513 509 0 TEXT "Conditions" | 55372,33724 1 0 0 "SIEPortData[1:0] == `DATA"
+C 512 508 0 TEXT "Conditions" | 54864,67310 1 0 0 "SIEPortData[1:0] == `HANDSHAKE"
+I 787 733 0 Builtin Entry | 62705,250796
+L 788 789 0 TEXT "State Labels" | 90750,192400 1 0 0 "CHK_STOP\n/3/"
+S 789 734 0 ELLIPSE "States" | 90750,192400 6500 6500
+W 790 734 8193 789 744 BEZIER "Transitions" | 84430,190883 71180,188633 44000,183400 37625,167025\
+                                              31250,150650 32250,89650 34750,72525 37250,55400\
+                                              46250,47900 56000,46150 65750,44400 95896,46012\
+                                              103573,44899 111250,43786 113107,43935 113607,43935
+C 791 790 0 TEXT "Conditions" | 28148,194956 1 0 0 "SIEPortCtrl == `TX_PACKET_STOP"
+W 795 734 0 772 756 BEZIER "Transitions" | 100994,81753 104106,78392 108938,71609 118897,69430\
+                                           128857,67252 162473,65260 171997,66691 181521,68123\
+                                           186003,75843 187123,97692 188244,119542 188244,199222\
+                                           184384,221196 180525,243170 165087,251388 155563,253628\
+                                           146039,255869 123379,256617 115100,254625 106821,252633\
+                                           98206,243956 92977,239599
+S 797 733 0 ELLIPSE "States" | 98719,229711 6500 6500
+W 798 733 0 797 801 BEZIER "Transitions" | 98323,223238 98188,209551 98052,196323 97917,182636
+C 799 798 0 TEXT "Conditions" | 99353,221346 1 0 0 "processTxByteRdy == 1'b1"
+A 1082 1080 16 TEXT "Actions" | 95072,224240 1 0 0 "TxByteOutFullSpeedRate <= 1'b1; //SOF and PRE always at full speed"
+C 1081 1080 0 TEXT "Conditions" | 102248,241873 1 0 0 "SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE"
+W 1080 360 1 1073 453 BEZIER "Transitions" | 103127,252141 112392,249752 130361,224032 127627,220759\
+                                             124894,217487 107954,214253 97790,213829 87626,213406\
+                                             65074,215466 53216,216236
+W 1079 360 2 1073 453 BEZIER "Transitions" | 97595,252197 93012,236072 61888,222891 52340,220350
+W 1078 1075 0 1076 1077 BEZIER "Transitions" | 90122,167640 102263,150334 114604,129067 126745,111760
+I 1077 1075 0 Builtin Exit | 129540,111760
+I 1076 1075 0 Builtin Entry | 86360,167640
+L 1074 1073 0 TEXT "State Labels" | 100383,254312 1 0 0 "J3"
+S 1073 360 73748 ELLIPSE "Junction" | 100383,254312 3500 3500
+H 1075 1073 0 RECT 0,0,0 0 0 1 255,255,255 0 | 15700,15700 200200,263700
+I 1072 0 2 Builtin OutPort | 124970,218488 "" ""
+I 540 458 0 Builtin Exit | 68103,43333
+A 800 798 16 TEXT "Actions" | 78080,207968 1 0 0 "processTxByteWEn <= 1'b1;\nTxByteOut <= ~CRC16Result[7:0];\nTxByteOutCtrl <= `DATA_STREAM;"
+S 801 733 0 ELLIPSE "States" | 97442,176161 6500 6500
+L 802 801 0 TEXT "State Labels" | 97442,176161 1 0 0 "PKT_SENT1\n/11/"
+L 803 797 0 TEXT "State Labels" | 98719,229711 1 0 0 "WAIT_RDY1\n/38/"
+A 804 801 4 TEXT "Actions" | 111664,177697 1 0 0 "processTxByteWEn <= 1'b0;"
+W 805 733 0 787 797 BEZIER "Transitions" | 66467,250796 73606,246725 85810,236773 92949,232702
+W 806 733 0 801 760 BEZIER "Transitions" | 98101,169695 98927,162969 100807,150169 101633,143443
+L 807 808 0 TEXT "Labels" | 24830,251978 1 0 0 "SIEPortWEn"
+I 808 0 2 Builtin InPort | 18830,251978 "" ""
+L 809 810 0 TEXT "Labels" | 22510,247106 1 0 0 "SIEPortTxRdy"
+I 810 0 2 Builtin OutPort | 16510,247106 "" ""
+L 811 812 0 TEXT "Labels" | 24598,242466 1 0 0 "SIEPortDataIn[7:0]"
+I 812 0 130 Builtin InPort | 18598,242466 "" ""
+L 813 814 0 TEXT "Labels" | 25062,237826 1 0 0 "SIEPortCtrlIn[7:0]"
+I 814 0 130 Builtin InPort | 19062,237826 "" ""
+L 815 816 0 TEXT "Labels" | 70372,247878 1 0 0 "processTxByteWEn"
+END

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/SIETransmitter.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v	(revision 264)
@@ -0,0 +1,422 @@
+
+// File        : ../RTL/serialInterfaceEngine/processRxBit.v
+// Generated   : 11/10/06 05:37:22
+// From        : ../RTL/serialInterfaceEngine/processRxBit.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processrxbit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, fullSpeedBitRate);
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [1:0] RxBitsIn;
+input   RxWireActive;
+input   clk;
+input   processRxBitsWEn;
+input   processRxByteRdy;
+input   rst;
+output  [7:0] RxCtrlOut;
+output  [7:0] RxDataOut;
+output  processRxBitRdy;
+output  processRxByteWEn;
+output  resumeDetected;
+input fullSpeedBitRate;
+
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [1:0] RxBitsIn;
+reg     [7:0] RxCtrlOut, next_RxCtrlOut;
+reg     [7:0] RxDataOut, next_RxDataOut;
+wire    RxWireActive;
+wire    clk;
+reg     processRxBitRdy, next_processRxBitRdy;
+wire    processRxBitsWEn;
+wire    processRxByteRdy;
+reg     processRxByteWEn, next_processRxByteWEn;
+reg     resumeDetected, next_resumeDetected;
+wire    rst;
+
+// diagram signals declarations
+reg  [3:0]RXBitCount, next_RXBitCount;
+reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg  [7:0]RXByte, next_RXByte;
+reg  [3:0]RXSameBitCount, next_RXSameBitCount;
+reg  [1:0]RxBits, next_RxBits;
+reg  bitStuffError, next_bitStuffError;
+reg  [1:0]oldRXBits, next_oldRXBits;
+reg  [4:0]resumeWaitCnt, next_resumeWaitCnt;
+reg  [7:0]delayCnt, next_delayCnt;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+`define LOW_SPEED_EOP_DELAY 4'b1111
+
+reg [3:0] CurrState_prRxBit;
+reg [3:0] NextState_prRxBit;
+
+
+//--------------------------------------------------------------------
+// Machine: prRxBit
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (*)
+begin : prRxBit_NextState
+  NextState_prRxBit <= CurrState_prRxBit;
+  // Set default values for outputs and signals
+  next_processRxByteWEn <= processRxByteWEn;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOut <= RxDataOut;
+  next_resumeDetected <= resumeDetected;
+  next_RXBitStMachCurrState <= RXBitStMachCurrState;
+  next_RxBits <= RxBits;
+  next_RXSameBitCount <= RXSameBitCount;
+  next_RXBitCount <= RXBitCount;
+  next_oldRXBits <= oldRXBits;
+  next_RXByte <= RXByte;
+  next_bitStuffError <= bitStuffError;
+  next_resumeWaitCnt <= resumeWaitCnt;
+  next_delayCnt <= delayCnt;
+  next_processRxBitRdy <= processRxBitRdy;
+  case (CurrState_prRxBit)
+    `START:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOut <= 8'h00;
+      next_resumeDetected <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_RxBits <= 2'b00;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h0;
+      next_oldRXBits <= 2'b00;
+      next_RXByte <= 8'h00;
+      next_bitStuffError <= 1'b0;
+      next_resumeWaitCnt <= 5'h0;
+      next_processRxBitRdy <= 1'b1;
+      NextState_prRxBit <= `WAIT_BITS;
+    end
+    `WAIT_BITS:
+      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))	
+      begin
+        NextState_prRxBit <= `RES_RX_CHK;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))	
+      begin
+        NextState_prRxBit <= `DATA_RX_CHK_SE0;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))	
+      begin
+        NextState_prRxBit <= `IDLE_CHK_KBIT;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))	
+      begin
+        NextState_prRxBit <= `RES_END_CHK1;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+    `IDLE_FIRST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h1;
+      next_oldRXBits <= RxBits;
+      //zero is always the first RZ data bit of a new packet
+      next_RXByte <= 8'h00;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `IDLE_CHK_KBIT:
+      if ((RxBits == KBit) && (RxWireActive == 1'b1))	
+        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    `IDLE_WAIT_PRB_RDY:
+      if (processRxByteRdy == 1'b1)	
+      begin
+        NextState_prRxBit <= `IDLE_FIRST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_START;
+        //start of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    `DATA_RX_LAST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_CHK_SE0:
+    begin
+      next_bitStuffError <= 1'b0;
+      if (RxBits == `SE0) begin
+        if (fullSpeedBitRate == 1'b0) begin
+          NextState_prRxBit <= `LOW_SPEED_EOP_DELAY;
+          next_delayCnt <= 8'h00;
+        end
+        else
+          NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+      end
+      else
+      begin
+        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
+        begin
+          next_RXSameBitCount <= RXSameBitCount + 1'b1;
+            //inc 'RXSameBitCount'
+            if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+            next_bitStuffError <= 1'b1;
+                //flag 'bitStuffError'
+            else                                          //else no bit stuffing error
+            begin
+            next_RXBitCount <= RXBitCount + 1'b1;
+                if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+              next_processRxBitRdy <= 1'b1;
+                    //early indication of ready
+        		end
+            next_RXByte <= { 1'b1, RXByte[7:1]};
+                //RZ bit = 1 (ie no change in 'RxBits')
+            end
+        end
+        else                                            //else current 'RxBits' are different from old 'RxBits'
+        begin
+            if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+            begin
+            next_RXBitCount <= RXBitCount + 1'b1;
+                if (RXBitCount != 4'h7) begin
+              next_processRxBitRdy <= 1'b1;
+                    //early indication of ready
+        		end
+            next_RXByte <= {1'b0, RXByte[7:1]};
+                //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
+            end
+           next_RXSameBitCount <= 4'h0;
+              //reset 'RXSameBitCount'
+        end
+        next_oldRXBits <= RxBits;
+      end
+    end
+    `DATA_RX_WAIT_PRB_RDY:
+      if (processRxByteRdy == 1'b1)	
+      begin
+        NextState_prRxBit <= `DATA_RX_LAST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_STOP;
+        //end of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    `DATA_RX_DATA_DESTUFF:
+      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)	
+        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+      else if (bitStuffError == 1'b1)	
+        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    `DATA_RX_BYTE_SEND2:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_BYTE_WAIT_RDY:
+      if (processRxByteRdy == 1'b1)	
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+        next_RXBitCount <= 4'h0;
+        next_RxDataOut <= RXByte;
+        next_RxCtrlOut <= `DATA_STREAM;
+        next_processRxByteWEn <= 1'b1;
+      end
+    `DATA_RX_ERROR_CHK_RES:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      if (RxBits == JBit)                           //if current bit is a JBit, then
+        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+          //next state is idle
+      else                                          //else
+      begin
+        next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+          //check for resume
+        next_resumeWaitCnt <= 5'h0;
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_ERROR_WAIT_RDY:
+      if (processRxByteRdy == 1'b1)	
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+        next_processRxByteWEn <= 1'b1;
+      end
+    `RES_RX_CHK:
+    begin
+      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
+        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      else
+      begin
+        next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+          //if we've waited long enough, then
+          if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
+          begin
+          next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+          next_resumeDetected <= 1'b1;
+              //report resume detected
+          end
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `RES_END_CHK1:
+    begin
+      if (RxBits != KBit)  //line must leave KBit state for the end of resume
+      begin
+        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+        next_resumeDetected <= 1'b0;
+          //clear resume detected flag
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `LOW_SPEED_EOP_DELAY:
+    begin
+      //turn around time must be at least 2 low speed bit periods
+      next_delayCnt <= delayCnt + 1'b1;
+      if (delayCnt == `LS_OVER_SAMPLE_RATE * 2)
+        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prRxBit_CurrentState
+  if (rst)	
+    CurrState_prRxBit <= `START;
+  else
+    CurrState_prRxBit <= NextState_prRxBit;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prRxBit_RegOutput
+  if (rst)	
+  begin
+    RXBitStMachCurrState <= `IDLE_BIT_ST;
+    RxBits <= 2'b00;
+    RXSameBitCount <= 4'h0;
+    RXBitCount <= 4'h0;
+    oldRXBits <= 2'b00;
+    RXByte <= 8'h00;
+    bitStuffError <= 1'b0;
+    resumeWaitCnt <= 5'h0;
+    delayCnt <= 8'h00;
+    processRxByteWEn <= 1'b0;
+    RxCtrlOut <= 8'h00;
+    RxDataOut <= 8'h00;
+    resumeDetected <= 1'b0;
+    processRxBitRdy <= 1'b1;
+  end
+  else 
+  begin
+    RXBitStMachCurrState <= next_RXBitStMachCurrState;
+    RxBits <= next_RxBits;
+    RXSameBitCount <= next_RXSameBitCount;
+    RXBitCount <= next_RXBitCount;
+    oldRXBits <= next_oldRXBits;
+    RXByte <= next_RXByte;
+    bitStuffError <= next_bitStuffError;
+    resumeWaitCnt <= next_resumeWaitCnt;
+    delayCnt <= next_delayCnt;
+    processRxByteWEn <= next_processRxByteWEn;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOut <= next_RxDataOut;
+    resumeDetected <= next_resumeDetected;
+    processRxBitRdy <= next_processRxBitRdy;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processRxBit.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v	(revision 264)
@@ -0,0 +1,450 @@
+
+// File        : ../RTL/serialInterfaceEngine/processTxByte.v
+// Generated   : 11/10/06 05:37:23
+// From        : ../RTL/serialInterfaceEngine/processTxByte.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processTxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [7:0] TxByteCtrlIn;
+input   TxByteFullSpeedRateIn;
+input   [7:0] TxByteIn;
+input   USBWireGnt;
+input   USBWireRdy;
+input   clk;
+input   processTxByteWEn;
+input   rst;
+output  USBWireCtrl;
+output  [1:0] USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+output  processTxByteRdy;
+
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [7:0] TxByteCtrlIn;
+wire    TxByteFullSpeedRateIn;
+wire    [7:0] TxByteIn;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0] USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+reg     processTxByteRdy, next_processTxByteRdy;
+wire    processTxByteWEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [1:0]TXLineState, next_TXLineState;
+reg  [3:0]TXOneCount, next_TXOneCount;
+reg  [7:0]TxByteCtrl, next_TxByteCtrl;
+reg  TxByteFullSpeedRate, next_TxByteFullSpeedRate;
+reg  [7:0]TxByte, next_TxByte;
+reg  [3:0]i, next_i;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+`define LS_START_W_RDY1 5'b10110
+`define LS_START_W_RDY2 5'b10111
+`define LS_START_W_RDY3 5'b11000
+`define STOP_W_RDY1 5'b11001
+`define STOP_W_RDY2 5'b11010
+`define STOP_W_RDY3 5'b11011
+`define STOP_W_RDY4 5'b11100
+
+reg [4:0] CurrState_prcTxB;
+reg [4:0] NextState_prcTxB;
+
+
+//--------------------------------------------------------------------
+// Machine: prcTxB
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB)
+begin : prcTxB_NextState
+  NextState_prcTxB <= CurrState_prcTxB;
+  // Set default values for outputs and signals
+  next_processTxByteRdy <= processTxByteRdy;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_USBWireReq <= USBWireReq;
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_TxByte <= TxByte;
+  next_TxByteCtrl <= TxByteCtrl;
+  next_TXLineState <= TXLineState;
+  next_TXOneCount <= TXOneCount;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
+  case (CurrState_prcTxB)
+    `START_PTBY:
+    begin
+      next_processTxByteRdy <= 1'b0;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_i <= 4'h0;
+      next_TxByte <= 8'h00;
+      next_TxByteCtrl <= 8'h00;
+      next_TXLineState <= 2'b0;
+      next_TXOneCount <= 4'h0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      next_TxByteFullSpeedRate <= 1'b0;
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `PTBY_WAIT_EN:
+    begin
+      next_processTxByteRdy <= 1'b1;
+      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))	
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_GNT;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_TXOneCount <= 4'h0;
+        next_TXLineState <= JBit;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (processTxByteWEn == 1'b1)	
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_i <= 4'h0;
+      end
+    end
+    `PTBY_WAIT_GNT:
+      if (USBWireGnt == 1'b1)	
+        NextState_prcTxB <= `WAIT_RDY_WIRE;
+    `WAIT_RDY_WIRE:
+      if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate  == 1'b0))	
+        NextState_prcTxB <= `LS_START_SND_IDLE1;
+      else if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `WAIT_RDY_PKT;
+        //actively drive the first J bit
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `WAIT_RDY_PKT:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `SEND_BYTE_UPDATE_BYTE:
+    begin
+      next_i <= i + 1'b1;
+      next_TxByte <= {1'b0, TxByte[7:1] };
+      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
+        next_TXOneCount <= TXOneCount + 1'b1;
+          //increment 'TXOneCount'
+      else                                        //else this is a zero bit
+      begin
+        next_TXOneCount <= 4'h0;
+          //reset 'TXOneCount'
+          if (TXLineState == JBit)
+          next_TXLineState <= KBit;
+              //toggle the line state
+          else
+          next_TXLineState <= JBit;
+      end
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+    end
+    `SEND_BYTE_WAIT_RDY:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `SEND_BYTE_CHK:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (TXOneCount == `MAX_CONSEC_SAME_BITS)	
+        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+      else if (i != 4'h8)	
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      else
+        NextState_prcTxB <= `STOP_CHK;
+    end
+    `SEND_BYTE_BIT_STUFF:
+    begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+        next_TXLineState <= KBit;
+          //toggle the line state
+      else
+        next_TXLineState <= JBit;
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+    end
+    `SEND_BYTE_WAIT_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `SEND_BYTE_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (i == 4'h8)	
+        NextState_prcTxB <= `STOP_CHK;
+      else
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+    end
+    `STOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY2;
+    end
+    `STOP_SND_SE0_1:
+      NextState_prcTxB <= `STOP_W_RDY1;
+    `STOP_CHK:
+      if (TxByteCtrl == `DATA_STOP)	
+        NextState_prcTxB <= `STOP_SND_SE0_1;
+      else if (TxByteCtrl == `DATA_STOP_PRE)	
+        NextState_prcTxB <= `STOP_SND_J;
+      else
+        NextState_prcTxB <= `PTBY_WAIT_EN;
+    `STOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY3;
+    end
+    `STOP_SND_IDLE:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY4;
+    end
+    `STOP_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      //release the wire
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `STOP_W_RDY1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `STOP_W_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `STOP_SND_J;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `STOP_W_RDY3:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `STOP_SND_IDLE;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `STOP_W_RDY4:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `STOP_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    `LS_START_SND_IDLE3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY2;
+    end
+    `LS_START_SND_J1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY3;
+    end
+    `LS_START_SND_IDLE1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    `LS_START_SND_IDLE2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY1;
+    end
+    `LS_START_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `LS_START_W_RDY1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE3;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    `LS_START_W_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `LS_START_SND_J1;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    `LS_START_W_RDY3:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `LS_START_FIN;
+        //Drive the first JBit
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prcTxB_CurrentState
+  if (rst)	
+    CurrState_prcTxB <= `START_PTBY;
+  else
+    CurrState_prcTxB <= NextState_prcTxB;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prcTxB_RegOutput
+  if (rst)	
+  begin
+    i <= 4'h0;
+    TxByte <= 8'h00;
+    TxByteCtrl <= 8'h00;
+    TXLineState <= 2'b0;
+    TXOneCount <= 4'h0;
+    TxByteFullSpeedRate <= 1'b0;
+    processTxByteRdy <= 1'b0;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    USBWireReq <= 1'b0;
+    USBWireWEn <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+  end
+  else 
+  begin
+    i <= next_i;
+    TxByte <= next_TxByte;
+    TxByteCtrl <= next_TxByteCtrl;
+    TXLineState <= next_TXLineState;
+    TXOneCount <= next_TXOneCount;
+    TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
+    processTxByteRdy <= next_processTxByteRdy;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    USBWireReq <= next_USBWireReq;
+    USBWireWEn <= next_USBWireWEn;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+  end
+end
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/processTxByte.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/updateCRC16.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/updateCRC16.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/updateCRC16.v	(revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC16.v                                                ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [15:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [15:0] CRCResult;
+reg    ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 16'hffff;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0)
+    begin
+      if (CRCEn == 1'b1) begin
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        ready <= 1'b0;
+    end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[15:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == 4'h7)
+      begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/updateCRC16.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbTxWireArbiter.v	(revision 264)
@@ -0,0 +1,213 @@
+
+// File        : ../RTL/serialInterfaceEngine/usbTxWireArbiter.v
+// Generated   : 11/10/06 05:37:24
+// From        : ../RTL/serialInterfaceEngine/usbTxWireArbiter.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbTxWireArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn, clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst);
+input   SIETxCtrl;
+input   [1:0] SIETxData;
+input   SIETxFSRate;
+input   SIETxReq;
+input   SIETxWEn;
+input   USBWireRdyIn;
+input   clk;
+input   prcTxByteCtrl;
+input   [1:0] prcTxByteData;
+input   prcTxByteFSRate;
+input   prcTxByteReq;
+input   prcTxByteWEn;
+input   rst;
+output  SIETxGnt;
+output  [1:0] TxBits;
+output  TxCtl;
+output  TxFSRate;
+output  USBWireRdyOut;
+output  USBWireWEn;
+output  prcTxByteGnt;
+
+wire    SIETxCtrl;
+wire    [1:0] SIETxData;
+wire    SIETxFSRate;
+reg     SIETxGnt, next_SIETxGnt;
+wire    SIETxReq;
+wire    SIETxWEn;
+reg     [1:0] TxBits, next_TxBits;
+reg     TxCtl, next_TxCtl;
+reg     TxFSRate, next_TxFSRate;
+wire    USBWireRdyIn;
+reg     USBWireRdyOut, next_USBWireRdyOut;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+wire    prcTxByteCtrl;
+wire    [1:0] prcTxByteData;
+wire    prcTxByteFSRate;
+reg     prcTxByteGnt, next_prcTxByteGnt;
+wire    prcTxByteReq;
+wire    prcTxByteWEn;
+wire    rst;
+
+// diagram signals declarations
+reg  muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0] CurrState_txWireArb;
+reg [1:0] NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+    USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
+SIETxFSRate or prcTxByteFSRate)
+begin
+    if (muxSIENotPTXB  == 1'b1)
+    begin
+        USBWireWEn <= SIETxWEn;
+        TxBits <= SIETxData;
+        TxCtl <= SIETxCtrl;
+        TxFSRate <= SIETxFSRate;
+    end
+    else
+    begin
+        USBWireWEn <= prcTxByteWEn;
+        TxBits <= prcTxByteData;
+        TxCtl <= prcTxByteCtrl;
+        TxFSRate <= prcTxByteFSRate;
+    end
+end
+
+//--------------------------------------------------------------------
+// Machine: txWireArb
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb)
+begin : txWireArb_NextState
+  NextState_txWireArb <= CurrState_txWireArb;
+  // Set default values for outputs and signals
+  next_prcTxByteGnt <= prcTxByteGnt;
+  next_muxSIENotPTXB <= muxSIENotPTXB;
+  next_SIETxGnt <= SIETxGnt;
+  case (CurrState_txWireArb)
+    `START_TARB:
+      NextState_txWireArb <= `TARB_WAIT_REQ;
+    `TARB_WAIT_REQ:
+      if (prcTxByteReq == 1'b1)	
+      begin
+        NextState_txWireArb <= `PTXB_ACT;
+        next_prcTxByteGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b0;
+      end
+      else if (SIETxReq == 1'b1)	
+      begin
+        NextState_txWireArb <= `SIE_TX_ACT;
+        next_SIETxGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b1;
+      end
+    `PTXB_ACT:
+      if (prcTxByteReq == 1'b0)	
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_prcTxByteGnt <= 1'b0;
+      end
+    `SIE_TX_ACT:
+      if (SIETxReq == 1'b0)	
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_SIETxGnt <= 1'b0;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : txWireArb_CurrentState
+  if (rst)	
+    CurrState_txWireArb <= `START_TARB;
+  else
+    CurrState_txWireArb <= NextState_txWireArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : txWireArb_RegOutput
+  if (rst)	
+  begin
+    muxSIENotPTXB <= 1'b0;
+    prcTxByteGnt <= 1'b0;
+    SIETxGnt <= 1'b0;
+  end
+  else 
+  begin
+    muxSIENotPTXB <= next_muxSIENotPTXB;
+    prcTxByteGnt <= next_prcTxByteGnt;
+    SIETxGnt <= next_SIETxGnt;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/usbTxWireArbiter.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/fifoMux.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/fifoMux.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/fifoMux.v	(revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module fifoMux (
+  currEndP,
+  //TxFifo
+  TxFifoREn,
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoData,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEmpty,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  //RxFifo
+  RxFifoWEn,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoFull,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+  //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+  //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+  TxFifoREn or
+  RxFifoWEn or
+  TxFifoEP0Data or
+  TxFifoEP1Data or
+  TxFifoEP2Data or
+  TxFifoEP3Data or
+  TxFifoEP0Empty or
+  TxFifoEP1Empty or
+  TxFifoEP2Empty or
+  TxFifoEP3Empty or
+  RxFifoEP0Full or
+  RxFifoEP1Full or
+  RxFifoEP2Full or
+  RxFifoEP3Full)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      TxFifoEP0REn <= TxFifoREn;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP0Data;
+      TxFifoEmpty <= TxFifoEP0Empty;
+      RxFifoEP0WEn <= RxFifoWEn;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP0Full;
+    end
+    2'b01: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= TxFifoREn;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP1Data;
+      TxFifoEmpty <= TxFifoEP1Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= RxFifoWEn;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP1Full;
+    end
+    2'b10: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= TxFifoREn;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP2Data;
+      TxFifoEmpty <= TxFifoEP2Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= RxFifoWEn;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP2Full;
+    end
+    2'b11: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= TxFifoREn;
+      TxFifoData <= TxFifoEP3Data;
+      TxFifoEmpty <= TxFifoEP3Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= RxFifoWEn;
+      RxFifoFull <= RxFifoEP3Full;
+    end
+  endcase  
+end      
+
+
+endmodule

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/fifoMux.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/slaveDirectcontrol.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/slaveDirectcontrol.v	(revision 264)
@@ -0,0 +1,197 @@
+
+// File        : ../RTL/slaveController/slaveDirectcontrol.v
+// Generated   : 11/10/06 05:37:25
+// From        : ../RTL/slaveController/slaveDirectcontrol.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveDirectControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   clk;
+input   directControlEn;
+input   [1:0] directControlLineState;
+input   rst;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+wire    clk;
+wire    directControlEn;
+wire    [1:0] directControlLineState;
+wire    rst;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0] CurrState_slvDrctCntl;
+reg [2:0] NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// diagram ACTION
+
+//--------------------------------------------------------------------
+// Machine: slvDrctCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)
+begin : slvDrctCntl_NextState
+  NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+  // Set default values for outputs and signals
+  next_SCTxPortReq <= SCTxPortReq;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortCntl <= SCTxPortCntl;
+  case (CurrState_slvDrctCntl)
+    `START_SDC:
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    `CHK_DRCT_CNTL:
+      if (directControlEn == 1'b1)	
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+    `DRCT_CNTL_WAIT_GNT:
+      if (SCTxPortGnt == 1'b1)	
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)	
+      begin
+        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+        next_SCTxPortReq <= 1'b0;
+      end
+      else
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+    end
+    `DRCT_CNTL_WAIT_RDY:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= {6'b000000, directControlLineState};
+        next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    `IDLE_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      next_SCTxPortReq <= 1'b0;
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+      if (SCTxPortGnt == 1'b1)	
+        NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+    `IDLE_WAIT_RDY:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvDrctCntl <= `IDLE_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_IDLE;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_CurrentState
+  if (rst)	
+    CurrState_slvDrctCntl <= `START_SDC;
+  else
+    CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_RegOutput
+  if (rst)	
+  begin
+    SCTxPortCntl <= 8'h00;
+    SCTxPortData <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/slaveDirectcontrol.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/slaveController/slaveSendpacket.asf
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/slaveSendpacket.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/slaveSendpacket.asf	(revision 264)
@@ -0,0 +1,171 @@
+VERSION=1.15
+HEADER
+FILE="slaveSendpacket.asf"
+FID=405e9201
+LANGUAGE=VERILOG
+ENTITY="slaveSendPacket"
+FRAMES=ON
+FREEOID=215
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// slaveSendPacket\n////                                                              ////\n//// This file is part of the usbhostslave opencores effort.\n//// http://www.opencores.org/cores/usbhostslave/                 ////\n////                                                              ////\n//// Module Description:                                          ////\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from http://www.opencores.org/lgpl.shtml                     ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n//\n`include \"timescale.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbConstants_h.v\"\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3333 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3333 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 0  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3333 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 0  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3333 0 0000 0  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 0  "Arial" 0
+B F "Junction" 0,0,0 0 0 1 255,0,0 1 3527 1480 0000 0  "Arial" 0
+B F "Initial State Indicator" 0,0,0 0 0 1 240,140,40 1 3527 1480 0000 0  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+INSTHEADER 21
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 45
+PAGE 25400,0 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+S 11 6 4096 ELLIPSE "States" | 110774,159341 6500 6500
+L 10 11 0 TEXT "State Labels" | 110774,159341 1 0 0 "SP_WAIT_ENABLE\n/1/"
+S 9 6 0 ELLIPSE "States" | 108917,188434 6500 6500
+L 8 9 0 TEXT "State Labels" | 108917,188434 1 0 0 "START_SP1\n/0/"
+L 7 6 0 TEXT "Labels" | 32660,203132 1 0 0 "slvSndPkt"
+F 6 0 671089152 188 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,3000 212900,208064
+A 5 0 1 TEXT "Actions" | 29672,248644 1 0 0 "always @(PID)\nbegin\n  PIDNotPID <=  { (PID ^ 4'hf), PID };\nend"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 0  "Arial" 0 | 110650,251000 1 0 0 "Module: slaveSendPacket"
+I 12 6 0 Builtin Reset | 74872,202290
+W 13 6 0 12 9 BEZIER "Transitions" | 74872,202290 82145,199755 95857,193927 103130,191392
+W 14 6 0 9 11 BEZIER "Transitions" | 108829,181945 109138,177774 109593,169949 109902,165778
+L 15 16 0 TEXT "State Labels" | 112482,123658 1 0 0 "SP1_WAIT_GNT\n/2/"
+S 16 6 8192 ELLIPSE "States" | 112482,123658 6500 6500
+W 17 6 0 11 16 BEZIER "Transitions" | 110929,152860 111315,148225 111934,134981 112152,130145
+C 18 17 0 TEXT "Conditions" | 111903,152311 1 0 0 "sendPacketWEn == 1'b1"
+A 19 17 16 TEXT "Actions" | 106114,144280 1 0 0 "sendPacketRdy <= 1'b0;\nSCTxPortReq <= 1'b1;"
+L 20 21 0 TEXT "State Labels" | 113767,93734 1 0 0 "SP_SEND_PID"
+S 21 6 12292 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 113767,93734 6500 6500
+W 22 6 0 16 21 BEZIER "Transitions" | 112482,117158 112791,112755 112951,104607 113260,100204
+C 23 22 0 TEXT "Conditions" | 114630,116691 1 0 0 "SCTxPortGnt == 1'b1"
+H 25 21 0 RECT 0,0,0 0 0 1 255,255,255 0 | 29624,2084 214124,250084
+S 26 25 16384 ELLIPSE "States" | 72734,192072 6500 6500
+L 27 26 0 TEXT "State Labels" | 72734,192775 1 0 0 "WAIT_RDY\n/3/"
+I 28 25 0 Builtin Entry | 49237,230379
+I 29 25 0 Builtin Exit | 146004,95604
+W 30 25 0 28 26 BEZIER "Transitions" | 53779,230379 60054,220138 63123,209223 69341,197615
+L 32 33 0 TEXT "State Labels" | 75021,153035 1 0 0 "FIN\n/4/"
+S 33 25 20480 ELLIPSE "States" | 75021,153035 6500 6500
+W 34 25 0 26 33 BEZIER "Transitions" | 72953,185597 73302,178879 73960,166205 74309,159487
+C 36 34 0 TEXT "Conditions" | 75236,185214 1 0 0 "SCTxPortRdy == 1'b1"
+A 37 34 16 TEXT "Actions" | 67602,177580 1 0 0 "SCTxPortWEn <= 1'b1;\nSCTxPortData <= PIDNotPID;\nSCTxPortCntl <= `TX_PACKET_START;"
+A 38 33 4 TEXT "Actions" | 93627,154331 1 0 0 "SCTxPortWEn <= 1'b0;"
+W 39 25 0 33 29 BEZIER "Transitions" | 79375,148210 95944,135371 126275,108443 142844,95604
+L 44 45 0 TEXT "State Labels" | 182202,45960 1 0 0 "SP_D0_D1"
+S 45 6 24580 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 182202,45960 6500 6500
+L 46 47 0 TEXT "State Labels" | 115848,16910 1 0 0 "FIN_SP1\n/5/"
+S 47 6 28672 ELLIPSE "States" | 115848,16910 6500 6500
+W 48 6 8194 21 205 BEZIER "Transitions" | 108645,89734 97773,80901 77133,63853 66261,55020
+W 50 6 8193 21 45 BEZIER "Transitions" | 119169,90120 134042,80003 162156,60011 177029,49894
+H 65 45 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,2136 212900,250688
+W 73 6 0 45 47 BEZIER "Transitions" | 176581,42697 162161,37714 135904,25306 121888,19311
+W 74 6 0 205 47 BEZIER "Transitions" | 67096,47093 78647,41129 99521,27639 110324,20335
+W 75 6 0 47 11 BEZIER "Transitions" | 110250,13609 107004,12024 101864,9321 93182,8641\
+                                      84500,7962 56262,8416 48108,10114 39955,11813\
+                                      35575,18155 34480,31669 33386,45184 33386,92900\
+                                      35198,110038 37010,127177 44258,148015 49996,153300\
+                                      55734,158585 71438,158887 78535,158887 85632,158887\
+                                      97934,159370 104276,159219
+A 77 75 16 TEXT "Actions" | 56036,13776 1 0 0 "sendPacketRdy <= 1'b1;\nSCTxPortReq <= 1'b0;"
+C 81 50 0 TEXT "Conditions" | 136027,85940 1 0 0 "PID == `DATA0 || PID == `DATA1"
+I 127 65 0 Builtin Exit | 176933,37229
+I 126 65 0 Builtin Entry | 68162,237252
+L 143 142 0 TEXT "State Labels" | 93499,188608 1 0 0 "WAIT_READ_FIFO\n/7/"
+S 142 65 36864 ELLIPSE "States" | 93499,187905 6500 6500
+A 141 136 4 TEXT "Actions" | 118498,153974 1 0 0 "SCTxPortWEn <= 1'b1;	 \nSCTxPortData <= fifoData;\nSCTxPortCntl <= `TX_PACKET_STREAM;"
+A 140 138 16 TEXT "Actions" | 77848,170826 1 0 0 "fifoReadEn <= 1'b1;"
+C 139 138 0 TEXT "Conditions" | 93949,179372 1 0 0 "SCTxPortRdy == 1'b1"
+W 138 65 0 142 212 BEZIER "Transitions" | 93778,181425 88301,173716 82823,166005 77346,158296
+L 137 136 0 TEXT "State Labels" | 97634,134508 1 0 0 "READ_FIFO\n/6/"
+S 136 65 32768 ELLIPSE "States" | 97326,133352 6500 6500
+W 128 65 0 126 145 BEZIER "Transitions" | 72704,237252 77515,245311 99394,235265 108723,227500
+L 159 158 0 TEXT "State Labels" | 59589,120610 1 0 0 "TERM_BYTE\n/10/"
+S 158 65 49152 ELLIPSE "States" | 59589,119907 6500 6500
+A 157 152 4 TEXT "Actions" | 82022,67382 1 0 0 "SCTxPortWEn <= 1'b0;"
+A 156 154 16 TEXT "Actions" | 58975,105373 1 0 0 "//Last byte is not valid data, \n//but the 'TX_PACKET_STOP' flag is required \n//by the SIE state machine to detect end of data packet\nSCTxPortWEn <= 1'b1;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= `TX_PACKET_STOP;"
+C 155 154 0 TEXT "Conditions" | 61533,111844 1 0 0 "SCTxPortRdy == 1'b1"
+W 154 65 0 158 152 BEZIER "Transitions" | 59808,113432 60157,106714 62272,79249 62621,72531
+L 153 152 0 TEXT "State Labels" | 63724,65778 1 0 0 "FIN\n/9/"
+S 152 65 45056 ELLIPSE "States" | 63416,66086 6500 6500
+C 148 146 0 TEXT "Conditions" | 110699,212736 1 0 0 "fifoEmpty == 1'b0"
+W 146 65 8193 145 142 BEZIER "Transitions" | 109258,216579 105891,210391 99971,199802 96604,193614
+S 145 65 40960 ELLIPSE "States" | 112500,222212 6500 6500
+L 144 145 0 TEXT "State Labels" | 111719,222145 1 0 0 "FIFO_EMPTY\n/8/"
+I 175 0 2 Builtin OutPort | 155450,237706 "" ""
+L 174 173 0 TEXT "Labels" | 41299,213676 1 0 0 "PID[3:0]"
+I 173 0 130 Builtin InPort | 35299,213676 "" ""
+L 172 171 0 TEXT "Labels" | 39427,218968 1 0 0 "sendPacketRdy"
+I 171 0 2 Builtin OutPort | 33427,218968 "" ""
+I 170 0 2 Builtin InPort | 35414,224168 "" ""
+L 169 170 0 TEXT "Labels" | 41414,224168 1 0 0 "sendPacketWEn"
+I 168 0 2 Builtin OutPort | 99800,215222 "" ""
+L 167 168 0 TEXT "Labels" | 105800,214970 1 0 0 "fifoReadEn"
+L 166 165 0 TEXT "Labels" | 108007,220336 1 0 0 "fifoData[7:0]"
+I 165 0 130 Builtin InPort | 102007,220336 "" ""
+I 164 0 2 Builtin InPort | 101658,228164 "" ""
+L 163 164 0 TEXT "Labels" | 107658,228164 1 0 0 "fifoEmpty"
+W 162 65 0 152 127 BEZIER "Transitions" | 69206,63133 84852,58192 113349,46697 126570,43677\
+                                          139792,40658 161594,38692 165369,38074 169145,37457\
+                                          170187,37688 173773,37229
+W 160 65 8194 145 158 BEZIER "Transitions" | 106145,220849 94342,218470 70892,213593 64258,206319\
+                                             57625,199045 54697,174705 54514,164091 54331,153478\
+                                             57228,135338 58326,126280
+C 191 13 0 TEXT "Conditions" | 86196,196179 1 0 0 "rst"
+L 190 189 0 TEXT "Labels" | 204532,251890 1 0 0 "rst"
+I 189 0 2 Builtin InPort | 198532,251890 "" ""
+I 188 0 3 Builtin InPort | 198206,245948 "" ""
+L 187 188 0 TEXT "Labels" | 204206,245948 1 0 0 "clk"
+L 186 185 0 TEXT "Labels" | 162179,213226 1 0 0 "SCTxPortCntl[7:0]"
+I 185 0 130 Builtin OutPort | 156179,213226 "" ""
+L 184 183 0 TEXT "Labels" | 162035,218266 1 0 0 "SCTxPortData[7:0]"
+I 183 0 130 Builtin OutPort | 156035,218266 "" ""
+L 182 181 0 TEXT "Labels" | 164231,223036 1 0 0 "SCTxPortRdy"
+I 181 0 2 Builtin InPort | 158231,223036 "" ""
+I 180 0 2 Builtin OutPort | 155564,228002 "" ""
+L 179 180 0 TEXT "Labels" | 161564,228002 1 0 0 "SCTxPortWEn"
+L 178 177 0 TEXT "Labels" | 163583,232918 1 0 0 "SCTxPortGnt"
+I 177 0 2 Builtin InPort | 157583,232918 "" ""
+L 176 175 0 TEXT "Labels" | 161450,237706 1 0 0 "SCTxPortReq"
+S 207 65 57344 ELLIPSE "States" | 163561,124222 6500 6500
+L 206 207 0 TEXT "State Labels" | 163561,124222 1 0 0 "CLR_WEN\n/12/"
+A 192 9 2 TEXT "Actions" | 127282,199550 1 0 0 "sendPacketRdy <= 1'b1;\nfifoReadEn <= 1'b0;\nSCTxPortData <= 8'h00;\nSCTxPortCntl <= 8'h00;\nSCTxPortWEn <= 1'b0;\nSCTxPortReq <= 1'b0;"
+L 194 195 0 TEXT "Labels" | 38000,231468 1 0 0 "PIDNotPID[7:0]"
+I 195 0 128 Builtin Signal | 35000,231468 "" ""
+L 204 205 0 TEXT "State Labels" | 61573,50520 1 0 0 "SP_NOT_DATA\n/11/"
+S 205 6 53248 ELLIPSE "States" | 61573,50520 6500 6500
+W 210 65 0 207 145 BEZIER "Transitions" | 169895,125680 176804,126013 188953,127552 193864,130465\
+                                          198775,133379 204604,144369 205686,152818 206768,161268\
+                                          205269,184079 201481,192903 197694,201727 184040,214216\
+                                          173218,217462 162396,220708 133810,221642 118992,221891
+W 209 65 0 136 207 BEZIER "Transitions" | 103712,132145 117531,130730 143304,126529 157123,125114
+A 208 207 4 TEXT "Actions" | 145246,113566 1 0 0 "SCTxPortWEn <= 1'b0;"
+L 211 212 0 TEXT "State Labels" | 76973,151815 1 0 0 "CLR_REN\n/13/"
+S 212 65 61440 ELLIPSE "States" | 76973,151815 6500 6500
+A 213 212 4 TEXT "Actions" | 88033,161295 1 0 0 "fifoReadEn <= 1'b0;"
+W 214 65 0 212 136 BEZIER "Transitions" | 81800,147464 84861,145094 89728,140374 92789,138004
+END

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/slaveSendpacket.asf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/model/wb_master_model.v
===================================================================
--- common/components/usbhostslave/trunk/model/wb_master_model.v	(nonexistent)
+++ common/components/usbhostslave/trunk/model/wb_master_model.v	(revision 264)
@@ -0,0 +1,178 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  wb_master_model.v                                           ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  Based on:                                                   ////
+////      - i2c/bench/verilog/wb_master_model.v                   ////
+////        Copyright (C) 2001 Richard Herveille                  ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+
+module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
+
+  parameter dwidth = 32;
+  parameter awidth = 32;
+  
+  input                  clk, rst;
+  output [awidth   -1:0] adr;
+  input  [dwidth   -1:0] din;
+  output [dwidth   -1:0] dout;
+  output                 cyc, stb;
+  output                 we;
+  output [dwidth/8 -1:0] sel;
+  input                  ack, err, rty;
+  
+  // Internal signals
+  reg    [awidth   -1:0] adr;
+  reg    [dwidth   -1:0] dout;
+  reg                    cyc, stb;
+  reg                    we;
+  reg    [dwidth/8 -1:0] sel;
+         
+  reg    [dwidth   -1:0] q;
+  
+  // Memory Logic
+  initial
+    begin
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+      #1;
+    end
+  
+  // Wishbone write cycle
+  task wb_write;
+    input   delay;
+    integer delay;
+  
+    input [awidth -1:0] a;
+    input [dwidth -1:0] d;
+  
+    begin
+  
+      // wait initial delay
+      repeat(delay) @(posedge clk);
+  
+      // assert wishbone signal
+      #1;
+      adr  = a;
+      dout = d;
+      cyc  = 1'b1;
+      stb  = 1'b1;
+      we   = 1'b1;
+      sel  = {dwidth/8{1'b1}};
+      @(posedge clk);
+  
+      // wait for acknowledge from slave
+      while(~ack) @(posedge clk);
+  
+      // negate wishbone signals
+      #1;
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+  
+    end
+  endtask
+  
+  // Wishbone read cycle
+  task wb_read;
+    input   delay;
+    integer delay;
+  
+    input  [awidth -1:0]  a;
+    output  [dwidth -1:0] d;
+  
+    begin
+  
+      // wait initial delay
+      repeat(delay) @(posedge clk);
+  
+      // assert wishbone signals
+      #1;
+      adr  = a;
+      dout = {dwidth{1'bx}};
+      cyc  = 1'b1;
+      stb  = 1'b1;
+      we   = 1'b0;
+      sel  = {dwidth/8{1'b1}};
+      @(posedge clk);
+  
+      // wait for acknowledge from slave
+      while(~ack) @(posedge clk);
+  
+      // negate wishbone signals
+      #1;
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+      d    = din;
+  
+    end
+  endtask
+  
+  // Wishbone compare cycle (read data from location and compare with expected data)
+  task wb_cmp;
+    input   delay;
+    integer delay;
+  
+    input [awidth -1:0] a;
+    input [dwidth -1:0] d_exp;
+  
+    begin
+      wb_read (delay, a, q);
+
+      if (d_exp !== q) begin
+        $display("\n--- ERROR: At address 0x%0x, got 0x%0x, expected 0x%0x at time %t", a, q, d_exp, $time);
+        $stop;
+      end
+    end
+  endtask
+  
+endmodule
+ 
Index: common/components/usbhostslave/trunk/sim/filelistSepHostSlave.icarus
===================================================================
--- common/components/usbhostslave/trunk/sim/filelistSepHostSlave.icarus	(nonexistent)
+++ common/components/usbhostslave/trunk/sim/filelistSepHostSlave.icarus	(revision 264)
@@ -0,0 +1,56 @@
+../RTL/buffers/dpMem_dc.v
+../RTL/buffers/fifoRTL.v
+../RTL/buffers/RxFifoBI.v
+../RTL/buffers/TxFifoBI.v
+../RTL/buffers/RxFifo.v
+../RTL/buffers/TxFifo.v
+../RTL/busInterface/wishBoneBI.v
+../RTL/hostController/directControl.v
+../RTL/hostController/getPacket.v
+../RTL/hostController/hctxportarbiter.v
+../RTL/hostController/hostcontroller.v
+../RTL/hostController/rxStatusMonitor.v
+../RTL/hostController/sendPacket.v
+../RTL/hostController/sendpacketarbiter.v
+../RTL/hostController/sendpacketcheckpreamble.v
+../RTL/hostController/sofcontroller.v
+../RTL/hostController/softransmit.v
+../RTL/hostController/speedctrlMux.v
+../RTL/hostController/usbHostControl.v
+../RTL/hostController/USBHostControlBI.v
+../RTL/hostSlaveMux/hostSlaveMux.v
+../RTL/hostSlaveMux/hostSlaveMuxBI.v
+../RTL/serialInterfaceEngine/lineControlUpdate.v
+../RTL/serialInterfaceEngine/processRxBit.v
+../RTL/serialInterfaceEngine/processRxByte.v
+../RTL/serialInterfaceEngine/processTxByte.v
+../RTL/serialInterfaceEngine/readUSBWireData.v
+../RTL/serialInterfaceEngine/siereceiver.v
+../RTL/serialInterfaceEngine/SIETransmitter.v
+../RTL/serialInterfaceEngine/updateCRC5.v
+../RTL/serialInterfaceEngine/updateCRC16.v
+../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+../RTL/serialInterfaceEngine/usbTxWireArbiter.v
+../RTL/serialInterfaceEngine/writeUSBWireData.v
+../RTL/slaveController/endpMux.v
+../RTL/slaveController/fifoMux.v
+../RTL/slaveController/sctxportarbiter.v
+../RTL/slaveController/slavecontroller.v
+../RTL/slaveController/slaveDirectcontrol.v
+../RTL/slaveController/slaveGetpacket.v
+../RTL/slaveController/slaveRxStatusMonitor.v
+../RTL/slaveController/slaveSendpacket.v
+../RTL/slaveController/usbSlaveControl.v
+../RTL/slaveController/USBSlaveControlBI.v
+../RTL/wrapper/usbHost.v
+../RTL/wrapper/usbSlave.v
+../RTL/wrapper/usbHostSlave.v
+../model/wb_master_model.v
+../bench/sepHostSlaveTestHarness.v
+../bench/testCase0.v
+
++incdir+../RTL
++incdir+../RTL/include
++incdir+../bench
++define+SIM_COMPILE
+
Index: common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbHostSlaveAvalonWrap.qpf
===================================================================
--- common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbHostSlaveAvalonWrap.qpf	(nonexistent)
+++ common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbHostSlaveAvalonWrap.qpf	(revision 264)
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2006 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "6.0"
+DATE = "19:38:48  October 06, 2006"
+
+
+# Revisions
+
+PROJECT_REVISION = "usbHostSlaveAvalonWrap"
Index: common/components/usbhostslave/trunk/RTL/wrapper/usbSlave.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/wrapper/usbSlave.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/wrapper/usbSlave.v	(revision 264)
@@ -0,0 +1,481 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlave.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbSlave(
+  clk_i,
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  usbClk,
+  slaveVBusDetIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+  USBWireDataIn,
+  USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+  USBWireCtrlOut,
+  USBFullSpeed,
+  USBDPlusPullup,
+  USBDMinusPullup,
+  vBusDetect
+   );
+  parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+  parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+  parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+  parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk_i;               //Wishbone bus clock. Maximum 5*usbClk=240MHz
+input rst_i;               //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
+input [7:0] address_i;     //Wishbone bus address in
+input [7:0] data_i;        //Wishbone bus data in
+output [7:0] data_o;       //Wishbone bus data out
+input we_i;                //Wishbone bus write enable in
+input strobe_i;            //Wishbone bus strobe in
+output ack_o;              //Wishbone bus acknowledge out
+input usbClk;              //usb clock. 48Mhz +/-0.25%
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+output slaveVBusDetIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+output USBDPlusPullup;
+output USBDMinusPullup;
+input vBusDetect;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire we_i; 
+wire strobe_i;
+wire ack_o;
+wire usbClk;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire slaveVBusDetIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+wire USBDPlusPullup;
+wire USBDMinusPullup;
+wire vBusDetect;
+
+//internal wiring
+wire slaveControlSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostSlaveMux;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire connectSlaveToHost;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+wire noActivityTimeOutEnableToSIE;
+wire noActivityTimeOutEnableFromHost;
+wire noActivityTimeOutEnableFromSlave;
+
+// This is not a bug.
+// USBFullSpeed controls the PHY edge speed.
+// The only time that the PHY needs to operate with low speed edge rate is
+// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
+// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
+// but according to spec edge speed must be full rate edge speed. 
+assign USBFullSpeed = fullSpeedPolarityToSIE;
+//assign USBFullSpeed = fullSpeedBitRateToSIE;  
+assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
+assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
+
+usbSlaveControl u_usbSlaveControl(
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut), 
+  .SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
+  .RxFifoData(slaveRxFifoData),
+  .connectSlaveToHost(connectSlaveToHost),
+  .fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+  .SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+  .SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+  .vBusDetect(vBusDetect),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(we_i),
+  .busStrobe_i(strobe_i),
+  .SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .vBusDetIntOut(slaveVBusDetIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(we_i), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk_i), 
+  .rst(rstSyncToBusClk),
+  .hostControlSel(), 
+  .hostRxFifoSel(), 
+  .hostTxFifoSel(),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(8'h00),
+  .dataFromHostRxFifo(8'h00),
+  .dataFromHostTxFifo(8'h00),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+   );
+
+
+
+assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave;
+assign SIEPortDataInToSIE = SIEPortDataInFromSlave;
+assign SIEPortWEnToSIE = SIEPortWEnFromSlave;
+assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave;
+assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave;
+assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave;
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux),
+  .address(address_i[0]),
+  .writeEn(we_i),
+  .strobe_i(strobe_i),
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .hostMode(), 
+  .rstFromWire(rst_i),
+  .rstSyncToBusClkOut(rstSyncToBusClk),
+  .rstSyncToUsbClkOut(rstSyncToUsbClk)
+);
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .connectState(connectState),
+  .resumeDetected(resumeDetected),
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataFromSIE), 
+  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+  .SIEPortDataIn(SIEPortDataInToSIE), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEnToSIE), 
+  .fullSpeedPolarity(fullSpeedPolarityToSIE),
+  .fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut),
+  .noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
+);
+
+
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i),
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/bench/sepHostSlaveTestHarness.v
===================================================================
--- common/components/usbhostslave/trunk/bench/sepHostSlaveTestHarness.v	(nonexistent)
+++ common/components/usbhostslave/trunk/bench/sepHostSlaveTestHarness.v	(revision 264)
@@ -0,0 +1,200 @@
+`include "timescale.v"
+
+module testHarness(	);
+
+
+// -----------------------------------
+// Local Wires
+// -----------------------------------
+reg clk;
+reg rst;
+reg usbClk;
+wire [8:0] adr;
+wire [7:0] masterDout;
+wire [7:0] masterDin;
+wire [7:0] usbSlaveDout;
+wire [7:0] usbHostDout;
+wire stb;
+wire we;
+wire ack;
+wire host_stb;
+wire slave_stb;
+wire DPlusPullup;
+wire DPlusPullDown;
+wire DMinusPullup;
+wire DMinusPulDown;
+reg USBWireVP;
+reg USBWireVM;
+wire [1:0] hostUSBWireDataIn;
+wire [1:0] hostUSBWireDataOut;
+wire [1:0] slaveUSBWireDataIn;
+wire [1:0] slaveUSBWireDataOut;
+wire hostUSBWireCtrlOut;
+wire slaveUSBWireCtrlOut;
+
+initial begin
+$dumpfile("wave.vcd");
+$dumpvars(0, testHarness); 
+end
+
+pullup(DPlusPullup);
+pulldown(DPlusPullDown);
+pullup(DMinusPullup);
+pulldown(DMinusPullDown);
+
+assign hostUSBWireDataIn = {USBWireVP, USBWireVM};
+assign slaveUSBWireDataIn = {USBWireVP, USBWireVM};
+//always @(hostUSBWireCtrlOut or slaveUSBWireCtrlOut or hostUSBWireDataOut or slaveUSBWireDataOut or
+//  DPlusPullup or DPlusPullDown or DMinusPullup or DMinusPullDown) begin
+always @(*) begin
+  if (hostUSBWireCtrlOut == 1'b1 && slaveUSBWireCtrlOut == 1'b0)
+    {USBWireVP, USBWireVM} <= hostUSBWireDataOut;
+  else if (hostUSBWireCtrlOut == 1'b0 && slaveUSBWireCtrlOut == 1'b1)
+    {USBWireVP, USBWireVM} <= slaveUSBWireDataOut;
+  else if (hostUSBWireCtrlOut == 1'b1 && slaveUSBWireCtrlOut == 1'b1)
+    {USBWireVP, USBWireVM} <= 2'bxx;
+  else if (hostUSBWireCtrlOut == 1'b0 && slaveUSBWireCtrlOut == 1'b0) begin
+    if (USBDPlusPullup == 1'b1)
+      USBWireVP <= DPlusPullup;
+    else
+      USBWireVP <= DPlusPullDown;
+    if (USBDMinusPullup == 1'b1)
+      USBWireVM <= DMinusPullup;
+    else
+      USBWireVM <= DMinusPullDown;
+  end
+end
+
+assign host_stb = ~adr[8] & stb;
+assign slave_stb = adr[8] & stb;
+assign masterDin = host_stb == 1'b1 ? usbHostDout : usbSlaveDout;
+
+//Parameters declaration: 
+defparam u_usbHost.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam u_usbHost.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+usbHost u_usbHost (
+  .clk_i(clk),
+  .rst_i(rst),
+  .address_i(adr[7:0]),
+  .data_i(masterDout),
+  .data_o(usbHostDout),
+  .we_i(we),
+  .strobe_i(host_stb),
+  .ack_o(ack),
+  .usbClk(usbClk),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .USBWireDataIn(hostUSBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(hostUSBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(hostUSBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed)
+
+
+);
+
+
+
+//Parameters declaration: 
+defparam u_usbSlave.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam u_usbSlave.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam u_usbSlave.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam u_usbSlave.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam u_usbSlave.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam u_usbSlave.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam u_usbSlave.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam u_usbSlave.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbSlave u_usbSlave (
+  .clk_i(clk),
+  .rst_i(rst),
+  .address_i(adr[7:0]),
+  .data_i(masterDout),
+  .data_o(usbSlaveDout),
+  .we_i(we),
+  .strobe_i(slave_stb),
+  .ack_o(ack),
+  .usbClk(usbClk),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .slaveVBusDetIntOut(slaveVBusDetIntOut),
+  .USBWireDataIn(slaveUSBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(slaveUSBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(slaveUSBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed),
+  .USBDPlusPullup(USBDPlusPullup),
+  .USBDMinusPullup(USBDMinusPullup),
+  .vBusDetect(1'b1)
+);
+
+
+
+
+wb_master_model #(.dwidth(8), .awidth(9)) u_wb_master_model (
+  .clk(clk), 
+  .rst(rst), 
+  .adr(adr), 
+  .din(masterDin), 
+  .dout(masterDout), 
+  .cyc(), 
+  .stb(stb), 
+  .we(we), 
+  .sel(), 
+  .ack(ack), 
+  .err(1'b0), 
+  .rty(1'b0)
+);
+
+
+//--------------- reset ---------------
+initial begin
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  rst <= 1'b1;
+  @(posedge clk);
+  rst <= 1'b0;
+  @(posedge clk);
+end
+ 
+// ******************************  Clock section  ******************************
+`define CLK_50MHZ_HALF_PERIOD 10
+`define CLK_25MHZ_HALF_PERIOD 20
+
+always begin
+  #`CLK_25MHZ_HALF_PERIOD clk <= 1'b0;
+  #`CLK_25MHZ_HALF_PERIOD clk <= 1'b1;
+end
+
+always begin
+  #`CLK_50MHZ_HALF_PERIOD usbClk <= 1'b0;
+  #`CLK_50MHZ_HALF_PERIOD usbClk <= 1'b1;
+end
+
+
+
+
+endmodule
+
Index: common/components/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v	(revision 264)
@@ -0,0 +1,521 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbSlaveControl(
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  //getPacket
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut, RxFifoData, SIERxTimeOutEn,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  connectSlaveToHost,
+  //SCTxPortArbiter
+  SCTxPortEn, SCTxPortRdy,
+  SCTxPortData, SCTxPortCtrl,
+  //rxStatusMonitor
+  vBusDetect,
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFRxedIntOut, 
+  resetEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  vBusDetIntOut,
+  NAKSentIntOut,
+  slaveControlSelect,
+  //fifoMux
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut; 
+output SIERxTimeOutEn;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+output connectSlaveToHost;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input vBusDetect;
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [4:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut; 
+output resetEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+output vBusDetIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire SIERxTimeOutEn;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire connectSlaveToHost;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut; 
+wire resetEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire vBusDetIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed; 
+wire CRCError; 
+wire RXOverflow; 
+wire RXTimeOut; 
+wire bitStuffError; 
+wire dataSequence; 
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [4:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire endPointReadyFromSlaveCtrlrToGetPkt;
+
+USBSlaveControlBI u_USBSlaveControlBI
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .SOFRxedIntOut(SOFRxedIntOut), 
+  .resetEventIntOut(resetEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .vBusDetIntOut(vBusDetIntOut),
+  .NAKSentIntOut(NAKSentIntOut),
+  .endP0TransTypeReg(endP0TransTypeReg), 
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg), 
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg), 
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg), 
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .EP0StatusReg(endP0StatusReg),
+  .EP1StatusReg(endP1StatusReg),
+  .EP2StatusReg(endP2StatusReg),
+  .EP3StatusReg(endP3StatusReg),
+  .SCAddrReg(USBTgtAddress), 
+  .frameNum(frameNum),
+  .connectStateIn(connectStateOut),
+  .vBusDetectIn(vBusDetect),
+  .SOFRxedIn(SOFRxed), 
+  .resetEventIn(resetEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .NAKSentIn(NAKSent),
+  .slaveControlSelect(slaveControlSelect),
+  .clrEP0Ready(clrEP0Rdy), 
+  .clrEP1Ready(clrEP1Rdy), 
+  .clrEP2Ready(clrEP2Rdy), 
+  .clrEP3Ready(clrEP3Rdy),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .connectSlaveToHost(connectSlaveToHost),
+  .SCGlobalEn(SCGlobalEn)
+  );
+
+slavecontroller u_slavecontroller
+  (.CRCError(CRCError), 
+  .NAKSent(NAKSent), 
+  .RxByte(RxData), 
+  .RxDataWEn(RxDataValid), 
+  .RxOverflow(RXOverflow), 
+  .RxStatus(RxByteStatus), 
+  .RxTimeOut(RXTimeOut), 
+  .SCGlobalEn(SCGlobalEn), 
+  .SOFRxed(SOFRxed), 
+  .USBEndPControlReg(endPControlReg), 
+  .USBEndPNakTransTypeReg(transTypeNAK), 
+  .USBEndPTransTypeReg(transType), 
+  .USBEndP(currEndP), 
+  .USBTgtAddress(USBTgtAddress),
+  .bitStuffError(bitStuffError), 
+  .clk(usbClk), 
+  .clrEPRdy(clrEPRdy), 
+  .endPMuxErrorsWEn(endPMuxErrorsWEn), 
+  .frameNum(frameNum), 
+  .getPacketREn(getPacketREn), 
+  .getPacketRdy(getPacketRdy), 
+  .rst(rstSyncToUsbClk), 
+  .sendPacketPID(slaveControllerPIDOut), 
+  .sendPacketRdy(slaveControllerReadyIn), 
+  .sendPacketWEn(slaveControllerWEnOut), 
+  .stallSent(stallSent), 
+  .transDone(transDone),
+  .endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
+    );
+
+
+endpMux u_endpMux (
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .currEndP(currEndP),
+  .NAKSent(NAKSent),
+  .stallSent(stallSent),
+  .CRCError(CRCError),
+  .bitStuffError(bitStuffError),
+  .RxOverflow(RXOverflow),
+  .RxTimeOut(RXTimeOut),
+  .dataSequence(dataSequence),
+  .ACKRxed(ACKRxed),
+  .transType(transType),
+  .transTypeNAK(transTypeNAK),
+  .endPControlReg(endPControlReg),
+  .clrEPRdy(clrEPRdy),
+  .endPMuxErrorsWEn(endPMuxErrorsWEn),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .endP0StatusReg(endP0StatusReg),
+  .endP1StatusReg(endP1StatusReg),
+  .endP2StatusReg(endP2StatusReg),
+  .endP3StatusReg(endP3StatusReg),
+  .endP0TransTypeReg(endP0TransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg),
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .clrEP0Rdy(clrEP0Rdy),
+  .clrEP1Rdy(clrEP1Rdy),
+  .clrEP2Rdy(clrEP2Rdy),
+  .clrEP3Rdy(clrEP3Rdy)
+    );
+
+slaveSendPacket u_slaveSendPacket
+  (.PID(slaveControllerPIDOut), 
+  .SCTxPortCntl(sendPacketCntl),
+  .SCTxPortData(sendPacketData),
+  .SCTxPortGnt(sendPacketGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(sendPacketReq),
+  .SCTxPortWEn(sendPacketWEn),
+  .clk(usbClk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .rst(rstSyncToUsbClk),
+  .sendPacketRdy(slaveControllerReadyIn),
+  .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+  (.SCTxPortCntl(directCntlCntl),
+  .SCTxPortData(directCntlData),
+  .SCTxPortGnt(directCntlGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(directCntlReq),
+  .SCTxPortWEn(directCntlWEn),
+  .clk(usbClk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rstSyncToUsbClk) ); 
+
+SCTxPortArbiter u_SCTxPortArbiter
+  (.SCTxPortCntl(SCTxPortCtrl),
+  .SCTxPortData(SCTxPortData),
+  .SCTxPortRdyIn(SCTxPortRdy),
+  .SCTxPortRdyOut(SCTxPortArbRdyOut),
+  .SCTxPortWEnable(SCTxPortEn),
+  .clk(usbClk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+
+slaveGetPacket u_slaveGetPacket
+  (.ACKRxed(ACKRxed), 
+  .CRCError(CRCError), 
+  .RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .SIERxTimeOutEn(SIERxTimeOutEn),
+  .clk(usbClk),
+  .RXOverflow(RXOverflow), 
+  .RXTimeOut(RXTimeOut), 
+  .bitStuffError(bitStuffError), 
+  .dataSequence(dataSequence), 
+  .getPacketEn(getPacketREn),
+  .rst(rstSyncToUsbClk),
+  .endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
+  ); 
+
+slaveRxStatusMonitor  u_slaveRxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .resetEventOut(resetEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk)  );    
+  
+fifoMux u_fifoMux (
+  .currEndP(currEndP),
+  //TxFifo
+  .TxFifoREn(TxFifoRE),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoData(TxFifoData),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEmpty(TxFifoEmpty),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  //RxFifo
+  .RxFifoWEn(RxFifoWE),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoFull(RxFifoFull),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+    );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/trunk/RTL/slaveController/usbSlaveControl.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v	(revision 264)
@@ -0,0 +1,583 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbHostSlave.v                                               ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbHostSlave(
+  clk_i,
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  usbClk,
+  hostSOFSentIntOut, 
+  hostConnEventIntOut, 
+  hostResumeIntOut, 
+  hostTransDoneIntOut,
+  slaveVBusDetIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+  USBWireDataIn,
+  USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+  USBWireCtrlOut,
+  USBFullSpeed,
+  USBDPlusPullup,
+  USBDMinusPullup,
+  vBusDetect
+   );
+  parameter HOST_FIFO_DEPTH = 64; //HOST_FIFO_DEPTH = HOST_ADDR_WIDTH^2
+  parameter HOST_FIFO_ADDR_WIDTH = 6;   
+  parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+  parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+  parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+  parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk_i;               //Wishbone bus clock. Min = usbClk/2 = 24MHz. Max 5*usbClk=240MHz
+input rst_i;               //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
+input [7:0] address_i;     //Wishbone bus address in
+input [7:0] data_i;        //Wishbone bus data in
+output [7:0] data_o;       //Wishbone bus data out
+input we_i;                //Wishbone bus write enable in
+input strobe_i;            //Wishbone bus strobe in
+output ack_o;              //Wishbone bus acknowledge out
+input usbClk;              //usb clock. 48Mhz +/-0.25%
+output hostSOFSentIntOut; 
+output hostConnEventIntOut; 
+output hostResumeIntOut; 
+output hostTransDoneIntOut;
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+output slaveVBusDetIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+output USBDPlusPullup;
+output USBDMinusPullup;
+input vBusDetect;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire we_i; 
+wire strobe_i;
+wire ack_o;
+wire usbClk;
+wire hostSOFSentIntOut; 
+wire hostConnEventIntOut; 
+wire hostResumeIntOut; 
+wire hostTransDoneIntOut;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire slaveVBusDetIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+wire USBDPlusPullup;
+wire USBDMinusPullup;
+wire vBusDetect;
+
+//internal wiring
+wire hostControlSel;
+wire slaveControlSel;
+wire hostRxFifoSel; 
+wire hostTxFifoSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromHostSlaveMux;
+wire hostTxFifoRE; 
+wire [7:0] hostTxFifoData; 
+wire hostTxFifoEmpty;
+wire hostRxFifoWE; 
+wire [7:0] hostRxFifoData; 
+wire hostRxFifoFull;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromHost; 
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromHost;
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromHost; 
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromHost; 
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromHost;
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+wire noActivityTimeOutEnableToSIE;
+wire noActivityTimeOutEnableFromHost;
+wire noActivityTimeOutEnableFromSlave;
+wire connectSlaveToHost;
+
+// This is not a bug.
+// USBFullSpeed controls the PHY edge speed.
+// The only time that the PHY needs to operate with low speed edge rate is
+// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
+// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
+// but according to spec edge speed must be full rate edge speed. 
+assign USBFullSpeed = fullSpeedPolarityToSIE;
+//assign USBFullSpeed = fullSpeedBitRateToSIE;  
+assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
+assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
+
+usbHostControl u_usbHostControl(
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .TxFifoRE(hostTxFifoRE), 
+  .TxFifoData(hostTxFifoData), 
+  .TxFifoEmpty(hostTxFifoEmpty),
+  .RxFifoWE(hostRxFifoWE), 
+  .RxFifoData(hostRxFifoData), 
+  .RxFifoFull(hostRxFifoFull),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut),
+  .SIERxTimeOutEn(noActivityTimeOutEnableFromHost),
+  .fullSpeedRate(fullSpeedBitRateFromHost), 
+  .fullSpeedPol(fullSpeedPolarityFromHost),
+  .HCTxPortEn(SIEPortWEnFromHost), 
+  .HCTxPortRdy(SIEPortTxRdy),
+  .HCTxPortData(SIEPortDataInFromHost), 
+  .HCTxPortCtrl(SIEPortCtrlInFromHost),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[3:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostControl), 
+  .busWriteEn(we_i),
+  .busStrobe_i(strobe_i),
+  .SOFSentIntOut(hostSOFSentIntOut), 
+  .connEventIntOut(hostConnEventIntOut), 
+  .resumeIntOut(hostResumeIntOut), 
+  .transDoneIntOut(hostTransDoneIntOut),
+  .hostControlSelect(hostControlSel) );
+  
+
+usbSlaveControl u_usbSlaveControl(
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut), 
+  .SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
+  .RxFifoData(slaveRxFifoData),
+  .connectSlaveToHost(connectSlaveToHost),
+  .fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+  .SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+  .SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+  .vBusDetect(vBusDetect),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(we_i),
+  .busStrobe_i(strobe_i),
+  .SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .vBusDetIntOut(slaveVBusDetIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(we_i), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk_i), 
+  .rst(rstSyncToBusClk),
+  .hostControlSel(hostControlSel), 
+  .hostRxFifoSel(hostRxFifoSel), 
+  .hostTxFifoSel(hostTxFifoSel),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(dataFromHostControl),
+  .dataFromHostRxFifo(dataFromHostRxFifo),
+  .dataFromHostTxFifo(dataFromHostTxFifo),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+   );
+
+hostSlaveMux u_hostSlaveMux(
+  .SIEPortCtrlInToSIE(SIEPortCtrlInToSIE),
+  .SIEPortCtrlInFromHost(SIEPortCtrlInFromHost),
+  .SIEPortCtrlInFromSlave(SIEPortCtrlInFromSlave),
+  .SIEPortDataInToSIE(SIEPortDataInToSIE), 
+  .SIEPortDataInFromHost(SIEPortDataInFromHost), 
+  .SIEPortDataInFromSlave(SIEPortDataInFromSlave), 
+  .SIEPortWEnToSIE(SIEPortWEnToSIE), 
+  .SIEPortWEnFromHost(SIEPortWEnFromHost), 
+  .SIEPortWEnFromSlave(SIEPortWEnFromSlave), 
+  .fullSpeedPolarityToSIE(fullSpeedPolarityToSIE),
+  .fullSpeedPolarityFromHost(fullSpeedPolarityFromHost),
+  .fullSpeedPolarityFromSlave(fullSpeedPolarityFromSlave),
+  .fullSpeedBitRateToSIE(fullSpeedBitRateToSIE),
+  .fullSpeedBitRateFromHost(fullSpeedBitRateFromHost),
+  .fullSpeedBitRateFromSlave(fullSpeedBitRateFromSlave),
+  .noActivityTimeOutEnableToSIE(noActivityTimeOutEnableToSIE),
+  .noActivityTimeOutEnableFromHost(noActivityTimeOutEnableFromHost),
+  .noActivityTimeOutEnableFromSlave(noActivityTimeOutEnableFromSlave),
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux),
+  .address(address_i[0]),
+  .writeEn(we_i),
+  .strobe_i(strobe_i),
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .rstFromWire(rst_i),
+  .rstSyncToBusClkOut(rstSyncToBusClk),
+  .rstSyncToUsbClkOut(rstSyncToUsbClk)
+);
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .connectState(connectState),
+  .resumeDetected(resumeDetected),
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataFromSIE), 
+  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+  .SIEPortDataIn(SIEPortDataInToSIE), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEnToSIE), 
+  .fullSpeedPolarity(fullSpeedPolarityToSIE),
+  .fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut),
+  .noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
+);
+
+//---Host fifos
+TxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostTxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(hostTxFifoRE), 
+  .fifoEmpty(hostTxFifoEmpty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostTxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostTxFifo),
+  .fifoDataOut(hostTxFifoData) );
+
+
+RxFifo #(HOST_FIFO_DEPTH, HOST_FIFO_ADDR_WIDTH) HostRxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i),
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(hostRxFifoWE), 
+  .fifoFull(hostRxFifoFull),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(hostRxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromHostRxFifo),
+  .fifoDataIn(hostRxFifoData)  );
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i),
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+endmodule
+
+  
+  
+
+
+
+

Property changes on: common/components/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/components/usbhostslave/trunk/RTL/wrapper/usbSlaveCyc2Wrap.v
===================================================================
--- common/components/usbhostslave/trunk/RTL/wrapper/usbSlaveCyc2Wrap.v	(nonexistent)
+++ common/components/usbhostslave/trunk/RTL/wrapper/usbSlaveCyc2Wrap.v	(revision 264)
@@ -0,0 +1,168 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveCyc2Wrap.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module wrapper. 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+
+module usbSlaveCyc2Wrap(
+  clk_i, 
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  irq, 
+  usbClk,
+  USBWireVP,
+  USBWireVM,
+  USBWireOE_n,
+  USBFullSpeed,
+  USBDPlusPullup,
+  USBDMinusPullup,
+  vBusDetect
+   );
+
+input clk_i;
+input rst_i;
+input [7:0] address_i; 
+input [7:0] data_i; 
+output [7:0] data_o; 
+input we_i; 
+input strobe_i;
+output ack_o;
+output irq; 
+input usbClk;
+inout USBWireVP /* synthesis useioff=1 */;
+inout USBWireVM /* synthesis useioff=1 */;
+output USBWireOE_n /* synthesis useioff=1 */;
+output USBFullSpeed /* synthesis useioff=1 */;
+output USBDPlusPullup;
+output USBDMinusPullup;
+input vBusDetect;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire irq;
+wire usbClk;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBFullSpeed;
+
+//internal wiring 
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire slaveVBusDetIntOut;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+assign irq = slaveSOFRxedIntOut | slaveResetEventIntOut |
+             slaveResumeIntOut | slaveTransDoneIntOut |
+             slaveNAKSentIntOut | slaveVBusDetIntOut;
+
+assign USBWireDataIn = {USBWireVP, USBWireVM};
+assign {USBWireVP, USBWireVM} = (USBWireCtrlOut == 1'b1) ? USBWireDataOut : 2'bzz;
+assign USBWireOE_n = ~USBWireCtrlOut;
+
+//Parameters declaration: 
+defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
+parameter EP0_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+parameter EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
+parameter EP1_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+parameter EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
+parameter EP2_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+parameter EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
+parameter EP3_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+parameter EP3_FIFO_ADDR_WIDTH = 6;
+usbSlave usbSlaveInst (
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .address_i(address_i),
+  .data_i(data_i),
+  .data_o(data_o),
+  .we_i(we_i),
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .usbClk(usbClk),
+  .slaveSOFRxedIntOut(slaveSOFRxedIntOut),
+  .slaveResetEventIntOut(slaveResetEventIntOut),
+  .slaveResumeIntOut(slaveResumeIntOut),
+  .slaveTransDoneIntOut(slaveTransDoneIntOut),
+  .slaveNAKSentIntOut(slaveNAKSentIntOut),
+  .slaveVBusDetIntOut(slaveVBusDetIntOut),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed),
+  .USBDPlusPullup(USBDPlusPullup),
+  .USBDMinusPullup(USBDMinusPullup),
+  .vBusDetect(vBusDetect)
+);
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/bench/testCase0.v
===================================================================
--- common/components/usbhostslave/trunk/bench/testCase0.v	(nonexistent)
+++ common/components/usbhostslave/trunk/bench/testCase0.v	(revision 264)
@@ -0,0 +1,252 @@
+// ---------------------------------- testcase0.v ----------------------------
+`include "timescale.v"
+`include "usbHostSlave_h.v"
+`include "usbHostControl_h.v"
+`include "usbHostSlaveTB_defines.v"
+
+module testCase0();
+
+reg ack;
+reg [7:0] data;
+reg [15:0] dataWord;
+reg [7:0] dataRead;
+reg [7:0] dataWrite;
+reg [7:0] USBAddress;
+reg [7:0] USBEndPoint;
+reg [7:0] transType;
+integer dataSize;
+integer i;
+integer j;
+
+initial
+begin
+  $write("\n\n");
+  #1000;
+
+  testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
+  $display("Host Version number = 0x%0x\n", dataRead);
+  testHarness.u_wb_master_model.wb_read(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
+  $display("Slave Version number = 0x%0x\n", dataRead);
+
+  $write("Testing host register read/write  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  $write("--- PASSED\n");
+  $write("Testing slave register read/write  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
+  $write("--- PASSED\n");
+
+  $write("Testing register reset  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
+  #1000;
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h00);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h00);
+  $write("--- PASSED\n");
+  #1000;
+
+  $write("Configure host and slave mode.  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h1);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h0);
+
+  $write("Connect full speed  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
+  #20000;
+  //expecting connection event interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
+  //expecting full speed connect
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 6'h02);
+  //expecting change in reset state event, and change in vbus state event
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h24);
+  //expecting full speed connect and vbus present
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
+  $write("--- PASSED\n");
+
+  $write("Cancel interrupts  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h24);
+  //expecting all interrupts cancelled
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
+  //expecting all interrupts cancelled
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
+  $write("--- PASSED\n");
+  #1000;
+
+  $write("Disconnect  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h30);
+  #10000;
+  //expecting connection event interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
+  //expecting disconnect state
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h00);
+  //expecting change in reset state event
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
+  //expecting vbus present, and disconnect state
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h04);
+  //cancel interrupts
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
+  $write("--- PASSED\n");
+
+
+  $write("Connect full speed  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
+  #20000;
+  //expecting connection event interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
+  //expecting full speed connect
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
+  //expecting change in reset state event
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
+  //expecting full speed connect and vbus present
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
+  //cancel interrupts
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
+  $write("--- PASSED\n");
+  #1000;
+
+
+  $write("Host forcing reset  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h1c);
+  #20000;
+  //expecting change in reset state event
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
+  //expecting vbus present, and disconnect state
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h04);
+  //cancel interrupt
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
+  $write("--- PASSED\n");
+
+  $write("Connect full speed  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h70);
+  #20000;
+  //expecting no host interrupts
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
+  //expecting full speed connect
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
+  //expecting change in reset state event
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
+  //expecting full speed connect and vbus present
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_LINE_STATUS_REG , 8'h06);
+  //cancel interrupts
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h04);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h00);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h00);
+  $write("--- PASSED\n");
+  #1000;
+
+  $write("Trans test: Device address = 0x00, 2 byte SETUP transaction to Endpoint 0. ");
+  USBAddress = 8'h00;
+  USBEndPoint = 8'h00;
+  transType = `SETUP_TRANS;
+  dataSize = 2;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP0_CTRL_REG , 8'h03);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  data = 8'h00;
+  for (i=0; i<dataSize; i=i+1) begin
+    testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
+    data = data + 1'b1;
+  end
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #20000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
+  //endpoint enabled, and endpoint ready cleared
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP0_CTRL_REG , 8'h01);
+  $write("Checking receive data  ");
+  data = 8'h00;
+  for (i=0; i<dataSize; i=i+1) begin
+    testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP0_RX_FIFO_BASE + `FIFO_DATA_REG , data);
+    data = data + 1'b1;
+  end
+  $write("--- PASSED\n");
+
+  $write("Trans test: Device address = 0x5a, 20 byte OUT DATA0 transaction to Endpoint 1. ");
+  USBAddress = 8'h5a;
+  USBEndPoint = 8'h01;
+  transType = `OUTDATA0_TRANS;
+  dataSize = 20;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP1_CTRL_REG , 8'h03);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  data = 8'h00;
+  for (i=0; i<dataSize; i=i+1) begin
+    testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , data);
+    data = data + 1'b1;
+  end
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #20000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
+  //endpoint enabled, and endpoint ready cleared
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP1_CTRL_REG , 8'h01);
+  $write("Checking receive data  ");
+  data = 8'h00;
+  for (i=0; i<dataSize; i=i+1) begin
+    testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `EP1_RX_FIFO_BASE + `FIFO_DATA_REG , data);
+    data = data + 1'b1;
+  end
+  $write("--- PASSED\n");
+
+  $write("Trans test: Device address = 0x01, 2 byte IN transaction to Endpoint 2. ");
+  USBAddress = 8'h01;
+  USBEndPoint = 8'h02;
+  transType = `IN_TRANS;
+  dataSize = 2;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_CONTROL_REG , 8'h71);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_ADDRESS , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP2_CTRL_REG , 8'h03);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  data = 8'h00;
+  for (i=0; i<dataSize; i=i+1) begin
+    testHarness.u_wb_master_model.wb_write(1, `SIM_SLAVE_BASE_ADDR + `EP2_TX_FIFO_BASE + `FIFO_DATA_REG , data);
+    data = data + 1'b1;
+  end
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #20000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`SC_INTERRUPT_STATUS_REG , 8'h01);
+  //endpoint enabled, and endpoint ready cleared
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_SLAVE_BASE_ADDR + `SCREG_BASE+`EP2_CTRL_REG , 8'h01);
+  $write("Checking receive data  ");
+  data = 8'h00;
+  for (i=0; i<dataSize; i=i+1) begin
+    testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , data);
+    data = data + 1'b1;
+  end
+  $write("--- PASSED\n");
+
+  $write("Finished all tests\n");
+  $stop;	
+
+end
+
+endmodule
+
Index: common/components/usbhostslave/trunk/doc/src/USBHostSlave_IPCore_Specification.sxw
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/trunk/doc/src/USBHostSlave_IPCore_Specification.sxw
___________________________________________________________________
Added: svn:executable
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+*
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Index: common/components/usbhostslave/trunk/sim/build_icarus_sepHostSlave.bat
===================================================================
--- common/components/usbhostslave/trunk/sim/build_icarus_sepHostSlave.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/sim/build_icarus_sepHostSlave.bat	(revision 264)
@@ -0,0 +1,4 @@
+iverilog  -o testHarness -cfilelistSepHostSlave.icarus
+
+pause
+
Index: common/components/usbhostslave/trunk/sim/run_icarus.bat
===================================================================
--- common/components/usbhostslave/trunk/sim/run_icarus.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/sim/run_icarus.bat	(revision 264)
@@ -0,0 +1,2 @@
+vvp testHarness
+
Index: common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbhostslaveavalonwrap/cb_generator.pl
===================================================================
--- common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbhostslaveavalonwrap/cb_generator.pl	(nonexistent)
+++ common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbhostslaveavalonwrap/cb_generator.pl	(revision 264)
@@ -0,0 +1,1159 @@
+# | file: cb_generator.pl
+# |
+# | This SOPC Builder Generator program is provided by
+# | the Component Builder application. It is copied
+# | straight across and is data-driven from its command
+# | line arguments and the PTF files referenced.
+# |
+# | Its purpose is to construct an HDL "wrapper" for
+# | a particular instance of a particular SOPC Builder
+# | peripheral. This wrapper resolves the instance
+# | name and any HDL parameterization.
+# |
+# +-------------------------------------------
+
+
+
+# +-------------------------------------------
+# |
+
+use strict;
+use format_conversion_utils;
+use ptf_parse;
+use wiz_utils;
+use europa_all;
+use run_system_command_utils;
+
+# |
+# +-------------------------------------------
+
+
+
+# +-------------------------------------------
+# |
+# | first pass: include all of generator_libarary.pm RIGHT HERE.
+# | dvb04.08.02
+# | then prune down to actual functionality.
+# |
+# | TODO: Rewrite this whole file into something readable
+# | this is much more confusing than I'm comfortable with. dvb04.
+# | (though it does seem to work.)
+# |
+
+my $DEBUG_DEFAULT_GEN = 1;
+
+#This is the global hash of arguments passed in by the generator program
+
+my $generator_hr = {
+		     wrapper_args => {
+				      make_wrapper => 0,
+				      top_module_name => "",
+				      simulate_hdl => 1,
+				      ports => "",
+				     },
+		     class_ptf_hr => "",
+		     module_ptf_hr => "",
+		     system_ptf_hr => "",
+		     language => "",
+		     external_args => "",
+		     external_args_hr => "",
+		     project_path_widget => "__PROJECT_DIRECTORY__",
+		     generator_mode => "silent",
+		    };
+
+
+sub generator_print_verbose
+{
+  my ($info) = (@_);
+
+  if($generator_hr->{generator_mode} eq "verbose"){
+    print("cb_generator.pl: ".$info);
+  }
+}
+
+sub generator_enable_mode
+{
+  my ($mode) = (@_);
+  $generator_hr->{generator_mode} = $mode;
+}
+
+sub generator_get_system_ptf_handle
+{ 
+  return $generator_hr->{system_ptf_hr};
+}
+
+sub generator_get_language
+{
+  return $generator_hr->{language};
+}
+
+sub generator_get_class_ptf_handle
+{
+  return $generator_hr->{class_ptf_hr};
+}
+
+sub default_ribbit
+{
+  my ($arg) = (@_);
+  &ribbit("\n\n--Error: default_gen_lib: $arg\n");  
+}
+
+
+sub _copy_files
+{
+  my ($dest_dir, $source_dir, @files) = (@_);
+  my $function_name;
+  
+  #validate args
+  &default_ribbit("No target dir for function copy_files!")
+  unless ($dest_dir ne "");
+  
+  &default_ribbit("No source dir for function copy_files!")
+  unless ($source_dir ne "");
+
+  &default_ribbit("No files for function copy_files!")
+  unless (@files != 0);
+
+  
+  #check for valid directories
+  opendir (SDIR, $source_dir) or 
+    &default_ribbit("can't open $source_dir !");
+  
+  opendir (DDIR, $dest_dir) or
+    &default_ribbit("can't open $dest_dir !");
+  
+  
+  foreach my $source_file(@files){
+    # |
+    # | Separate out the source subdir and the source filename
+    # |
+    my $source_subdir = "";
+    my $source_filename = $source_file;
+
+    if($source_filename =~ /^(.*)\/(.*)$/)  # break on last slash
+    {
+      $source_subdir = "/$1"; # embed its leading slash, for concatty
+      $source_filename = $2;
+    }
+
+    my $source_fullpath = "$source_dir$source_subdir/$source_filename";
+    my $dest_fullpath = "$dest_dir/$source_filename";
+
+    &Perlcopy($source_fullpath, $dest_fullpath);
+    &generator_print_verbose("Copying file: \"$source_fullpath\""
+            . " to \"$dest_fullpath\".\n");
+  }
+
+  closedir (SDIR);
+  closedir (DDIR);
+}
+
+
+sub get_module_wrapper_arg_hash_from_system_ptf_file
+{
+  my $module_ptf_hr = $generator_hr->{module_ptf_hr};
+  
+  my @list_of_sections = ("MASTER","SLAVE","PORT_WIRING");
+  my @port_list;
+  foreach my $section(@list_of_sections){
+    my $number = get_child_count($module_ptf_hr, $section);
+
+    for(my $initial=0; $initial < $number; $initial++){
+      
+      my $interface_section = get_child($module_ptf_hr, $initial, $section);	
+      my $interface_section_name = get_data($interface_section);
+
+      my $port_wiring_section;
+      if($section ne "PORT_WIRING"){
+	$port_wiring_section = 
+	  get_child_by_path($module_ptf_hr, $section." ".$interface_section_name."/PORT_WIRING");	
+      }else{
+	$port_wiring_section =
+	  get_child_by_path($module_ptf_hr, $section);
+      }
+      my $num_ports = get_child_count($port_wiring_section, "PORT");
+      foreach(my $port_count = 0; $port_count < $num_ports; $port_count++){
+	my $port = get_child($port_wiring_section, $port_count, "PORT");
+	
+	my %port_info_struct;
+	$port_info_struct{name} = get_data($port);
+	$port_info_struct{direction} = get_data_by_path($port, "direction");
+	$port_info_struct{width} = get_data_by_path($port, "width");
+	$port_info_struct{vhdl_record_name} = get_data_by_path($port, "vhdl_record_name");
+	$port_info_struct{vhdl_record_type} = get_data_by_path($port, "vhdl_record_type");
+	
+	push(@port_list, \%port_info_struct);
+	
+      }
+    }	
+  }
+  $generator_hr->{wrapper_args}{ports} = \@port_list;
+}
+
+
+sub generator_make_module_wrapper
+{
+  my ($simulate_hdl, $top_module_name, $module_language) = (@_);
+
+  &default_ribbit("generator_make_module_wrapper: no arg0 passed in for simulate_hdl\n")
+    if($simulate_hdl eq '');
+
+  &default_ribbit("generator_make_module_wrapper: no arg1 passed in for top_module_name\n")
+    unless($top_module_name);
+
+  $generator_hr->{wrapper_args}{simulate_hdl} = $simulate_hdl;
+  $generator_hr->{wrapper_args}{top_module_name} = $top_module_name;
+  $generator_hr->{wrapper_args}{make_wrapper} = 1;
+  $generator_hr->{wrapper_args}{module_language} = $module_language;
+
+}
+
+
+
+
+# |
+# | recognize varous number forms,
+# | return 'h0123abcd-ish.
+# |
+sub turn_anything_into_appropriate_string($$$$)
+	{
+	my ($value,$type,$editable,$module_language) = (@_);
+
+    return $value if($value =~ /^\"/);   # quoted string: unscathed
+    return $value if($type eq "string"); # string: anything is ok
+    
+    return $value if(!$editable);        # and you know, if you can't change it, keep it!
+    
+    
+	# |
+	# | first, convert to a number
+	# |
+	my $base = 10;
+	my $n = $value;
+	my $width = 32;
+	my $number = 0;
+	
+	$value = lc($value); # lower case
+	
+	if($value =~ /^([0-9]*)\'([hbo])(.*)$/)
+		{
+		# | tick notation: AOK for verilog
+		if($module_language eq "verilog")
+			{
+			$number = $value;
+			}
+		# |
+		# | note: at this point, we could notice if the
+		# | result should be vhdl binary, and convert
+		# | to that, avoiding the precision-losing
+		# | integer intermediary
+		# |
+		# | (alternatively, we could use a binary string
+		# | always as the intermediate form, rather than
+		# | a precision-losing int.)
+		# |
+		else
+			{
+			$width = $1;
+			my $baseletter = $2;
+			my $digits = $3;
+			
+			if($baseletter eq "h")
+				{
+				$base = 16;
+				}
+			elsif($baseletter eq "b")
+				{
+				$base = 2;
+				}
+			elsif($baseletter eq "o") # must be
+				{
+				$base = 8;
+				}
+			
+			$digits =~ s/[ _-]//g; # crush out dividing value
+			
+			while(length($digits) > 0)
+				{
+				my $digit = substr($digits,0,1);
+				$digits = substr($digits,1);
+				my $digitvalue = hex($digit); # how handy
+				$number = $number * $base + $digitvalue;
+				}
+			}
+		}
+	elsif($value =~ /^0x(.*)$/)
+		{
+		$number = hex($1);
+		}
+	else  # try for decimal
+		{
+		$number = int(1 * $value);
+		}
+	
+	# |
+	# | ok, we have a number. If our target type
+	# | is "std_logic_vector(this downto that)"
+	# | for tricky VHDL, we
+	# | must quote a binary string out of it.
+	# |
+	
+	if(($module_language eq "vhdl") and ($type =~ /^.*\((\d+) downto (\d+)\).*$/))
+		{
+		my ($high_bit,$low_bit) = ($1,$2);
+		my $binary = "";
+		for(my $bit = $low_bit; $bit <= $high_bit; $bit++)
+			{
+			$binary = ($number % 2) . $binary;
+			$number = int($number >> 1);
+			}
+		
+		$number = '"' . $binary . '"';
+		}
+	
+	return $number;
+	}
+
+#
+# return @array of vhdl libraries, if any, from the class.ptf
+sub get_libraries()
+{
+    my $class_ptf = generator_get_class_ptf_handle();
+    my @libraries;
+    my $libraries_ptf = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/LIBRARIES");
+
+    if($libraries_ptf)
+        {
+        my $library_count = get_child_count($libraries_ptf,"library");
+        for(my $i = 0; $i < $library_count; $i++)
+        {
+            my $library_ptf = get_child($libraries_ptf,$i,"library");
+            my $library_name = get_data($library_ptf);
+            push(@libraries,$library_name);
+        }
+    }
+
+    return @libraries;
+}
+
+
+
+sub _generator_make_module_wrapper	
+{
+  
+  my $wrapper_args = $generator_hr->{wrapper_args};
+  my $no_black_box = $wrapper_args->{simulate_hdl};
+  my $top_module_name = $wrapper_args->{top_module_name};
+  my $language = $generator_hr->{language};
+  my @external_args = @{$generator_hr->{external_args}};
+  my $module_ptf_hr = $generator_hr->{module_ptf_hr};
+
+  ### Build Module
+  my $project = e_project->new(@external_args);
+  my $top = $project->top();
+  
+  # add the ports to the system module
+  my @ports;
+  
+  foreach my $port_hash(@{$wrapper_args->{ports}}){
+    my $porto = e_port->new({
+			     name => $port_hash->{name},
+			     width => $port_hash->{width},
+			     direction => $port_hash->{direction},
+			     vhdl_record_name => $port_hash->{vhdl_record_name},
+			     vhdl_record_type => $port_hash->{vhdl_record_type}
+			    });
+    push(@ports, $porto);
+  }
+  $top->add_contents(@ports);
+  
+
+
+
+
+    # +----------------------------------------
+    # | Get parameters from class.ptf
+    # | create @array of parameters, eacho
+    # | one like name=>, default=>, type=>,
+    # |  
+    # | These are the definitions of parameters for
+    # | ANY instance of this module; we need to 
+    # | have them in the "wrapee" module so that
+    # | when the system bus is knitted together
+    # | the parameter types can be properly used.
+    # |
+    # | (as it turns out, verilog doesnt need
+    # | them, but vhld does)
+    # |
+    # | dvb2004
+
+
+    my @e_hdl_parameters; # list of e_parameters
+
+    my $class_ptf = generator_get_class_ptf_handle();
+    my $hdl_parameter_definitions_ptf = get_child_by_path($class_ptf,"CLASS/COMPONENT_BUILDER/HDL_PARAMETERS");
+
+    my @libraries = get_libraries();
+
+    my $hdl_parameter_count = get_child_count($hdl_parameter_definitions_ptf,"HDL_PARAMETER");
+
+    my $module_language = $generator_hr->{wrapper_args}{module_language};
+
+    for(my $i = 0; $i < $hdl_parameter_count; $i++)
+        {
+        my $a_parameter = get_child($hdl_parameter_definitions_ptf,$i,"HDL_PARAMETER");
+        my $parameter_editable = get_data_by_path($a_parameter,"editable");
+        if($parameter_editable)
+                {
+                my $boring_name = get_data($a_parameter); # legal guinevere-ized
+                my $name = get_data_by_path($a_parameter,"parameter_name"); # original HDL name
+                my $default = get_data_by_path($a_parameter,"default_value");
+                my $type = get_data_by_path($a_parameter,"type");
+                
+                $default = turn_anything_into_appropriate_string($default,$type,1,$module_language);
+
+                my $a_parameter = e_parameter->new
+                    ({
+                    name => $name,
+                    default => $default,
+                    type => $type
+                    });
+
+                push (@e_hdl_parameters,$a_parameter);
+                }
+        }
+        
+
+
+    # | and @e_hdl_parameters is used below in the wrapee module
+    # +--------------------------------------------
+
+    # +--------------------------------------------
+    # | Now, we build a "hdl_parameter_map", which is just
+    # | your basic hash table with keys (parameters)
+    # | and values (parameter values).
+    # |
+    # | these are the particular values for this instance.
+    # |
+
+    my %hdl_parameter_map;
+    my $module_ptf = $generator_hr->{module_ptf_hr};
+    my $hdl_parameters_ptf =
+            get_child_by_path($module_ptf,"WIZARD_SCRIPT_ARGUMENTS/hdl_parameters");
+
+    my $child_count = get_child_count($hdl_parameters_ptf);
+
+    for(my $i = 0; $i < $child_count; $i++)
+        {
+        my $a_parameter = get_child($hdl_parameters_ptf,$i);
+
+        my $boring_name = get_name($a_parameter);
+        my $value = get_data($a_parameter);
+
+		# refer back to the original HDL name...
+        my $parameter_definition_ptf = get_child_by_path($hdl_parameter_definitions_ptf,"HDL_PARAMETER $boring_name");
+        my $parameter_name = get_data_by_path($parameter_definition_ptf,"parameter_name");
+        my $parameter_type = get_data_by_path($parameter_definition_ptf,"type");
+        my $parameter_editable = get_data_by_path($parameter_definition_ptf,"editable");
+        
+        $value = turn_anything_into_appropriate_string($value,$parameter_type,$parameter_editable,$module_language);
+
+        # |
+        # | our internal _dummy assignment shows up here
+        # | without a corresponding hdl entry. we
+        # | ignore it.
+        # |
+
+        if(($parameter_name ne "") and $parameter_editable)
+            {
+            $hdl_parameter_map{$parameter_name} = $value;
+            }
+        }
+
+  my $wrapee_module;
+  $wrapee_module = e_module->new({
+				 name => $top_module_name,
+				 contents =>  [@ports,@e_hdl_parameters],
+				 do_black_box => 0,
+				 do_ptf => 0,
+				 _hdl_generated => 1,
+				 _explicitly_empty_module => 1,
+				});
+
+  # VHDL Libraries, from PTF file...
+  $wrapee_module->add_vhdl_libraries(@libraries);
+  $top->add_vhdl_libraries(@libraries);
+
+
+  $top->add_contents (
+		      e_instance->new({
+				       module => $wrapee_module,
+                       parameter_map => \%hdl_parameter_map
+				      }),
+		     );
+  
+  $project->top()->do_ptf(0);
+  $project->do_write_ptf(0);
+  
+  
+  my $module_file = $project->_target_module_name().".v";
+  $module_file = $project->_target_module_name().".vhd"
+    if($language eq "vhdl");
+
+  $module_file = $generator_hr->{project_path_widget}."/".$module_file;
+  &generator_set_files_in_system_ptf("Synthesis_HDL_Files", ($module_file));
+  $project->output();
+
+
+  # if you don't want a simulation model, you don't get a simulation model
+  if($no_black_box eq "0")
+  {
+    my $black_project = e_project->new(@external_args);
+    $black_project->_target_module_name($top_module_name);
+    my $black_top = $black_project->top();
+
+
+
+    $black_top->add_contents(@ports);
+    my $black_top_instance;
+    $black_top_instance = e_module->new({
+				   name => $wrapper_args->{top_module_name}."_bb",
+				   contents =>  [@ports],
+				   do_black_box => 1,
+				   do_ptf => 0,
+				   _hdl_generated => 0,
+				   _explicitly_empty_module => 1,
+				  });
+    
+    $black_top->add_contents (
+			e_instance->new({
+					 module => $black_top_instance,
+					}),
+		       );
+
+
+
+
+    $black_project->top()->do_ptf(0);
+    $black_project->do_write_ptf(0);
+
+    my $black_module_file = $black_project->_target_module_name().".v";
+    $black_module_file = $black_project->_target_module_name().".vhd"
+      if($language eq "vhdl");
+
+
+    $black_module_file = $generator_hr->{project_path_widget}."/".$black_module_file;
+    &generator_set_files_in_system_ptf("Simulation_HDL_Files", ($black_module_file));
+
+#    &set_data_by_path($module_ptf_hr, "HDL_INFO/Simulation_HDL_Files", $black_module_file);
+
+
+    $black_project->output();
+  }
+
+}
+
+####
+# Args: $file_type : "synthesis", "synthesis_only", "simulation"
+#       @file_list   :  an array of files.  This list of files is assumed to be relative to the
+#                       component's directory
+
+
+my $decoder_ring_hr = {
+			quartus_only => {
+					 copy => 1,
+					 copy_to => "project",
+					 ptf_set => 0,
+					},
+			simulation_only => {
+					    copy => 1,
+					    copy_to => "simulation",
+					    ptf_set => 1,
+					    ptf_section => "Simulation_HDL_Files",
+					   },
+			simulation_and_quartus => {
+						   copy => 1,
+						   copy_to => "project",
+						   ptf_set => 1,
+						   ptf_section => "Synthesis_HDL_Files",
+						  }, 
+		       precompiled_simulation_files => {
+							copy => 0,
+							ptf_set => 1,
+							ptf_section => "Precompiled_Simulation_Library_Files",
+						       },
+		      };
+
+
+
+
+sub generator_copy_files_and_set_system_ptf
+{
+  my ($hdl_section, @file_list) = (@_);
+
+  my $ptf_path_prefix = "";  
+  my $external_args_hr = $generator_hr->{external_args_hr};
+  my @new_file_array;
+
+  #validate first
+  my $decoder_hash = $decoder_ring_hr->{$hdl_section};
+  &default_ribbit("generator_copy_files_and_set_system_ptf: No understood HDL section passed in for first arg\n")
+    unless($decoder_ring_hr->{$hdl_section} ne "");
+
+  &generator_print_verbose("generator_copy_files_and_set_system_ptf: copying files for section ".$hdl_section."\n");
+
+  #copy second
+  my @new_file_array;
+
+  # If we need to copy over some files, then we need to make sure we are 
+  # keeping track of what files we copy over.
+  # Otherwise, we just need to keep track of the files that the user has asked to copy over
+  # and use these instead.
+  if($decoder_hash->{copy}){
+    my $copy_to_location;
+    my $copy_from_location;
+
+    if($decoder_hash->{copy_to} eq "project"){
+      $copy_to_location = $external_args_hr->{system_directory};
+    }elsif($decoder_hash->{copy_to} eq "simulation"){
+      $copy_to_location = $external_args_hr->{system_sim_dir};
+    }else{
+      &default_ribbit("generator_copy_files_and_set_system_ptf: No understood copy files to location\n");
+    }
+
+    $copy_from_location = $external_args_hr->{class_directory};
+    @new_file_array = &generator_copy_files($copy_to_location, $copy_from_location, @file_list);
+  }else{
+    @new_file_array = @file_list;
+  }	
+
+  #scribble on PTF hash last
+  if($decoder_hash->{ptf_set}){
+
+    if($decoder_hash->{copy_to} eq "project"){
+      foreach my $file(@new_file_array){
+         $file =~ s/^.*\/(.*?)$/$1/;
+         $file = $generator_hr->{project_path_widget}."/".$file;
+      }
+    }
+    &generator_print_verbose("generator_copy_files_and_set_system_ptf: setting system PTF file in section ".$hdl_section."\n");
+    if($decoder_hash->{ptf_section} eq "Precompiled_Simulation_Library_Files"){
+      @new_file_array = map{$external_args_hr->{class_directory}."/".$_} @new_file_array;
+    }
+    &generator_set_files_in_system_ptf($decoder_hash->{ptf_section}, @new_file_array);
+  }
+}
+
+
+
+####
+# Name: generator_set_files_in_system_ptf
+# Args: $hdl_section
+#       @list_of_files
+# Returns: 1 or 0
+# Purpose: This is an internal function used to set files in the module's section in the system PTF file
+#
+sub generator_set_files_in_system_ptf
+{
+  my ($hdl_section, @list_of_files) = (@_);
+
+  my $file_list = join(",", @list_of_files);
+  my $previous_data;  
+
+  &generator_print_verbose("setting HDL_INFO/".$hdl_section." in system PTF file with ".$file_list."\n");
+  my $previous_data = &get_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section);  
+  if($previous_data){
+    $file_list = $previous_data . ", $file_list"; # spr 132177
+                                                  # swapping order, dvb 2003
+  }
+  &set_data_by_path($generator_hr->{module_ptf_hr}, "HDL_INFO/".$hdl_section, $file_list);
+}
+
+####
+# Name: generator_copy_files
+# Args: $target_directory
+#       $source_directory
+#       @list_of_files
+# Returns: The list of files which has been copied (suitable for framing!)
+# Purpose: This is an internal function used to copy files around in the generator program.
+#
+sub generator_copy_files
+{
+  my ($target_directory, $source_directory, @list_of_files) = (@_);
+
+  my @new_file_array;
+
+  foreach my $file_name(@list_of_files){
+     $file_name =~ s|\\|\/|g;
+    if($file_name =~ /\*\.*/){
+      $file_name =~ s/\*/$1/;
+      my @found_list = &_find_all_dir_files_with_ext($source_directory, $file_name);
+      push(@new_file_array, @found_list);
+    }else{
+      &generator_print_verbose("Copying: ".$file_name."\n");
+      push(@new_file_array, $file_name);
+    }
+  }
+
+  &_copy_files($target_directory, $source_directory, @new_file_array);
+  return @new_file_array;
+}
+
+
+
+sub _find_all_dir_files_with_ext
+{
+  my ($dir,
+      $ext) = (@_);
+
+  opendir (DIR, $dir) or
+    &default_ribbit("can't open $dir !");
+  
+  my @all_files = readdir(DIR);
+  my @new_file_list; 
+ 
+  
+  foreach my $file (@all_files){
+    if($file =~ /^.*($ext)$/){
+      push(@new_file_list, $file);
+    }
+  }
+
+  return @new_file_list;
+}
+
+####
+# Name: generator_begin
+# Args: Array of generator program launcher args
+# Returns: A hash reference to the module's section in the system PTF file
+# Purpose: This is the first subroutine a user should call before running the rest of their
+#          generator program.
+#
+
+sub generator_begin
+{
+  my @external_args = (@_);
+
+  my  ($external_args_hr, 
+       $temp_user_defined, 
+       $temp_db_Module, 
+       $temp_db_PTF_File) = Process_Wizard_Script_Arguments("", @external_args);
+
+  &generator_print_verbose("generator_begin: initializing\n");
+
+  $generator_hr->{external_args_hr} = $external_args_hr;
+  $generator_hr->{external_args} = \@external_args;
+
+  # open up class.ptf and 
+  $generator_hr->{class_ptf_hr} = new_ptf_from_file($external_args_hr->{class_directory}."/class.ptf");
+
+  # get the system.ptf 
+  $generator_hr->{system_ptf_hr} = new_ptf_from_file($external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf");
+  $generator_hr->{module_ptf_hr} = &get_child_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/MODULE $external_args_hr->{target_module_name}");
+  my $class_name = get_data_by_path($generator_hr->{module_ptf_hr}, "class");
+
+  # find the default generator section
+  $generator_hr->{language} = get_data_by_path($generator_hr->{system_ptf_hr}, "SYSTEM $external_args_hr->{system_name}/WIZARD_SCRIPT_ARGUMENTS/hdl_language");
+
+  # get some wrapper settings
+  &get_module_wrapper_arg_hash_from_system_ptf_file();
+
+  # clear system ptf's HDL section
+  &delete_child($generator_hr->{module_ptf_hr}, "HDL_INFO");
+
+  return $generator_hr->{module_ptf_hr};
+}	
+
+####
+# Name: generator_end
+# Args: none
+# Returns: nothing
+# Purpose: This is the last subroutine a user should call from their generator program.
+#          Not calling this subroutine will make you very sad... =<
+#
+
+sub generator_end
+{
+  # o.k., time to make the wrapper and output it.
+  if($generator_hr->{wrapper_args}{make_wrapper}){
+    &_generator_make_module_wrapper();
+  }
+
+  
+  my $external_args_hr = $generator_hr->{external_args_hr};
+  my $ptf_file_name = $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf";
+  &generator_print_verbose("generator_end: writing PTF file ".$external_args_hr->{system_name}.".ptf to ".$external_args_hr->{system_directory}."\n");
+
+  default_ribbit("Cannot write PTF file ".$ptf_file_name."!\n")
+    unless(&write_ptf_file($generator_hr->{system_ptf_hr}, $external_args_hr->{system_directory}."/".$external_args_hr->{system_name}.".ptf"));  
+}
+
+sub generator_end_read_module_wrapper_string
+{
+   my $language = &generator_get_language();
+   my $ls;
+
+   if($language =~ /vhdl/){
+     $ls = ".vhd";
+   }elsif($language =~ /verilog/){
+     $ls = ".v";
+   }else{
+     &ribbit("generator_end_read_module_wrapper_string invoked with unkown language");
+   }
+   my $system_dir = $generator_hr->{external_args_hr}->{system_directory};
+   my $module_name = $generator_hr->{external_args_hr}->{target_module_name};
+
+   my $file = $system_dir."/".$module_name.$ls;
+   &generator_print_verbose("generator library reading file into string: $file\n");
+
+   open (FILE,"<$file") or ribbit "cannot open file ($file) ($!)\n";
+   my $return_string;
+   while (<FILE>)
+   {
+      $return_string .= $_;
+   }
+   close (FILE);
+   return($return_string);
+}
+
+sub generator_end_write_module_wrapper_string
+{
+   my $string = shift or ribbit "no string specified\n";
+
+   my $language = &generator_get_language();
+   my $ls;
+
+   print $language;
+
+   if($language =~ /vhdl/){
+     $ls = ".vhd";
+   }elsif($language =~ /verilog/){
+     $ls = ".v";
+   }else{
+     &ribbit("generator_end_read_module_wrapper_string invoked with unkown language");
+   }
+   my $system_dir = $generator_hr->{external_args_hr}->{system_directory};
+   my $module_name = $generator_hr->{external_args_hr}->{target_module_name};
+
+   my $file = $system_dir."/".$module_name.$ls;
+   &generator_print_verbose("generator library writing string into file: $file\n");
+
+   open (FILE,">$file") or ribbit "cannot open file ($file) ($!)\n";
+   print FILE $string;
+   close (FILE);
+}
+# end of generator_library.pm
+
+
+
+
+
+#
+#
+#
+#
+# ---------------------------------------------------------------------
+
+# +----------------------------------------------------
+# | emit_system_h
+# |
+# | if "is_cpu", attempt to emit a system.h
+# | memory map.
+# |
+
+sub emit_system_h($$$)
+    {
+    my ($sopc_directory,$master,$system_ptf) = (@_);
+
+    # |
+    # | Build a system.h file for masters.
+    # |
+
+
+# as of quartus 5.0, we prefer gtf-generate in sopc_builder directly
+
+    my $gtf_generate = "$sopc_directory/bin/gtf-generate";
+    my $gtf_filename = "$sopc_directory/bin/gtf/system.h.gtf";
+    
+    if(! -f $gtf_generate)
+    	{
+    	# but if sopc_builder is missing it for whatever reason,
+    	# try the one in sopc_kit_nios2
+    	
+	    my $sopc_kit_nios2 = $ENV{SOPC_KIT_NIOS2};
+	    if($sopc_kit_nios2 ne "")
+	    	{
+	    	$gtf_generate = "$sopc_kit_nios2/bin/gtf-generate";
+    		$gtf_filename = "$sopc_kit_nios2/bin/gtf/system.h.gtf";
+    		}
+    	}
+
+    # |
+    # | xml template
+    # |
+
+    my $stf_template = <<EOP;
+<?xml version="1.0" encoding="UTF-8"?>
+<stf>
+<!-- This file generated on --date-- by --whoami-- -->
+    <project name="--project_name--"
+             ptf="--system_ptf--"
+             dir="--output_directory--"
+    />
+    <cpu name="--master--" />
+</stf>
+
+EOP
+
+    # |
+    # | THINK
+    # |
+
+    my $output_directory = "./${master}_map";
+    my $project_name = "ignored";
+    my $stf_filename = "./${master}_project.stf";
+
+    # |
+    # | build up template variables
+    # |
+
+    my %template_vars;
+    $template_vars{date} = fcu_date_time();
+    $template_vars{whoami} = $0;
+    $template_vars{project_name} = $project_name;
+    $template_vars{system_ptf} = $system_ptf;
+    $template_vars{output_directory} = $output_directory;
+    $template_vars{master} = $master;
+
+    # |
+    # | poke in the values to the template
+    # |
+
+    foreach my $key (sort(keys(%template_vars)))
+        {
+        $stf_template =~ s/--$key--/$template_vars{$key}/gs;
+        }
+
+    ## debug print $stf_template;
+
+    # |
+    # | write out the stf file, so we can soon use it
+    # |
+
+    fcu_write_file($stf_filename,$stf_template);
+
+    # |
+    # | and use it
+    # |
+
+    if(-e $gtf_generate && -e $gtf_filename)
+        {
+
+        my $generate_cmd = $gtf_generate;
+
+        $generate_cmd .= " --output-directory=$output_directory";
+        $generate_cmd .= " --gtf=$gtf_filename";
+        $generate_cmd .= " --stf=$stf_filename";
+
+        r_system($sopc_directory,$generate_cmd);
+    
+        # |
+        # | done with it
+        # |
+
+        r_system($sopc_directory,"rm $stf_filename");
+
+        fcu_print_command("Generated memory map \"$output_directory/system.h\"");
+        }
+    else
+        {
+        fcu_print_command("Warning: did NOT emit system.h for $master");
+        }
+
+
+
+
+    }
+
+
+sub r_system($$)
+    {
+    my ($sopc_directory,$cmd) = (@_);
+    fcu_print_command($cmd);
+    return Run_Command_In_Unix_Like_Shell($sopc_directory,$cmd);
+    }
+
+
+
+
+
+
+
+# +------------------------------------------
+# | synthesis and simulation files are are
+# | listed in CLASS/CB_GENERATOR/HDL_FILES.
+# |
+
+sub get_synthesis_files($)
+    {
+    my ($class_ptf) = (@_);
+    my $synthesis_files = "";
+    my $simulation_files = "";
+
+    my $hdl_files = get_child_by_path($class_ptf,"CLASS/CB_GENERATOR/HDL_FILES");
+    my $child_count = get_child_count($hdl_files);
+    for(my $i = 0; $i < $child_count; $i++)
+        {
+        my $hdl_file = get_child($hdl_files,$i);
+        if(get_name($hdl_file) eq "FILE")
+            {
+            my $filename = get_data_by_path($hdl_file,"filepath");
+            my $use_in_synthesis = get_data_by_path($hdl_file,"use_in_synthesis");
+            my $use_in_simulation = get_data_by_path($hdl_file,"use_in_simulation");
+
+            if($use_in_synthesis)
+                {
+                $synthesis_files .= ", " if $synthesis_files;
+                $synthesis_files .= $filename;
+                }
+
+            if($use_in_simulation)
+                {
+                $simulation_files .= ", " if $simulation_files;
+                $simulation_files .= $filename;
+                }
+            }
+        }
+
+    return $synthesis_files;
+    }
+
+
+
+
+
+
+
+
+sub main
+    {
+
+    push(@ARGV,"--verbose=1") if 0;
+    my %args = fcu_parse_args(@ARGV);
+    
+    if(0)
+    	{
+    	foreach my $key (sort(keys(%args)))
+    		{
+    		print("--$key = $args{$key} \n");
+    		}
+    	}
+
+    # |
+    # | get the arguments we care about
+    # |
+
+    my $class_dir = fcu_get_switch(\%args,"module_lib_dir");
+
+
+    my $target_module_name = fcu_get_switch(\%args,"target_module_name");
+    my $system_name = fcu_get_switch(\%args,"system_name");
+    my $sopc_directory = fcu_get_switch(\%args,"sopc_directory");
+
+    # |
+    # | preflight the arguments a little
+    # |
+
+    my $error_count = 0;
+
+    my $class_ptf_path = "$class_dir/class.ptf";
+    if(!-f $class_ptf_path)
+        {
+        print "error: no class.ptf at \"$class_dir\"\n";
+        $error_count++;
+        }
+
+    die "$error_count errors" if($error_count > 0);
+
+    # +-------------------------------------------
+    # | ok, let us get to work
+    # |
+
+
+    my $class_ptf = new_ptf_from_file($class_ptf_path);
+
+    # |
+    # | emit system.h for this module
+    # | TODO iff Is_CPU i guess.
+    # |
+
+    my $do_emit_system_h = get_data_by_path($class_ptf,
+            "CLASS/CB_GENERATOR/emit_system_h");
+    if($do_emit_system_h)
+        {
+        emit_system_h($sopc_directory,
+                $target_module_name,
+                "./$system_name.ptf");
+        }
+    
+    my $top_module_name = get_data_by_path($class_ptf,
+            "CLASS/CB_GENERATOR/top_module_name");
+    my $file_name = "";
+    
+    # | stored as file_name.v:module_name, so we break it open
+    if($top_module_name =~ /^(.*):(.*)$/)
+        {
+        $file_name = $1;
+        my $module_name = $2;
+        $top_module_name = $module_name;
+        }
+    
+    # | language of this particular module...
+
+    my $module_language = "verilog";
+    if($file_name =~ /^.*\.vhd$/)
+    	{
+    	$module_language = "vhdl";
+    	}
+    
+    # |
+    # | consult the CB_GENERATOR/HDL_FILES section regarding
+    # | where our HDL files for synthesis are.
+    # |
+     
+
+    my $synthesis_files = get_synthesis_files($class_ptf);
+
+    
+    my $instantiate_in_system_module = get_data_by_path($class_ptf,
+    	"CLASS/MODULE_DEFAULTS/SYSTEM_BUILDER_INFO/Instantiate_In_System_Module");
+
+
+
+	if($instantiate_in_system_module)
+		{
+	    generator_enable_mode ("terse");
+
+
+	    generator_begin (@ARGV);
+
+
+	    generator_make_module_wrapper(1,$top_module_name,$module_language);
+
+	    generator_copy_files_and_set_system_ptf
+    	        (
+        	    "simulation_and_quartus", 
+                split(/ *, */,$synthesis_files)
+#            	"$synthesis_files"
+          	  );
+
+		generator_end ();
+		}
+
+    exit (0);
+    }
+
+$| = 1;  # always polite to flush.
+main()
+
+# end of file
Index: common/components/usbhostslave/trunk/syn/readme.txt
===================================================================
--- common/components/usbhostslave/trunk/syn/readme.txt	(nonexistent)
+++ common/components/usbhostslave/trunk/syn/readme.txt	(revision 264)
@@ -0,0 +1,13 @@
+The component Builder in Quartus 6.0 will not accept include files, so you have to use Quartus to synthesize
+the source code into a single .vqm file, then rename this as a .v file, and then import this using component Builder.
+There is a make file in this directory that can called from cygwin and used to copy the RTL source to sopcCompProj/src
+
+From cygwin
+make
+Open Quartus project 'usbHostSlaveAvalonWrap.qpf'
+Processing >> Start >> Start Analysis and Synthesis
+Processing >> Start >> Start VQM Writer
+Copy sopcCompProj/atom_net_list/usbHostSlaveAvalonWrap.vqm to 
+sopcCompProj/usbhostslaveavalonwrap/hdl/usbHostSlaveAvalonWrap.v
+Copy sopcCompProj/usbhostslaveavalonwrap directory to the Quartus project directory where you wish to use the new component
+
Index: common/components/usbhostslave/trunk/usbDevice/Aldec/design0/src/EP1Mouse.asf
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/Aldec/design0/src/EP1Mouse.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/Aldec/design0/src/EP1Mouse.asf	(revision 264)
@@ -0,0 +1,172 @@
+VERSION=1.15
+HEADER
+FILE="EP1Mouse.asf"
+FID=4788d213
+LANGUAGE=VERILOG
+ENTITY="EP1Mouse"
+FRAMES=ON
+FREEOID=1083
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// EP1Mouse.v                                                 ////\n////                                                              ////\n//// This file is part of the usbHostSlave opencores effort.\n//// <http://www.opencores.org/cores//>                           ////\n////                                                              ////\n//// Module Description:                                          ////\n//// Implements EP1 as a IN endpoint\n//// simulating a mouse (a broken one) by \n//// responding to IN requests with a constant (x,y) = (1,1)\n//// which causes the mouse pointer to move from \n//// top left to bottom right of the screen\n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from <http://www.opencores.org/lgpl.shtml>                   ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbHostSlaveReg_define.v\"\n"
+END
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+I 499 0 2 Builtin InPort | 92423,247683 "" ""
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+C 1066 1062 0 TEXT "Conditions" | 94485,177150 1 0 0 "initComplete == 1'b1"
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+L 1081 1082 0 TEXT "Labels" | 171220,218950 1 0 0 "transDone"
+I 1082 0 2 Builtin Signal | 168220,218950 "" ""
+END
Index: common/components/usbhostslave/trunk/usbDevice/RTL/checkLineState.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/checkLineState.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/checkLineState.v	(revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// checkLineState.v                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Checks USB line state. When reset state detected
+//// asserts usbRstDet for one clock tick
+//// usbRstDet is used to reset most of the logic.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSlaveControl_h.v"
+`include "usbHostSlaveReg_define.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbDevice_define.v"
+module checkLineState (clk, initComplete, rst, usbRstDet, wb_ack, wb_addr, wb_data_i, wb_stb, wb_we, wbBusGnt, wbBusReq);
+input   clk;
+input   initComplete;
+input   rst;
+input   wb_ack;
+input   [7:0]wb_data_i;
+input   wbBusGnt;
+output  usbRstDet;
+output  [7:0]wb_addr;
+output  wb_stb;
+output  wb_we;
+output  wbBusReq;
+
+wire    clk;
+wire    initComplete;
+wire    rst;
+reg     usbRstDet, next_usbRstDet;
+wire    wb_ack;
+reg     [7:0]wb_addr, next_wb_addr;
+wire    [7:0]wb_data_i;
+reg     wb_stb, next_wb_stb;
+reg     wb_we, next_wb_we;
+wire    wbBusGnt;
+reg     wbBusReq, next_wbBusReq;
+
+// diagram signals declarations
+reg  [15:0]cnt, next_cnt;
+reg  [1:0]resetState, next_resetState;
+
+// BINARY ENCODED state machine: chkLSt
+// State codes definitions:
+`define START 3'b000
+`define GET_STAT 3'b001
+`define WT_GNT 3'b010
+`define SET_RST_DET 3'b011
+`define DEL_ONE_MSEC 3'b100
+
+reg [2:0]CurrState_chkLSt, NextState_chkLSt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: chkLSt
+
+// NextState logic (combinatorial)
+always @ (initComplete or wb_ack or resetState or wbBusGnt or cnt or usbRstDet or wbBusReq or wb_addr or wb_stb or wb_we or CurrState_chkLSt)
+begin
+  NextState_chkLSt <= CurrState_chkLSt;
+  // Set default values for outputs and signals
+  next_usbRstDet <= usbRstDet;
+  next_wbBusReq <= wbBusReq;
+  next_wb_addr <= wb_addr;
+  next_wb_stb <= wb_stb;
+  next_wb_we <= wb_we;
+  next_cnt <= cnt;
+  next_resetState <= resetState;
+  case (CurrState_chkLSt)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_usbRstDet <= 1'b0;
+      next_wbBusReq <= 1'b0;
+      next_wb_addr <= 8'h00;
+      next_wb_stb <= 1'b0;
+      next_wb_we <= 1'b0;
+      next_cnt <= 16'h0000;
+      next_resetState <= 2'b00;
+      if (initComplete == 1'b1)
+      begin
+        NextState_chkLSt <= `WT_GNT;
+      end
+    end
+    `GET_STAT:
+    begin
+      next_wb_addr <= `RA_SC_LINE_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_chkLSt <= `SET_RST_DET;
+        next_wb_stb <= 1'b0;
+        if ( (wb_data_i[1:0] == `DISCONNECT) || (wb_data_i[`VBUS_PRES_BIT] == 1'b0) )
+        next_resetState <= {resetState[0], 1'b1};
+        else
+        next_resetState <= 2'b00;
+        next_wbBusReq <= 1'b0;
+      end
+    end
+    `WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_chkLSt <= `GET_STAT;
+      end
+    end
+    `SET_RST_DET:
+    begin
+      NextState_chkLSt <= `DEL_ONE_MSEC;
+      if (resetState == 2'b11) // if reset condition aserted for 2mS
+      next_usbRstDet <= 1'b1;
+      next_cnt <= 16'h0000;
+    end
+    `DEL_ONE_MSEC:
+    begin
+      next_cnt <= cnt + 1'b1;
+      next_usbRstDet <= 1'b0;
+      if (cnt == `ONE_MSEC_DEL)
+      begin
+        NextState_chkLSt <= `WT_GNT;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+    CurrState_chkLSt <= `START;
+  else
+    CurrState_chkLSt <= NextState_chkLSt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    usbRstDet <= 1'b0;
+    wbBusReq <= 1'b0;
+    wb_addr <= 8'h00;
+    wb_stb <= 1'b0;
+    wb_we <= 1'b0;
+    cnt <= 16'h0000;
+    resetState <= 2'b00;
+  end
+  else 
+  begin
+    usbRstDet <= next_usbRstDet;
+    wbBusReq <= next_wbBusReq;
+    wb_addr <= next_wb_addr;
+    wb_stb <= next_wb_stb;
+    wb_we <= next_wb_we;
+    cnt <= next_cnt;
+    resetState <= next_resetState;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceAlteraTop.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceAlteraTop.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceAlteraTop.v	(revision 264)
@@ -0,0 +1,425 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbDeviceAlteraTop.v                                                 ////
+////                                                              ////
+//// This file is part of the spiMaster opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Top level module for Altera FPGA and NXP ISP1105 USB PHY.
+//// Specifically it targets the Base2Designs Altera Development board.
+//// Instantiates a PLL so that the lock signal can be used
+//// to reset the logic, and ties unused control signals
+//// to the off or disabled state
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//`define PHY_ISP1105
+module usbDeviceAlteraTop (
+
+	//
+	// Global signals
+	//
+		clk,
+
+	//
+	// SDRAM
+	//
+	mc_addr,
+	mc_ba,
+	mc_dqm,
+	mc_we_,
+	mc_cas_,
+	mc_ras_,
+	mc_cke_,
+	sdram_cs,
+	sdram_clk,
+
+  //
+  // SPI bus
+  //
+  spiClk,
+  spiMasterDataOut,
+  spiCS_n,
+
+
+  //
+  // USB host
+  //
+  //usbHostOE_n,
+
+  //
+  // USB slave
+  //
+  //usbSlaveVP,
+  //usbSlaveVM,
+
+  //usbSlaveOE_n,
+  //usbDPlusPullup,
+  //vBusDetect,
+
+  //
+  // Santa Cruz header
+  //
+  SC_P_CLK,
+  SC_RST_N,
+  SC_CS_N,
+  SC_P0,
+  SC_P1,
+  SC_P2,
+  SC_P3,
+  SC_P4,
+  SC_P5,
+  SC_P6,
+  SC_P7,
+  SC_P8,
+  SC_P9,
+  SC_P10,
+  SC_P11,
+  SC_P12,
+  SC_P13,
+  SC_P14,
+  SC_P15,
+  SC_P16,
+  SC_P17,
+  SC_P18,
+  SC_P19,
+  SC_P20,
+  SC_P21,
+  SC_P22,
+  SC_P23,
+  SC_P24,
+  SC_P25,
+  SC_P26,
+  SC_P27,
+  SC_P28,
+  SC_P29,
+  SC_P30,
+  SC_P31,
+  SC_P32,
+  SC_P33,
+  SC_P34,
+  SC_P35,
+  SC_P36,
+  SC_P37,
+  SC_P38,
+  SC_P39
+
+
+
+);
+	//
+	// Global signals
+	//
+	input	clk;
+
+	//
+	// SDRAM
+	//
+	output	[11:0]	mc_addr;
+	output	[1:0]	mc_ba;
+	output	[3:0]	mc_dqm;
+	output		mc_we_;
+	output		mc_cas_;
+	output		mc_ras_;
+	output		mc_cke_;
+	output		sdram_cs;
+	output		sdram_clk;
+
+  //
+  // SPI bus
+  //
+  output spiClk;
+  output spiMasterDataOut;
+  output spiCS_n;
+
+  //
+  // USB host
+  //
+  //output usbHostOE_n;
+
+  //
+  // USB slave
+  //
+  //inout usbSlaveVP;
+  //inout usbSlaveVM;
+
+  //output usbSlaveOE_n;
+  //output usbDPlusPullup;
+  //input vBusDetect;
+
+`ifdef PHY_ISP1105
+  output SC_P_CLK;
+  output SC_RST_N;
+  output SC_CS_N;
+  output SC_P0;
+  output SC_P1;
+  output SC_P2;
+  output SC_P3;
+  output SC_P4;
+  output SC_P5;
+  output SC_P6;
+  output SC_P7;
+  output SC_P8;
+  output SC_P9;
+  output SC_P10;
+  output SC_P11;
+  output SC_P12;
+  output SC_P13;
+  output SC_P14;
+  output SC_P15;
+  output SC_P16;
+  output SC_P17;
+  output SC_P18;
+  output SC_P19;
+  input SC_P20;
+  output SC_P21;
+  inout SC_P22;
+  inout SC_P23;
+  output SC_P24;
+  output SC_P25;
+  output SC_P26;
+  output SC_P27;
+  output SC_P28;
+  output SC_P29;
+  output SC_P30;
+  output SC_P31;
+  output SC_P32;
+  output SC_P33;
+  output SC_P34;
+  output SC_P35;
+  output SC_P36;
+  output SC_P37;
+  output SC_P38;
+  output SC_P39;
+`else
+  output SC_P_CLK;
+  output SC_RST_N;
+  output SC_CS_N;
+  output SC_P0;
+  output SC_P1;
+  input SC_P2;
+  output SC_P3;
+  input SC_P4;
+  output SC_P5;
+  output SC_P6;
+  output SC_P7;
+  output SC_P8;
+  output SC_P9;
+  output SC_P10;
+  output SC_P11;
+  output SC_P12;
+  output SC_P13;
+  output SC_P14;
+  output SC_P15;
+  output SC_P16;
+  output SC_P17;
+  output SC_P18;
+  output SC_P19;
+  output SC_P20;
+  output SC_P21;
+  input SC_P22;
+  output SC_P23;
+  input SC_P24;
+  output SC_P25;
+  output SC_P26;
+  output SC_P27;
+  output SC_P28;
+  output SC_P29;
+  output SC_P30;
+  output SC_P31;
+  output SC_P32;
+  output SC_P33;
+  output SC_P34;
+  output SC_P35;
+  output SC_P36;
+  output SC_P37;
+  output SC_P38;
+  output SC_P39;
+`endif
+
+
+
+//local wires and regs
+reg [1:0] rstReg;
+wire rst;
+wire pll_locked;
+wire usbSlaveVP_in;
+wire usbSlaveVM_in;
+wire usbSlaveVP_out;
+wire usbSlaveVM_out;
+wire usbSlaveFullSpeed;
+
+assign mc_addr = {12{1'b0}};
+assign mc_ba = 2'b00;
+assign mc_dqm = 4'h0;
+assign mc_we_ = 1'b1;
+assign mc_cas_ = 1'b1;
+assign mc_ras_ = 1'b1;
+assign mc_cke_ = 1'b1;
+assign sdram_cs = 1'b1;
+assign sdram_clk = 1'b1;
+assign spiClk = 1'b0;
+assign spiMasterDataOut = 1'b0;
+assign spiCS_n = 1'b1;
+assign usbHostOE_n = 1'b1;
+
+pll_48MHz	pll_48MHz_inst (
+	.inclk0 ( clk ),
+	.locked( pll_locked)
+	);
+
+//generate sync reset from pll lock signal
+always @(posedge clk) begin
+  rstReg[1:0] <= {rstReg[0], ~pll_locked};
+end
+assign rst = rstReg[1];
+
+
+usbDevice u_usbDevice (
+  .clk(clk),
+  .rst(rst),
+  .usbSlaveVP_in(usbSlaveVP_in),
+  .usbSlaveVM_in(usbSlaveVM_in),
+  .usbSlaveVP_out(usbSlaveVP_out),
+  .usbSlaveVM_out(usbSlaveVM_out),
+  .usbSlaveOE_n(usbSlaveOE_n),
+  .USBFullSpeed(usbSlaveFullSpeed),
+  .usbDPlusPullup(usbDPlusPullup),
+  .usbDMinusPullup(usbDMinusPullup),
+  .vBusDetect(vBusDetect)
+);
+
+`ifdef PHY_ISP1105
+assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
+assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
+`else
+assign vBusDetect = 1'b1;
+`endif
+
+`ifdef PHY_ISP1105
+  assign SC_P_CLK = 1'b0;
+  assign SC_RST_N = 1'b0;
+  assign SC_CS_N = 1'b0;
+  assign SC_P0 = 1'b0;
+  assign SC_P1 = 1'b0;
+  assign SC_P2 = 1'b0;
+  assign SC_P3 = 1'b0;
+  assign SC_P4 = 1'b0;
+  assign SC_P5 = 1'b0;
+  assign SC_P6 = 1'b0;
+  assign SC_P7 = 1'b0;
+  assign SC_P8 = 1'b0;
+  assign SC_P9 = 1'b0;
+  assign SC_P10 = 1'b0;
+  assign SC_P11 = 1'b0;
+  assign SC_P12 = 1'b0;
+  assign SC_P13 = 1'b0;
+  assign SC_P14 = 1'b0;
+  assign SC_P15 = 1'b0;
+  assign SC_P16 = 1'b0;
+  assign SC_P17 = 1'b0;
+  assign SC_P18 = 1'b0;
+  assign SC_P19 = 1'b0;
+  assign vBusDetect = SC_P20;
+  assign SC_P21 = 1'b0;
+  assign SC_P22 = usbSlaveVM;
+  assign SC_P23 = usbSlaveVP;
+  assign SC_P24 = usbSlaveOE_n;
+  assign SC_P25 = 1'b0;
+  assign SC_P26 = usbDPlusPullup;
+  assign SC_P27 = 1'b0;
+  assign SC_P28 = usbHostOE_n;
+  assign SC_P29 = 1'b0;
+  assign SC_P30 = 1'b0;
+  assign SC_P31 = 1'b0;
+  assign SC_P32 = 1'b0;
+  assign SC_P33 = 1'b0;
+  assign SC_P34 = 1'b0;
+  assign SC_P35 = 1'b0;
+  assign SC_P36 = 1'b0;
+  assign SC_P37 = 1'b0;
+  assign SC_P38 = 1'b0;
+  assign SC_P39 = 1'b0;
+`else
+  assign SC_P_CLK = 1'b0;
+  assign SC_RST_N = 1'b0;
+  assign SC_CS_N = 1'b0;
+  assign SC_P0 = usbSlaveFullSpeed;
+  assign SC_P1 = 1'b0;
+  assign usbSlaveVM_in = SC_P2;
+  assign SC_P3 = 1'b0;
+  assign usbSlaveVP_in = SC_P4;
+  assign SC_P5 = 1'b0;
+  assign SC_P6 = usbSlaveOE_n;
+  assign SC_P7 = 1'b0;
+  assign SC_P8 = usbSlaveVM_out;
+  assign SC_P9 = 1'b0;
+  assign SC_P10 = usbSlaveVP_out;
+  assign SC_P11 = 1'b0;
+  assign SC_P12 = usbDPlusPullup;
+  assign SC_P13 = 1'b0;
+  assign SC_P14 = usbDMinusPullup;
+  assign SC_P15 = 1'b0;
+  assign SC_P16 = 1'b0;
+  assign SC_P17 = 1'b0;
+  assign SC_P18 = 1'b0;
+  assign SC_P19 = 1'b0;
+  assign SC_P20 = 1'b0;
+  assign SC_P21 = 1'b0;
+  assign usbHostVM_in = SC_P22;
+  assign SC_P23 = 1'b0;
+  assign usbHostVP_in = SC_P24;
+  assign SC_P25 = usbHostOE_n;
+  assign SC_P26 = 1'b0;
+  assign SC_P27 = 1'b0;
+  assign SC_P28 = 1'b0;
+  assign SC_P29 = 1'b0;
+  assign SC_P30 = 1'b0;
+  assign SC_P31 = 1'b0;
+  assign SC_P32 = 1'b0;
+  assign SC_P33 = 1'b0;
+  assign SC_P34 = 1'b0;
+  assign SC_P35 = 1'b0;
+  assign SC_P36 = 1'b0;
+  assign SC_P37 = 1'b0;
+  assign SC_P38 = 1'b0;
+  assign SC_P39 = 1'b0;
+`endif
+
+
+
+endmodule
+
+
Index: common/components/usbhostslave/trunk/usbDevice/RTL/usbROM.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/usbROM.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/usbROM.v	(revision 264)
@@ -0,0 +1,254 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbROM.v                                                     ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// if you modify this file, be sure to modify usbDevice_define.v
+//// Using RAM rather than logic resources might be a more efficient implememtation
+//// but this has the advantage of working with FPGAs that do not provide a 
+//// mechanism for initialising RAM, eg Actel IGLOO
+//// Quartus 7.2 will infer this code as BLOCK RAM, and provide initialisation - nice
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "usbDevice_define.v"
+
+
+module usbROM (
+  clk,
+  addr,
+  data
+);
+input clk;
+input [7:0] addr;
+output [7:0] data;
+reg [7:0] data;
+
+always @(posedge clk) begin
+  case (addr)
+// ====================================
+// =====    DEVICE Descriptor     =====
+// ====================================
+
+    8'h00: data <= 8'h12;  //BYTE bLength
+    8'h01: data <= 8'h01;  //BYTE bDescriptorType
+    8'h02: data <= 8'h10;  //WORD (Lo) bcdUSB version supported
+    8'h03: data <= 8'h01;  //WORD (Hi) bcdUSB version supported
+    8'h04: data <= 8'h00;  //BYTE bDeviceClass
+    8'h05: data <= 8'h00;  //BYTE bDeviceSubClass
+    8'h06: data <= 8'h00;  //BYTE bDeviceProtocol
+	 8'h07: data <= `MAX_RESP_SIZE;  //BYTE bMaxPacketSize 
+    8'h08: data <= 8'hC7;  //WORD (Lo) idVendor
+    8'h09: data <= 8'h05;  //WORD (Hi) idVendor
+    8'h0a: data <= 8'h13;  //WORD (Lo) idProduct; For Philips Hub mouse
+    8'h0b: data <= 8'h01;  //WORD (Hi) idProduct; For Philips Hub mouse
+    8'h0c: data <= 8'h01;  //WORD (Lo) bcdDevice
+    8'h0d: data <= 8'h00;  //WORD (Hi) bcdDevice
+    8'h0e: data <= 8'h01;  //BYTE iManufacturer
+    8'h0f: data <= 8'h02;  //BYTE iProduct
+    8'h10: data <= 8'h03;  //BYTE iSerialNumber
+    8'h11: data <= 8'h01;  //BYTE bNumConfigurations
+
+ 
+// ====================================
+// ===== Configuration Descriptor =====
+// ====================================
+    8'h12: data <= 8'h09;  //BYTE bLength (Configuration descriptor)
+    8'h13: data <= 8'h02;  //BYTE bDescriptorType //Assigned by USB
+	 8'h14: data <= 8'd34;  //WORD (Lo) wTotalLength
+    8'h15: data <= 8'h00;  //WORD (Hi) wTotalLength
+    8'h16: data <= 8'h01;  //BYTE bNumInterfaces
+    8'h17: data <= 8'h01;  //BYTE bConfigurationValue
+    8'h18: data <= 8'h00;  //BYTE iConfiguration
+    8'h19: data <= 8'ha0;  //BYTE bmAttributes, Bus powered and remote wakeup
+    8'h1a: data <= 8'h32;  //BYTE MaxPower, 100mA
+ 
+// ====================================
+// =====   Interface Descriptor   =====
+// ====================================
+    8'h1b: data <= 8'h09;  //BYTE bLength (Interface descriptor)
+    8'h1c: data <= 8'h04;  //BYTE bDescriptionType; assigned by USB
+    8'h1d: data <= 8'h00;  //BYTE bInterfaceNumber
+    8'h1e: data <= 8'h00;  //BYTE bAlternateSetting
+    8'h1f: data <= 8'h01;  //BYTE bNumEndpoints; uses 1 endpoints
+    8'h20: data <= 8'h03;  //BYTE bInterfaceClass; HID Class - 0x03
+    8'h21: data <= 8'h01;  //BYTE bInterfaceSubClass
+    8'h22: data <= 8'h02;  //BYTE bInterfaceProtocol
+    8'h23: data <= 8'h00;  //BYTE iInterface
+ 
+// ====================================
+// =====   HID Descriptor   =====
+// ====================================
+    8'h24: data <= 8'h09;  //BYTE bLength (HID Descriptor)
+    8'h25: data <= 8'h21;  //BYTE bDescriptorType
+    8'h26: data <= 8'h10;  //WORD (Lo) bcdHID
+    8'h27: data <= 8'h01;  //WORD (Hi) bcdHID
+    8'h28: data <= 8'h00;  //BYTE bCountryCode
+    8'h29: data <= 8'h01;  //BYTE bNumDescriptors
+    8'h2a: data <= 8'h22;  //BYTE bReportDescriptorType
+    8'h2b: data <= 8'h32;  //WORD (Lo) wItemLength
+    8'h2c: data <= 8'h00;  //WORD (Hi) wItemLength
+
+// ====================================
+// =====   Endpoint 1 Descriptor  =====
+// ====================================
+    8'h2d: data <= 8'h07;  //BYTE bLength (Endpoint Descriptor)
+    8'h2e: data <= 8'h05;  //BYTE bDescriptorType; assigned by USB
+    8'h2f: data <= 8'h81;  //BYTE bEndpointAddress; IN endpoint; endpoint 1
+    8'h30: data <= 8'h03;  //BYTE bmAttributes; Interrupt endpoint
+    8'h31: data <= 8'h10;  //WORD (Lo) wMaxPacketSize
+    8'h32: data <= 8'h00;  //WORD (Hi) wMaxPacketSize
+    8'h33: data <= 8'hFF;  //BYTE bInterval
+
+ 
+// ====================================
+// =====   Report Descriptor  =====
+// ====================================
+
+    8'h3a: data <= 8'h05;     8'h3b: data <= 8'h01;    // USAGE_PAGE (Generic Desktop)
+    8'h3c: data <= 8'h09;     8'h3d: data <= 8'h02;    // USAGE (Mouse)
+    8'h3e: data <= 8'ha1;     8'h3f: data <= 8'h01;    // COLLECTION (Application)
+    8'h40: data <= 8'h09;     8'h41: data <= 8'h01;    //   USAGE (Pointer)
+    8'h42: data <= 8'ha1;     8'h43: data <= 8'h00;    //   COLLECTION (Physical)
+    8'h44: data <= 8'h05;     8'h45: data <= 8'h09;    //     USAGE_PAGE (Button)
+    8'h46: data <= 8'h19;     8'h47: data <= 8'h01;    //     USAGE_MINIMUM (Button 1)
+    8'h48: data <= 8'h29;     8'h49: data <= 8'h03;    //     USAGE_MAXIMUM (Button 3)
+    8'h4a: data <= 8'h15;     8'h4b: data <= 8'h00;    //     LOGICAL_MINIMUM (0)
+    8'h4c: data <= 8'h25;     8'h4d: data <= 8'h01;    //     LOGICAL_MAXIMUM (1)
+    8'h4e: data <= 8'h95;     8'h4f: data <= 8'h03;    //     REPORT_COUNT (3)
+    8'h50: data <= 8'h75;     8'h51: data <= 8'h01;    //     REPORT_SIZE (1)
+    8'h52: data <= 8'h81;     8'h53: data <= 8'h02;    //     INPUT (Data,Var,Abs)
+    8'h54: data <= 8'h95;     8'h55: data <= 8'h01;    //     REPORT_COUNT (1)
+    8'h56: data <= 8'h75;     8'h57: data <= 8'h05;    //     REPORT_SIZE (5)
+    8'h58: data <= 8'h81;     8'h59: data <= 8'h01;    //     INPUT (Cnst,Var,Rel)
+    8'h5a: data <= 8'h05;     8'h5b: data <= 8'h01;    //     USAGE_PAGE (Generic Desktop)
+    8'h5c: data <= 8'h09;     8'h5d: data <= 8'h30;    //     USAGE (X)
+    8'h5e: data <= 8'h09;     8'h5f: data <= 8'h31;    //     USAGE (Y)
+    8'h60: data <= 8'h15;     8'h61: data <= 8'h81;    //     LOGICAL_MINIMUM (-127)
+    8'h62: data <= 8'h25;     8'h63: data <= 8'h7f;    //     LOGICAL_MAXIMUM (127)
+    8'h64: data <= 8'h75;     8'h65: data <= 8'h08;    //     REPORT_SIZE (8)
+    8'h66: data <= 8'h95;     8'h67: data <= 8'h02;    //     REPORT_COUNT (2)
+    8'h68: data <= 8'h81;     8'h69: data <= 8'h06;    //     INPUT (Data,Var,Rel)
+    8'h6a: data <= 8'hc0;                              //END_COLLECTION
+    8'h6b: data <= 8'hc0;                              // END_COLLECTION
+
+// ZERO_ZERO
+    8'h6c: data <= 8'h00; 
+    8'h6d: data <= 8'h00; 
+// ONE_ZERO
+    8'h6e: data <= 8'h01; 
+    8'h6f: data <= 8'h00; 
+// Vendor data
+    8'h70: data <= 8'h00; 
+    8'h71: data <= 8'h00; 
+
+// =============================================
+// =====   Language ID Descriptor(String0) =====
+// =============================================
+    8'h80: data <= 8'h04;  // bLength
+    8'h81: data <= 8'h03;  // bDescriptorType = String Desc
+    8'h82: data <= 8'h09;  // wLangID (Lo) (Lang ID for English = 0x0409)
+    8'h83: data <= 8'h04;  // wLangID (Hi) (Lang ID for English = 0x0409)
+
+// ====================================
+// =====   string 1 Descriptor  =====
+// ====================================
+    8'h90: data <= 8'd26;  	// bLength
+    8'h91: data <= 8'h03;     // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'h92: data <= "B";  8'h93: data <= 8'h00;
+    8'h94: data <= "a";  8'h95: data <= 8'h00;
+    8'h96: data <= "s";  8'h97: data <= 8'h00;
+    8'h98: data <= "e";  8'h99: data <= 8'h00;
+    8'h9a: data <= "2";  8'h9b: data <= 8'h00;
+    8'h9c: data <= "D";  8'h9d: data <= 8'h00;
+    8'h9e: data <= "e";  8'h9f: data <= 8'h00;
+    8'ha0: data <= "s";  8'ha1: data <= 8'h00;
+    8'ha2: data <= "i";  8'ha3: data <= 8'h00;
+    8'ha4: data <= "g";  8'ha5: data <= 8'h00;
+    8'ha6: data <= "n";  8'ha7: data <= 8'h00;
+    8'ha8: data <= "s";  8'ha9: data <= 8'h00;
+
+
+
+// ====================================
+// =====   string 2 Descriptor  =====
+// ====================================
+	 8'hb0: data <= 8'd20;   // bLength
+    8'hb1: data <= 8'h03;   // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'hb2: data <= "B";  8'hb3: data <= 8'h00;
+    8'hb4: data <= "2";  8'hb5: data <= 8'h00;
+    8'hb6: data <= "D";  8'hb7: data <= 8'h00;
+    8'hb8: data <= " ";  8'hb9: data <= 8'h00;
+    8'hba: data <= "M";  8'hbb: data <= 8'h00;
+    8'hbc: data <= "o";  8'hbd: data <= 8'h00;
+    8'hbe: data <= "u";  8'hbf: data <= 8'h00;
+    8'hc0: data <= "s";  8'hc1: data <= 8'h00;
+    8'hc2: data <= "e";  8'hc3: data <= 8'h00;
+
+// ====================================
+// =====   string 3 Descriptor  =====
+// ====================================
+	 8'hd0: data <= 8'd30;   // bLength
+    8'hd1: data <= 8'h03;   // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'hd2: data <= "L";  8'hd3: data <= 8'h00;
+    8'hd4: data <= "i";  8'hd5: data <= 8'h00;
+    8'hd6: data <= "m";  8'hd7: data <= 8'h00;
+    8'hd8: data <= "i";  8'hd9: data <= 8'h00;
+    8'hda: data <= "t";  8'hdb: data <= 8'h00;
+    8'hdc: data <= "e";  8'hdd: data <= 8'h00;
+    8'hde: data <= "d";  8'hdf: data <= 8'h00;
+    8'he0: data <= "E";  8'he1: data <= 8'h00;
+    8'he2: data <= "d";  8'he3: data <= 8'h00;
+    8'he4: data <= "i";  8'he5: data <= 8'h00;
+    8'he6: data <= "t";  8'he7: data <= 8'h00;
+    8'he8: data <= "i";  8'he9: data <= 8'h00;
+    8'hea: data <= "o";  8'heb: data <= 8'h00;
+    8'hec: data <= "n";  8'hed: data <= 8'h00;
+
+
+
+    default: data <= 8'h00;
+  endcase
+end
+
+endmodule
+
+
+ 
Index: common/components/usbhostslave/trunk/usbDevice/bench/testHarness.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/bench/testHarness.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/bench/testHarness.v	(revision 264)
@@ -0,0 +1,155 @@
+`include "timescale.v"
+
+module testHarness(	);
+
+
+// -----------------------------------
+// Local Wires
+// -----------------------------------
+reg clk;
+reg rst;
+wire [8:0] adr;
+wire [7:0] masterDout;
+wire [7:0] masterDin;
+wire [7:0] usbSlaveDout;
+wire [7:0] usbHostDout;
+wire stb;
+wire we;
+wire ack;
+wire host_stb;
+wire DPlusPullup;
+wire DPlusPullDown;
+wire DMinusPullup;
+wire DMinusPulDown;
+reg USBWireVP;
+reg USBWireVM;
+wire [1:0] hostUSBWireDataIn;
+wire [1:0] hostUSBWireDataOut;
+wire hostUSBWireCtrlOut;
+wire usbSlaveOE_n;
+wire usbSlaveVP_out;
+wire usbSlaveVM_out;
+wire USBDMinusPullup;
+
+assign USBDMinusPullup = 1'b0;
+
+initial begin
+$dumpfile("wave.vcd");
+$dumpvars(0, testHarness); 
+end
+
+pullup(DPlusPullup);
+pulldown(DPlusPullDown);
+pullup(DMinusPullup);
+pulldown(DMinusPullDown);
+
+assign hostUSBWireDataIn = {USBWireVP, USBWireVM};
+always @(*) begin
+  if (hostUSBWireCtrlOut == 1'b1 && usbSlaveOE_n == 1'b1)
+    {USBWireVP, USBWireVM} <= hostUSBWireDataOut;
+  else if (hostUSBWireCtrlOut == 1'b0 && usbSlaveOE_n == 1'b0)
+    {USBWireVP, USBWireVM} <= {usbSlaveVP_out, usbSlaveVM_out};
+  else if (hostUSBWireCtrlOut == 1'b1 && usbSlaveOE_n == 1'b0)
+    {USBWireVP, USBWireVM} <= 2'bxx;
+  else if (hostUSBWireCtrlOut == 1'b0 && usbSlaveOE_n == 1'b1) begin
+    if (USBDPlusPullup == 1'b1)
+      USBWireVP <= DPlusPullup;
+    else
+      USBWireVP <= DPlusPullDown;
+    if (USBDMinusPullup == 1'b1)
+      USBWireVM <= DMinusPullup;
+    else
+      USBWireVM <= DMinusPullDown;
+  end
+end
+
+assign host_stb = stb;
+assign masterDin = usbHostDout;
+
+//Parameters declaration: 
+defparam u_usbHost.HOST_FIFO_DEPTH = 64;
+parameter HOST_FIFO_DEPTH = 64;
+defparam u_usbHost.HOST_FIFO_ADDR_WIDTH = 6;
+parameter HOST_FIFO_ADDR_WIDTH = 6;
+usbHost u_usbHost (
+  .clk_i(clk),
+  .rst_i(rst),
+  .address_i(adr[7:0]),
+  .data_i(masterDout),
+  .data_o(usbHostDout),
+  .we_i(we),
+  .strobe_i(host_stb),
+  .ack_o(ack),
+  .usbClk(clk),
+  .hostSOFSentIntOut(hostSOFSentIntOut),
+  .hostConnEventIntOut(hostConnEventIntOut),
+  .hostResumeIntOut(hostResumeIntOut),
+  .hostTransDoneIntOut(hostTransDoneIntOut),
+  .USBWireDataIn(hostUSBWireDataIn),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOut(hostUSBWireDataOut),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(hostUSBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed)
+);
+
+usbDevice u_usbDevice (
+  .clk(clk),
+  .rst(rst),
+  .usbSlaveVP_in(USBWireVP),
+  .usbSlaveVM_in(USBWireVM),
+  .usbSlaveVP_out(usbSlaveVP_out),
+  .usbSlaveVM_out(usbSlaveVM_out),
+  .usbSlaveOE_n(usbSlaveOE_n),
+  .usbDPlusPullup(USBDPlusPullup),
+  .vBusDetect(1'b1)
+);
+
+
+wb_master_model #(.dwidth(8), .awidth(9)) u_wb_master_model (
+  .clk(clk), 
+  .rst(rst), 
+  .adr(adr), 
+  .din(masterDin), 
+  .dout(masterDout), 
+  .cyc(), 
+  .stb(stb), 
+  .we(we), 
+  .sel(), 
+  .ack(ack), 
+  .err(1'b0), 
+  .rty(1'b0)
+);
+
+
+//--------------- reset ---------------
+initial begin
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  @(posedge clk);
+  rst <= 1'b1;
+  @(posedge clk);
+  rst <= 1'b0;
+  @(posedge clk);
+end
+ 
+// ******************************  Clock section  ******************************
+`define CLK_50MHZ_HALF_PERIOD 10
+`define CLK_25MHZ_HALF_PERIOD 20
+
+always begin
+  #`CLK_25MHZ_HALF_PERIOD clk <= 1'b0;
+  #`CLK_25MHZ_HALF_PERIOD clk <= 1'b1;
+end
+
+
+
+
+
+endmodule
+
Index: common/components/usbhostslave/trunk/doc/USBHostSlave_IPCore_Specification.pdf
===================================================================
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+*
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Index: common/components/usbhostslave/trunk/sim/build_icarus_comboHostSlave.bat
===================================================================
--- common/components/usbhostslave/trunk/sim/build_icarus_comboHostSlave.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/sim/build_icarus_comboHostSlave.bat	(revision 264)
@@ -0,0 +1,4 @@
+iverilog  -o testHarness -cfilelistComboHostSlave.icarus
+
+pause
+
Index: common/components/usbhostslave/trunk/sim/gtkwave.ini
===================================================================
--- common/components/usbhostslave/trunk/sim/gtkwave.ini	(nonexistent)
+++ common/components/usbhostslave/trunk/sim/gtkwave.ini	(revision 264)
@@ -0,0 +1,50 @@
+#
+# sample rc file
+#
+hier_max_level 1
+force_toolbars 0
+
+dynamic_resizing 1
+hpane_pack 1
+use_vcd 0
+#initial_window_x 700
+#initial_window_y 400
+use_maxtime_display 0
+
+enable_vcd_autosave 0
+use_roundcaps 1
+
+use_nonprop_fonts yes
+enable_horiz_grid yes
+use_big_fonts no
+constant_marker_update yes
+show_grid yes
+show_base_symbols no
+use_roundcaps yes
+
+atomic_vectors yes
+vcd_explicit_zero_subscripts no
+
+#
+# color additions
+#
+color_back   000000
+color_grid   202070
+color_high   00ff00
+color_low    008000
+color_trans  00c000
+color_mid    c0c000
+
+color_value  ffffff
+color_vbox   00ff00
+color_vtrans 00c000
+
+color_x      00ff00
+color_xfill  004000
+
+color_umark  ff8080
+color_mark   ffff80
+
+color_time   ffffff
+color_timeb  000000
+
Index: common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbHostSlaveAvalonWrap.qsf
===================================================================
--- common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbHostSlaveAvalonWrap.qsf	(nonexistent)
+++ common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbHostSlaveAvalonWrap.qsf	(revision 264)
@@ -0,0 +1,84 @@
+# Copyright (C) 1991-2006 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		usbHostSlaveAvalonWrap_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name DEVICE EP1C4F400C7
+set_global_assignment -name TOP_LEVEL_ENTITY usbHostSlaveAvalonWrap
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:38:48  OCTOBER 06, 2006"
+set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1"
+set_global_assignment -name VERILOG_FILE src/writeUSBWireData.v
+set_global_assignment -name VERILOG_FILE src/directcontrol.v
+set_global_assignment -name VERILOG_FILE src/dpMem_dc.v
+set_global_assignment -name VERILOG_FILE src/endpMux.v
+set_global_assignment -name VERILOG_FILE src/fifoMux.v
+set_global_assignment -name VERILOG_FILE src/fifoRTL.v
+set_global_assignment -name VERILOG_FILE src/getpacket.v
+set_global_assignment -name VERILOG_FILE src/hctxportarbiter.v
+set_global_assignment -name VERILOG_FILE src/hostcontroller.v
+set_global_assignment -name VERILOG_FILE src/hostSlaveMux.v
+set_global_assignment -name VERILOG_FILE src/hostSlaveMuxBI.v
+set_global_assignment -name VERILOG_FILE src/lineControlUpdate.v
+set_global_assignment -name VERILOG_FILE src/processRxBit.v
+set_global_assignment -name VERILOG_FILE src/processRxByte.v
+set_global_assignment -name VERILOG_FILE src/processTxByte.v
+set_global_assignment -name VERILOG_FILE src/readUSBWireData.v
+set_global_assignment -name VERILOG_FILE src/RxFifo.v
+set_global_assignment -name VERILOG_FILE src/RxFifoBI.v
+set_global_assignment -name VERILOG_FILE src/rxStatusMonitor.v
+set_global_assignment -name VERILOG_FILE src/sctxportarbiter.v
+set_global_assignment -name VERILOG_FILE src/sendpacket.v
+set_global_assignment -name VERILOG_FILE src/sendpacketarbiter.v
+set_global_assignment -name VERILOG_FILE src/sendpacketcheckpreamble.v
+set_global_assignment -name VERILOG_FILE src/siereceiver.v
+set_global_assignment -name VERILOG_FILE src/SIETransmitter.v
+set_global_assignment -name VERILOG_FILE src/slavecontroller.v
+set_global_assignment -name VERILOG_FILE src/slaveDirectcontrol.v
+set_global_assignment -name VERILOG_FILE src/slaveGetpacket.v
+set_global_assignment -name VERILOG_FILE src/slaveRxStatusMonitor.v
+set_global_assignment -name VERILOG_FILE src/slaveSendpacket.v
+set_global_assignment -name VERILOG_FILE src/sofcontroller.v
+set_global_assignment -name VERILOG_FILE src/softransmit.v
+set_global_assignment -name VERILOG_FILE src/speedCtrlMux.v
+set_global_assignment -name VERILOG_FILE src/timescale.v
+set_global_assignment -name VERILOG_FILE src/TxFifo.v
+set_global_assignment -name VERILOG_FILE src/TxFifoBI.v
+set_global_assignment -name VERILOG_FILE src/updateCRC5.v
+set_global_assignment -name VERILOG_FILE src/updateCRC16.v
+set_global_assignment -name VERILOG_FILE src/usbConstants_h.v
+set_global_assignment -name VERILOG_FILE src/usbHostControl.v
+set_global_assignment -name VERILOG_FILE src/usbHostControl_h.v
+set_global_assignment -name VERILOG_FILE src/USBHostControlBI.v
+set_global_assignment -name VERILOG_FILE src/usbHostSlave.v
+set_global_assignment -name VERILOG_FILE src/usbHostSlave_h.v
+set_global_assignment -name VERILOG_FILE src/usbHostSlaveAvalonWrap.v
+set_global_assignment -name VERILOG_FILE src/usbSerialInterfaceEngine.v
+set_global_assignment -name VERILOG_FILE src/usbSerialInterfaceEngine_h.v
+set_global_assignment -name VERILOG_FILE src/usbSlaveControl.v
+set_global_assignment -name VERILOG_FILE src/usbSlaveControl_h.v
+set_global_assignment -name VERILOG_FILE src/USBSlaveControlBI.v
+set_global_assignment -name VERILOG_FILE src/usbTxWireArbiter.v
+set_global_assignment -name VERILOG_FILE src/wishBoneBI.v
+set_global_assignment -name VERILOG_FILE src/wishBoneBus_h.v
\ No newline at end of file
Index: common/components/usbhostslave/trunk/syn/Makefile
===================================================================
--- common/components/usbhostslave/trunk/syn/Makefile	(nonexistent)
+++ common/components/usbhostslave/trunk/syn/Makefile	(revision 264)
@@ -0,0 +1,22 @@
+#copy master source files to a single directory. Makes it easier to build SOPC component
+
+CVS_DIR=../RTL
+SOPC_DIR=Altera/sopcCompProj/src
+
+all:
+	mkdir $(SOPC_DIR)
+	make copyRTLtoSOPC
+
+copyRTLtoSOPC:
+	cp -u -v -p $(CVS_DIR)/buffers/*.v $(SOPC_DIR)
+	cp -u -v -p $(CVS_DIR)/busInterface/*.v $(SOPC_DIR)
+	cp -u -v -p $(CVS_DIR)/hostController/*.v $(SOPC_DIR)
+	cp -u -v -p $(CVS_DIR)/hostSlaveMux/*.v $(SOPC_DIR)
+	cp -u -v -p $(CVS_DIR)/include/*.v $(SOPC_DIR)
+	cp -u -v -p $(CVS_DIR)/serialInterfaceEngine/*.v $(SOPC_DIR)
+	cp -u -v -p $(CVS_DIR)/slaveController/*.v $(SOPC_DIR)
+	cp -u -v -p $(CVS_DIR)/wrapper/*.v $(SOPC_DIR)
+
+
+
+
Index: common/components/usbhostslave/trunk/usbDevice/Aldec/design0/src/EP0.asf
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/Aldec/design0/src/EP0.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/Aldec/design0/src/EP0.asf	(revision 264)
@@ -0,0 +1,586 @@
+VERSION=1.15
+HEADER
+FILE="EP0.asf"
+FID=4788d213
+LANGUAGE=VERILOG
+ENTITY="EP0"
+FRAMES=ON
+FREEOID=1113
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// EP0.v                                                 ////\n////                                                              ////\n//// This file is part of the usbHostSlave opencores effort.\n//// <http://www.opencores.org/cores//>                           ////\n////                                                              ////\n//// Module Description:                                          ////\n//// Implements EP0 control endpoint\n//// Responds to 8-byte SETUP packets\n//// of type GET_STATUS, GET_DESCRIPTOR and\n//// SET_ADDRESS\n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from <http://www.opencores.org/lgpl.shtml>                   ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbHostSlaveReg_define.v\"\n`include \"usbDevice_define.v\"\n\n"
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1  "Arial" 0
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+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 829
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 718
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+INSTHEADER 720
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 0,0 10000,10000
+END
+OBJECTS
+S 831 721 151552 ELLIPSE "States" | 145680,171360 6500 6500
+L 830 831 0 TEXT "State Labels" | 145680,171360 1 0 0 "SET_ADDR\n/33/"
+S 829 721 147460 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 146040,194400 6500 6500
+L 828 829 0 TEXT "State Labels" | 146040,194400 1 0 0 "GET_DESC"
+S 827 721 143360 ELLIPSE "States" | 145320,213120 6500 6500
+L 826 827 0 TEXT "State Labels" | 145320,213120 1 0 0 "GET_STAT\n/32/"
+C 825 823 0 TEXT "Conditions" | 71092,83196 1 0 0 "wb_ack == 1'b1"
+A 824 823 16 TEXT "Actions" | 78820,70592 1 0 0 "wb_stb <= 1'b0;\nwValue[15:8] <= wb_data_i;"
+W 823 757 0 792 802 BEZIER "Transitions" | 65559,83939 72275,78603 83788,68016 90251,65831\
+                                           96714,63646 109134,65578 112653,75008 116172,84438\
+                                           117828,120226 118357,140857 118886,161488 122227,209160\
+                                           120341,226084 118456,243008 117042,237676 119071,252228\
+                                           121101,266780 129059,264211 135366,263925
+C 822 821 0 TEXT "Conditions" | 155548,85404 1 0 0 "wbBusGnt == 1'b0"
+W 821 757 0 820 761 BEZIER "Transitions" | 150160,89614 163592,76044 186060,47668 199492,34098
+S 820 757 139264 ELLIPSE "States" | 145888,94512 6500 6500
+L 819 820 0 TEXT "State Labels" | 145888,94512 1 0 0 "WT_UNGNT\n/31/"
+A 818 807 16 TEXT "Actions" | 146478,123188 1 0 0 "wb_stb <= 1'b0;\nwLength[15:8] <= wb_data_i;\nwbBusReq <= 1'b0;"
+C 817 807 0 TEXT "Conditions" | 144878,132753 1 0 0 "wb_ack == 1'b1"
+A 816 814 4 TEXT "Actions" | 155960,185231 1 0 0 "wb_stb <= 1'b1;"
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1  "Arial" 0 | 110650,276400 1 0 0 "Module: EP0"
+A 5 0 1 TEXT "Actions" | 30400,271392 1 0 0 "-- diagram ACTION"
+F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,212603
+L 7 6 0 TEXT "Labels" | 31673,209974 1 0 0 "EP0St"
+W 1089 485 0 1085 1095 BEZIER "Transitions" | 125212,139108 125596,133108 49427,119475 42131,114819
+C 1090 1089 0 TEXT "Conditions" | 115920,133773 1 0 0 "wb_ack == 1'b1"
+A 1091 1089 16 TEXT "Actions" | 76138,128516 1 0 0 "wb_stb <= 1'b0;"
+W 1092 485 0 508 515 BEZIER "Transitions" | 59048,201412 59144,196948 59459,190379 59555,185915
+C 1093 1092 0 TEXT "Conditions" | 58512,198480 1 0 0 "cnt == 8'hff"
+S 1095 485 229376 ELLIPSE "States" | 42368,108336 6500 6500
+A 1096 1095 4 TEXT "Actions" | 55936,113636 1 0 0 "wb_addr <= `RA_SC_LINE_STATUS_REG;\nwb_stb <= 1'b1;\nwb_we <= 1'b0;"
+L 1097 1095 0 TEXT "State Labels" | 42368,108336 1 0 0 "WT_CONN\n/46/"
+W 1098 485 0 1095 524 BEZIER "Transitions" | 46784,103569 58928,95505 79104,78768 92568,77568\
+                                             106032,76368 134712,86356 149496,92020
+C 1099 1098 0 TEXT "Conditions" | 42576,75984 1 0 0 "(wb_ack == 1'b1) && (wb_data_i[1:0] == `FULL_SPEED_CONNECT)"
+A 1101 1098 16 TEXT "Actions" | 62352,94128 1 0 0 "wb_stb <= 1'b0;"
+L 1102 1103 0 TEXT "State Labels" | 142449,164834 1 0 0 "DEL\n/47/"
+S 1103 443 233472 ELLIPSE "States" | 142449,164834 6500 6500
+C 833 832 0 TEXT "Conditions" | 88800,217260 1 0 0 "bRequest == `GET_STATUS"
+W 832 721 1 756 827 BEZIER "Transitions" | 76438,243508 76438,236758 76200,225270 77055,220995\
+                                           77910,216720 81330,213120 89430,212400 97530,211680\
+                                           124335,212512 138825,212872
+L 570 571 0 TEXT "Labels" | 77651,239593 1 0 0 "txDataSize[7:0]"
+I 571 0 130 Builtin Signal | 74651,239593 "" ""
+I 572 0 130 Builtin Signal | 74747,234627 "" ""
+L 573 572 0 TEXT "Labels" | 77747,234627 1 0 0 "txDataIndex[7:0]"
+A 1104 1103 4 TEXT "Actions" | 160690,166171 1 0 0 "memRdEn <= 1'b0;"
+W 1105 443 0 604 1103 BEZIER "Transitions" | 134066,177905 135641,175375 137374,172840 138949,170310
+W 1106 443 0 1103 607 BEZIER "Transitions" | 138698,159527 136693,156806 135613,154644 133608,151923
+L 1107 1108 0 TEXT "State Labels" | 152381,67042 1 0 0 "PTR_SET\n/48/"
+S 1108 721 237568 ELLIPSE "States" | 152381,67042 6500 6500
+A 1110 1108 4 TEXT "Actions" | 78942,102568 1 0 0 "if (txPacketRemSize > `MAX_RESP_SIZE) begin\n  txDataSize <= `MAX_RESP_SIZE;\n  txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;\nend\nelse begin\n  txDataSize <= txPacketRemSize;\n  txPacketRemSize <= 8'h00;\nend"
+W 1111 721 0 1108 725 BEZIER "Transitions" | 157931,63661 168818,58361 189435,47130 195069,43955\
+                                             200704,40780 200486,38998 200868,37948
+W 1112 721 0 963 1108 BEZIER "Transitions" | 177140,79165 171649,76444 163667,72705 158176,69984
+S 576 443 28676 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 67019,183707 3780 3780
+L 577 576 0 TEXT "State Labels" | 66785,183895 1 0 0 "J2"
+W 578 443 0 589 581 BEZIER "Transitions" | 50089,271133 53640,267847 58870,261756 62421,258470
+S 579 443 24576 ELLIPSE "States" | 66317,231102 6500 6500
+A 580 579 4 TEXT "Actions" | 78943,227786 1 0 0 "wb_addr <= `RA_EP0_TX_FIFO_CONTROL_REG;\nwb_data_o <= 8'h01; //force tx fifo empty\nwb_stb <= 1'b1;\nwb_we <= 1'b1;"
+S 581 443 20480 ELLIPSE "States" | 65707,252862 6500 6500
+L 582 581 0 TEXT "State Labels" | 65707,252862 1 0 0 "WT_GNT\n/5/"
+A 583 581 4 TEXT "Actions" | 83515,254558 1 0 0 "wbBusReq <= 1'b1;"
+W 585 443 1 576 604 BEZIER "Transitions" | 70798,183705 82453,183705 112107,183343 123816,183367
+C 587 585 0 TEXT "Conditions" | 76226,189478 1 0 0 "txDataSize != 8'h00"
+I 588 443 0 Builtin Exit | 202013,33571
+I 589 443 0 Builtin Entry | 46379,271133
+W 590 443 0 581 579 BEZIER "Transitions" | 65586,246409 65639,243865 65740,240120 65793,237576
+C 591 590 0 TEXT "Conditions" | 67827,244806 1 0 0 "wbBusGnt == 1'b1"
+H 599 576 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+L 595 579 0 TEXT "State Labels" | 66317,231102 1 0 0 "TX_EMPTY\n/6/"
+W 596 599 0 598 597 BEZIER "Transitions" | 100230,182880 105316,175905 109388,157925 120824,149056
+I 597 599 0 Builtin Exit | 123580,149056
+I 598 599 0 Builtin Entry | 96520,182880
+L 603 604 0 TEXT "State Labels" | 130314,183210 1 0 0 "RD_MEM\n/8/"
+S 604 443 36864 ELLIPSE "States" | 130314,183210 6500 6500
+A 605 604 4 TEXT "Actions" | 147534,185940 1 0 0 "memAddr <= txDataIndex;\nmemRdEn <= 1'b1;\ntxDataSize <= txDataSize - 1'b1;\ntxDataIndex <= txDataIndex + 1'b1;"
+L 606 607 0 TEXT "State Labels" | 131708,145710 1 0 0 "WR_TX_FIFO\n/7/"
+S 607 443 32768 ELLIPSE "States" | 131708,145710 6500 6500
+I 892 889 0 Builtin Entry | 38008,268256
+H 889 829 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 74 0 2 Builtin InPort | 195700,267632 "" ""
+L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst"
+I 72 0 3 Builtin InPort | 195700,272800 "" ""
+L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk"
+A 610 607 4 TEXT "Actions" | 144806,154759 1 0 0 "wb_data_o <= memData;\nwb_addr <= `RA_EP0_TX_FIFO_DATA_REG;\nwb_stb <= 1'b1;\nwb_we <= 1'b1;"
+L 611 612 0 TEXT "State Labels" | 133464,116430 1 0 0 "CHK_TX_DONE\n/9/"
+S 612 443 40960 ELLIPSE "States" | 133464,116430 6500 6500
+W 613 443 0 607 612 BEZIER "Transitions" | 131632,139220 131812,133487 132447,128407 132428,122842
+C 614 613 0 TEXT "Conditions" | 109920,137705 1 0 0 "wb_ack == 1'b1"
+A 615 613 16 TEXT "Actions" | 131042,132247 1 0 0 "wb_stb <= 1'b0;"
+S 616 443 45056 ELLIPSE "States" | 56781,109882 6500 6500
+A 617 616 4 TEXT "Actions" | 75530,105258 1 0 0 "wb_addr <= `RA_EP0_CONTROL_REG;\nif (dataSeq == 1'b1)\n  wb_data_o <= 8'h07; \nelse\n  wb_data_o <= 8'h03; \nwb_stb <= 1'b1;\nwb_we <= 1'b1;"
+L 618 616 0 TEXT "State Labels" | 56781,109882 1 0 0 "TRANS_GO\n/10/"
+W 619 443 0 616 627 BEZIER "Transitions" | 56746,103393 56799,100213 58679,65431 58646,61903
+A 620 619 16 TEXT "Actions" | 37650,86574 1 0 0 "wb_stb <= 1'b0;"
+C 621 619 0 TEXT "Conditions" | 34482,100249 1 0 0 "wb_ack == 1'b1"
+W 622 443 1 612 616 BEZIER "Transitions" | 127111,117802 118659,119219 102226,122363 93695,121890\
+                                           85164,121418 70939,115628 62329,113266
+C 623 622 0 TEXT "Conditions" | 87054,125880 1 0 0 "txDataSize == 8'h00"
+C 897 896 0 TEXT "Conditions" | 86815,197702 1 0 0 "bRequest == `GET_DESCRIPTOR"
+W 896 721 2 756 829 BEZIER "Transitions" | 76084,243537 76173,230972 75238,208651 75731,201965\
+                                           76224,195279 78020,193662 86501,193303 94982,192944\
+                                           123490,193875 139555,193964
+W 624 443 2 612 604 BEZIER "Transitions" | 128097,120095 118385,125397 100126,136538 95742,142837\
+                                           91359,149137 93249,163733 97764,168536 102279,173340\
+                                           116285,178270 124370,180580
+W 625 443 2 576 616 BEZIER "Transitions" | 66405,179981 64200,163339 59790,132966 57585,116324
+L 626 627 0 TEXT "State Labels" | 59948,55540 1 0 0 "WT_TRANS_DONE"
+S 627 443 49156 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 59948,55540 6500 6500
+S 100 6 196608 ELLIPSE "States" | 112176,193512 6500 6500
+L 99 100 0 TEXT "State Labels" | 112176,193512 1 0 0 "START\n/44/"
+H 650 627 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 653 650 0 Builtin Entry | 41566,267228
+I 654 650 0 Builtin Exit | 197817,37572
+C 389 388 0 TEXT "Conditions" | 60416,196339 1 0 0 "rst == 1'b1"
+W 388 6 0 387 100 BEZIER "Transitions" | 49555,202550 64193,201024 91216,196545 105854,195019
+I 387 6 0 Builtin Reset | 49555,202550
+W 657 443 0 627 588 BEZIER "Transitions" | 66297,56929 80114,57860 104701,61151 121933,57942\
+                                           139166,54734 178674,40919 199322,33571
+W 658 650 0 660 663 BEZIER "Transitions" | 80070,185399 80123,182855 80224,179110 80277,176566
+C 659 658 0 TEXT "Conditions" | 82311,183796 1 0 0 "wbBusGnt == 1'b1"
+S 660 650 53248 ELLIPSE "States" | 80191,191852 6500 6500
+A 661 660 4 TEXT "Actions" | 97999,193548 1 0 0 "wbBusReq <= 1'b1;"
+L 662 660 0 TEXT "State Labels" | 80191,191852 1 0 0 "WT_GNT\n/11/"
+S 663 650 57344 ELLIPSE "States" | 80801,170092 6500 6500
+A 664 663 4 TEXT "Actions" | 97363,177436 1 0 0 "wb_addr <= `RA_EP0_CONTROL_REG;\nwb_stb <= 1'b1;\nwb_we <= 1'b0;"
+L 665 663 0 TEXT "State Labels" | 80801,170092 1 0 0 "GET_RDY_STS\n/12/"
+W 666 650 0 663 671 BEZIER "Transitions" | 80766,163603 80819,160423 75553,87685 75520,84157
+A 667 666 16 TEXT "Actions" | 64401,127355 1 0 0 "wb_stb <= 1'b0;\ntransDone <= ~wb_data_i[`ENDPOINT_READY_BIT];"
+C 668 666 0 TEXT "Conditions" | 57855,156703 1 0 0 "wb_ack == 1'b1"
+L 670 671 0 TEXT "State Labels" | 74949,77688 1 0 0 "WT_UNGNT\n/13/"
+S 671 650 61440 ELLIPSE "States" | 74949,77688 6500 6500
+W 958 889 0 954 957 BEZIER "Transitions" | 96605,229505 96649,223961 97092,214792 97136,209248
+I 957 889 0 Builtin Exit | 97136,207312
+W 956 889 0 892 954 BEZIER "Transitions" | 38008,266320 37964,258576 37692,243392 38572,239036\
+                                           39452,234680 43060,232744 50100,232678 57140,232612\
+                                           78050,234430 90326,235266
+A 955 954 4 TEXT "Actions" | 134536,257560 1 0 0 "case (wValue[15:8])\n  `DEV_DESC: begin\n    txPacketRemSize <= `DEV_DESC_SIZE;\n    txDataIndex <= `DEV_DESC_INDEX;\n  end\n  `CFG_DESC: begin\n    txPacketRemSize <= `CFG_DESC_SIZE;\n    txDataIndex <= `CFG_DESC_INDEX;\n  end\n  `REP_DESC: begin\n    txPacketRemSize <= `REP_DESC_SIZE;\n    txDataIndex <= `REP_DESC_INDEX;\n  end\n  `STRING_DESC: begin\n    case (wValue[3:0])\n      4'h0: begin\n        txPacketRemSize <= `LANGID_DESC_SIZE;\n        txDataIndex <= `LANGID_DESC_INDEX;\n      end\n      4'h1: begin\n        txPacketRemSize <= `STRING1_DESC_SIZE;\n        txDataIndex <= `STRING1_DESC_INDEX;\n      end\n      4'h2: begin\n        txPacketRemSize <= `STRING2_DESC_SIZE;\n        txDataIndex <= `STRING2_DESC_INDEX;\n      end\n      4'h3: begin\n        txPacketRemSize <= `STRING3_DESC_SIZE;\n        txDataIndex <= `STRING3_DESC_INDEX;\n      end\n    endcase\n  end\nendcase"
+S 954 889 155648 ELLIPSE "States" | 96784,236000 6500 6500
+L 953 954 0 TEXT "State Labels" | 96784,236000 1 0 0 "S1\n/34/"
+A 952 827 4 TEXT "Actions" | 110300,270290 1 0 0 "if (bm_req_type == 2'b00)  begin\n  txPacketRemSize <= 8'h02;\n  if (bm_req_recp == 5'b00000)\n    txDataIndex <= `ONE_ZERO_STAT_INDEX;\n  else\n    txDataIndex <= `ZERO_ZERO_STAT_INDEX;\nend\nelse if (bm_req_type == 2'b10) begin\n  txDataIndex <= `VENDOR_DATA_STAT_INDEX;\n  txPacketRemSize <= 8'h02;\nend"
+C 951 950 0 TEXT "Conditions" | 85803,175564 1 0 0 "bRequest == `SET_ADDRESS"
+W 950 721 3 756 831 BEZIER "Transitions" | 76316,243513 76063,225937 74733,192802 75831,183169\
+                                           76930,173536 81832,170156 90112,169649 98393,169142\
+                                           125076,170390 139187,171066
+A 949 831 4 TEXT "Actions" | 51283,157308 1 0 0 "if ( (wValue[15:7] == {9{1'b0}}) && (wIndex == 16'h0000) && (wLength == 16'h0000) ) begin\n  USBAddress <= wValue[7:0];\n  updateUSBAddress <= 1'b1; \nend"
+C 687 686 0 TEXT "Conditions" | 70215,206772 1 0 0 "wb_ack == 1'b1"
+W 686 450 0 683 699 BEZIER "Transitions" | 67876,208091 68035,204540 69445,190397 69388,186682
+A 685 683 4 TEXT "Actions" | 81161,219883 1 0 0 "wb_addr <= `RA_EP0_STATUS_REG;\nwb_stb <= 1'b1;\nwb_we <= 1'b0;"
+L 684 683 0 TEXT "State Labels" | 67593,214583 1 0 0 "RD_STAT\n/15/"
+S 683 450 69632 ELLIPSE "States" | 67593,214583 6500 6500
+A 672 671 4 TEXT "Actions" | 93930,80240 1 0 0 "wbBusReq <= 1'b0;"
+L 674 675 0 TEXT "State Labels" | 75587,50892 1 0 0 "CHK_DONE\n/14/"
+S 675 650 65536 ELLIPSE "States" | 75587,50892 6500 6500
+W 676 650 0 671 675 BEZIER "Transitions" | 74787,71229 74866,66763 74949,61824 75028,57358
+C 677 676 0 TEXT "Conditions" | 74152,69075 1 0 0 "wbBusGnt == 1'b0"
+W 678 650 1 675 654 BEZIER "Transitions" | 82063,50346 110842,47087 166335,40831 195114,37572
+C 679 678 0 TEXT "Conditions" | 109319,51405 1 0 0 "transDone == 1'b1"
+W 680 650 0 653 660 BEZIER "Transitions" | 45528,267228 54483,249952 68565,215051 77520,197775
+A 681 680 16 TEXT "Actions" | 53844,248262 1 0 0 "transDone <= 1'b0;"
+I 974 970 0 Builtin Exit | 201084,36544
+I 973 970 0 Builtin Entry | 37640,268992
+H 970 718 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+W 969 721 4 756 725 BEZIER "Transitions" | 73449,244406 67774,232316 56014,209963 52272,201574\
+                                           48530,193185 44910,183808 44211,174637 43512,165467\
+                                           44335,138159 48529,122326 52724,106494 68681,70467\
+                                           82128,61502 95576,52537 133412,52702 146736,51838\
+                                           160060,50975 175524,47355 181240,45299 186956,43243\
+                                           194206,38246 197907,35943
+W 967 721 0 827 963 BEZIER "Transitions" | 151749,212167 162226,211177 181853,208830 188164,207345\
+                                           194475,205860 198765,201900 197857,186761 196950,171623\
+                                           188193,116474 184233,88177
+W 966 721 0 829 963 BEZIER "Transitions" | 152536,194612 160868,194447 175088,194475 180079,193650\
+                                           185070,192825 188370,189855 188535,176531 188700,163208\
+                                           185027,113403 183707,88241
+W 965 721 0 831 963 BEZIER "Transitions" | 152161,171855 160246,171030 175005,170715 179088,169106\
+                                           183172,167498 183338,162712 183090,152317 182843,141923\
+                                           183278,106650 182701,88253
+A 964 963 4 TEXT "Actions" | 132945,115035 1 0 0 "if (txPacketRemSize > wLength)\n  txPacketRemSize <= wLength;"
+S 963 721 159744 ELLIPSE "States" | 183090,81780 6500 6500
+L 962 963 0 TEXT "State Labels" | 183090,81780 1 0 0 "CHK_MAX_LEN\n/35/"
+W 703 450 0 705 711 BEZIER "Transitions" | 72094,140370 72253,136819 74502,121202 74445,117487
+A 702 697 16 TEXT "Actions" | 67545,166122 1 0 0 "wb_stb <= 1'b0;\nrxDataSize[15:8] <= wb_data_i;"
+L 701 699 0 TEXT "State Labels" | 69399,180714 1 0 0 "RD_RX_SIZE1\n/17/"
+A 700 699 4 TEXT "Actions" | 82967,186014 1 0 0 "wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_MSB;\nwb_stb <= 1'b1;\nwb_we <= 1'b0;"
+S 699 450 77824 ELLIPSE "States" | 69399,180714 6500 6500
+C 698 697 0 TEXT "Conditions" | 72107,172903 1 0 0 "wb_ack == 1'b1"
+W 697 450 0 699 705 BEZIER "Transitions" | 69682,174222 69841,170671 72070,157057 72013,153342
+C 696 695 0 TEXT "Conditions" | 66173,233440 1 0 0 "wbBusGnt == 1'b1"
+W 695 450 0 692 683 BEZIER "Transitions" | 66810,236404 66810,231900 67051,225557 67051,221053
+A 694 693 16 TEXT "Actions" | 51431,263561 1 0 0 "wbBusReq <= 1'b1;"
+W 693 450 0 453 692 BEZIER "Transitions" | 45899,268890 51404,263203 58036,254207 63541,248520
+S 692 450 73728 ELLIPSE "States" | 66810,242904 6500 6500
+L 691 692 0 TEXT "State Labels" | 66810,242904 1 0 0 "WT_GNT\n/16/"
+A 688 686 16 TEXT "Actions" | 65257,200004 1 0 0 "wb_stb <= 1'b0;\nepStatus <= wb_data_i;"
+L 991 992 0 TEXT "State Labels" | 38750,241828 1 0 0 "CHK_ACK\n/37/"
+C 990 985 0 TEXT "Conditions" | 70644,44491 1 0 0 "epTransType == `SC_OUTDATA_TRANS"
+C 989 984 0 TEXT "Conditions" | 70644,62738 1 0 0 "epTransType == `SC_IN_TRANS"
+W 988 6 5 435 433 BEZIER "Transitions" | 68713,91889 78159,90820 94604,86977 107197,87883\
+                                         119791,88790 151260,94359 158156,99797 165052,105236\
+                                         161166,121425 155533,127996 149900,134568 131252,144670\
+                                         121119,145414 110986,146159 89099,139036 82171,136155\
+                                         75244,133274 71271,130287 68358,128086
+C 987 986 0 TEXT "Conditions" | 80782,97297 1 0 0 "(epStatus & 8'h0f) != 8'h00"
+W 986 6 1 435 433 BEZIER "Transitions" | 69121,93300 85505,93256 116425,90863 126363,93355\
+                                         136302,95848 143296,105690 144040,109963 144785,114237\
+                                         140770,121489 138245,123528 135720,125568 129633,126475\
+                                         120536,126733 111439,126992 84705,125187 69554,125251
+W 985 6 4 435 720 BEZIER "Transitions" | 62339,87911 62513,76035 61993,54233 62811,47683\
+                                         63630,41133 66774,38251 76828,37956 86882,37661\
+                                         122506,38677 141042,39528
+W 984 6 3 435 718 BEZIER "Transitions" | 62077,87922 62307,80316 61927,67398 62942,63042\
+                                         63957,58687 67757,56329 77843,56001 87930,55674\
+                                         121635,57270 139909,57794
+I 981 977 0 Builtin Exit | 202766,35308
+I 980 977 0 Builtin Entry | 37800,268391
+L 979 978 0 TEXT "State Labels" | 38809,237911 1 0 0 "CHK_SEQ\n/36/"
+S 978 977 163840 ELLIPSE "States" | 38809,237911 6500 6500
+H 977 720 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+L 719 720 0 TEXT "State Labels" | 147541,39589 1 0 0 "OUT"
+S 718 6 212996 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 146393,58244 6500 6500
+L 717 718 0 TEXT "State Labels" | 146393,58244 1 0 0 "IN"
+S 716 6 208900 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 146967,76612 6500 6500
+L 715 716 0 TEXT "State Labels" | 146967,76612 1 0 0 "SETUP"
+C 714 709 0 TEXT "Conditions" | 77240,102705 1 0 0 "wb_ack == 1'b1"
+A 713 711 4 TEXT "Actions" | 88291,116308 1 0 0 "wb_addr <= `RA_EP0_TRANSTYPE_STATUS_REG;\nwb_stb <= 1'b1;\nwb_we <= 1'b0;"
+L 712 711 0 TEXT "State Labels" | 74723,111008 1 0 0 "RD_TRANS_TYPE\n/19/"
+S 711 450 86016 ELLIPSE "States" | 74723,111008 6500 6500
+A 710 709 16 TEXT "Actions" | 71433,90893 1 0 0 "wb_stb <= 1'b0;\nepTransType <= wb_data_i;"
+W 709 450 0 711 730 BEZIER "Transitions" | 75072,104520 75292,101661 75496,80446 76628,73323
+C 708 703 0 TEXT "Conditions" | 74502,138871 1 0 0 "wb_ack == 1'b1"
+A 707 705 4 TEXT "Actions" | 85379,152162 1 0 0 "wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_LSB;\nwb_stb <= 1'b1;\nwb_we <= 1'b0;"
+L 706 705 0 TEXT "State Labels" | 71811,146862 1 0 0 "RD_RX_SIZE2\n/18/"
+S 705 450 81920 ELLIPSE "States" | 71811,146862 6500 6500
+A 704 703 16 TEXT "Actions" | 69860,131262 1 0 0 "wb_stb <= 1'b0;\nrxDataSize[7:0] <= wb_data_i;"
+L 432 433 0 TEXT "State Labels" | 63138,124215 1 0 0 "DO_TRANS"
+S 433 6 204804 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 63138,124215 6500 6500
+L 434 435 0 TEXT "State Labels" | 62714,94389 1 0 0 "CHK_TRANS"
+S 435 6 200708 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 62714,94389 6500 6500
+H 443 433 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+A 1007 1005 4 TEXT "Actions" | 128957,247758 1 0 0 "wbBusReq <= 1'b1;\nupdateUSBAddress <= 1'b0;"
+L 1006 1005 0 TEXT "State Labels" | 111149,246062 1 0 0 "WT_GNT\n/40/"
+S 1005 970 180224 ELLIPSE "States" | 111149,246062 6500 6500
+A 1004 1003 4 TEXT "Actions" | 128321,231646 1 0 0 "wb_addr <= `RA_SC_ADDRESS;\nwb_data_o <= USBAddress; \nwb_stb <= 1'b1;\nwb_we <= 1'b1;"
+S 1003 970 176128 ELLIPSE "States" | 111759,224302 6500 6500
+A 1002 1000 4 TEXT "Actions" | 126800,110413 1 0 0 "if (txPacketRemSize > `MAX_RESP_SIZE) begin\n  txDataSize <= `MAX_RESP_SIZE;\n  txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;\nend\nelse begin\n  txDataSize <= txPacketRemSize;\n  txPacketRemSize <= 8'h00;\nend"
+S 1000 970 172032 ELLIPSE "States" | 108915,107493 6500 6500
+L 999 1000 0 TEXT "State Labels" | 108915,107493 1 0 0 "SET_PTR\n/38/"
+I 998 0 130 Builtin Signal | 74850,244256 "" ""
+L 997 998 0 TEXT "Labels" | 77850,244256 1 0 0 "txPacketRemSize[7:0]"
+C 996 994 0 TEXT "Conditions" | 62939,41019 1 0 0 "epStatus[`SC_ACK_RXED_BIT] != 1'b1"
+W 994 970 1 992 974 BEZIER "Transitions" | 38627,235330 37985,186795 36456,91449 37327,65989\
+                                           38199,40529 43009,35488 61615,34980 80221,34473\
+                                           159613,35810 198148,36544
+W 993 970 0 973 992 BEZIER "Transitions" | 37640,266790 37640,261010 37968,254059 37968,248279
+S 992 970 167936 ELLIPSE "States" | 38750,241828 6500 6500
+I 735 450 0 Builtin Exit | 78396,39528
+L 734 730 0 TEXT "State Labels" | 77721,66917 1 0 0 "WT_UNGNT\n/20/"
+C 733 732 0 TEXT "Conditions" | 77069,57247 1 0 0 "wbBusGnt == 1'b0"
+W 732 450 0 730 735 BEZIER "Transitions" | 77738,60732 77817,56266 78317,45963 78396,41497
+A 731 730 4 TEXT "Actions" | 96702,69469 1 0 0 "wbBusReq <= 1'b0;"
+S 730 450 90112 ELLIPSE "States" | 77721,66917 6500 6500
+C 729 728 0 TEXT "Conditions" | 69199,80672 1 0 0 "epTransType == `SC_SETUP_TRANS"
+W 728 6 2 435 716 BEZIER "Transitions" | 62421,87898 62634,84876 62733,80199 63665,78370\
+                                         64598,76541 68042,75248 74678,75140 81315,75033\
+                                         128875,76431 140471,76412
+I 725 721 0 Builtin Exit | 200868,35943
+I 724 721 0 Builtin Entry | 38956,269226
+H 721 716 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 720 6 217092 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 147541,39589 6500 6500
+H 450 435 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+I 453 450 0 Builtin Entry | 41986,268890
+W 459 6 0 433 435 BEZIER "Transitions" | 62976,117735 62976,112485 62852,106294 62762,100805
+S 1023 443 188416 ELLIPSE "States" | 134708,254716 6500 6500
+L 1022 1023 0 TEXT "State Labels" | 134708,254716 1 0 0 "RX_EMPTY\n/42/"
+W 1021 970 0 1000 974 BEZIER "Transitions" | 109274,101015 110184,89367 111582,68912 122911,60676\
+                                             134241,52441 176423,41367 198172,36544
+W 1020 970 3 992 1000 BEZIER "Transitions" | 41850,236116 57411,204357 90178,144921 105739,113162
+C 1019 1018 0 TEXT "Conditions" | 113493,176474 1 0 0 "wbBusGnt == 1'b0"
+W 1018 970 0 1017 1000 BEZIER "Transitions" | 112403,181095 111448,163714 110127,131350 109172,113969
+S 1017 970 184320 ELLIPSE "States" | 112674,187576 6500 6500
+L 1016 1017 0 TEXT "State Labels" | 112674,187576 1 0 0 "WT_UNGNT\n/41/"
+C 1015 1014 0 TEXT "Conditions" | 48469,252925 1 0 0 "updateUSBAddress == 1'b1"
+W 1014 970 2 992 1005 BEZIER "Transitions" | 44994,243632 60509,246544 87608,250662 104654,245830
+L 1013 1003 0 TEXT "State Labels" | 111759,224302 1 0 0 "SET_ADDR\n/39/"
+A 1012 1010 16 TEXT "Actions" | 98203,208853 1 0 0 "wb_stb <= 1'b0;\nwbBusReq <= 1'b0;"
+C 1011 1010 0 TEXT "Conditions" | 89366,216390 1 0 0 "wb_ack == 1'b1"
+W 1010 970 0 1003 1017 BEZIER "Transitions" | 111724,217813 111777,214633 112420,197589 112387,194061
+C 1009 1008 0 TEXT "Conditions" | 113269,238006 1 0 0 "wbBusGnt == 1'b1"
+W 1008 970 0 1005 1003 BEZIER "Transitions" | 111028,239609 111081,237065 111182,233320 111235,230776
+I 745 0 130 Builtin Signal | 74905,218191 "" ""
+L 744 745 0 TEXT "Labels" | 77521,217999 1 0 0 "rxDataSize[15:0]"
+I 743 0 130 Builtin Signal | 74936,222496 "" ""
+L 742 743 0 TEXT "Labels" | 77936,222496 1 0 0 "epStatus[7:0]"
+I 741 0 130 Builtin Signal | 74714,227615 "" ""
+L 740 741 0 TEXT "Labels" | 78098,227423 1 0 0 "epTransType[7:0]"
+S 737 721 94208 ELLIPSE "States" | 40282,250972 6500 6500
+L 736 737 0 TEXT "State Labels" | 40282,250972 1 0 0 "CHK_ERR\n/21/"
+I 471 0 130 Builtin OutPort | 120974,258272 "" ""
+L 472 471 0 TEXT "Labels" | 126974,258272 1 0 0 "wb_addr[7:0]"
+I 473 0 2 Builtin OutPort | 121470,234129 "" ""
+L 474 473 0 TEXT "Labels" | 127470,234129 1 0 0 "wb_we"
+I 475 0 2 Builtin OutPort | 121470,239089 "" ""
+L 476 475 0 TEXT "Labels" | 127470,239089 1 0 0 "wb_stb"
+I 477 0 130 Builtin OutPort | 121232,248761 "" ""
+L 478 477 0 TEXT "Labels" | 127232,248761 1 0 0 "wb_data_o[7:0]"
+I 479 0 130 Builtin InPort | 123454,253473 "" ""
+W 1038 6 0 720 433 BEZIER "Transitions" | 151135,45004 155102,52249 162483,64635 166392,74065\
+                                          170302,83495 178008,106725 179186,115810 180365,124895\
+                                          177375,138005 173637,142777 169900,147550 157940,153530\
+                                          151960,155628 145980,157727 134020,160143 127752,160516\
+                                          121485,160890 108375,159970 101791,158619 95208,157268\
+                                          81982,152782 77382,150885 72783,148988 67607,145882\
+                                          66112,143180 64618,140478 64050,134541 63648,130689
+W 1037 6 0 718 433 BEZIER "Transitions" | 150688,63120 155058,71055 164610,84875 167542,91343\
+                                          170475,97812 173465,107818 173752,113539 174040,119260\
+                                          172200,132140 168232,137430 164265,142720 150235,151000\
+                                          142731,153328 135228,155657 119242,156693 111940,156060\
+                                          104638,155428 91412,151862 85806,150022 80200,148183\
+                                          71000,144387 68441,141886 65883,139385 64872,133700\
+                                          64355,130595
+W 1036 6 0 716 433 BEZIER "Transitions" | 151320,81438 156092,86728 164898,96490 166766,103016\
+                                          168635,109542 166565,125068 162482,131651 158400,138235\
+                                          144140,149045 136464,151287 128788,153530 112342,151690\
+                                          104292,150051 96243,148413 80487,143697 75600,140995\
+                                          70713,138293 67816,133136 65919,130089
+A 1035 1034 16 TEXT "Actions" | 80424,187044 1 0 0 "dataSeq <= ~dataSeq;"
+W 1034 977 2 978 981 BEZIER "Transitions" | 42955,232907 83215,182582 159578,85633 199838,35308
+C 1033 1032 0 TEXT "Conditions" | 57366,41559 1 0 0 "epStatus[`SC_DATA_SEQUENCE_BIT] != dataSeq"
+W 1032 977 1 978 981 BEZIER "Transitions" | 38745,231423 38287,184264 37373,91174 37832,66585\
+                                            38291,41997 41044,37959 61641,36858 82239,35758\
+                                            160011,35491 199830,35308
+W 1031 977 0 980 978 BEZIER "Transitions" | 37800,266189 37891,260042 38628,250536 38719,244389
+A 1030 1028 16 TEXT "Actions" | 158488,238316 1 0 0 "wb_stb <= 1'b0;"
+C 1029 1028 0 TEXT "Conditions" | 145614,251518 1 0 0 "wb_ack == 1'b1"
+W 1028 443 0 1023 576 BEZIER "Transitions" | 139970,250901 147637,245530 161973,235323 166319,229419\
+                                             170665,223515 172715,210641 168533,207443 164351,204245\
+                                             145573,204327 132535,204306 119497,204286 86123,204122\
+                                             77574,203220 69026,202318 68206,198874 67898,196639\
+                                             67591,194405 67341,190212 67136,187465
+A 1027 1024 16 TEXT "Actions" | 106992,243728 1 0 0 "wb_stb <= 1'b0;"
+C 1026 1024 0 TEXT "Conditions" | 82966,232330 1 0 0 "wb_ack == 1'b1"
+A 1025 1023 4 TEXT "Actions" | 134708,273248 1 0 0 "wb_addr <= `RA_EP0_RX_FIFO_CONTROL_REG;\nwb_data_o <= 8'h01; //force rx fifo empty\nwb_stb <= 1'b1;\nwb_we <= 1'b1;"
+W 1024 443 0 579 1023 BEZIER "Transitions" | 72756,231983 81981,232721 99735,234626 105454,239197\
+                                             111174,243769 115602,260579 118287,264863 120973,269148\
+                                             127287,269476 129111,268287 130936,267098 131897,263328\
+                                             132389,260786
+A 767 765 4 TEXT "Actions" | 70225,209519 1 0 0 "wb_stb <= 1'b1;"
+L 766 765 0 TEXT "State Labels" | 56657,204219 1 0 0 "DAT1\n/22/"
+S 765 757 102400 ELLIPSE "States" | 56657,204219 6500 6500
+W 764 721 2 737 756 BEZIER "Transitions" | 46780,251089 53551,251180 63542,250698 70313,250789
+I 761 757 0 Builtin Exit | 202344,34098
+I 760 757 0 Builtin Entry | 38956,270702
+H 757 756 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 756 721 98308 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 76764,249996 6500 6500
+L 755 756 0 TEXT "State Labels" | 76764,249996 1 0 0 "GET_DATA"
+C 754 753 0 TEXT "Conditions" | 58464,41925 1 0 0 "rxDataSize != 16'h0008"
+W 753 721 1 737 725 BEZIER "Transitions" | 40052,244483 39320,194524 36870,96093 36824,69741\
+                                           36778,43389 38060,37899 58464,36663 78868,35428\
+                                           157772,35669 197940,35943
+W 752 721 0 724 737 BEZIER "Transitions" | 38956,267030 39047,264377 39176,260043 39267,257390
+L 480 479 0 TEXT "Labels" | 129454,253473 1 0 0 "wb_data_i[7:0]"
+I 481 0 2 Builtin InPort | 123702,243801 "" ""
+L 482 481 0 TEXT "Labels" | 129702,243801 1 0 0 "wb_ack"
+L 483 484 0 TEXT "State Labels" | 46548,147798 1 0 0 "INIT"
+S 484 6 221188 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 46548,147798 6500 6500
+H 485 484 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400
+S 486 485 0 ELLIPSE "States" | 58746,236352 6500 6500
+L 487 486 0 TEXT "State Labels" | 58746,236352 1 0 0 "RST\n/0/"
+I 488 485 0 Builtin Entry | 38008,268952
+I 489 485 0 Builtin Exit | 156088,64010
+L 494 495 0 TEXT "Labels" | 94710,263444 1 0 0 "initComplete"
+I 495 0 2 Builtin OutPort | 88710,263444 "" ""
+I 1051 0 130 Builtin Signal | 121948,219040 "" ""
+L 1050 1051 0 TEXT "Labels" | 124948,219040 1 0 0 "cnt[7:0]"
+A 1049 1043 4 TEXT "Actions" | 45197,183834 1 0 0 "cnt <= cnt + 1'b1;"
+C 1048 1047 0 TEXT "Conditions" | 34477,205359 1 0 0 "cnt == `ONE_USEC_DEL"
+W 1047 650 0 1043 660 BEZIER "Transitions" | 43925,196399 47927,198791 53798,199463 57386,199578\
+                                             60974,199693 71650,197679 74824,195517
+A 1046 1045 16 TEXT "Actions" | 41999,121018 1 0 0 "cnt <= 8'h00;"
+W 1045 650 2 675 1043 BEZIER "Transitions" | 72197,56437 63273,75619 43922,112763 40242,129369\
+                                             36562,145975 36145,172368 37709,186398
+L 1044 1043 0 TEXT "State Labels" | 38481,192850 1 0 0 "DEL\n/43/"
+S 1043 650 192512 ELLIPSE "States" | 38481,192850 6500 6500
+W 783 757 0 786 792 BEZIER "Transitions" | 60573,120171 60732,116620 61546,98364 61489,94649
+C 782 780 0 TEXT "Conditions" | 60690,157992 1 0 0 "wb_ack == 1'b1"
+A 781 780 16 TEXT "Actions" | 62006,151938 1 0 0 "wb_stb <= 1'b0;\nbRequest = wb_data_i;"
+W 780 757 0 777 786 BEZIER "Transitions" | 58917,159547 59076,155996 60183,136852 60126,133137
+L 779 777 0 TEXT "State Labels" | 58634,166039 1 0 0 "DAT2\n/24/"
+A 778 777 4 TEXT "Actions" | 72202,171339 1 0 0 "wb_stb <= 1'b1;"
+S 777 757 110592 ELLIPSE "States" | 58634,166039 6500 6500
+C 776 775 0 TEXT "Conditions" | 54808,221840 1 0 0 "wbBusGnt == 1'b1"
+W 775 757 0 772 765 BEZIER "Transitions" | 56181,226593 56273,221349 56243,215939 56335,210695
+A 774 773 16 TEXT "Actions" | 44422,267415 1 0 0 "wbBusReq <= 1'b1;\ntxDataSize <= 8'h00; \ntxPacketRemSize <= 8'h00; //default tx packet size\ndataSeq <= 1'b1;\nwb_addr <= `RA_EP0_RX_FIFO_DATA_REG;\nwb_we <= 1'b0;"
+W 773 757 0 760 772 BEZIER "Transitions" | 43188,270702 46684,266746 51543,244896 53318,238645
+S 772 757 106496 ELLIPSE "States" | 56648,233064 6500 6500
+L 771 772 0 TEXT "State Labels" | 56648,233064 1 0 0 "WT_GNT\n/23/"
+A 770 768 16 TEXT "Actions" | 60029,189673 1 0 0 "wb_stb <= 1'b0;\nbm_req_dir <= wb_data_i[7]; \nbm_req_type <= wb_data_i[6:5]; \nbm_req_recp <= wb_data_i[4:0];"
+C 769 768 0 TEXT "Conditions" | 58713,196251 1 0 0 "wb_ack == 1'b1"
+W 768 757 0 765 777 BEZIER "Transitions" | 56940,197727 57099,194176 58282,176236 58225,172521
+L 496 497 0 TEXT "Labels" | 94710,259022 1 0 0 "wbBusReq"
+I 497 0 2 Builtin OutPort | 88710,259022 "" ""
+L 498 499 0 TEXT "Labels" | 96921,254399 1 0 0 "wbBusGnt"
+I 499 0 2 Builtin InPort | 90921,254399 "" ""
+A 500 486 4 TEXT "Actions" | 75308,243696 1 0 0 "wb_addr <= `RA_HOST_SLAVE_MODE;\nwb_data_o <= 8'h2; //reset usbHostSlave\nwb_stb <= 1'b1;\nwb_we <= 1'b1;"
+L 501 502 0 TEXT "State Labels" | 58136,258112 1 0 0 "WT_GNT\n/1/"
+S 502 485 4096 ELLIPSE "States" | 58136,258112 6500 6500
+A 504 502 4 TEXT "Actions" | 75944,259808 1 0 0 "wbBusReq <= 1'b1;"
+W 505 485 0 502 486 BEZIER "Transitions" | 58015,251659 58068,249115 58169,245370 58222,242826
+C 506 505 0 TEXT "Conditions" | 60256,250056 1 0 0 "wbBusGnt == 1'b1"
+L 507 508 0 TEXT "State Labels" | 58984,207868 1 0 0 "WT_RST\n/2/"
+S 508 485 8192 ELLIPSE "States" | 58984,207868 6500 6500
+W 509 485 0 486 508 BEZIER "Transitions" | 58314,229881 58367,226701 58553,217874 58520,214346
+C 510 509 0 TEXT "Conditions" | 35664,229916 1 0 0 "wb_ack == 1'b1"
+A 511 509 16 TEXT "Actions" | 35028,223980 1 0 0 "wb_stb <= 1'b0;\ncnt <= 8'h00;"
+W 1040 6 0 100 484 BEZIER "Transitions" | 106850,189787 92302,180454 66213,161139 51665,151806
+W 1041 6 0 484 433 BEZIER "Transitions" | 49584,142052 52512,138026 55866,133075 58794,129049
+A 1042 100 4 TEXT "Actions" | 169432,209270 1 0 0 "initComplete <= 1'b0;\nwbBusReq <= 1'b0;\nwb_addr <= 8'h00;\nwb_data_o <= 8'h00;\nwb_stb <= 1'b0;\nwb_we <= 1'b0;\ntxPacketRemSize <= 8'h00;\ntxDataSize <= 8'h00;\ntxDataIndex <= 8'h00;\nepTransType <= 8'h00;\nepStatus <= 8'h00;\nrxDataSize <= 16'h0000;\ncnt <= 8'h00;\nmemRdEn <= 1'b0;\nmemAddr <= 8'h00;\nupdateUSBAddress <= 1'b0;\ntransDone <= 1'b0;\nbm_req_type <= 2'b00;\nbm_req_dir <= 1'b0;\nbm_req_recp <= 5'b00000;\nbRequest <= 8'h00;\nwLength <= 16'h0000;\nwIndex <= 16'h0000;\nwValue <= 16'h0000;\ndataSeq <= 1'b0;\nUSBAddress <= 8'h00;"
+L 1052 1053 0 TEXT "Labels" | 167321,261694 1 0 0 "memRdEn"
+I 1053 0 2 Builtin OutPort | 161321,261694 "" ""
+L 1054 1055 0 TEXT "Labels" | 167321,256622 1 0 0 "memAddr[7:0]"
+I 1055 0 130 Builtin OutPort | 161321,256622 "" ""
+W 799 757 0 796 814 BEZIER "Transitions" | 140099,213919 140258,210368 142700,190140 142643,186425
+L 798 796 0 TEXT "State Labels" | 139816,220411 1 0 0 "DAT6\n/27/"
+A 797 796 4 TEXT "Actions" | 153384,225711 1 0 0 "wb_stb <= 1'b1;"
+S 796 757 122880 ELLIPSE "States" | 139816,220411 6500 6500
+W 795 757 0 802 796 BEZIER "Transitions" | 139731,252375 139890,248824 140629,230581 140572,226866
+A 794 792 4 TEXT "Actions" | 74226,93507 1 0 0 "wb_stb <= 1'b1;"
+L 793 792 0 TEXT "State Labels" | 60658,88207 1 0 0 "DAT4\n/26/"
+S 792 757 118784 ELLIPSE "States" | 60658,88207 6500 6500
+A 788 786 4 TEXT "Actions" | 73858,131963 1 0 0 "wb_stb <= 1'b1;"
+L 787 786 0 TEXT "State Labels" | 60290,126663 1 0 0 "DAT3\n/25/"
+S 786 757 114688 ELLIPSE "States" | 60290,126663 6500 6500
+A 785 783 16 TEXT "Actions" | 63662,112637 1 0 0 "wb_stb <= 1'b0;\nwValue[7:0] <= wb_data_i;"
+C 784 783 0 TEXT "Conditions" | 62346,118634 1 0 0 "wb_ack == 1'b1"
+W 512 485 0 488 502 BEZIER "Transitions" | 41718,268952 45852,267256 49710,264689 53844,262993
+A 513 508 4 TEXT "Actions" | 69172,209968 1 0 0 "cnt <= cnt + 1'b1;"
+L 514 515 0 TEXT "State Labels" | 60256,179460 1 0 0 "WT_VBUS\n/3/"
+S 515 485 12288 ELLIPSE "States" | 60256,179460 6500 6500
+A 518 515 4 TEXT "Actions" | 73824,187832 1 0 0 "wb_addr <= `RA_SC_LINE_STATUS_REG;\nwb_stb <= 1'b1;\nwb_we <= 1'b0;"
+W 521 485 0 515 1085 BEZIER "Transitions" | 59880,172978 59605,170845 120032,158243 121840,151345
+C 522 521 0 TEXT "Conditions" | 78034,171446 1 0 0 "(wb_ack == 1'b1)  && (wb_data_i[`VBUS_PRES_BIT] == 1'b1)"
+A 523 521 16 TEXT "Actions" | 94249,161439 1 0 0 "wb_stb <= 1'b0;"
+S 524 485 16384 ELLIPSE "States" | 155702,93951 6500 6500
+L 525 524 0 TEXT "State Labels" | 155702,93951 1 0 0 "FIN\n/4/"
+W 526 485 0 524 489 BEZIER "Transitions" | 155567,87487 155620,84307 156121,69428 156088,65900
+L 1056 1057 0 TEXT "Labels" | 169398,251734 1 0 0 "memData[7:0]"
+I 1057 0 130 Builtin InPort | 163398,251734 "" ""
+L 1058 1059 0 TEXT "Labels" | 124776,224384 1 0 0 "localRst"
+I 1059 0 2 Builtin Signal | 121776,224384 "" ""
+L 1060 1061 0 TEXT "Labels" | 178925,227382 1 0 0 "updateUSBAddress"
+I 1061 0 2 Builtin Signal | 175925,227382 "" ""
+L 1062 1063 0 TEXT "Labels" | 42640,237190 1 0 0 "transDone"
+I 1063 0 2 Builtin Signal | 39640,237190 "" ""
+L 1064 1065 0 TEXT "Labels" | 42692,231800 1 0 0 "bm_req_type[1:0]"
+I 1065 0 130 Builtin Signal | 39692,231800 "" ""
+L 1066 1067 0 TEXT "Labels" | 42874,227432 1 0 0 "bm_req_dir"
+I 1067 0 2 Builtin Signal | 39874,227432 "" ""
+L 1068 1069 0 TEXT "Labels" | 42692,222518 1 0 0 "bm_req_recp[4:0]"
+I 1069 0 130 Builtin Signal | 39692,222518 "" ""
+L 1070 1071 0 TEXT "Labels" | 43056,217786 1 0 0 "bRequest[7:0]"
+I 1071 0 130 Builtin Signal | 40056,217786 "" ""
+L 815 814 0 TEXT "State Labels" | 142392,179931 1 0 0 "DAT7\n/30/"
+S 814 757 135168 ELLIPSE "States" | 142392,179931 6500 6500
+A 813 811 16 TEXT "Actions" | 145555,165828 1 0 0 "wb_stb <= 1'b0;\nwLength[7:0] <= wb_data_i;"
+C 812 811 0 TEXT "Conditions" | 144402,171884 1 0 0 "wb_ack == 1'b1"
+W 811 757 0 814 808 BEZIER "Transitions" | 142675,173439 142834,169888 143227,151667 143170,147952
+A 810 808 4 TEXT "Actions" | 156328,146775 1 0 0 "wb_stb <= 1'b1;"
+L 809 808 0 TEXT "State Labels" | 142760,141475 1 0 0 "DAT8\n/29/"
+S 808 757 131072 ELLIPSE "States" | 142760,141475 6500 6500
+W 807 757 0 808 820 BEZIER "Transitions" | 143043,134983 143202,131432 145225,104683 145168,100968
+C 806 795 0 TEXT "Conditions" | 141488,250777 1 0 0 "wb_ack == 1'b1"
+A 805 795 16 TEXT "Actions" | 142751,244567 1 0 0 "wb_stb <= 1'b0;\nwIndex[7:0] <= wb_data_i;"
+L 804 802 0 TEXT "State Labels" | 139448,258867 1 0 0 "DAT5\n/28/"
+A 803 802 4 TEXT "Actions" | 153016,264167 1 0 0 "wb_stb <= 1'b1;"
+S 802 757 126976 ELLIPSE "States" | 139448,258867 6500 6500
+C 801 799 0 TEXT "Conditions" | 141997,212219 1 0 0 "wb_ack == 1'b1"
+A 800 799 16 TEXT "Actions" | 143749,205660 1 0 0 "wb_stb <= 1'b0;\nwIndex[15:8] <= wb_data_i;"
+A 535 524 4 TEXT "Actions" | 174518,95411 1 0 0 "wbBusReq <= 1'b0;\ninitComplete <= 1'b1;"
+C 536 526 0 TEXT "Conditions" | 155118,83142 1 0 0 "wbBusGnt == 1'b0"
+L 1072 1073 0 TEXT "Labels" | 148434,218150 1 0 0 "wValue[15:0]"
+I 1073 0 130 Builtin Signal | 145434,218150 "" ""
+L 1074 1075 0 TEXT "Labels" | 148616,222882 1 0 0 "wIndex[15:0]"
+I 1075 0 130 Builtin Signal | 145616,222882 "" ""
+L 1076 1077 0 TEXT "Labels" | 148616,228342 1 0 0 "wLength[15:0]"
+I 1077 0 130 Builtin Signal | 145616,228342 "" ""
+L 1078 1079 0 TEXT "Labels" | 148798,233074 1 0 0 "dataSeq"
+I 1079 0 2 Builtin Signal | 145798,233074 "" ""
+L 1080 1081 0 TEXT "Labels" | 178414,233058 1 0 0 "USBAddress[7:0]"
+I 1081 0 130 Builtin Signal | 175414,233058 "" ""
+L 1084 1085 0 TEXT "State Labels" | 125040,145776 1 0 0 "CONN\n/45/"
+S 1085 485 225280 ELLIPSE "States" | 124848,145584 6500 6500
+A 1086 1085 4 TEXT "Actions" | 142800,149040 1 0 0 "wb_addr <= `RA_SC_CONTROL_REG;\nwb_data_o <= 8'h71; //connect to host, full speed\nwb_stb <= 1'b1;\nwb_we <= 1'b1;"
+END
Index: common/components/usbhostslave/trunk/usbDevice/RTL/EP1Mouse.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/EP1Mouse.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/EP1Mouse.v	(revision 264)
@@ -0,0 +1,295 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// EP1Mouse.v                                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Implements EP1 as a IN endpoint
+//// simulating a mouse (a broken one) by 
+//// responding to IN requests with a constant (x,y) <= (1,1)
+//// which causes the mouse pointer to move from 
+//// top left to bottom right of the screen
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostSlaveReg_define.v"
+
+module EP1Mouse (clk, initComplete, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
+input   clk;
+input   initComplete;
+input   rst;
+input   wb_ack;
+input   [7:0]wb_data_i;
+input   wbBusGnt;
+output  [7:0]wb_addr;
+output  [7:0]wb_data_o;
+output  wb_stb;
+output  wb_we;
+output  wbBusReq;
+
+wire    clk;
+wire    initComplete;
+wire    rst;
+wire    wb_ack;
+reg     [7:0]wb_addr, next_wb_addr;
+wire    [7:0]wb_data_i;
+reg     [7:0]wb_data_o, next_wb_data_o;
+reg     wb_stb, next_wb_stb;
+reg     wb_we, next_wb_we;
+wire    wbBusGnt;
+reg     wbBusReq, next_wbBusReq;
+
+// diagram signals declarations
+reg  [7:0]cnt, next_cnt;
+reg dataSeq, next_dataSeq;
+reg localRst, next_localRst;
+reg transDone, next_transDone;
+
+// BINARY ENCODED state machine: EP1St
+// State codes definitions:
+`define DO_TRANS_WT_GNT 4'b0000
+`define DO_TRANS_TX_EMPTY 4'b0001
+`define DO_TRANS_WR_TX_FIFO1 4'b0010
+`define DO_TRANS_TRANS_GO 4'b0011
+`define DO_TRANS_WT_TRANS_DONE_WT_GNT 4'b0100
+`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 4'b0101
+`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 4'b0110
+`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 4'b0111
+`define START 4'b1000
+`define DO_TRANS_WR_TX_FIFO2 4'b1001
+`define DO_TRANS_WR_TX_FIFO3 4'b1010
+`define DO_TRANS_WT_TRANS_DONE_DEL 4'b1011
+
+reg [3:0]CurrState_EP1St, NextState_EP1St;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: EP1St
+
+// NextState logic (combinatorial)
+always @ (wbBusGnt or wb_ack or wb_data_i or transDone or initComplete or cnt or wbBusReq or wb_addr or wb_data_o or wb_stb or wb_we or dataSeq or CurrState_EP1St)
+begin
+  NextState_EP1St <= CurrState_EP1St;
+  // Set default values for outputs and signals
+  next_wbBusReq <= wbBusReq;
+  next_wb_addr <= wb_addr;
+  next_wb_data_o <= wb_data_o;
+  next_wb_stb <= wb_stb;
+  next_wb_we <= wb_we;
+  next_dataSeq <= dataSeq;
+  next_transDone <= transDone;
+  next_cnt <= cnt;
+  case (CurrState_EP1St)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_wbBusReq <= 1'b0;
+      next_wb_addr <= 8'h00;
+      next_wb_data_o <= 8'h00;
+      next_wb_stb <= 1'b0;
+      next_wb_we <= 1'b0;
+      next_cnt <= 8'h00;
+      next_dataSeq <= 1'b0;
+      next_transDone <= 1'b0;
+      if (initComplete == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_GNT;
+      end
+    end
+    `DO_TRANS_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_TX_EMPTY;
+      end
+    end
+    `DO_TRANS_TX_EMPTY:
+    begin
+      next_wb_addr <= `RA_EP1_TX_FIFO_CONTROL_REG;
+      next_wb_data_o <= 8'h01;
+      //force tx fifo empty
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO1;
+        next_wb_stb <= 1'b0;
+        next_wb_addr <= `RA_EP1_TX_FIFO_DATA_REG;
+        next_wb_we <= 1'b1;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO1:
+    begin
+      next_wb_data_o <= 8'h00;
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO2;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_TRANS_GO:
+    begin
+      next_wb_addr <= `RA_EP1_CONTROL_REG;
+      if (dataSeq == 1'b1)
+      next_wb_data_o <= 8'h07;
+      else
+      next_wb_data_o <= 8'h03;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+        next_wb_stb <= 1'b0;
+        if (dataSeq == 1'b1)
+        next_dataSeq <= 1'b0;
+        else
+        next_dataSeq <= 1'b1;
+        next_transDone <= 1'b0;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO2:
+    begin
+      next_wb_data_o <= 8'h01;
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO3;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO3:
+    begin
+      next_wb_data_o <= 8'h01;
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_TRANS_GO;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
+    begin
+      next_wb_addr <= `RA_EP1_CONTROL_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
+    begin
+      next_wbBusReq <= 1'b0;
+      if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_CHK_DONE:
+    begin
+      if (transDone == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_GNT;
+      end
+      else
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_DEL;
+        next_cnt <= 8'h00;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_DEL:
+    begin
+      next_cnt <= cnt + 1'b1;
+      if (cnt == `ONE_USEC_DEL)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+    CurrState_EP1St <= `START;
+  else
+    CurrState_EP1St <= NextState_EP1St;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    wbBusReq <= 1'b0;
+    wb_addr <= 8'h00;
+    wb_data_o <= 8'h00;
+    wb_stb <= 1'b0;
+    wb_we <= 1'b0;
+    dataSeq <= 1'b0;
+    transDone <= 1'b0;
+    cnt <= 8'h00;
+  end
+  else 
+  begin
+    wbBusReq <= next_wbBusReq;
+    wb_addr <= next_wb_addr;
+    wb_data_o <= next_wb_data_o;
+    wb_stb <= next_wb_stb;
+    wb_we <= next_wb_we;
+    dataSeq <= next_dataSeq;
+    transDone <= next_transDone;
+    cnt <= next_cnt;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceActelTop.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceActelTop.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceActelTop.v	(revision 264)
@@ -0,0 +1,88 @@
+
+module usbDeviceActelTop (
+
+  //
+  // Global signals
+  //
+  clk,
+  rst_n,
+
+  // eval board features
+  ledOut,
+
+  //
+  // USB
+  //
+  usbSlaveVP,
+  usbSlaveVM,
+  usbSlaveOE_n,
+  usbDPlusPullup
+
+);
+
+  //
+  // Global signals
+  //
+  input	clk;
+  input rst_n;
+
+  output [9:0] ledOut;
+
+  //
+  // USB
+  //
+  inout usbSlaveVP;
+  inout usbSlaveVM;
+  output usbSlaveOE_n;
+  output usbDPlusPullup;
+
+//local wires and regs
+reg [1:0] rstReg;
+wire rst;
+
+//generate sync reset
+always @(posedge clk) begin
+  rstReg[1:0] <= {rstReg[0], ~rst_n};
+end
+assign rst = rstReg[1];
+
+
+usbDevice u_usbDevice (
+  .clk(clk),
+  .rst(rst),
+  .usbSlaveVP_in(usbSlaveVP_in),
+  .usbSlaveVM_in(usbSlaveVM_in),
+  .usbSlaveVP_out(usbSlaveVP_out),
+  .usbSlaveVM_out(usbSlaveVM_out),
+  .usbSlaveOE_n(usbSlaveOE_n),
+  .usbDPlusPullup(usbDPlusPullup),
+  .vBusDetect(1'b1)
+);
+
+
+assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
+assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
+
+
+// comfort lights
+reg [9:0] ledCntReg;
+reg [21:0] cnt;
+
+assign ledOut = ledCntReg;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+    ledCntReg <= 10'b00_0000_0000;
+    cnt <= {22{1'b0}};
+  end
+  else begin
+    cnt <= cnt + 1'b1;
+    if (cnt == {22{1'b0}})
+      ledCntReg <= ledCntReg + 1'b1;
+  end
+end
+
+endmodule
+
+
Index: common/components/usbhostslave/trunk/usbDevice/RTL/usbHostSlaveReg_define.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/usbHostSlaveReg_define.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/usbHostSlaveReg_define.v	(revision 264)
@@ -0,0 +1,78 @@
+// ------------------------------ usbHostSlaveReg_define.v ----------------------------
+`include "wishBoneBus_h.v"
+`include "usbHostSlave_h.v"
+
+
+
+`define RA_EP0_CONTROL_REG              `SCREG_BASE+`ENDPOINT_CONTROL_REG
+`define RA_EP0_STATUS_REG               `SCREG_BASE+`ENDPOINT_STATUS_REG
+`define RA_EP0_TRANSTYPE_STATUS_REG     `SCREG_BASE+`ENDPOINT_TRANSTYPE_STATUS_REG
+`define RA_EP0_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NAK_TRANSTYPE_STATUS_REG
+`define RA_EP1_CONTROL_REG              `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_CONTROL_REG
+`define RA_EP1_STATUS_REG               `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_STATUS_REG
+`define RA_EP1_TRANSTYPE_STATUS_REG     `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_TRANSTYPE_STATUS_REG
+`define RA_EP1_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`NAK_TRANSTYPE_STATUS_REG
+`define RA_EP2_CONTROL_REG              `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_CONTROL_REG
+`define RA_EP2_STATUS_REG               `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_STATUS_REG
+`define RA_EP2_TRANSTYPE_STATUS_REG     `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)`+`ENDPOINT_TRANSTYPE_STATUS_REG
+`define RA_EP2_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`NAK_TRANSTYPE_STATUS_REG
+`define RA_EP3_CONTROL_REG              `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_CONTROL_REG
+`define RA_EP3_STATUS_REG               `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_STATUS_REG
+`define RA_EP3_TRANSTYPE_STATUS_REG     `SCREG_BASE+(NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_TRANSTYPE_STATUS_REG
+`define RA_EP3_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`NAK_TRANSTYPE_STATUS_REG
+`define RA_SC_CONTROL_REG               `SCREG_BASE+`SC_CONTROL_REG
+`define RA_SC_LINE_STATUS_REG           `SCREG_BASE+`SC_LINE_STATUS_REG
+`define RA_SC_INTERRUPT_STATUS_REG      `SCREG_BASE+`SC_INTERRUPT_STATUS_REG
+`define RA_SC_INTERRUPT_MASK_REG        `SCREG_BASE+`SC_INTERRUPT_MASK_REG
+`define RA_SC_ADDRESS                   `SCREG_BASE+`SC_ADDRESS
+`define RA_SC_FRAME_NUM_MSP             `SCREG_BASE+`SC_FRAME_NUM_MSP
+`define RA_SC_FRAME_NUM_LSP             `SCREG_BASE+`SC_FRAME_NUM_LSP
+
+`define RA_EP0_RX_FIFO_DATA_REG         `EP0_RX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP0_RX_FIFO_STATUS_REG       `EP0_RX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP0_RX_FIFO_DATA_COUNT_MSB   `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP0_RX_FIFO_DATA_COUNT_LSB   `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP0_RX_FIFO_CONTROL_REG      `EP0_RX_FIFO_BASE+`FIFO_CONTROL_REG
+`define RA_EP0_TX_FIFO_DATA_REG         `EP0_TX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP0_TX_FIFO_STATUS_REG       `EP0_TX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP0_TX_FIFO_DATA_COUNT_MSB   `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP0_TX_FIFO_DATA_COUNT_LSB   `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP0_TX_FIFO_CONTROL_REG      `EP0_TX_FIFO_BASE+`FIFO_CONTROL_REG
+
+`define RA_EP1_RX_FIFO_DATA_REG         `EP1_RX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP1_RX_FIFO_STATUS_REG       `EP1_RX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP1_RX_FIFO_DATA_COUNT_MSB   `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP1_RX_FIFO_DATA_COUNT_LSB   `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP1_RX_FIFO_CONTROL_REG      `EP1_RX_FIFO_BASE+`FIFO_CONTROL_REG
+`define RA_EP1_TX_FIFO_DATA_REG         `EP1_TX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP1_TX_FIFO_STATUS_REG       `EP1_TX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP1_TX_FIFO_DATA_COUNT_MSB   `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP1_TX_FIFO_DATA_COUNT_LSB   `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP1_TX_FIFO_CONTROL_REG      `EP1_TX_FIFO_BASE+`FIFO_CONTROL_REG
+
+`define RA_EP2_RX_FIFO_DATA_REG         `EP2_RX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP2_RX_FIFO_STATUS_REG       `EP2_RX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP2_RX_FIFO_DATA_COUNT_MSB   `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP2_RX_FIFO_DATA_COUNT_LSB   `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP2_RX_FIFO_CONTROL_REG      `EP2_RX_FIFO_BASE+`FIFO_CONTROL_REG
+`define RA_EP2_TX_FIFO_DATA_REG         `EP2_TX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP2_TX_FIFO_STATUS_REG       `EP2_TX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP2_TX_FIFO_DATA_COUNT_MSB   `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP2_TX_FIFO_DATA_COUNT_LSB   `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP2_TX_FIFO_CONTROL_REG      `EP2_TX_FIFO_BASE+`FIFO_CONTROL_REG
+
+`define RA_EP3_RX_FIFO_DATA_REG         `EP3_RX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP3_RX_FIFO_STATUS_REG       `EP3_RX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP3_RX_FIFO_DATA_COUNT_MSB   `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP3_RX_FIFO_DATA_COUNT_LSB   `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP3_RX_FIFO_CONTROL_REG      `EP3_RX_FIFO_BASE+`FIFO_CONTROL_REG
+`define RA_EP3_TX_FIFO_DATA_REG         `EP3_TX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP3_TX_FIFO_STATUS_REG       `EP3_TX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP3_TX_FIFO_DATA_COUNT_MSB   `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP3_TX_FIFO_DATA_COUNT_LSB   `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP3_TX_FIFO_CONTROL_REG      `EP3_TX_FIFO_BASE+`FIFO_CONTROL_REG
+
+`define RA_HOST_SLAVE_MODE              `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG
+`define RA_HOST_SLAVE_VERSION           `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG
+
+
Index: common/components/usbhostslave/trunk/usbDevice/bench/testCase0.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/bench/testCase0.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/bench/testCase0.v	(revision 264)
@@ -0,0 +1,329 @@
+// ---------------------------------- testcase0.v ----------------------------
+`include "timescale.v"
+`include "usbHostSlave_h.v"
+`include "usbHostControl_h.v"
+`include "usbHostSlaveTB_defines.v"
+
+module testCase0();
+
+reg ack;
+reg [7:0] data;
+reg [15:0] dataWord;
+reg [7:0] dataRead;
+reg [7:0] dataWrite;
+reg [7:0] USBAddress;
+reg [7:0] USBEndPoint;
+reg [7:0] transType;
+integer dataSize;
+integer i;
+integer j;
+reg bm_req_dir;
+reg [1:0] bm_req_type;
+reg [4:0] bm_req_recp;
+reg [7:0] bRequest;
+reg [15:0] wValue;
+reg [15:0] wIndex;
+reg [15:0] wLength;
+
+initial
+begin
+  $write("\n\n");
+  #1000;
+
+  testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG , dataRead);
+  $display("Host Version number = 0x%0x\n", dataRead);
+
+  $write("Testing host register read/write  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  $write("--- PASSED\n");
+
+  $write("Testing register reset  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG , 8'h2);
+  #1000;
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h00);
+  $write("--- PASSED\n");
+  #1000;
+
+  $write("Connect full speed  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  #40000;
+  //expecting full speed connect
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 6'h02);
+  $write("--- PASSED\n");
+
+
+  $write("Host forcing reset  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h1c);
+  #40000;
+  $write("--- PASSED\n");
+
+  $write("Connect full speed  ");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_LINE_CONTROL_REG , 8'h18);
+  #20000;
+  //expecting full speed connect
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_CONNECT_STATE_REG , 8'h02);
+  $write("--- PASSED\n");
+  #5000;
+
+  $write("Cancel interrupts  \n");
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h04);
+
+
+  // --- get status
+  $write("Trans test: Device address = 0x00, GET_STATUS. ");
+  USBAddress = 8'h00;
+  USBEndPoint = 8'h00;
+  transType = `SETUP_TRANS;
+  dataSize = 8;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  bm_req_dir = 1'b1;   // 0-Host to device; 1-device to host 
+  bm_req_type = 2'b00;  // 0-standard; 1-class; 2-vendor; 3-RESERVED
+  bm_req_recp = 5'b00000;   // 0-device; 1-interface; 2-endpoint; 3-other 4..31-reserved
+  bRequest =  `GET_STATUS; 
+  wValue = 16'h0000;
+  wIndex = 16'h0000;
+  wLength = 16'h0008;
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , {bm_req_dir, bm_req_type, bm_req_recp}); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , bRequest); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #100000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h40);
+  $write("--- PASSED\n");
+  $write("Trans test: Device address = 0x00, 3 byte IN transaction to Endpoint 0. ");
+  USBAddress = 8'h00;
+  USBEndPoint = 8'h00;
+  transType = `IN_TRANS;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #20000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h80);
+  $write("Checking receive data  ");
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_LSB , 2);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_MSB , 0);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 1);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 0);
+  $write("--- PASSED\n");
+
+
+
+
+
+
+
+
+
+  // --- set address
+  $write("Trans test: Device address = 0x00, SET_ADDRESS. ");
+  USBAddress = 8'h00;
+  USBEndPoint = 8'h00;
+  transType = `SETUP_TRANS;
+  dataSize = 8;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  bm_req_dir = 1'b1;   // 0-Host to device; 1-device to host 
+  bm_req_type = 2'b00;  // 0-standard; 1-class; 2-vendor; 3-RESERVED
+  bm_req_recp = 5'b00000;   // 0-device; 1-interface; 2-endpoint; 3-other 4..31-reserved
+  bRequest =  `SET_ADDRESS; 
+  wValue = 16'h0012; //set device address = 0x12
+  wIndex = 16'h0000;
+  wLength = 16'h0000;
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , {bm_req_dir, bm_req_type, bm_req_recp}); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , bRequest); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #100000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h40);
+  $write("--- PASSED\n");
+  $write("Trans test: Device address = 0x00, Sending IN so that USB address change will take effect. ");
+  USBAddress = 8'h00;
+  USBEndPoint = 8'h00;
+  transType = `IN_TRANS;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #20000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h80);
+  $write("Checking receive data is zero  ");
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_LSB , 0);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_MSB , 0);
+  $write("--- PASSED\n");
+
+
+
+  // --- get device descriptor
+  $write("Trans test: Device address = 0x12, get device descriptor. ");
+  USBAddress = 8'h012;
+  USBEndPoint = 8'h00;
+  transType = `SETUP_TRANS;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  bm_req_dir = 1'b1;   // 0-Host to device; 1-device to host 
+  bm_req_type = 2'b00;  // 0-standard; 1-class; 2-vendor; 3-RESERVED
+  bm_req_recp = 5'b00000;   // 0-device; 1-interface; 2-endpoint; 3-other 4..31-reserved
+  bRequest =  `GET_DESCRIPTOR; 
+  wValue = {`DEV_DESC, 8'h00};
+  wIndex = 16'h0000;
+  wLength = 16'h0040;
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , {bm_req_dir, bm_req_type, bm_req_recp}); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , bRequest); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #100000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h40);
+  $write("--- PASSED\n");
+  $write("Trans test: Device address = 0x12, 18 byte IN transaction to Endpoint 0. ");
+  USBAddress = 8'h12;
+  USBEndPoint = 8'h00;
+  transType = `IN_TRANS;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #100000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h80);
+  $write("Checking receive data  ");
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_LSB , 8'h12);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_MSB , 0);
+  for (i=0; i<18; i=i+1) begin
+    testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , dataRead);
+    $display("Data[0x%0x] = 0x%0x\n", i, dataRead);
+  end
+  $write("--- PASSED\n");
+
+
+
+
+
+
+  // --- get config descriptor
+  $write("Trans test: Device address = 0x12, get config descriptor. ");
+  USBAddress = 8'h012;
+  USBEndPoint = 8'h00;
+  transType = `SETUP_TRANS;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  bm_req_dir = 1'b1;   // 0-Host to device; 1-device to host 
+  bm_req_type = 2'b00;  // 0-standard; 1-class; 2-vendor; 3-RESERVED
+  bm_req_recp = 5'b00000;   // 0-device; 1-interface; 2-endpoint; 3-other 4..31-reserved
+  bRequest =  `GET_DESCRIPTOR; 
+  wValue = {`CFG_DESC, 8'h00};
+  wIndex = 16'h0000;
+  wLength = 16'h0009;
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , {bm_req_dir, bm_req_type, bm_req_recp}); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , bRequest); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wValue[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wIndex[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[7:0]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HOST_TX_FIFO_BASE + `FIFO_DATA_REG , wLength[15:8]); 
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #100000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h40);
+  $write("--- PASSED\n");
+  $write("Trans test: Device address = 0x12, 18 byte IN transaction to Endpoint 0. ");
+  USBAddress = 8'h12;
+  USBEndPoint = 8'h00;
+  transType = `IN_TRANS;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #100000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h80);
+  $write("Checking receive data  ");
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_LSB , 8'h09);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_COUNT_MSB , 0);
+  for (i=0; i<9; i=i+1) begin
+    testHarness.u_wb_master_model.wb_read(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , dataRead);
+    $display("Data[0x%0x] = 0x%0x\n", i, dataRead);
+  end
+  $write("--- PASSED\n");
+
+
+
+  // -- get mouse data from EP1
+  $write("Trans test: Device address = 0x12, 3 byte IN transaction to Endpoint 1. ");
+  USBAddress = 8'h12;
+  USBEndPoint = 8'h01;
+  transType = `IN_TRANS;
+  //enable endpoint, and make ready
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ADDR_REG , USBAddress);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_ENDP_REG , USBEndPoint);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_TRANS_TYPE_REG , transType);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`TX_CONTROL_REG , 8'h01);
+  #20000
+  //expecting transaction done interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01);
+  testHarness.u_wb_master_model.wb_write(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`INTERRUPT_STATUS_REG , 8'h01); //cancel interrupt
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HCREG_BASE+`RX_STATUS_REG , 8'h00);
+  $write("Checking receive data  ");
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 0);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 1);
+  testHarness.u_wb_master_model.wb_cmp(1, `SIM_HOST_BASE_ADDR + `HOST_RX_FIFO_BASE + `FIFO_DATA_REG , 1);
+  $write("--- PASSED\n");
+
+  $write("Finished all tests\n");
+  $stop;	
+
+end
+
+endmodule
+
Index: common/components/usbhostslave/trunk/usbDevice/progFiles/2008_08_22/download.bat
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/progFiles/2008_08_22/download.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/progFiles/2008_08_22/download.bat	(revision 264)
@@ -0,0 +1,3 @@
+fpgaConfig -i usbDeviceAlteraTop.rbf -r -a 0 -w -l
+pause
+
Index: common/components/usbhostslave/trunk/usbDevice/sim/run_icarus.bat
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/sim/run_icarus.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/sim/run_icarus.bat	(revision 264)
@@ -0,0 +1,2 @@
+vvp testHarness
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.ide_des
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.ide_des	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.ide_des	(revision 264)
@@ -0,0 +1,19 @@
+KEY IDE_DES_TOOL "Designer"
+KEY IDE_DES_FAMILY "IGLOO"
+KEY IDE_DES_DIE "IS6X6M2LP"
+KEY IDE_DES_PACKAGE "fg256"
+KEY IDE_DES_TOP_CELL_NAME "usbDeviceActelTop"
+KEY IDE_DES_KEEP_PHY_CONSTR "FALSE"
+KEY IDE_DES_KEEP_TIME_CONSTR "TRUE"
+KEY IDE_DES_LAYOUT_DONE "TRUE"
+KEY IDE_DES_BA_EXPORTED "FALSE"
+KEY IDE_DES_ERROR_FOUND "FALSE"
+KEY IDE_DES_ADB_PATH "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\designer\impl1\usbDeviceActelTop.adb"
+LIST SOURCE_FILES
+VALUE "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\synthesis\usbDeviceActelTop.edn;edn"
+VALUE "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\synthesis\usbDeviceActelTop_sdc.sdc;sdc"
+VALUE "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\constraint\usbDeviceActelTop.pdc;pdc"
+ENDLIST
+LIST OPTIONAL_FILES
+VALUE "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop\synthesis\usbDeviceActelTop_sdc.sdc;Used"
+ENDLIST
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/Copy of EP1Mouse.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/Copy of EP1Mouse.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/Copy of EP1Mouse.v	(revision 264)
@@ -0,0 +1,290 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// EP1Mouse.v                                                 ////
+////                                                              ////
+//// This file is part of the spiMaster opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized dual clock domain fifo. 
+////  fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostSlaveReg_define.v"
+
+module EP1Mouse (clk, initComplete, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
+input   clk;
+input   initComplete;
+input   rst;
+input   wb_ack;
+input   [7:0]wb_data_i;
+input   wbBusGnt;
+output  [7:0]wb_addr;
+output  [7:0]wb_data_o;
+output  wb_stb;
+output  wb_we;
+output  wbBusReq;
+
+wire    clk;
+wire    initComplete;
+wire    rst;
+wire    wb_ack;
+reg     [7:0]wb_addr, next_wb_addr;
+wire    [7:0]wb_data_i;
+reg     [7:0]wb_data_o, next_wb_data_o;
+reg     wb_stb, next_wb_stb;
+reg     wb_we, next_wb_we;
+wire    wbBusGnt;
+reg     wbBusReq, next_wbBusReq;
+
+// diagram signals declarations
+reg  [7:0]cnt, next_cnt;
+reg dataSeq, next_dataSeq;
+reg localRst, next_localRst;
+reg transDone, next_transDone;
+
+// BINARY ENCODED state machine: EP1St
+// State codes definitions:
+`define DO_TRANS_WT_GNT 4'b0000
+`define DO_TRANS_TX_EMPTY 4'b0001
+`define DO_TRANS_WR_TX_FIFO1 4'b0010
+`define DO_TRANS_TRANS_GO 4'b0011
+`define DO_TRANS_WT_TRANS_DONE_WT_GNT 4'b0100
+`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 4'b0101
+`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 4'b0110
+`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 4'b0111
+`define START 4'b1000
+`define DO_TRANS_WR_TX_FIFO2 4'b1001
+`define DO_TRANS_WR_TX_FIFO3 4'b1010
+`define DO_TRANS_WT_TRANS_DONE_DEL 4'b1011
+
+reg [3:0]CurrState_EP1St, NextState_EP1St;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: EP1St
+
+// NextState logic (combinatorial)
+always @ (wbBusGnt or wb_ack or wb_data_i or transDone or initComplete or cnt or wbBusReq or wb_addr or wb_data_o or wb_stb or wb_we or dataSeq or CurrState_EP1St)
+begin
+  NextState_EP1St <= CurrState_EP1St;
+  // Set default values for outputs and signals
+  next_wbBusReq <= wbBusReq;
+  next_wb_addr <= wb_addr;
+  next_wb_data_o <= wb_data_o;
+  next_wb_stb <= wb_stb;
+  next_wb_we <= wb_we;
+  next_transDone <= transDone;
+  next_cnt <= cnt;
+  next_dataSeq <= dataSeq;
+  case (CurrState_EP1St)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_wbBusReq <= 1'b0;
+      next_wb_addr <= 8'h00;
+      next_wb_data_o <= 8'h00;
+      next_wb_stb <= 1'b0;
+      next_wb_we <= 1'b0;
+      next_cnt <= 8'h00;
+      next_dataSeq <= 1'b0;
+      next_transDone <= 1'b0;
+      if (initComplete == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_GNT;
+      end
+    end
+    `DO_TRANS_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_TX_EMPTY;
+      end
+    end
+    `DO_TRANS_TX_EMPTY:
+    begin
+      next_wb_addr <= `RA_EP1_TX_FIFO_CONTROL_REG;
+      next_wb_data_o <= 8'h01;
+      //force tx fifo empty
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO1;
+        next_wb_stb <= 1'b0;
+        next_wb_addr <= `RA_EP1_TX_FIFO_DATA_REG;
+        next_wb_we <= 1'b1;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO1:
+    begin
+      next_wb_data_o <= 8'h00;
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO2;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_TRANS_GO:
+    begin
+      next_wb_addr <= `RA_EP1_CONTROL_REG;
+      if (dataSeq == 1'b1)
+      next_wb_data_o <= 8'h07;
+      else
+      next_wb_data_o <= 8'h03;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+        next_wb_stb <= 1'b0;
+        next_transDone <= 1'b0;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO2:
+    begin
+      next_wb_data_o <= 8'h01;
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO3;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO3:
+    begin
+      next_wb_data_o <= 8'h01;
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_TRANS_GO;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
+    begin
+      next_wb_addr <= `RA_EP1_CONTROL_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
+    begin
+      next_wbBusReq <= 1'b0;
+      if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_CHK_DONE:
+    begin
+      if (transDone == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_GNT;
+      end
+      else
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_DEL;
+        next_cnt <= 8'h00;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_DEL:
+    begin
+      next_cnt <= cnt + 1'b1;
+      if (cnt == `ONE_USEC_DEL)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+    CurrState_EP1St <= `START;
+  else
+    CurrState_EP1St <= NextState_EP1St;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    wbBusReq <= 1'b0;
+    wb_addr <= 8'h00;
+    wb_data_o <= 8'h00;
+    wb_stb <= 1'b0;
+    wb_we <= 1'b0;
+    transDone <= 1'b0;
+    cnt <= 8'h00;
+    dataSeq <= 1'b0;
+  end
+  else 
+  begin
+    wbBusReq <= next_wbBusReq;
+    wb_addr <= next_wb_addr;
+    wb_data_o <= next_wb_data_o;
+    wb_stb <= next_wb_stb;
+    wb_we <= next_wb_we;
+    transDone <= next_transDone;
+    cnt <= next_cnt;
+    dataSeq <= next_dataSeq;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifoBI.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifoBI.v	(revision 264)
@@ -0,0 +1,154 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "wishBoneBus_h.v"
+
+module RxfifoBI (
+  address, 
+  writeEn, 
+  strobe_i,
+  busClk, 
+  usbClk, 
+  rstSyncToBusClk, 
+  fifoSelect,
+  fifoDataIn,
+  busDataIn, 
+  busDataOut,
+  fifoREn,
+  forceEmptySyncToUsbClk,
+  forceEmptySyncToBusClk,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] fifoDataIn;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoREn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] fifoDataIn;
+wire [7:0] busDataIn; 
+reg [7:0] busDataOut;
+reg fifoREn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg forceEmptyReg;
+reg forceEmpty;
+reg forceEmptyToggle;
+reg [2:0] forceEmptyToggleSyncToUsbClk;
+
+//sync write
+always @(posedge busClk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+    address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+//detect rising edge of 'forceEmpty', and generate toggle signal
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) begin
+    forceEmptyReg <= 1'b0;
+    forceEmptyToggle <= 1'b0;
+  end
+  else begin
+    if (forceEmpty == 1'b1)
+      forceEmptyReg <= 1'b1;
+    else
+      forceEmptyReg <= 1'b0;
+    if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0)
+      forceEmptyToggle <= ~forceEmptyToggle;
+  end
+end
+assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0;
+
+
+// double sync across clock domains to generate 'forceEmptySyncToUsbClk'
+always @(posedge usbClk) begin
+    forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle};
+end
+assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1];
+
+// async read mux
+always @(address or fifoDataIn or numElementsInFifo)
+begin
+  case (address)
+      `FIFO_DATA_REG : busDataOut <= fifoDataIn;
+      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+      default: busDataOut <= 8'h00; 
+  endcase
+end
+
+//generate fifo read strobe
+always @(address or writeEn or strobe_i or fifoSelect) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b0 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoREn <= 1'b1;
+  else
+    fifoREn <= 1'b0;
+end
+
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/USBSlaveControlBI.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/USBSlaveControlBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/USBSlaveControlBI.v	(revision 264)
@@ -0,0 +1,714 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// USBSlaveControlBI.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////       
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSlaveControl_h.v"
+ 
+module USBSlaveControlBI (address, dataIn, dataOut, writeEn,
+  strobe_i,
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  SOFRxedIntOut, resetEventIntOut, resumeIntOut, transDoneIntOut, NAKSentIntOut, vBusDetIntOut,
+  endP0TransTypeReg, endP0NAKTransTypeReg,
+  endP1TransTypeReg, endP1NAKTransTypeReg,
+  endP2TransTypeReg, endP2NAKTransTypeReg,
+  endP3TransTypeReg, endP3NAKTransTypeReg,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  EP0StatusReg,
+  EP1StatusReg,
+  EP2StatusReg,
+  EP3StatusReg,
+  SCAddrReg, frameNum,
+  connectStateIn,
+  vBusDetectIn,
+  SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn,
+  slaveControlSelect,
+  clrEP0Ready, clrEP1Ready, clrEP2Ready, clrEP3Ready,
+  TxLineState,
+  LineDirectControlEn,
+  fullSpeedPol, 
+  fullSpeedRate,
+  connectSlaveToHost,
+  SCGlobalEn
+  );
+input [4:0] address;
+input [7:0] dataIn;
+input writeEn; 
+input strobe_i;
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+output [7:0] dataOut;
+output SOFRxedIntOut;
+output resetEventIntOut;
+output resumeIntOut;
+output transDoneIntOut;
+output NAKSentIntOut;
+output vBusDetIntOut;
+
+input [1:0] endP0TransTypeReg;
+input [1:0] endP0NAKTransTypeReg;
+input [1:0] endP1TransTypeReg; 
+input [1:0] endP1NAKTransTypeReg;
+input [1:0] endP2TransTypeReg; 
+input [1:0] endP2NAKTransTypeReg;
+input [1:0] endP3TransTypeReg; 
+input [1:0] endP3NAKTransTypeReg;
+output [4:0] endP0ControlReg;
+output [4:0] endP1ControlReg;
+output [4:0] endP2ControlReg;
+output [4:0] endP3ControlReg;
+input [7:0] EP0StatusReg;
+input [7:0] EP1StatusReg;
+input [7:0] EP2StatusReg;
+input [7:0] EP3StatusReg;
+output [6:0] SCAddrReg;
+input [10:0] frameNum;
+input [1:0] connectStateIn;
+input vBusDetectIn;
+input SOFRxedIn;
+input resetEventIn;
+input resumeIntIn;
+input transDoneIn;
+input NAKSentIn;
+input slaveControlSelect;
+input clrEP0Ready;
+input clrEP1Ready;
+input clrEP2Ready;
+input clrEP3Ready;
+output [1:0] TxLineState;
+output LineDirectControlEn;
+output fullSpeedPol; 
+output fullSpeedRate;
+output connectSlaveToHost;
+output SCGlobalEn;
+
+wire [4:0] address;
+wire [7:0] dataIn;
+wire writeEn;
+wire strobe_i;
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+reg [7:0] dataOut;
+
+reg SOFRxedIntOut;
+reg resetEventIntOut;
+reg resumeIntOut;
+reg transDoneIntOut;
+reg NAKSentIntOut;
+reg vBusDetIntOut;
+
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1TransTypeReg; 
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2TransTypeReg; 
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3TransTypeReg; 
+wire [1:0] endP3NAKTransTypeReg;
+reg [4:0] endP0ControlReg;
+reg [4:0] endP0ControlReg1;
+reg [4:0] endP1ControlReg;
+reg [4:0] endP1ControlReg1;
+reg [4:0] endP2ControlReg;
+reg [4:0] endP2ControlReg1;
+reg [4:0] endP3ControlReg;
+reg [4:0] endP3ControlReg1;
+wire [7:0] EP0StatusReg;
+wire [7:0] EP1StatusReg;
+wire [7:0] EP2StatusReg;
+wire [7:0] EP3StatusReg;
+reg [6:0] SCAddrReg;
+reg [3:0] TxEndPReg;
+wire [10:0] frameNum;
+wire [1:0] connectStateIn;
+
+wire SOFRxedIn;
+wire resetEventIn;
+wire resumeIntIn;
+wire transDoneIn;
+wire NAKSentIn;
+wire slaveControlSelect;
+wire clrEP0Ready;
+wire clrEP1Ready;
+wire clrEP2Ready;
+wire clrEP3Ready;
+reg [1:0] TxLineState;
+reg [1:0] TxLineState_reg1;
+reg LineDirectControlEn;
+reg LineDirectControlEn_reg1;
+reg fullSpeedPol; 
+reg fullSpeedPol_reg1; 
+reg fullSpeedRate;
+reg fullSpeedRate_reg1;
+reg connectSlaveToHost;
+reg connectSlaveToHost_reg1;
+reg SCGlobalEn;
+reg SCGlobalEn_reg1;
+
+//internal wire and regs
+reg [6:0] SCControlReg;
+reg clrVBusDetReq;
+reg clrNAKReq;
+reg clrSOFReq;
+reg clrResetReq;
+reg clrResInReq;
+reg clrTransDoneReq;
+reg SOFRxedInt;
+reg resetEventInt;
+reg resumeInt;
+reg transDoneInt;
+reg vBusDetInt;
+reg NAKSentInt;
+reg [5:0] interruptMaskReg;
+reg EP0SetReady;
+reg EP1SetReady;
+reg EP2SetReady;
+reg EP3SetReady;
+reg EP0SendStall;
+reg EP1SendStall;
+reg EP2SendStall;
+reg EP3SendStall;
+reg EP0IsoEn;
+reg EP1IsoEn;
+reg EP2IsoEn;
+reg EP3IsoEn;
+reg EP0DataSequence;
+reg EP1DataSequence;
+reg EP2DataSequence;
+reg EP3DataSequence;
+reg EP0Enable;
+reg EP1Enable;
+reg EP2Enable;
+reg EP3Enable;
+reg EP0Ready;
+reg EP1Ready;
+reg EP2Ready;
+reg EP3Ready;
+reg [2:0] SOFRxedInExtend;
+reg [2:0] resetEventInExtend;
+reg [2:0] resumeIntInExtend;
+reg [2:0] transDoneInExtend;
+reg [2:0] NAKSentInExtend;
+reg [2:0] clrEP0ReadyExtend;
+reg [2:0] clrEP1ReadyExtend;
+reg [2:0] clrEP2ReadyExtend;
+reg [2:0] clrEP3ReadyExtend;
+
+
+//clock domain crossing sync registers
+//STB = Sync To Busclk
+reg [4:0] endP0ControlRegSTB;
+reg [4:0] endP1ControlRegSTB;
+reg [4:0] endP2ControlRegSTB;
+reg [4:0] endP3ControlRegSTB;
+reg [2:0] NAKSentInSTB;
+reg [2:0] SOFRxedInSTB;
+reg [2:0] resetEventInSTB;
+reg [2:0] resumeIntInSTB;
+reg [2:0] transDoneInSTB;
+reg [2:0] clrEP0ReadySTB;
+reg [2:0] clrEP1ReadySTB;
+reg [2:0] clrEP2ReadySTB;
+reg [2:0] clrEP3ReadySTB;
+reg SCGlobalEnSTB;
+reg [1:0] TxLineStateSTB;
+reg LineDirectControlEnSTB;
+reg fullSpeedPolSTB; 
+reg fullSpeedRateSTB;
+reg connectSlaveToHostSTB;
+reg [7:0] EP0StatusRegSTB;
+reg [7:0] EP0StatusRegSTB_reg1;
+reg [7:0] EP1StatusRegSTB;
+reg [7:0] EP1StatusRegSTB_reg1;
+reg [7:0] EP2StatusRegSTB;
+reg [7:0] EP2StatusRegSTB_reg1;
+reg [7:0] EP3StatusRegSTB;
+reg [7:0] EP3StatusRegSTB_reg1;
+reg [1:0] endP0TransTypeRegSTB;
+reg [1:0] endP0TransTypeRegSTB_reg1;
+reg [1:0] endP0NAKTransTypeRegSTB;
+reg [1:0] endP0NAKTransTypeRegSTB_reg1;
+reg [1:0] endP1TransTypeRegSTB; 
+reg [1:0] endP1TransTypeRegSTB_reg1; 
+reg [1:0] endP1NAKTransTypeRegSTB;
+reg [1:0] endP1NAKTransTypeRegSTB_reg1;
+reg [1:0] endP2TransTypeRegSTB; 
+reg [1:0] endP2TransTypeRegSTB_reg1; 
+reg [1:0] endP2NAKTransTypeRegSTB;
+reg [1:0] endP2NAKTransTypeRegSTB_reg1;
+reg [1:0] endP3TransTypeRegSTB; 
+reg [1:0] endP3TransTypeRegSTB_reg1; 
+reg [1:0] endP3NAKTransTypeRegSTB;
+reg [1:0] endP3NAKTransTypeRegSTB_reg1;
+reg [10:0] frameNumSTB;
+reg [10:0] frameNumSTB_reg1;
+reg [2:0] vBusDetectInSTB;
+reg [1:0] connectStateInSTB;
+reg [1:0] connectStateInSTB_reg1;
+
+  
+//sync write demux
+always @(posedge busClk)
+begin   
+  if (rstSyncToBusClk == 1'b1) begin
+    EP0IsoEn <= 1'b0;
+    EP0SendStall <= 1'b0;
+    EP0DataSequence <= 1'b0;
+    EP0Enable <= 1'b0;
+    EP1IsoEn <= 1'b0;
+    EP1SendStall <= 1'b0;
+    EP1DataSequence <= 1'b0;
+    EP1Enable <= 1'b0;
+    EP2IsoEn <= 1'b0;
+    EP2SendStall <= 1'b0;
+    EP2DataSequence <= 1'b0;
+    EP2Enable <= 1'b0;
+    EP3IsoEn <= 1'b0;
+    EP3SendStall <= 1'b0;
+    EP3DataSequence <= 1'b0;
+    EP3Enable <= 1'b0;
+    SCControlReg <= 7'h00;
+    SCAddrReg <= 7'h00;
+    interruptMaskReg <= 6'h00;
+  end
+  else begin
+    clrVBusDetReq <= 1'b0;
+    clrNAKReq <= 1'b0;
+    clrSOFReq <= 1'b0;
+    clrResetReq <= 1'b0;
+    clrResInReq <= 1'b0;
+    clrTransDoneReq <= 1'b0;
+    EP0SetReady <= 1'b0;
+    EP1SetReady <= 1'b0;
+    EP2SetReady <= 1'b0;
+    EP3SetReady <= 1'b0;
+    if (writeEn == 1'b1 && strobe_i == 1'b1 && slaveControlSelect == 1'b1)
+    begin
+      case (address)
+        `EP0_CTRL_REG : begin
+          EP0IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP0SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP0DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP0SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP0Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP1_CTRL_REG : begin
+          EP1IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP1SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP1DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP1SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP1Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP2_CTRL_REG : begin
+          EP2IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP2SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP2DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP2SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP2Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `EP3_CTRL_REG : begin
+          EP3IsoEn <= dataIn[`ENDPOINT_ISO_ENABLE_BIT];
+          EP3SendStall <= dataIn[`ENDPOINT_SEND_STALL_BIT];
+          EP3DataSequence <= dataIn[`ENDPOINT_OUTDATA_SEQUENCE_BIT];
+          EP3SetReady <= dataIn[`ENDPOINT_READY_BIT];
+          EP3Enable <= dataIn[`ENDPOINT_ENABLE_BIT];
+        end
+        `SC_CONTROL_REG : SCControlReg <= dataIn[6:0];
+        `SC_ADDRESS : SCAddrReg <= dataIn[6:0];
+        `SC_INTERRUPT_STATUS_REG : begin
+          clrVBusDetReq <= dataIn[`VBUS_DET_INT_BIT];
+          clrNAKReq <= dataIn[`NAK_SENT_INT_BIT];
+          clrSOFReq <= dataIn[`SOF_RECEIVED_BIT];
+          clrResetReq <= dataIn[`RESET_EVENT_BIT];
+          clrResInReq <= dataIn[`RESUME_INT_BIT];
+          clrTransDoneReq <= dataIn[`TRANS_DONE_BIT];
+        end
+        `SC_INTERRUPT_MASK_REG  : interruptMaskReg <= dataIn[5:0];
+      endcase
+    end
+  end
+end
+
+//interrupt control 
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    vBusDetInt <= 1'b0;
+    NAKSentInt <= 1'b0;
+    SOFRxedInt <= 1'b0;
+    resetEventInt <= 1'b0;
+    resumeInt <= 1'b0;
+    transDoneInt <= 1'b0;
+  end
+  else begin
+    if (vBusDetectInSTB[0] != vBusDetectInSTB[1])
+      vBusDetInt <= 1'b1;
+    else if (clrVBusDetReq == 1'b1)
+      vBusDetInt <= 1'b0; 
+
+    if (NAKSentInSTB[1] == 1'b1 && NAKSentInSTB[0] == 1'b0)
+      NAKSentInt <= 1'b1;
+    else if (clrNAKReq == 1'b1)
+      NAKSentInt <= 1'b0; 
+    
+    if (SOFRxedInSTB[1] == 1'b1 && SOFRxedInSTB[0] == 1'b0)
+      SOFRxedInt <= 1'b1;
+    else if (clrSOFReq == 1'b1)
+      SOFRxedInt <= 1'b0;
+    
+    if (resetEventInSTB[1] == 1'b1 && resetEventInSTB[0] == 1'b0)
+      resetEventInt <= 1'b1;
+    else if (clrResetReq == 1'b1)
+      resetEventInt <= 1'b0;
+    
+    if (resumeIntInSTB[1] == 1'b1 && resumeIntInSTB[0] == 1'b0)
+      resumeInt <= 1'b1;
+    else if (clrResInReq == 1'b1)
+      resumeInt <= 1'b0;
+
+    if (transDoneInSTB[1] == 1'b1 && transDoneInSTB[0] == 1'b0)
+      transDoneInt <= 1'b1;
+    else if (clrTransDoneReq == 1'b1)
+      transDoneInt <= 1'b0;
+  end
+end
+
+//mask interrupts
+always @(*) begin
+  transDoneIntOut <= transDoneInt & interruptMaskReg[`TRANS_DONE_BIT];
+  resumeIntOut <= resumeInt & interruptMaskReg[`RESUME_INT_BIT];
+  resetEventIntOut <= resetEventInt & interruptMaskReg[`RESET_EVENT_BIT];
+  SOFRxedIntOut <= SOFRxedInt & interruptMaskReg[`SOF_RECEIVED_BIT];
+  NAKSentIntOut <= NAKSentInt & interruptMaskReg[`NAK_SENT_INT_BIT];
+  vBusDetIntOut <= vBusDetInt & interruptMaskReg[`VBUS_DET_INT_BIT];
+end  
+
+//end point ready, set/clear
+//Since 'busClk' can be a higher freq than 'usbClk',
+//'EP0SetReady' etc must be delayed with respect to other control signals, thus
+//ensuring that control signals have been clocked through to 'usbClk' clock
+//domain before the ready is asserted.
+//Not sure this is required because there is at least two 'usbClk' ticks between
+//detection of 'EP0Ready' and sampling of related control signals.
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClk == 1'b1) begin
+    EP0Ready <= 1'b0;
+    EP1Ready <= 1'b0;
+    EP2Ready <= 1'b0;
+    EP3Ready <= 1'b0;
+  end
+  else begin
+    if (EP0SetReady == 1'b1)
+      EP0Ready <= 1'b1;
+    else if (clrEP0ReadySTB[1] == 1'b1 && clrEP0ReadySTB[0] == 1'b0)
+      EP0Ready <= 1'b0;
+    
+    if (EP1SetReady == 1'b1)
+      EP1Ready <= 1'b1;
+    else if (clrEP1ReadySTB[1] == 1'b1 && clrEP1ReadySTB[0] == 1'b0)
+      EP1Ready <= 1'b0;
+    
+    if (EP2SetReady == 1'b1)
+      EP2Ready <= 1'b1;
+    else if (clrEP2ReadySTB[1] == 1'b1 && clrEP2ReadySTB[0] == 1'b0)
+      EP2Ready <= 1'b0;
+    
+    if (EP3SetReady == 1'b1)
+      EP3Ready <= 1'b1;
+    else if (clrEP3ReadySTB[1] == 1'b1 && clrEP3ReadySTB[0] == 1'b0)
+      EP3Ready <= 1'b0;
+  end
+end  
+  
+//break out control signals
+always @(SCControlReg) begin
+  SCGlobalEnSTB <= SCControlReg[`SC_GLOBAL_ENABLE_BIT];
+  TxLineStateSTB <= SCControlReg[`SC_TX_LINE_STATE_MSBIT:`SC_TX_LINE_STATE_LSBIT];
+  LineDirectControlEnSTB <= SCControlReg[`SC_DIRECT_CONTROL_BIT];
+  fullSpeedPolSTB <= SCControlReg[`SC_FULL_SPEED_LINE_POLARITY_BIT]; 
+  fullSpeedRateSTB <= SCControlReg[`SC_FULL_SPEED_LINE_RATE_BIT];
+  connectSlaveToHostSTB <= SCControlReg[`SC_CONNECT_TO_HOST_BIT];
+end
+
+//combine endpoint control signals 
+always @(*) 
+begin
+  endP0ControlRegSTB <= {EP0IsoEn, EP0SendStall, EP0DataSequence, EP0Ready, EP0Enable};
+  endP1ControlRegSTB <= {EP1IsoEn, EP1SendStall, EP1DataSequence, EP1Ready, EP1Enable};
+  endP2ControlRegSTB <= {EP2IsoEn, EP2SendStall, EP2DataSequence, EP2Ready, EP2Enable};
+  endP3ControlRegSTB <= {EP3IsoEn, EP3SendStall, EP3DataSequence, EP3Ready, EP3Enable};
+end
+      
+      
+// async read mux
+always @(*)
+begin
+  case (address)
+      `EP0_CTRL_REG : dataOut <= endP0ControlRegSTB;
+      `EP0_STS_REG : dataOut <= EP0StatusRegSTB;
+      `EP0_TRAN_TYPE_STS_REG : dataOut <= endP0TransTypeRegSTB;
+      `EP0_NAK_TRAN_TYPE_STS_REG : dataOut <= endP0NAKTransTypeRegSTB;
+      `EP1_CTRL_REG : dataOut <= endP1ControlRegSTB;
+      `EP1_STS_REG :  dataOut <= EP1StatusRegSTB;
+      `EP1_TRAN_TYPE_STS_REG : dataOut <= endP1TransTypeRegSTB;
+      `EP1_NAK_TRAN_TYPE_STS_REG : dataOut <= endP1NAKTransTypeRegSTB;
+      `EP2_CTRL_REG : dataOut <= endP2ControlRegSTB;
+      `EP2_STS_REG :  dataOut <= EP2StatusRegSTB;
+      `EP2_TRAN_TYPE_STS_REG : dataOut <= endP2TransTypeRegSTB;
+      `EP2_NAK_TRAN_TYPE_STS_REG : dataOut <= endP2NAKTransTypeRegSTB;
+      `EP3_CTRL_REG : dataOut <= endP3ControlRegSTB;
+      `EP3_STS_REG :  dataOut <= EP3StatusRegSTB;
+      `EP3_TRAN_TYPE_STS_REG : dataOut <= endP3TransTypeRegSTB;
+      `EP3_NAK_TRAN_TYPE_STS_REG : dataOut <= endP3NAKTransTypeRegSTB;
+      `SC_CONTROL_REG : dataOut <= SCControlReg;
+      `SC_LINE_STATUS_REG : dataOut <= {5'b00000, vBusDetectInSTB[0], connectStateInSTB}; 
+      `SC_INTERRUPT_STATUS_REG :  dataOut <= {2'b00, vBusDetInt, NAKSentInt, SOFRxedInt, resetEventInt, resumeInt, transDoneInt};
+      `SC_INTERRUPT_MASK_REG  : dataOut <= {2'b00, interruptMaskReg};
+      `SC_ADDRESS : dataOut <= {1'b0, SCAddrReg};
+      `SC_FRAME_NUM_MSP : dataOut <= {5'b00000, frameNumSTB[10:8]};
+      `SC_FRAME_NUM_LSP : dataOut <= frameNumSTB[7:0];
+      default: dataOut <= 8'h00;
+  endcase
+end
+
+
+//Extend SOFRxedIn, resetEventIn, resumeIntIn, transDoneIn, NAKSentIn from 1 tick
+//pulses to 3 tick pulses
+always @(posedge usbClk) begin
+  if (rstSyncToUsbClk == 1'b1) begin
+    SOFRxedInExtend <= 3'b000;
+    resetEventInExtend <= 3'b000;
+    resumeIntInExtend <= 3'b000;
+    transDoneInExtend <= 3'b000;
+    NAKSentInExtend <= 3'b000;
+    clrEP0ReadyExtend <= 3'b000;
+    clrEP1ReadyExtend <= 3'b000;
+    clrEP2ReadyExtend <= 3'b000;
+    clrEP3ReadyExtend <= 3'b000;
+  end
+  else begin
+    if (SOFRxedIn == 1'b1)
+      SOFRxedInExtend <= 3'b111;
+    else
+      SOFRxedInExtend <= {1'b0, SOFRxedInExtend[2:1]};
+    if (resetEventIn == 1'b1)
+      resetEventInExtend <= 3'b111;
+    else
+      resetEventInExtend <= {1'b0, resetEventInExtend[2:1]};
+    if (resumeIntIn == 1'b1)
+      resumeIntInExtend <= 3'b111;
+    else
+      resumeIntInExtend <= {1'b0, resumeIntInExtend[2:1]};
+    if (transDoneIn == 1'b1)
+      transDoneInExtend <= 3'b111;
+    else
+      transDoneInExtend <= {1'b0, transDoneInExtend[2:1]};
+    if (NAKSentIn == 1'b1)
+      NAKSentInExtend <= 3'b111;
+    else
+      NAKSentInExtend <= {1'b0, NAKSentInExtend[2:1]};
+    if (clrEP0Ready == 1'b1)
+      clrEP0ReadyExtend <= 3'b111;
+    else
+      clrEP0ReadyExtend <= {1'b0, clrEP0ReadyExtend[2:1]};
+    if (clrEP1Ready == 1'b1)
+      clrEP1ReadyExtend <= 3'b111;
+    else
+      clrEP1ReadyExtend <= {1'b0, clrEP1ReadyExtend[2:1]};
+    if (clrEP2Ready == 1'b1)
+      clrEP2ReadyExtend <= 3'b111;
+    else
+      clrEP2ReadyExtend <= {1'b0, clrEP2ReadyExtend[2:1]};
+    if (clrEP3Ready == 1'b1)
+      clrEP3ReadyExtend <= 3'b111;
+    else
+      clrEP3ReadyExtend <= {1'b0, clrEP3ReadyExtend[2:1]};
+  end
+end
+
+//re-sync from busClk to usbClk. 
+always @(posedge usbClk) begin
+  if (rstSyncToUsbClk == 1'b1) begin
+    endP0ControlReg <= {5{1'b0}};
+    endP0ControlReg1 <= {5{1'b0}};
+    endP1ControlReg <= {5{1'b0}};
+    endP1ControlReg1 <= {5{1'b0}};
+    endP2ControlReg <= {5{1'b0}};
+    endP2ControlReg1 <= {5{1'b0}};
+    endP3ControlReg <= {5{1'b0}};
+    endP3ControlReg1 <= {5{1'b0}};
+    SCGlobalEn <= 1'b0;
+    SCGlobalEn_reg1 <= 1'b0;
+    TxLineState <= 2'b00;
+    TxLineState_reg1 <= 2'b00;
+    LineDirectControlEn <= 1'b0;
+    LineDirectControlEn_reg1 <= 1'b0;
+    fullSpeedPol <= 1'b0;
+    fullSpeedPol_reg1 <= 1'b0;
+    fullSpeedRate <= 1'b0;
+    fullSpeedRate_reg1 <= 1'b0;
+    connectSlaveToHost <= 1'b0;
+    connectSlaveToHost_reg1 <= 1'b0;
+  end
+  else begin
+    endP0ControlReg1 <= endP0ControlRegSTB;
+    endP0ControlReg <= endP0ControlReg1;
+    endP1ControlReg1 <= endP1ControlRegSTB;
+    endP1ControlReg <= endP1ControlReg1;
+    endP2ControlReg1 <= endP2ControlRegSTB;
+    endP2ControlReg <= endP2ControlReg1;
+    endP3ControlReg1 <= endP3ControlRegSTB;
+    endP3ControlReg <= endP3ControlReg1;
+    SCGlobalEn_reg1 <= SCGlobalEnSTB;
+    SCGlobalEn <= SCGlobalEn_reg1;
+    TxLineState_reg1 <= TxLineStateSTB;
+    TxLineState <= TxLineState_reg1;
+    LineDirectControlEn_reg1 <= LineDirectControlEnSTB;
+    LineDirectControlEn <= LineDirectControlEn_reg1;
+    fullSpeedPol_reg1 <= fullSpeedPolSTB; 
+    fullSpeedPol <= fullSpeedPol_reg1; 
+    fullSpeedRate_reg1 <= fullSpeedRateSTB;
+    fullSpeedRate <= fullSpeedRate_reg1;
+    connectSlaveToHost_reg1 <= connectSlaveToHostSTB;
+    connectSlaveToHost <= connectSlaveToHost_reg1;
+  end
+end
+
+//re-sync from usbClk and async inputs to busClk. Since 'NAKSentIn', 'SOFRxedIn' etc 
+//are only asserted for 3 usbClk ticks
+//busClk freq must be greater than usbClk/3 (plus some allowance for setup and hold) freq
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) begin
+    vBusDetectInSTB <= 3'b000;
+    NAKSentInSTB <= 3'b000;
+    SOFRxedInSTB <= 3'b000;
+    resetEventInSTB <= 3'b000;
+    resumeIntInSTB <= 3'b000;
+    transDoneInSTB <= 3'b000;
+    clrEP0ReadySTB <= 3'b000;
+    clrEP1ReadySTB <= 3'b000;
+    clrEP2ReadySTB <= 3'b000;
+    clrEP3ReadySTB <= 3'b000;
+    EP0StatusRegSTB <= 8'h00;
+    EP0StatusRegSTB_reg1 <= 8'h00;
+    EP1StatusRegSTB <= 8'h00;
+    EP1StatusRegSTB_reg1 <= 8'h00;
+    EP2StatusRegSTB <= 8'h00;
+    EP2StatusRegSTB_reg1 <= 8'h00;
+    EP3StatusRegSTB <= 8'h00;
+    EP3StatusRegSTB_reg1 <= 8'h00;
+    endP0TransTypeRegSTB <= 2'b00;
+    endP0TransTypeRegSTB_reg1 <= 2'b00;
+    endP1TransTypeRegSTB <= 2'b00;
+    endP1TransTypeRegSTB_reg1 <= 2'b00;
+    endP2TransTypeRegSTB <= 2'b00;
+    endP2TransTypeRegSTB_reg1 <= 2'b00;
+    endP3TransTypeRegSTB <= 2'b00;
+    endP3TransTypeRegSTB_reg1 <= 2'b00;
+    endP0NAKTransTypeRegSTB <= 2'b00;
+    endP0NAKTransTypeRegSTB_reg1 <= 2'b00;
+    endP1NAKTransTypeRegSTB <= 2'b00;
+    endP1NAKTransTypeRegSTB_reg1 <= 2'b00;
+    endP2NAKTransTypeRegSTB <= 2'b00;
+    endP2NAKTransTypeRegSTB_reg1 <= 2'b00;
+    endP3NAKTransTypeRegSTB <= 2'b00;
+    endP3NAKTransTypeRegSTB_reg1 <= 2'b00;
+    frameNumSTB <= {11{1'b0}};
+    frameNumSTB_reg1 <= {11{1'b0}};
+    connectStateInSTB <= 2'b00;
+    connectStateInSTB_reg1 <= 2'b00;
+  end
+  else begin
+    vBusDetectInSTB <= {vBusDetectIn, vBusDetectInSTB[2:1]};
+    NAKSentInSTB <= {NAKSentInExtend[0], NAKSentInSTB[2:1]};
+    SOFRxedInSTB <= {SOFRxedInExtend[0], SOFRxedInSTB[2:1]};
+    resetEventInSTB <= {resetEventInExtend[0], resetEventInSTB[2:1]};
+    resumeIntInSTB <= {resumeIntInExtend[0], resumeIntInSTB[2:1]};
+    transDoneInSTB <= {transDoneInExtend[0], transDoneInSTB[2:1]};
+    clrEP0ReadySTB <= {clrEP0ReadyExtend[0], clrEP0ReadySTB[2:1]};
+    clrEP1ReadySTB <= {clrEP1ReadyExtend[0], clrEP1ReadySTB[2:1]};
+    clrEP2ReadySTB <= {clrEP2ReadyExtend[0], clrEP2ReadySTB[2:1]};
+    clrEP3ReadySTB <= {clrEP3ReadyExtend[0], clrEP3ReadySTB[2:1]};
+    EP0StatusRegSTB_reg1 <= EP0StatusReg;
+    EP0StatusRegSTB <= EP0StatusRegSTB_reg1;
+    EP1StatusRegSTB_reg1 <= EP1StatusReg;
+    EP1StatusRegSTB <= EP1StatusRegSTB_reg1;
+    EP2StatusRegSTB_reg1 <= EP2StatusReg;
+    EP2StatusRegSTB <= EP2StatusRegSTB_reg1;
+    EP3StatusRegSTB_reg1 <= EP3StatusReg;
+    EP3StatusRegSTB <= EP3StatusRegSTB_reg1;
+    endP0TransTypeRegSTB_reg1 <= endP0TransTypeReg;
+    endP0TransTypeRegSTB <= endP0TransTypeRegSTB_reg1;
+    endP1TransTypeRegSTB_reg1 <= endP1TransTypeReg;
+    endP1TransTypeRegSTB <= endP1TransTypeRegSTB_reg1;
+    endP2TransTypeRegSTB_reg1 <= endP2TransTypeReg;
+    endP2TransTypeRegSTB <= endP2TransTypeRegSTB_reg1;
+    endP3TransTypeRegSTB_reg1 <= endP3TransTypeReg;
+    endP3TransTypeRegSTB <= endP3TransTypeRegSTB_reg1;
+    endP0NAKTransTypeRegSTB_reg1 <= endP0NAKTransTypeReg;
+    endP0NAKTransTypeRegSTB <= endP0NAKTransTypeRegSTB_reg1;
+    endP1NAKTransTypeRegSTB_reg1 <= endP1NAKTransTypeReg;
+    endP1NAKTransTypeRegSTB <= endP1NAKTransTypeRegSTB_reg1;
+    endP2NAKTransTypeRegSTB_reg1 <= endP2NAKTransTypeReg;
+    endP2NAKTransTypeRegSTB <= endP2NAKTransTypeRegSTB_reg1;
+    endP3NAKTransTypeRegSTB_reg1 <= endP3NAKTransTypeReg;
+    endP3NAKTransTypeRegSTB <= endP3NAKTransTypeRegSTB_reg1;
+    frameNumSTB_reg1 <= frameNum;
+    frameNumSTB <= frameNumSTB_reg1;
+    connectStateInSTB_reg1 <= connectStateIn;
+    connectStateInSTB <= connectStateInSTB_reg1;
+  end
+end
+
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoMux.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoMux.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoMux.v	(revision 264)
@@ -0,0 +1,212 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module fifoMux (
+  currEndP,
+  //TxFifo
+  TxFifoREn,
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoData,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEmpty,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  //RxFifo
+  RxFifoWEn,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoFull,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+
+input [3:0] currEndP;
+//TxFifo
+input TxFifoREn;
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+output [7:0] TxFifoData;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+output TxFifoEmpty;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+  //RxFifo
+input RxFifoWEn;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+output RxFifoFull;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire [3:0] currEndP;
+//TxFifo
+wire TxFifoREn;
+reg TxFifoEP0REn;
+reg TxFifoEP1REn;
+reg TxFifoEP2REn;
+reg TxFifoEP3REn;
+reg [7:0] TxFifoData;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+reg TxFifoEmpty;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+  //RxFifo
+wire RxFifoWEn;
+reg RxFifoEP0WEn;
+reg RxFifoEP1WEn;
+reg RxFifoEP2WEn;
+reg RxFifoEP3WEn;
+reg RxFifoFull;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wires and regs
+
+//combinatorially mux TX and RX fifos for end points 0 through 3
+always @(currEndP or
+  TxFifoREn or
+  RxFifoWEn or
+  TxFifoEP0Data or
+  TxFifoEP1Data or
+  TxFifoEP2Data or
+  TxFifoEP3Data or
+  TxFifoEP0Empty or
+  TxFifoEP1Empty or
+  TxFifoEP2Empty or
+  TxFifoEP3Empty or
+  RxFifoEP0Full or
+  RxFifoEP1Full or
+  RxFifoEP2Full or
+  RxFifoEP3Full)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      TxFifoEP0REn <= TxFifoREn;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP0Data;
+      TxFifoEmpty <= TxFifoEP0Empty;
+      RxFifoEP0WEn <= RxFifoWEn;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP0Full;
+    end
+    2'b01: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= TxFifoREn;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP1Data;
+      TxFifoEmpty <= TxFifoEP1Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= RxFifoWEn;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP1Full;
+    end
+    2'b10: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= TxFifoREn;
+      TxFifoEP3REn <= 1'b0;
+      TxFifoData <= TxFifoEP2Data;
+      TxFifoEmpty <= TxFifoEP2Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= RxFifoWEn;
+      RxFifoEP3WEn <= 1'b0;
+      RxFifoFull <= RxFifoEP2Full;
+    end
+    2'b11: begin
+      TxFifoEP0REn <= 1'b0;
+      TxFifoEP1REn <= 1'b0;
+      TxFifoEP2REn <= 1'b0;
+      TxFifoEP3REn <= TxFifoREn;
+      TxFifoData <= TxFifoEP3Data;
+      TxFifoEmpty <= TxFifoEP3Empty;
+      RxFifoEP0WEn <= 1'b0;
+      RxFifoEP1WEn <= 1'b0;
+      RxFifoEP2WEn <= 1'b0;
+      RxFifoEP3WEn <= RxFifoWEn;
+      RxFifoFull <= RxFifoEP3Full;
+    end
+  endcase  
+end      
+
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/pll_48MHz.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/pll_48MHz.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/pll_48MHz.v	(revision 264)
@@ -0,0 +1,278 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll_48MHz.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Build 203 02/05/2008 SP 2 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll_48MHz (
+	inclk0,
+	locked);
+
+	input	  inclk0;
+	output	  locked;
+
+	wire  sub_wire0;
+	wire [0:0] sub_wire3 = 1'h0;
+	wire  locked = sub_wire0;
+	wire  sub_wire1 = inclk0;
+	wire [1:0] sub_wire2 = {sub_wire3, sub_wire1};
+
+	altpll	altpll_component (
+				.inclk (sub_wire2),
+				.locked (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clk (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.gate_lock_signal = "NO",
+		altpll_component.inclk0_input_frequency = 20833,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.invalid_lock_multiplier = 5,
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_48MHz",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NO_COMPENSATION",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_UNUSED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_48MHz.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_inst.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_waveforms.html TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_wave*.jpg FALSE FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/readUSBWireData.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/readUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/readUSBWireData.v	(revision 264)
@@ -0,0 +1,274 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// readUSBWireData.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////      This module reads data from the differential USB data lines
+////      and writes into a 4 entry FIFO. The data is read from
+////      the fifo and output from the module when the higher level
+////      state machine is ready to receive the data.
+////      This module must recover the clock phase from the incoming
+////      USB data. 'sampleCnt' is reset to zero whenever a RX data
+////      edge is detected. Note that due to metastability the data
+////      at the edge may not be registered correctly, but this does
+////      not matter. All that matters is that an edge was detected. The
+////      data will be accurately sampled in the middle of the USB bit 
+////      period without metastability issues. 
+////      After the edge detect, 'sampleCnt' is incremented at every clock
+////      tick, and when it indicates the middle of a USB bit period
+////      the RX data is sampled and written to the input buffer.
+////      Single clock tick adjustments to 'sampleCnt' can be made at 
+////      every RX data edge detect without double sampling the incoming
+////      data. However, the first RX data bit in a packet may cause 
+////      'sampleCnt' to be adjusted by a value greater than a single 
+////      clock tick, and this can result in double sampling of the 
+////      first data bit a RX packet. This 
+////      double sampled data must be rejected by the higher level module.
+////      This is achieved by 
+////      qualifying the outgoing data with 'RxWireActive'. Thus 
+////      the first data bit in a RX packet may be double sampled
+////      as the clock recovery mechanism synchronizes to 'RxBitsIn'
+////      but the double sampled data will be rejected by the higher 
+////      level module.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable);
+input   [1:0] RxBitsIn;
+output  RxDataInTick;
+input   SIERxRdyIn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+input   TxWireActiveDrive;
+output  [1:0] RxBitsOut;
+output  SIERxWEn;
+output noActivityTimeOut;
+output RxWireActive;
+input  noActivityTimeOutEnable;
+
+wire   [1:0] RxBitsIn;
+reg    RxDataInTick;
+wire   SIERxRdyIn;
+wire   clk;
+wire   fullSpeedRate;
+wire   rst;
+reg    [1:0] RxBitsOut;
+reg    SIERxWEn;
+reg    noActivityTimeOut;
+reg    RxWireActive;
+wire   noActivityTimeOutEnable;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]sampleCnt;
+reg incBufferCnt;
+reg  [1:0]oldRxBitsIn;
+reg [1:0] RxBitsInReg;
+reg [15:0] timeOutCnt;
+reg [7:0] rxActiveCnt;
+reg RxWireEdgeDetect;
+reg RxWireActiveReg;
+reg RxWireActiveReg2;
+reg [1:0] RxBitsInSyncReg1;
+reg [1:0] RxBitsInSyncReg2;
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_NOT_EMPTY 2'b00
+`define WAIT_SIE_RX_READY 2'b01
+`define SIE_RX_WRITE 2'b10
+
+// re-synchronize incoming bits
+always @(posedge clk) begin
+  RxBitsInSyncReg1 <= RxBitsIn;
+  RxBitsInSyncReg2 <= RxBitsInSyncReg1;
+end
+
+reg [1:0] bufferOutStMachCurrState;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+
+//Perform line rate clock recovery
+//Recover the wire data, and store data to buffer
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    sampleCnt <= 5'b00000;
+    incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    RxDataInTick <= 1'b0;
+    RxWireEdgeDetect <= 1'b0;
+    RxWireActiveReg <= 1'b0;
+    RxWireActiveReg2 <= 1'b0;
+  end
+  else begin
+    RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
+    RxBitsInReg <= RxBitsInSyncReg2;    
+    oldRxBitsIn <= RxBitsInReg;
+    incBufferCnt <= 1'b0;         //default value
+    if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin  //if edge detected then
+      sampleCnt <= 5'b00000;        
+      RxWireEdgeDetect <= 1'b1;   // flag receive activity 
+      RxWireActiveReg <= 1'b1;
+      rxActiveCnt <= 8'h00;
+    end
+    else begin
+      sampleCnt <= sampleCnt + 1'b1;
+      RxWireEdgeDetect <= 1'b0;
+      rxActiveCnt <= rxActiveCnt + 1'b1;
+      //clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods 
+      if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE)
+        || (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) ) 
+        RxWireActiveReg <= 1'b0;
+    end
+    if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) )
+    begin
+      RxDataInTick <= !RxDataInTick;
+      if (TxWireActiveDrive != 1'b1)  //do not read wire data when transmitter is active
+      begin
+        incBufferCnt <= 1'b1;
+        bufferInIndex <= bufferInIndex + 1'b1;
+        case (bufferInIndex)
+          2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn}; 
+          2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn};
+          2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn};
+          2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn};
+        endcase
+      end
+    end
+  end
+end
+
+        
+
+//read from buffer, and output to SIEReceiver
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    decBufferCnt <= 1'b0;
+    bufferOutIndex <= 2'b00;
+    RxBitsOut <= 2'b00;
+    SIERxWEn <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+  end
+  else begin
+    case (bufferOutStMachCurrState)
+      `WAIT_BUFFER_NOT_EMPTY:
+      begin
+        if (bufferCnt != 3'b000)
+          bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
+      end
+      `WAIT_SIE_RX_READY:
+      begin
+        if (SIERxRdyIn == 1'b1)
+        begin 
+          SIERxWEn <= 1'b1;
+          bufferOutStMachCurrState <= `SIE_RX_WRITE;
+          decBufferCnt <= 1'b1;
+          bufferOutIndex <= bufferOutIndex + 1'b1;
+          case (bufferOutIndex)
+            2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
+            2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
+            2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
+            2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
+          endcase
+        end
+      end
+      `SIE_RX_WRITE:
+      begin
+        SIERxWEn <= 1'b0;
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
+      end
+    endcase
+  end
+end
+
+//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods
+//'noActivityTimeOut'  pulse can only be generated when the host or slave getPacket
+//process enables via 'noActivityTimeOutEnable' signal
+//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if 
+//there has been a response time out.
+always @(posedge clk) begin
+  if (rst) begin
+    timeOutCnt <= 16'h0000;
+    noActivityTimeOut <= 1'b0;
+  end
+  else begin
+    if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0)
+      timeOutCnt <= 16'h0000;
+    else
+      timeOutCnt <= timeOutCnt + 1'b1;
+    if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
+      || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) ) 
+      noActivityTimeOut <= 1'b1; 
+    else 
+      noActivityTimeOut <= 1'b0;
+  end
+end
+
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/progFiles/2008_08_22/usbDeviceAlteraTop.rbf
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/trunk/usbDevice/progFiles/2008_08_22/usbDeviceAlteraTop.rbf
___________________________________________________________________
Added: svn:mime-type
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+application/octet-stream
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Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/copyRTLtoActelHDLFolder.bat
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/copyRTLtoActelHDLFolder.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/copyRTLtoActelHDLFolder.bat	(revision 264)
@@ -0,0 +1,11 @@
+copy /Y ..\..\RTL\*.v usbDeviceActelTop\hdl
+copy /Y ..\..\..\RTL\buffers\*.v usbDeviceActelTop\hdl
+copy /Y ..\..\..\RTL\busInterface\*.v usbDeviceActelTop\hdl
+copy /Y ..\..\..\RTL\hostSlaveMux\hostSlaveMuxBI.v.v usbDeviceActelTop\hdl
+copy /Y ..\..\..\RTL\include\*.v usbDeviceActelTop\hdl
+copy /Y ..\..\..\RTL\serialInterfaceEngine\*.v usbDeviceActelTop\hdl
+copy /Y ..\..\..\RTL\slaveController\*.v usbDeviceActelTop\hdl
+copy /Y ..\..\..\RTL\wrapper\usbSlave.v usbDeviceActelTop\hdl
+
+pause
+
Index: common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbhostslaveavalonwrap/hdl/usbHostSlaveAvalonWrap.v
===================================================================
--- common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbhostslaveavalonwrap/hdl/usbHostSlaveAvalonWrap.v	(nonexistent)
+++ common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbhostslaveavalonwrap/hdl/usbHostSlaveAvalonWrap.v	(revision 264)
@@ -0,0 +1,51876 @@
+// Copyright (C) 1991-2006 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II"
+// VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition"
+
+// DATE "10/15/2006 20:38:20"
+
+module 	usbHostSlaveAvalonWrap (
+	clk,
+	reset,
+	address,
+	writedata,
+	readdata,
+	write,
+	read,
+	waitrequest,
+	chipselect,
+	irq,
+	usbClk,
+	USBWireVPI,
+	USBWireVMI,
+	USBWireDataInTick,
+	USBWireVPO,
+	USBWireVMO,
+	USBWireDataOutTick,
+	USBWireOutEn_n,
+	USBFullSpeed);
+input 	clk;
+input 	reset;
+input 	[7:0] address;
+input 	[7:0] writedata;
+output 	[7:0] readdata;
+input 	write;
+input 	read;
+output 	waitrequest;
+input 	chipselect;
+output 	irq;
+input 	usbClk;
+input 	USBWireVPI;
+input 	USBWireVMI;
+output 	USBWireDataInTick;
+output 	USBWireVPO;
+output 	USBWireVMO;
+output 	USBWireDataOutTick;
+output 	USBWireOutEn_n;
+output 	USBFullSpeed;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378 ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34 ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~41 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~40 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~43 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~44 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~753 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~754 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~751 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~752 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~750 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~755 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~756 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~749 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~739 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~740 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~741 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~742 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~743 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~744 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~745 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~523 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~524 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~521 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~522 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~525 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~526 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~527 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~617 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~618 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~615 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~616 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~75 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~74 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~81 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~78 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~80 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~79 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~76 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~73 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~72 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~75 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~76 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~781 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~782 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~779 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~780 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~783 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~784 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~785 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~786 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~777 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~217 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~226 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~217 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~226 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~217 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~226 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~217 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~226 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \strobe_i~19 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~217 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~223 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~217 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~223 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~217 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~223 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~217 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~223 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~210 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~211 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~212 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~224 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~213 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~215 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~214 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~216 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~217 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~209 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~218 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~219 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~220 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~221 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~222 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~217 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~223 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~226 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~214 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~220 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~211 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~70 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~68 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~69 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~208 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~223 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~71 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10 ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289 ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~767 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~768 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~769 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~770 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~771 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~772 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~773 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~774 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~775 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~777 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~776 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~778 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~779 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~780 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~781 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~89 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~91 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~93 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~94 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~95 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~96 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~97 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~98 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~88 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~90 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525 ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~1172 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~1173 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~1174 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1171 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~1175 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~1176 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~1177 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425 ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15] ;
+wire \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429 ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7] ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156 ;
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258 ;
+wire \irq~54 ;
+wire \irq~55 ;
+wire \irq~56 ;
+wire \irq~57 ;
+wire \irq~58 ;
+wire \irq~7 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0 ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB ;
+wire [10:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1 ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0 ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3 ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData ;
+wire [9:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB ;
+wire [10:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2 ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg ;
+wire [10:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3 ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i ;
+wire [10:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1 ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg ;
+wire [4:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex ;
+wire [2:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2 ;
+wire [15:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg ;
+wire [1:0] \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID ;
+wire [3:0] \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [5:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex ;
+wire [6:0] \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk ;
+wire [7:0] \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b ;
+
+wire \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|__ALT_INV__ack_o~258 ;
+wire \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|__ALT_INV__TxCtrlOut ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ;
+wire \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ;
+
+wire gnd;
+wire vcc;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+
+assign \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|__ALT_INV__ack_o~258  = ~ \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258 ;
+assign \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|__ALT_INV__TxCtrlOut  = ~ \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ;
+assign \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0]  = ~ \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ;
+assign \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut  = ~ \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378_I .lut_mask = "4000";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34_I (
+	.dataa(write),
+	.datab(chipselect),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~378 ),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34 ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34 ),
+	.datab(writedata[1]),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus~I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus ),
+	.datab(reset),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5]~I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus ),
+	.datab(reset),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus ),
+	.datab(reset),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus ),
+	.datab(reset),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus ),
+	.datab(reset),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstFromBus ),
+	.datac(reset),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242_I .lut_mask = "FFFC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0]~I .lut_mask = "0101";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]~I .lut_mask = "0880";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]~I .lut_mask = "0880";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Add0~105 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]~I .lut_mask = "0888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22_I .lut_mask = "BFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034_I .lut_mask = "003F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100~I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1]~I (
+	.clk(usbClk),
+	.dataa(USBWireVPI),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~41 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~I .lut_mask = "55AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]~41 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~40 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick~I .lut_mask = "1111";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]~40 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~43 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]~43 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~44 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]~44 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~41 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal3~42 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252_I (
+	.dataa(writedata[4]),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857_I (
+	.datac(address[7]),
+	.datad(address[5]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857 ),
+	.datab(write),
+	.datac(chipselect),
+	.datad(address[6]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200_I (
+	.dataa(address[0]),
+	.datab(address[1]),
+	.datac(address[2]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200_I .lut_mask = "0004";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~200 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332_I (
+	.dataa(writedata[5]),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155_I (
+	.dataa(address[1]),
+	.datab(address[2]),
+	.datac(address[0]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857 ),
+	.datac(write),
+	.datad(chipselect),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300_I (
+	.dataa(address[4]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300_I .lut_mask = "FF80";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datab(writedata[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|always0~34 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedRate ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.combout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9_I .lut_mask = "AFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000~I .lut_mask = "5555";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108_I (
+	.dataa(writedata[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088_I .lut_mask = "A8A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5087 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5088 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089_I .lut_mask = "EFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010~I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~35 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100~I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector4~36 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~86 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector8~87 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349_I .lut_mask = "0AFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~349 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~348 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55_I .lut_mask = "88EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector23~55 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202_I (
+	.dataa(address[0]),
+	.datab(address[1]),
+	.datac(address[2]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011~I .lut_mask = "EEAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001~I .lut_mask = "00AF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84_I .lut_mask = "0AEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector14~84 ),
+	.datac(vcc),
+	.aclr(gnd),
+	.sload(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201_I (
+	.dataa(address[0]),
+	.datab(address[1]),
+	.datac(address[2]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ),
+	.datab(writedata[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~201 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB~I .lut_mask = "CAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~117 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr~I .lut_mask = "A0E4";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~753 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~I .lut_mask = "55AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]~753 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~754 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]~754 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~751 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]~751 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~752 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]~752 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~750 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]~750 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~755 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]~755 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~756 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]~756 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~749 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]~749 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~739 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]~739 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~740 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]~740 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~741 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]~741 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~742 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]~742 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~743 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]~743 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~744 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~744 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~745 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~747 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]~748 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]~745 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]~I .lut_mask = "5A5A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218_I .lut_mask = "8880";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251_I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~251 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252_I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~252 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254_I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100~I .lut_mask = "F400";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121_I .lut_mask = "003F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110~I .lut_mask = "3388";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530_I .lut_mask = "FFD1";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~523 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~I .lut_mask = "55AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]~523 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~524 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]~524 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~521 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]~521 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~522 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]~522 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~525 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]~525 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~526 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]~526 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~527 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~529 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~530 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]~527 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]~I .lut_mask = "5A5A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~70 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~71 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101~I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275_I .lut_mask = "0AAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132_I .lut_mask = "0AAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219_I .lut_mask = "0FFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~219 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~218 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~250 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220_I .lut_mask = "ABFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~220 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~253 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221_I .lut_mask = "02FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16_I (
+	.dataa(writedata[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan0~221 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1127 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128_I .lut_mask = "002F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1132 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1131 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133_I .lut_mask = "8AFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1133 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001~I .lut_mask = "BF88";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~275 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276_I .lut_mask = "AAAE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Selector7~276 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357_I .lut_mask = "0AFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~357 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00~I .lut_mask = "2000";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~55 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56_I .lut_mask = "88EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector4~56 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199_I (
+	.dataa(address[0]),
+	.datab(address[1]),
+	.datac(address[2]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~199 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143_I (
+	.dataa(writedata[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~144 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080_I .lut_mask = "0007";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102_I .lut_mask = "AAFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011~I .lut_mask = "0040";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72_I (
+	.dataa(writedata[3]),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~71 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001~I .lut_mask = "0400";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|fullSpeedPol ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.combout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621_I .lut_mask = "0280";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215_I .lut_mask = "AFF5";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308_I .lut_mask = "0280";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620_I .lut_mask = "FF55";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622_I .lut_mask = "FF11";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~617 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~I .lut_mask = "9944";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~617 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~618 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]~618 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~615 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]~615 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~616 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~620 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~622 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]~616 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~52 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~619 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~126 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~127 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector20~128 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01~I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~475 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011~I .lut_mask = "1000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213_I .lut_mask = "8AA2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~211 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~212 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~213 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector19~214 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10~I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]~621 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~301 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~302 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState~303 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00~I .lut_mask = "1101";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011~I .lut_mask = "1000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0]~I (
+	.clk(usbClk),
+	.dataa(USBWireVMI),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0] ),
+	.datad(USBWireVMI),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18_I .lut_mask = "0FF0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1] ),
+	.datac(USBWireVPI),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304_I .lut_mask = "00BE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~75 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~I .lut_mask = "55AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0]~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~74 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1]~74 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~81 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2]~81 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~78 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3]~78 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~80 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4]~80 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~79 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5]~79 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~76 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6]~76 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]~I .lut_mask = "5A5A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229_I .lut_mask = "0140";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230_I .lut_mask = "D4D4";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~230 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[6] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231_I .lut_mask = "0240";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|rxActiveCnt[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~229 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~231 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232_I .lut_mask = "8CCC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1] ),
+	.datad(USBWireVPI),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19_I .lut_mask = "0FF0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~232 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~18 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal0~19 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~I .lut_mask = "BBBA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActiveReg2 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~I .lut_mask = "6666";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]~21 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]~I .lut_mask = "66AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~73 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~I .lut_mask = "55AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0]~73 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~72 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1]~72 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~75 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~76 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2]~77 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3]~76 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~41 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55_I .lut_mask = "EEFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]~I .lut_mask = "99AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649_I .lut_mask = "FF10";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611_I .lut_mask = "FF80";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~651 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Selector2~14 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector58~36 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100~I .lut_mask = "AAEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254_I .lut_mask = "4E4E";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~254 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255_I .lut_mask = "7C38";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~255 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256_I .lut_mask = "FEE0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector8~256 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035_I .lut_mask = "003F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086_I .lut_mask = "EFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001~I .lut_mask = "0AFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~36 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95_I .lut_mask = "808A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector1~95 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~37 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537_I .lut_mask = "FFD0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~537 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|oldRXBits[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530_I .lut_mask = "11E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~530 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528_I .lut_mask = "28CC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~528 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~103 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527_I .lut_mask = "28CC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~527 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add0~104 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529_I .lut_mask = "28CC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXSameBitCount~529 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~822 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~816 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776_I .lut_mask = "00FE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~776 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784_I .lut_mask = "FF07";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~80 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~820 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~817 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~81 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~823 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~819 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~83 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34_I .lut_mask = "EBD7";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~84 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~821 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~86 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~87 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3_I .lut_mask = "0FF0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~34 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|prRxByte_NextState~3 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35_I .lut_mask = "EBFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~789 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~790 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791_I .lut_mask = "FF01";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~781 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~I .lut_mask = "55AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0]~781 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~782 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]~782 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~779 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2]~779 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~780 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]~780 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~783 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4]~783 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~784 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5]~784 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~785 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6]~785 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~786 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7]~786 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~777 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~788 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~791 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~777 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9]~I .lut_mask = "5A5A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398_I .lut_mask = "00F1";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[9] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358_I .lut_mask = "AAA8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418_I .lut_mask = "AAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~96 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97_I .lut_mask = "002A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~418 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419_I .lut_mask = "2FFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011~I .lut_mask = "2000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000~I .lut_mask = "1000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8~I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8~I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8~I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~176 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~179 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~180 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100~I .lut_mask = "1000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173_I .lut_mask = "008A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~172 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174_I .lut_mask = "8AFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~174 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841_I .lut_mask = "02CE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~147 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~148 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~150 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~841 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842_I .lut_mask = "FF51";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector91~32 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En~I .lut_mask = "FFA8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124_I .lut_mask = "1110";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5]~842 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4]~I .lut_mask = "EFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2]~I .lut_mask = "96FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal3~41 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360_I .lut_mask = "88AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244_I .lut_mask = "1110";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~251 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~I .lut_mask = "D5C0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCData[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13]~I .lut_mask = "96FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]~I .lut_mask = "96FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15]~I .lut_mask = "EFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[15] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[13] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[12] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[14] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[11] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[10] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[9] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[8] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~146 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~147 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~148 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~149 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~359 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~360 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal2~150 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361_I .lut_mask = "88A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362_I .lut_mask = "03CF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~361 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRCError ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363_I .lut_mask = "AEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401_I .lut_mask = "00AE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182_I .lut_mask = "AAAF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~358 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1952 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~787 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953_I .lut_mask = "FF51";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~363 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr15~21 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540_I .lut_mask = "1D3F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183_I .lut_mask = "08AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~183 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356_I .lut_mask = "00EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~356 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~357 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~358 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359_I .lut_mask = "AAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector79~359 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|bitStuffError ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~276 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector58~362 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~776 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277_I .lut_mask = "0AEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~277 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Equal0~85 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101~I .lut_mask = "0888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100~I .lut_mask = "AAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010~I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101~I .lut_mask = "22F2";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1081 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5102 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000~I .lut_mask = "0004";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011~I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~140 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~141 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~142 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157_I .lut_mask = "00EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector59~275 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303_I .lut_mask = "A8AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|LessThan0~149 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~421 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306_I .lut_mask = "001D";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~303 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~304 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxOverflow ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~306 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector60~305 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223_I (
+	.datac(address[1]),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225_I (
+	.dataa(address[3]),
+	.datac(address[2]),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75_I .lut_mask = "FF80";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010~I .lut_mask = "30B8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214_I .lut_mask = "FEF2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|NAKRxed ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~213 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1_I .lut_mask = "EFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~358 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359_I .lut_mask = "0ACE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365_I .lut_mask = "AEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137_I .lut_mask = "0ACE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224_I (
+	.dataa(address[2]),
+	.datab(address[1]),
+	.datac(address[0]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75_I (
+	.dataa(address[4]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542_I .lut_mask = "22F2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~542 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~539 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211_I (
+	.dataa(address[4]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17_I (
+	.dataa(address[2]),
+	.datac(address[1]),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector1~14 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3]~I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335_I (
+	.dataa(address[4]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335_I .lut_mask = "FF80";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|stallRxed ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~218 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector62~219 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238_I .lut_mask = "6FF6";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239_I .lut_mask = "6FF6";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~214 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|ACKRxed ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector61~212 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector63~207 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240_I .lut_mask = "6FF6";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333_I (
+	.dataa(writedata[6]),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0]~335 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338_I .lut_mask = "8AAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~338 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|dataSequence ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~339 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~340 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1949 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector64~341 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1950 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[1]~1953 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector4~14 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0]~I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBAddress[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCGlobalEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241_I .lut_mask = "6FFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~238 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~239 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~240 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~241 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~531 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~242 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517_I .lut_mask = "FF50";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38_I (
+	.dataa(write),
+	.datab(chipselect),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381_I .lut_mask = "0800";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(writedata[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "0020";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~1 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~226 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~226 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27_I (
+	.datac(address[2]),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~381 ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~58 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59_I .lut_mask = "8282";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~56 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~57 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Equal1~59 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty~I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382_I .lut_mask = "0200";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(writedata[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "0020";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~1 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~226 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~226 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~382 ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~58 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59_I .lut_mask = "8282";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~56 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~57 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Equal1~59 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty~I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(writedata[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "0010";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~1 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~226 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~226 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~383 ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~58 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59_I .lut_mask = "8282";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~56 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~57 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Equal1~59 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty~I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoEmpty ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoEmpty ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14_I .lut_mask = "B0B5";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384_I .lut_mask = "2000";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(writedata[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~1 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~226 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~226 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~384 ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0]~67 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2]~71 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~58 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59_I .lut_mask = "8282";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~56 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~57 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Equal1~59 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty~I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~14 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoEmpty ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15_I .lut_mask = "34F4";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011~I .lut_mask = "002A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~129 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~128 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010~I .lut_mask = "0F88";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108_I .lut_mask = "88B8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011~I .lut_mask = "8F88";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|WideOr2~28 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097_I .lut_mask = "0EEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~108 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~I .lut_mask = "00EF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001~I .lut_mask = "BBFB";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10~I .lut_mask = "8880";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~51 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~419 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52_I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector5~52 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110~I .lut_mask = "2222";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094_I .lut_mask = "A8A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5093 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5094 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095_I .lut_mask = "EFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5095 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010~I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~35 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|directCntlGnt ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100~I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~86 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector4~36 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector8~87 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01~I .lut_mask = "8880";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.10 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417_I .lut_mask = "AACF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~417 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb~418 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00~I .lut_mask = "5F77";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.01 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50_I .lut_mask = "E8EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|Selector4~50 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|sendPacketGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5096 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5097 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111~I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83_I .lut_mask = "EAEF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector30~83 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127_I .lut_mask = "BA10";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~127 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector31~126 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246_I .lut_mask = "01F1";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~246 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~245 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000~I .lut_mask = "EEAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector8~15 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5098 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010~I .lut_mask = "2222";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|slvSndPkt_NextState~24 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101~I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50_I .lut_mask = "0AEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector14~50 ),
+	.datac(vcc),
+	.aclr(gnd),
+	.sload(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001~I .lut_mask = "22F2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100~I .lut_mask = "AAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~63 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector18~64 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~366 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010~I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector20~43 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~33 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101~I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34_I .lut_mask = "BFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~34 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138_I .lut_mask = "002A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector27~127 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139_I .lut_mask = "0ACE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1139 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|WideOr5~33 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140_I .lut_mask = "00AE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141_I .lut_mask = "03FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1137 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1140 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1141 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142_I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1138 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110~I .lut_mask = "00EF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal5~53 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~361 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~360 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~362 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~359 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~363 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector21~364 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468_I .lut_mask = "FF50";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~468 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29_I .lut_mask = "EFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[3]~115 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector0~14 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4]~I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001~I .lut_mask = "4F44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378_I .lut_mask = "FF50";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~181 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~182 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus~183 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~378 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~469 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector12~37 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010~I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~572 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573_I .lut_mask = "FFD0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError~I .lut_mask = "88D8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError~I .lut_mask = "88D8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375_I .lut_mask = "0100";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375 ),
+	.datab(writedata[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \strobe_i~19_I (
+	.dataa(chipselect),
+	.datab(write),
+	.datac(read),
+	.combout(\strobe_i~19 ));
+defparam \strobe_i~19_I .operation_mode = "normal";
+defparam \strobe_i~19_I .synch_mode = "off";
+defparam \strobe_i~19_I .register_cascade_mode = "off";
+defparam \strobe_i~19_I .sum_lutc_input = "datac";
+defparam \strobe_i~19_I .lut_mask = "A8A8";
+defparam \strobe_i~19_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\strobe_i~19 ),
+	.datac(address[1]),
+	.datad(write),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~375 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~223 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~223 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50_I .lut_mask = "0006";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~50 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~51 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~52 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~53 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379_I .lut_mask = "0400";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(writedata[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~379 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~223 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~223 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50_I .lut_mask = "0006";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~50 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~51 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~52 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~53 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376_I .lut_mask = "0040";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376 ),
+	.datab(writedata[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~376 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~223 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~223 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50_I .lut_mask = "0006";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~50 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~51 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~52 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~53 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|fifoFull ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|fifoFull ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374_I .lut_mask = "1000";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374 ),
+	.datab(writedata[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~374 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~223 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~223 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50_I .lut_mask = "0006";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~50 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~51 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~52 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~53 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|fifoFull ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~27 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|fifoFull ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector13~37 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001~I .lut_mask = "BAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168_I .lut_mask = "ABEF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~525 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~167 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~168 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector21~169 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177_I .lut_mask = "ACFC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~177 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~178 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179_I .lut_mask = "EEE2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector22~179 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384_I .lut_mask = "0AAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~384 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385_I .lut_mask = "EEE0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|sendPacketRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386_I .lut_mask = "EEE0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387_I .lut_mask = "EAEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~387 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388_I .lut_mask = "AAEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~385 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~386 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~388 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector17~389 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy~I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP1Rdy ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datac(writedata[1]),
+	.datad(address[4]),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP1ReadySTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SetReady ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy~I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP2Rdy ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(writedata[1]),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP2ReadySTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SetReady ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy~I .lut_mask = "AAAC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP0Rdy ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datac(writedata[1]),
+	.datad(address[4]),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP0ReadySTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SetReady ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy~I .lut_mask = "ACCC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|clrEP3Rdy ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~226 ),
+	.datac(writedata[1]),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady~I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrEP3ReadySTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SetReady ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector3~14 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1]~I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~49 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector2~50 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011~I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129_I .lut_mask = "0888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130_I .lut_mask = "A8AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131_I .lut_mask = "A8AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132_I .lut_mask = "A8AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~129 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~130 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~131 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector9~132 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101~I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142_I .lut_mask = "AAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~142 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~143 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXStreamStatus[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~84 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Selector16~144 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~574 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242_I .lut_mask = "AAAE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~242 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~243 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~244 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~I .lut_mask = "00FE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111~I .lut_mask = "BFBB";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXPacketRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~243 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133_I .lut_mask = "8880";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1133 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136_I .lut_mask = "0007";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471_I .lut_mask = "AAFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1136 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1142 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0]~471 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011~I .lut_mask = "08AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp[5]~642 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1144 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl~1130 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100~I .lut_mask = "5444";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~237 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|slvCntrl_NextState~17 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203_I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~202 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204_I .lut_mask = "AAA8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~203 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~204 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.10011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector26~205 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|getPacketREn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~526 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~527 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt~528 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101~I .lut_mask = "000E";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|SIERxTimeOutEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always1~304 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~225 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireEdgeDetect ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226_I .lut_mask = "FFFD";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~210 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~I .lut_mask = "55AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]~210 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]~211 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]~212 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~224 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]~224 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~213 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]~213 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]~215 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]~214 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~216 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]~216 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]~217 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]~209 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10]~218 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~219 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11]~219 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12]~220 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~221 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~222 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13]~226 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14]~222 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15]~I .lut_mask = "5A5A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~172 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~173 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~174 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~175 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~176 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal7~81 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal6~177 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~157 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~158 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~I .lut_mask = "00FE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111~I .lut_mask = "DFDD";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~442 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~443 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector11~37 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010~I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001~I .lut_mask = "EEAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377_I .lut_mask = "0004";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377 ),
+	.datab(writedata[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn~I .lut_mask = "8ACE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]~67 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]~69 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~23 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~377 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~223 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~223 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59_I .lut_mask = "0006";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~59 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~60 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~61 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~62 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector2~40 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011~I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~179 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~441 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180_I .lut_mask = "FFD0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endpCRCTemp~530 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001~I .lut_mask = "BAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165_I .lut_mask = "AAA8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130_I .lut_mask = "0888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131_I .lut_mask = "A8AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132_I .lut_mask = "A8AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133_I .lut_mask = "A8AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~130 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~131 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~132 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector8~133 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101~I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116_I .lut_mask = "AAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~165 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~452 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~116 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~117 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100~I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_NAKRxed~10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed~I .lut_mask = "A0E4";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_stallRxed~10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed~I .lut_mask = "A0E4";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError~I .lut_mask = "88D8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError~I .lut_mask = "88D8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector12~37 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~152 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153_I .lut_mask = "AAA8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~153 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt~440 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector16~115 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector20~154 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163_I .lut_mask = "ACFC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~163 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164_I .lut_mask = "EEE2";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Selector21~164 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~342 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010~I .lut_mask = "44F4";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186_I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~185 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~186 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|NextState_hstCntrl~343 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector22~187 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|transDone ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq~I (
+	.clk(clk),
+	.dataa(writedata[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~202 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq~I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1083 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010~I .lut_mask = "08A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1064 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087_I .lut_mask = "EFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector39~143 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088_I .lut_mask = "88AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1086 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1087 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1088 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089_I .lut_mask = "AABF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1068 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1069 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1080 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1084 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1090 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1091 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1089 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1092 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000~I .lut_mask = "80BF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001~I .lut_mask = "DDFD";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~353 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01~I .lut_mask = "8880";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354_I .lut_mask = "AACF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~354 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb~355 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10~I .lut_mask = "5F77";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63_I .lut_mask = "E8EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|Selector5~63 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|Equal0~72 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125_I .lut_mask = "03FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126_I .lut_mask = "0888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1125 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1126 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1128 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1129 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010~I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1121 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx~1122 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|next_SOFTimerClr~118 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011~I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|LessThan1~254 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1070 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl~1071 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector38~104 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC~I .lut_mask = "F2AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000~I .lut_mask = "BBFB";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketWEnable~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103_I .lut_mask = "028A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5103 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001~I .lut_mask = "2222";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~34 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr0~35 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP~409 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010~I .lut_mask = "00A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5104 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100~I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~165 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166_I .lut_mask = "2AEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector43~166 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[0]~17 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121_I .lut_mask = "0010";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~121 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120_I .lut_mask = "EACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector41~120 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~I .lut_mask = "00FE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~232 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~233 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234_I .lut_mask = "EACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector42~234 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|next_sendPacketPID~11 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|sendPacketPID[1]~18 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~189 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191_I .lut_mask = "08AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~191 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~190 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|Selector40~192 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]~421 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3]~I .lut_mask = "1F11";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~521 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011~I .lut_mask = "2EAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~20 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt~522 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sndPkt_NextState~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101~I .lut_mask = "E2AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380_I (
+	.dataa(address[4]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I (
+	.clk(clk),
+	.dataa(writedata[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Equal0~17 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmpty ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClkFirst ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always2~1 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~226 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225_I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~226 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~214 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~213 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~214 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~220 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~219 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~220 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~211 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~210 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~211 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~208 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207_I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~207 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|always0~38 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Decoder0~380 ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn~I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]~70 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~68 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]~68 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~69 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]~69 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]~65 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~208 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~223 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222_I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222_I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~222 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~223 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216_I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216_I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~216 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]~66 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~71 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|always0~0 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]~71 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58_I .lut_mask = "8241";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~57 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~58 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11_I .lut_mask = "8200";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Equal1~56 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~11 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Equal0~21 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61_I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector15~61 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110~I .lut_mask = "FF44";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091_I .lut_mask = "0777";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5090 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101~I .lut_mask = "2222";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector17~67 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110~I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5092 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000~I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~79 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~80 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector14~81 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50_I .lut_mask = "0AEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector23~50 ),
+	.datac(vcc),
+	.aclr(gnd),
+	.sload(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|WideOr13~10 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~37 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|Selector15~38 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn~I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010~I .lut_mask = "0F88";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114_I .lut_mask = "88B8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~114 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5091 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~I .lut_mask = "00EF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001~I .lut_mask = "DDFD";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010~I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56_I .lut_mask = "88EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector22~56 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126_I .lut_mask = "0BBB";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~125 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~126 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~127 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~I .lut_mask = "00EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010~I .lut_mask = "8F88";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011~I .lut_mask = "EEAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328_I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl~328 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001~I .lut_mask = "000B";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100~I .lut_mask = "A088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~345 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~346 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb~347 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001~I .lut_mask = "13DF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~61 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~62 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001~I .lut_mask = "DDFD";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5089 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110~I .lut_mask = "2222";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~123 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~522 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector9~124 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|Selector24~60 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104_I .lut_mask = "FFD0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10~I .lut_mask = "0101";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288 ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222_I .lut_mask = "0010";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~30 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~222 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223_I .lut_mask = "5850";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~223 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224_I .lut_mask = "3FF2";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector25~224 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl~104 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00~I .lut_mask = "5511";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~288 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289 ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.combout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470_I .lut_mask = "AAA8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265_I .lut_mask = "FFE4";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1]~I .lut_mask = "5555";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167_I .lut_mask = "0AAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25_I .lut_mask = "AFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168_I .lut_mask = "AAAE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~167 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~168 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169_I .lut_mask = "AAEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector40~169 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|CurrState_SCTxArb.00 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn~I .lut_mask = "0EAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135_I .lut_mask = "ACEC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|Selector23~135 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267_I .lut_mask = "EEE0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268_I .lut_mask = "00AF";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~267 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~268 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector39~269 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135_I .lut_mask = "ACEC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector23~135 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~596 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~597 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt~381 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortCntl[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortCntl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]~I .lut_mask = "EEAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234_I .lut_mask = "ACFC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~233 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~234 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235_I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~235 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~623 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~622 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~624 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625_I .lut_mask = "EEE2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_SIEPortCtrl~625 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector107~274 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr2~29 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121_I .lut_mask = "028A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector34~121 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7]~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099_I .lut_mask = "003D";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3762 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101~I .lut_mask = "1500";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304_I .lut_mask = "03C3";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3764 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011~I .lut_mask = "0015";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]~I .lut_mask = "04AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]~I .lut_mask = "28EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Add0~38 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr37~14 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]~I .lut_mask = "28EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1381 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110~I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305_I .lut_mask = "AEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~304 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~305 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~306 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11~I .lut_mask = "0A88";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~131 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb~132 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01~I .lut_mask = "13DF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~60 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector5~61 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000~I .lut_mask = "F444";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010~I .lut_mask = "FF44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011~I .lut_mask = "FF44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783_I .lut_mask = "FF55";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~784 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785_I .lut_mask = "FF53";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~767 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0]~767 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~768 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1]~768 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~769 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~769 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~770 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[3]~770 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~771 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4]~771 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~772 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5]~772 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~773 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6]~773 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~774 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[7]~774 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~775 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8]~775 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~777 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9]~777 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~776 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10]~776 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~778 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[8] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[10] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[9] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[11]~778 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~779 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12]~779 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~780 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13]~780 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~781 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~783 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[2]~785 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14]~781 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15]~I .lut_mask = "5A5A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[12] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[13] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[14] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|resumeCnt[15] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~154 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~155 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~156 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~157 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100~I .lut_mask = "1100";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763_I .lut_mask = "99AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735_I .lut_mask = "0AA2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3763 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100~I .lut_mask = "1000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1382 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011~I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1383 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0]~I .lut_mask = "5100";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~I .lut_mask = "08A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647_I .lut_mask = "000B";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]~I .lut_mask = "7080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i~647 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Add0~103 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]~I .lut_mask = "2888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit~I .lut_mask = "AEAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~37 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector88~38 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En~I .lut_mask = "FFEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~192 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2]~I .lut_mask = "ACCC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124_I .lut_mask = "BFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~124 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125_I .lut_mask = "AAFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190_I .lut_mask = "88AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~190 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|Equal0~125 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~I .lut_mask = "AEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010~I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110~I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524_I .lut_mask = "FFE0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~89 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~I .lut_mask = "6688";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]~89 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~91 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]~91 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~93 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]~93 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~94 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]~94 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~95 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]~95 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~96 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]~96 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~97 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]~97 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~98 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]~98 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~88 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]~88 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~90 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[1]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptySyncToUsbClk ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198_I (
+	.dataa(address[0]),
+	.datab(address[1]),
+	.datac(address[2]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198_I .lut_mask = "0010";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~198 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197_I (
+	.dataa(address[0]),
+	.datab(address[1]),
+	.datac(address[2]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197_I .lut_mask = "0020";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~197 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1505 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1506 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1507 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|Selector41~232 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509_I .lut_mask = "0100";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|WideOr14~25 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1509 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510_I .lut_mask = "FCF8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1508 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524_I .lut_mask = "FFE0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[1]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[1]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[1]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[1]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|fifoReadEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|always2~0 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|fifoREnDelayed ),
+	.combout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1267 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1268 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1744 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1745 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]~251 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~524 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[0]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1515 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1516 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1517 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1518 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5]~300 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|TxLineState[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~524 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[0]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[0]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[0]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[0]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1273 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1274 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortData[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1749 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1750 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3757 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111~I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3759 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101~I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724_I .lut_mask = "0ACE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3724 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726_I .lut_mask = "AAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal13~158 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001~I .lut_mask = "F022";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101~I .lut_mask = "FF44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110~I .lut_mask = "FF44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3719 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3720 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~159 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3734 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3745 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100~I .lut_mask = "1500";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3731 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3732 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3735 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736_I .lut_mask = "002A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746_I .lut_mask = "7777";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3761 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000~I .lut_mask = "1000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3752 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001~I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~97 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~98 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector79~99 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242_I .lut_mask = "FFFC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0]~I .lut_mask = "0101";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]~I .lut_mask = "0880";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]~I .lut_mask = "0110";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Add0~104 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]~I .lut_mask = "0888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22_I .lut_mask = "BFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En~I .lut_mask = "AEAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156_I .lut_mask = "88AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~156 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|Equal0~22 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~I .lut_mask = "AEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3726 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3725 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727_I .lut_mask = "2AAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728_I .lut_mask = "A8A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3728 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100_I .lut_mask = "AAFC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5099 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3733 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101_I .lut_mask = "ACFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal12~37 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5101 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~I .lut_mask = "2222";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751_I .lut_mask = "003F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3751 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3755 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3753 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101~I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010~I .lut_mask = "EFEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~25 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26_I .lut_mask = "DFDF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600_I .lut_mask = "FFD0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl~601 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1]~I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[2]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[2]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[2]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[2]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1270 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1271 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]~90 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]~I .lut_mask = "A5A5";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[2]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1511 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1512 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1513 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1514 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1747 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]~I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[3]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[3]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[3]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[3]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1276 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall~211 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2ControlReg[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0ControlReg[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~75 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1ControlReg[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Selector2~14 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3ControlReg[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2]~I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endPControlReg[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~517 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_sendPacketPID~273 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481_I .lut_mask = "88FC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal2~32 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal3~30 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal4~18 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~482 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483_I .lut_mask = "D0D0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~483 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484_I .lut_mask = "EC4C";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~481 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~484 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485_I .lut_mask = "FECC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector28~485 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1277 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520_I .lut_mask = "AAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521_I .lut_mask = "DAD0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[3]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1521 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522_I .lut_mask = "F2C2";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523_I .lut_mask = "AAAE";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1522 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1752 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3]~I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471_I .lut_mask = "0028";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal0~38 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~471 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~470 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~472 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector127~473 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~160 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector57~161 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteFullSpeedRate~11 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate~I .lut_mask = "F808";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011~I .lut_mask = "22E2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137_I .lut_mask = "808A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector66~137 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19_I .lut_mask = "0FFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296_I .lut_mask = "0BFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~307 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~296 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~297 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~308 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~19 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309_I .lut_mask = "0BFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~309 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector72~295 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector73~310 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175_I .lut_mask = "AAA8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~526 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527_I .lut_mask = "FF51";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0]~I .lut_mask = "1100";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1]~I .lut_mask = "0028";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2]~I .lut_mask = "0220";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i~525 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add0~103 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~527 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~I .lut_mask = "2888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[7]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[7]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[7]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[7]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1288 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1289 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7]~I .lut_mask = "008B";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]~207 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534_I .lut_mask = "D0DA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[7]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1534 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535_I .lut_mask = "F2C2";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1535 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1760 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7]~I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7]~I .lut_mask = "4F44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244_I .lut_mask = "1110";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC16En ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~251 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~I .lut_mask = "BA30";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[6]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[6]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[6]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[6]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1285 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1286 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~I .lut_mask = "008B";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~333 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531_I .lut_mask = "0E5E";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[6]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1531 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1532 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1758 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6]~I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6]~I .lut_mask = "4F44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[5]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[5]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[5]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[5]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1282 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1283 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5]~I .lut_mask = "008B";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB~332 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528_I .lut_mask = "D0DA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[5]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1528 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529_I .lut_mask = "F2C2";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1529 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1756 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5]~I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]~I .lut_mask = "4F44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[4]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_7|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[4]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_6|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[4]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_5|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|TxFifo:EP1TxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP0TxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[4]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~227 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|Add2~218 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_8|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:EP2TxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1279 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:EP3TxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData~1280 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|sendPacketPID[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1266 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1265 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4]~I .lut_mask = "008B";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~331 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1519 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525_I .lut_mask = "0E5E";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(clk),
+	.clk1(usbClk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|fifoWEn ),
+	.portadatain({writedata[4]}),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~209 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~212 ,
+\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|Add2~227 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_9|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]~12 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1520 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1525 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData~1526 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[5]~1523 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]~1510 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~595 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData~1754 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~600 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4]~I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]~I .lut_mask = "4F44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]~I .lut_mask = "2F22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]~I .lut_mask = "2F22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]~I .lut_mask = "22F2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr31~2 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr30~1 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]~I .lut_mask = "22F2";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~244 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]~I .lut_mask = "96FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]~I .lut_mask = "96FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|data[7]~242 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]~I .lut_mask = "EFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819_I .lut_mask = "AAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832_I .lut_mask = "EAEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1832 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833_I .lut_mask = "7A70";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124_I .lut_mask = "1110";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~124 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC~111 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]~I .lut_mask = "96FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]~I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|data[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]~I .lut_mask = "EFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1833 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834_I .lut_mask = "C1F1";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr22~18 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813_I .lut_mask = "FF74";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1834 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByte~26 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7]~I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1829 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830_I .lut_mask = "5B0B";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1830 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831_I .lut_mask = "34F4";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1831 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056_I .lut_mask = "AAAF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064_I .lut_mask = "FF0D";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1826 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827_I .lut_mask = "7A70";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1827 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828_I .lut_mask = "C1F1";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1828 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1823 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824_I .lut_mask = "5B0B";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1824 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825_I .lut_mask = "34F4";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1825 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1819 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1820 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821_I .lut_mask = "7A70";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[4]~1818 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1821 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822_I .lut_mask = "C1F1";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1822 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816_I .lut_mask = "0AFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1816 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2]~I .lut_mask = "08A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814_I .lut_mask = "0AFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1814 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1]~I .lut_mask = "08A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811_I .lut_mask = "0AFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1810 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut~1811 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~1813 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~I .lut_mask = "08A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOut[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1056 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[4]~1064 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~940 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941_I .lut_mask = "8ACF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437_I .lut_mask = "FFF0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0]~I .lut_mask = "1000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1]~I .lut_mask = "0AA0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2]~I .lut_mask = "7080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount~436 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Add1~103 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~437 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~I .lut_mask = "2888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174_I .lut_mask = "88A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~174 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~175 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|i[3]~524 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176_I .lut_mask = "EAFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector60~176 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal3~28 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Equal2~35 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011~I .lut_mask = "2232";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~49 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]~I .lut_mask = "F808";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~47 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7]~I .lut_mask = "F808";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|next_TxByteCtrl~48 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]~I .lut_mask = "F808";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~957 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80_I .lut_mask = "A8AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~80 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001~I .lut_mask = "FFFD";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector4~32 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq~I .lut_mask = "FAF8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10~I .lut_mask = "A8A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56_I .lut_mask = "88EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|Selector4~56 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960_I .lut_mask = "08F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~960 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000~I .lut_mask = "002A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|prcTxByteGnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector62~79 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~132 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387_I .lut_mask = "00BF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~955 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~39 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956_I .lut_mask = "0AEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|prcTxB_NextState~1 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111~I .lut_mask = "3A0A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154_I .lut_mask = "AAEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~154 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~954 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB~956 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~I .lut_mask = "00EF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|processTxByteWEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy~I .lut_mask = "08F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100~I .lut_mask = "8F88";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|processTxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000~I .lut_mask = "BBAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2]~599 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr36~26 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171_I .lut_mask = "0ACE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~171 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|LineDirectControlEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001~I .lut_mask = "DDFD";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~127 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128_I .lut_mask = "A8AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~128 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|CurrState_slvDrctCntl.100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|Selector9~129 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.1100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|CurrState_slvSndPkt.0110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~136 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~137 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortData[6]~1264 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|Selector16~138 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveDirectControl:u_slaveDirectControl|SCTxPortWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveSendPacket:u_slaveSendPacket|SCTxPortWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|SCTxPortArbiter:u_SCTxPortArbiter|muxDCEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290 ));
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170_I .lut_mask = "028A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Equal7~16 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector77~303 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204_I .lut_mask = "EAFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~204 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~205 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector56~206 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~289 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~290 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723_I .lut_mask = "EBEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector50~159 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3723 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011~I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3727 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3729 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730_I .lut_mask = "EEEF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3730 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3736 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010~I .lut_mask = "80BF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx~3721 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~121 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122_I .lut_mask = "AAFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector78~122 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127_I .lut_mask = "0EEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~129 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~127 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~130 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~131 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.01 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB~I .lut_mask = "0EAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299_I .lut_mask = "01AB";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~299 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01~I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292_I .lut_mask = "AFFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]~I .lut_mask = "1111";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always0~0 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]~I .lut_mask = "1441";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~300 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal1~9 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00~I .lut_mask = "5101";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368_I .lut_mask = "00BF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~368 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState~298 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369_I .lut_mask = "A8FD";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~369 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.00 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370_I .lut_mask = "2EEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector3~370 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001110 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111~I .lut_mask = "FF44";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|SIEPortWEnToSIE~291 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573_I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|next_USBWireFullSpeedRate~162 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~574 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575_I .lut_mask = "88B8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~573 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector91~170 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~575 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector128~576 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireFullSpeedRate ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|TxFSRate~10 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10~I .lut_mask = "1000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt~I .lut_mask = "00EA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|incBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345_I .lut_mask = "BDFC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Add0~345 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~292 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~I .lut_mask = "5005";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~198 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~17 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|Selector76~199 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector5~128 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378_I .lut_mask = "AAFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379_I .lut_mask = "AAAF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~376 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~377 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16_I .lut_mask = "BFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~378 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~379 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|Selector3~380 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireCtrl ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0]~I .lut_mask = "35CA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|USBWireWEn~10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~61 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~I .lut_mask = "66AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|always3~135 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201_I .lut_mask = "FF50";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferCnt[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]~I .lut_mask = "01FE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]~I .lut_mask = "66AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666_I .lut_mask = "FF10";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferInIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Selector0~54 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539_I .lut_mask = "FF80";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~668 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~59 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~60 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]~I .lut_mask = "9999";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~613 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~650 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~507 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~508 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~38 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]~I .lut_mask = "F808";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~473 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101~I .lut_mask = "03AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132_I .lut_mask = "BBB8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~132 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~I .lut_mask = "3232";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|oldRxBitsIn[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[2]~612 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~614 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~649 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer2[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer0~648 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[1]~611 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer1[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~504 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|buffer3[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut~505 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1]~506 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RxBits~39 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]~I .lut_mask = "F808";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~815 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39_I .lut_mask = "E000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_bitStuffError~39 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError~I .lut_mask = "D888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288_I .lut_mask = "8008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~587 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~288 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~289 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector31~290 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178_I .lut_mask = "00EE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~588 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0001 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589_I .lut_mask = "0ACE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~589 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591_I .lut_mask = "FF0D";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~I .lut_mask = "0028";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]~I .lut_mask = "0220";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit~469 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Add1~104 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]~591 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]~I .lut_mask = "2888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~71 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175_I .lut_mask = "ABFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176_I .lut_mask = "EFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177_I .lut_mask = "BFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~177 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~178 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179_I .lut_mask = "EAFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181_I .lut_mask = "0AEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~175 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~176 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~179 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~181 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~182 ),
+	.datac(vcc),
+	.aclr(gnd),
+	.sload(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive~1 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal4~42 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal3~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt~I .lut_mask = "5044";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229_I .lut_mask = "AFFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0]~I .lut_mask = "1111";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|always0~0 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~I .lut_mask = "1441";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|incBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344_I .lut_mask = "BDFC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Add0~344 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]~229 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]~I .lut_mask = "5005";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00~I .lut_mask = "1101";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|Equal5~17 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01~I .lut_mask = "11F1";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt~I .lut_mask = "A8EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110~I .lut_mask = "00A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000~I .lut_mask = "F222";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr5~28 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230_I .lut_mask = "AEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~230 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|prRxBit_NextState~5 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231_I .lut_mask = "AAAE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~231 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector63~232 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~159 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~160 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161_I .lut_mask = "88FA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector0~161 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector81~173 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~168 ),
+	.datac(vcc),
+	.aclr(gnd),
+	.sload(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|bitStuffError ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110~I .lut_mask = "F222";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector48~180 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16_I .lut_mask = "0FFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr2~16 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217_I .lut_mask = "0EFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~775 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|processRxByteRdy ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~217 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218_I .lut_mask = "EAC8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector7~218 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxCtrl~35 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Decoder2~422 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector93~32 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En~I .lut_mask = "FFA8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156_I .lut_mask = "88AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~156 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|Equal0~22 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~I .lut_mask = "AEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1036 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110~I .lut_mask = "7000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector57~119 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~393 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394_I .lut_mask = "0E1F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1039 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~177 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector52~178 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|WideOr8 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal5~36 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~395 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396_I .lut_mask = "EAE0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~394 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~396 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000~I .lut_mask = "3131";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector104~167 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1030 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1031 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032_I .lut_mask = "FFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1032 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101~I .lut_mask = "0015";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Equal1~35 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[8]~792 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC~I .lut_mask = "CE8A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0]~I .lut_mask = "5100";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]~I .lut_mask = "08A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643_I .lut_mask = "000B";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]~I .lut_mask = "7080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i~643 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Add0~103 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|CRCResult[3]~603 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]~I .lut_mask = "2888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RXByteStMachCurrState~78 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit~I .lut_mask = "ECA8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~192 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2]~I .lut_mask = "ACCC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124_I .lut_mask = "BFFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~124 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125_I .lut_mask = "AAFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190_I .lut_mask = "88AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~190 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|Equal0~125 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC~175 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~I .lut_mask = "AEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1029 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1033 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011~I .lut_mask = "0100";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~95 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~97 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98_I .lut_mask = "EEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector29~98 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal1~13 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal3~42 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|next_RXByte~818 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|WideOr9~7 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]~I .lut_mask = "A0EC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[4]~784 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxDataOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|next_RxByte~82 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]~I .lut_mask = "E4A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState~398 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101~419 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1034 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte~1035 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165_I .lut_mask = "7000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~165 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5086 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~I .lut_mask = "88F0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~540 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541_I .lut_mask = "E0FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector65~541 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~401 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector73~182 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|Selector80~402 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|slvGetPkt_NextState~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.10001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001~I .lut_mask = "EEAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18_I .lut_mask = "AAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_RXFifoWEn~18 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn~I .lut_mask = "A0E4";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoWEn ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|Selector9~28 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697_I .lut_mask = "FAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|Equal3~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642_I .lut_mask = "FAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|always2~24 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .lut_mask = "66DD";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|always2~13 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .lut_mask = "66DD";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~737 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739_I (
+	.dataa(address[1]),
+	.datab(address[0]),
+	.datad(address[2]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739_I .lut_mask = "0099";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~738 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|always2~13 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .lut_mask = "66DD";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505_I .lut_mask = "FF50";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664_I .lut_mask = "FAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~85 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635_I .lut_mask = "FAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|always2~13 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .lut_mask = "66DD";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~741 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~742 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196_I (
+	.dataa(address[0]),
+	.datab(address[1]),
+	.datac(address[2]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196_I .lut_mask = "0200";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~196 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203_I (
+	.dataa(address[0]),
+	.datab(address[1]),
+	.datac(address[2]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203_I .lut_mask = "0100";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq~I (
+	.clk(clk),
+	.dataa(writedata[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq~I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInSTB ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|Equal3~84 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~398 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~99 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[8] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~103 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~102 ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~104 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100~I .lut_mask = "7777";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101~I .lut_mask = "00EF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~80 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1]~I .lut_mask = "F808";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsOut[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RxBits~79 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0]~I .lut_mask = "F808";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183_I .lut_mask = "F854";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181_I .lut_mask = "AFFA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450_I .lut_mask = "A8A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43_I .lut_mask = "EEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177_I .lut_mask = "0FF0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448_I .lut_mask = "EEE0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~448 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449_I .lut_mask = "000B";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~451 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452_I .lut_mask = "AEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~450 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~452 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~453 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079_I .lut_mask = "00A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082_I .lut_mask = "28FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083_I .lut_mask = "AAEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5082 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5083 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101~I .lut_mask = "0100";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~559 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~449 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560_I .lut_mask = "0EFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~560 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561_I .lut_mask = "EAC8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562_I .lut_mask = "0AAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~561 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~562 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector5~563 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5084 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110~I .lut_mask = "0100";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179_I .lut_mask = "0003";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105_I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5079 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080_I .lut_mask = "8AFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5105 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5080 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081_I .lut_mask = "FEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010~I .lut_mask = "4400";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491_I .lut_mask = "AFF6";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1181 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~491 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|WideOr1~7 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182_I .lut_mask = "0ACE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1183 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1182 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184_I .lut_mask = "F0F1";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~1172 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~I .lut_mask = "55AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]~1172 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~1173 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]~1173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~1174 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]~1174 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1171 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1171 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~1175 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]~1175 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~1176 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~I .lut_mask = "5A5F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]~1176 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~1177 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~I .lut_mask = "A50A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1184 ),
+	.cin(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]~1177 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7]~I .lut_mask = "5A5A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324_I .lut_mask = "07FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325_I .lut_mask = "008F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~324 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~325 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326_I .lut_mask = "888A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327_I .lut_mask = "03AB";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|next_RXStMachCurrState~177 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328_I .lut_mask = "035F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128_I .lut_mask = "003F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~327 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~328 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~128 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329_I .lut_mask = "8088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~326 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector8~329 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~I .lut_mask = "1515";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011~I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101011~5081 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001~I .lut_mask = "2200";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|decBufferCnt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0100 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~452 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr~453 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0011 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000~I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1179 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180_I .lut_mask = "FF75";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]~1180_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102_I .lut_mask = "0002";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~446 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState~490 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440_I .lut_mask = "AEEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0100 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0010 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442_I (
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.1000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0111 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442_I .lut_mask = "000F";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~441 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~442 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal3~43 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443_I .lut_mask = "88A8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector4~447 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~440 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444_I .lut_mask = "EAEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~444 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106_I (
+	.dataa(address[1]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[0] ),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~100 ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~105 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~106 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CRCError ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82_I .lut_mask = "0ABB";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector1~82 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17_I .lut_mask = "FEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|next_endPMuxErrorsWEn~17 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn~I .lut_mask = "A0E4";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[0] ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Enable ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Enable ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NextState_slvCntrl~365 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520_I .lut_mask = "FF50";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0]~I .lut_mask = "F6FF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495_I (
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495_I .lut_mask = "FFC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPControlRegCopy[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.01000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~494 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402_I .lut_mask = "FF40";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~72 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638_I .lut_mask = "FF10";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[0] ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~71 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360_I .lut_mask = "FF80";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[0] ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~112 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[0] ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Enable ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~170 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Enable ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~114 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116_I (
+	.dataa(address[2]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~113 ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~115 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~69 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360_I .lut_mask = "FF80";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~637 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[0] ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|Decoder0~70 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360_I .lut_mask = "FF80";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~401 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[0] ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~117 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~111 ),
+	.datab(address[2]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~116 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~118 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector7~107 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~119 ),
+	.datac(address[6]),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746_I .lut_mask = "FF50";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~745 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[0] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~113 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[8] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~745 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[8] ),
+	.datac(address[0]),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49_I (
+	.dataa(address[1]),
+	.datab(address[4]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49 ),
+	.datac(writedata[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|transDone ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrTransDoneReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInSTB ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120_I (
+	.dataa(address[1]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48_I (
+	.dataa(address[4]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887_I (
+	.dataa(address[1]),
+	.datab(address[0]),
+	.datad(address[2]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275_I .lut_mask = "FF80";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB~143 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt ),
+	.datab(address[1]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~120 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~746 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector7~121 ),
+	.datad(address[2]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748_I (
+	.dataa(address[6]),
+	.datab(address[4]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~744 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~747 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749_I .lut_mask = "EAEA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750_I (
+	.dataa(address[7]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~743 ),
+	.datac(address[5]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~749 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .lut_mask = "66DD";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[0] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[0] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a0 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|always2~13 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|RxfifoBI:u_RxfifoBI|forceEmptyShift[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751_I (
+	.dataa(address[1]),
+	.datab(address[2]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751_I .lut_mask = "3120";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752_I (
+	.dataa(address[6]),
+	.datab(address[0]),
+	.datac(address[4]),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752_I .lut_mask = "F9FC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~751 ),
+	.datac(address[6]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~752 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~740 ),
+	.datab(address[7]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~750 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~753 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856_I (
+	.dataa(address[6]),
+	.datab(address[0]),
+	.datac(address[7]),
+	.datad(address[5]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856_I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~39 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector6~40 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2861 ),
+	.datac(address[7]),
+	.datad(address[6]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[1] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[1] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a1 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[0]~31 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[1] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~39 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2862 ),
+	.datab(address[7]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector6~40 ),
+	.datad(address[5]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863_I .lut_mask = "AAC0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2863 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864_I .lut_mask = "00EA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~747 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[9] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[9] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[1] ),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~748 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2865 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[1] ),
+	.datac(address[1]),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RxBits[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~102 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~103 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416_I .lut_mask = "BFFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|CurrState_rcvr.0001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~416 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector18~443 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417_I .lut_mask = "EAFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Equal1~104 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~415 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~417 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|Selector17~418 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(writedata[1]),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0000 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal0~215 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309_I .lut_mask = "AEFE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Equal7~53 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~308 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~309 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|Selector17~310 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeDetected ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldResumeDetected ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resumeIntOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2866 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~111 ),
+	.datad(address[2]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB~16 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datab(writedata[1]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq~I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeIntInSTB ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198_I (
+	.dataa(address[1]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1] ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~400 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[1] ),
+	.datab(address[1]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~198 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~200 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~202 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ),
+	.datac(address[0]),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~201 ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~203 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205_I (
+	.dataa(address[1]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[9] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB[1] ),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~199 ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~204 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~205 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte[0] ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~520 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~I .lut_mask = "0100";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|tempUSBEndPTransTypeReg[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[0]~495 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2TransTypeReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1TransTypeReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1TransTypeRegSTB[1] ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0TransTypeRegSTB[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg~639 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3TransTypeReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2TransTypeRegSTB[1] ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~112 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3TransTypeRegSTB[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|bitStuffError ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[1] ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~171 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[1] ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~114 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1Ready ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0Ready ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2Ready ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~116 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3Ready ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118_I (
+	.dataa(address[1]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~115 ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~117 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPTransTypeReg~496 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~498 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndPNakTransTypeReg[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~360 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2NAKTransTypeReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~360 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1NAKTransTypeReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~402 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP1NAKTransTypeRegSTB[1] ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP0NAKTransTypeRegSTB[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0NAKTransTypeReg~403 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~360 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3NAKTransTypeReg[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP2NAKTransTypeRegSTB[1] ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~119 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|endP3NAKTransTypeRegSTB[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~113 ),
+	.datab(address[1]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~118 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~120 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector6~206 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector6~121 ),
+	.datac(address[6]),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2864 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2867 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2868 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~679 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~680 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~470 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~682 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~683 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datab(writedata[2]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq~I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|oldConnectState[1] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut~I .lut_mask = "6FF6";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveRxStatusMonitor:u_slaveRxStatusMonitor|resetEventOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138_I (
+	.dataa(address[1]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2] ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~401 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2] ),
+	.datab(address[1]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~138 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~140 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB ),
+	.datac(address[1]),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~141 ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~142 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144_I (
+	.dataa(address[1]),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~139 ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~143 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~144 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~749 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[10] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB~108 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[10] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2] ),
+	.datac(address[1]),
+	.datad(address[2]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685_I .lut_mask = "0AC0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~750 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(writedata[2]),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResetReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInSTB ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[2] ),
+	.datab(address[1]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt ),
+	.datad(address[2]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686_I .lut_mask = "BBC0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[2] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~686 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687_I .lut_mask = "FA0C";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~685 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~687 ),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXOverflow ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3DataSequence ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2DataSequence ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[2] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2870 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1DataSequence ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0DataSequence ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~172 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[2] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2872 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2871 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2873 ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector5~145 ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~688 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~689 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690_I .lut_mask = "EEE2";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691_I (
+	.dataa(address[7]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~684 ),
+	.datac(address[5]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~690 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datac(address[6]),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692_I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[1]~32 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[2] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[2] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a2 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[2] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[2] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~681 ),
+	.datab(address[7]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~691 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~693 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~878 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~879 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|PIDByte~467 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~881 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~882 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1]~207 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|always0~41 ),
+	.datab(writedata[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Decoder0~203 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq~I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID~402 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]~399 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~199 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3] ),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~201 ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202_I .lut_mask = "88F0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB ),
+	.datac(address[1]),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~202 ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~203 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205_I (
+	.dataa(address[1]),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~200 ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~204 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~205 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~751 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[3] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(writedata[3]),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00110 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Equal6~29 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed~I .lut_mask = "8ACE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|SOFRxed ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrSOFReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInSTB ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[3] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~884 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~885 ),
+	.datac(address[2]),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB~72 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~886 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888_I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXTimeOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3SendStall ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2SendStall ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[3] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2874 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876_I (
+	.dataa(address[2]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[3] ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0SendStall ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~173 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1SendStall ),
+	.datab(address[2]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2876 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[3] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2875 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2877 ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|Selector4~206 ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~888 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~889 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890_I .lut_mask = "EEE2";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891_I (
+	.dataa(address[7]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~883 ),
+	.datac(address[5]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~890 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[3] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[2]~33 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[3] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[3] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a3 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[3] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[3] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~880 ),
+	.datab(address[7]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~891 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~892 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4] ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4] ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2878 ),
+	.datab(address[2]),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2879 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880_I .lut_mask = "8380";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881_I (
+	.dataa(address[1]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~224 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2880 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~752 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[4] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|RxfifoBI:u_RxfifoBI|Decoder0~27 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|always0~49 ),
+	.datad(writedata[4]),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|__ALT_INV__rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq~I .lut_mask = "8000";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrNAKReq ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInSTB ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0] ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt~I .lut_mask = "FF22";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[4] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2882 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2883 ),
+	.datac(address[2]),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg~252 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2]~275 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~48 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2884 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~887 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885_I .lut_mask = "A888";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg~174 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886_I (
+	.dataa(address[0]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3IsoEn ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2IsoEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174_I .lut_mask = "ACCC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg~174 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[4] ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2886 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174_I .lut_mask = "AAAC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~174 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888_I (
+	.dataa(address[2]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[4] ),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0IsoEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|NAKSent ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174_I .lut_mask = "AACA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg~174 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|endPMuxErrorsWEn ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1IsoEn ),
+	.datab(address[2]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2888 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2887 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2889 ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2881 ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2885 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2890 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891_I .lut_mask = "EEE2";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~39 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|RxfifoBI:u_RxfifoBI|Selector3~40 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~858 ),
+	.datac(address[5]),
+	.datad(address[6]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859_I .lut_mask = "0ACA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[4] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~643 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[4] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a4 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[4] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[3]~34 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .lut_mask = "964D";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[4] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~39 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~859 ),
+	.datab(address[5]),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|Selector3~40 ),
+	.datad(address[7]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860_I .lut_mask = "AAC0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~856 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~860 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861_I .lut_mask = "EAEA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~857 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2891 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~861 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862_I .lut_mask = "88F8";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~644 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1071 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1072 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1074 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1075 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077_I (
+	.dataa(address[6]),
+	.datab(address[1]),
+	.datac(address[0]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077_I .lut_mask = "4140";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[13] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5] ),
+	.datac(address[3]),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078_I .lut_mask = "53F0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079_I (
+	.dataa(address[2]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1077 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1078 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079_I .lut_mask = "0808";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080_I (
+	.dataa(address[6]),
+	.datab(address[0]),
+	.datac(address[1]),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~85 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|CurrState_slvCntrl.00000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector29~244 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86_I .lut_mask = "0AEE";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|Selector0~86 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|stallSent ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[5] ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~175 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[5] ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1081 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1082 ),
+	.datad(address[2]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084_I (
+	.dataa(address[1]),
+	.datab(address[3]),
+	.datac(address[6]),
+	.datad(address[2]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~753 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[5] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1085 ),
+	.datab(address[2]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCControlReg[5] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086_I .lut_mask = "88B8";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~748 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1084 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1086 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1079 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1083 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1087 ),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088_I .lut_mask = "EEFE";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089_I (
+	.dataa(address[5]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1076 ),
+	.datac(address[7]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1088 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[4]~35 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.cout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .operation_mode = "arithmetic";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .lut_mask = "692B";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[5] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[5] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a5 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[5] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[5] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1073 ),
+	.datab(address[5]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1089 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1090 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .lut_mask = "9696";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .lut_mask = "9696";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~906 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~907 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .lut_mask = "9696";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~645 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909_I (
+	.dataa(address[6]),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ),
+	.datac(address[1]),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .lut_mask = "9696";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.datab(address[6]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~909 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~739 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~910 ),
+	.datad(address[4]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum~754 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SCAddrReg[6] ),
+	.datac(address[1]),
+	.datad(address[6]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912_I .lut_mask = "ACF0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6] ),
+	.datab(address[4]),
+	.datac(address[6]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~912 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913_I .lut_mask = "C00A";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914_I (
+	.dataa(address[2]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~913 ),
+	.datac(address[0]),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914_I .lut_mask = "0008";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|next_ACKRxed~10 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed~I .lut_mask = "A0E4";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|ACKRxed ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915_I (
+	.dataa(address[2]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[6] ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~176 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[6] ),
+	.datac(address[3]),
+	.datad(address[2]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~914 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1080 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~915 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~916 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917_I .lut_mask = "EEEA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892_I (
+	.dataa(address[2]),
+	.datab(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892_I .lut_mask = "8888";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[5] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|next_ACKRxed~22 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed~I .lut_mask = "A0E4";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6] ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~918 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~917 ),
+	.datab(address[1]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~919 ),
+	.datad(address[6]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920_I .lut_mask = "AAEA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921_I (
+	.dataa(address[7]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~911 ),
+	.datac(address[5]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~920 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferOutIndex[6] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6] ),
+	.aclr(gnd),
+	.cin(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[5]~36 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .sum_lutc_input = "cin";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .lut_mask = "9696";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[6] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[6] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a6 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[6] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~692 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|numElementsInFifo[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[6] ),
+	.datad(address[1]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~908 ),
+	.datab(address[7]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~921 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~922 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421_I (
+	.dataa(address[1]),
+	.datab(address[4]),
+	.datac(address[2]),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421_I .lut_mask = "0001";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[1]~573 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[0]~697 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOld[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~642 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByteOldest[0]~641 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP0WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_1|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|addrEndPTemp~646 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]~180 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]~664 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]~635 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]~I .lut_mask = "CCAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~505 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP0RxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.datad(address[6]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP3WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_4|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP1WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_2|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP3RxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|RxFifo:EP1RxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.datad(address[6]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423_I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|USBEndP~114 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[1]~746 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slavecontroller:u_slavecontroller|frameNum[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424_I (
+	.dataa(address[2]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|frameNumSTB[7] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|clrResInReq~49 ),
+	.datad(address[0]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424_I .lut_mask = "0080";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXByte[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|CurrState_slvGetPkt.01101 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence~I .lut_mask = "8D88";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|dataSequence ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[1]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP2StatusReg[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[5]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP1StatusReg[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0TransTypeReg[0]~638 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43_I (
+	.dataa(address[3]),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP1StatusRegSTB[7] ),
+	.datac(address[2]),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP0StatusRegSTB[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP0StatusReg~177 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[2]~173 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|endpMux:u_endpMux|endP3StatusReg[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP2StatusRegSTB[7] ),
+	.datab(address[3]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~43 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|EP3StatusRegSTB[7] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~424 ),
+	.datab(address[0]),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~223 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Selector0~44 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425_I .lut_mask = "EAAA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101 ),
+	.aclr(gnd),
+	.sclr(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence~I .synch_mode = "on";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence~I .lut_mask = "88D8";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7] ),
+	.datad(address[3]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426_I .lut_mask = "AACC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2892 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|Decoder0~225 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~426 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427_I .lut_mask = "EAC0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~425 ),
+	.datab(address[1]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~427 ),
+	.datad(address[6]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428_I .lut_mask = "AAC0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429_I (
+	.dataa(address[5]),
+	.datab(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~423 ),
+	.datac(address[7]),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~428 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429_I .output_mode = "comb_only";
+
+cyclone_ram_block \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 (
+	.portawe(vcc),
+	.portbrewe(vcc),
+	.clk0(usbClk),
+	.clk1(clk),
+	.ena0(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|fifoMux:u_fifoMux|RxFifoEP2WEn~13 ),
+	.portadatain({\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|slaveGetPacket:u_slaveGetPacket|RXFifoData[7] }),
+	.portaaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[5] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[4] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[3] ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[2] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[1] ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|bufferInIndex[0] }),
+	.portbaddr({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~224 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~221 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~218 ,
+\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~215 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~212 ,\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|Add2~209 }),
+	.portbdataout({\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[7] }));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .ram_block_type = "auto";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .logical_ram_name = "usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ALTSYNCRAM";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_width = 6;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_depth = 64;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_in_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clock = "clock1";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_read_enable_write_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_byte_enable_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clock = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_last_address = 63;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|ram_block1a7 .port_b_data_width = 1;
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_3|altsyncram_7ie1:auto_generated|q_b[7] ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7]~I (
+	.clk(clk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7] ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[0]~15 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7] ));
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~421 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|RxFifo:EP2RxFifo|fifoRTL:u_fifo|dataOut[7] ),
+	.datad(address[6]),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430_I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~422 ),
+	.datab(address[5]),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~429 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~430 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed~I (
+	.clk(clk),
+	.dataa(\strobe_i~19 ),
+	.aclr(gnd),
+	.regout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156_I (
+	.dataa(address[7]),
+	.datab(address[5]),
+	.datac(address[6]),
+	.datad(write),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156_I .lut_mask = "006E";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_delayed ),
+	.datab(\strobe_i~19 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~155 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|always3~156 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258 ));
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258_I .lut_mask = "ACCC";
+defparam \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258_I .output_mode = "comb_only";
+
+cyclone_lcell \irq~54_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[2] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[1] ),
+	.combout(\irq~54 ));
+defparam \irq~54_I .operation_mode = "normal";
+defparam \irq~54_I .synch_mode = "off";
+defparam \irq~54_I .register_cascade_mode = "off";
+defparam \irq~54_I .sum_lutc_input = "datac";
+defparam \irq~54_I .lut_mask = "EAC0";
+defparam \irq~54_I .output_mode = "comb_only";
+
+cyclone_lcell \irq~55_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resumeInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[1] ),
+	.combout(\irq~55 ));
+defparam \irq~55_I .operation_mode = "normal";
+defparam \irq~55_I .synch_mode = "off";
+defparam \irq~55_I .register_cascade_mode = "off";
+defparam \irq~55_I .sum_lutc_input = "datac";
+defparam \irq~55_I .lut_mask = "EAC0";
+defparam \irq~55_I .output_mode = "comb_only";
+
+cyclone_lcell \irq~56_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|NAKSentInt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[4] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|interruptMaskReg[0] ),
+	.combout(\irq~56 ));
+defparam \irq~56_I .operation_mode = "normal";
+defparam \irq~56_I .synch_mode = "off";
+defparam \irq~56_I .register_cascade_mode = "off";
+defparam \irq~56_I .sum_lutc_input = "datac";
+defparam \irq~56_I .lut_mask = "EAC0";
+defparam \irq~56_I .output_mode = "comb_only";
+
+cyclone_lcell \irq~57_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|resetEventInt ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|SOFRxedInt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[3] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[2] ),
+	.combout(\irq~57 ));
+defparam \irq~57_I .operation_mode = "normal";
+defparam \irq~57_I .synch_mode = "off";
+defparam \irq~57_I .register_cascade_mode = "off";
+defparam \irq~57_I .sum_lutc_input = "datac";
+defparam \irq~57_I .lut_mask = "EAC0";
+defparam \irq~57_I .output_mode = "comb_only";
+
+cyclone_lcell \irq~58_I (
+	.dataa(\irq~54 ),
+	.datab(\irq~55 ),
+	.datac(\irq~56 ),
+	.datad(\irq~57 ),
+	.combout(\irq~58 ));
+defparam \irq~58_I .operation_mode = "normal";
+defparam \irq~58_I .synch_mode = "off";
+defparam \irq~58_I .register_cascade_mode = "off";
+defparam \irq~58_I .sum_lutc_input = "datac";
+defparam \irq~58_I .lut_mask = "FFFE";
+defparam \irq~58_I .output_mode = "comb_only";
+
+cyclone_lcell \irq~7_I (
+	.dataa(\irq~58 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|transDoneInt ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSlaveControl:u_usbSlaveControl|USBSlaveControlBI:u_USBSlaveControlBI|interruptMaskReg[0] ),
+	.combout(\irq~7 ));
+defparam \irq~7_I .operation_mode = "normal";
+defparam \irq~7_I .synch_mode = "off";
+defparam \irq~7_I .register_cascade_mode = "off";
+defparam \irq~7_I .sum_lutc_input = "datac";
+defparam \irq~7_I .lut_mask = "EAEA";
+defparam \irq~7_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~55 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~I .lut_mask = "1111";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375_I .lut_mask = "0BF8";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377_I .lut_mask = "0007";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1376 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1379 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380_I .lut_mask = "00BF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|USBWireRdy ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1380 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387_I .lut_mask = "FF32";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1387 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010010 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|WideOr23~16 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384_I .lut_mask = "FF15";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1375 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00101 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938_I .lut_mask = "1FF1";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByte[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~941 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942_I .lut_mask = "FF70";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~I .lut_mask = "5300";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState~937 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~938 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0]~942 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1]~I .lut_mask = "88A0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1383 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384_I .lut_mask = "8080";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11010 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00000 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385_I .lut_mask = "FEFF";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388_I .lut_mask = "00AA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1387 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1388 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|WideOr0~16 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389_I .lut_mask = "FF10";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~665 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~198 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~199 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011 ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385_I .lut_mask = "AAC5";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData~1385 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1377 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~1384 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~I .lut_mask = "000A";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXLineState[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1384 ),
+	.datac(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedPolarityToSIE~11 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1385 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[1]~1389 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0]~I .lut_mask = "002E";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireData[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireData[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|muxSIENotPTXB ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667_I .lut_mask = "00AC";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[2]~540 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[0]~540 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[0]~666 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202_I .lut_mask = "E5E0";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer0~667 ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~539 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~I .lut_mask = "AAAA";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203_I (
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer1[1] ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ),
+	.datac(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~202 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[1] ),
+	.combout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203 ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203_I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203_I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203_I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203_I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203_I .lut_mask = "F838";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203_I .output_mode = "comb_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|Equal4~73 ),
+	.datab(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut~203 ),
+	.datad(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~I .lut_mask = "0088";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~I .output_mode = "reg_only";
+
+cyclone_lcell \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick~I (
+	.clk(usbClk),
+	.dataa(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick ),
+	.datab(\usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut ),
+	.aclr(gnd),
+	.ena(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]~201 ),
+	.regout(\usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick ));
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick~I .operation_mode = "normal";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick~I .synch_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick~I .register_cascade_mode = "off";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick~I .sum_lutc_input = "datac";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick~I .lut_mask = "1111";
+defparam \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick~I .output_mode = "reg_only";
+
+assign readdata[0] = \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector7~754 ;
+
+assign readdata[1] = \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector6~2869 ;
+
+assign readdata[2] = \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector5~694 ;
+
+assign readdata[3] = \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector4~893 ;
+
+assign readdata[4] = \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector3~862 ;
+
+assign readdata[5] = \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector2~1091 ;
+
+assign readdata[6] = \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector1~923 ;
+
+assign readdata[7] = \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|Selector0~431 ;
+
+assign waitrequest = ~ \usbHostSlave:usbHostSlaveInst|wishBoneBI:u_wishBoneBI|ack_o~258 ;
+
+assign irq = \irq~7 ;
+
+assign USBWireDataInTick = \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxDataInTick ;
+
+assign USBWireVPO = \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1] ;
+
+assign USBWireVMO = \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0] ;
+
+assign USBWireDataOutTick = \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxDataOutTick ;
+
+assign USBWireOutEn_n = ~ \usbHostSlave:usbHostSlaveInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxCtrlOut ;
+
+assign USBFullSpeed = \usbHostSlave:usbHostSlaveInst|hostSlaveMux:u_hostSlaveMux|fullSpeedBitRateToSIE~11 ;
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/Aldec/design0/fsm.set
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/Aldec/design0/fsm.set	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/Aldec/design0/fsm.set	(revision 264)
@@ -0,0 +1,5 @@
+FSMSET_CUTHEADER=1
+FSMSET_GENCOMMENTS=1
+FSMSET_USEDEFINE=1
+FSMSET_OMITGENNULL=0
+FSMSET_ENABLEPARSING=1
Index: common/components/usbhostslave/trunk/usbDevice/RTL/EP0.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/EP0.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/EP0.v	(revision 264)
@@ -0,0 +1,869 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// EP0.v                                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Implements EP0 control endpoint
+//// Responds to 8-byte SETUP packets
+//// of type GET_STATUS, GET_DESCRIPTOR and
+//// SET_ADDRESS
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostSlaveReg_define.v"
+`include "usbDevice_define.v"
+
+
+module EP0 (clk, initComplete, memAddr, memData, memRdEn, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
+input   clk;
+input   [7:0]memData;
+input   rst;
+input   wb_ack;
+input   [7:0]wb_data_i;
+input   wbBusGnt;
+output  initComplete;
+output  [7:0]memAddr;
+output  memRdEn;
+output  [7:0]wb_addr;
+output  [7:0]wb_data_o;
+output  wb_stb;
+output  wb_we;
+output  wbBusReq;
+
+wire    clk;
+reg     initComplete, next_initComplete;
+reg     [7:0]memAddr, next_memAddr;
+wire    [7:0]memData;
+reg     memRdEn, next_memRdEn;
+wire    rst;
+wire    wb_ack;
+reg     [7:0]wb_addr, next_wb_addr;
+wire    [7:0]wb_data_i;
+reg     [7:0]wb_data_o, next_wb_data_o;
+reg     wb_stb, next_wb_stb;
+reg     wb_we, next_wb_we;
+wire    wbBusGnt;
+reg     wbBusReq, next_wbBusReq;
+
+// diagram signals declarations
+reg bm_req_dir, next_bm_req_dir;
+reg  [4:0]bm_req_recp, next_bm_req_recp;
+reg  [1:0]bm_req_type, next_bm_req_type;
+reg  [7:0]bRequest, next_bRequest;
+reg  [7:0]cnt, next_cnt;
+reg dataSeq, next_dataSeq;
+reg  [7:0]epStatus, next_epStatus;
+reg  [7:0]epTransType, next_epTransType;
+reg localRst, next_localRst;
+reg  [15:0]rxDataSize, next_rxDataSize;
+reg transDone, next_transDone;
+reg  [7:0]txDataIndex, next_txDataIndex;
+reg  [7:0]txDataSize, next_txDataSize;
+reg  [7:0]txPacketRemSize, next_txPacketRemSize;
+reg updateUSBAddress, next_updateUSBAddress;
+reg  [7:0]USBAddress, next_USBAddress;
+reg  [15:0]wIndex, next_wIndex;
+reg  [15:0]wLength, next_wLength;
+reg  [15:0]wValue, next_wValue;
+
+// BINARY ENCODED state machine: EP0St
+// State codes definitions:
+`define INIT_RST 6'b000000
+`define INIT_WT_GNT 6'b000001
+`define INIT_WT_RST 6'b000010
+`define INIT_WT_VBUS 6'b000011
+`define INIT_FIN 6'b000100
+`define DO_TRANS_WT_GNT 6'b000101
+`define DO_TRANS_TX_EMPTY 6'b000110
+`define DO_TRANS_WR_TX_FIFO 6'b000111
+`define DO_TRANS_RD_MEM 6'b001000
+`define DO_TRANS_CHK_TX_DONE 6'b001001
+`define DO_TRANS_TRANS_GO 6'b001010
+`define DO_TRANS_WT_TRANS_DONE_WT_GNT 6'b001011
+`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 6'b001100
+`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 6'b001101
+`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 6'b001110
+`define CHK_TRANS_RD_STAT 6'b001111
+`define CHK_TRANS_WT_GNT 6'b010000
+`define CHK_TRANS_RD_RX_SIZE1 6'b010001
+`define CHK_TRANS_RD_RX_SIZE2 6'b010010
+`define CHK_TRANS_RD_TRANS_TYPE 6'b010011
+`define CHK_TRANS_WT_UNGNT 6'b010100
+`define SETUP_CHK_ERR 6'b010101
+`define SETUP_GET_DATA_DAT1 6'b010110
+`define SETUP_GET_DATA_WT_GNT 6'b010111
+`define SETUP_GET_DATA_DAT2 6'b011000
+`define SETUP_GET_DATA_DAT3 6'b011001
+`define SETUP_GET_DATA_DAT4 6'b011010
+`define SETUP_GET_DATA_DAT6 6'b011011
+`define SETUP_GET_DATA_DAT5 6'b011100
+`define SETUP_GET_DATA_DAT8 6'b011101
+`define SETUP_GET_DATA_DAT7 6'b011110
+`define SETUP_GET_DATA_WT_UNGNT 6'b011111
+`define SETUP_GET_STAT 6'b100000
+`define SETUP_SET_ADDR 6'b100001
+`define SETUP_GET_DESC_S1 6'b100010
+`define SETUP_CHK_MAX_LEN 6'b100011
+`define OUT_CHK_SEQ 6'b100100
+`define IN_CHK_ACK 6'b100101
+`define IN_SET_PTR 6'b100110
+`define IN_SET_ADDR 6'b100111
+`define IN_WT_GNT 6'b101000
+`define IN_WT_UNGNT 6'b101001
+`define DO_TRANS_RX_EMPTY 6'b101010
+`define DO_TRANS_WT_TRANS_DONE_DEL 6'b101011
+`define START 6'b101100
+`define INIT_CONN 6'b101101
+`define INIT_WT_CONN 6'b101110
+`define DO_TRANS_DEL 6'b101111
+`define SETUP_PTR_SET 6'b110000
+
+reg [5:0]CurrState_EP0St, NextState_EP0St;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: EP0St
+
+// NextState logic (combinatorial)
+always @ (wb_ack or wbBusGnt or cnt or wb_data_i or memData or txDataIndex or txDataSize or transDone or epStatus or epTransType or rxDataSize or bRequest or wValue or wLength or dataSeq or updateUSBAddress or txPacketRemSize or USBAddress or wb_addr or wb_data_o or wb_stb or wb_we or wbBusReq or initComplete or memAddr or memRdEn or bm_req_dir or bm_req_type or bm_req_recp or wIndex or CurrState_EP0St)
+begin
+  NextState_EP0St <= CurrState_EP0St;
+  // Set default values for outputs and signals
+  next_wb_addr <= wb_addr;
+  next_wb_data_o <= wb_data_o;
+  next_wb_stb <= wb_stb;
+  next_wb_we <= wb_we;
+  next_cnt <= cnt;
+  next_wbBusReq <= wbBusReq;
+  next_initComplete <= initComplete;
+  next_memAddr <= memAddr;
+  next_memRdEn <= memRdEn;
+  next_txDataSize <= txDataSize;
+  next_txDataIndex <= txDataIndex;
+  next_transDone <= transDone;
+  next_epStatus <= epStatus;
+  next_rxDataSize <= rxDataSize;
+  next_epTransType <= epTransType;
+  next_bm_req_dir <= bm_req_dir;
+  next_bm_req_type <= bm_req_type;
+  next_bm_req_recp <= bm_req_recp;
+  next_bRequest <= bRequest;
+  next_wValue <= wValue;
+  next_wIndex <= wIndex;
+  next_wLength <= wLength;
+  next_txPacketRemSize <= txPacketRemSize;
+  next_USBAddress <= USBAddress;
+  next_updateUSBAddress <= updateUSBAddress;
+  next_dataSeq <= dataSeq;
+  case (CurrState_EP0St)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_initComplete <= 1'b0;
+      next_wbBusReq <= 1'b0;
+      next_wb_addr <= 8'h00;
+      next_wb_data_o <= 8'h00;
+      next_wb_stb <= 1'b0;
+      next_wb_we <= 1'b0;
+      next_txPacketRemSize <= 8'h00;
+      next_txDataSize <= 8'h00;
+      next_txDataIndex <= 8'h00;
+      next_epTransType <= 8'h00;
+      next_epStatus <= 8'h00;
+      next_rxDataSize <= 16'h0000;
+      next_cnt <= 8'h00;
+      next_memRdEn <= 1'b0;
+      next_memAddr <= 8'h00;
+      next_updateUSBAddress <= 1'b0;
+      next_transDone <= 1'b0;
+      next_bm_req_type <= 2'b00;
+      next_bm_req_dir <= 1'b0;
+      next_bm_req_recp <= 5'b00000;
+      next_bRequest <= 8'h00;
+      next_wLength <= 16'h0000;
+      next_wIndex <= 16'h0000;
+      next_wValue <= 16'h0000;
+      next_dataSeq <= 1'b0;
+      next_USBAddress <= 8'h00;
+      NextState_EP0St <= `INIT_WT_GNT;
+    end
+    `CHK_TRANS_RD_STAT:
+    begin
+      next_wb_addr <= `RA_EP0_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE1;
+        next_wb_stb <= 1'b0;
+        next_epStatus <= wb_data_i;
+      end
+    end
+    `CHK_TRANS_WT_GNT:
+    begin
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_RD_STAT;
+      end
+    end
+    `CHK_TRANS_RD_RX_SIZE1:
+    begin
+      next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_MSB;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE2;
+        next_wb_stb <= 1'b0;
+        next_rxDataSize[15:8] <= wb_data_i;
+      end
+    end
+    `CHK_TRANS_RD_RX_SIZE2:
+    begin
+      next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_LSB;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_RD_TRANS_TYPE;
+        next_wb_stb <= 1'b0;
+        next_rxDataSize[7:0] <= wb_data_i;
+      end
+    end
+    `CHK_TRANS_RD_TRANS_TYPE:
+    begin
+      next_wb_addr <= `RA_EP0_TRANSTYPE_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_epTransType <= wb_data_i;
+      end
+    end
+    `CHK_TRANS_WT_UNGNT:
+    begin
+      next_wbBusReq <= 1'b0;
+      if ((wbBusGnt == 1'b0) && ((epStatus & 8'h0f) != 8'h00))
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+      else if ((wbBusGnt == 1'b0) && (epTransType == `SC_SETUP_TRANS))
+      begin
+        NextState_EP0St <= `SETUP_CHK_ERR;
+      end
+      else if ((wbBusGnt == 1'b0) && (epTransType == `SC_IN_TRANS))
+      begin
+        NextState_EP0St <= `IN_CHK_ACK;
+      end
+      else if ((wbBusGnt == 1'b0) && (epTransType == `SC_OUTDATA_TRANS))
+      begin
+        NextState_EP0St <= `OUT_CHK_SEQ;
+      end
+      else if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+    end
+    `DO_TRANS_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_TX_EMPTY;
+      end
+    end
+    `DO_TRANS_TX_EMPTY:
+    begin
+      next_wb_addr <= `RA_EP0_TX_FIFO_CONTROL_REG;
+      next_wb_data_o <= 8'h01;
+      //force tx fifo empty
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_RX_EMPTY;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO:
+    begin
+      next_wb_data_o <= memData;
+      next_wb_addr <= `RA_EP0_TX_FIFO_DATA_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_CHK_TX_DONE;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_RD_MEM:
+    begin
+      next_memAddr <= txDataIndex;
+      next_memRdEn <= 1'b1;
+      next_txDataSize <= txDataSize - 1'b1;
+      next_txDataIndex <= txDataIndex + 1'b1;
+      NextState_EP0St <= `DO_TRANS_DEL;
+    end
+    `DO_TRANS_CHK_TX_DONE:
+    begin
+      if (txDataSize == 8'h00)
+      begin
+        NextState_EP0St <= `DO_TRANS_TRANS_GO;
+      end
+      else
+      begin
+        NextState_EP0St <= `DO_TRANS_RD_MEM;
+      end
+    end
+    `DO_TRANS_TRANS_GO:
+    begin
+      next_wb_addr <= `RA_EP0_CONTROL_REG;
+      if (dataSeq == 1'b1)
+      next_wb_data_o <= 8'h07;
+      else
+      next_wb_data_o <= 8'h03;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+        next_wb_stb <= 1'b0;
+        next_transDone <= 1'b0;
+      end
+    end
+    `DO_TRANS_RX_EMPTY:
+    begin
+      next_wb_addr <= `RA_EP0_RX_FIFO_CONTROL_REG;
+      next_wb_data_o <= 8'h01;
+      //force rx fifo empty
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if ((wb_ack == 1'b1) && (txDataSize != 8'h00))
+      begin
+        NextState_EP0St <= `DO_TRANS_RD_MEM;
+        next_wb_stb <= 1'b0;
+      end
+      else if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_TRANS_GO;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_DEL:
+    begin
+      next_memRdEn <= 1'b0;
+      NextState_EP0St <= `DO_TRANS_WR_TX_FIFO;
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
+    begin
+      next_wb_addr <= `RA_EP0_CONTROL_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
+    begin
+      next_wbBusReq <= 1'b0;
+      if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_CHK_DONE:
+    begin
+      if (transDone == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_WT_GNT;
+        next_wbBusReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_DEL;
+        next_cnt <= 8'h00;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_DEL:
+    begin
+      next_cnt <= cnt + 1'b1;
+      if (cnt == `ONE_USEC_DEL)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+      end
+    end
+    `SETUP_CHK_ERR:
+    begin
+      if (rxDataSize != 16'h0008)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+      else
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_WT_GNT;
+        next_wbBusReq <= 1'b1;
+        next_txDataSize <= 8'h00;
+        next_txPacketRemSize <= 8'h00;
+        //default tx packet size
+        next_dataSeq <= 1'b1;
+        next_wb_addr <= `RA_EP0_RX_FIFO_DATA_REG;
+        next_wb_we <= 1'b0;
+      end
+    end
+    `SETUP_GET_STAT:
+    begin
+      if (bm_req_type == 2'b00)  begin
+      next_txPacketRemSize <= 8'h02;
+      if (bm_req_recp == 5'b00000)
+      next_txDataIndex <= `ONE_ZERO_STAT_INDEX;
+      else
+      next_txDataIndex <= `ZERO_ZERO_STAT_INDEX;
+      end
+      else if (bm_req_type == 2'b10) begin
+      next_txDataIndex <= `VENDOR_DATA_STAT_INDEX;
+      next_txPacketRemSize <= 8'h02;
+      end
+      NextState_EP0St <= `SETUP_CHK_MAX_LEN;
+    end
+    `SETUP_SET_ADDR:
+    begin
+      if ( (wValue[15:7] == {9{1'b0}}) && (wIndex == 16'h0000) && (wLength == 16'h0000) ) begin
+      next_USBAddress <= wValue[7:0];
+      next_updateUSBAddress <= 1'b1;
+      end
+      NextState_EP0St <= `SETUP_CHK_MAX_LEN;
+    end
+    `SETUP_CHK_MAX_LEN:
+    begin
+      if (txPacketRemSize > wLength)
+      next_txPacketRemSize <= wLength;
+      NextState_EP0St <= `SETUP_PTR_SET;
+    end
+    `SETUP_PTR_SET:
+    begin
+      if (txPacketRemSize > `MAX_RESP_SIZE) begin
+      next_txDataSize <= `MAX_RESP_SIZE;
+      next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
+      end
+      else begin
+      next_txDataSize <= txPacketRemSize;
+      next_txPacketRemSize <= 8'h00;
+      end
+      NextState_EP0St <= `DO_TRANS_WT_GNT;
+    end
+    `SETUP_GET_DATA_DAT1:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT2;
+        next_wb_stb <= 1'b0;
+        next_bm_req_dir <= wb_data_i[7];
+        next_bm_req_type <= wb_data_i[6:5];
+        next_bm_req_recp <= wb_data_i[4:0];
+      end
+    end
+    `SETUP_GET_DATA_WT_GNT:
+    begin
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT1;
+      end
+    end
+    `SETUP_GET_DATA_DAT2:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT3;
+        next_wb_stb <= 1'b0;
+        next_bRequest <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT3:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT4;
+        next_wb_stb <= 1'b0;
+        next_wValue[7:0] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT4:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT5;
+        next_wb_stb <= 1'b0;
+        next_wValue[15:8] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT6:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT7;
+        next_wb_stb <= 1'b0;
+        next_wIndex[15:8] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT5:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT6;
+        next_wb_stb <= 1'b0;
+        next_wIndex[7:0] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT8:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_wLength[15:8] <= wb_data_i;
+        next_wbBusReq <= 1'b0;
+      end
+    end
+    `SETUP_GET_DATA_DAT7:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT8;
+        next_wb_stb <= 1'b0;
+        next_wLength[7:0] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_WT_UNGNT:
+    begin
+      if ((wbBusGnt == 1'b0) && (bRequest == `GET_STATUS))
+      begin
+        NextState_EP0St <= `SETUP_GET_STAT;
+      end
+      else if ((wbBusGnt == 1'b0) && (bRequest == `GET_DESCRIPTOR))
+      begin
+        NextState_EP0St <= `SETUP_GET_DESC_S1;
+      end
+      else if ((wbBusGnt == 1'b0) && (bRequest == `SET_ADDRESS))
+      begin
+        NextState_EP0St <= `SETUP_SET_ADDR;
+      end
+      else if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+    end
+    `SETUP_GET_DESC_S1:
+    begin
+      case (wValue[15:8])
+      `DEV_DESC: begin
+      next_txPacketRemSize <= `DEV_DESC_SIZE;
+      next_txDataIndex <= `DEV_DESC_INDEX;
+      end
+      `CFG_DESC: begin
+      next_txPacketRemSize <= `CFG_DESC_SIZE;
+      next_txDataIndex <= `CFG_DESC_INDEX;
+      end
+      `REP_DESC: begin
+      next_txPacketRemSize <= `REP_DESC_SIZE;
+      next_txDataIndex <= `REP_DESC_INDEX;
+      end
+      `STRING_DESC: begin
+      case (wValue[3:0])
+      4'h0: begin
+      next_txPacketRemSize <= `LANGID_DESC_SIZE;
+      next_txDataIndex <= `LANGID_DESC_INDEX;
+      end
+      4'h1: begin
+      next_txPacketRemSize <= `STRING1_DESC_SIZE;
+      next_txDataIndex <= `STRING1_DESC_INDEX;
+      end
+      4'h2: begin
+      next_txPacketRemSize <= `STRING2_DESC_SIZE;
+      next_txDataIndex <= `STRING2_DESC_INDEX;
+      end
+      4'h3: begin
+      next_txPacketRemSize <= `STRING3_DESC_SIZE;
+      next_txDataIndex <= `STRING3_DESC_INDEX;
+      end
+      endcase
+      end
+      endcase
+      NextState_EP0St <= `SETUP_CHK_MAX_LEN;
+    end
+    `IN_CHK_ACK:
+    begin
+      if (epStatus[`SC_ACK_RXED_BIT] != 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+      else if (updateUSBAddress == 1'b1)
+      begin
+        NextState_EP0St <= `IN_WT_GNT;
+      end
+      else
+      begin
+        NextState_EP0St <= `IN_SET_PTR;
+      end
+    end
+    `IN_SET_PTR:
+    begin
+      if (txPacketRemSize > `MAX_RESP_SIZE) begin
+      next_txDataSize <= `MAX_RESP_SIZE;
+      next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
+      end
+      else begin
+      next_txDataSize <= txPacketRemSize;
+      next_txPacketRemSize <= 8'h00;
+      end
+      NextState_EP0St <= `DO_TRANS_WT_GNT;
+    end
+    `IN_SET_ADDR:
+    begin
+      next_wb_addr <= `RA_SC_ADDRESS;
+      next_wb_data_o <= USBAddress;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `IN_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_wbBusReq <= 1'b0;
+      end
+    end
+    `IN_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      next_updateUSBAddress <= 1'b0;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `IN_SET_ADDR;
+      end
+    end
+    `IN_WT_UNGNT:
+    begin
+      if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `IN_SET_PTR;
+      end
+    end
+    `OUT_CHK_SEQ:
+    begin
+      if (epStatus[`SC_DATA_SEQUENCE_BIT] != dataSeq)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+      else
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+        next_dataSeq <= ~dataSeq;
+      end
+    end
+    `INIT_RST:
+    begin
+      next_wb_addr <= `RA_HOST_SLAVE_MODE;
+      next_wb_data_o <= 8'h2;
+      //reset usbHostSlave
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `INIT_WT_RST;
+        next_wb_stb <= 1'b0;
+        next_cnt <= 8'h00;
+      end
+    end
+    `INIT_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `INIT_RST;
+      end
+    end
+    `INIT_WT_RST:
+    begin
+      next_cnt <= cnt + 1'b1;
+      if (cnt == 8'hff)
+      begin
+        NextState_EP0St <= `INIT_WT_VBUS;
+      end
+    end
+    `INIT_WT_VBUS:
+    begin
+      next_wb_addr <= `RA_SC_LINE_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if ((wb_ack == 1'b1)  && (wb_data_i[`VBUS_PRES_BIT] == 1'b1))
+      begin
+        NextState_EP0St <= `INIT_CONN;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `INIT_FIN:
+    begin
+      next_wbBusReq <= 1'b0;
+      next_initComplete <= 1'b1;
+      if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+    end
+    `INIT_CONN:
+    begin
+      next_wb_addr <= `RA_SC_CONTROL_REG;
+      next_wb_data_o <= 8'h71;
+      //connect to host, full speed
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `INIT_WT_CONN;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `INIT_WT_CONN:
+    begin
+      next_wb_addr <= `RA_SC_LINE_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if ((wb_ack == 1'b1) && (wb_data_i[1:0] == `FULL_SPEED_CONNECT))
+      begin
+        NextState_EP0St <= `INIT_FIN;
+        next_wb_stb <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+    CurrState_EP0St <= `START;
+  else
+    CurrState_EP0St <= NextState_EP0St;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    wb_addr <= 8'h00;
+    wb_data_o <= 8'h00;
+    wb_stb <= 1'b0;
+    wb_we <= 1'b0;
+    wbBusReq <= 1'b0;
+    initComplete <= 1'b0;
+    memAddr <= 8'h00;
+    memRdEn <= 1'b0;
+    cnt <= 8'h00;
+    txDataSize <= 8'h00;
+    txDataIndex <= 8'h00;
+    transDone <= 1'b0;
+    epStatus <= 8'h00;
+    rxDataSize <= 16'h0000;
+    epTransType <= 8'h00;
+    bm_req_dir <= 1'b0;
+    bm_req_type <= 2'b00;
+    bm_req_recp <= 5'b00000;
+    bRequest <= 8'h00;
+    wValue <= 16'h0000;
+    wIndex <= 16'h0000;
+    wLength <= 16'h0000;
+    txPacketRemSize <= 8'h00;
+    USBAddress <= 8'h00;
+    updateUSBAddress <= 1'b0;
+    dataSeq <= 1'b0;
+  end
+  else 
+  begin
+    wb_addr <= next_wb_addr;
+    wb_data_o <= next_wb_data_o;
+    wb_stb <= next_wb_stb;
+    wb_we <= next_wb_we;
+    wbBusReq <= next_wbBusReq;
+    initComplete <= next_initComplete;
+    memAddr <= next_memAddr;
+    memRdEn <= next_memRdEn;
+    cnt <= next_cnt;
+    txDataSize <= next_txDataSize;
+    txDataIndex <= next_txDataIndex;
+    transDone <= next_transDone;
+    epStatus <= next_epStatus;
+    rxDataSize <= next_rxDataSize;
+    epTransType <= next_epTransType;
+    bm_req_dir <= next_bm_req_dir;
+    bm_req_type <= next_bm_req_type;
+    bm_req_recp <= next_bm_req_recp;
+    bRequest <= next_bRequest;
+    wValue <= next_wValue;
+    wIndex <= next_wIndex;
+    wLength <= next_wLength;
+    txPacketRemSize <= next_txPacketRemSize;
+    USBAddress <= next_USBAddress;
+    updateUSBAddress <= next_updateUSBAddress;
+    dataSeq <= next_dataSeq;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/RTL/usbDevice.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/usbDevice.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/usbDevice.v	(revision 264)
@@ -0,0 +1,235 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbDevice.v                                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Top level module for usbDevice
+//// Instantiates a usbSlave, and controllers for EP0 and EP1
+//// If you wish to implement another type of HID, then you will
+//// need to modify usbROM.v, and EP1Mouse.v
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+
+module usbDevice (
+  clk,
+  rst,
+  usbSlaveVP_in,
+  usbSlaveVM_in,
+  usbSlaveVP_out,
+  usbSlaveVM_out,
+  usbSlaveOE_n,
+  USBFullSpeed,
+  usbDPlusPullup,
+  usbDMinusPullup,
+  vBusDetect
+);
+
+input clk;
+input rst;
+input usbSlaveVP_in;
+input usbSlaveVM_in;
+output usbSlaveVP_out;
+output usbSlaveVM_out;
+output usbSlaveOE_n;
+output USBFullSpeed;
+output usbDPlusPullup;
+output usbDMinusPullup;
+input vBusDetect;
+
+//local wires and regs
+wire [7:0] wb_addr0;
+wire wb_stb0;
+wire wb_we0;
+wire wbBusReq0;
+wire wbBusGnt0;
+wire [7:0] wb_addr1;
+wire [7:0] wb_data_o1;
+wire wb_stb1;
+wire wb_we1;
+wire wbBusReq1;
+wire wbBusGnt1;
+wire [7:0] wb_addr2;
+wire [7:0] wb_data_o2;
+wire wb_stb2;
+wire wb_we2;
+wire wbBusReq2;
+wire wbBusGnt2;
+wire [7:0] wb_adr;
+wire [7:0] wb_dat_to_usb;
+wire [7:0] wb_dat_from_usb;
+wire wb_we;
+wire wb_stb;
+wire wb_ack;
+reg [1:0] resetReg;
+wire initComplete;
+wire usbRstDet;
+wire [7:0] memAddr;
+wire [7:0] memData;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+//Parameters declaration: 
+defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+usbSlave usbSlaveInst (
+  .clk_i(clk),
+  .rst_i(rst),
+  .address_i(wb_adr),
+  .data_i(wb_dat_to_usb),
+  .data_o(wb_dat_from_usb),
+  .we_i(wb_we),
+  .strobe_i(wb_stb),
+  .ack_o(wb_ack),
+  .usbClk(clk),
+  .slaveSOFRxedIntOut(),
+  .slaveResetEventIntOut(),
+  .slaveResumeIntOut(),
+  .slaveTransDoneIntOut(),
+  .slaveNAKSentIntOut(),
+  .slaveVBusDetIntOut(),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(USBFullSpeed),
+  .USBDPlusPullup(usbDPlusPullup),
+  .USBDMinusPullup(usbDMinusPullup),
+  .vBusDetect(vBusDetect)
+);
+
+assign USBWireDataIn = {usbSlaveVP_in, usbSlaveVM_in};
+assign {usbSlaveVP_out, usbSlaveVM_out} = USBWireDataOut;
+assign usbSlaveOE_n = ~USBWireCtrlOut;
+
+checkLineState u_checkLineState (
+  .clk(clk),
+  .rst(rst),
+  .initComplete(initComplete),
+  .usbRstDet(usbRstDet),
+  .wb_ack(wb_ack),
+  .wb_addr(wb_addr0),
+  .wb_data_i(wb_dat_from_usb),
+  .wb_stb(wb_stb0),
+  .wb_we(wb_we0),
+  .wbBusGnt(wbBusGnt0),
+  .wbBusReq(wbBusReq0)
+);
+
+
+EP0 u_EP0 (
+  .clk(clk), 
+  .rst(rst | usbRstDet),
+  .initComplete(initComplete),
+  .wb_ack(wb_ack),
+  .wb_addr(wb_addr1),
+  .wb_data_i(wb_dat_from_usb),
+  .wb_data_o(wb_data_o1),
+  .wb_stb(wb_stb1),
+  .wb_we(wb_we1),
+  .wbBusGnt(wbBusGnt1),
+  .wbBusReq(wbBusReq1),
+  .memAddr(memAddr),
+  .memData(memData),
+  .memRdEn()
+);
+
+usbROM u_usbROM (
+  .clk(clk),
+  .addr(memAddr),
+  .data(memData)
+);
+
+
+EP1Mouse u_EP1Mouse (
+  .clk(clk),
+  .rst(rst | usbRstDet),
+  .initComplete(initComplete),
+  .wb_ack(wb_ack),
+  .wb_addr(wb_addr2),
+  .wb_data_i(wb_dat_from_usb),
+  .wb_data_o(wb_data_o2),
+  .wb_stb(wb_stb2),
+  .wb_we(wb_we2),
+  .wbBusGnt(wbBusGnt2),
+  .wbBusReq(wbBusReq2)
+);
+
+wishboneArb u_wishboneArb (
+  .clk(clk),
+  .rst(rst),
+
+  .addr0_i(wb_addr0),
+  .data0_i(8'h00),
+  .stb0_i(wb_stb0),
+  .we0_i(wb_we0),
+  .req0(wbBusReq0),
+  .gnt0(wbBusGnt0),
+
+  .addr1_i(wb_addr1),
+  .data1_i(wb_data_o1),
+  .stb1_i(wb_stb1),
+  .we1_i(wb_we1),
+  .req1(wbBusReq1),
+  .gnt1(wbBusGnt1),
+
+  .addr2_i(wb_addr2),
+  .data2_i(wb_data_o2),
+  .stb2_i(wb_stb2),
+  .we2_i(wb_we2),
+  .req2(wbBusReq2),
+  .gnt2(wbBusGnt2),
+
+
+  .addr_o(wb_adr),
+  .data_o(wb_dat_to_usb),
+  .stb_o(wb_stb),
+  .we_o(wb_we)
+);
+
+
+endmodule
+
Index: common/components/usbhostslave/trunk/usbDevice/RTL/usbDevice_define.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/usbDevice_define.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/usbDevice_define.v	(revision 264)
@@ -0,0 +1,48 @@
+// ----------------------------- usbDevice_define ---------------------------
+
+`define ZERO_ZERO_STAT_INDEX 8'h6c
+`define ONE_ZERO_STAT_INDEX 8'h6e
+`define VENDOR_DATA_STAT_INDEX 8'h70
+`define DEV_DESC_INDEX 8'h00
+`define DEV_DESC_SIZE 8'h12
+//config descriptor is bundled with interface desc, HID desc, and EP1 desc
+`define CFG_DESC_INDEX 8'h12
+`define CFG_DESC_SIZE 8'h22
+`define REP_DESC_INDEX 8'h3a
+`define REP_DESC_SIZE 8'h32
+`define LANGID_DESC_INDEX 8'h80
+`define LANGID_DESC_SIZE 8'h04
+`define STRING1_DESC_INDEX 8'h90
+`define STRING1_DESC_SIZE 8'd26
+`define STRING2_DESC_INDEX 8'hb0
+`define STRING2_DESC_SIZE 8'd20
+`define STRING3_DESC_INDEX 8'hd0
+`define STRING3_DESC_SIZE 8'd30
+
+`define DEV_DESC 8'h01
+`define CFG_DESC 8'h02
+`define REP_DESC 8'h22
+`define STRING_DESC 8'h03
+
+//delays at 48MHz
+`ifdef SIM_COMPILE
+`define ONE_MSEC_DEL 16'h0300
+`else
+`define ONE_MSEC_DEL 16'hbb80
+`endif
+`define ONE_USEC_DEL 8'h30
+
+`define GET_STATUS 8'h00
+`define CLEAR_FEATURE 8'h01
+`define SET_FEATURE 8'h03
+`define SET_ADDRESS 8'h05
+`define GET_DESCRIPTOR 8'h06
+`define SET_DESCRIPTOR 8'h07
+`define GET_CONFIG 8'h08
+`define SET_CONFIG 8'h09
+`define GET_INTERFACE 8'h0a
+`define SET_INTERFACE 8'h0b
+`define SYNCH_FRAME 8'h0c
+
+`define MAX_RESP_SIZE 8'h40
+
Index: common/components/usbhostslave/trunk/usbDevice/RTL/wishboneArb.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/wishboneArb.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/wishboneArb.v	(revision 264)
@@ -0,0 +1,218 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishboneArb.v                                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Arbitrate between 3 wishbone bus controllers
+//// Uses Round Robin access controller
+//// 
+////
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+module wishboneArb (
+  clk,
+  rst,
+
+  addr0_i,
+  data0_i,
+  stb0_i,
+  we0_i,
+  req0,
+  gnt0,
+
+  addr1_i,
+  data1_i,
+  stb1_i,
+  we1_i,
+  req1,
+  gnt1,
+
+  addr2_i,
+  data2_i,
+  stb2_i,
+  we2_i,
+  req2,
+  gnt2,
+
+
+  addr_o,
+  data_o,
+  stb_o,
+  we_o
+);
+
+input clk;
+input rst;
+
+input [7:0] addr0_i;
+input [7:0] data0_i;
+input stb0_i;
+input we0_i;
+input req0;
+output gnt0;
+reg gnt0;
+
+input [7:0] addr1_i;
+input [7:0] data1_i;
+input stb1_i;
+input we1_i;
+input req1;
+output gnt1;
+reg gnt1;
+
+input [7:0] addr2_i;
+input [7:0] data2_i;
+input stb2_i;
+input we2_i;
+input req2;
+output gnt2;
+reg gnt2;
+
+
+output [7:0] addr_o;
+reg [7:0] addr_o;
+output [7:0] data_o;
+reg [7:0] data_o;
+output stb_o;
+reg stb_o;
+output we_o;
+reg we_o;
+
+//local wires and regs
+reg [1:0] muxSel;
+reg [2:0] arbSt;
+
+`define REQ_0 3'b000
+`define REQ_1 3'b001
+`define REQ_2 3'b010
+`define GNT_0 3'b011
+`define GNT_1 3'b100
+`define GNT_2 3'b101
+
+
+//arb
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+    gnt0 <= 1'b0;
+    gnt1 <= 1'b0;
+    gnt2 <= 1'b0;
+    muxSel <= 2'b00;
+    arbSt <= `REQ_0;
+  end
+  else begin
+    case (arbSt)
+      `REQ_0: begin
+        if (req0 == 1'b1)
+          arbSt <= `GNT_0;
+        else
+          arbSt <= `REQ_1;
+      end
+      `REQ_1: begin
+        if (req1 == 1'b1)
+          arbSt <= `GNT_1;
+        else
+          arbSt <= `REQ_2;
+      end
+      `REQ_2: begin
+        if (req2 == 1'b1)
+          arbSt <= `GNT_2;
+        else
+          arbSt <= `REQ_0;
+      end
+      `GNT_0: begin
+        gnt0 <= 1'b1;
+        muxSel <= 2'b00;
+        if (req0 == 1'b0) begin
+          arbSt <= `REQ_1;
+          gnt0 <= 1'b0;
+        end
+      end
+      `GNT_1: begin
+        gnt1 <= 1'b1;
+        muxSel <= 2'b01;
+        if (req1 == 1'b0) begin
+          arbSt <= `REQ_2;
+          gnt1 <= 1'b0;
+        end
+      end
+      `GNT_2: begin
+        gnt2 <= 1'b1;
+        muxSel <= 2'b10;
+        if (req2 == 1'b0) begin
+          arbSt <= `REQ_0;
+          gnt2 <= 1'b0;
+        end
+      end
+    endcase
+  end
+end
+
+
+//mux
+always @(*) begin
+  case (muxSel)
+    2'b00: begin
+      addr_o <= addr0_i;
+      data_o <= data0_i;
+      stb_o <= stb0_i;
+      we_o <= we0_i;
+    end
+    2'b01: begin
+      addr_o <= addr1_i;
+      data_o <= data1_i;
+      stb_o <= stb1_i;
+      we_o <= we1_i;
+    end
+    2'b10: begin
+      addr_o <= addr2_i;
+      data_o <= data2_i;
+      stb_o <= stb2_i;
+      we_o <= we2_i;
+    end
+    default: begin
+      addr_o <= addr0_i;
+      data_o <= data0_i;
+      stb_o <= stb0_i;
+      we_o <= we0_i;
+    end
+  endcase
+end
+
+
+endmodule
+
Index: common/components/usbhostslave/trunk/usbDevice/model/wb_master_model.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/model/wb_master_model.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/model/wb_master_model.v	(revision 264)
@@ -0,0 +1,178 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  wb_master_model.v                                           ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  Based on:                                                   ////
+////      - i2c/bench/verilog/wb_master_model.v                   ////
+////        Copyright (C) 2001 Richard Herveille                  ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+
+module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
+
+  parameter dwidth = 32;
+  parameter awidth = 32;
+  
+  input                  clk, rst;
+  output [awidth   -1:0] adr;
+  input  [dwidth   -1:0] din;
+  output [dwidth   -1:0] dout;
+  output                 cyc, stb;
+  output                 we;
+  output [dwidth/8 -1:0] sel;
+  input                  ack, err, rty;
+  
+  // Internal signals
+  reg    [awidth   -1:0] adr;
+  reg    [dwidth   -1:0] dout;
+  reg                    cyc, stb;
+  reg                    we;
+  reg    [dwidth/8 -1:0] sel;
+         
+  reg    [dwidth   -1:0] q;
+  
+  // Memory Logic
+  initial
+    begin
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+      #1;
+    end
+  
+  // Wishbone write cycle
+  task wb_write;
+    input   delay;
+    integer delay;
+  
+    input [awidth -1:0] a;
+    input [dwidth -1:0] d;
+  
+    begin
+  
+      // wait initial delay
+      repeat(delay) @(posedge clk);
+  
+      // assert wishbone signal
+      #1;
+      adr  = a;
+      dout = d;
+      cyc  = 1'b1;
+      stb  = 1'b1;
+      we   = 1'b1;
+      sel  = {dwidth/8{1'b1}};
+      @(posedge clk);
+  
+      // wait for acknowledge from slave
+      while(~ack) @(posedge clk);
+  
+      // negate wishbone signals
+      #1;
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+  
+    end
+  endtask
+  
+  // Wishbone read cycle
+  task wb_read;
+    input   delay;
+    integer delay;
+  
+    input  [awidth -1:0]  a;
+    output  [dwidth -1:0] d;
+  
+    begin
+  
+      // wait initial delay
+      repeat(delay) @(posedge clk);
+  
+      // assert wishbone signals
+      #1;
+      adr  = a;
+      dout = {dwidth{1'bx}};
+      cyc  = 1'b1;
+      stb  = 1'b1;
+      we   = 1'b0;
+      sel  = {dwidth/8{1'b1}};
+      @(posedge clk);
+  
+      // wait for acknowledge from slave
+      while(~ack) @(posedge clk);
+  
+      // negate wishbone signals
+      #1;
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+      d    = din;
+  
+    end
+  endtask
+  
+  // Wishbone compare cycle (read data from location and compare with expected data)
+  task wb_cmp;
+    input   delay;
+    integer delay;
+  
+    input [awidth -1:0] a;
+    input [dwidth -1:0] d_exp;
+  
+    begin
+      wb_read (delay, a, q);
+
+      if (d_exp !== q) begin
+        $display("\n--- ERROR: At address 0x%0x, got 0x%0x, expected 0x%0x at time %t", a, q, d_exp, $time);
+        $stop;
+      end
+    end
+  endtask
+  
+endmodule
+ 
Index: common/components/usbhostslave/trunk/usbDevice/sim/filelist.icarus
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/sim/filelist.icarus	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/sim/filelist.icarus	(revision 264)
@@ -0,0 +1,61 @@
+../../RTL/buffers/dpMem_dc.v
+../../RTL/buffers/fifoRTL.v
+../../RTL/buffers/RxFifoBI.v
+../../RTL/buffers/TxFifoBI.v
+../../RTL/buffers/RxFifo.v
+../../RTL/buffers/TxFifo.v
+../../RTL/busInterface/wishBoneBI.v
+../../RTL/hostController/directControl.v
+../../RTL/hostController/getPacket.v
+../../RTL/hostController/hctxportarbiter.v
+../../RTL/hostController/hostcontroller.v
+../../RTL/hostController/rxStatusMonitor.v
+../../RTL/hostController/sendPacket.v
+../../RTL/hostController/sendpacketarbiter.v
+../../RTL/hostController/sendpacketcheckpreamble.v
+../../RTL/hostController/sofcontroller.v
+../../RTL/hostController/softransmit.v
+../../RTL/hostController/speedctrlMux.v
+../../RTL/hostController/usbHostControl.v
+../../RTL/hostController/USBHostControlBI.v
+../../RTL/hostSlaveMux/hostSlaveMux.v
+../../RTL/hostSlaveMux/hostSlaveMuxBI.v
+../../RTL/serialInterfaceEngine/lineControlUpdate.v
+../../RTL/serialInterfaceEngine/processRxBit.v
+../../RTL/serialInterfaceEngine/processRxByte.v
+../../RTL/serialInterfaceEngine/processTxByte.v
+../../RTL/serialInterfaceEngine/readUSBWireData.v
+../../RTL/serialInterfaceEngine/siereceiver.v
+../../RTL/serialInterfaceEngine/SIETransmitter.v
+../../RTL/serialInterfaceEngine/updateCRC5.v
+../../RTL/serialInterfaceEngine/updateCRC16.v
+../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+../../RTL/serialInterfaceEngine/usbTxWireArbiter.v
+../../RTL/serialInterfaceEngine/writeUSBWireData.v
+../../RTL/slaveController/endpMux.v
+../../RTL/slaveController/fifoMux.v
+../../RTL/slaveController/sctxportarbiter.v
+../../RTL/slaveController/slavecontroller.v
+../../RTL/slaveController/slaveDirectcontrol.v
+../../RTL/slaveController/slaveGetpacket.v
+../../RTL/slaveController/slaveRxStatusMonitor.v
+../../RTL/slaveController/slaveSendpacket.v
+../../RTL/slaveController/usbSlaveControl.v
+../../RTL/slaveController/USBSlaveControlBI.v
+../../RTL/wrapper/usbHost.v
+../../RTL/wrapper/usbSlave.v
+../RTL/checkLineState.v
+../RTL/EP0.v
+../RTL/EP1Mouse.v
+../RTL/usbDevice.v
+../RTL/usbROM.v
+../RTL/wishboneArb.v
+../model/wb_master_model.v
+../bench/testHarness.v
+../bench/testCase0.v
+
++incdir+../RTL
++incdir+../../RTL/include
++incdir+../bench
++define+SIM_COMPILE
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.pdb
===================================================================
Cannot display: file marked as a binary type.
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Property changes on: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.pdb
___________________________________________________________________
Added: svn:mime-type
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+application/octet-stream
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Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP0.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP0.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP0.v	(revision 264)
@@ -0,0 +1,869 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// EP0.v                                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Implements EP0 control endpoint
+//// Responds to 8-byte SETUP packets
+//// of type GET_STATUS, GET_DESCRIPTOR and
+//// SET_ADDRESS
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostSlaveReg_define.v"
+`include "usbDevice_define.v"
+
+
+module EP0 (clk, initComplete, memAddr, memData, memRdEn, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
+input   clk;
+input   [7:0]memData;
+input   rst;
+input   wb_ack;
+input   [7:0]wb_data_i;
+input   wbBusGnt;
+output  initComplete;
+output  [7:0]memAddr;
+output  memRdEn;
+output  [7:0]wb_addr;
+output  [7:0]wb_data_o;
+output  wb_stb;
+output  wb_we;
+output  wbBusReq;
+
+wire    clk;
+reg     initComplete, next_initComplete;
+reg     [7:0]memAddr, next_memAddr;
+wire    [7:0]memData;
+reg     memRdEn, next_memRdEn;
+wire    rst;
+wire    wb_ack;
+reg     [7:0]wb_addr, next_wb_addr;
+wire    [7:0]wb_data_i;
+reg     [7:0]wb_data_o, next_wb_data_o;
+reg     wb_stb, next_wb_stb;
+reg     wb_we, next_wb_we;
+wire    wbBusGnt;
+reg     wbBusReq, next_wbBusReq;
+
+// diagram signals declarations
+reg bm_req_dir, next_bm_req_dir;
+reg  [4:0]bm_req_recp, next_bm_req_recp;
+reg  [1:0]bm_req_type, next_bm_req_type;
+reg  [7:0]bRequest, next_bRequest;
+reg  [7:0]cnt, next_cnt;
+reg dataSeq, next_dataSeq;
+reg  [7:0]epStatus, next_epStatus;
+reg  [7:0]epTransType, next_epTransType;
+reg localRst, next_localRst;
+reg  [15:0]rxDataSize, next_rxDataSize;
+reg transDone, next_transDone;
+reg  [7:0]txDataIndex, next_txDataIndex;
+reg  [7:0]txDataSize, next_txDataSize;
+reg  [7:0]txPacketRemSize, next_txPacketRemSize;
+reg updateUSBAddress, next_updateUSBAddress;
+reg  [7:0]USBAddress, next_USBAddress;
+reg  [15:0]wIndex, next_wIndex;
+reg  [15:0]wLength, next_wLength;
+reg  [15:0]wValue, next_wValue;
+
+// BINARY ENCODED state machine: EP0St
+// State codes definitions:
+`define INIT_RST 6'b000000
+`define INIT_WT_GNT 6'b000001
+`define INIT_WT_RST 6'b000010
+`define INIT_WT_VBUS 6'b000011
+`define INIT_FIN 6'b000100
+`define DO_TRANS_WT_GNT 6'b000101
+`define DO_TRANS_TX_EMPTY 6'b000110
+`define DO_TRANS_WR_TX_FIFO 6'b000111
+`define DO_TRANS_RD_MEM 6'b001000
+`define DO_TRANS_CHK_TX_DONE 6'b001001
+`define DO_TRANS_TRANS_GO 6'b001010
+`define DO_TRANS_WT_TRANS_DONE_WT_GNT 6'b001011
+`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 6'b001100
+`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 6'b001101
+`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 6'b001110
+`define CHK_TRANS_RD_STAT 6'b001111
+`define CHK_TRANS_WT_GNT 6'b010000
+`define CHK_TRANS_RD_RX_SIZE1 6'b010001
+`define CHK_TRANS_RD_RX_SIZE2 6'b010010
+`define CHK_TRANS_RD_TRANS_TYPE 6'b010011
+`define CHK_TRANS_WT_UNGNT 6'b010100
+`define SETUP_CHK_ERR 6'b010101
+`define SETUP_GET_DATA_DAT1 6'b010110
+`define SETUP_GET_DATA_WT_GNT 6'b010111
+`define SETUP_GET_DATA_DAT2 6'b011000
+`define SETUP_GET_DATA_DAT3 6'b011001
+`define SETUP_GET_DATA_DAT4 6'b011010
+`define SETUP_GET_DATA_DAT6 6'b011011
+`define SETUP_GET_DATA_DAT5 6'b011100
+`define SETUP_GET_DATA_DAT8 6'b011101
+`define SETUP_GET_DATA_DAT7 6'b011110
+`define SETUP_GET_DATA_WT_UNGNT 6'b011111
+`define SETUP_GET_STAT 6'b100000
+`define SETUP_SET_ADDR 6'b100001
+`define SETUP_GET_DESC_S1 6'b100010
+`define SETUP_CHK_MAX_LEN 6'b100011
+`define OUT_CHK_SEQ 6'b100100
+`define IN_CHK_ACK 6'b100101
+`define IN_SET_PTR 6'b100110
+`define IN_SET_ADDR 6'b100111
+`define IN_WT_GNT 6'b101000
+`define IN_WT_UNGNT 6'b101001
+`define DO_TRANS_RX_EMPTY 6'b101010
+`define DO_TRANS_WT_TRANS_DONE_DEL 6'b101011
+`define START 6'b101100
+`define INIT_CONN 6'b101101
+`define INIT_WT_CONN 6'b101110
+`define DO_TRANS_DEL 6'b101111
+`define SETUP_PTR_SET 6'b110000
+
+reg [5:0]CurrState_EP0St, NextState_EP0St;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: EP0St
+
+// NextState logic (combinatorial)
+always @ (wb_ack or wbBusGnt or cnt or wb_data_i or memData or txDataIndex or txDataSize or transDone or epStatus or epTransType or rxDataSize or bRequest or wValue or wLength or dataSeq or updateUSBAddress or txPacketRemSize or USBAddress or wb_addr or wb_data_o or wb_stb or wb_we or wbBusReq or initComplete or memAddr or memRdEn or bm_req_dir or bm_req_type or bm_req_recp or wIndex or CurrState_EP0St)
+begin
+  NextState_EP0St <= CurrState_EP0St;
+  // Set default values for outputs and signals
+  next_wb_addr <= wb_addr;
+  next_wb_data_o <= wb_data_o;
+  next_wb_stb <= wb_stb;
+  next_wb_we <= wb_we;
+  next_cnt <= cnt;
+  next_wbBusReq <= wbBusReq;
+  next_initComplete <= initComplete;
+  next_memAddr <= memAddr;
+  next_memRdEn <= memRdEn;
+  next_txDataSize <= txDataSize;
+  next_txDataIndex <= txDataIndex;
+  next_transDone <= transDone;
+  next_epStatus <= epStatus;
+  next_rxDataSize <= rxDataSize;
+  next_epTransType <= epTransType;
+  next_bm_req_dir <= bm_req_dir;
+  next_bm_req_type <= bm_req_type;
+  next_bm_req_recp <= bm_req_recp;
+  next_bRequest <= bRequest;
+  next_wValue <= wValue;
+  next_wIndex <= wIndex;
+  next_wLength <= wLength;
+  next_txPacketRemSize <= txPacketRemSize;
+  next_USBAddress <= USBAddress;
+  next_updateUSBAddress <= updateUSBAddress;
+  next_dataSeq <= dataSeq;
+  case (CurrState_EP0St)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_initComplete <= 1'b0;
+      next_wbBusReq <= 1'b0;
+      next_wb_addr <= 8'h00;
+      next_wb_data_o <= 8'h00;
+      next_wb_stb <= 1'b0;
+      next_wb_we <= 1'b0;
+      next_txPacketRemSize <= 8'h00;
+      next_txDataSize <= 8'h00;
+      next_txDataIndex <= 8'h00;
+      next_epTransType <= 8'h00;
+      next_epStatus <= 8'h00;
+      next_rxDataSize <= 16'h0000;
+      next_cnt <= 8'h00;
+      next_memRdEn <= 1'b0;
+      next_memAddr <= 8'h00;
+      next_updateUSBAddress <= 1'b0;
+      next_transDone <= 1'b0;
+      next_bm_req_type <= 2'b00;
+      next_bm_req_dir <= 1'b0;
+      next_bm_req_recp <= 5'b00000;
+      next_bRequest <= 8'h00;
+      next_wLength <= 16'h0000;
+      next_wIndex <= 16'h0000;
+      next_wValue <= 16'h0000;
+      next_dataSeq <= 1'b0;
+      next_USBAddress <= 8'h00;
+      NextState_EP0St <= `INIT_WT_GNT;
+    end
+    `CHK_TRANS_RD_STAT:
+    begin
+      next_wb_addr <= `RA_EP0_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE1;
+        next_wb_stb <= 1'b0;
+        next_epStatus <= wb_data_i;
+      end
+    end
+    `CHK_TRANS_WT_GNT:
+    begin
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_RD_STAT;
+      end
+    end
+    `CHK_TRANS_RD_RX_SIZE1:
+    begin
+      next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_MSB;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_RD_RX_SIZE2;
+        next_wb_stb <= 1'b0;
+        next_rxDataSize[15:8] <= wb_data_i;
+      end
+    end
+    `CHK_TRANS_RD_RX_SIZE2:
+    begin
+      next_wb_addr <= `RA_EP0_RX_FIFO_DATA_COUNT_LSB;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_RD_TRANS_TYPE;
+        next_wb_stb <= 1'b0;
+        next_rxDataSize[7:0] <= wb_data_i;
+      end
+    end
+    `CHK_TRANS_RD_TRANS_TYPE:
+    begin
+      next_wb_addr <= `RA_EP0_TRANSTYPE_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_epTransType <= wb_data_i;
+      end
+    end
+    `CHK_TRANS_WT_UNGNT:
+    begin
+      next_wbBusReq <= 1'b0;
+      if ((wbBusGnt == 1'b0) && ((epStatus & 8'h0f) != 8'h00))
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+      else if ((wbBusGnt == 1'b0) && (epTransType == `SC_SETUP_TRANS))
+      begin
+        NextState_EP0St <= `SETUP_CHK_ERR;
+      end
+      else if ((wbBusGnt == 1'b0) && (epTransType == `SC_IN_TRANS))
+      begin
+        NextState_EP0St <= `IN_CHK_ACK;
+      end
+      else if ((wbBusGnt == 1'b0) && (epTransType == `SC_OUTDATA_TRANS))
+      begin
+        NextState_EP0St <= `OUT_CHK_SEQ;
+      end
+      else if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+    end
+    `DO_TRANS_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_TX_EMPTY;
+      end
+    end
+    `DO_TRANS_TX_EMPTY:
+    begin
+      next_wb_addr <= `RA_EP0_TX_FIFO_CONTROL_REG;
+      next_wb_data_o <= 8'h01;
+      //force tx fifo empty
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_RX_EMPTY;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO:
+    begin
+      next_wb_data_o <= memData;
+      next_wb_addr <= `RA_EP0_TX_FIFO_DATA_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_CHK_TX_DONE;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_RD_MEM:
+    begin
+      next_memAddr <= txDataIndex;
+      next_memRdEn <= 1'b1;
+      next_txDataSize <= txDataSize - 1'b1;
+      next_txDataIndex <= txDataIndex + 1'b1;
+      NextState_EP0St <= `DO_TRANS_DEL;
+    end
+    `DO_TRANS_CHK_TX_DONE:
+    begin
+      if (txDataSize == 8'h00)
+      begin
+        NextState_EP0St <= `DO_TRANS_TRANS_GO;
+      end
+      else
+      begin
+        NextState_EP0St <= `DO_TRANS_RD_MEM;
+      end
+    end
+    `DO_TRANS_TRANS_GO:
+    begin
+      next_wb_addr <= `RA_EP0_CONTROL_REG;
+      if (dataSeq == 1'b1)
+      next_wb_data_o <= 8'h07;
+      else
+      next_wb_data_o <= 8'h03;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+        next_wb_stb <= 1'b0;
+        next_transDone <= 1'b0;
+      end
+    end
+    `DO_TRANS_RX_EMPTY:
+    begin
+      next_wb_addr <= `RA_EP0_RX_FIFO_CONTROL_REG;
+      next_wb_data_o <= 8'h01;
+      //force rx fifo empty
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if ((wb_ack == 1'b1) && (txDataSize != 8'h00))
+      begin
+        NextState_EP0St <= `DO_TRANS_RD_MEM;
+        next_wb_stb <= 1'b0;
+      end
+      else if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_TRANS_GO;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_DEL:
+    begin
+      next_memRdEn <= 1'b0;
+      NextState_EP0St <= `DO_TRANS_WR_TX_FIFO;
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
+    begin
+      next_wb_addr <= `RA_EP0_CONTROL_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
+    begin
+      next_wbBusReq <= 1'b0;
+      if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_CHK_DONE:
+    begin
+      if (transDone == 1'b1)
+      begin
+        NextState_EP0St <= `CHK_TRANS_WT_GNT;
+        next_wbBusReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_DEL;
+        next_cnt <= 8'h00;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_DEL:
+    begin
+      next_cnt <= cnt + 1'b1;
+      if (cnt == `ONE_USEC_DEL)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+      end
+    end
+    `SETUP_CHK_ERR:
+    begin
+      if (rxDataSize != 16'h0008)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+      else
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_WT_GNT;
+        next_wbBusReq <= 1'b1;
+        next_txDataSize <= 8'h00;
+        next_txPacketRemSize <= 8'h00;
+        //default tx packet size
+        next_dataSeq <= 1'b1;
+        next_wb_addr <= `RA_EP0_RX_FIFO_DATA_REG;
+        next_wb_we <= 1'b0;
+      end
+    end
+    `SETUP_GET_STAT:
+    begin
+      if (bm_req_type == 2'b00)  begin
+      next_txPacketRemSize <= 8'h02;
+      if (bm_req_recp == 5'b00000)
+      next_txDataIndex <= `ONE_ZERO_STAT_INDEX;
+      else
+      next_txDataIndex <= `ZERO_ZERO_STAT_INDEX;
+      end
+      else if (bm_req_type == 2'b10) begin
+      next_txDataIndex <= `VENDOR_DATA_STAT_INDEX;
+      next_txPacketRemSize <= 8'h02;
+      end
+      NextState_EP0St <= `SETUP_CHK_MAX_LEN;
+    end
+    `SETUP_SET_ADDR:
+    begin
+      if ( (wValue[15:7] == {9{1'b0}}) && (wIndex == 16'h0000) && (wLength == 16'h0000) ) begin
+      next_USBAddress <= wValue[7:0];
+      next_updateUSBAddress <= 1'b1;
+      end
+      NextState_EP0St <= `SETUP_CHK_MAX_LEN;
+    end
+    `SETUP_CHK_MAX_LEN:
+    begin
+      if (txPacketRemSize > wLength)
+      next_txPacketRemSize <= wLength;
+      NextState_EP0St <= `SETUP_PTR_SET;
+    end
+    `SETUP_PTR_SET:
+    begin
+      if (txPacketRemSize > `MAX_RESP_SIZE) begin
+      next_txDataSize <= `MAX_RESP_SIZE;
+      next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
+      end
+      else begin
+      next_txDataSize <= txPacketRemSize;
+      next_txPacketRemSize <= 8'h00;
+      end
+      NextState_EP0St <= `DO_TRANS_WT_GNT;
+    end
+    `SETUP_GET_DATA_DAT1:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT2;
+        next_wb_stb <= 1'b0;
+        next_bm_req_dir <= wb_data_i[7];
+        next_bm_req_type <= wb_data_i[6:5];
+        next_bm_req_recp <= wb_data_i[4:0];
+      end
+    end
+    `SETUP_GET_DATA_WT_GNT:
+    begin
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT1;
+      end
+    end
+    `SETUP_GET_DATA_DAT2:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT3;
+        next_wb_stb <= 1'b0;
+        next_bRequest <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT3:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT4;
+        next_wb_stb <= 1'b0;
+        next_wValue[7:0] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT4:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT5;
+        next_wb_stb <= 1'b0;
+        next_wValue[15:8] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT6:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT7;
+        next_wb_stb <= 1'b0;
+        next_wIndex[15:8] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT5:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT6;
+        next_wb_stb <= 1'b0;
+        next_wIndex[7:0] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_DAT8:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_wLength[15:8] <= wb_data_i;
+        next_wbBusReq <= 1'b0;
+      end
+    end
+    `SETUP_GET_DATA_DAT7:
+    begin
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `SETUP_GET_DATA_DAT8;
+        next_wb_stb <= 1'b0;
+        next_wLength[7:0] <= wb_data_i;
+      end
+    end
+    `SETUP_GET_DATA_WT_UNGNT:
+    begin
+      if ((wbBusGnt == 1'b0) && (bRequest == `GET_STATUS))
+      begin
+        NextState_EP0St <= `SETUP_GET_STAT;
+      end
+      else if ((wbBusGnt == 1'b0) && (bRequest == `GET_DESCRIPTOR))
+      begin
+        NextState_EP0St <= `SETUP_GET_DESC_S1;
+      end
+      else if ((wbBusGnt == 1'b0) && (bRequest == `SET_ADDRESS))
+      begin
+        NextState_EP0St <= `SETUP_SET_ADDR;
+      end
+      else if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+    end
+    `SETUP_GET_DESC_S1:
+    begin
+      case (wValue[15:8])
+      `DEV_DESC: begin
+      next_txPacketRemSize <= `DEV_DESC_SIZE;
+      next_txDataIndex <= `DEV_DESC_INDEX;
+      end
+      `CFG_DESC: begin
+      next_txPacketRemSize <= `CFG_DESC_SIZE;
+      next_txDataIndex <= `CFG_DESC_INDEX;
+      end
+      `REP_DESC: begin
+      next_txPacketRemSize <= `REP_DESC_SIZE;
+      next_txDataIndex <= `REP_DESC_INDEX;
+      end
+      `STRING_DESC: begin
+      case (wValue[3:0])
+      4'h0: begin
+      next_txPacketRemSize <= `LANGID_DESC_SIZE;
+      next_txDataIndex <= `LANGID_DESC_INDEX;
+      end
+      4'h1: begin
+      next_txPacketRemSize <= `STRING1_DESC_SIZE;
+      next_txDataIndex <= `STRING1_DESC_INDEX;
+      end
+      4'h2: begin
+      next_txPacketRemSize <= `STRING2_DESC_SIZE;
+      next_txDataIndex <= `STRING2_DESC_INDEX;
+      end
+      4'h3: begin
+      next_txPacketRemSize <= `STRING3_DESC_SIZE;
+      next_txDataIndex <= `STRING3_DESC_INDEX;
+      end
+      endcase
+      end
+      endcase
+      NextState_EP0St <= `SETUP_CHK_MAX_LEN;
+    end
+    `IN_CHK_ACK:
+    begin
+      if (epStatus[`SC_ACK_RXED_BIT] != 1'b1)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+      else if (updateUSBAddress == 1'b1)
+      begin
+        NextState_EP0St <= `IN_WT_GNT;
+      end
+      else
+      begin
+        NextState_EP0St <= `IN_SET_PTR;
+      end
+    end
+    `IN_SET_PTR:
+    begin
+      if (txPacketRemSize > `MAX_RESP_SIZE) begin
+      next_txDataSize <= `MAX_RESP_SIZE;
+      next_txPacketRemSize <= txPacketRemSize - `MAX_RESP_SIZE;
+      end
+      else begin
+      next_txDataSize <= txPacketRemSize;
+      next_txPacketRemSize <= 8'h00;
+      end
+      NextState_EP0St <= `DO_TRANS_WT_GNT;
+    end
+    `IN_SET_ADDR:
+    begin
+      next_wb_addr <= `RA_SC_ADDRESS;
+      next_wb_data_o <= USBAddress;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `IN_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_wbBusReq <= 1'b0;
+      end
+    end
+    `IN_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      next_updateUSBAddress <= 1'b0;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `IN_SET_ADDR;
+      end
+    end
+    `IN_WT_UNGNT:
+    begin
+      if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `IN_SET_PTR;
+      end
+    end
+    `OUT_CHK_SEQ:
+    begin
+      if (epStatus[`SC_DATA_SEQUENCE_BIT] != dataSeq)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+      else
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+        next_dataSeq <= ~dataSeq;
+      end
+    end
+    `INIT_RST:
+    begin
+      next_wb_addr <= `RA_HOST_SLAVE_MODE;
+      next_wb_data_o <= 8'h2;
+      //reset usbHostSlave
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `INIT_WT_RST;
+        next_wb_stb <= 1'b0;
+        next_cnt <= 8'h00;
+      end
+    end
+    `INIT_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP0St <= `INIT_RST;
+      end
+    end
+    `INIT_WT_RST:
+    begin
+      next_cnt <= cnt + 1'b1;
+      if (cnt == 8'hff)
+      begin
+        NextState_EP0St <= `INIT_WT_VBUS;
+      end
+    end
+    `INIT_WT_VBUS:
+    begin
+      next_wb_addr <= `RA_SC_LINE_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if ((wb_ack == 1'b1)  && (wb_data_i[`VBUS_PRES_BIT] == 1'b1))
+      begin
+        NextState_EP0St <= `INIT_CONN;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `INIT_FIN:
+    begin
+      next_wbBusReq <= 1'b0;
+      next_initComplete <= 1'b1;
+      if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP0St <= `DO_TRANS_WT_GNT;
+      end
+    end
+    `INIT_CONN:
+    begin
+      next_wb_addr <= `RA_SC_CONTROL_REG;
+      next_wb_data_o <= 8'h71;
+      //connect to host, full speed
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP0St <= `INIT_WT_CONN;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `INIT_WT_CONN:
+    begin
+      next_wb_addr <= `RA_SC_LINE_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if ((wb_ack == 1'b1) && (wb_data_i[1:0] == `FULL_SPEED_CONNECT))
+      begin
+        NextState_EP0St <= `INIT_FIN;
+        next_wb_stb <= 1'b0;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+    CurrState_EP0St <= `START;
+  else
+    CurrState_EP0St <= NextState_EP0St;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    wb_addr <= 8'h00;
+    wb_data_o <= 8'h00;
+    wb_stb <= 1'b0;
+    wb_we <= 1'b0;
+    wbBusReq <= 1'b0;
+    initComplete <= 1'b0;
+    memAddr <= 8'h00;
+    memRdEn <= 1'b0;
+    cnt <= 8'h00;
+    txDataSize <= 8'h00;
+    txDataIndex <= 8'h00;
+    transDone <= 1'b0;
+    epStatus <= 8'h00;
+    rxDataSize <= 16'h0000;
+    epTransType <= 8'h00;
+    bm_req_dir <= 1'b0;
+    bm_req_type <= 2'b00;
+    bm_req_recp <= 5'b00000;
+    bRequest <= 8'h00;
+    wValue <= 16'h0000;
+    wIndex <= 16'h0000;
+    wLength <= 16'h0000;
+    txPacketRemSize <= 8'h00;
+    USBAddress <= 8'h00;
+    updateUSBAddress <= 1'b0;
+    dataSeq <= 1'b0;
+  end
+  else 
+  begin
+    wb_addr <= next_wb_addr;
+    wb_data_o <= next_wb_data_o;
+    wb_stb <= next_wb_stb;
+    wb_we <= next_wb_we;
+    wbBusReq <= next_wbBusReq;
+    initComplete <= next_initComplete;
+    memAddr <= next_memAddr;
+    memRdEn <= next_memRdEn;
+    cnt <= next_cnt;
+    txDataSize <= next_txDataSize;
+    txDataIndex <= next_txDataIndex;
+    transDone <= next_transDone;
+    epStatus <= next_epStatus;
+    rxDataSize <= next_rxDataSize;
+    epTransType <= next_epTransType;
+    bm_req_dir <= next_bm_req_dir;
+    bm_req_type <= next_bm_req_type;
+    bm_req_recp <= next_bm_req_recp;
+    bRequest <= next_bRequest;
+    wValue <= next_wValue;
+    wIndex <= next_wIndex;
+    wLength <= next_wLength;
+    txPacketRemSize <= next_txPacketRemSize;
+    USBAddress <= next_USBAddress;
+    updateUSBAddress <= next_updateUSBAddress;
+    dataSeq <= next_dataSeq;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/SIETransmitter.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/SIETransmitter.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/SIETransmitter.v	(revision 264)
@@ -0,0 +1,714 @@
+
+// File        : ../RTL/serialInterfaceEngine/SIETransmitter.v
+// Generated   : 10/15/06 20:31:22
+// From        : ../RTL/serialInterfaceEngine/SIETransmitter.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIETransmitter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+
+module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC);
+input   [15:0] CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0] CRC5Result;
+input   CRC5UpdateRdy;
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [7:0] SIEPortCtrlIn;
+input   [7:0] SIEPortDataIn;
+input   SIEPortWEn;
+input   USBWireGnt;
+input   USBWireRdy;
+input   clk;
+input   fullSpeedRateIn;
+input   processTxByteRdy;
+input   rst;
+output  CRC16En;
+output  CRC5En;
+output  CRC5_8Bit;
+output  [7:0] CRCData;
+output  SIEPortTxRdy;
+output  [7:0] TxByteOutCtrl;
+output  TxByteOutFullSpeedRate;
+output  [7:0] TxByteOut;
+output  USBWireCtrl;
+output  [1:0] USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+output  processTxByteWEn;
+output  rstCRC;
+
+reg     CRC16En, next_CRC16En;
+wire    [15:0] CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5En, next_CRC5En;
+wire    [4:0] CRC5Result;
+wire    CRC5UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     [7:0] CRCData, next_CRCData;
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [7:0] SIEPortCtrlIn;
+wire    [7:0] SIEPortDataIn;
+reg     SIEPortTxRdy, next_SIEPortTxRdy;
+wire    SIEPortWEn;
+reg     [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
+reg     TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
+reg     [7:0] TxByteOut, next_TxByteOut;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0] USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+wire    fullSpeedRateIn;
+wire    processTxByteRdy;
+reg     processTxByteWEn, next_processTxByteWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+
+// diagram signals declarations
+reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
+reg  [7:0]SIEPortData, next_SIEPortData;
+reg  [2:0]i, next_i;
+reg  [15:0]resumeCnt, next_resumeCnt;
+
+// BINARY ENCODED state machine: SIETx
+// State codes definitions:
+`define DIR_CTL_CHK_FIN 6'b000000
+`define RES_ST_CHK_FIN 6'b000001
+`define PKT_ST_CHK_PID 6'b000010
+`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
+`define IDLE 6'b000100
+`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
+`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
+`define PKT_ST_HS_PKT_SENT 6'b000111
+`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
+`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
+`define PKT_ST_SPCL_PKT_SENT 6'b001010
+`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
+`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
+`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
+`define RES_ST_SND_J_1 6'b001110
+`define RES_ST_SND_J_2 6'b001111
+`define RES_ST_SND_SE0_1 6'b010000
+`define RES_ST_SND_SE0_2 6'b010001
+`define START_SIETX 6'b010010
+`define STX_CHK_ST 6'b010011
+`define STX_WAIT_BYTE 6'b010100
+`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
+`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
+`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
+`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000
+`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011001
+`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011010
+`define DIR_CTL_WAIT_GNT 6'b011011
+`define RES_ST_WAIT_GNT 6'b011100
+`define PKT_ST_HS_WAIT_RDY 6'b011101
+`define DIR_CTL_WAIT_RDY 6'b011110
+`define PKT_ST_SPCL_WAIT_RDY 6'b011111
+`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
+`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
+`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100010
+`define RES_ST_WAIT_RDY 6'b100011
+`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
+`define PKT_ST_DATA_PID_WAIT_RDY 6'b100101
+`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110
+`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111
+`define PKT_ST_WAIT_RDY_PKT 6'b101000
+`define RES_ST_W_RDY1 6'b101001
+`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
+`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
+`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
+`define TX_LS_EOP_WAIT_GNT1 6'b101101
+`define TX_LS_EOP_SND_SE0_2 6'b101110
+`define TX_LS_EOP_SND_SE0_1 6'b101111
+`define TX_LS_EOP_W_RDY1 6'b110000
+`define TX_LS_EOP_SND_J 6'b110001
+`define TX_LS_EOP_W_RDY2 6'b110010
+`define TX_LS_EOP_W_RDY3 6'b110011
+`define RES_ST_DELAY 6'b110100
+`define RES_ST_W_RDY2 6'b110101
+`define RES_ST_W_RDY3 6'b110110
+`define RES_ST_W_RDY4 6'b110111
+`define DIR_CTL_DELAY 6'b111000
+
+reg [5:0] CurrState_SIETx;
+reg [5:0] NextState_SIETx;
+
+
+//--------------------------------------------------------------------
+// Machine: SIETx
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx)
+begin : SIETx_NextState
+  NextState_SIETx <= CurrState_SIETx;
+  // Set default values for outputs and signals
+  next_processTxByteWEn <= processTxByteWEn;
+  next_TxByteOut <= TxByteOut;
+  next_TxByteOutCtrl <= TxByteOutCtrl;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_USBWireReq <= USBWireReq;
+  next_USBWireWEn <= USBWireWEn;
+  next_rstCRC <= rstCRC;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_SIEPortTxRdy <= SIEPortTxRdy;
+  next_SIEPortData <= SIEPortData;
+  next_SIEPortCtrl <= SIEPortCtrl;
+  next_i <= i;
+  next_resumeCnt <= resumeCnt;
+  next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  case (CurrState_SIETx)
+    `IDLE:
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    `START_SIETX:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_TxByteOut <= 8'h00;
+      next_TxByteOutCtrl <= 8'h00;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_SIEPortTxRdy <= 1'b0;
+      next_SIEPortData <= 8'h00;
+      next_SIEPortCtrl <= 8'h00;
+      next_i <= 3'h0;
+      next_resumeCnt <= 16'h0000;
+      next_TxByteOutFullSpeedRate <= 1'b0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `STX_CHK_ST:
+      if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))	
+      begin
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+        next_TxByteOutFullSpeedRate <= 1'b1;
+        //SOF and PRE always at full speed
+      end
+      else if (SIEPortCtrl == `TX_PACKET_START)	
+        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
+      else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)	
+      begin
+        NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)	
+      begin
+        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (SIEPortCtrl == `TX_IDLE)	
+        NextState_SIETx <= `IDLE;
+      else if (SIEPortCtrl == `TX_RESUME_START)	
+      begin
+        NextState_SIETx <= `RES_ST_WAIT_GNT;
+        next_USBWireReq <= 1'b1;
+        next_resumeCnt <= 16'h0000;
+        next_USBWireFullSpeedRate <= 1'b0;
+        //resume always uses low speed timing
+      end
+    `STX_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)	
+      begin
+        NextState_SIETx <= `STX_CHK_ST;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+        next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
+        next_USBWireFullSpeedRate <= fullSpeedRateIn;
+      end
+    end
+    `DIR_CTL_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_i <= i + 1'b1;
+      if (i == 3'h7)	
+      begin
+        NextState_SIETx <= `STX_WAIT_BYTE;
+        next_USBWireReq <= 1'b0;
+      end
+      else
+        NextState_SIETx <= `DIR_CTL_DELAY;
+    end
+    `DIR_CTL_WAIT_GNT:
+    begin
+      next_i <= 3'h0;
+      if (USBWireGnt == 1'b1)	
+        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+    end
+    `DIR_CTL_WAIT_RDY:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `DIR_CTL_CHK_FIN;
+        next_USBWireData <= SIEPortData[1:0];
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `DIR_CTL_DELAY:
+      NextState_SIETx <= `DIR_CTL_WAIT_RDY;
+    `PKT_ST_CHK_PID:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      if (SIEPortData[1:0] == `TOKEN)	
+        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
+      else if (SIEPortData[1:0] == `HANDSHAKE)	
+        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
+      else if (SIEPortData[1:0] == `DATA)	
+        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
+      else if (SIEPortData[1:0] == `SPECIAL)	
+        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
+    end
+    `PKT_ST_WAIT_RDY_PKT:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_CHK_PID;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= `SYNC_BYTE;
+        next_TxByteOutCtrl <= `DATA_START;
+      end
+    `PKT_ST_DATA_CRC_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
+    end
+    `PKT_ST_DATA_CRC_PKT_SENT2:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_CRC_WAIT_RDY1:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[7:0];
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    `PKT_ST_DATA_CRC_WAIT_RDY2:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= ~CRC16Result[15:8];
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    `PKT_ST_DATA_DATA_CHK_STOP:
+      if (SIEPortCtrl == `TX_PACKET_STOP)	
+        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
+      else
+        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
+    `PKT_ST_DATA_DATA_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_DATA_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC16En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
+    end
+    `PKT_ST_DATA_DATA_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_RDY:
+    begin
+      next_CRC16En <= 1'b0;
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
+      if (CRC16UpdateRdy == 1'b1)	
+        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
+    `PKT_ST_DATA_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
+    end
+    `PKT_ST_DATA_PID_WAIT_RDY:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    `PKT_ST_HS_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_HS_WAIT_RDY:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    `PKT_ST_SPCL_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_SPCL_WAIT_RDY:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    `PKT_ST_TKN_BYTE1_PKT_SENT1:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_BYTE1_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b1;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+      end
+    end
+    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
+      if (CRC5UpdateRdy == 1'b1)	
+        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
+    `PKT_ST_TKN_CRC_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_CRC_UPD_CRC:
+    begin
+      next_CRCData <= SIEPortData;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC5En <= 1'b1;
+      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
+    end
+    `PKT_ST_TKN_CRC_WAIT_BYTE:
+    begin
+      next_SIEPortTxRdy <= 1'b1;
+      if (SIEPortWEn == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
+        next_SIEPortData <= SIEPortDataIn;
+        next_SIEPortCtrl <= SIEPortCtrlIn;
+        next_SIEPortTxRdy <= 1'b0;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_RDY:
+    begin
+      next_CRC5En <= 1'b0;
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
+        next_TxByteOutCtrl <= `DATA_STOP;
+      end
+    end
+    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
+      if (CRC5UpdateRdy == 1'b1)	
+        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
+    `PKT_ST_TKN_PID_PKT_SENT:
+    begin
+      next_processTxByteWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
+    end
+    `PKT_ST_TKN_PID_WAIT_RDY:
+      if (processTxByteRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
+        next_processTxByteWEn <= 1'b1;
+        next_TxByteOut <= SIEPortData;
+        next_TxByteOutCtrl <= `DATA_STREAM;
+        next_rstCRC <= 1'b1;
+      end
+    `RES_ST_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (resumeCnt == `HOST_TX_RESUME_TIME)	
+        NextState_SIETx <= `RES_ST_W_RDY1;
+      else
+        NextState_SIETx <= `RES_ST_DELAY;
+    end
+    `RES_ST_SND_J_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY4;
+    end
+    `RES_ST_SND_J_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+      next_USBWireFullSpeedRate <= fullSpeedRateIn;
+    end
+    `RES_ST_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY2;
+    end
+    `RES_ST_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `RES_ST_W_RDY3;
+    end
+    `RES_ST_WAIT_GNT:
+      if (USBWireGnt == 1'b1)	
+        NextState_SIETx <= `RES_ST_WAIT_RDY;
+    `RES_ST_WAIT_RDY:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_CHK_FIN;
+        next_USBWireData <= KBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+        next_resumeCnt <= resumeCnt  + 1'b1;
+      end
+    `RES_ST_W_RDY1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `RES_ST_DELAY:
+      NextState_SIETx <= `RES_ST_WAIT_RDY;
+    `RES_ST_W_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `RES_ST_W_RDY3:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `RES_ST_W_RDY4:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `RES_ST_SND_J_2;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `TX_LS_EOP_WAIT_GNT1:
+      if (USBWireGnt == 1'b1)	
+        NextState_SIETx <= `TX_LS_EOP_W_RDY1;
+    `TX_LS_EOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY3;
+    end
+    `TX_LS_EOP_SND_SE0_1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_SIETx <= `TX_LS_EOP_W_RDY2;
+    end
+    `TX_LS_EOP_W_RDY1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `TX_LS_EOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      NextState_SIETx <= `STX_WAIT_BYTE;
+    end
+    `TX_LS_EOP_W_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `TX_LS_EOP_W_RDY3:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_SIETx <= `TX_LS_EOP_SND_J;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SIETx_CurrentState
+  if (rst)	
+    CurrState_SIETx <= `START_SIETX;
+  else
+    CurrState_SIETx <= NextState_SIETx;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SIETx_RegOutput
+  if (rst)	
+  begin
+    SIEPortData <= 8'h00;
+    SIEPortCtrl <= 8'h00;
+    i <= 3'h0;
+    resumeCnt <= 16'h0000;
+    processTxByteWEn <= 1'b0;
+    TxByteOut <= 8'h00;
+    TxByteOutCtrl <= 8'h00;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    USBWireReq <= 1'b0;
+    USBWireWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    SIEPortTxRdy <= 1'b0;
+    TxByteOutFullSpeedRate <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+  end
+  else 
+  begin
+    SIEPortData <= next_SIEPortData;
+    SIEPortCtrl <= next_SIEPortCtrl;
+    i <= next_i;
+    resumeCnt <= next_resumeCnt;
+    processTxByteWEn <= next_processTxByteWEn;
+    TxByteOut <= next_TxByteOut;
+    TxByteOutCtrl <= next_TxByteOutCtrl;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    USBWireReq <= next_USBWireReq;
+    USBWireWEn <= next_USBWireWEn;
+    rstCRC <= next_rstCRC;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    SIEPortTxRdy <= next_SIEPortTxRdy;
+    TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/checkLineState.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/checkLineState.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/checkLineState.v	(revision 264)
@@ -0,0 +1,202 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// checkLineState.v                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Checks USB line state. When reset state detected
+//// asserts usbRstDet for one clock tick
+//// usbRstDet is used to reset most of the logic.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSlaveControl_h.v"
+`include "usbHostSlaveReg_define.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbDevice_define.v"
+module checkLineState (clk, initComplete, rst, usbRstDet, wb_ack, wb_addr, wb_data_i, wb_stb, wb_we, wbBusGnt, wbBusReq);
+input   clk;
+input   initComplete;
+input   rst;
+input   wb_ack;
+input   [7:0]wb_data_i;
+input   wbBusGnt;
+output  usbRstDet;
+output  [7:0]wb_addr;
+output  wb_stb;
+output  wb_we;
+output  wbBusReq;
+
+wire    clk;
+wire    initComplete;
+wire    rst;
+reg     usbRstDet, next_usbRstDet;
+wire    wb_ack;
+reg     [7:0]wb_addr, next_wb_addr;
+wire    [7:0]wb_data_i;
+reg     wb_stb, next_wb_stb;
+reg     wb_we, next_wb_we;
+wire    wbBusGnt;
+reg     wbBusReq, next_wbBusReq;
+
+// diagram signals declarations
+reg  [15:0]cnt, next_cnt;
+reg  [1:0]resetState, next_resetState;
+
+// BINARY ENCODED state machine: chkLSt
+// State codes definitions:
+`define START 3'b000
+`define GET_STAT 3'b001
+`define WT_GNT 3'b010
+`define SET_RST_DET 3'b011
+`define DEL_ONE_MSEC 3'b100
+
+reg [2:0]CurrState_chkLSt, NextState_chkLSt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: chkLSt
+
+// NextState logic (combinatorial)
+always @ (initComplete or wb_ack or resetState or wbBusGnt or cnt or usbRstDet or wbBusReq or wb_addr or wb_stb or wb_we or CurrState_chkLSt)
+begin
+  NextState_chkLSt <= CurrState_chkLSt;
+  // Set default values for outputs and signals
+  next_usbRstDet <= usbRstDet;
+  next_wbBusReq <= wbBusReq;
+  next_wb_addr <= wb_addr;
+  next_wb_stb <= wb_stb;
+  next_wb_we <= wb_we;
+  next_cnt <= cnt;
+  next_resetState <= resetState;
+  case (CurrState_chkLSt)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_usbRstDet <= 1'b0;
+      next_wbBusReq <= 1'b0;
+      next_wb_addr <= 8'h00;
+      next_wb_stb <= 1'b0;
+      next_wb_we <= 1'b0;
+      next_cnt <= 16'h0000;
+      next_resetState <= 2'b00;
+      if (initComplete == 1'b1)
+      begin
+        NextState_chkLSt <= `WT_GNT;
+      end
+    end
+    `GET_STAT:
+    begin
+      next_wb_addr <= `RA_SC_LINE_STATUS_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_chkLSt <= `SET_RST_DET;
+        next_wb_stb <= 1'b0;
+        if ( (wb_data_i[1:0] == `DISCONNECT) || (wb_data_i[`VBUS_PRES_BIT] == 1'b0) )
+        next_resetState <= {resetState[0], 1'b1};
+        else
+        next_resetState <= 2'b00;
+        next_wbBusReq <= 1'b0;
+      end
+    end
+    `WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_chkLSt <= `GET_STAT;
+      end
+    end
+    `SET_RST_DET:
+    begin
+      NextState_chkLSt <= `DEL_ONE_MSEC;
+      if (resetState == 2'b11) // if reset condition aserted for 2mS
+      next_usbRstDet <= 1'b1;
+      next_cnt <= 16'h0000;
+    end
+    `DEL_ONE_MSEC:
+    begin
+      next_cnt <= cnt + 1'b1;
+      next_usbRstDet <= 1'b0;
+      if (cnt == `ONE_MSEC_DEL)
+      begin
+        NextState_chkLSt <= `WT_GNT;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+    CurrState_chkLSt <= `START;
+  else
+    CurrState_chkLSt <= NextState_chkLSt;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    usbRstDet <= 1'b0;
+    wbBusReq <= 1'b0;
+    wb_addr <= 8'h00;
+    wb_stb <= 1'b0;
+    wb_we <= 1'b0;
+    cnt <= 16'h0000;
+    resetState <= 2'b00;
+  end
+  else 
+  begin
+    usbRstDet <= next_usbRstDet;
+    wbBusReq <= next_wbBusReq;
+    wb_addr <= next_wb_addr;
+    wb_stb <= next_wb_stb;
+    wb_we <= next_wb_we;
+    cnt <= next_cnt;
+    resetState <= next_resetState;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoRTL.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoRTL.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoRTL.v	(revision 264)
@@ -0,0 +1,164 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// fifoRTL.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized dual clock domain fifo. 
+////  fifo depth is restricted to 2^ADDR_WIDTH
+////  No protection against over runs and under runs.
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn, 
+  dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty,
+  forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo);
+//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+
+// Two clock domains within this module
+// These ports are within 'wrClk' domain
+input wrClk;
+input rstSyncToWrClk;
+input [FIFO_WIDTH-1:0] dataIn;
+input fifoWEn;
+input forceEmptySyncToWrClk;
+output fifoFull;
+
+// These ports are within 'rdClk' domain
+input rdClk;
+input rstSyncToRdClk;
+output [FIFO_WIDTH-1:0] dataOut;
+input fifoREn;
+input forceEmptySyncToRdClk;
+output fifoEmpty;
+output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
+
+wire wrClk;
+wire rdClk;
+wire rstSyncToWrClk;
+wire rstSyncToRdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire fifoWEn;
+wire fifoREn;
+reg fifoFull;
+reg fifoEmpty;
+wire forceEmpty;
+reg  [15:0]numElementsInFifo;
+
+
+// local registers
+reg  [ADDR_WIDTH:0]bufferInIndex; 
+reg  [ADDR_WIDTH:0]bufferInIndexSyncToRdClk;
+reg  [ADDR_WIDTH:0]bufferOutIndex;
+reg  [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk;
+reg  [ADDR_WIDTH-1:0]bufferInIndexToMem;
+reg  [ADDR_WIDTH-1:0]bufferOutIndexToMem;
+reg  [ADDR_WIDTH:0]bufferCnt;
+reg  fifoREnDelayed;
+wire [FIFO_WIDTH-1:0] dataFromMem;
+
+always @(posedge wrClk)
+begin
+  bufferOutIndexSyncToWrClk <= bufferOutIndex;
+  if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1)
+  begin
+    fifoFull <= 1'b0;
+    bufferInIndex <= 0;
+  end
+    else
+    begin
+      if (fifoWEn == 1'b1) begin
+        bufferInIndex <= bufferInIndex + 1'b1;
+      end 
+      if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
+          (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
+        fifoFull <= 1'b1;
+      else
+        fifoFull <= 1'b0;
+    end
+end
+
+always @(bufferInIndexSyncToRdClk or bufferOutIndex) 
+  bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
+
+always @(posedge rdClk)
+begin
+  numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes
+  bufferInIndexSyncToRdClk <= bufferInIndex;
+  if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1)
+  begin
+    fifoEmpty <= 1'b1;
+    bufferOutIndex <= 0;
+    fifoREnDelayed <= 1'b0;
+  end
+    else
+    begin
+      fifoREnDelayed <= fifoREn;
+      if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
+        dataOut <= dataFromMem;
+        bufferOutIndex <= bufferOutIndex + 1'b1;
+      end
+      if (bufferInIndexSyncToRdClk == bufferOutIndex) 
+        fifoEmpty <= 1'b1;
+      else
+        fifoEmpty <= 1'b0;
+    end
+end
+
+
+always @(bufferInIndex or bufferOutIndex) begin
+  bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
+  bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
+end
+
+dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH)  u_dpMem_dc (
+  .addrIn(bufferInIndexToMem),
+  .addrOut(bufferOutIndexToMem),
+  .wrClk(wrClk),
+  .rdClk(rdClk),
+  .dataIn(dataIn),
+  .writeEn(fifoWEn),
+  .readEn(fifoREn),
+  .dataOut(dataFromMem));
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxBit.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxBit.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxBit.v	(revision 264)
@@ -0,0 +1,403 @@
+
+// File        : ../RTL/serialInterfaceEngine/processRxBit.v
+// Generated   : 11/10/06 05:37:22
+// From        : ../RTL/serialInterfaceEngine/processRxBit.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processrxbit
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [1:0] RxBitsIn;
+input   RxWireActive;
+input   clk;
+input   processRxBitsWEn;
+input   processRxByteRdy;
+input   rst;
+output  [7:0] RxCtrlOut;
+output  [7:0] RxDataOut;
+output  processRxBitRdy;
+output  processRxByteWEn;
+output  resumeDetected;
+
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [1:0] RxBitsIn;
+reg     [7:0] RxCtrlOut, next_RxCtrlOut;
+reg     [7:0] RxDataOut, next_RxDataOut;
+wire    RxWireActive;
+wire    clk;
+reg     processRxBitRdy, next_processRxBitRdy;
+wire    processRxBitsWEn;
+wire    processRxByteRdy;
+reg     processRxByteWEn, next_processRxByteWEn;
+reg     resumeDetected, next_resumeDetected;
+wire    rst;
+
+// diagram signals declarations
+reg  [3:0]RXBitCount, next_RXBitCount;
+reg  [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
+reg  [7:0]RXByte, next_RXByte;
+reg  [3:0]RXSameBitCount, next_RXSameBitCount;
+reg  [1:0]RxBits, next_RxBits;
+reg  bitStuffError, next_bitStuffError;
+reg  [1:0]oldRXBits, next_oldRXBits;
+reg  [4:0]resumeWaitCnt, next_resumeWaitCnt;
+
+// BINARY ENCODED state machine: prRxBit
+// State codes definitions:
+`define START 4'b0000
+`define IDLE_FIRST_BIT 4'b0001
+`define WAIT_BITS 4'b0010
+`define IDLE_CHK_KBIT 4'b0011
+`define DATA_RX_LAST_BIT 4'b0100
+`define DATA_RX_CHK_SE0 4'b0101
+`define DATA_RX_DATA_DESTUFF 4'b0110
+`define DATA_RX_BYTE_SEND2 4'b0111
+`define DATA_RX_BYTE_WAIT_RDY 4'b1000
+`define RES_RX_CHK 4'b1001
+`define DATA_RX_ERROR_CHK_RES 4'b1010
+`define RES_END_CHK1 4'b1011
+`define IDLE_WAIT_PRB_RDY 4'b1100
+`define DATA_RX_WAIT_PRB_RDY 4'b1101
+`define DATA_RX_ERROR_WAIT_RDY 4'b1110
+
+reg [3:0] CurrState_prRxBit;
+reg [3:0] NextState_prRxBit;
+
+
+//--------------------------------------------------------------------
+// Machine: prRxBit
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
+begin : prRxBit_NextState
+  NextState_prRxBit <= CurrState_prRxBit;
+  // Set default values for outputs and signals
+  next_processRxByteWEn <= processRxByteWEn;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOut <= RxDataOut;
+  next_resumeDetected <= resumeDetected;
+  next_RXBitStMachCurrState <= RXBitStMachCurrState;
+  next_RxBits <= RxBits;
+  next_RXSameBitCount <= RXSameBitCount;
+  next_RXBitCount <= RXBitCount;
+  next_oldRXBits <= oldRXBits;
+  next_RXByte <= RXByte;
+  next_bitStuffError <= bitStuffError;
+  next_resumeWaitCnt <= resumeWaitCnt;
+  next_processRxBitRdy <= processRxBitRdy;
+  case (CurrState_prRxBit)
+    `START:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOut <= 8'h00;
+      next_resumeDetected <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      next_RxBits <= 2'b00;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h0;
+      next_oldRXBits <= 2'b00;
+      next_RXByte <= 8'h00;
+      next_bitStuffError <= 1'b0;
+      next_resumeWaitCnt <= 5'h0;
+      next_processRxBitRdy <= 1'b1;
+      NextState_prRxBit <= `WAIT_BITS;
+    end
+    `WAIT_BITS:
+      if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))	
+      begin
+        NextState_prRxBit <= `RES_RX_CHK;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))	
+      begin
+        NextState_prRxBit <= `DATA_RX_CHK_SE0;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))	
+      begin
+        NextState_prRxBit <= `IDLE_CHK_KBIT;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+      else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))	
+      begin
+        NextState_prRxBit <= `RES_END_CHK1;
+        next_RxBits <= RxBitsIn;
+        next_processRxBitRdy <= 1'b0;
+      end
+    `IDLE_FIRST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
+      next_RXSameBitCount <= 4'h0;
+      next_RXBitCount <= 4'h1;
+      next_oldRXBits <= RxBits;
+      //zero is always the first RZ data bit of a new packet
+      next_RXByte <= 8'h00;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `IDLE_CHK_KBIT:
+      if ((RxBits == KBit) && (RxWireActive == 1'b1))	
+        NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    `IDLE_WAIT_PRB_RDY:
+      if (processRxByteRdy == 1'b1)	
+      begin
+        NextState_prRxBit <= `IDLE_FIRST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_START;
+        //start of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    `DATA_RX_LAST_BIT:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_CHK_SE0:
+    begin
+      next_bitStuffError <= 1'b0;
+      if (RxBits == `SE0)	
+        NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
+      else
+      begin
+        NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
+        if (RxBits == oldRXBits)                 //if the current 'RxBits' are the same as the old 'RxBits', then
+        begin
+          next_RXSameBitCount <= RXSameBitCount + 1'b1;
+            //inc 'RXSameBitCount'
+            if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
+            next_bitStuffError <= 1'b1;
+                //flag 'bitStuffError'
+            else                                          //else no bit stuffing error
+            begin
+            next_RXBitCount <= RXBitCount + 1'b1;
+                if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
+              next_processRxBitRdy <= 1'b1;
+                    //early indication of ready
+        		end
+            next_RXByte <= { 1'b1, RXByte[7:1]};
+                //RZ bit = 1 (ie no change in 'RxBits')
+            end
+        end
+        else                                            //else current 'RxBits' are different from old 'RxBits'
+        begin
+            if (RXSameBitCount != `MAX_CONSEC_SAME_BITS)  //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
+            begin
+            next_RXBitCount <= RXBitCount + 1'b1;
+                if (RXBitCount != 4'h7) begin
+              next_processRxBitRdy <= 1'b1;
+                    //early indication of ready
+        		end
+            next_RXByte <= {1'b0, RXByte[7:1]};
+                //RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
+            end
+           next_RXSameBitCount <= 4'h0;
+              //reset 'RXSameBitCount'
+        end
+        next_oldRXBits <= RxBits;
+      end
+    end
+    `DATA_RX_WAIT_PRB_RDY:
+      if (processRxByteRdy == 1'b1)	
+      begin
+        NextState_prRxBit <= `DATA_RX_LAST_BIT;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_STOP;
+        //end of packet
+        next_processRxByteWEn <= 1'b1;
+      end
+    `DATA_RX_DATA_DESTUFF:
+      if (RXBitCount == 4'h8 & bitStuffError == 1'b0)	
+        NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
+      else if (bitStuffError == 1'b1)	
+        NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
+      else
+      begin
+        NextState_prRxBit <= `WAIT_BITS;
+        next_processRxBitRdy <= 1'b1;
+      end
+    `DATA_RX_BYTE_SEND2:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_BYTE_WAIT_RDY:
+      if (processRxByteRdy == 1'b1)	
+      begin
+        NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
+        next_RXBitCount <= 4'h0;
+        next_RxDataOut <= RXByte;
+        next_RxCtrlOut <= `DATA_STREAM;
+        next_processRxByteWEn <= 1'b1;
+      end
+    `DATA_RX_ERROR_CHK_RES:
+    begin
+      next_processRxByteWEn <= 1'b0;
+      if (RxBits == JBit)                           //if current bit is a JBit, then
+        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+          //next state is idle
+      else                                          //else
+      begin
+        next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
+          //check for resume
+        next_resumeWaitCnt <= 5'h0;
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `DATA_RX_ERROR_WAIT_RDY:
+      if (processRxByteRdy == 1'b1)	
+      begin
+        NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
+        next_RxDataOut <= 8'h00;
+        //redundant data
+        next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
+        next_processRxByteWEn <= 1'b1;
+      end
+    `RES_RX_CHK:
+    begin
+      if (RxBits != KBit)  //can only be a resume if line remains in Kbit state
+        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+      else
+      begin
+        next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
+          //if we've waited long enough, then
+          if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
+          begin
+          next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
+          next_resumeDetected <= 1'b1;
+              //report resume detected
+          end
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+    `RES_END_CHK1:
+    begin
+      if (RxBits != KBit)  //line must leave KBit state for the end of resume
+      begin
+        next_RXBitStMachCurrState <= `IDLE_BIT_ST;
+        next_resumeDetected <= 1'b0;
+          //clear resume detected flag
+      end
+      NextState_prRxBit <= `WAIT_BITS;
+      next_processRxBitRdy <= 1'b1;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prRxBit_CurrentState
+  if (rst)	
+    CurrState_prRxBit <= `START;
+  else
+    CurrState_prRxBit <= NextState_prRxBit;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prRxBit_RegOutput
+  if (rst)	
+  begin
+    RXBitStMachCurrState <= `IDLE_BIT_ST;
+    RxBits <= 2'b00;
+    RXSameBitCount <= 4'h0;
+    RXBitCount <= 4'h0;
+    oldRXBits <= 2'b00;
+    RXByte <= 8'h00;
+    bitStuffError <= 1'b0;
+    resumeWaitCnt <= 5'h0;
+    processRxByteWEn <= 1'b0;
+    RxCtrlOut <= 8'h00;
+    RxDataOut <= 8'h00;
+    resumeDetected <= 1'b0;
+    processRxBitRdy <= 1'b1;
+  end
+  else 
+  begin
+    RXBitStMachCurrState <= next_RXBitStMachCurrState;
+    RxBits <= next_RxBits;
+    RXSameBitCount <= next_RXSameBitCount;
+    RXBitCount <= next_RXBitCount;
+    oldRXBits <= next_oldRXBits;
+    RXByte <= next_RXByte;
+    bitStuffError <= next_bitStuffError;
+    resumeWaitCnt <= next_resumeWaitCnt;
+    processRxByteWEn <= next_processRxByteWEn;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOut <= next_RxDataOut;
+    resumeDetected <= next_resumeDetected;
+    processRxBitRdy <= next_processRxBitRdy;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/sctxportarbiter.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/sctxportarbiter.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/sctxportarbiter.v	(revision 264)
@@ -0,0 +1,202 @@
+
+// File        : ../RTL/slaveController/sctxportarbiter.v
+// Generated   : 11/10/06 05:37:24
+// From        : ../RTL/slaveController/sctxportarbiter.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SCTxPortArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module SCTxPortArbiter (SCTxPortCntl, SCTxPortData, SCTxPortRdyIn, SCTxPortRdyOut, SCTxPortWEnable, clk, directCntlCntl, directCntlData, directCntlGnt, directCntlReq, directCntlWEn, rst, sendPacketCntl, sendPacketData, sendPacketGnt, sendPacketReq, sendPacketWEn);
+input   SCTxPortRdyIn;
+input   clk;
+input   [7:0] directCntlCntl;
+input   [7:0] directCntlData;
+input   directCntlReq;
+input   directCntlWEn;
+input   rst;
+input   [7:0] sendPacketCntl;
+input   [7:0] sendPacketData;
+input   sendPacketReq;
+input   sendPacketWEn;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortRdyOut;
+output  SCTxPortWEnable;
+output  directCntlGnt;
+output  sendPacketGnt;
+
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortRdyIn;
+reg     SCTxPortRdyOut, next_SCTxPortRdyOut;
+reg     SCTxPortWEnable, next_SCTxPortWEnable;
+wire    clk;
+wire    [7:0] directCntlCntl;
+wire    [7:0] directCntlData;
+reg     directCntlGnt, next_directCntlGnt;
+wire    directCntlReq;
+wire    directCntlWEn;
+wire    rst;
+wire    [7:0] sendPacketCntl;
+wire    [7:0] sendPacketData;
+reg     sendPacketGnt, next_sendPacketGnt;
+wire    sendPacketReq;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  muxDCEn, next_muxDCEn;
+
+// BINARY ENCODED state machine: SCTxArb
+// State codes definitions:
+`define SARB1_WAIT_REQ 2'b00
+`define SARB_SEND_PACKET 2'b01
+`define SARB_DC 2'b10
+`define START_SARB 2'b11
+
+reg [1:0] CurrState_SCTxArb;
+reg [1:0] NextState_SCTxArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// SOFController/directContol/sendPacket mux
+always @(SCTxPortRdyIn)
+begin
+    SCTxPortRdyOut <= SCTxPortRdyIn;
+end
+always @(muxDCEn or
+		 		 directCntlWEn or directCntlData or directCntlCntl or
+                  directCntlWEn or directCntlData or directCntlCntl or
+ 		  		 sendPacketWEn or sendPacketData or sendPacketCntl)
+begin
+if (muxDCEn == 1'b1)
+    begin
+        SCTxPortWEnable <= directCntlWEn;
+        SCTxPortData <= directCntlData;
+        SCTxPortCntl <= directCntlCntl;
+    end
+else
+    begin
+        SCTxPortWEnable <= sendPacketWEn;
+        SCTxPortData <= sendPacketData;
+        SCTxPortCntl <= sendPacketCntl;
+    end
+end
+
+//--------------------------------------------------------------------
+// Machine: SCTxArb
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (sendPacketReq or directCntlReq or sendPacketGnt or muxDCEn or directCntlGnt or CurrState_SCTxArb)
+begin : SCTxArb_NextState
+  NextState_SCTxArb <= CurrState_SCTxArb;
+  // Set default values for outputs and signals
+  next_sendPacketGnt <= sendPacketGnt;
+  next_muxDCEn <= muxDCEn;
+  next_directCntlGnt <= directCntlGnt;
+  case (CurrState_SCTxArb)
+    `SARB1_WAIT_REQ:
+      if (sendPacketReq == 1'b1)	
+      begin
+        NextState_SCTxArb <= `SARB_SEND_PACKET;
+        next_sendPacketGnt <= 1'b1;
+        next_muxDCEn <= 1'b0;
+      end
+      else if (directCntlReq == 1'b1)	
+      begin
+        NextState_SCTxArb <= `SARB_DC;
+        next_directCntlGnt <= 1'b1;
+        next_muxDCEn <= 1'b1;
+      end
+    `SARB_SEND_PACKET:
+      if (sendPacketReq == 1'b0)	
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_sendPacketGnt <= 1'b0;
+      end
+    `SARB_DC:
+      if (directCntlReq == 1'b0)	
+      begin
+        NextState_SCTxArb <= `SARB1_WAIT_REQ;
+        next_directCntlGnt <= 1'b0;
+      end
+    `START_SARB:
+      NextState_SCTxArb <= `SARB1_WAIT_REQ;
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_CurrentState
+  if (rst)	
+    CurrState_SCTxArb <= `START_SARB;
+  else
+    CurrState_SCTxArb <= NextState_SCTxArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : SCTxArb_RegOutput
+  if (rst)	
+  begin
+    muxDCEn <= 1'b0;
+    sendPacketGnt <= 1'b0;
+    directCntlGnt <= 1'b0;
+  end
+  else 
+  begin
+    muxDCEn <= next_muxDCEn;
+    sendPacketGnt <= next_sendPacketGnt;
+    directCntlGnt <= next_directCntlGnt;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveRxStatusMonitor.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveRxStatusMonitor.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveRxStatusMonitor.v	(revision 264)
@@ -0,0 +1,95 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveRxStatusMonitor.v                                       ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module slaveRxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, resetEventOut, resumeIntOut, clk, rst);
+
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+input clk;
+input rst;
+output resetEventOut;
+output [1:0] connectStateOut;
+output resumeIntOut;
+
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+reg resetEventOut;
+reg [1:0] connectStateOut;
+reg resumeIntOut;
+wire clk;
+wire rst;
+
+reg [1:0]oldConnectState;
+reg oldResumeDetected;
+
+always @(connectStateIn)
+begin
+  connectStateOut <= connectStateIn;
+end
+
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+  end
+  else
+  begin
+    oldConnectState <= connectStateIn;
+    oldResumeDetected <= resumeDetectedIn;
+    if (oldConnectState != connectStateIn)
+      resetEventOut <= 1'b1;
+    else
+      resetEventOut <= 1'b0;
+    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
+      resumeIntOut <= 1'b1;
+    else 
+      resumeIntOut <= 1'b0;
+  end
+end
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveGetpacket.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveGetpacket.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveGetpacket.v	(revision 264)
@@ -0,0 +1,357 @@
+
+// File        : ../RTL/slaveController/slaveGetpacket.v
+// Generated   : 11/10/06 05:37:25
+// From        : ../RTL/slaveController/slaveGetpacket.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveGetPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst);
+input   [7:0] RXDataIn;
+input   RXDataValid;
+input   RXFifoFull;
+input   [7:0] RXStreamStatusIn;
+input   SIERxTimeOut;		// Single cycle pulse
+input   clk;
+input   endPointReady;
+input   getPacketEn;
+input   rst;
+output  ACKRxed;
+output  CRCError;
+output  [7:0] RXFifoData;
+output  RXFifoWEn;
+output  RXOverflow;
+output  RXPacketRdy;
+output  RXTimeOut;
+output  [3:0] RxPID;
+output  SIERxTimeOutEn;
+output  bitStuffError;
+output  dataSequence;
+
+reg     ACKRxed, next_ACKRxed;
+reg     CRCError, next_CRCError;
+wire    [7:0] RXDataIn;
+wire    RXDataValid;
+reg     [7:0] RXFifoData, next_RXFifoData;
+wire    RXFifoFull;
+reg     RXFifoWEn, next_RXFifoWEn;
+reg     RXOverflow, next_RXOverflow;
+reg     RXPacketRdy, next_RXPacketRdy;
+wire    [7:0] RXStreamStatusIn;
+reg     RXTimeOut, next_RXTimeOut;
+reg     [3:0] RxPID, next_RxPID;
+wire    SIERxTimeOut;
+reg     SIERxTimeOutEn, next_SIERxTimeOutEn;
+reg     bitStuffError, next_bitStuffError;
+wire    clk;
+reg     dataSequence, next_dataSequence;
+wire    endPointReady;
+wire    getPacketEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [7:0]RXByteOld, next_RXByteOld;
+reg  [7:0]RXByteOldest, next_RXByteOldest;
+reg  [7:0]RXByte, next_RXByte;
+reg  [7:0]RXStreamStatus, next_RXStreamStatus;
+
+// BINARY ENCODED state machine: slvGetPkt
+// State codes definitions:
+`define PROC_PKT_CHK_PID 5'b00000
+`define PROC_PKT_HS 5'b00001
+`define PROC_PKT_DATA_W_D1 5'b00010
+`define PROC_PKT_DATA_CHK_D1 5'b00011
+`define PROC_PKT_DATA_W_D2 5'b00100
+`define PROC_PKT_DATA_FIN 5'b00101
+`define PROC_PKT_DATA_CHK_D2 5'b00110
+`define PROC_PKT_DATA_W_D3 5'b00111
+`define PROC_PKT_DATA_CHK_D3 5'b01000
+`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
+`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
+`define PROC_PKT_DATA_LOOP_W_D 5'b01011
+`define START_GP 5'b01100
+`define WAIT_PKT 5'b01101
+`define CHK_PKT_START 5'b01110
+`define WAIT_EN 5'b01111
+`define PKT_RDY 5'b10000
+`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
+`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
+
+reg [4:0] CurrState_slvGetPkt;
+reg [4:0] NextState_slvGetPkt;
+
+
+//--------------------------------------------------------------------
+// Machine: slvGetPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
+begin : slvGetPkt_NextState
+  NextState_slvGetPkt <= CurrState_slvGetPkt;
+  // Set default values for outputs and signals
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RXOverflow <= RXOverflow;
+  next_RXTimeOut <= RXTimeOut;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_SIERxTimeOutEn <= SIERxTimeOutEn;
+  next_RXByte <= RXByte;
+  next_RXStreamStatus <= RXStreamStatus;
+  next_RxPID <= RxPID;
+  next_RXPacketRdy <= RXPacketRdy;
+  next_RXByteOldest <= RXByteOldest;
+  next_RXByteOld <= RXByteOld;
+  next_RXFifoWEn <= RXFifoWEn;
+  next_RXFifoData <= RXFifoData;
+  case (CurrState_slvGetPkt)
+    `START_GP:
+      NextState_slvGetPkt <= `WAIT_EN;
+    `WAIT_PKT:
+    begin
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RXOverflow <= 1'b0;
+      next_RXTimeOut <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b1;
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `CHK_PKT_START;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+      else if (SIERxTimeOut == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    end
+    `CHK_PKT_START:
+      if (RXStreamStatus == `RX_PACKET_START)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
+        next_RxPID <= RXByte[3:0];
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXTimeOut <= 1'b1;
+      end
+    `WAIT_EN:
+    begin
+      next_RXPacketRdy <= 1'b0;
+      next_SIERxTimeOutEn <= 1'b0;
+      if (getPacketEn == 1'b1)	
+        NextState_slvGetPkt <= `WAIT_PKT;
+    end
+    `PKT_RDY:
+    begin
+      next_RXPacketRdy <= 1'b1;
+      NextState_slvGetPkt <= `WAIT_EN;
+    end
+    `PROC_PKT_CHK_PID:
+      if (RXByte[1:0] == `HANDSHAKE)	
+        NextState_slvGetPkt <= `PROC_PKT_HS;
+      else if (RXByte[1:0] == `DATA)	
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
+      else
+        NextState_slvGetPkt <= `PKT_RDY;
+    `PROC_PKT_HS:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PKT_RDY;
+        next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
+        next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
+      end
+    `PROC_PKT_DATA_W_D1:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    `PROC_PKT_DATA_CHK_D1:
+      if (RXStreamStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
+        next_RXByteOldest <= RXByte;
+      end
+      else
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+    `PROC_PKT_DATA_W_D2:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    `PROC_PKT_DATA_FIN:
+    begin
+      next_CRCError <= RXByte[`CRC_ERROR_BIT];
+      next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
+      next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
+      NextState_slvGetPkt <= `PKT_RDY;
+    end
+    `PROC_PKT_DATA_CHK_D2:
+      if (RXStreamStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
+        next_RXByteOld <= RXByte;
+      end
+      else
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+    `PROC_PKT_DATA_W_D3:
+      if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
+        next_RXByte <= RXDataIn;
+        next_RXStreamStatus <= RXStreamStatusIn;
+      end
+    `PROC_PKT_DATA_CHK_D3:
+      if (RXStreamStatus == `RX_PACKET_STREAM)	
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+      else
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+    `PROC_PKT_DATA_LOOP_CHK_FIFO:
+      if (endPointReady == 1'b0)	
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
+      else if (RXFifoFull == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
+        next_RXOverflow <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+        next_RXFifoWEn <= 1'b1;
+        next_RXFifoData <= RXByteOldest;
+        next_RXByteOldest <= RXByteOld;
+        next_RXByteOld <= RXByte;
+      end
+    `PROC_PKT_DATA_LOOP_FIFO_FULL:
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+    `PROC_PKT_DATA_LOOP_W_D:
+    begin
+      next_RXFifoWEn <= 1'b0;
+      if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
+        next_RXByte <= RXDataIn;
+      end
+      else if (RXDataValid == 1'b1)	
+      begin
+        NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
+        next_RXByte <= RXDataIn;
+      end
+    end
+    `PROC_PKT_DATA_LOOP_DELAY:
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
+    `PROC_PKT_DATA_LOOP_EP_N_RDY:    // Discard data
+      NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_CurrentState
+  if (rst)	
+    CurrState_slvGetPkt <= `START_GP;
+  else
+    CurrState_slvGetPkt <= NextState_slvGetPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvGetPkt_RegOutput
+  if (rst)	
+  begin
+    RXByteOld <= 8'h00;
+    RXByteOldest <= 8'h00;
+    RXByte <= 8'h00;
+    RXStreamStatus <= 8'h00;
+    RXPacketRdy <= 1'b0;
+    RXFifoWEn <= 1'b0;
+    RXFifoData <= 8'h00;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RXOverflow <= 1'b0;
+    RXTimeOut <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    SIERxTimeOutEn <= 1'b0;
+    RxPID <= 4'h0;
+  end
+  else 
+  begin
+    RXByteOld <= next_RXByteOld;
+    RXByteOldest <= next_RXByteOldest;
+    RXByte <= next_RXByte;
+    RXStreamStatus <= next_RXStreamStatus;
+    RXPacketRdy <= next_RXPacketRdy;
+    RXFifoWEn <= next_RXFifoWEn;
+    RXFifoData <= next_RXFifoData;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RXOverflow <= next_RXOverflow;
+    RXTimeOut <= next_RXTimeOut;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    SIERxTimeOutEn <= next_SIERxTimeOutEn;
+    RxPID <= next_RxPID;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC16.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC16.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC16.v	(revision 264)
@@ -0,0 +1,105 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC16.v                                                ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module updateCRC16 (rstCRC, CRCResult, CRCEn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [15:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [15:0] CRCResult;
+reg    ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 16'hffff;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0)
+    begin
+      if (CRCEn == 1'b1) begin
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        ready <= 1'b0;
+    end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[15:1]} ^ 16'ha001;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[15:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == 4'h7)
+      begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/timescale.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/timescale.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/timescale.v	(revision 264)
@@ -0,0 +1,5 @@
+//////////////////////////////////////////////////////////////////////
+// timescale.v                                              
+//////////////////////////////////////////////////////////////////////
+`timescale 1ns / 1ps
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice.v	(revision 264)
@@ -0,0 +1,231 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbDevice.v                                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Top level module for usbDevice
+//// Instantiates a usbSlave, and controllers for EP0 and EP1
+//// If you wish to implement another type of HID, then you will
+//// need to modify usbROM.v, and EP1Mouse.v
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+
+module usbDevice (
+  clk,
+  rst,
+  usbSlaveVP_in,
+  usbSlaveVM_in,
+  usbSlaveVP_out,
+  usbSlaveVM_out,
+  usbSlaveOE_n,
+  usbDPlusPullup,
+  vBusDetect
+);
+
+input clk;
+input rst;
+input usbSlaveVP_in;
+input usbSlaveVM_in;
+output usbSlaveVP_out;
+output usbSlaveVM_out;
+output usbSlaveOE_n;
+output usbDPlusPullup;
+input vBusDetect;
+
+//local wires and regs
+wire [7:0] wb_addr0;
+wire wb_stb0;
+wire wb_we0;
+wire wbBusReq0;
+wire wbBusGnt0;
+wire [7:0] wb_addr1;
+wire [7:0] wb_data_o1;
+wire wb_stb1;
+wire wb_we1;
+wire wbBusReq1;
+wire wbBusGnt1;
+wire [7:0] wb_addr2;
+wire [7:0] wb_data_o2;
+wire wb_stb2;
+wire wb_we2;
+wire wbBusReq2;
+wire wbBusGnt2;
+wire [7:0] wb_adr;
+wire [7:0] wb_dat_to_usb;
+wire [7:0] wb_dat_from_usb;
+wire wb_we;
+wire wb_stb;
+wire wb_ack;
+reg [1:0] resetReg;
+wire initComplete;
+wire usbRstDet;
+wire [7:0] memAddr;
+wire [7:0] memData;
+wire USBWireCtrlOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+
+
+//Parameters declaration: 
+defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
+defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
+defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
+usbSlave usbSlaveInst (
+  .clk_i(clk),
+  .rst_i(rst),
+  .address_i(wb_adr),
+  .data_i(wb_dat_to_usb),
+  .data_o(wb_dat_from_usb),
+  .we_i(wb_we),
+  .strobe_i(wb_stb),
+  .ack_o(wb_ack),
+  .usbClk(clk),
+  .slaveSOFRxedIntOut(),
+  .slaveResetEventIntOut(),
+  .slaveResumeIntOut(),
+  .slaveTransDoneIntOut(),
+  .slaveNAKSentIntOut(),
+  .slaveVBusDetIntOut(),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataInTick(),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataOutTick(),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .USBFullSpeed(),
+  .USBDPlusPullup(usbDPlusPullup),
+  .USBDMinusPullup(),
+  .vBusDetect(vBusDetect)
+);
+
+assign USBWireDataIn = {usbSlaveVP_in, usbSlaveVM_in};
+assign {usbSlaveVP_out, usbSlaveVM_out} = USBWireDataOut;
+assign usbSlaveOE_n = ~USBWireCtrlOut;
+
+checkLineState u_checkLineState (
+  .clk(clk),
+  .rst(rst),
+  .initComplete(initComplete),
+  .usbRstDet(usbRstDet),
+  .wb_ack(wb_ack),
+  .wb_addr(wb_addr0),
+  .wb_data_i(wb_dat_from_usb),
+  .wb_stb(wb_stb0),
+  .wb_we(wb_we0),
+  .wbBusGnt(wbBusGnt0),
+  .wbBusReq(wbBusReq0)
+);
+
+
+EP0 u_EP0 (
+  .clk(clk), 
+  .rst(rst | usbRstDet),
+  .initComplete(initComplete),
+  .wb_ack(wb_ack),
+  .wb_addr(wb_addr1),
+  .wb_data_i(wb_dat_from_usb),
+  .wb_data_o(wb_data_o1),
+  .wb_stb(wb_stb1),
+  .wb_we(wb_we1),
+  .wbBusGnt(wbBusGnt1),
+  .wbBusReq(wbBusReq1),
+  .memAddr(memAddr),
+  .memData(memData),
+  .memRdEn()
+);
+
+usbROM u_usbROM (
+  .clk(clk),
+  .addr(memAddr),
+  .data(memData)
+);
+
+
+EP1Mouse u_EP1Mouse (
+  .clk(clk),
+  .rst(rst | usbRstDet),
+  .initComplete(initComplete),
+  .wb_ack(wb_ack),
+  .wb_addr(wb_addr2),
+  .wb_data_i(wb_dat_from_usb),
+  .wb_data_o(wb_data_o2),
+  .wb_stb(wb_stb2),
+  .wb_we(wb_we2),
+  .wbBusGnt(wbBusGnt2),
+  .wbBusReq(wbBusReq2)
+);
+
+wishboneArb u_wishboneArb (
+  .clk(clk),
+  .rst(rst),
+
+  .addr0_i(wb_addr0),
+  .data0_i(8'h00),
+  .stb0_i(wb_stb0),
+  .we0_i(wb_we0),
+  .req0(wbBusReq0),
+  .gnt0(wbBusGnt0),
+
+  .addr1_i(wb_addr1),
+  .data1_i(wb_data_o1),
+  .stb1_i(wb_stb1),
+  .we1_i(wb_we1),
+  .req1(wbBusReq1),
+  .gnt1(wbBusGnt1),
+
+  .addr2_i(wb_addr2),
+  .data2_i(wb_data_o2),
+  .stb2_i(wb_stb2),
+  .we2_i(wb_we2),
+  .req2(wbBusReq2),
+  .gnt2(wbBusGnt2),
+
+
+  .addr_o(wb_adr),
+  .data_o(wb_dat_to_usb),
+  .stb_o(wb_stb),
+  .we_o(wb_we)
+);
+
+
+endmodule
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceActelTop.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceActelTop.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceActelTop.v	(revision 264)
@@ -0,0 +1,88 @@
+
+module usbDeviceActelTop (
+
+  //
+  // Global signals
+  //
+  clk,
+  rst_n,
+
+  // eval board features
+  ledOut,
+
+  //
+  // USB
+  //
+  usbSlaveVP,
+  usbSlaveVM,
+  usbSlaveOE_n,
+  usbDPlusPullup
+
+);
+
+  //
+  // Global signals
+  //
+  input	clk;
+  input rst_n;
+
+  output [9:0] ledOut;
+
+  //
+  // USB
+  //
+  inout usbSlaveVP;
+  inout usbSlaveVM;
+  output usbSlaveOE_n;
+  output usbDPlusPullup;
+
+//local wires and regs
+reg [1:0] rstReg;
+wire rst;
+
+//generate sync reset
+always @(posedge clk) begin
+  rstReg[1:0] <= {rstReg[0], ~rst_n};
+end
+assign rst = rstReg[1];
+
+
+usbDevice u_usbDevice (
+  .clk(clk),
+  .rst(rst),
+  .usbSlaveVP_in(usbSlaveVP_in),
+  .usbSlaveVM_in(usbSlaveVM_in),
+  .usbSlaveVP_out(usbSlaveVP_out),
+  .usbSlaveVM_out(usbSlaveVM_out),
+  .usbSlaveOE_n(usbSlaveOE_n),
+  .usbDPlusPullup(usbDPlusPullup),
+  .vBusDetect(1'b1)
+);
+
+
+assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
+assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
+
+
+// comfort lights
+reg [9:0] ledCntReg;
+reg [21:0] cnt;
+
+assign ledOut = ledCntReg;
+
+
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+    ledCntReg <= 10'b00_0000_0000;
+    cnt <= {22{1'b0}};
+  end
+  else begin
+    cnt <= cnt + 1'b1;
+    if (cnt == {22{1'b0}})
+      ledCntReg <= ledCntReg + 1'b1;
+  end
+end
+
+endmodule
+
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice_define.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice_define.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice_define.v	(revision 264)
@@ -0,0 +1,48 @@
+// ----------------------------- usbDevice_define ---------------------------
+
+`define ZERO_ZERO_STAT_INDEX 8'h6c
+`define ONE_ZERO_STAT_INDEX 8'h6e
+`define VENDOR_DATA_STAT_INDEX 8'h70
+`define DEV_DESC_INDEX 8'h00
+`define DEV_DESC_SIZE 8'h12
+//config descriptor is bundled with interface desc, HID desc, and EP1 desc
+`define CFG_DESC_INDEX 8'h12
+`define CFG_DESC_SIZE 8'h22
+`define REP_DESC_INDEX 8'h3a
+`define REP_DESC_SIZE 8'h32
+`define LANGID_DESC_INDEX 8'h80
+`define LANGID_DESC_SIZE 8'h04
+`define STRING1_DESC_INDEX 8'h90
+`define STRING1_DESC_SIZE 8'd26
+`define STRING2_DESC_INDEX 8'hb0
+`define STRING2_DESC_SIZE 8'd20
+`define STRING3_DESC_INDEX 8'hd0
+`define STRING3_DESC_SIZE 8'd30
+
+`define DEV_DESC 8'h01
+`define CFG_DESC 8'h02
+`define REP_DESC 8'h22
+`define STRING_DESC 8'h03
+
+//delays at 48MHz
+`ifdef SIM_COMPILE
+`define ONE_MSEC_DEL 16'h0300
+`else
+`define ONE_MSEC_DEL 16'hbb80
+`endif
+`define ONE_USEC_DEL 8'h30
+
+`define GET_STATUS 8'h00
+`define CLEAR_FEATURE 8'h01
+`define SET_FEATURE 8'h03
+`define SET_ADDRESS 8'h05
+`define GET_DESCRIPTOR 8'h06
+`define SET_DESCRIPTOR 8'h07
+`define GET_CONFIG 8'h08
+`define SET_CONFIG 8'h09
+`define GET_INTERFACE 8'h0a
+`define SET_INTERFACE 8'h0b
+`define SYNCH_FRAME 8'h0c
+
+`define MAX_RESP_SIZE 8'h40
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbROM.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbROM.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbROM.v	(revision 264)
@@ -0,0 +1,254 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbROM.v                                                     ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// if you modify this file, be sure to modify usbDevice_define.v
+//// Using RAM rather than logic resources might be a more efficient implememtation
+//// but this has the advantage of working with FPGAs that do not provide a 
+//// mechanism for initialising RAM, eg Actel IGLOO
+//// Quartus 7.2 will infer this code as BLOCK RAM, and provide initialisation - nice
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "usbDevice_define.v"
+
+
+module usbROM (
+  clk,
+  addr,
+  data
+);
+input clk;
+input [7:0] addr;
+output [7:0] data;
+reg [7:0] data;
+
+always @(posedge clk) begin
+  case (addr)
+// ====================================
+// =====    DEVICE Descriptor     =====
+// ====================================
+
+    8'h00: data <= 8'h12;  //BYTE bLength
+    8'h01: data <= 8'h01;  //BYTE bDescriptorType
+    8'h02: data <= 8'h10;  //WORD (Lo) bcdUSB version supported
+    8'h03: data <= 8'h01;  //WORD (Hi) bcdUSB version supported
+    8'h04: data <= 8'h00;  //BYTE bDeviceClass
+    8'h05: data <= 8'h00;  //BYTE bDeviceSubClass
+    8'h06: data <= 8'h00;  //BYTE bDeviceProtocol
+	 8'h07: data <= `MAX_RESP_SIZE;  //BYTE bMaxPacketSize 
+    8'h08: data <= 8'hC7;  //WORD (Lo) idVendor
+    8'h09: data <= 8'h05;  //WORD (Hi) idVendor
+    8'h0a: data <= 8'h13;  //WORD (Lo) idProduct; For Philips Hub mouse
+    8'h0b: data <= 8'h01;  //WORD (Hi) idProduct; For Philips Hub mouse
+    8'h0c: data <= 8'h01;  //WORD (Lo) bcdDevice
+    8'h0d: data <= 8'h00;  //WORD (Hi) bcdDevice
+    8'h0e: data <= 8'h01;  //BYTE iManufacturer
+    8'h0f: data <= 8'h02;  //BYTE iProduct
+    8'h10: data <= 8'h03;  //BYTE iSerialNumber
+    8'h11: data <= 8'h01;  //BYTE bNumConfigurations
+
+ 
+// ====================================
+// ===== Configuration Descriptor =====
+// ====================================
+    8'h12: data <= 8'h09;  //BYTE bLength (Configuration descriptor)
+    8'h13: data <= 8'h02;  //BYTE bDescriptorType //Assigned by USB
+	 8'h14: data <= 8'd34;  //WORD (Lo) wTotalLength
+    8'h15: data <= 8'h00;  //WORD (Hi) wTotalLength
+    8'h16: data <= 8'h01;  //BYTE bNumInterfaces
+    8'h17: data <= 8'h01;  //BYTE bConfigurationValue
+    8'h18: data <= 8'h00;  //BYTE iConfiguration
+    8'h19: data <= 8'ha0;  //BYTE bmAttributes, Bus powered and remote wakeup
+    8'h1a: data <= 8'h32;  //BYTE MaxPower, 100mA
+ 
+// ====================================
+// =====   Interface Descriptor   =====
+// ====================================
+    8'h1b: data <= 8'h09;  //BYTE bLength (Interface descriptor)
+    8'h1c: data <= 8'h04;  //BYTE bDescriptionType; assigned by USB
+    8'h1d: data <= 8'h00;  //BYTE bInterfaceNumber
+    8'h1e: data <= 8'h00;  //BYTE bAlternateSetting
+    8'h1f: data <= 8'h01;  //BYTE bNumEndpoints; uses 1 endpoints
+    8'h20: data <= 8'h03;  //BYTE bInterfaceClass; HID Class - 0x03
+    8'h21: data <= 8'h01;  //BYTE bInterfaceSubClass
+    8'h22: data <= 8'h02;  //BYTE bInterfaceProtocol
+    8'h23: data <= 8'h00;  //BYTE iInterface
+ 
+// ====================================
+// =====   HID Descriptor   =====
+// ====================================
+    8'h24: data <= 8'h09;  //BYTE bLength (HID Descriptor)
+    8'h25: data <= 8'h21;  //BYTE bDescriptorType
+    8'h26: data <= 8'h10;  //WORD (Lo) bcdHID
+    8'h27: data <= 8'h01;  //WORD (Hi) bcdHID
+    8'h28: data <= 8'h00;  //BYTE bCountryCode
+    8'h29: data <= 8'h01;  //BYTE bNumDescriptors
+    8'h2a: data <= 8'h22;  //BYTE bReportDescriptorType
+    8'h2b: data <= 8'h32;  //WORD (Lo) wItemLength
+    8'h2c: data <= 8'h00;  //WORD (Hi) wItemLength
+
+// ====================================
+// =====   Endpoint 1 Descriptor  =====
+// ====================================
+    8'h2d: data <= 8'h07;  //BYTE bLength (Endpoint Descriptor)
+    8'h2e: data <= 8'h05;  //BYTE bDescriptorType; assigned by USB
+    8'h2f: data <= 8'h81;  //BYTE bEndpointAddress; IN endpoint; endpoint 1
+    8'h30: data <= 8'h03;  //BYTE bmAttributes; Interrupt endpoint
+    8'h31: data <= 8'h10;  //WORD (Lo) wMaxPacketSize
+    8'h32: data <= 8'h00;  //WORD (Hi) wMaxPacketSize
+    8'h33: data <= 8'hFF;  //BYTE bInterval
+
+ 
+// ====================================
+// =====   Report Descriptor  =====
+// ====================================
+
+    8'h3a: data <= 8'h05;     8'h3b: data <= 8'h01;    // USAGE_PAGE (Generic Desktop)
+    8'h3c: data <= 8'h09;     8'h3d: data <= 8'h02;    // USAGE (Mouse)
+    8'h3e: data <= 8'ha1;     8'h3f: data <= 8'h01;    // COLLECTION (Application)
+    8'h40: data <= 8'h09;     8'h41: data <= 8'h01;    //   USAGE (Pointer)
+    8'h42: data <= 8'ha1;     8'h43: data <= 8'h00;    //   COLLECTION (Physical)
+    8'h44: data <= 8'h05;     8'h45: data <= 8'h09;    //     USAGE_PAGE (Button)
+    8'h46: data <= 8'h19;     8'h47: data <= 8'h01;    //     USAGE_MINIMUM (Button 1)
+    8'h48: data <= 8'h29;     8'h49: data <= 8'h03;    //     USAGE_MAXIMUM (Button 3)
+    8'h4a: data <= 8'h15;     8'h4b: data <= 8'h00;    //     LOGICAL_MINIMUM (0)
+    8'h4c: data <= 8'h25;     8'h4d: data <= 8'h01;    //     LOGICAL_MAXIMUM (1)
+    8'h4e: data <= 8'h95;     8'h4f: data <= 8'h03;    //     REPORT_COUNT (3)
+    8'h50: data <= 8'h75;     8'h51: data <= 8'h01;    //     REPORT_SIZE (1)
+    8'h52: data <= 8'h81;     8'h53: data <= 8'h02;    //     INPUT (Data,Var,Abs)
+    8'h54: data <= 8'h95;     8'h55: data <= 8'h01;    //     REPORT_COUNT (1)
+    8'h56: data <= 8'h75;     8'h57: data <= 8'h05;    //     REPORT_SIZE (5)
+    8'h58: data <= 8'h81;     8'h59: data <= 8'h01;    //     INPUT (Cnst,Var,Rel)
+    8'h5a: data <= 8'h05;     8'h5b: data <= 8'h01;    //     USAGE_PAGE (Generic Desktop)
+    8'h5c: data <= 8'h09;     8'h5d: data <= 8'h30;    //     USAGE (X)
+    8'h5e: data <= 8'h09;     8'h5f: data <= 8'h31;    //     USAGE (Y)
+    8'h60: data <= 8'h15;     8'h61: data <= 8'h81;    //     LOGICAL_MINIMUM (-127)
+    8'h62: data <= 8'h25;     8'h63: data <= 8'h7f;    //     LOGICAL_MAXIMUM (127)
+    8'h64: data <= 8'h75;     8'h65: data <= 8'h08;    //     REPORT_SIZE (8)
+    8'h66: data <= 8'h95;     8'h67: data <= 8'h02;    //     REPORT_COUNT (2)
+    8'h68: data <= 8'h81;     8'h69: data <= 8'h06;    //     INPUT (Data,Var,Rel)
+    8'h6a: data <= 8'hc0;                              //END_COLLECTION
+    8'h6b: data <= 8'hc0;                              // END_COLLECTION
+
+// ZERO_ZERO
+    8'h6c: data <= 8'h00; 
+    8'h6d: data <= 8'h00; 
+// ONE_ZERO
+    8'h6e: data <= 8'h01; 
+    8'h6f: data <= 8'h00; 
+// Vendor data
+    8'h70: data <= 8'h00; 
+    8'h71: data <= 8'h00; 
+
+// =============================================
+// =====   Language ID Descriptor(String0) =====
+// =============================================
+    8'h80: data <= 8'h04;  // bLength
+    8'h81: data <= 8'h03;  // bDescriptorType = String Desc
+    8'h82: data <= 8'h09;  // wLangID (Lo) (Lang ID for English = 0x0409)
+    8'h83: data <= 8'h04;  // wLangID (Hi) (Lang ID for English = 0x0409)
+
+// ====================================
+// =====   string 1 Descriptor  =====
+// ====================================
+    8'h90: data <= 8'd26;  	// bLength
+    8'h91: data <= 8'h03;     // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'h92: data <= "B";  8'h93: data <= 8'h00;
+    8'h94: data <= "a";  8'h95: data <= 8'h00;
+    8'h96: data <= "s";  8'h97: data <= 8'h00;
+    8'h98: data <= "e";  8'h99: data <= 8'h00;
+    8'h9a: data <= "2";  8'h9b: data <= 8'h00;
+    8'h9c: data <= "D";  8'h9d: data <= 8'h00;
+    8'h9e: data <= "e";  8'h9f: data <= 8'h00;
+    8'ha0: data <= "s";  8'ha1: data <= 8'h00;
+    8'ha2: data <= "i";  8'ha3: data <= 8'h00;
+    8'ha4: data <= "g";  8'ha5: data <= 8'h00;
+    8'ha6: data <= "n";  8'ha7: data <= 8'h00;
+    8'ha8: data <= "s";  8'ha9: data <= 8'h00;
+
+
+
+// ====================================
+// =====   string 2 Descriptor  =====
+// ====================================
+	 8'hb0: data <= 8'd20;   // bLength
+    8'hb1: data <= 8'h03;   // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'hb2: data <= "B";  8'hb3: data <= 8'h00;
+    8'hb4: data <= "2";  8'hb5: data <= 8'h00;
+    8'hb6: data <= "D";  8'hb7: data <= 8'h00;
+    8'hb8: data <= " ";  8'hb9: data <= 8'h00;
+    8'hba: data <= "M";  8'hbb: data <= 8'h00;
+    8'hbc: data <= "o";  8'hbd: data <= 8'h00;
+    8'hbe: data <= "u";  8'hbf: data <= 8'h00;
+    8'hc0: data <= "s";  8'hc1: data <= 8'h00;
+    8'hc2: data <= "e";  8'hc3: data <= 8'h00;
+
+// ====================================
+// =====   string 3 Descriptor  =====
+// ====================================
+	 8'hd0: data <= 8'd30;   // bLength
+    8'hd1: data <= 8'h03;   // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'hd2: data <= "L";  8'hd3: data <= 8'h00;
+    8'hd4: data <= "i";  8'hd5: data <= 8'h00;
+    8'hd6: data <= "m";  8'hd7: data <= 8'h00;
+    8'hd8: data <= "i";  8'hd9: data <= 8'h00;
+    8'hda: data <= "t";  8'hdb: data <= 8'h00;
+    8'hdc: data <= "e";  8'hdd: data <= 8'h00;
+    8'hde: data <= "d";  8'hdf: data <= 8'h00;
+    8'he0: data <= "E";  8'he1: data <= 8'h00;
+    8'he2: data <= "d";  8'he3: data <= 8'h00;
+    8'he4: data <= "i";  8'he5: data <= 8'h00;
+    8'he6: data <= "t";  8'he7: data <= 8'h00;
+    8'he8: data <= "i";  8'he9: data <= 8'h00;
+    8'hea: data <= "o";  8'heb: data <= 8'h00;
+    8'hec: data <= "n";  8'hed: data <= 8'h00;
+
+
+
+    default: data <= 8'h00;
+  endcase
+end
+
+endmodule
+
+
+ 
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostControl_h.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostControl_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostControl_h.v	(revision 264)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostControl_h.v                                          
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostControl_h_vdefined
+`else
+`define usbHostControl_h_vdefined
+
+//HCRegIndices
+`define TX_CONTROL_REG 4'h0
+`define TX_TRANS_TYPE_REG 4'h1
+`define TX_LINE_CONTROL_REG 4'h2
+`define TX_SOF_ENABLE_REG 4'h3
+`define TX_ADDR_REG 4'h4
+`define TX_ENDP_REG 4'h5
+`define FRAME_NUM_MSB_REG 4'h6
+`define FRAME_NUM_LSB_REG 4'h7
+`define INTERRUPT_STATUS_REG 4'h8
+`define INTERRUPT_MASK_REG 4'h9
+`define RX_STATUS_REG 4'ha
+`define RX_PID_REG 4'hb
+`define RX_ADDR_REG 4'hc
+`define RX_ENDP_REG 4'hd
+`define RX_CONNECT_STATE_REG 4'he
+`define HOST_SOF_TIMER_MSB_REG 4'hf
+
+`define HCREG_BUFFER_LEN 4'hf
+`define HCREG_MASK 4'hf
+
+//TXControlRegIndices
+`define TRANS_REQ_BIT 0
+`define SOF_SYNC_BIT 1
+`define PREAMBLE_ENABLE_BIT 2
+`define ISO_ENABLE_BIT 3
+
+//interruptRegIndices
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define CONNECTION_EVENT_BIT 2
+`define SOF_SENT_BIT 3
+
+//TXTransactionTypes
+`define SETUP_TRANS 0
+`define IN_TRANS 1
+`define OUTDATA0_TRANS 2
+`define OUTDATA1_TRANS 3
+ 
+ //TXLineControlIndices
+`define TX_LINE_STATE_LSBIT 0
+`define TX_LINE_STATE_MSBIT 1
+`define DIRECT_CONTROL_BIT 2
+`define FULL_SPEED_LINE_POLARITY_BIT 3
+`define FULL_SPEED_LINE_RATE_BIT 4
+
+//TXSOFEnableIndices
+`define SOF_EN_BIT 0
+
+//SOFTimeConstants 
+//`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval   
+//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer 
+`define SOF_TX_TIME 16'hbb7d     //Correct SOF interval for 48MHz clock.
+//`define SOF_TX_MARGIN 2 
+`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
+       
+//Host RXStatusRegIndices 
+`define HC_CRC_ERROR_BIT 0
+`define HC_BIT_STUFF_ERROR_BIT 1
+`define HC_RX_OVERFLOW_BIT 2
+`define HC_RX_TIME_OUT_BIT 3
+`define HC_NAK_RXED_BIT 4
+`define HC_STALL_RXED_BIT 5
+`define HC_ACK_RXED_BIT 6
+`define HC_DATA_SEQUENCE_BIT 7
+
+`endif //usbHostControl_h_vdefined 
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbROM_logitech_mouse.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbROM_logitech_mouse.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbROM_logitech_mouse.v	(revision 264)
@@ -0,0 +1,213 @@
+// ----------------------------- usbROM ---------------------------
+// if you modify this file, be sure to modify usbDevice_define.v
+// Using RAM rather than logic resources might be a more efficient implememtation
+// but this has the advantage of working with FPGAs that do not provide a 
+// mechanism for initialising RAM, eg Actel IGLOO
+// Quartus 7.2 will infer this code as BLOCK RAM, and provide initialisation - nice
+`include "usbDevice_define.v"
+
+
+module usbROM (
+  clk,
+  addr,
+  data
+);
+input clk;
+input [7:0] addr;
+output [7:0] data;
+reg [7:0] data;
+
+always @(posedge clk) begin
+  case (addr)
+// ====================================
+// =====    DEVICE Descriptor     =====
+// ====================================
+
+    8'h00: data <= 8'h12;  //BYTE bLength
+    8'h01: data <= 8'h01;  //BYTE bDescriptorType
+    8'h02: data <= 8'h10;  //WORD (Lo) bcdUSB version supported
+    8'h03: data <= 8'h01;  //WORD (Hi) bcdUSB version supported
+    8'h04: data <= 8'h00;  //BYTE bDeviceClass
+    8'h05: data <= 8'h00;  //BYTE bDeviceSubClass
+    8'h06: data <= 8'h00;  //BYTE bDeviceProtocol
+	 8'h07: data <= `MAX_RESP_SIZE;  //BYTE bMaxPacketSize 
+    8'h08: data <= 8'h6d;  //WORD (Lo) idVendor
+    8'h09: data <= 8'h04;  //WORD (Hi) idVendor
+    8'h0a: data <= 8'h3d;  //WORD (Lo) idProduct; For Logitech mouse
+    8'h0b: data <= 8'hc0;  //WORD (Hi) idProduct; For Logitech Hub mouse
+    8'h0c: data <= 8'h00;  //WORD (Lo) bcdDevice
+    8'h0d: data <= 8'h20;  //WORD (Hi) bcdDevice
+    8'h0e: data <= 8'h01;  //BYTE iManufacturer
+    8'h0f: data <= 8'h02;  //BYTE iProduct
+    8'h10: data <= 8'h00;  //BYTE iSerialNumber
+    8'h11: data <= 8'h01;  //BYTE bNumConfigurations
+
+ 
+// ====================================
+// ===== Configuration Descriptor =====
+// ====================================
+    8'h12: data <= 8'h09;  //BYTE bLength (Configuration descriptor)
+    8'h13: data <= 8'h02;  //BYTE bDescriptorType //Assigned by USB
+	 8'h14: data <= 8'h22;  //WORD (Lo) wTotalLength
+    8'h15: data <= 8'h00;  //WORD (Hi) wTotalLength
+    8'h16: data <= 8'h01;  //BYTE bNumInterfaces
+    8'h17: data <= 8'h01;  //BYTE bConfigurationValue
+    8'h18: data <= 8'h00;  //BYTE iConfiguration
+    8'h19: data <= 8'ha0;  //BYTE bmAttributes, Bus powered and remote wakeup
+    8'h1a: data <= 8'h31;  //BYTE MaxPower, 98mA
+ 
+// ====================================
+// =====   Interface Descriptor   =====
+// ====================================
+    8'h1b: data <= 8'h09;  //BYTE bLength (Interface descriptor)
+    8'h1c: data <= 8'h04;  //BYTE bDescriptionType; assigned by USB
+    8'h1d: data <= 8'h00;  //BYTE bInterfaceNumber
+    8'h1e: data <= 8'h00;  //BYTE bAlternateSetting
+    8'h1f: data <= 8'h01;  //BYTE bNumEndpoints; uses 1 endpoints
+    8'h20: data <= 8'h03;  //BYTE bInterfaceClass; HID Class - 0x03
+    8'h21: data <= 8'h01;  //BYTE bInterfaceSubClass
+    8'h22: data <= 8'h02;  //BYTE bInterfaceProtocol
+    8'h23: data <= 8'h00;  //BYTE iInterface
+ 
+// ====================================
+// =====   HID Descriptor   =====
+// ====================================
+    8'h24: data <= 8'h09;  //BYTE bLength (HID Descriptor)
+    8'h25: data <= 8'h21;  //BYTE bDescriptorType
+    8'h26: data <= 8'h10;  //WORD (Lo) bcdHID
+    8'h27: data <= 8'h01;  //WORD (Hi) bcdHID
+    8'h28: data <= 8'h00;  //BYTE bCountryCode
+    8'h29: data <= 8'h01;  //BYTE bNumDescriptors
+    8'h2a: data <= 8'h22;  //BYTE bReportDescriptorType
+    8'h2b: data <= 8'h32;  //WORD (Lo) wItemLength
+    8'h2c: data <= 8'h00;  //WORD (Hi) wItemLength
+
+// ====================================
+// =====   Endpoint 1 Descriptor  =====
+// ====================================
+    8'h2d: data <= 8'h07;  //BYTE bLength (Endpoint Descriptor)
+    8'h2e: data <= 8'h05;  //BYTE bDescriptorType; assigned by USB
+    8'h2f: data <= 8'h81;  //BYTE bEndpointAddress; IN endpoint; endpoint 1
+    8'h30: data <= 8'h03;  //BYTE bmAttributes; Interrupt endpoint
+    8'h31: data <= 8'h04;  //WORD (Lo) wMaxPacketSize
+    8'h32: data <= 8'h00;  //WORD (Hi) wMaxPacketSize
+    8'h33: data <= 8'h0a;  //BYTE bInterval
+
+ 
+// ====================================
+// =====   Report Descriptor  =====
+// ====================================
+
+    8'h3a: data <= 8'h05;     8'h3b: data <= 8'h01;    // USAGE_PAGE (Generic Desktop)
+    8'h3c: data <= 8'h09;     8'h3d: data <= 8'h02;    // USAGE (Mouse)
+    8'h3e: data <= 8'ha1;     8'h3f: data <= 8'h01;    // COLLECTION (Application)
+    8'h40: data <= 8'h09;     8'h41: data <= 8'h01;    //   USAGE (Pointer)
+    8'h42: data <= 8'ha1;     8'h43: data <= 8'h00;    //   COLLECTION (Physical)
+    8'h44: data <= 8'h05;     8'h45: data <= 8'h09;    //     USAGE_PAGE (Button)
+    8'h46: data <= 8'h19;     8'h47: data <= 8'h01;    //     USAGE_MINIMUM (Button 1)
+    8'h48: data <= 8'h29;     8'h49: data <= 8'h03;    //     USAGE_MAXIMUM (Button 3)
+    8'h4a: data <= 8'h15;     8'h4b: data <= 8'h00;    //     LOGICAL_MINIMUM (0)
+    8'h4c: data <= 8'h25;     8'h4d: data <= 8'h01;    //     LOGICAL_MAXIMUM (1)
+    8'h4e: data <= 8'h95;     8'h4f: data <= 8'h03;    //     REPORT_COUNT (3)
+    8'h50: data <= 8'h75;     8'h51: data <= 8'h01;    //     REPORT_SIZE (1)
+    8'h52: data <= 8'h81;     8'h53: data <= 8'h02;    //     INPUT (Data,Var,Abs)
+    8'h54: data <= 8'h95;     8'h55: data <= 8'h05;    //     REPORT_COUNT (5)
+    8'h56: data <= 8'h81;     8'h57: data <= 8'h03;    //     INPUT (Cnst,Var,Rel)
+    8'h58: data <= 8'h05;     8'h59: data <= 8'h01;    //     USAGE_PAGE (Generic Desktop)
+    8'h5a: data <= 8'h09;     8'h5b: data <= 8'h30;    //     USAGE (X)
+    8'h5c: data <= 8'h09;     8'h5d: data <= 8'h31;    //     USAGE (Y)
+    8'h5e: data <= 8'h09;     8'h5f: data <= 8'h38;    //     USAGE ?
+    8'h60: data <= 8'h15;     8'h61: data <= 8'h81;    //     LOGICAL_MINIMUM (-127)
+    8'h62: data <= 8'h25;     8'h63: data <= 8'h7f;    //     LOGICAL_MAXIMUM (127)
+    8'h64: data <= 8'h75;     8'h65: data <= 8'h08;    //     REPORT_SIZE (8)
+    8'h66: data <= 8'h95;     8'h67: data <= 8'h03;    //     REPORT_COUNT (3)
+    8'h68: data <= 8'h81;     8'h69: data <= 8'h06;    //     INPUT (Data,Var,Rel)
+    8'h6a: data <= 8'hc0;                              //END_COLLECTION
+    8'h6b: data <= 8'hc0;                              // END_COLLECTION
+
+// ZERO_ZERO
+    8'h6c: data <= 8'h00; 
+    8'h6d: data <= 8'h00; 
+// ONE_ZERO
+    8'h6e: data <= 8'h01; 
+    8'h6f: data <= 8'h00; 
+// Vendor data
+    8'h70: data <= 8'h00; 
+    8'h71: data <= 8'h00; 
+
+// =============================================
+// =====   Language ID Descriptor(String0) =====
+// =============================================
+    8'h80: data <= 8'h04;  // bLength
+    8'h81: data <= 8'h03;  // bDescriptorType = String Desc
+    8'h82: data <= 8'h09;  // wLangID (Lo) (Lang ID for English = 0x0409)
+    8'h83: data <= 8'h04;  // wLangID (Hi) (Lang ID for English = 0x0409)
+
+// ====================================
+// =====   string 1 Descriptor  =====
+// ====================================
+    8'h90: data <= 8'd26;  	// bLength
+    8'h91: data <= 8'h03;     // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'h92: data <= "B";  8'h93: data <= 8'h00;
+    8'h94: data <= "a";  8'h95: data <= 8'h00;
+    8'h96: data <= "s";  8'h97: data <= 8'h00;
+    8'h98: data <= "e";  8'h99: data <= 8'h00;
+    8'h9a: data <= "2";  8'h9b: data <= 8'h00;
+    8'h9c: data <= "D";  8'h9d: data <= 8'h00;
+    8'h9e: data <= "e";  8'h9f: data <= 8'h00;
+    8'ha0: data <= "s";  8'ha1: data <= 8'h00;
+    8'ha2: data <= "i";  8'ha3: data <= 8'h00;
+    8'ha4: data <= "g";  8'ha5: data <= 8'h00;
+    8'ha6: data <= "n";  8'ha7: data <= 8'h00;
+    8'ha8: data <= "s";  8'ha9: data <= 8'h00;
+
+
+
+// ====================================
+// =====   string 2 Descriptor  =====
+// ====================================
+	 8'hb0: data <= 8'd20;   // bLength
+    8'hb1: data <= 8'h03;   // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'hb2: data <= "B";  8'hb3: data <= 8'h00;
+    8'hb4: data <= "2";  8'hb5: data <= 8'h00;
+    8'hb6: data <= "D";  8'hb7: data <= 8'h00;
+    8'hb8: data <= " ";  8'hb9: data <= 8'h00;
+    8'hba: data <= "M";  8'hbb: data <= 8'h00;
+    8'hbc: data <= "o";  8'hbd: data <= 8'h00;
+    8'hbe: data <= "u";  8'hbf: data <= 8'h00;
+    8'hc0: data <= "s";  8'hc1: data <= 8'h00;
+    8'hc2: data <= "e";  8'hc3: data <= 8'h00;
+
+// ====================================
+// =====   string 3 Descriptor  =====
+// ====================================
+	 8'hd0: data <= 8'd30;   // bLength
+    8'hd1: data <= 8'h03;   // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'hd2: data <= "L";  8'hd3: data <= 8'h00;
+    8'hd4: data <= "i";  8'hd5: data <= 8'h00;
+    8'hd6: data <= "m";  8'hd7: data <= 8'h00;
+    8'hd8: data <= "i";  8'hd9: data <= 8'h00;
+    8'hda: data <= "t";  8'hdb: data <= 8'h00;
+    8'hdc: data <= "e";  8'hdd: data <= 8'h00;
+    8'hde: data <= "d";  8'hdf: data <= 8'h00;
+    8'he0: data <= "E";  8'he1: data <= 8'h00;
+    8'he2: data <= "d";  8'he3: data <= 8'h00;
+    8'he4: data <= "i";  8'he5: data <= 8'h00;
+    8'he6: data <= "t";  8'he7: data <= 8'h00;
+    8'he8: data <= "i";  8'he9: data <= 8'h00;
+    8'hea: data <= "o";  8'heb: data <= 8'h00;
+    8'hec: data <= "n";  8'hed: data <= 8'h00;
+
+
+
+    default: data <= 8'h00;
+  endcase
+end
+
+endmodule
+
+
+ 
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlave.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlave.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlave.v	(revision 264)
@@ -0,0 +1,474 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlave.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////   Top level module
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbSlave(
+  clk_i,
+  rst_i,
+  address_i, 
+  data_i, 
+  data_o, 
+  we_i, 
+  strobe_i,
+  ack_o,
+  usbClk,
+  slaveVBusDetIntOut,
+  slaveNAKSentIntOut,
+  slaveSOFRxedIntOut, 
+  slaveResetEventIntOut, 
+  slaveResumeIntOut, 
+  slaveTransDoneIntOut,
+  USBWireDataIn,
+  USBWireDataInTick,
+  USBWireDataOut,
+  USBWireDataOutTick,
+  USBWireCtrlOut,
+  USBFullSpeed,
+  USBDPlusPullup,
+  USBDMinusPullup,
+  vBusDetect
+   );
+  parameter EP0_FIFO_DEPTH = 64; 
+  parameter EP0_FIFO_ADDR_WIDTH = 6;   
+  parameter EP1_FIFO_DEPTH = 64; 
+  parameter EP1_FIFO_ADDR_WIDTH = 6;   
+  parameter EP2_FIFO_DEPTH = 64; 
+  parameter EP2_FIFO_ADDR_WIDTH = 6;   
+  parameter EP3_FIFO_DEPTH = 64; 
+  parameter EP3_FIFO_ADDR_WIDTH = 6;   
+
+input clk_i;               //Wishbone bus clock. Maximum 5*usbClk=240MHz
+input rst_i;               //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
+input [7:0] address_i;     //Wishbone bus address in
+input [7:0] data_i;        //Wishbone bus data in
+output [7:0] data_o;       //Wishbone bus data out
+input we_i;                //Wishbone bus write enable in
+input strobe_i;            //Wishbone bus strobe in
+output ack_o;              //Wishbone bus acknowledge out
+input usbClk;              //usb clock. 48Mhz +/-0.25%
+output slaveSOFRxedIntOut; 
+output slaveResetEventIntOut; 
+output slaveResumeIntOut; 
+output slaveTransDoneIntOut;
+output slaveNAKSentIntOut;
+output slaveVBusDetIntOut;
+input [1:0] USBWireDataIn;
+output [1:0] USBWireDataOut;
+output USBWireDataOutTick;
+output USBWireDataInTick;
+output USBWireCtrlOut;
+output USBFullSpeed;
+output USBDPlusPullup;
+output USBDMinusPullup;
+input vBusDetect;
+
+wire clk_i;
+wire rst_i;
+wire [7:0] address_i; 
+wire [7:0] data_i; 
+wire [7:0] data_o; 
+wire we_i; 
+wire strobe_i;
+wire ack_o;
+wire usbClk;
+wire slaveSOFRxedIntOut; 
+wire slaveResetEventIntOut; 
+wire slaveResumeIntOut; 
+wire slaveTransDoneIntOut;
+wire slaveNAKSentIntOut;
+wire slaveVBusDetIntOut;
+wire [1:0] USBWireDataIn;
+wire [1:0] USBWireDataOut;
+wire USBWireDataOutTick;
+wire USBWireDataInTick;
+wire USBWireCtrlOut;
+wire USBFullSpeed;
+wire USBDPlusPullup;
+wire USBDMinusPullup;
+wire vBusDetect;
+
+//internal wiring
+wire slaveControlSel;
+wire hostSlaveMuxSel;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromHostSlaveMux;
+wire [7:0] RxCtrlOut; 
+wire [7:0] RxDataFromSIE; 
+wire RxDataOutWEn;
+wire fullSpeedBitRateFromSlave; 
+wire fullSpeedPolarityFromSlave;
+wire SIEPortWEnFromSlave; 
+wire SIEPortTxRdy;
+wire [7:0] SIEPortDataInFromSlave; 
+wire [7:0] SIEPortCtrlInFromSlave;
+wire [1:0] connectState; 
+wire resumeDetected;
+wire [7:0] SIEPortDataInToSIE;
+wire SIEPortWEnToSIE;
+wire [7:0] SIEPortCtrlInToSIE;
+wire fullSpeedPolarityToSIE;
+wire fullSpeedBitRateToSIE;
+wire connectSlaveToHost;
+wire noActivityTimeOut;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+wire [7:0] slaveRxFifoData;
+wire [7:0] dataFromEP0RxFifo;
+wire [7:0] dataFromEP1RxFifo;
+wire [7:0] dataFromEP2RxFifo;
+wire [7:0] dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo;
+wire [7:0] dataFromEP1TxFifo;
+wire [7:0] dataFromEP2TxFifo;
+wire [7:0] dataFromEP3TxFifo;
+wire slaveEP0RxFifoSel;
+wire slaveEP1RxFifoSel;
+wire slaveEP2RxFifoSel;
+wire slaveEP3RxFifoSel;
+wire slaveEP0TxFifoSel;
+wire slaveEP1TxFifoSel;
+wire slaveEP2TxFifoSel;
+wire slaveEP3TxFifoSel;
+wire rstSyncToBusClk;
+wire rstSyncToUsbClk;
+wire noActivityTimeOutEnableToSIE;
+wire noActivityTimeOutEnableFromHost;
+wire noActivityTimeOutEnableFromSlave;
+
+assign USBFullSpeed = fullSpeedBitRateToSIE;  
+assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
+assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
+
+usbSlaveControl u_usbSlaveControl(
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .RxByteStatus(RxCtrlOut), 
+  .RxData(RxDataFromSIE), 
+  .RxDataValid(RxDataOutWEn),
+  .SIERxTimeOut(noActivityTimeOut), 
+  .SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
+  .RxFifoData(slaveRxFifoData),
+  .connectSlaveToHost(connectSlaveToHost),
+  .fullSpeedRate(fullSpeedBitRateFromSlave), 
+  .fullSpeedPol(fullSpeedPolarityFromSlave),
+  .SCTxPortEn(SIEPortWEnFromSlave), 
+  .SCTxPortRdy(SIEPortTxRdy),
+  .SCTxPortData(SIEPortDataInFromSlave), 
+  .SCTxPortCtrl(SIEPortCtrlInFromSlave),
+  .vBusDetect(vBusDetect),
+  .connectStateIn(connectState), 
+  .resumeDetectedIn(resumeDetected),
+  .busAddress(address_i[4:0]),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromSlaveControl), 
+  .busWriteEn(we_i),
+  .busStrobe_i(strobe_i),
+  .SOFRxedIntOut(slaveSOFRxedIntOut), 
+  .resetEventIntOut(slaveResetEventIntOut), 
+  .resumeIntOut(slaveResumeIntOut), 
+  .transDoneIntOut(slaveTransDoneIntOut),
+  .NAKSentIntOut(slaveNAKSentIntOut),
+  .vBusDetIntOut(slaveVBusDetIntOut),
+  .slaveControlSelect(slaveControlSel),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+  );
+
+
+wishBoneBI u_wishBoneBI (
+  .address(address_i), 
+  .dataIn(data_i), 
+  .dataOut(data_o), 
+  .writeEn(we_i), 
+  .strobe_i(strobe_i),
+  .ack_o(ack_o),
+  .clk(clk_i), 
+  .rst(rstSyncToBusClk),
+  .hostControlSel(), 
+  .hostRxFifoSel(), 
+  .hostTxFifoSel(),
+  .slaveControlSel(slaveControlSel),
+  .slaveEP0RxFifoSel(slaveEP0RxFifoSel), 
+  .slaveEP1RxFifoSel(slaveEP1RxFifoSel), 
+  .slaveEP2RxFifoSel(slaveEP2RxFifoSel), 
+  .slaveEP3RxFifoSel(slaveEP3RxFifoSel), 
+  .slaveEP0TxFifoSel(slaveEP0TxFifoSel), 
+  .slaveEP1TxFifoSel(slaveEP1TxFifoSel), 
+  .slaveEP2TxFifoSel(slaveEP2TxFifoSel), 
+  .slaveEP3TxFifoSel(slaveEP3TxFifoSel), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .dataFromHostControl(8'h00),
+  .dataFromHostRxFifo(8'h00),
+  .dataFromHostTxFifo(8'h00),
+  .dataFromSlaveControl(dataFromSlaveControl),
+  .dataFromEP0RxFifo(dataFromEP0RxFifo), 
+  .dataFromEP1RxFifo(dataFromEP1RxFifo), 
+  .dataFromEP2RxFifo(dataFromEP2RxFifo), 
+  .dataFromEP3RxFifo(dataFromEP3RxFifo),
+  .dataFromEP0TxFifo(dataFromEP0TxFifo), 
+  .dataFromEP1TxFifo(dataFromEP1TxFifo), 
+  .dataFromEP2TxFifo(dataFromEP2TxFifo), 
+  .dataFromEP3TxFifo(dataFromEP3TxFifo),
+  .dataFromHostSlaveMux(dataFromHostSlaveMux)
+   );
+
+
+
+assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave;
+assign SIEPortDataInToSIE = SIEPortDataInFromSlave;
+assign SIEPortWEnToSIE = SIEPortWEnFromSlave;
+assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave;
+assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave;
+assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave;
+
+hostSlaveMuxBI u_hostSlaveMuxBI (
+  .dataIn(data_i), 
+  .dataOut(dataFromHostSlaveMux),
+  .address(address_i[0]),
+  .writeEn(we_i),
+  .strobe_i(strobe_i),
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .hostSlaveMuxSel(hostSlaveMuxSel),
+  .hostMode(), 
+  .rstFromWire(rst_i),
+  .rstSyncToBusClkOut(rstSyncToBusClk),
+  .rstSyncToUsbClkOut(rstSyncToUsbClk)
+);
+
+usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .USBWireDataIn(USBWireDataIn),
+  .USBWireDataOut(USBWireDataOut),
+  .USBWireDataInTick(USBWireDataInTick),
+  .USBWireDataOutTick(USBWireDataOutTick),
+  .USBWireCtrlOut(USBWireCtrlOut),
+  .connectState(connectState),
+  .resumeDetected(resumeDetected),
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataFromSIE), 
+  .SIEPortCtrlIn(SIEPortCtrlInToSIE),
+  .SIEPortDataIn(SIEPortDataInToSIE), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEnToSIE), 
+  .fullSpeedPolarity(fullSpeedPolarityToSIE),
+  .fullSpeedBitRate(fullSpeedBitRateToSIE),
+  .noActivityTimeOut(noActivityTimeOut),
+  .noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
+);
+
+
+
+//---Slave fifos
+
+TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP0REn), 
+  .fifoEmpty(TxFifoEP0Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0TxFifoSel),
+  .busDataIn(data_i),
+  .busDataOut(dataFromEP0TxFifo),
+  .fifoDataOut(TxFifoEP0Data) );
+
+TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP1REn), 
+  .fifoEmpty(TxFifoEP1Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1TxFifo),
+  .fifoDataOut(TxFifoEP1Data) );
+
+TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP2REn), 
+  .fifoEmpty(TxFifoEP2Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2TxFifo),
+  .fifoDataOut(TxFifoEP2Data) );
+
+TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoREn(TxFifoEP3REn), 
+  .fifoEmpty(TxFifoEP3Empty),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3TxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3TxFifo),
+  .fifoDataOut(TxFifoEP3Data) );
+
+RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP0WEn), 
+  .fifoFull(RxFifoEP0Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP0RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP0RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP1WEn), 
+  .fifoFull(RxFifoEP1Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP1RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP1RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP2WEn), 
+  .fifoFull(RxFifoEP2Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP2RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP2RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
+  .usbClk(usbClk), 
+  .busClk(clk_i), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk), 
+  .fifoWEn(RxFifoEP3WEn), 
+  .fifoFull(RxFifoEP3Full),
+  .busAddress(address_i[2:0]), 
+  .busWriteEn(we_i), 
+  .busStrobe_i(strobe_i),
+  .busFifoSelect(slaveEP3RxFifoSel),
+  .busDataIn(data_i), 
+  .busDataOut(dataFromEP3RxFifo),
+  .fifoDataIn(slaveRxFifoData)  );
+
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl.v	(revision 264)
@@ -0,0 +1,521 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSlaveControl.v                                            ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbSlaveControl(
+  busClk, 
+  rstSyncToBusClk,
+  usbClk, 
+  rstSyncToUsbClk,
+  //getPacket
+  RxByteStatus, RxData, RxDataValid,
+  SIERxTimeOut, RxFifoData, SIERxTimeOutEn,
+  //speedCtrlMux
+  fullSpeedRate, fullSpeedPol,
+  connectSlaveToHost,
+  //SCTxPortArbiter
+  SCTxPortEn, SCTxPortRdy,
+  SCTxPortData, SCTxPortCtrl,
+  //rxStatusMonitor
+  vBusDetect,
+  connectStateIn, 
+  resumeDetectedIn,
+  //USBHostControlBI 
+  busAddress,
+  busDataIn, 
+  busDataOut, 
+  busWriteEn,
+  busStrobe_i,
+  SOFRxedIntOut, 
+  resetEventIntOut, 
+  resumeIntOut, 
+  transDoneIntOut,
+  vBusDetIntOut,
+  NAKSentIntOut,
+  slaveControlSelect,
+  //fifoMux
+  TxFifoEP0REn,
+  TxFifoEP1REn,
+  TxFifoEP2REn,
+  TxFifoEP3REn,
+  TxFifoEP0Data,
+  TxFifoEP1Data,
+  TxFifoEP2Data,
+  TxFifoEP3Data,
+  TxFifoEP0Empty,
+  TxFifoEP1Empty,
+  TxFifoEP2Empty,
+  TxFifoEP3Empty,
+  RxFifoEP0WEn,
+  RxFifoEP1WEn,
+  RxFifoEP2WEn,
+  RxFifoEP3WEn,
+  RxFifoEP0Full,
+  RxFifoEP1Full,
+  RxFifoEP2Full,
+  RxFifoEP3Full
+    );
+
+input busClk; 
+input rstSyncToBusClk;
+input usbClk; 
+input rstSyncToUsbClk;
+//getPacket
+input [7:0] RxByteStatus;
+input [7:0] RxData;
+input RxDataValid;
+input SIERxTimeOut; 
+output SIERxTimeOutEn;
+output [7:0] RxFifoData;
+//speedCtrlMux
+output fullSpeedRate;
+output fullSpeedPol;
+output connectSlaveToHost;
+//HCTxPortArbiter
+output SCTxPortEn;
+input SCTxPortRdy;
+output [7:0] SCTxPortData;
+output [7:0] SCTxPortCtrl;
+//rxStatusMonitor
+input vBusDetect;
+input [1:0] connectStateIn;
+input resumeDetectedIn;
+//USBHostControlBI 
+input [4:0] busAddress;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+input busWriteEn;
+input busStrobe_i;
+output SOFRxedIntOut; 
+output resetEventIntOut; 
+output resumeIntOut; 
+output transDoneIntOut;
+output vBusDetIntOut;
+output NAKSentIntOut;
+input slaveControlSelect;
+//fifoMux
+output TxFifoEP0REn;
+output TxFifoEP1REn;
+output TxFifoEP2REn;
+output TxFifoEP3REn;
+input [7:0] TxFifoEP0Data;
+input [7:0] TxFifoEP1Data;
+input [7:0] TxFifoEP2Data;
+input [7:0] TxFifoEP3Data;
+input TxFifoEP0Empty;
+input TxFifoEP1Empty;
+input TxFifoEP2Empty;
+input TxFifoEP3Empty;
+output RxFifoEP0WEn;
+output RxFifoEP1WEn;
+output RxFifoEP2WEn;
+output RxFifoEP3WEn;
+input RxFifoEP0Full;
+input RxFifoEP1Full;
+input RxFifoEP2Full;
+input RxFifoEP3Full;
+
+wire busClk; 
+wire rstSyncToBusClk;
+wire usbClk; 
+wire rstSyncToUsbClk;
+wire [7:0] RxByteStatus;
+wire [7:0] RxData;
+wire RxDataValid;
+wire SIERxTimeOut;
+wire SIERxTimeOutEn;
+wire [7:0] RxFifoData;
+wire fullSpeedRate;
+wire fullSpeedPol;
+wire connectSlaveToHost;
+wire [7:0] SCTxPortData;
+wire [7:0] SCTxPortCtrl;
+wire [1:0] connectStateIn;
+wire resumeDetectedIn;
+wire [4:0] busAddress;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire busWriteEn;
+wire busStrobe_i;
+wire SOFRxedIntOut; 
+wire resetEventIntOut; 
+wire resumeIntOut; 
+wire transDoneIntOut;
+wire vBusDetIntOut;
+wire NAKSentIntOut;
+wire slaveControlSelect;
+wire TxFifoEP0REn;
+wire TxFifoEP1REn;
+wire TxFifoEP2REn;
+wire TxFifoEP3REn;
+wire [7:0] TxFifoEP0Data;
+wire [7:0] TxFifoEP1Data;
+wire [7:0] TxFifoEP2Data;
+wire [7:0] TxFifoEP3Data;
+wire TxFifoEP0Empty;
+wire TxFifoEP1Empty;
+wire TxFifoEP2Empty;
+wire TxFifoEP3Empty;
+wire RxFifoEP0WEn;
+wire RxFifoEP1WEn;
+wire RxFifoEP2WEn;
+wire RxFifoEP3WEn;
+wire RxFifoEP0Full;
+wire RxFifoEP1Full;
+wire RxFifoEP2Full;
+wire RxFifoEP3Full;
+
+//internal wiring
+wire [7:0] directCntlCntl;
+wire [7:0] directCntlData;
+wire directCntlGnt;
+wire directCntlReq;
+wire directCntlWEn;
+wire [7:0] sendPacketCntl;
+wire [7:0] sendPacketData;
+wire sendPacketGnt;
+wire sendPacketReq;
+wire sendPacketWEn;    
+wire SCTxPortArbRdyOut;
+wire transDone;
+wire [1:0] directLineState;
+wire directLineCtrlEn;
+wire [3:0] RxPID;
+wire [1:0] connectStateOut;
+wire resumeIntFromRxStatusMon;
+wire [1:0] endP0TransTypeReg;
+wire [1:0] endP1TransTypeReg;
+wire [1:0] endP2TransTypeReg;
+wire [1:0] endP3TransTypeReg;
+wire [1:0] endP0NAKTransTypeReg;
+wire [1:0] endP1NAKTransTypeReg;
+wire [1:0] endP2NAKTransTypeReg;
+wire [1:0] endP3NAKTransTypeReg;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+wire [7:0] endP0StatusReg;
+wire [7:0] endP1StatusReg;
+wire [7:0] endP2StatusReg;
+wire [7:0] endP3StatusReg;
+wire [6:0] USBTgtAddress;
+wire [10:0] frameNum;
+wire clrEP0Rdy;
+wire clrEP1Rdy;
+wire clrEP2Rdy;
+wire clrEP3Rdy;
+wire SCGlobalEn;
+wire ACKRxed; 
+wire CRCError; 
+wire RXOverflow; 
+wire RXTimeOut; 
+wire bitStuffError; 
+wire dataSequence; 
+wire stallSent;
+wire NAKSent;
+wire SOFRxed;
+wire [4:0] endPControlReg;
+wire [1:0] transTypeNAK;
+wire [1:0] transType;
+wire [3:0] currEndP;
+wire getPacketREn;
+wire getPacketRdy;
+wire [3:0] slaveControllerPIDOut;
+wire slaveControllerReadyIn;
+wire slaveControllerWEnOut;
+wire TxFifoRE;
+wire [7:0] TxFifoData;
+wire TxFifoEmpty;
+wire RxFifoWE;
+wire RxFifoFull;
+wire resetEventFromRxStatusMon;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire endPointReadyFromSlaveCtrlrToGetPkt;
+
+USBSlaveControlBI u_USBSlaveControlBI
+  (.address(busAddress),
+  .dataIn(busDataIn), 
+  .dataOut(busDataOut), 
+  .writeEn(busWriteEn),
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .rstSyncToBusClk(rstSyncToBusClk),
+  .usbClk(usbClk), 
+  .rstSyncToUsbClk(rstSyncToUsbClk),
+  .SOFRxedIntOut(SOFRxedIntOut), 
+  .resetEventIntOut(resetEventIntOut), 
+  .resumeIntOut(resumeIntOut), 
+  .transDoneIntOut(transDoneIntOut),
+  .vBusDetIntOut(vBusDetIntOut),
+  .NAKSentIntOut(NAKSentIntOut),
+  .endP0TransTypeReg(endP0TransTypeReg), 
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg), 
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg), 
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg), 
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .EP0StatusReg(endP0StatusReg),
+  .EP1StatusReg(endP1StatusReg),
+  .EP2StatusReg(endP2StatusReg),
+  .EP3StatusReg(endP3StatusReg),
+  .SCAddrReg(USBTgtAddress), 
+  .frameNum(frameNum),
+  .connectStateIn(connectStateOut),
+  .vBusDetectIn(vBusDetect),
+  .SOFRxedIn(SOFRxed), 
+  .resetEventIn(resetEventFromRxStatusMon), 
+  .resumeIntIn(resumeIntFromRxStatusMon), 
+  .transDoneIn(transDone),
+  .NAKSentIn(NAKSent),
+  .slaveControlSelect(slaveControlSelect),
+  .clrEP0Ready(clrEP0Rdy), 
+  .clrEP1Ready(clrEP1Rdy), 
+  .clrEP2Ready(clrEP2Rdy), 
+  .clrEP3Ready(clrEP3Rdy),
+  .TxLineState(directLineState),
+  .LineDirectControlEn(directLineCtrlEn),
+  .fullSpeedPol(fullSpeedPol), 
+  .fullSpeedRate(fullSpeedRate),
+  .connectSlaveToHost(connectSlaveToHost),
+  .SCGlobalEn(SCGlobalEn)
+  );
+
+slavecontroller u_slavecontroller
+  (.CRCError(CRCError), 
+  .NAKSent(NAKSent), 
+  .RxByte(RxData), 
+  .RxDataWEn(RxDataValid), 
+  .RxOverflow(RXOverflow), 
+  .RxStatus(RxByteStatus), 
+  .RxTimeOut(RXTimeOut), 
+  .SCGlobalEn(SCGlobalEn), 
+  .SOFRxed(SOFRxed), 
+  .USBEndPControlReg(endPControlReg), 
+  .USBEndPNakTransTypeReg(transTypeNAK), 
+  .USBEndPTransTypeReg(transType), 
+  .USBEndP(currEndP), 
+  .USBTgtAddress(USBTgtAddress),
+  .bitStuffError(bitStuffError), 
+  .clk(usbClk), 
+  .clrEPRdy(clrEPRdy), 
+  .endPMuxErrorsWEn(endPMuxErrorsWEn), 
+  .frameNum(frameNum), 
+  .getPacketREn(getPacketREn), 
+  .getPacketRdy(getPacketRdy), 
+  .rst(rstSyncToUsbClk), 
+  .sendPacketPID(slaveControllerPIDOut), 
+  .sendPacketRdy(slaveControllerReadyIn), 
+  .sendPacketWEn(slaveControllerWEnOut), 
+  .stallSent(stallSent), 
+  .transDone(transDone),
+  .endPointReadyToGetPkt(endPointReadyFromSlaveCtrlrToGetPkt)
+    );
+
+
+endpMux u_endpMux (
+  .clk(usbClk), 
+  .rst(rstSyncToUsbClk),
+  .currEndP(currEndP),
+  .NAKSent(NAKSent),
+  .stallSent(stallSent),
+  .CRCError(CRCError),
+  .bitStuffError(bitStuffError),
+  .RxOverflow(RXOverflow),
+  .RxTimeOut(RXTimeOut),
+  .dataSequence(dataSequence),
+  .ACKRxed(ACKRxed),
+  .transType(transType),
+  .transTypeNAK(transTypeNAK),
+  .endPControlReg(endPControlReg),
+  .clrEPRdy(clrEPRdy),
+  .endPMuxErrorsWEn(endPMuxErrorsWEn),
+  .endP0ControlReg(endP0ControlReg),
+  .endP1ControlReg(endP1ControlReg),
+  .endP2ControlReg(endP2ControlReg),
+  .endP3ControlReg(endP3ControlReg),
+  .endP0StatusReg(endP0StatusReg),
+  .endP1StatusReg(endP1StatusReg),
+  .endP2StatusReg(endP2StatusReg),
+  .endP3StatusReg(endP3StatusReg),
+  .endP0TransTypeReg(endP0TransTypeReg),
+  .endP1TransTypeReg(endP1TransTypeReg),
+  .endP2TransTypeReg(endP2TransTypeReg),
+  .endP3TransTypeReg(endP3TransTypeReg),
+  .endP0NAKTransTypeReg(endP0NAKTransTypeReg),
+  .endP1NAKTransTypeReg(endP1NAKTransTypeReg),
+  .endP2NAKTransTypeReg(endP2NAKTransTypeReg),
+  .endP3NAKTransTypeReg(endP3NAKTransTypeReg),
+  .clrEP0Rdy(clrEP0Rdy),
+  .clrEP1Rdy(clrEP1Rdy),
+  .clrEP2Rdy(clrEP2Rdy),
+  .clrEP3Rdy(clrEP3Rdy)
+    );
+
+slaveSendPacket u_slaveSendPacket
+  (.PID(slaveControllerPIDOut), 
+  .SCTxPortCntl(sendPacketCntl),
+  .SCTxPortData(sendPacketData),
+  .SCTxPortGnt(sendPacketGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(sendPacketReq),
+  .SCTxPortWEn(sendPacketWEn),
+  .clk(usbClk),
+  .fifoData(TxFifoData),
+  .fifoEmpty(TxFifoEmpty),
+  .fifoReadEn(TxFifoRE),
+  .rst(rstSyncToUsbClk),
+  .sendPacketRdy(slaveControllerReadyIn),
+  .sendPacketWEn(slaveControllerWEnOut) );
+
+slaveDirectControl u_slaveDirectControl
+  (.SCTxPortCntl(directCntlCntl),
+  .SCTxPortData(directCntlData),
+  .SCTxPortGnt(directCntlGnt),
+  .SCTxPortRdy(SCTxPortArbRdyOut),
+  .SCTxPortReq(directCntlReq),
+  .SCTxPortWEn(directCntlWEn),
+  .clk(usbClk),
+  .directControlEn(directLineCtrlEn),
+  .directControlLineState(directLineState),
+  .rst(rstSyncToUsbClk) ); 
+
+SCTxPortArbiter u_SCTxPortArbiter
+  (.SCTxPortCntl(SCTxPortCtrl),
+  .SCTxPortData(SCTxPortData),
+  .SCTxPortRdyIn(SCTxPortRdy),
+  .SCTxPortRdyOut(SCTxPortArbRdyOut),
+  .SCTxPortWEnable(SCTxPortEn),
+  .clk(usbClk),
+  .directCntlCntl(directCntlCntl),
+  .directCntlData(directCntlData),
+  .directCntlGnt(directCntlGnt),
+  .directCntlReq(directCntlReq),
+  .directCntlWEn(directCntlWEn),
+  .rst(rstSyncToUsbClk),
+  .sendPacketCntl(sendPacketCntl),
+  .sendPacketData(sendPacketData),
+  .sendPacketGnt(sendPacketGnt),
+  .sendPacketReq(sendPacketReq),
+  .sendPacketWEn(sendPacketWEn) );    
+
+
+slaveGetPacket u_slaveGetPacket
+  (.ACKRxed(ACKRxed), 
+  .CRCError(CRCError), 
+  .RXDataIn(RxData),
+  .RXDataValid(RxDataValid),
+  .RXFifoData(RxFifoData),
+  .RXFifoFull(RxFifoFull),
+  .RXFifoWEn(RxFifoWE),
+  .RXPacketRdy(getPacketRdy),
+  .RXStreamStatusIn(RxByteStatus),
+  .RxPID(RxPID),
+  .SIERxTimeOut(SIERxTimeOut),
+  .SIERxTimeOutEn(SIERxTimeOutEn),
+  .clk(usbClk),
+  .RXOverflow(RXOverflow), 
+  .RXTimeOut(RXTimeOut), 
+  .bitStuffError(bitStuffError), 
+  .dataSequence(dataSequence), 
+  .getPacketEn(getPacketREn),
+  .rst(rstSyncToUsbClk),
+  .endPointReady(endPointReadyFromSlaveCtrlrToGetPkt)
+  ); 
+
+slaveRxStatusMonitor  u_slaveRxStatusMonitor
+  (.connectStateIn(connectStateIn),
+  .connectStateOut(connectStateOut),
+  .resumeDetectedIn(resumeDetectedIn),
+  .resetEventOut(resetEventFromRxStatusMon),
+  .resumeIntOut(resumeIntFromRxStatusMon),
+  .clk(usbClk),
+  .rst(rstSyncToUsbClk)  );    
+  
+fifoMux u_fifoMux (
+  .currEndP(currEndP),
+  //TxFifo
+  .TxFifoREn(TxFifoRE),
+  .TxFifoEP0REn(TxFifoEP0REn),
+  .TxFifoEP1REn(TxFifoEP1REn),
+  .TxFifoEP2REn(TxFifoEP2REn),
+  .TxFifoEP3REn(TxFifoEP3REn),
+  .TxFifoData(TxFifoData),
+  .TxFifoEP0Data(TxFifoEP0Data),
+  .TxFifoEP1Data(TxFifoEP1Data),
+  .TxFifoEP2Data(TxFifoEP2Data),
+  .TxFifoEP3Data(TxFifoEP3Data),
+  .TxFifoEmpty(TxFifoEmpty),
+  .TxFifoEP0Empty(TxFifoEP0Empty),
+  .TxFifoEP1Empty(TxFifoEP1Empty),
+  .TxFifoEP2Empty(TxFifoEP2Empty),
+  .TxFifoEP3Empty(TxFifoEP3Empty),
+  //RxFifo
+  .RxFifoWEn(RxFifoWE),
+  .RxFifoEP0WEn(RxFifoEP0WEn),
+  .RxFifoEP1WEn(RxFifoEP1WEn),
+  .RxFifoEP2WEn(RxFifoEP2WEn),
+  .RxFifoEP3WEn(RxFifoEP3WEn),
+  .RxFifoFull(RxFifoFull),
+  .RxFifoEP0Full(RxFifoEP0Full),
+  .RxFifoEP1Full(RxFifoEP1Full),
+  .RxFifoEP2Full(RxFifoEP2Full),
+  .RxFifoEP3Full(RxFifoEP3Full)
+    );
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBus_h.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBus_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBus_h.v	(revision 264)
@@ -0,0 +1,35 @@
+//////////////////////////////////////////////////////////////////////
+// wishBoneBus_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef wishBoneBus_h_vdefined
+`else
+`define wishBoneBus_h_vdefined
+ 
+//memoryMap
+`define HCREG_BASE 8'h00
+`define HCREG_BASE_PLUS_0X10 8'h10
+`define HOST_RX_FIFO_BASE 8'h20
+`define HOST_TX_FIFO_BASE 8'h30
+`define SCREG_BASE 8'h40
+`define SCREG_BASE_PLUS_0X10 8'h50
+`define EP0_RX_FIFO_BASE 8'h60
+`define EP0_TX_FIFO_BASE 8'h70
+`define EP1_RX_FIFO_BASE 8'h80
+`define EP1_TX_FIFO_BASE 8'h90
+`define EP2_RX_FIFO_BASE 8'ha0
+`define EP2_TX_FIFO_BASE 8'hb0
+`define EP3_RX_FIFO_BASE 8'hc0
+`define EP3_TX_FIFO_BASE 8'hd0
+`define HOST_SLAVE_CONTROL_BASE 8'he0
+`define ADDRESS_DECODE_MASK 8'hf0
+
+//FifoAddresses
+`define FIFO_DATA_REG 3'b000
+`define FIFO_STATUS_REG 3'b001
+`define FIFO_DATA_COUNT_MSB 3'b010
+`define FIFO_DATA_COUNT_LSB 3'b011
+`define FIFO_CONTROL_REG 3'b100
+
+`endif //wishBoneBus_h_vdefined
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBI.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBI.v	(revision 264)
@@ -0,0 +1,245 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishBoneBI.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "wishBoneBus_h.v"
+
+ 
+module wishBoneBI (
+  address, dataIn, dataOut, writeEn, 
+  strobe_i,
+  ack_o,
+  clk, rst,
+  hostControlSel, 
+  hostRxFifoSel, hostTxFifoSel,
+  slaveControlSel,
+  slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel, 
+  slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel, 
+  hostSlaveMuxSel,
+  dataFromHostControl,
+  dataFromHostRxFifo,
+  dataFromHostTxFifo,
+  dataFromSlaveControl,
+  dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
+  dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
+  dataFromHostSlaveMux
+   );
+input clk;
+input rst;
+input [7:0] address;
+input [7:0] dataIn;
+output [7:0] dataOut;
+input strobe_i;
+output ack_o;
+input writeEn;
+output hostControlSel;
+output hostRxFifoSel;
+output hostTxFifoSel;
+output slaveControlSel;
+output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+output hostSlaveMuxSel;
+input [7:0] dataFromHostControl;
+input [7:0] dataFromHostRxFifo;
+input [7:0] dataFromHostTxFifo;
+input [7:0] dataFromSlaveControl;
+input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+input [7:0] dataFromHostSlaveMux;
+
+
+wire clk;
+wire rst;
+wire [7:0] address;
+wire [7:0] dataIn;
+reg [7:0] dataOut;
+wire writeEn;
+wire strobe_i;
+reg ack_o;
+reg hostControlSel;
+reg hostRxFifoSel;
+reg hostTxFifoSel;
+reg slaveControlSel;
+reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel; 
+reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel; 
+reg hostSlaveMuxSel;
+wire [7:0] dataFromHostControl;
+wire [7:0] dataFromHostRxFifo;
+wire [7:0] dataFromHostTxFifo;
+wire [7:0] dataFromSlaveControl;
+wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
+wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
+wire [7:0] dataFromHostSlaveMux;
+
+//internal wires and regs
+reg ack_delayed;
+reg ack_immediate;
+
+//address decode and data mux
+always @(address or
+  dataFromHostControl or
+  dataFromHostRxFifo or
+  dataFromHostTxFifo or
+  dataFromSlaveControl or
+  dataFromEP0RxFifo or 
+  dataFromEP1RxFifo or
+  dataFromEP2RxFifo or
+  dataFromEP3RxFifo or
+  dataFromHostSlaveMux or 
+  dataFromEP0TxFifo or
+  dataFromEP1TxFifo or
+  dataFromEP2TxFifo or
+  dataFromEP3TxFifo)
+begin
+  hostControlSel <= 1'b0;
+  hostRxFifoSel <= 1'b0;
+  hostTxFifoSel <= 1'b0;
+  slaveControlSel <= 1'b0;
+  slaveEP0RxFifoSel <= 1'b0;
+  slaveEP0TxFifoSel <= 1'b0;
+  slaveEP1RxFifoSel <= 1'b0;
+  slaveEP1TxFifoSel <= 1'b0;
+  slaveEP2RxFifoSel <= 1'b0;
+  slaveEP2TxFifoSel <= 1'b0;
+  slaveEP3RxFifoSel <= 1'b0;
+  slaveEP3TxFifoSel <= 1'b0;
+  hostSlaveMuxSel <= 1'b0;
+  case (address & `ADDRESS_DECODE_MASK)
+    `HCREG_BASE : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HCREG_BASE_PLUS_0X10 : begin
+      hostControlSel <= 1'b1;
+      dataOut <= dataFromHostControl;
+    end
+    `HOST_RX_FIFO_BASE : begin
+      hostRxFifoSel <= 1'b1;
+      dataOut <= dataFromHostRxFifo;
+    end
+    `HOST_TX_FIFO_BASE : begin
+      hostTxFifoSel <= 1'b1;
+      dataOut <= dataFromHostTxFifo;
+    end
+    `SCREG_BASE : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `SCREG_BASE_PLUS_0X10 : begin
+      slaveControlSel <= 1'b1;
+      dataOut <= dataFromSlaveControl;
+    end
+    `EP0_RX_FIFO_BASE : begin
+      slaveEP0RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0RxFifo;
+    end
+    `EP0_TX_FIFO_BASE : begin
+      slaveEP0TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP0TxFifo;
+    end
+    `EP1_RX_FIFO_BASE : begin
+      slaveEP1RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1RxFifo;
+    end
+    `EP1_TX_FIFO_BASE : begin
+      slaveEP1TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP1TxFifo;
+    end
+    `EP2_RX_FIFO_BASE : begin
+      slaveEP2RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2RxFifo;
+    end
+    `EP2_TX_FIFO_BASE : begin
+      slaveEP2TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP2TxFifo;
+    end
+    `EP3_RX_FIFO_BASE : begin
+      slaveEP3RxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3RxFifo;
+    end
+    `EP3_TX_FIFO_BASE : begin
+      slaveEP3TxFifoSel <= 1'b1;
+      dataOut <= dataFromEP3TxFifo;
+    end
+    `HOST_SLAVE_CONTROL_BASE : begin
+      hostSlaveMuxSel <= 1'b1; 
+      dataOut <= dataFromHostSlaveMux;
+    end
+    default: 
+      dataOut <= 8'h00;
+  endcase
+end
+
+//delayed ack
+always @(posedge clk) begin
+  ack_delayed <= strobe_i;
+end
+
+//immediate ack
+always @(strobe_i) begin
+  ack_immediate <= strobe_i;
+end 
+
+//select between immediate and delayed ack
+always @(writeEn or address or ack_delayed or ack_immediate) begin
+  if (writeEn == 1'b0 &&
+      (address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
+       address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
+  begin
+    ack_o <= ack_delayed & ack_immediate;
+  end
+  else
+  begin
+    ack_o <= ack_immediate;
+  end
+end
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/smartgen/smartgen.aws
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/smartgen/smartgen.aws	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/smartgen/smartgen.aws	(revision 264)
@@ -0,0 +1 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?><workspace xmlns="http://actel.com/sweng/afi"><name>smartgen</name><netlistFormat>Verilog</netlistFormat><reports><resource select="F"></resource></reports><subproject libero="T"/><hdltype>Verilog</hdltype><device die="IS6X6M2LP" family="IGLOO" package="fg256"/><componentInstances/><SmartGen version="8.0"/></workspace>
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.adb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.adb
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.tcl
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.tcl	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.tcl	(revision 264)
@@ -0,0 +1,8 @@
+# Created by Libero Project Manager 8.3.0.22
+# Fri Aug 22 14:28:19 2008
+
+# (OPEN DESIGN)
+
+
+# set default back-annotation base-name
+set_defvar "BA_NAME" "usbDeviceActelTop_ba"
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifo.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifo.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifo.v	(revision 264)
@@ -0,0 +1,134 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// RxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo read access via bus interface, fifo write access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module RxFifo(
+  busClk,
+  usbClk,
+  rstSyncToBusClk, 
+  rstSyncToUsbClk, 
+  fifoWEn, 
+  fifoFull,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoDataIn  );
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input busClk; 
+input usbClk; 
+input rstSyncToBusClk; 
+input rstSyncToUsbClk; 
+input fifoWEn;
+output fifoFull;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+input [7:0] fifoDataIn;
+
+wire busClk; 
+wire usbClk; 
+wire rstSyncToBusClk; 
+wire rstSyncToUsbClk; 
+wire fifoWEn; 
+wire fifoFull;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+wire [7:0] fifoDataIn;
+
+//internal wires and regs
+wire [7:0] dataFromFifoToBus;
+wire fifoREn;
+wire forceEmptySyncToBusClk;
+wire forceEmptySyncToUsbClk;
+wire [15:0] numElementsInFifo;
+wire fifoEmpty;   //not used
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .wrClk(usbClk), 
+  .rdClk(busClk), 
+  .rstSyncToWrClk(rstSyncToUsbClk), 
+  .rstSyncToRdClk(rstSyncToBusClk), 
+  .dataIn(fifoDataIn), 
+  .dataOut(dataFromFifoToBus), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmptySyncToWrClk(forceEmptySyncToUsbClk), 
+  .forceEmptySyncToRdClk(forceEmptySyncToBusClk), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+RxfifoBI u_RxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .fifoSelect(busFifoSelect),
+  .fifoDataIn(dataFromFifoToBus),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut),
+  .fifoREn(fifoREn),
+  .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+  .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifoBI.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifoBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifoBI.v	(revision 264)
@@ -0,0 +1,149 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxfifoBI.v                                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "wishBoneBus_h.v"
+
+module TxfifoBI (
+  address, writeEn, strobe_i,
+  busClk, 
+  usbClk, 
+  rstSyncToBusClk, 
+  fifoSelect,
+  busDataIn, 
+  busDataOut,
+  fifoWEn,
+  forceEmptySyncToUsbClk,
+  forceEmptySyncToBusClk,
+  numElementsInFifo
+  );
+input [2:0] address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+input rstSyncToBusClk;
+input [7:0] busDataIn; 
+output [7:0] busDataOut;
+output fifoWEn;
+output forceEmptySyncToUsbClk;
+output forceEmptySyncToBusClk;
+input [15:0] numElementsInFifo;
+input fifoSelect;
+
+
+wire [2:0] address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+wire rstSyncToBusClk;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut;
+reg fifoWEn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoSelect;
+
+reg forceEmptyReg;
+reg forceEmpty;
+reg forceEmptyToggle;
+reg [2:0] forceEmptyToggleSyncToUsbClk;
+
+//sync write
+always @(posedge busClk)
+begin
+  if (writeEn == 1'b1 && fifoSelect == 1'b1 && 
+  address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
+    forceEmpty <= 1'b1;
+  else
+    forceEmpty <= 1'b0;
+end
+
+//detect rising edge of 'forceEmpty', and generate toggle signal
+always @(posedge busClk) begin
+  if (rstSyncToBusClk == 1'b1) begin
+    forceEmptyReg <= 1'b0;
+    forceEmptyToggle <= 1'b0;
+  end
+  else begin
+    if (forceEmpty == 1'b1)
+      forceEmptyReg <= 1'b1;
+    else
+      forceEmptyReg <= 1'b0;
+    if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0)
+      forceEmptyToggle <= ~forceEmptyToggle;
+  end
+end
+assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0;
+
+// double sync across clock domains to generate 'forceEmptySyncToUsbClk'
+always @(posedge usbClk) begin
+    forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle};
+end
+assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1];
+
+// async read mux
+assign busDataOut = 8'h00;
+//always @(address or fifoFull or numElementsInFifo)
+//begin
+//  case (address)
+//      `FIFO_STATUS_REG : busDataOut <= {7'b0000000, fifoFull};
+//      `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
+//      `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
+//      default: busDataOut <= 8'h00;
+//  endcase
+//end
+
+//generate fifo write strobe
+always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin
+  if (address == `FIFO_DATA_REG &&   writeEn == 1'b1 && 
+  strobe_i == 1'b1 &&   fifoSelect == 1'b1)
+    fifoWEn <= 1'b1;
+  else
+    fifoWEn <= 1'b0;
+end
+
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/endpMux.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/endpMux.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/endpMux.v	(revision 264)
@@ -0,0 +1,259 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// endpMux.v                                                    ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSlaveControl_h.v" 
+
+module endpMux (
+  clk, 
+  rst,
+  currEndP,
+  NAKSent,
+  stallSent,
+  CRCError,
+  bitStuffError,
+  RxOverflow,
+  RxTimeOut,
+  dataSequence,
+  ACKRxed,
+  transType,
+  transTypeNAK,
+  endPControlReg,
+  clrEPRdy,
+  endPMuxErrorsWEn,
+  endP0ControlReg,
+  endP1ControlReg,
+  endP2ControlReg,
+  endP3ControlReg,
+  endP0StatusReg,
+  endP1StatusReg,
+  endP2StatusReg,
+  endP3StatusReg,
+  endP0TransTypeReg,
+  endP1TransTypeReg,
+  endP2TransTypeReg,
+  endP3TransTypeReg,
+  endP0NAKTransTypeReg,
+  endP1NAKTransTypeReg,
+  endP2NAKTransTypeReg,
+  endP3NAKTransTypeReg,
+  clrEP0Rdy,
+  clrEP1Rdy,
+  clrEP2Rdy,
+  clrEP3Rdy);
+
+
+input clk; 
+input rst;
+input [3:0] currEndP;
+input NAKSent;
+input stallSent;
+input CRCError;
+input bitStuffError;
+input RxOverflow;
+input RxTimeOut;
+input dataSequence;
+input ACKRxed;
+input [1:0] transType;
+input [1:0] transTypeNAK;
+output [4:0] endPControlReg;
+input clrEPRdy;
+input endPMuxErrorsWEn;
+input [4:0] endP0ControlReg;
+input [4:0] endP1ControlReg;
+input [4:0] endP2ControlReg;
+input [4:0] endP3ControlReg;
+output [7:0] endP0StatusReg;
+output [7:0] endP1StatusReg;
+output [7:0] endP2StatusReg;
+output [7:0] endP3StatusReg;
+output [1:0] endP0TransTypeReg;
+output [1:0] endP1TransTypeReg;
+output [1:0] endP2TransTypeReg;
+output [1:0] endP3TransTypeReg;
+output [1:0] endP0NAKTransTypeReg;
+output [1:0] endP1NAKTransTypeReg;
+output [1:0] endP2NAKTransTypeReg;
+output [1:0] endP3NAKTransTypeReg;
+output clrEP0Rdy;
+output clrEP1Rdy;
+output clrEP2Rdy;
+output clrEP3Rdy;
+
+wire clk; 
+wire rst;
+wire [3:0] currEndP;
+wire NAKSent;
+wire stallSent;
+wire CRCError;
+wire bitStuffError;
+wire RxOverflow;
+wire RxTimeOut;
+wire dataSequence;
+wire ACKRxed;
+wire [1:0] transType;
+wire [1:0] transTypeNAK;
+reg [4:0] endPControlReg;
+wire clrEPRdy;
+wire endPMuxErrorsWEn;
+wire [4:0] endP0ControlReg;
+wire [4:0] endP1ControlReg;
+wire [4:0] endP2ControlReg;
+wire [4:0] endP3ControlReg;
+reg [7:0] endP0StatusReg;
+reg [7:0] endP1StatusReg;
+reg [7:0] endP2StatusReg;
+reg [7:0] endP3StatusReg;
+reg [1:0] endP0TransTypeReg;
+reg [1:0] endP1TransTypeReg;
+reg [1:0] endP2TransTypeReg;
+reg [1:0] endP3TransTypeReg;
+reg [1:0] endP0NAKTransTypeReg;
+reg [1:0] endP1NAKTransTypeReg;
+reg [1:0] endP2NAKTransTypeReg;
+reg [1:0] endP3NAKTransTypeReg;
+reg clrEP0Rdy;
+reg clrEP1Rdy;
+reg clrEP2Rdy;
+reg clrEP3Rdy;
+
+//internal wires and regs
+reg [7:0] endPStatusCombine;
+
+//mux endPControlReg and clrEPRdy
+always @(posedge clk)
+begin
+  case (currEndP[1:0])
+    2'b00: begin
+      endPControlReg <= endP0ControlReg;
+      clrEP0Rdy <= clrEPRdy;
+    end
+    2'b01: begin
+      endPControlReg <= endP1ControlReg;
+      clrEP1Rdy <= clrEPRdy;
+    end
+    2'b10: begin
+      endPControlReg <= endP2ControlReg;
+      clrEP2Rdy <= clrEPRdy;
+    end
+    2'b11: begin
+      endPControlReg <= endP3ControlReg;
+      clrEP3Rdy <= clrEPRdy;
+    end
+  endcase  
+end      
+
+//mux endPNAKTransType, endPTransType, endPStatusReg
+//If there was a NAK sent then set the NAKSent bit, and leave the other status reg bits untouched.
+//else update the entire status reg
+always @(posedge clk)
+begin
+  if (rst) begin
+    endP0NAKTransTypeReg <= 2'b00;
+    endP1NAKTransTypeReg <= 2'b00;
+    endP2NAKTransTypeReg <= 2'b00;
+    endP3NAKTransTypeReg <= 2'b00;
+    endP0TransTypeReg <= 2'b00;
+    endP1TransTypeReg <= 2'b00;
+    endP2TransTypeReg <= 2'b00;
+    endP3TransTypeReg <= 2'b00;
+    endP0StatusReg <= 4'h0;
+    endP1StatusReg <= 4'h0;
+    endP2StatusReg <= 4'h0;
+    endP3StatusReg <= 4'h0;
+  end
+  else begin
+    if (endPMuxErrorsWEn == 1'b1) begin
+      if (NAKSent == 1'b1) begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0NAKTransTypeReg <= transTypeNAK;
+            endP0StatusReg <= endP0StatusReg | `NAK_SET_MASK; 
+          end
+          2'b01: begin
+            endP1NAKTransTypeReg <= transTypeNAK;
+            endP1StatusReg <= endP1StatusReg | `NAK_SET_MASK; 
+          end
+          2'b10: begin
+            endP2NAKTransTypeReg <= transTypeNAK;
+            endP2StatusReg <= endP2StatusReg | `NAK_SET_MASK; 
+          end
+          2'b11: begin
+            endP3NAKTransTypeReg <= transTypeNAK;
+            endP3StatusReg <= endP3StatusReg | `NAK_SET_MASK; 
+          end
+        endcase
+      end
+      else begin
+        case (currEndP[1:0])
+          2'b00: begin
+            endP0TransTypeReg <= transType;
+            endP0StatusReg <= endPStatusCombine; 
+          end
+          2'b01: begin
+            endP1TransTypeReg <= transType;
+            endP1StatusReg <= endPStatusCombine; 
+          end
+          2'b10: begin
+            endP2TransTypeReg <= transType;
+            endP2StatusReg <= endPStatusCombine; 
+          end
+          2'b11: begin
+            endP3TransTypeReg <= transType;
+            endP3StatusReg <= endPStatusCombine; 
+          end
+        endcase
+      end
+    end
+  end
+end
+        
+
+//combine status bits into a single word
+always @(dataSequence or ACKRxed or stallSent or RxTimeOut or RxOverflow or bitStuffError or CRCError)
+begin
+  endPStatusCombine <= {dataSequence, ACKRxed, stallSent, 1'b0, RxTimeOut, RxOverflow, bitStuffError, CRCError};
+end
+
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/lineControlUpdate.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/lineControlUpdate.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/lineControlUpdate.v	(revision 264)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// lineControlUpdate.v                                          ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+module lineControlUpdate(fullSpeedPolarity, fullSpeedBitRate, JBit, KBit);
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+output [1:0] JBit;
+output [1:0] KBit;
+
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+reg [1:0] JBit;
+reg [1:0] KBit;
+
+
+
+always @(fullSpeedPolarity)
+begin
+    if (fullSpeedPolarity == 1'b1)
+  begin
+      JBit = `ONE_ZERO;
+      KBit = `ZERO_ONE;
+    end
+    else
+  begin
+      JBit = `ZERO_ONE;
+      KBit = `ONE_ZERO;
+    end
+end
+
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processTxByte.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processTxByte.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processTxByte.v	(revision 264)
@@ -0,0 +1,448 @@
+
+// File        : ../RTL/serialInterfaceEngine/processTxByte.v
+// Generated   : 11/10/06 05:37:23
+// From        : ../RTL/serialInterfaceEngine/processTxByte.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processTxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
+input   [1:0] JBit;
+input   [1:0] KBit;
+input   [7:0] TxByteCtrlIn;
+input   TxByteFullSpeedRateIn;
+input   [7:0] TxByteIn;
+input   USBWireGnt;
+input   USBWireRdy;
+input   clk;
+input   processTxByteWEn;
+input   rst;
+output  USBWireCtrl;
+output  [1:0] USBWireData;
+output  USBWireFullSpeedRate;
+output  USBWireReq;
+output  USBWireWEn;
+output  processTxByteRdy;
+
+wire    [1:0] JBit;
+wire    [1:0] KBit;
+wire    [7:0] TxByteCtrlIn;
+wire    TxByteFullSpeedRateIn;
+wire    [7:0] TxByteIn;
+reg     USBWireCtrl, next_USBWireCtrl;
+reg     [1:0] USBWireData, next_USBWireData;
+reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
+wire    USBWireGnt;
+wire    USBWireRdy;
+reg     USBWireReq, next_USBWireReq;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+reg     processTxByteRdy, next_processTxByteRdy;
+wire    processTxByteWEn;
+wire    rst;
+
+// diagram signals declarations
+reg  [1:0]TXLineState, next_TXLineState;
+reg  [3:0]TXOneCount, next_TXOneCount;
+reg  [7:0]TxByteCtrl, next_TxByteCtrl;
+reg  TxByteFullSpeedRate, next_TxByteFullSpeedRate;
+reg  [7:0]TxByte, next_TxByte;
+reg  [3:0]i, next_i;
+
+// BINARY ENCODED state machine: prcTxB
+// State codes definitions:
+`define START_PTBY 5'b00000
+`define PTBY_WAIT_EN 5'b00001
+`define SEND_BYTE_UPDATE_BYTE 5'b00010
+`define SEND_BYTE_WAIT_RDY 5'b00011
+`define SEND_BYTE_CHK 5'b00100
+`define SEND_BYTE_BIT_STUFF 5'b00101
+`define SEND_BYTE_WAIT_RDY2 5'b00110
+`define SEND_BYTE_CHK_FIN 5'b00111
+`define PTBY_WAIT_GNT 5'b01000
+`define STOP_SND_SE0_2 5'b01001
+`define STOP_SND_SE0_1 5'b01010
+`define STOP_CHK 5'b01011
+`define STOP_SND_J 5'b01100
+`define STOP_SND_IDLE 5'b01101
+`define STOP_FIN 5'b01110
+`define WAIT_RDY_WIRE 5'b01111
+`define WAIT_RDY_PKT 5'b10000
+`define LS_START_SND_IDLE3 5'b10001
+`define LS_START_SND_J1 5'b10010
+`define LS_START_SND_IDLE1 5'b10011
+`define LS_START_SND_IDLE2 5'b10100
+`define LS_START_FIN 5'b10101
+`define LS_START_W_RDY1 5'b10110
+`define LS_START_W_RDY2 5'b10111
+`define LS_START_W_RDY3 5'b11000
+`define STOP_W_RDY1 5'b11001
+`define STOP_W_RDY2 5'b11010
+`define STOP_W_RDY3 5'b11011
+`define STOP_W_RDY4 5'b11100
+
+reg [4:0] CurrState_prcTxB;
+reg [4:0] NextState_prcTxB;
+
+
+//--------------------------------------------------------------------
+// Machine: prcTxB
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB)
+begin : prcTxB_NextState
+  NextState_prcTxB <= CurrState_prcTxB;
+  // Set default values for outputs and signals
+  next_processTxByteRdy <= processTxByteRdy;
+  next_USBWireData <= USBWireData;
+  next_USBWireCtrl <= USBWireCtrl;
+  next_USBWireReq <= USBWireReq;
+  next_USBWireWEn <= USBWireWEn;
+  next_i <= i;
+  next_TxByte <= TxByte;
+  next_TxByteCtrl <= TxByteCtrl;
+  next_TXLineState <= TXLineState;
+  next_TXOneCount <= TXOneCount;
+  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
+  next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
+  case (CurrState_prcTxB)
+    `START_PTBY:
+    begin
+      next_processTxByteRdy <= 1'b0;
+      next_USBWireData <= 2'b00;
+      next_USBWireCtrl <= `TRI_STATE;
+      next_USBWireReq <= 1'b0;
+      next_USBWireWEn <= 1'b0;
+      next_i <= 4'h0;
+      next_TxByte <= 8'h00;
+      next_TxByteCtrl <= 8'h00;
+      next_TXLineState <= 2'b0;
+      next_TXOneCount <= 4'h0;
+      next_USBWireFullSpeedRate <= 1'b0;
+      next_TxByteFullSpeedRate <= 1'b0;
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `PTBY_WAIT_EN:
+    begin
+      next_processTxByteRdy <= 1'b1;
+      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))	
+      begin
+        NextState_prcTxB <= `PTBY_WAIT_GNT;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_TXOneCount <= 4'h0;
+        next_TXLineState <= JBit;
+        next_USBWireReq <= 1'b1;
+      end
+      else if (processTxByteWEn == 1'b1)	
+      begin
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+        next_processTxByteRdy <= 1'b0;
+        next_TxByte <= TxByteIn;
+        next_TxByteCtrl <= TxByteCtrlIn;
+        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
+        next_i <= 4'h0;
+      end
+    end
+    `PTBY_WAIT_GNT:
+      if (USBWireGnt == 1'b1)	
+        NextState_prcTxB <= `WAIT_RDY_WIRE;
+    `WAIT_RDY_WIRE:
+      if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate  == 1'b0))	
+        NextState_prcTxB <= `LS_START_SND_IDLE1;
+      else if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `WAIT_RDY_PKT;
+        //actively drive the first J bit
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+        next_USBWireWEn <= 1'b1;
+      end
+    `WAIT_RDY_PKT:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `SEND_BYTE_UPDATE_BYTE:
+    begin
+      next_i <= i + 1'b1;
+      next_TxByte <= {1'b0, TxByte[7:1] };
+      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
+        next_TXOneCount <= TXOneCount + 1'b1;
+          //increment 'TXOneCount'
+      else                                        //else this is a zero bit
+      begin
+        next_TXOneCount <= 4'h0;
+          //reset 'TXOneCount'
+          if (TXLineState == JBit)
+          next_TXLineState <= KBit;
+              //toggle the line state
+          else
+          next_TXLineState <= JBit;
+      end
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
+    end
+    `SEND_BYTE_WAIT_RDY:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `SEND_BYTE_CHK:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (TXOneCount == `MAX_CONSEC_SAME_BITS)	
+        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
+      else if (i != 4'h8)	
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      else
+        NextState_prcTxB <= `STOP_CHK;
+    end
+    `SEND_BYTE_BIT_STUFF:
+    begin
+      next_TXOneCount <= 4'h0;
+      //reset 'TXOneCount'
+      if (TXLineState == JBit)
+        next_TXLineState <= KBit;
+          //toggle the line state
+      else
+        next_TXLineState <= JBit;
+      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
+    end
+    `SEND_BYTE_WAIT_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= TXLineState;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `SEND_BYTE_CHK_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      if (i == 4'h8)	
+        NextState_prcTxB <= `STOP_CHK;
+      else
+        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+    end
+    `STOP_SND_SE0_2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY2;
+    end
+    `STOP_SND_SE0_1:
+      NextState_prcTxB <= `STOP_W_RDY1;
+    `STOP_CHK:
+      if (TxByteCtrl == `DATA_STOP)	
+        NextState_prcTxB <= `STOP_SND_SE0_1;
+      else
+        NextState_prcTxB <= `PTBY_WAIT_EN;
+    `STOP_SND_J:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY3;
+    end
+    `STOP_SND_IDLE:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `STOP_W_RDY4;
+    end
+    `STOP_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      next_USBWireReq <= 1'b0;
+      //release the wire
+      NextState_prcTxB <= `PTBY_WAIT_EN;
+    end
+    `STOP_W_RDY1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `STOP_SND_SE0_2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `STOP_W_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `STOP_SND_J;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= `SE0;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `STOP_W_RDY3:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `STOP_SND_IDLE;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+    `STOP_W_RDY4:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `STOP_FIN;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    `LS_START_SND_IDLE3:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY2;
+    end
+    `LS_START_SND_J1:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY3;
+    end
+    `LS_START_SND_IDLE1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE2;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    `LS_START_SND_IDLE2:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `LS_START_W_RDY1;
+    end
+    `LS_START_FIN:
+    begin
+      next_USBWireWEn <= 1'b0;
+      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
+      next_i <= 4'h0;
+    end
+    `LS_START_W_RDY1:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `LS_START_SND_IDLE3;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    `LS_START_W_RDY2:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `LS_START_SND_J1;
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `TRI_STATE;
+      end
+    `LS_START_W_RDY3:
+      if (USBWireRdy == 1'b1)	
+      begin
+        NextState_prcTxB <= `LS_START_FIN;
+        //Drive the first JBit
+        next_USBWireWEn <= 1'b1;
+        next_USBWireData <= JBit;
+        next_USBWireCtrl <= `DRIVE;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prcTxB_CurrentState
+  if (rst)	
+    CurrState_prcTxB <= `START_PTBY;
+  else
+    CurrState_prcTxB <= NextState_prcTxB;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prcTxB_RegOutput
+  if (rst)	
+  begin
+    i <= 4'h0;
+    TxByte <= 8'h00;
+    TxByteCtrl <= 8'h00;
+    TXLineState <= 2'b0;
+    TXOneCount <= 4'h0;
+    TxByteFullSpeedRate <= 1'b0;
+    processTxByteRdy <= 1'b0;
+    USBWireData <= 2'b00;
+    USBWireCtrl <= `TRI_STATE;
+    USBWireReq <= 1'b0;
+    USBWireWEn <= 1'b0;
+    USBWireFullSpeedRate <= 1'b0;
+  end
+  else 
+  begin
+    i <= next_i;
+    TxByte <= next_TxByte;
+    TxByteCtrl <= next_TxByteCtrl;
+    TXLineState <= next_TXLineState;
+    TXOneCount <= next_TXOneCount;
+    TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
+    processTxByteRdy <= next_processTxByteRdy;
+    USBWireData <= next_USBWireData;
+    USBWireCtrl <= next_USBWireCtrl;
+    USBWireReq <= next_USBWireReq;
+    USBWireWEn <= next_USBWireWEn;
+    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveDirectcontrol.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveDirectcontrol.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveDirectcontrol.v	(revision 264)
@@ -0,0 +1,197 @@
+
+// File        : ../RTL/slaveController/slaveDirectcontrol.v
+// Generated   : 11/10/06 05:37:25
+// From        : ../RTL/slaveController/slaveDirectcontrol.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveDirectControl
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+module slaveDirectControl (SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, directControlEn, directControlLineState, rst);
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   clk;
+input   directControlEn;
+input   [1:0] directControlLineState;
+input   rst;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+wire    clk;
+wire    directControlEn;
+wire    [1:0] directControlLineState;
+wire    rst;
+
+// BINARY ENCODED state machine: slvDrctCntl
+// State codes definitions:
+`define START_SDC 3'b000
+`define CHK_DRCT_CNTL 3'b001
+`define DRCT_CNTL_WAIT_GNT 3'b010
+`define DRCT_CNTL_CHK_LOOP 3'b011
+`define DRCT_CNTL_WAIT_RDY 3'b100
+`define IDLE_FIN 3'b101
+`define IDLE_WAIT_GNT 3'b110
+`define IDLE_WAIT_RDY 3'b111
+
+reg [2:0] CurrState_slvDrctCntl;
+reg [2:0] NextState_slvDrctCntl;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// diagram ACTION
+
+//--------------------------------------------------------------------
+// Machine: slvDrctCntl
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (directControlLineState or directControlEn or SCTxPortGnt or SCTxPortRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or CurrState_slvDrctCntl)
+begin : slvDrctCntl_NextState
+  NextState_slvDrctCntl <= CurrState_slvDrctCntl;
+  // Set default values for outputs and signals
+  next_SCTxPortReq <= SCTxPortReq;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortCntl <= SCTxPortCntl;
+  case (CurrState_slvDrctCntl)
+    `START_SDC:
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    `CHK_DRCT_CNTL:
+      if (directControlEn == 1'b1)	
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvDrctCntl <= `IDLE_WAIT_GNT;
+        next_SCTxPortReq <= 1'b1;
+      end
+    `DRCT_CNTL_WAIT_GNT:
+      if (SCTxPortGnt == 1'b1)	
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+    `DRCT_CNTL_CHK_LOOP:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (directControlEn == 1'b0)	
+      begin
+        NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+        next_SCTxPortReq <= 1'b0;
+      end
+      else
+        NextState_slvDrctCntl <= `DRCT_CNTL_WAIT_RDY;
+    end
+    `DRCT_CNTL_WAIT_RDY:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvDrctCntl <= `DRCT_CNTL_CHK_LOOP;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= {6'b000000, directControlLineState};
+        next_SCTxPortCntl <= `TX_DIRECT_CONTROL;
+      end
+    `IDLE_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      next_SCTxPortReq <= 1'b0;
+      NextState_slvDrctCntl <= `CHK_DRCT_CNTL;
+    end
+    `IDLE_WAIT_GNT:
+      if (SCTxPortGnt == 1'b1)	
+        NextState_slvDrctCntl <= `IDLE_WAIT_RDY;
+    `IDLE_WAIT_RDY:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvDrctCntl <= `IDLE_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_IDLE;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_CurrentState
+  if (rst)	
+    CurrState_slvDrctCntl <= `START_SDC;
+  else
+    CurrState_slvDrctCntl <= NextState_slvDrctCntl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvDrctCntl_RegOutput
+  if (rst)	
+  begin
+    SCTxPortCntl <= 8'h00;
+    SCTxPortData <= 8'h00;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortReq <= 1'b0;
+  end
+  else 
+  begin
+    SCTxPortCntl <= next_SCTxPortCntl;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortReq <= next_SCTxPortReq;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slavecontroller.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slavecontroller.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slavecontroller.v	(revision 264)
@@ -0,0 +1,475 @@
+
+// File        : ../RTL/slaveController/slavecontroller.v
+// Generated   : 11/10/06 05:37:25
+// From        : ../RTL/slaveController/slavecontroller.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveController
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbSlaveControl_h.v"
+`include "usbConstants_h.v"
+
+
+module slavecontroller (CRCError, NAKSent, RxByte, RxDataWEn, RxOverflow, RxStatus, RxTimeOut, SCGlobalEn, SOFRxed, USBEndPControlReg, USBEndPNakTransTypeReg, USBEndPTransTypeReg, USBEndP, USBTgtAddress, bitStuffError, clk, clrEPRdy, endPMuxErrorsWEn, endPointReadyToGetPkt, frameNum, getPacketREn, getPacketRdy, rst, sendPacketPID, sendPacketRdy, sendPacketWEn, stallSent, transDone);
+input   CRCError;
+input   [7:0] RxByte;
+input   RxDataWEn;
+input   RxOverflow;
+input   [7:0] RxStatus;
+input   RxTimeOut;
+input   SCGlobalEn;
+input   [4:0] USBEndPControlReg;
+input   [6:0] USBTgtAddress;
+input   bitStuffError;
+input   clk;
+input   getPacketRdy;
+input   rst;
+input   sendPacketRdy;
+output  NAKSent;
+output  SOFRxed;
+output  [1:0] USBEndPNakTransTypeReg;
+output  [1:0] USBEndPTransTypeReg;
+output  [3:0] USBEndP;
+output  clrEPRdy;
+output  endPMuxErrorsWEn;
+output  endPointReadyToGetPkt;
+output  [10:0] frameNum;
+output  getPacketREn;
+output  [3:0] sendPacketPID;
+output  sendPacketWEn;
+output  stallSent;
+output  transDone;
+
+wire    CRCError;
+reg     NAKSent, next_NAKSent;
+wire    [7:0] RxByte;
+wire    RxDataWEn;
+wire    RxOverflow;
+wire    [7:0] RxStatus;
+wire    RxTimeOut;
+wire    SCGlobalEn;
+reg     SOFRxed, next_SOFRxed;
+wire    [4:0] USBEndPControlReg;
+reg     [1:0] USBEndPNakTransTypeReg, next_USBEndPNakTransTypeReg;
+reg     [1:0] USBEndPTransTypeReg, next_USBEndPTransTypeReg;
+reg     [3:0] USBEndP, next_USBEndP;
+wire    [6:0] USBTgtAddress;
+wire    bitStuffError;
+wire    clk;
+reg     clrEPRdy, next_clrEPRdy;
+reg     endPMuxErrorsWEn, next_endPMuxErrorsWEn;
+reg     endPointReadyToGetPkt, next_endPointReadyToGetPkt;
+reg     [10:0] frameNum, next_frameNum;
+reg     getPacketREn, next_getPacketREn;
+wire    getPacketRdy;
+wire    rst;
+reg     [3:0] sendPacketPID, next_sendPacketPID;
+wire    sendPacketRdy;
+reg     sendPacketWEn, next_sendPacketWEn;
+reg     stallSent, next_stallSent;
+reg     transDone, next_transDone;
+
+// diagram signals declarations
+reg  [7:0]PIDByte, next_PIDByte;
+reg  [6:0]USBAddress, next_USBAddress;
+reg  [4:0]USBEndPControlRegCopy, next_USBEndPControlRegCopy;
+reg  [7:0]addrEndPTemp, next_addrEndPTemp;
+reg  [7:0]endpCRCTemp, next_endpCRCTemp;
+reg  [1:0]tempUSBEndPTransTypeReg, next_tempUSBEndPTransTypeReg;
+
+// BINARY ENCODED state machine: slvCntrl
+// State codes definitions:
+`define WAIT_RX1 5'b00000
+`define FIN_SC 5'b00001
+`define GET_TOKEN_WAIT_CRC 5'b00010
+`define GET_TOKEN_WAIT_ADDR 5'b00011
+`define GET_TOKEN_WAIT_STOP 5'b00100
+`define CHK_PID 5'b00101
+`define GET_TOKEN_CHK_SOF 5'b00110
+`define PID_ERROR 5'b00111
+`define CHK_RDY 5'b01000
+`define IN_NAK_STALL 5'b01001
+`define IN_CHK_RDY 5'b01010
+`define SETUP_OUT_CHK 5'b01011
+`define SETUP_OUT_SEND 5'b01100
+`define SETUP_OUT_GET_PKT 5'b01101
+`define START_S1 5'b01110
+`define GET_TOKEN_DELAY 5'b01111
+`define GET_TOKEN_CHK_ADDR 5'b10000
+`define IN_RESP_GET_RESP 5'b10001
+`define IN_RESP_DATA 5'b10010
+`define IN_RESP_CHK_ISO 5'b10011
+
+reg [4:0] CurrState_slvCntrl;
+reg [4:0] NextState_slvCntrl;
+
+
+//--------------------------------------------------------------------
+// Machine: slvCntrl
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RxByte or tempUSBEndPTransTypeReg or endpCRCTemp or addrEndPTemp or USBEndPControlReg or RxDataWEn or RxStatus or PIDByte or USBEndPControlRegCopy or NAKSent or sendPacketRdy or getPacketRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or USBEndP or USBAddress or USBTgtAddress or SCGlobalEn or stallSent or SOFRxed or transDone or clrEPRdy or endPMuxErrorsWEn or getPacketREn or sendPacketWEn or sendPacketPID or USBEndPTransTypeReg or USBEndPNakTransTypeReg or frameNum or endPointReadyToGetPkt or CurrState_slvCntrl)
+begin : slvCntrl_NextState
+  NextState_slvCntrl <= CurrState_slvCntrl;
+  // Set default values for outputs and signals
+  next_stallSent <= stallSent;
+  next_NAKSent <= NAKSent;
+  next_SOFRxed <= SOFRxed;
+  next_PIDByte <= PIDByte;
+  next_transDone <= transDone;
+  next_clrEPRdy <= clrEPRdy;
+  next_endPMuxErrorsWEn <= endPMuxErrorsWEn;
+  next_tempUSBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+  next_getPacketREn <= getPacketREn;
+  next_sendPacketWEn <= sendPacketWEn;
+  next_sendPacketPID <= sendPacketPID;
+  next_USBEndPTransTypeReg <= USBEndPTransTypeReg;
+  next_USBEndPNakTransTypeReg <= USBEndPNakTransTypeReg;
+  next_endpCRCTemp <= endpCRCTemp;
+  next_addrEndPTemp <= addrEndPTemp;
+  next_frameNum <= frameNum;
+  next_USBAddress <= USBAddress;
+  next_USBEndP <= USBEndP;
+  next_USBEndPControlRegCopy <= USBEndPControlRegCopy;
+  next_endPointReadyToGetPkt <= endPointReadyToGetPkt;
+  case (CurrState_slvCntrl)
+    `WAIT_RX1:
+    begin
+      next_stallSent <= 1'b0;
+      next_NAKSent <= 1'b0;
+      next_SOFRxed <= 1'b0;
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_START && 
+        RxByte[1:0] == `TOKEN)	
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_ADDR;
+        next_PIDByte <= RxByte;
+      end
+    end
+    `FIN_SC:
+    begin
+      next_transDone <= 1'b0;
+      next_clrEPRdy <= 1'b0;
+      next_endPMuxErrorsWEn <= 1'b0;
+      NextState_slvCntrl <= `WAIT_RX1;
+    end
+    `CHK_PID:
+      if (PIDByte[3:0] == `SETUP)	
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_SETUP_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if (PIDByte[3:0] == `OUT)	
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_GET_PKT;
+        next_tempUSBEndPTransTypeReg <= `SC_OUTDATA_TRANS;
+        next_getPacketREn <= 1'b1;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy[`ENDPOINT_ISO_ENABLE_BIT] == 1'b0))	
+      begin
+        NextState_slvCntrl <= `IN_CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else if (((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)) && (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0))	
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else if ((PIDByte[3:0] == `IN) && (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1))	
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+      else if (PIDByte[3:0] == `IN)	
+      begin
+        NextState_slvCntrl <= `CHK_RDY;
+        next_tempUSBEndPTransTypeReg <= `SC_IN_TRANS;
+      end
+      else
+        NextState_slvCntrl <= `PID_ERROR;
+    `PID_ERROR:
+      NextState_slvCntrl <= `WAIT_RX1;
+    `CHK_RDY:
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b1)	
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_transDone <= 1'b1;
+        next_clrEPRdy <= 1'b1;
+        next_USBEndPTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else if (NAKSent == 1'b1)	
+      begin
+        NextState_slvCntrl <= `FIN_SC;
+        next_USBEndPNakTransTypeReg <= tempUSBEndPTransTypeReg;
+        next_endPMuxErrorsWEn <= 1'b1;
+      end
+      else
+        NextState_slvCntrl <= `FIN_SC;
+    `SETUP_OUT_CHK:
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)	
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)	
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `SETUP_OUT_SEND;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `ACK;
+      end
+    `SETUP_OUT_SEND:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+    end
+    `SETUP_OUT_GET_PKT:
+    begin
+      next_getPacketREn <= 1'b0;
+      if ((getPacketRdy == 1'b1) && (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1))	
+        NextState_slvCntrl <= `CHK_RDY;
+      else if ((getPacketRdy == 1'b1) && (CRCError == 1'b0 &&
+        bitStuffError == 1'b0 && 
+        RxOverflow == 1'b0 && 
+        RxTimeOut == 1'b0))	
+        NextState_slvCntrl <= `SETUP_OUT_CHK;
+      else if (getPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+    end
+    `IN_NAK_STALL:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+    end
+    `IN_CHK_RDY:
+      if (USBEndPControlRegCopy [`ENDPOINT_READY_BIT] == 1'b0)	
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `NAK;
+        next_NAKSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_SEND_STALL_BIT] == 1'b1)	
+      begin
+        NextState_slvCntrl <= `IN_NAK_STALL;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `STALL;
+        next_stallSent <= 1'b1;
+      end
+      else if (USBEndPControlRegCopy [`ENDPOINT_OUTDATA_SEQUENCE_BIT] == 1'b0)	
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA0;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_DATA;
+        next_sendPacketWEn <= 1'b1;
+        next_sendPacketPID <= `DATA1;
+      end
+    `IN_RESP_GET_RESP:
+    begin
+      next_getPacketREn <= 1'b0;
+      if (getPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+    end
+    `IN_RESP_DATA:
+    begin
+      next_sendPacketWEn <= 1'b0;
+      if (sendPacketRdy == 1'b1)	
+        NextState_slvCntrl <= `IN_RESP_CHK_ISO;
+    end
+    `IN_RESP_CHK_ISO:
+      if (USBEndPControlRegCopy [`ENDPOINT_ISO_ENABLE_BIT] == 1'b1)	
+        NextState_slvCntrl <= `CHK_RDY;
+      else
+      begin
+        NextState_slvCntrl <= `IN_RESP_GET_RESP;
+        next_getPacketREn <= 1'b1;
+      end
+    `START_S1:
+      NextState_slvCntrl <= `WAIT_RX1;
+    `GET_TOKEN_WAIT_CRC:
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_STOP;
+        next_endpCRCTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)	
+        NextState_slvCntrl <= `WAIT_RX1;
+    `GET_TOKEN_WAIT_ADDR:
+      if (RxDataWEn == 1'b1 && 
+        RxStatus == `RX_PACKET_STREAM)	
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_WAIT_CRC;
+        next_addrEndPTemp <= RxByte;
+      end
+      else if (RxDataWEn == 1'b1 && 
+        RxStatus != `RX_PACKET_STREAM)	
+        NextState_slvCntrl <= `WAIT_RX1;
+    `GET_TOKEN_WAIT_STOP:
+      if ((RxDataWEn == 1'b1) && (RxByte[`CRC_ERROR_BIT] == 1'b0 &&
+        RxByte[`BIT_STUFF_ERROR_BIT] == 1'b0 &&
+        RxByte [`RX_OVERFLOW_BIT] == 1'b0))	
+        NextState_slvCntrl <= `GET_TOKEN_CHK_SOF;
+      else if (RxDataWEn == 1'b1)	
+        NextState_slvCntrl <= `WAIT_RX1;
+    `GET_TOKEN_CHK_SOF:
+      if (PIDByte[3:0] == `SOF)	
+      begin
+        NextState_slvCntrl <= `WAIT_RX1;
+        next_frameNum <= {endpCRCTemp[2:0],addrEndPTemp};
+        next_SOFRxed <= 1'b1;
+      end
+      else
+      begin
+        NextState_slvCntrl <= `GET_TOKEN_DELAY;
+        next_USBAddress <= addrEndPTemp[6:0];
+        next_USBEndP <= { endpCRCTemp[2:0], addrEndPTemp[7]};
+      end
+    `GET_TOKEN_DELAY:    // Insert delay to allow USBEndP etc to update
+      NextState_slvCntrl <= `GET_TOKEN_CHK_ADDR;
+    `GET_TOKEN_CHK_ADDR:
+      if (USBEndP < `NUM_OF_ENDPOINTS  &&
+        USBAddress == USBTgtAddress &&
+        SCGlobalEn == 1'b1 &&
+        USBEndPControlReg[`ENDPOINT_ENABLE_BIT] == 1'b1)	
+      begin
+        NextState_slvCntrl <= `CHK_PID;
+        next_USBEndPControlRegCopy <= USBEndPControlReg;
+        next_endPointReadyToGetPkt <= USBEndPControlReg [`ENDPOINT_READY_BIT];
+      end
+      else
+        NextState_slvCntrl <= `WAIT_RX1;
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_CurrentState
+  if (rst)	
+    CurrState_slvCntrl <= `START_S1;
+  else
+    CurrState_slvCntrl <= NextState_slvCntrl;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvCntrl_RegOutput
+  if (rst)	
+  begin
+    tempUSBEndPTransTypeReg <= 2'b00;
+    addrEndPTemp <= 8'h00;
+    endpCRCTemp <= 8'h00;
+    USBAddress <= 7'b0000000;
+    PIDByte <= 8'h00;
+    USBEndPControlRegCopy <= 5'b00000;
+    transDone <= 1'b0;
+    getPacketREn <= 1'b0;
+    sendPacketPID <= 4'b0;
+    sendPacketWEn <= 1'b0;
+    clrEPRdy <= 1'b0;
+    USBEndPTransTypeReg <= 2'b00;
+    USBEndPNakTransTypeReg <= 2'b00;
+    NAKSent <= 1'b0;
+    stallSent <= 1'b0;
+    SOFRxed <= 1'b0;
+    endPMuxErrorsWEn <= 1'b0;
+    frameNum <= 11'b00000000000;
+    USBEndP <= 4'h0;
+    endPointReadyToGetPkt <= 1'b0;
+  end
+  else 
+  begin
+    tempUSBEndPTransTypeReg <= next_tempUSBEndPTransTypeReg;
+    addrEndPTemp <= next_addrEndPTemp;
+    endpCRCTemp <= next_endpCRCTemp;
+    USBAddress <= next_USBAddress;
+    PIDByte <= next_PIDByte;
+    USBEndPControlRegCopy <= next_USBEndPControlRegCopy;
+    transDone <= next_transDone;
+    getPacketREn <= next_getPacketREn;
+    sendPacketPID <= next_sendPacketPID;
+    sendPacketWEn <= next_sendPacketWEn;
+    clrEPRdy <= next_clrEPRdy;
+    USBEndPTransTypeReg <= next_USBEndPTransTypeReg;
+    USBEndPNakTransTypeReg <= next_USBEndPNakTransTypeReg;
+    NAKSent <= next_NAKSent;
+    stallSent <= next_stallSent;
+    SOFRxed <= next_SOFRxed;
+    endPMuxErrorsWEn <= next_endPMuxErrorsWEn;
+    frameNum <= next_frameNum;
+    USBEndP <= next_USBEndP;
+    endPointReadyToGetPkt <= next_endPointReadyToGetPkt;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbConstants_h.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbConstants_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbConstants_h.v	(revision 264)
@@ -0,0 +1,32 @@
+//////////////////////////////////////////////////////////////////////
+//// usbConstants_h.v                                             
+///////////////////////////////////////////////////////////////////////
+
+`ifdef usbConstants_h_vdefined
+`else
+`define usbConstants_h_vdefined
+
+//PIDTypes
+`define OUT 4'h1
+`define IN 4'h9
+`define SOF 4'h5
+`define SETUP 4'hd
+`define DATA0 4'h3
+`define DATA1 4'hb
+`define ACK 4'h2
+`define NAK 4'ha
+`define STALL 4'he
+`define PREAMBLE 4'hc 
+     
+
+//PIDGroups
+`define SPECIAL 2'b00
+`define TOKEN 2'b01
+`define HANDSHAKE 2'b10
+`define DATA 2'b11
+
+// start of packet SyncByte
+`define SYNC_BYTE 8'h80
+
+`endif //usbConstants_h_vdefined       
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceXilinxTop.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceXilinxTop.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceXilinxTop.v	(revision 264)
@@ -0,0 +1,92 @@
+
+module usbDeviceXilinxTop (
+
+  //
+  // Global signals
+  //
+  clk,
+
+  //
+  // misc Starter Kit control sigs
+  //
+  E_NRST,
+  SPI_SCK,
+  NF_CE,
+  SD_CS,
+
+  //
+  // USB slave
+  //
+  usbSlaveVP,
+  usbSlaveVM,
+  usbSlaveOE_n,
+  usbDPlusPullup
+
+);
+
+  //
+  // Global signals
+  //
+  input	clk;
+
+  //
+  // misc Starter Kit control sigs
+  //
+  output E_NRST;
+  output SPI_SCK;
+  output NF_CE;
+  output SD_CS;
+
+  //
+  // USB slave
+  //
+  inout usbSlaveVP;
+  inout usbSlaveVM;
+  output usbSlaveOE_n;
+  output usbDPlusPullup;
+
+//local wires and regs
+reg [1:0] rstReg;
+wire rst;
+wire pll_locked;
+wire clk48MHz;
+
+
+assign E_NRST = 1'b0;
+assign SPI_SCK = 1'b0;
+assign NF_CE = 1'b0;
+assign SD_CS = 1'b1;
+
+
+pll_48MHz_xilinx	pll_48MHz_inst (
+	.CLKIN_IN ( clk ),
+   .CLK0_OUT (clk48MHz),
+	.LOCKED_OUT( pll_locked)
+	);
+
+//generate sync reset from pll lock signal
+always @(posedge clk48MHz) begin
+  rstReg[1:0] <= {rstReg[0], ~pll_locked};
+end
+assign rst = rstReg[1];
+
+
+usbDevice u_usbDevice (
+  .clk(clk48MHz),
+  .rst(rst),
+  .usbSlaveVP_in(usbSlaveVP_in),
+  .usbSlaveVM_in(usbSlaveVM_in),
+  .usbSlaveVP_out(usbSlaveVP_out),
+  .usbSlaveVM_out(usbSlaveVM_out),
+  .usbSlaveOE_n(usbSlaveOE_n),
+  .usbDPlusPullup(usbDPlusPullup),
+  .vBusDetect(1'b1)
+);
+
+
+assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
+assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
+
+endmodule
+
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlave_h.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlave_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlave_h.v	(revision 264)
@@ -0,0 +1,80 @@
+//////////////////////////////////////////////////////////////////////
+// usbHostSlave_h.v                                              
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbHostSlave_h_vdefined
+`else
+`define usbHostSlave_h_vdefined
+
+// Version 0.6 - Feb 4th 2005. Fixed bit stuffing and de-stuffing. This version succesfully supports 
+//             control reads and writes to USB flash dongle
+// Version 0.7 - Feb 24th 2005. Added support for isochronous transfers, fixed resume, connect and disconnect 
+//             time outs, added low speed EOP keep alive. The TX bit rate is now controlled by 
+//             SIETransmitter, and takes account of the requirement that SOF, and PREAMBLE are always full
+//             speed, and TX resume is always low speed.
+//             Fixed read clock recovery (readUSBWireData.v) issue which was resulting 
+//             in missing receive packets.
+//             Fixed broken SOF Sync mode (where transacations are synchronized with the SOF transmission)
+//             by adding kludged delay to softranmit. This needs to be fixed properly.
+//             This version has undergone limited testing
+//             with full speed flash dongle, low speed keyboard, and a PC in full and low speed modes.
+// Version 0.8 - June 24th 2005. Added bus access to the host SOFTimer. This version has been tested
+//             with uClinux, and is known to work with a full speed USB flash stick.
+//             Moving Opencores project status from Beta to done.
+//             TODO: Test isochronous mode, and low speed mode using uClinux driver
+//                   Create a seperate clock domain for the bus interface
+//                   Add frame period adjustment capability
+//                   Add compilation flags for slave only and host only versions
+//                   Create data bus width options beyond 8-bit
+// Version 1.0 - October 14th 2005. Seperated the bus clock from the usb logic clock
+//             Removed TX and RX fifo status registers, and removed 
+//             TX fifo data count register.
+//             Added RESET_CORE bit to HOST_SLAVE_CONTROL_REG. 
+//             Fixed slave mode bug which caused receive fifo to be filled with 
+//             incoming data when the slave was responding with a NAK, and the 
+//             data should have been discarded.
+// Version 1.1 - February 23rd 2006. Fixed bug related to 'noActivityTimeOut'
+//             Previously the 'noActivityTimeOut' flag was repetitively pulsed whenever
+//             there was no detected activity on the USB data lines. This caused an infrequent
+//             misreporting of time out errors. 'noActivityTimeOut' is now only enabled when
+//             the higher level state machines are actively looking for receive packets. 
+//             Modified USB RX data clock recovery, so that data is sampled during the middle
+//             of a USB bit period. Fixed a bug which could result in double sampling
+//             of USB RX data if clock phase adjustments were required in the middle of a 
+//             USB packet.
+// Version 1.2 - October 1st 2006. Small changes to .asf FSM's required
+//             during migration to ActiveHDL 7.1. Released SystemC test bench.
+//             Re-generated .v files using ActiveHDL 7.1
+//             Replaced individual timescale directives with `include "timescale.v
+//             Renamed top level Altera wrapper from 'usbHostSlaveWrap' to 
+//             'usbHostSlaveAvalonWrap'
+// Version 1.3 - March 22nd 2008. Fixed bug in 'readUSBWireData'. Added
+//             synchronizer to incoming USB wire data to avoid
+//             metastability, and delay hazards. Not entirely sure, but it appears that 
+//             this bug caused more problems with some of the newer low power FPGAs
+//             Maybe because they are more prone to problems with metastable
+//             inputs that feed logic functions causing excessive high speed
+//             toggle activity, and disrupting nearby cicuits.
+// Version 1.4 - June 16th 2008. Added two new top level modules which
+//             allow the instantiation of only host (usbHost.v), or only device
+//             features. Added double sync stages between usbClk, and busClk domains
+//             to fix possible metastability issues. Also modified synchronization to
+//             allow operation with busClk frequency less than usbClk frequency (down to
+//             24MHz). Integrated full support for USB PHY. Prior to this modification
+//             the user would need to instantiate a GPIO module to control USB speed,
+//             D+ and D- pull-up control, and VBUS detect. Fixed bug in BI wb_ack.
+//             Modified cross-clock synchronisation of fifo resets
+//             Added usbDevice, a standalone usb device implementation of usbhostslave
+//             no additional hardware or software required
+
+
+// Most significant nibble corresponds to major revision.
+// Least significant nibble corresponds to minor revision.
+`define USBHOSTSLAVE_VERSION_NUM 8'h14   
+
+//Host slave common registers
+`define HOST_SLAVE_CONTROL_REG 1'b0
+`define HOST_SLAVE_VERSION_REG 1'b1
+
+`endif //usbHostSlave_h_vdefined
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine_h.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine_h.v	(revision 264)
@@ -0,0 +1,108 @@
+//////////////////////////////////////////////////////////////////////
+// usbSerialInterfaceEngine_h.v                                
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSerialInterfaceEngine_h_vdefined
+`else
+`define usbSerialInterfaceEngine_h_vdefined
+
+ // Sampling frequency = 'FS_OVER_SAMPLE_RATE' * full speed bit rate = 'LS_OVER_SAMPLE_RATE' * low speed bit rate
+`define FS_OVER_SAMPLE_RATE 4
+`define LS_OVER_SAMPLE_RATE 32
+
+//timeOuts
+`define RX_PACKET_TOUT 18
+`define RX_EDGE_DET_TOUT 7
+
+//TXStreamControlTypes
+`define TX_DIRECT_CONTROL 8'h00
+`define TX_RESUME_START 8'h01
+`define TX_PACKET_START 8'h02
+`define TX_PACKET_STREAM 8'h03
+`define TX_PACKET_STOP 8'h04
+`define TX_IDLE 8'h05
+`define TX_LS_KEEP_ALIVE 8'h06
+
+//RXStreamControlTypes
+`define RX_PACKET_START 0
+`define RX_PACKET_STREAM 1
+`define RX_PACKET_STOP 2
+
+//USBLineStates
+// ONE_ZERO corresponds to differential 1. ie D+ = Hi, D- = Lo
+`define ONE_ZERO 2'b10
+`define ZERO_ONE 2'b01
+`define SE0 2'b00
+`define SE1 2'b11
+
+//RXStatusIndices
+`define CRC_ERROR_BIT 0
+`define BIT_STUFF_ERROR_BIT 1
+`define RX_OVERFLOW_BIT 2
+`define NAK_RXED_BIT 3
+`define STALL_RXED_BIT 4
+`define ACK_RXED_BIT 5
+`define DATA_SEQUENCE_BIT 6
+
+//usbWireControlStates
+`define TRI_STATE 1'b0
+`define DRIVE 1'b1
+
+//limits
+`define MAX_CONSEC_SAME_BITS 4'h6
+`define MAX_CONSEC_SAME_BITS_PLUS1 4'h7
+// RESUME_RX_WAIT_TIME defines the time period for resume detection
+// The resume counter is incremented at the bit rate, so
+// RESUME_RX_WAIT_TIME = 29 corresponds to 30 * 1/12MHz = 2.5uS at full speed
+// and 30 * 1/1.5MHz =  20uS at low speed, both of which are within the USB spec of 
+// 2.5uS <= resumeDetectTime <= 100uS
+`define RESUME_RX_WAIT_TIME 5'd29
+//`define RESUME_WAIT_TIME_MINUS1 9
+// 'HOST_TX_RESUME_TIME' assumes counter is incremented at low speed bit rate 
+`ifdef SIM_COMPILE 
+`define HOST_TX_RESUME_TIME 16'd10
+`else
+`define HOST_TX_RESUME_TIME 16'd30000  //Host sends resume for 30000 * 1/1.5MHz = 20mS
+`endif
+//`define CONNECT_WAIT_TIME 8'd20
+`define CONNECT_WAIT_TIME 8'd120      //Device connect detected after 120 * 1/48MHz = 2.5uS
+//`define DISCONNECT_WAIT_TIME 8'd20   
+`define DISCONNECT_WAIT_TIME 8'd120   //Device disconnect detected after 120 * 1/48MHz = 2.5uS
+
+//RXConnectStates
+`define DISCONNECT 2'b00
+`define LOW_SPEED_CONNECT 2'b01
+`define FULL_SPEED_CONNECT 2'b10
+
+//TX_RX_InternalStreamTypes
+`define DATA_START 8'h00
+`define DATA_STOP 8'h01
+`define DATA_STREAM 8'h02
+`define DATA_BIT_STUFF_ERROR 8'h03
+
+//RXStMach states
+`define DISCONNECT_ST 4'h0
+`define WAIT_FULL_SPEED_CONN_ST 4'h1
+`define WAIT_LOW_SPEED_CONN_ST 4'h2
+`define CONNECT_LOW_SPEED_ST 4'h3
+`define CONNECT_FULL_SPEED_ST 4'h4
+`define WAIT_LOW_SP_DISCONNECT_ST 4'h5
+`define WAIT_FULL_SP_DISCONNECT_ST 4'h6
+
+//RXBitStateMachStates
+`define IDLE_BIT_ST 2'b00
+`define DATA_RECEIVE_BIT_ST 2'b01
+`define WAIT_RESUME_ST 2'b10
+`define RESUME_END_WAIT_ST 2'b11
+
+//RXByteStateMachStates 
+`define IDLE_BYTE_ST 3'b000
+`define CHECK_SYNC_ST 3'b001
+`define CHECK_PID_ST 3'b010
+`define HS_BYTE_ST 3'b011
+`define TOKEN_BYTE_ST 3'b100
+`define DATA_BYTE_ST 3'b101
+
+`endif //usbSerialInterfaceEngine_h_vdefined
+
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbTxWireArbiter.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbTxWireArbiter.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbTxWireArbiter.v	(revision 264)
@@ -0,0 +1,213 @@
+
+// File        : ../RTL/serialInterfaceEngine/usbTxWireArbiter.v
+// Generated   : 11/10/06 05:37:24
+// From        : ../RTL/serialInterfaceEngine/usbTxWireArbiter.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbTxWireArbiter
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbConstants_h.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+
+module USBTxWireArbiter (SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn, clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst);
+input   SIETxCtrl;
+input   [1:0] SIETxData;
+input   SIETxFSRate;
+input   SIETxReq;
+input   SIETxWEn;
+input   USBWireRdyIn;
+input   clk;
+input   prcTxByteCtrl;
+input   [1:0] prcTxByteData;
+input   prcTxByteFSRate;
+input   prcTxByteReq;
+input   prcTxByteWEn;
+input   rst;
+output  SIETxGnt;
+output  [1:0] TxBits;
+output  TxCtl;
+output  TxFSRate;
+output  USBWireRdyOut;
+output  USBWireWEn;
+output  prcTxByteGnt;
+
+wire    SIETxCtrl;
+wire    [1:0] SIETxData;
+wire    SIETxFSRate;
+reg     SIETxGnt, next_SIETxGnt;
+wire    SIETxReq;
+wire    SIETxWEn;
+reg     [1:0] TxBits, next_TxBits;
+reg     TxCtl, next_TxCtl;
+reg     TxFSRate, next_TxFSRate;
+wire    USBWireRdyIn;
+reg     USBWireRdyOut, next_USBWireRdyOut;
+reg     USBWireWEn, next_USBWireWEn;
+wire    clk;
+wire    prcTxByteCtrl;
+wire    [1:0] prcTxByteData;
+wire    prcTxByteFSRate;
+reg     prcTxByteGnt, next_prcTxByteGnt;
+wire    prcTxByteReq;
+wire    prcTxByteWEn;
+wire    rst;
+
+// diagram signals declarations
+reg  muxSIENotPTXB, next_muxSIENotPTXB;
+
+// BINARY ENCODED state machine: txWireArb
+// State codes definitions:
+`define START_TARB 2'b00
+`define TARB_WAIT_REQ 2'b01
+`define PTXB_ACT 2'b10
+`define SIE_TX_ACT 2'b11
+
+reg [1:0] CurrState_txWireArb;
+reg [1:0] NextState_txWireArb;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+// processTxByte/SIETransmitter mux
+always @(USBWireRdyIn)
+begin
+    USBWireRdyOut <= USBWireRdyIn;
+end
+always @(muxSIENotPTXB or SIETxWEn or SIETxData or
+SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
+SIETxFSRate or prcTxByteFSRate)
+begin
+    if (muxSIENotPTXB  == 1'b1)
+    begin
+        USBWireWEn <= SIETxWEn;
+        TxBits <= SIETxData;
+        TxCtl <= SIETxCtrl;
+        TxFSRate <= SIETxFSRate;
+    end
+    else
+    begin
+        USBWireWEn <= prcTxByteWEn;
+        TxBits <= prcTxByteData;
+        TxCtl <= prcTxByteCtrl;
+        TxFSRate <= prcTxByteFSRate;
+    end
+end
+
+//--------------------------------------------------------------------
+// Machine: txWireArb
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb)
+begin : txWireArb_NextState
+  NextState_txWireArb <= CurrState_txWireArb;
+  // Set default values for outputs and signals
+  next_prcTxByteGnt <= prcTxByteGnt;
+  next_muxSIENotPTXB <= muxSIENotPTXB;
+  next_SIETxGnt <= SIETxGnt;
+  case (CurrState_txWireArb)
+    `START_TARB:
+      NextState_txWireArb <= `TARB_WAIT_REQ;
+    `TARB_WAIT_REQ:
+      if (prcTxByteReq == 1'b1)	
+      begin
+        NextState_txWireArb <= `PTXB_ACT;
+        next_prcTxByteGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b0;
+      end
+      else if (SIETxReq == 1'b1)	
+      begin
+        NextState_txWireArb <= `SIE_TX_ACT;
+        next_SIETxGnt <= 1'b1;
+        next_muxSIENotPTXB <= 1'b1;
+      end
+    `PTXB_ACT:
+      if (prcTxByteReq == 1'b0)	
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_prcTxByteGnt <= 1'b0;
+      end
+    `SIE_TX_ACT:
+      if (SIETxReq == 1'b0)	
+      begin
+        NextState_txWireArb <= `TARB_WAIT_REQ;
+        next_SIETxGnt <= 1'b0;
+      end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : txWireArb_CurrentState
+  if (rst)	
+    CurrState_txWireArb <= `START_TARB;
+  else
+    CurrState_txWireArb <= NextState_txWireArb;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : txWireArb_RegOutput
+  if (rst)	
+  begin
+    muxSIENotPTXB <= 1'b0;
+    prcTxByteGnt <= 1'b0;
+    SIETxGnt <= 1'b0;
+  end
+  else 
+  begin
+    muxSIENotPTXB <= next_muxSIENotPTXB;
+    prcTxByteGnt <= next_prcTxByteGnt;
+    SIETxGnt <= next_SIETxGnt;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/writeUSBWireData.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/writeUSBWireData.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/writeUSBWireData.v	(revision 264)
@@ -0,0 +1,281 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// writeUSBWireData.v                                           ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+`define BUFFER_FULL  3'b100
+
+module writeUSBWireData (
+  TxBitsIn, 
+  TxBitsOut,
+   TxDataOutTick,
+  TxCtrlIn, 
+  TxCtrlOut, 
+  USBWireRdy,
+  USBWireWEn, 
+  TxWireActiveDrive, 
+  fullSpeedRate, 
+  clk, 
+  rst
+   );
+  
+input   [1:0] TxBitsIn;
+input   TxCtrlIn;
+input   USBWireWEn;
+input   clk;
+input   fullSpeedRate;
+input   rst;
+output  [1:0] TxBitsOut;
+output TxDataOutTick;
+output  TxCtrlOut;
+output  USBWireRdy;
+output  TxWireActiveDrive;
+
+wire    [1:0] TxBitsIn;
+reg     [1:0] TxBitsOut;
+reg     TxDataOutTick;
+wire    TxCtrlIn;
+reg     TxCtrlOut;
+reg     USBWireRdy;
+wire    USBWireWEn;
+wire    clk;
+wire    fullSpeedRate;
+wire    rst;
+reg     TxWireActiveDrive;
+
+// local registers
+reg  [2:0]buffer0;
+reg  [2:0]buffer1;
+reg  [2:0]buffer2;
+reg  [2:0]buffer3;
+reg  [2:0]bufferCnt;
+reg  [1:0]bufferInIndex;
+reg  [1:0]bufferOutIndex;
+reg decBufferCnt;
+reg  [4:0]i;
+reg incBufferCnt;
+reg fullSpeedTick;
+reg lowSpeedTick;
+
+// buffer in state machine state codes:
+`define WAIT_BUFFER_NOT_FULL 2'b00
+`define WAIT_WRITE_REQ 2'b01
+`define CLR_INC_BUFFER_CNT 2'b10
+
+// buffer output state machine state codes:
+`define WAIT_BUFFER_FULL 2'b00
+`define WAIT_LINE_WRITE 2'b01
+`define LINE_WRITE 2'b10
+
+reg [1:0] bufferInStMachCurrState;
+reg [1:0] bufferOutStMachCurrState;
+
+// buffer control
+always @(posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    bufferCnt <= 3'b000;
+  end
+  else
+  begin
+    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
+      bufferCnt <= bufferCnt + 1'b1;
+    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
+      bufferCnt <= bufferCnt - 1'b1;
+  end
+end
+
+
+//buffer input state machine 
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+     incBufferCnt <= 1'b0;
+    bufferInIndex <= 2'b00;
+    buffer0 <= 3'b000;
+    buffer1 <= 3'b000;
+    buffer2 <= 3'b000;
+    buffer3 <= 3'b000;
+    USBWireRdy <= 1'b0;
+    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+  end
+  else begin
+    case (bufferInStMachCurrState)
+      `WAIT_BUFFER_NOT_FULL:
+      begin
+        if (bufferCnt != `BUFFER_FULL)  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+      end
+      `WAIT_WRITE_REQ:
+      begin
+        if (USBWireWEn == 1'b1)
+        begin
+          incBufferCnt <= 1'b1;
+          USBWireRdy <= 1'b0;
+          bufferInIndex <= bufferInIndex + 1'b1;
+          case (bufferInIndex)
+            2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
+            2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
+            2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
+            2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
+          endcase
+          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
+        end
+      end
+      `CLR_INC_BUFFER_CNT:
+      begin
+        incBufferCnt <= 1'b0;
+        if (bufferCnt != (`BUFFER_FULL - 1'b1) )  
+        begin
+          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
+          USBWireRdy <= 1'b1;
+        end
+        else begin
+          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
+        end
+      end
+    endcase
+  end
+end
+        
+//increment counter used to generate USB bit rate
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    i <= 5'b00000;
+    fullSpeedTick <= 1'b0;
+    lowSpeedTick <= 1'b0;
+  end
+  else
+  begin
+    i <= i + 1'b1;
+    if (i[1:0] == 2'b00)
+      fullSpeedTick <= 1'b1;
+    else
+      fullSpeedTick <= 1'b0; 
+    if (i == 5'b00000)
+      lowSpeedTick <= 1'b1;
+    else
+      lowSpeedTick <= 1'b0;
+  end
+end
+
+//buffer output state machine
+//buffer is constantly emptied at either
+//the full or low speed rate
+//if the buffer is empty, then the output is forced to tri-state
+always @(posedge clk) begin
+  if (rst == 1'b1)
+  begin
+    bufferOutIndex <= 2'b00;
+    decBufferCnt <= 1'b0;
+    TxBitsOut <= 2'b00;
+    TxCtrlOut <= `TRI_STATE;
+    TxDataOutTick <= 1'b0;
+    bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+  end
+  else
+  begin
+    case (bufferOutStMachCurrState)
+      `WAIT_LINE_WRITE:
+      begin
+        if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
+        begin
+          TxDataOutTick <= !TxDataOutTick;
+          if (bufferCnt == 0) begin
+            TxBitsOut <= 2'b00;
+            TxCtrlOut <= `TRI_STATE;
+          end
+          else begin
+            bufferOutStMachCurrState <= `LINE_WRITE;
+            decBufferCnt <= 1'b1;
+            bufferOutIndex <= bufferOutIndex + 1'b1;
+            case (bufferOutIndex)
+              2'b00 :
+            begin 
+              TxBitsOut <= buffer0[2:1];
+              TxCtrlOut <= buffer0[0];
+            end
+            2'b01 : 
+            begin
+              TxBitsOut <= buffer1[2:1];
+              TxCtrlOut <= buffer1[0];
+            end
+            2'b10 : 
+            begin 
+              TxBitsOut <= buffer2[2:1];
+              TxCtrlOut <= buffer2[0];
+            end
+            2'b11 : 
+            begin
+              TxBitsOut <= buffer3[2:1];
+              TxCtrlOut <= buffer3[0];
+            end
+            endcase
+          end
+        end
+      end
+      `LINE_WRITE:
+      begin
+        decBufferCnt <= 1'b0;
+        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
+      end
+    endcase
+  end
+end
+
+// control 'TxWireActiveDrive' 
+always @(TxCtrlOut)
+begin  
+  if (TxCtrlOut == `DRIVE)
+    TxWireActiveDrive <= 1'b1;
+  else
+    TxWireActiveDrive <= 1'b0;
+end
+
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/altera/download.bat
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/altera/download.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/altera/download.bat	(revision 264)
@@ -0,0 +1,3 @@
+fpgaConfig -i usbDeviceAlteraTop.rbf -r -a 0 -w -l
+pause
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.cof
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.cof	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.cof	(revision 264)
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
+<cof>
+	<eprom_name>NONE</eprom_name>
+	<output_filename>usbDeviceAlteraTop.rbf</output_filename>
+	<n_pages>1</n_pages>
+	<width>1</width>
+	<mode>0</mode>
+	<sof_data>
+		<page_flags>1</page_flags>
+		<bit0>
+			<sof_filename>usbDeviceAlteraTop.sof</sof_filename>
+		</bit0>
+	</sof_data>
+	<version>4</version>
+	<options>
+	</options>
+</cof>
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/synthesis/usbDeviceActelTop_syn.prj
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/synthesis/usbDeviceActelTop_syn.prj	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/synthesis/usbDeviceActelTop_syn.prj	(revision 264)
@@ -0,0 +1,62 @@
+#add_file options
+add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/timescale.v"
+add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl_h.v"
+add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine_h.v"
+add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbConstants_h.v"
+add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBus_h.v"
+add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlave_h.v"
+add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlaveReg_define.v"
+add_file -_include "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice_define.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/USBSlaveControlBI.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slavecontroller.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/endpMux.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveSendpacket.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveDirectcontrol.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/sctxportarbiter.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveGetpacket.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveRxStatusMonitor.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoMux.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishBoneBI.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/hostSlaveMuxBI.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/lineControlUpdate.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/siereceiver.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxBit.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxByte.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC5.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC16.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/SIETransmitter.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processTxByte.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbTxWireArbiter.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/writeUSBWireData.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/readUSBWireData.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/dpMem_dc.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/fifoRTL.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifoBI.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifo.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifoBI.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/RxFifo.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlave.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/checkLineState.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP0.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbROM.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP1Mouse.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishboneArb.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDevice.v"
+add_file -verilog "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceActelTop.v"
+set_option -top_module usbDeviceActelTop
+
+#device options
+set_option -technology IGLOO
+set_option -part AGL600V5
+
+#compilation/mapping options
+set_option -symbolic_fsm_compiler true
+
+#compilation/mapping options
+set_option -frequency 100.000
+
+#simulation options
+impl -active "synthesis"
+project -result_file "C:/datasheets/Opencores/usbHostSlave_new/usbhostslave/usbDevice/syn/Actel/usbDeviceActelTop/synthesis/usbDeviceActelTop.edn"
Index: common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.qpf
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.qpf	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.qpf	(revision 264)
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "7.2"
+DATE = "13:52:36  August 08, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "usbDeviceAlteraTop"
Index: common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw	(revision 264)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$93x4>7<881:46?9'iA3<54<9Q;0>;5=0/:074=3:2>3;67!2/20m2=FZJB\EW?8;@PT^ZIIDPUHM^MNDHLD[FJL911J^ZTPOONZ[FJLAGUNTYK]N@N21>GU_SUDBAWPCMIJJZPFD\O:n6O]W[]LJI_XLJGT_ZG[CIKMCZEKC8:0M_YU_NLO]ZBCZVI;==5NRVX\KKJ^WMNYSN?>1:CQS_YHFESTHI\PCMI22>GU_SUDBAWPDEP\BIOWNEE[=85NRVX\KKJ^WOHTIUZJROCO57=FZ^PTCCBV_HLPPZHREl1J^ZTPOONZ[UKDL8?0M_YU_NLO]ZTB[L^T@BIFC0:8EWQ]WFDGURXNLHF\@CUXEFNNm6O\SNA\SLROn2K\VRMCKCWEP\VB98<0MZTPCMIAQCR^XL;TBBKKIU30?DQ]WJF@SB[[PTV\P\VBk2K\VRHCOVVZT@><I^PT\L\[d:CT^ZU^F]B_CBB;;CMWL1=E]OM?7NBD099@HN6XJ\Ln7NBD0^@VBBYNFZ^37NBD0^MVP3=DDB;3<;5LLJ0440=DDB8S46MCK3Z2<53<KEA2<85LLJFUg>EKCM\THDXFDD78GIMAJ11H@FHM_HL6?FJLNQ20OAEIX0:3g>EKCORTHDXFDDg8GIMAPVG^@YG_LX78GIMNF8;0OAEFN^FJRLBBWKST>o5LLJKM[LDRNN;;7NBDIO]JFP@@W@DXXk5LLJKM[LDRNNUDYY64CMIJJZOIk2IGGD@PPDPJKAc<KEABBR]]C^VZT@753JF@CXZPPICPAZUOAO^h7NBD_GGF@GGDC01HC@CFTUGG3>EUMH^NH;5KCL]PTg=CKDUX\RGASUf8@@ULM^UJHG[\T008@CUXN[OZYH@LY^OL@@5<LEF:>6JCL^DQATSBFJSTABJJ5:FPW@H6=2N^XTQLYBNF[FIUZLI_EB@8;E]UEISB02OSXH\AAM1e?C<(~lxxeb`Pcupo+pue`fyaoye.wpfAcqajo$^YB pmn\0=KOrVrb`d`w.ycte>@FK]EYURDI5:DBHVC>3OHT_B[]CDa8B@CCJHI@SO[I9:DJJZSIA]Y37KAZT^QWVd=AG\^TYCG[S`9EKPRX^HF^I<5F5:KAQCA?3@D_I_@NL038NLRSM[UBB][[_U[SA3=KGHNNH;5COBIF@d=KGJANHRAZT29OKR5<EAP<7@QYAMWF3>HB\^EYG95AOOG2?J><GONO^N^Jb:RKEVCX[ACMX45_IOJBWGSTi2ZBBD]HNEGG<>VNF^COXE64PSKNP\VB991[^B^PPHLJWDESA_O>7]]LLJ48TVBHFL>0\^KA8:RPMKECMJ90^^Zm;RKDA]RBZGKG:6]FNFNFg>USI[^^\RYNIU48WQGS]Z;97^W\TDO\W\HD@[EECX]<;UMS0>RU]L20Y^KPBTDD=>STMVH^JJ]:;WKFS4d<PH]TZH\\INL2`>^ND@DS!UJM 1,2$VRRJ):%=-O\CHK0?]US>2RonRGk119[`hYJiceyZh||inl24>^ceVGbbb|Yesqjkk3<S90;Q85T0;5^0>gus90hncm;wgqwlii(8$;86xgdmd8|f5t?9:j!8hh496~DEv4:2JKt965F;695~U4l3=h6:k51205<g2=;<l>>v`88;38j2?=<2.<;79:;|Q0g?1d2>o1=><98c6970`fk2Y>979l:6g956410k>1?;?84:Q0g?1d2>o1=><98c69737ei2n<o7>51;3xW6b=?j0<i7?<27:a0?52n<80zY9<:182>4<0sZ9o6:m57d82770?j=089k;=;c4e>5<72:0<w)o57e9'5f<0n2.:h76?;%3f>20<,>>156l<f;2956<729q/:>4<e:&a>7g<,j0=n6*j:338 c<592.:<7<:;%32>77<,8819h5+1285f>"6<380(<;55b9'53<3i2.:;7?i;%1a>1=#:k0>7)=?:39'74<03-9869o4$2:92>"413><7)=n:4a8 16=>l1/8;4=;%62>0><,=91955+44844>"31390(9l5529'0a<212.?j7;6;%73>5=#==0?i6*:a;58 0`=92.=o7:n;%52>24<,m037)?m:508m64=83.=>79n;%47>26<3`8h6=4+6384e>"1<3=;76g99;29 34=?h1/:<480:9j22<72-<96:o4$73935=<a?21<7*92;5b?!062>:07d8::18'27<0i2.==79?;:k70?6=,?81;l5+60844>=h:80;6)8=:6c8 32=?91/=44=0:&2e?2d32e957>5$7093d=<g;?1<7*92;5b?>i5>3:1(;<57`98k7g=83.=>79n;:m13?6=,?81;l54o3:94?"1:3=j76a=e;29 34=?h10c?h50;&56?1f32e=h7>5$7093g=#>90<<65`5783>!052>k0(;:57198k30=83.=>79n;:a70<72;0;6=u+62866>o293:1(;<57`9'21<0821d9i4?:%41>2g<,?>1;=54}c00>5<5290;w)8<:328m07=83.=>79n;%47>26<3f?o6=4+6384e>"1<3=;76s|3583>7}:;o08>63<5;7g?!7?2:<0q~<k:18185a2;i01?=55e9'5=<5<2wx>?4?:3y>7c<59279?7;>;|q63?6=9r78j7;9;%4b>0b<uz9<6=4>{<16>07<,?k19<5rs2494?6|,?k19i5rs3694?6|,?k19i5r}o07>5<6std997>51zm63<728qvb?950;3xyk4?290:wp`=9;295~{i:h0;6<ur}|CDF}4:3hh;>l<19CDG}7uIJ[wpNO
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.sdc
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.sdc	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.sdc	(revision 264)
@@ -0,0 +1,114 @@
+## Generated SDC file "cyc_or12_mini_top.sdc"
+
+## Copyright (C) 1991-2007 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition"
+
+## DATE    "Fri May 16 09:55:20 2008"
+
+##
+## DEVICE  "EP2C20Q240C8"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {clk} -period 20.830 -waveform { 0.000 10.415 } [get_ports {clk}] -add
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+derive_pll_clocks -use_tan_name
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.v	(revision 264)
@@ -0,0 +1,78 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+//   ____  ____ 
+//  /   /\/   / 
+// /___/  \  /    Vendor: Xilinx 
+// \   \   \/     Version : 9.2.03i
+//  \   \         Application : xaw2verilog
+//  /   /         Filename : pll_48MHz_xilinx.v
+// /___/   /\     Timestamp : 08/20/2008 15:22:39
+// \   \  /  \ 
+//  \___\/\___\ 
+//
+//Command: xaw2verilog -intstyle F:/version_ctrl/usbhostslave/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx.xaw -st pll_48MHz_xilinx.v
+//Design Name: pll_48MHz_xilinx
+//Device: xc3s700a-5fg484
+//
+// Module pll_48MHz_xilinx
+// Generated by Xilinx Architecture Wizard
+// Written for synthesis tool: XST
+`timescale 1ns / 1ps
+
+module pll_48MHz_xilinx(CLKIN_IN, 
+                        CLKIN_IBUFG_OUT, 
+                        CLK0_OUT, 
+                        LOCKED_OUT);
+
+    input CLKIN_IN;
+   output CLKIN_IBUFG_OUT;
+   output CLK0_OUT;
+   output LOCKED_OUT;
+   
+   wire CLKFB_IN;
+   wire CLKIN_IBUFG;
+   wire CLK0_BUF;
+   wire GND_BIT;
+   
+   assign GND_BIT = 0;
+   assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
+   assign CLK0_OUT = CLKFB_IN;
+   IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN), 
+                           .O(CLKIN_IBUFG));
+   BUFG CLK0_BUFG_INST (.I(CLK0_BUF), 
+                        .O(CLKFB_IN));
+   DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN), 
+                       .CLKIN(CLKIN_IBUFG), 
+                       .DSSEN(GND_BIT), 
+                       .PSCLK(GND_BIT), 
+                       .PSEN(GND_BIT), 
+                       .PSINCDEC(GND_BIT), 
+                       .RST(GND_BIT), 
+                       .CLKDV(), 
+                       .CLKFX(), 
+                       .CLKFX180(), 
+                       .CLK0(CLK0_BUF), 
+                       .CLK2X(), 
+                       .CLK2X180(), 
+                       .CLK90(), 
+                       .CLK180(), 
+                       .CLK270(), 
+                       .LOCKED(LOCKED_OUT), 
+                       .PSDONE(), 
+                       .STATUS());
+   defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_SP_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_SP_INST.CLKIN_PERIOD = 20.833;
+   defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
+   defparam DCM_SP_INST.PHASE_SHIFT = 0;
+   defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.prj
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.prj	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.prj	(revision 264)
@@ -0,0 +1,39 @@
+verilog work "../../../../RTL/buffers/dpMem_dc.v"
+verilog work "../../../../RTL/slaveController/slavecontroller.v"
+verilog work "../../../../RTL/slaveController/slaveSendpacket.v"
+verilog work "../../../../RTL/slaveController/slaveRxStatusMonitor.v"
+verilog work "../../../../RTL/slaveController/slaveGetpacket.v"
+verilog work "../../../../RTL/slaveController/slaveDirectcontrol.v"
+verilog work "../../../../RTL/slaveController/sctxportarbiter.v"
+verilog work "../../../../RTL/slaveController/fifoMux.v"
+verilog work "../../../../RTL/slaveController/endpMux.v"
+verilog work "../../../../RTL/slaveController/USBSlaveControlBI.v"
+verilog work "../../../../RTL/serialInterfaceEngine/writeUSBWireData.v"
+verilog work "../../../../RTL/serialInterfaceEngine/usbTxWireArbiter.v"
+verilog work "../../../../RTL/serialInterfaceEngine/updateCRC5.v"
+verilog work "../../../../RTL/serialInterfaceEngine/updateCRC16.v"
+verilog work "../../../../RTL/serialInterfaceEngine/siereceiver.v"
+verilog work "../../../../RTL/serialInterfaceEngine/readUSBWireData.v"
+verilog work "../../../../RTL/serialInterfaceEngine/processTxByte.v"
+verilog work "../../../../RTL/serialInterfaceEngine/processRxByte.v"
+verilog work "../../../../RTL/serialInterfaceEngine/processRxBit.v"
+verilog work "../../../../RTL/serialInterfaceEngine/lineControlUpdate.v"
+verilog work "../../../../RTL/serialInterfaceEngine/SIETransmitter.v"
+verilog work "../../../../RTL/buffers/fifoRTL.v"
+verilog work "../../../../RTL/buffers/TxFifoBI.v"
+verilog work "../../../../RTL/buffers/RxFifoBI.v"
+verilog work "../../../../RTL/slaveController/usbSlaveControl.v"
+verilog work "../../../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v"
+verilog work "../../../../RTL/hostSlaveMux/hostSlaveMuxBI.v"
+verilog work "../../../../RTL/busInterface/wishBoneBI.v"
+verilog work "../../../../RTL/buffers/TxFifo.v"
+verilog work "../../../../RTL/buffers/RxFifo.v"
+verilog work "../../../RTL/wishboneArb.v"
+verilog work "../../../RTL/usbROM.v"
+verilog work "../../../RTL/checkLineState.v"
+verilog work "../../../RTL/EP1Mouse.v"
+verilog work "../../../RTL/EP0.v"
+verilog work "../../../../RTL/wrapper/usbSlave.v"
+verilog work "pll_48MHz_xilinx.v"
+verilog work "../../../RTL/usbDevice.v"
+verilog work "../../../RTL/usbDeviceXilinxTop.v"
Index: common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ucf
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ucf	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ucf	(revision 264)
@@ -0,0 +1,144 @@
+##############################################################################
+## Copyright (c) 2006, 2007 Xilinx, Inc.
+## This design is confidential and proprietary of Xilinx, All Rights Reserved.
+##############################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /   Vendor:        Xilinx
+## \   \   \/    Version:       1.0.1
+##  \   \        Filename:      starter_kit_constraints.ucf
+##  /   /        Date Created:  December 25, 2006
+## /___/   /\    Last Modified: April 1, 2007
+## \   \  /  \
+##  \___\/\___\
+##
+## Devices:   Spartan-3 Generation FPGA
+## Purpose:   Complete constraint file for Spartan-3A(N) Starter Kit
+## Contact:   crabill@xilinx.com
+## Reference: None
+##
+## Revision History:
+##   Rev 1.0.0 - (crabill) Created December 25, 2006 for PCB revision C.
+##   Rev 1.0.1 - (crabill) Modified April 1, 2007 to mention revision D
+##                         of the PCB and applicability to Spartan-3AN.
+##
+##############################################################################
+##
+## LIMITED WARRANTY AND DISCLAIMER. These designs are provided to you "as is".
+## Xilinx and its licensors make and you receive no warranties or conditions,
+## express, implied, statutory or otherwise, and Xilinx specifically disclaims
+## any implied warranties of merchantability, non-infringement, or fitness for
+## a particular purpose. Xilinx does not warrant that the functions contained
+## in these designs will meet your requirements, or that the operation of
+## these designs will be uninterrupted or error free, or that defects in the
+## designs will be corrected. Furthermore, Xilinx does not warrant or make any
+## representations regarding use or the results of the use of the designs in
+## terms of correctness, accuracy, reliability, or otherwise.
+##
+## LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be liable
+## for any loss of data, lost profits, cost or procurement of substitute goods
+## or services, or for any special, incidental, consequential, or indirect
+## damages arising from the use or operation of the designs or accompanying
+## documentation, however caused and on any theory of liability. This
+## limitation will apply even if Xilinx has been advised of the possibility
+## of such damage. This limitation shall apply not-withstanding the failure
+## of the essential purpose of any limited remedies herein.
+##
+##############################################################################
+## Copyright (c) 2006, 2007 Xilinx, Inc.
+## This design is confidential and proprietary of Xilinx, All Rights Reserved.
+##############################################################################
+
+# On this board, VCCAUX is 3.3 volts.
+
+CONFIG VCCAUX = "3.3" ;
+
+# Configure SUSPEND mode options.
+ 
+CONFIG ENABLE_SUSPEND = "FILTERED" ;
+
+# FILTERED is appropriate for use with the switch on this board. Other allowed
+# settings are NO or UNFILTERED.  If set NO, the AWAKE pin becomes general I/O.
+# Please read the FPGA User Guide for more information.
+
+# Configure POST_CRC options.
+
+CONFIG POST_CRC = "DISABLE" ;
+
+# DISABLE the post-configuration CRC checking so INIT_B is available for
+# general I/O after configuration is done.  On this board, INIT_B is used
+# after configuration to control the Platform Flash device.  Other allowed
+# settings are ENABLE.  Please read the FPGA User Guide for more information.
+
+##############################################################################
+# These are sample constraints for the three clock inputs.  You will need
+# to change these constraints to suit your application.  Please read the
+# FPGA Development System Reference Guide for more information on expressing
+# timing constraints for your design.
+##############################################################################
+
+
+NET "clk"       LOC = "V12"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.830 ;
+OFFSET = IN  10.410 VALID 20.830 BEFORE "clk" ;
+OFFSET = OUT 20.830 AFTER "clk" ;
+
+
+
+
+
+
+##############################################################################
+# Accessory Headers (J18, J19, J20)
+##############################################################################
+
+#NET "J18_IO<1>"     LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+#NET "J18_IO<2>"     LOC = "AB21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+#NET "J18_IO<3>"     LOC = "AA19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+#NET "J18_IO<4>"     LOC = "AB19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "usbSlaveVP"     LOC = "AA21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "usbSlaveVM"     LOC = "AB21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "usbSlaveOE_n"     LOC = "AA19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+NET "usbDPlusPullup"     LOC = "AB19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+
+#NET "J19_IO<1>"     LOC = "Y18"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+#NET "J19_IO<2>"     LOC = "W18"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+#NET "J19_IO<3>"     LOC = "V17"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+#NET "J19_IO<4>"     LOC = "W17"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+
+#NET "J20_IO<1>"     LOC = "V14"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+#NET "J20_IO<2>"     LOC = "V15"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+#NET "J20_IO<3>"     LOC = "W16"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+#NET "J20_IO<4>"     LOC = "V16"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+
+
+
+
+
+##############################################################################
+# 10/100 Ethernet (E)
+##############################################################################
+
+
+NET "E_NRST"        LOC = "D15"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+
+##############################################################################
+# Serial Peripheral System
+##############################################################################
+
+NET "SPI_SCK"       LOC = "AA20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+
+##############################################################################
+# Parallel Flash (NF)
+##############################################################################
+
+NET "NF_CE"         LOC = "W20"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
+
+
+##############################################################################
+# DDR2 SDRAM Device (SD)
+##############################################################################
+
+NET "SD_CS"         LOC = "M5"   | IOSTANDARD = SSTL18_I ;
+
+
+##############################################################################
Index: common/components/usbhostslave/web_uploads/driver/ohs900_2.6.28.diff
===================================================================
--- common/components/usbhostslave/web_uploads/driver/ohs900_2.6.28.diff	(nonexistent)
+++ common/components/usbhostslave/web_uploads/driver/ohs900_2.6.28.diff	(revision 264)
@@ -0,0 +1,2160 @@
+--- host.old/Kconfig	2008-11-28 11:22:54.000000000 +0100
++++ host/Kconfig	2008-11-28 11:38:40.000000000 +0100
+@@ -17,6 +17,19 @@
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called c67x00.
+ 
++config USB_OHS900_HCD
++    tristate "OHS900 HCD support"
++    depends on USB
++    default N
++    help
++      The OHS900 is a single-port USB controller that supports either
++      host side or peripheral side roles.  Enable this option if your
++      board has this core, and you want to use it as a host controller. 
++      If unsure, say N.
++
++      To compile this driver as a module, choose M here: the
++      module will be called ohs900-hcd. 
++
+ config USB_EHCI_HCD
+ 	tristate "EHCI HCD (USB 2.0) support"
+ 	depends on USB && USB_ARCH_HAS_EHCI
+
+--- host.old/Makefile	2008-11-28 11:22:54.000000000 +0100
++++ host/Makefile	2008-11-28 11:38:40.000000000 +0100
+@@ -20,6 +20,7 @@
+ obj-$(CONFIG_USB_SL811_HCD)	+= sl811-hcd.o
+ obj-$(CONFIG_USB_SL811_CS)	+= sl811_cs.o
+ obj-$(CONFIG_USB_U132_HCD)	+= u132-hcd.o
++obj-$(CONFIG_USB_OHS900_HCD)	+= ohs900-hcd.o
+ obj-$(CONFIG_USB_R8A66597_HCD)	+= r8a66597-hcd.o
+ obj-$(CONFIG_USB_ISP1760_HCD)	+= isp1760.o
+ obj-$(CONFIG_USB_HWA_HCD)	+= hwa-hc.o
+
+--- host.old/ohs900.h	1970-01-01 01:00:00.000000000 +0100
++++ host/ohs900.h	2008-11-28 14:40:41.000000000 +0100
+@@ -0,0 +1,288 @@
++/*
++ * OHS900 register declarations and HCD data structures
++ *
++ * Copyright (C) 2005 Steve Fielding
++ * Copyright (C) 2004 Psion Teklogix
++ * Copyright (C) 2004 David Brownell
++ */
++
++//#include <asm/arch/sam255.h>
++
++// base address of OHS900
++#define OHS900_BASE		na_usb //(DIMI_USB_HOST_PHYS)
++#define OHS900_IRQ		na_usb_irq //(SAM255_INTERRUPT_USB_HOST)
++#define OHS900SLAVE_BASE	na_usb //(DIMI_USB_HOST_PHYS)
++#define OHS900SLAVE_IRQ		na_usb_irq //(SAM255_INTERRUPT_USB_HOST)
++
++
++/*
++ * OHS900 has transfer registers, and control registers.  In host/master
++ * mode one set of registers is used; in peripheral/slave mode, another.
++ */
++
++
++/* TRANSFER REGISTERS
++ */
++#define OHS900_HOST_TX_CTLREG	0x00 
++#	define OHS900_HCTLMASK_TRANS_REQ		0x01 
++#	define OHS900_HCTLMASK_SOF_SYNC		0x02 
++#	define OHS900_HCTLMASK_PREAMBLE_EN	0x04 
++#	define OHS900_HCTLMASK_ISO_EN		0x08 
++
++
++#define OHS900_HRXSTATREG	0x0a	/* read */ 
++#	define OHS900_STATMASK_CRC_ERROR		0x01 
++#	define OHS900_STATMASK_BS_ERROR		0x02 
++#	define OHS900_STATMASK_RX_OVF		0x04 
++#	define OHS900_STATMASK_RX_TMOUT		0x08 
++#	define OHS900_STATMASK_NAK_RXED		0x10 
++#	define OHS900_STATMASK_STALL_RXED	0x20 
++#	define OHS900_STATMASK_ACK_RXED		0x40 
++#	define OHS900_STATMASK_DATA_SEQ		0x80 
++
++#define OHS900_TXTRANSTYPEREG		0x01	/* write */ 
++#	define	OHS900_SETUP	0x00 
++#	define	OHS900_IN	0x01 
++#	define	OHS900_OUT_DATA0	0x02 
++#	define	OHS900_OUT_DATA1	0x03 
++
++#define OHS900_TXADDRREG	0x04	
++#define OHS900_TXENDPREG	0x05	
++
++/* CONTROL REGISTERS:  
++ */
++#define OHS900_SOFENREG		0x03 
++#	define OHS900_MASK_SOF_ENA	0x01 
++
++#define OHS900_TXLINECTLREG 0x02 
++#	define OHS900_TXLCTL_MASK_FORCE	0x4 
++#	define OHS900_TXLCTL_MASK_LINE_CTRL_BITS 0x7
++#		define OHS900_TXLCTL_MASK_NORMAL	0x00 
++#		define OHS900_TXLCTL_MASK_SE0	0x04	
++#		define OHS900_TXLCTL_MASK_FS_J	0x06    
++#		define OHS900_TXLCTL_MASK_FS_K	0x05	
++#	define OHS900_TXLCTL_MASK_LSPD	0x00 
++#	define OHS900_TXLCTL_MASK_FSPD	0x18 
++#	define OHS900_TXLCTL_MASK_FS_POL	0x08 
++#	define OHS900_TXLCTL_MASK_FS_RATE 0x10 
++
++
++#define OHS900_IRQ_ENABLE	0x09             
++#	define OHS900_INTMASK_TRANS_DONE	0x01   
++#	define OHS900_INTMASK_SOFINTR	0x08   
++#	define OHS900_INTMASK_INSRMV	0x04   	
++#	define OHS900_INTMASK_RESUME_DET	0x02   
++		  
++#define OHS900_RXCONNSTATEREG 0x0e
++#define   OHS900_DISCONNECT_STATE 0x00
++#define   OHS900_LS_CONN_STATE 0x01
++#define   OHS900_FS_CONN_STATE 0x02
++
++#define OHS900_SLAVE_ADDRESS		0x54 
++
++
++
++#define OHS900_IRQ_STATUS	0x08	/* write to ack */ 
++#define OHS900_HWREVREG		0xe1	/* read */ 
++
++#define OHS900_SOFTMRREG		0x0F 
++
++
++
++#define OHS900_HOSTSLAVECTLREG 			0xe0 
++#	define OHS900_HSCTLREG_HOST_EN_MASK	0x01 
++#	define OHS900_HSCTLREG_RESET_CORE	0x02 
++
++
++
++#define OHS900_HS_CTL_INIT OHS900_HSCTLREG_HOST_EN_MASK 
++
++/* 64-byte FIFO control and status
++ */
++#define H_MAXPACKET	64		/* bytes in fifos */
++
++#define OHS900_HOST_TXFIFO_DATA	0x30 
++#define OHS900_TXFIFOCNTMSBREG	0x32 
++#define OHS900_TXFIFOCNTLSBREG	0x33
++#define OHS900_TXFIFOCONTROLREG	0x34
++#define OHS900_HOST_RXFIFO_DATA	0x20 
++#define OHS900_RXFIFOCNTMSBREG	0x22 
++#define OHS900_RXFIFOCNTLSBREG	0x23
++#define OHS900_RXFIFOCONTROLREG	0x24
++#define		OHS900_FIFO_FORCE_EMPTY 0x01
++
++
++#define OHS900_IO_EXTENT 0x100
++
++/*-------------------------------------------------------------------------*/
++
++#define	LOG2_PERIODIC_SIZE	5	/* arbitrary; this matches OHCI */
++#define	PERIODIC_SIZE		(1 << LOG2_PERIODIC_SIZE)
++
++struct ohs900 {
++	spinlock_t		lock;
++	void __iomem		*addr_reg;
++	struct ohs900_platform_data	*board;
++	struct proc_dir_entry	*pde;
++
++	unsigned long		stat_insrmv;
++	unsigned long		stat_wake;
++	unsigned long		stat_sof;
++	unsigned long		stat_a;
++	unsigned long		stat_b;
++	unsigned long		stat_lost;
++	unsigned long		stat_overrun;
++
++	/* sw model */
++	struct timer_list	timer;
++	struct ohs900h_ep	*next_periodic;
++	struct ohs900h_ep	*next_async;
++
++	struct ohs900h_ep	*active_a;
++	unsigned long		jiffies_a;
++	struct ohs900h_ep	*active_b;
++	unsigned long		jiffies_b;
++
++	u32			port1;
++	u8			ctrl1, ctrl2, irq_enable;
++	u16			frame;
++
++	/* async schedule: control, bulk */
++	struct list_head	async;
++
++	/* periodic schedule: interrupt, iso */
++	u16			load[PERIODIC_SIZE];
++	struct ohs900h_ep	*periodic[PERIODIC_SIZE];
++	unsigned		periodic_count;
++};
++
++static inline struct ohs900 *hcd_to_ohs900(struct usb_hcd *hcd)
++{
++	return (struct ohs900 *) (hcd->hcd_priv);
++}
++
++static inline struct usb_hcd *ohs900_to_hcd(struct ohs900 *ohs900)
++{
++	return container_of((void *) ohs900, struct usb_hcd, hcd_priv);
++}
++
++struct ohs900h_ep {
++	struct usb_host_endpoint *hep;
++	struct usb_device	*udev;
++
++	u8			defctrl;
++	u8			maxpacket;
++	u8			epnum;
++	u8			nextpid;
++
++	u16			error_count;
++	u16			nak_count;
++	u16			length;		/* of current packet */
++
++	/* periodic schedule */
++	u16			period;
++	u16			branch;
++	u16			load;
++	struct ohs900h_ep	*next;
++
++	/* async schedule */
++	struct list_head	schedule;
++};
++
++/*-------------------------------------------------------------------------*/
++
++/* Register utilities
++ * NOTE:  caller must hold ohs900->lock.
++ */
++
++static inline u8 ohs900_read(struct ohs900 *ohs900, int reg)
++{
++	u8 temp;
++
++	temp = ( (volatile int *) ohs900->addr_reg) [reg];
++
++	return temp;
++}
++
++static inline void ohs900_write(struct ohs900 *ohs900, int reg, u8 val)
++{
++	( (volatile int *) ohs900->addr_reg) [reg] = val;
++}
++
++static inline void
++ohs900_write_buf(struct ohs900 *ohs900, int addr, const void *buf, size_t count)
++{
++    void __iomem *addr_reg = ohs900->addr_reg;
++	const u8	*data;
++	const u8	*tempData;
++	size_t tempCnt;
++	
++	if (!count)
++		return;
++
++	//printk("ohs900_write_buf(): Writing 0x%x bytes:\n", count);
++	tempData = buf;
++	tempCnt = count;
++	do {
++		//printk("0x%02x ", *tempData++);
++	} while (--tempCnt);
++	//printk("\n");
++
++	data = buf;
++	do {
++		( (int *) addr_reg) [addr] = *data++;
++	} while (--count);
++
++
++}
++
++static inline void
++ohs900_read_buf(struct ohs900 *ohs900, int addr, void *buf, size_t count)
++{
++    void __iomem *addr_reg = ohs900->addr_reg;
++	u8 		*data;
++	u8 		*tempData;
++	size_t		tempCnt;
++
++	if (!count)
++		return;
++
++	data = buf;
++	tempData = buf;
++	tempCnt = count;
++	//printk("ohs900_read_buf(): Reading 0x%x bytes\n", count);
++	do {
++		//*data++ = ( (int *) OHS900_BASE) [addr];
++		*data++ = ( (int *) addr_reg) [addr];
++	} while (--count);
++
++	do {
++		//printk("0x%02x ",*tempData++);
++	} while (--tempCnt);
++	//printk("\n");
++}
++
++/*-------------------------------------------------------------------------*/
++
++#ifdef DEBUG
++#define DBG(stuff...)		printk(KERN_DEBUG "ohs900: " stuff)
++#else
++#define DBG(stuff...)		do{}while(0)
++#endif
++
++#ifdef VERBOSE
++#    define VDBG		DBG
++#else
++#    define VDBG(stuff...)	do{}while(0)
++#endif
++
++#ifdef PACKET_TRACE
++#    define PACKET		VDBG
++#else
++#    define PACKET(stuff...)	do{}while(0)
++#endif
++
++#define ERR(stuff...)		printk(KERN_ERR "ohs900: " stuff)
++#define WARNING(stuff...)	printk(KERN_WARNING "ohs900: " stuff)
++#define INFO(stuff...)		printk(KERN_INFO "ohs900: " stuff)
++
+
+--- host.old/ohs900-hcd.c	1970-01-01 01:00:00.000000000 +0100
++++ host/ohs900-hcd.c	2008-12-01 16:46:00.000000000 +0100
+@@ -0,0 +1,1831 @@
++/*
++ * OHS900 HCD (Host Controller Driver) for USB.
++ *
++ * Based on David Brownell's SL811 HCD
++ *
++ * Copyright (C) 2005 Steve Fielding
++ * Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
++ * Copyright (C) 2004-2005 David Brownell
++ * 
++ * Periodic scheduling is based on Roman's OHCI code
++ * 	Copyright (C) 1999 Roman Weissgaerber
++ *
++ * The OHS900 controller handles host side USB 
++ * as well as peripheral side USB
++ * This driver version doesn't implement the Gadget API
++ * for the peripheral role.
++ *
++ * For documentation, see the OHS900 spec.
++ *
++ * Further changes for 2.6.22.1 kernel by Mario Becroft and Bryce Smith
++ */ 
++
++/*
++ * Status:  Passed basic testing, works with usb-storage.
++ *
++ * TODO:
++ * - Replace direct memory accesses.
++ * - various issues noted in the code
++ * - use urb->iso_frame_desc[] with ISO transfers
++ */
++
++//#undef	VERBOSE
++//#undef	PACKET_TRACE
++
++/*#define DEBUG*/
++#undef DEBUG
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/ioport.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/timer.h>
++#include <linux/list.h>
++#include <linux/interrupt.h>
++#include <linux/usb.h>
++#include <linux/usb_ohs900.h>
++#include <linux/platform_device.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/system.h>
++#include <asm/byteorder.h>
++
++#include "../core/hcd.h"
++#include "ohs900.h"
++
++
++MODULE_DESCRIPTION("OHS900 USB Host Controller Driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ohs900-hcd");
++
++#define DRIVER_VERSION	"19 Sep 2007"
++
++
++#ifndef DEBUG
++#	define	STUB_DEBUG_FILE
++#endif
++
++/* Disable the debug file since it broken at present */
++#define STUB_DEBUG_FILE
++
++/* for now, use only one transfer register bank */
++#undef	USE_B
++
++/* this doesn't understand urb->iso_frame_desc[], but if you had a driver
++ * that just queued one ISO frame per URB then iso transfers "should" work
++ * using the normal urb status fields.
++ */
++#define	DISABLE_ISO
++
++// #define	QUIRK2
++#define	QUIRK3
++
++static const char hcd_name[] = "ohs900-hcd";
++
++void ohs900_release(struct device *dev);
++
++/*-------------------------------------------------------------------------*/
++
++static irqreturn_t ohs900h_irq(struct usb_hcd *hcd);
++
++static void port_power(struct ohs900 *ohs900, int is_on)
++{
++	struct usb_hcd	*hcd = ohs900_to_hcd(ohs900);
++	u8			tmp;
++
++	printk(KERN_INFO "IRQ!\n");
++	INFO("driver %s, ohs900->addr_reg = 0x%x, OHS900_HWREVREG = 0x%x\n", 
++			hcd_name, (unsigned int) ohs900->addr_reg, OHS900_HWREVREG);
++	tmp = ohs900_read(ohs900, OHS900_HWREVREG);
++	INFO("driver %s, started port_power, usb hw version = %d\n", hcd_name, tmp);
++
++	/* hub is inactive unless the port is powered */
++	if (is_on) {
++		if (ohs900->port1 & (1 << USB_PORT_FEAT_POWER))
++			return;
++
++		ohs900->port1 = (1 << USB_PORT_FEAT_POWER);
++		ohs900->irq_enable = OHS900_INTMASK_INSRMV;
++	} else {
++		ohs900->port1 = 0;
++		ohs900->irq_enable = 0;
++		hcd->state = HC_STATE_HALT;
++	}
++
++	INFO("driver %s, setting ohs900->ctrl1\n", hcd_name);
++	ohs900->ctrl1 = OHS900_TXLCTL_MASK_FS_RATE & OHS900_TXLCTL_MASK_FS_POL;
++
++	INFO("driver %s, disabling interrupts\n", hcd_name);
++	ohs900_write(ohs900, OHS900_IRQ_ENABLE, 0);
++
++	INFO("driver %s, clearing interrupt status\n", hcd_name);
++	ohs900_write(ohs900, OHS900_IRQ_STATUS, ~0);
++
++	if (ohs900->board && ohs900->board->port_power) {
++		/* switch VBUS, at 500mA unless hub power budget gets set */
++		DBG("power %s\n", is_on ? "on" : "off");
++		ohs900->board->port_power(hcd->self.controller, is_on);
++	}
++
++	/* reset as thoroughly as we can */
++	if (ohs900->board && ohs900->board->reset)
++		ohs900->board->reset(hcd->self.controller);
++
++	ohs900_write(ohs900, OHS900_IRQ_ENABLE, 0);
++	ohs900_write(ohs900, OHS900_TXLINECTLREG, ohs900->ctrl1);
++
++	ohs900_write(ohs900, OHS900_SOFENREG, 0);
++	ohs900_write(ohs900, OHS900_HOSTSLAVECTLREG, OHS900_HS_CTL_INIT);
++
++	INFO("driver %s, OHS900_IRQ_ENABLE = %d\n", hcd_name, ohs900->irq_enable);
++	ohs900_write(ohs900, OHS900_IRQ_ENABLE, ohs900->irq_enable);
++
++	// if !is_on, put into lowpower mode now
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* This is a PIO-only HCD.  Queueing appends URBs to the endpoint's queue,
++ * and may start I/O.  Endpoint queues are scanned during completion irq
++ * handlers (one per packet: ACK, NAK, faults, etc) and urb cancelation.
++ *
++ * Using an external DMA engine to copy a packet at a time could work,
++ * though setup/teardown costs may be too big to make it worthwhile.
++ */
++
++/* SETUP starts a new control request.  Devices are not allowed to
++ * STALL or NAK these; they must cancel any pending control requests.
++ */
++static void setup_packet(
++	struct ohs900		*ohs900,
++	struct ohs900h_ep	*ep,
++	struct urb		*urb,
++	u8			control
++)
++{
++	u8			addr;
++	u8			len;
++
++	ohs900_write(ohs900, OHS900_TXFIFOCONTROLREG, OHS900_FIFO_FORCE_EMPTY);
++	addr = OHS900_HOST_TXFIFO_DATA;
++	len = sizeof(struct usb_ctrlrequest);
++	ohs900_write_buf(ohs900, addr, urb->setup_packet, len);
++
++	ohs900_write(ohs900, OHS900_TXTRANSTYPEREG, OHS900_SETUP);
++	ohs900_write(ohs900, OHS900_TXENDPREG, 0 /* ep->epnum */ );
++	ohs900_write(ohs900, OHS900_TXADDRREG, usb_pipedevice(urb->pipe));
++
++	/* always OUT/data0 */ ;
++	ohs900_write(ohs900, OHS900_HOST_TX_CTLREG, control);
++	ep->length = 0;
++	PACKET("SETUP qh%p\n", ep);
++}
++
++/* STATUS finishes control requests, often after IN or OUT data packets */
++static void status_packet(
++	struct ohs900		*ohs900,
++	struct ohs900h_ep	*ep,
++	struct urb		*urb,
++	u8			control
++)
++{
++	int			do_out;
++
++	do_out = urb->transfer_buffer_length && usb_pipein(urb->pipe);
++
++	ohs900_write(ohs900, OHS900_TXTRANSTYPEREG, (do_out ? OHS900_OUT_DATA1 : OHS900_IN));
++	ohs900_write(ohs900, OHS900_TXENDPREG, 0 /* ep->epnum */ );
++	ohs900_write(ohs900, OHS900_TXADDRREG, usb_pipedevice(urb->pipe));
++
++	/* always data1; sometimes IN */
++	ohs900_write(ohs900, OHS900_HOST_TX_CTLREG, control);
++	ep->length = 0;
++	PACKET("STATUS%s/%s qh%p\n", ep->nak_count ? "/retry" : "",
++			do_out ? "out" : "in", ep);
++}
++
++/* IN packets can be used with any type of endpoint. here we just
++ * start the transfer, data from the peripheral may arrive later.
++ * urb->iso_frame_desc is currently ignored here...
++ */
++static void in_packet(
++	struct ohs900		*ohs900,
++	struct ohs900h_ep	*ep,
++	struct urb		*urb,
++	u8			control
++)
++{
++	u8			len;
++
++	/* avoid losing data on overflow */
++	len = ep->maxpacket;
++
++
++	ohs900_write(ohs900, OHS900_RXFIFOCONTROLREG, OHS900_FIFO_FORCE_EMPTY);
++	ohs900_write(ohs900, OHS900_TXTRANSTYPEREG, OHS900_IN);
++	ohs900_write(ohs900, OHS900_TXADDRREG, usb_pipedevice(urb->pipe));
++	ohs900_write(ohs900, OHS900_TXENDPREG, ep->epnum);
++	ohs900_write(ohs900, OHS900_HOST_TX_CTLREG, control);
++	ep->length = min((int)len,
++			urb->transfer_buffer_length - urb->actual_length);
++	PACKET("IN%s/%d qh%p len%d\n", ep->nak_count ? "/retry" : "",
++			!!usb_gettoggle(urb->dev, ep->epnum, 0), ep, len);
++}
++
++/* OUT packets can be used with any type of endpoint.
++ * urb->iso_frame_desc is currently ignored here...
++ */
++static void out_packet(
++	struct ohs900		*ohs900,
++	struct ohs900h_ep	*ep,
++	struct urb		*urb,
++	u8			control
++)
++{
++	void			*buf;
++	u8			len;
++
++	buf = urb->transfer_buffer + urb->actual_length;
++	prefetch(buf);
++
++	len = min((int)ep->maxpacket,
++			urb->transfer_buffer_length - urb->actual_length);
++
++	ohs900_write(ohs900, OHS900_TXFIFOCONTROLREG, OHS900_FIFO_FORCE_EMPTY);
++	if (!(control & OHS900_HCTLMASK_ISO_EN)
++			&& usb_gettoggle(urb->dev, ep->epnum, 1))
++		ohs900_write(ohs900, OHS900_TXTRANSTYPEREG, OHS900_OUT_DATA1);
++	else
++		ohs900_write(ohs900, OHS900_TXTRANSTYPEREG, OHS900_OUT_DATA0);
++
++
++	ohs900_write_buf(ohs900, OHS900_HOST_TXFIFO_DATA, buf, len);
++
++	ohs900_write(ohs900, OHS900_TXADDRREG, usb_pipedevice(urb->pipe));
++	ohs900_write(ohs900, OHS900_TXENDPREG, ep->epnum);
++	ohs900_write(ohs900, OHS900_HOST_TX_CTLREG, control);
++
++	ep->length = len;
++	PACKET("OUT%s/%d qh%p len%d\n", ep->nak_count ? "/retry" : "",
++			!!usb_gettoggle(urb->dev, ep->epnum, 1), ep, len);
++}
++/*-------------------------------------------------------------------------*/
++
++/* caller updates on-chip enables later */
++
++static inline void sofirq_on(struct ohs900 *ohs900)
++{
++	if (ohs900->irq_enable & OHS900_INTMASK_SOFINTR)
++		return;
++	VDBG("sof irq on\n");
++	ohs900->irq_enable |= OHS900_INTMASK_SOFINTR;
++}
++
++static inline void sofirq_off(struct ohs900 *ohs900)
++{
++	if (!(ohs900->irq_enable & OHS900_INTMASK_SOFINTR))
++		return;
++	VDBG("sof irq off\n");
++	ohs900->irq_enable &= ~OHS900_INTMASK_SOFINTR;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* pick the next endpoint for a transaction, and issue it.
++ * frames start with periodic transfers (after whatever is pending
++ * from the previous frame), and the rest of the time is async
++ * transfers, scheduled round-robin.
++ */
++static struct ohs900h_ep	*start(struct ohs900 *ohs900)
++{
++	struct ohs900h_ep	*ep;
++	struct urb		*urb;
++	int			fclock;
++	u8			control;
++
++	/* use endpoint at schedule head */
++	if (ohs900->next_periodic) {
++		ep = ohs900->next_periodic;
++		ohs900->next_periodic = ep->next;
++	} else {
++		if (ohs900->next_async)
++			ep = ohs900->next_async;
++		else if (!list_empty(&ohs900->async))
++			ep = container_of(ohs900->async.next,
++					struct ohs900h_ep, schedule);
++		else {
++			/* could set up the first fullspeed periodic
++			 * transfer for the next frame ...
++			 */
++			return NULL;
++		}
++
++
++
++
++
++
++		if (ep->schedule.next == &ohs900->async)
++			ohs900->next_async = NULL;
++		else
++			ohs900->next_async = container_of(ep->schedule.next,
++					struct ohs900h_ep, schedule);
++	}
++
++	if (unlikely(list_empty(&ep->hep->urb_list))) {
++		DBG("empty %p queue?\n", ep);
++		return NULL;
++	}
++
++	urb = container_of(ep->hep->urb_list.next, struct urb, urb_list);
++	control = ep->defctrl;
++
++	/* if this frame doesn't have enough time left to transfer this
++	 * packet, wait till the next frame.  too-simple algorithm...
++	 */
++	fclock = 12000 - (ohs900_read(ohs900, OHS900_SOFTMRREG) << 6);
++	fclock -= 100;		/* setup takes not much time */
++	fclock -= 1500; /* Margin to workaround too-long-frame bug */
++	if (urb->dev->speed == USB_SPEED_LOW) {
++		if (control & OHS900_HCTLMASK_PREAMBLE_EN) {
++			/* also note erratum 1: some hubs won't work */
++			fclock -= 800;
++		}
++		fclock -= ep->maxpacket << 8;
++
++		/* erratum 2: AFTERSOF only works for fullspeed */
++		if (fclock < 0) {
++			if (ep->period)
++				ohs900->stat_overrun++;
++			sofirq_on(ohs900);
++			return NULL;
++		}
++	} else {
++		fclock -= 12000 / 19;	/* 19 64byte packets/msec */
++		if (fclock < 0) {
++			if (ep->period)
++				ohs900->stat_overrun++;
++			control |= OHS900_HCTLMASK_SOF_SYNC;
++
++		/* throttle bulk/control irq noise */
++		} else if (ep->nak_count)
++			control |= OHS900_HCTLMASK_SOF_SYNC;
++	}
++
++
++	switch (ep->nextpid) {
++	case USB_PID_IN:
++		in_packet(ohs900, ep, urb, control);
++		break;
++	case USB_PID_OUT:
++		out_packet(ohs900, ep, urb, control);
++		break;
++	case USB_PID_SETUP:
++		setup_packet(ohs900, ep, urb, control);
++		break;
++	case USB_PID_ACK:		/* for control status */
++		status_packet(ohs900, ep, urb, control);
++		break;
++	default:
++		DBG("bad ep%p pid %02x\n", ep, ep->nextpid);
++		ep = NULL;
++	}
++	return ep;
++}
++
++#define MIN_JIFFIES	((msecs_to_jiffies(2) > 1) ? msecs_to_jiffies(2) : 2)
++
++static inline void start_transfer(struct ohs900 *ohs900)
++{
++	if (ohs900->port1 & (1 << USB_PORT_FEAT_SUSPEND))
++		return;
++	if (ohs900->active_a == NULL) {
++		ohs900->active_a = start(ohs900);
++		if (ohs900->active_a != NULL)
++			ohs900->jiffies_a = jiffies + MIN_JIFFIES;
++	}
++}
++
++static void finish_request(
++	struct ohs900		*ohs900,
++	struct ohs900h_ep	*ep,
++	struct urb		*urb,
++	int			status
++) __releases(ohs900->lock) __acquires(ohs900->lock)
++{
++	unsigned		i;
++
++	urb->hcpriv = NULL;
++
++	if (usb_pipecontrol(urb->pipe))
++		ep->nextpid = USB_PID_SETUP;
++
++	usb_hcd_unlink_urb_from_ep(ohs900_to_hcd(ohs900),urb);
++	spin_unlock(&ohs900->lock);
++	usb_hcd_giveback_urb(ohs900_to_hcd(ohs900), urb, status);
++	spin_lock(&ohs900->lock);
++
++	/* leave active endpoints in the schedule */
++	if (!list_empty(&ep->hep->urb_list))
++		return;
++
++	/* async deschedule? */
++	if (!list_empty(&ep->schedule)) {
++		list_del_init(&ep->schedule);
++		if (ep == ohs900->next_async)
++			ohs900->next_async = NULL;
++		return;
++	}
++
++	/* periodic deschedule */
++	DBG("deschedule qh%d/%p branch %d\n", ep->period, ep, ep->branch);
++	for (i = ep->branch; i < PERIODIC_SIZE; i += ep->period) {
++		struct ohs900h_ep	*temp;
++		struct ohs900h_ep	**prev = &ohs900->periodic[i];
++
++		while (*prev && ((temp = *prev) != ep))
++			prev = &temp->next;
++		if (*prev)
++			*prev = ep->next;
++		ohs900->load[i] -= ep->load;
++	}	
++	ep->branch = PERIODIC_SIZE;
++	ohs900->periodic_count--;
++	ohs900_to_hcd(ohs900)->self.bandwidth_allocated
++		-= ep->load / ep->period;
++	if (ep == ohs900->next_periodic)
++		ohs900->next_periodic = ep->next;
++
++	/* we might turn SOFs back on again for the async schedule */
++	if (ohs900->periodic_count == 0)
++		sofirq_off(ohs900);
++}
++
++static void
++done(struct ohs900 *ohs900, struct ohs900h_ep *ep)
++{
++	u8			status;
++	struct urb		*urb;
++	int			urbstat = -EINPROGRESS;
++
++	if (unlikely(!ep))
++		return;
++
++	status = ohs900_read(ohs900, OHS900_HRXSTATREG);
++
++	urb = container_of(ep->hep->urb_list.next, struct urb, urb_list);
++
++	/* we can safely ignore NAKs */
++	if (status & OHS900_STATMASK_NAK_RXED) {
++		// PACKET("...NAK qh%p\n", ep);
++		if (!ep->period)
++			ep->nak_count++;
++		ep->error_count = 0;
++
++	/* ACK, or IN with no errors, advances transfer, toggle, and maybe queue */
++	} else if (status & OHS900_STATMASK_ACK_RXED
++			|| ((status & ~OHS900_STATMASK_DATA_SEQ) == 0) ) {
++		struct usb_device	*udev = urb->dev;
++		int			len;
++		unsigned char		*buf;
++
++		/* urb->iso_frame_desc is currently ignored here... */
++
++		ep->nak_count = ep->error_count = 0;
++		switch (ep->nextpid) {
++		case USB_PID_OUT:
++			// PACKET("...ACK/out qh%p\n", ep);
++			urb->actual_length += ep->length;
++			usb_dotoggle(udev, ep->epnum, 1);
++			if (urb->actual_length
++					== urb->transfer_buffer_length) {
++				if (usb_pipecontrol(urb->pipe))
++					ep->nextpid = USB_PID_ACK;
++
++				/* some bulk protocols terminate OUT transfers
++				 * by a short packet, using ZLPs not padding.
++				 */
++				else if (ep->length < ep->maxpacket
++						|| !(urb->transfer_flags
++							& URB_ZERO_PACKET))
++					urbstat = 0;
++			}
++			break;
++		case USB_PID_IN:
++			// PACKET("...ACK/in qh%p\n", ep);
++			buf = urb->transfer_buffer + urb->actual_length;
++			prefetchw(buf);
++			len = ohs900_read(ohs900, OHS900_RXFIFOCNTLSBREG) 
++					+ (ohs900_read(ohs900,
++					OHS900_RXFIFOCNTMSBREG) << 8);
++			
++			if (len > ep->length) {
++				len = ep->length;
++				urbstat = -EOVERFLOW;
++			}
++			urb->actual_length += len;
++			ohs900_read_buf(ohs900, OHS900_HOST_RXFIFO_DATA,
++					buf, len);
++			usb_dotoggle(udev, ep->epnum, 0);
++			if (urbstat == -EINPROGRESS &&
++				(len < ep->maxpacket ||
++					urb->actual_length ==
++					urb->transfer_buffer_length)) {
++				if (usb_pipecontrol(urb->pipe))
++					ep->nextpid = USB_PID_ACK;
++				else
++					urbstat = 0;
++			}
++			break;
++		case USB_PID_SETUP:
++			// PACKET("...ACK/setup qh%p\n", ep);
++			if (urb->transfer_buffer_length == urb->actual_length)
++				ep->nextpid = USB_PID_ACK;
++			else if (usb_pipeout(urb->pipe)) {
++				usb_settoggle(udev, 0, 1, 1);
++				ep->nextpid = USB_PID_OUT;
++			} else {
++				usb_settoggle(udev, 0, 0, 1);
++				ep->nextpid = USB_PID_IN;
++			}
++			break;
++		case USB_PID_ACK:
++			// PACKET("...ACK/status qh%p\n", ep);
++			urbstat = 0;
++			break;
++		}
++
++	/* STALL stops all transfers */
++	} else if (status & OHS900_STATMASK_STALL_RXED) {
++		PACKET("...STALL qh%p\n", ep);
++		ep->nak_count = ep->error_count = 0;
++		urbstat = -EPIPE;
++
++	/* error? retry, until "3 strikes" */
++	} else if (++ep->error_count >= 3) {
++		if (status & OHS900_STATMASK_RX_TMOUT)
++			urbstat = -ETIME;
++		else if (status & OHS900_STATMASK_RX_OVF)
++			urbstat = -EOVERFLOW;
++		else
++			urbstat = -EPROTO;
++		ep->error_count = 0;
++		PACKET("...3STRIKES %02x qh%p stat %d\n",
++				status, ep, urbstat);
++	}
++
++	if (urbstat != -EINPROGRESS || urb->unlinked)
++		finish_request(ohs900, ep, urb, urbstat);
++}
++
++static inline u8 checkdone(struct ohs900 *ohs900)
++{
++	u8	ctl;
++	u8	irqstat = 0;
++
++	if (ohs900->active_a && time_before_eq(ohs900->jiffies_a, jiffies)) {
++		ctl = ohs900_read(ohs900, OHS900_HOST_TX_CTLREG);
++		if (ctl & OHS900_HCTLMASK_TRANS_REQ)
++			ohs900_write(ohs900, OHS900_HOST_TX_CTLREG, 0);
++		DBG("%s DONE_A: ctrl %02x sts %02x\n",
++			(ctl & OHS900_HCTLMASK_TRANS_REQ) ? "timeout" : "lost",
++			ctl,
++			ohs900_read(ohs900, OHS900_HRXSTATREG));
++		irqstat |= OHS900_INTMASK_TRANS_DONE;
++	}
++	return irqstat;
++}
++
++static irqreturn_t ohs900h_irq(struct usb_hcd *hcd)
++{
++	struct ohs900	*ohs900 = hcd_to_ohs900(hcd);
++	u8		irqstat;
++	irqreturn_t	ret = IRQ_NONE;
++	unsigned	retries = 5;
++
++	//printk("Entering ohs900h_irq\n");
++	spin_lock(&ohs900->lock);
++
++retry:
++	irqstat = ohs900_read(ohs900, OHS900_IRQ_STATUS);
++	if (irqstat) {
++		ohs900_write(ohs900, OHS900_IRQ_STATUS, irqstat);
++		irqstat &= ohs900->irq_enable;
++	}
++
++#ifdef	QUIRK2
++	/* this may no longer be necessary ... */
++	if (irqstat == 0) {
++		irqstat = checkdone(ohs900);
++		if (irqstat)
++			ohs900->stat_lost++;
++	}
++#endif
++
++	/* USB packets, not necessarily handled in the order they're
++	 * issued ... that's fine if they're different endpoints.
++	 */
++	if (irqstat & OHS900_INTMASK_TRANS_DONE) {
++		done(ohs900, ohs900->active_a);
++		ohs900->active_a = NULL;
++		ohs900->stat_a++;
++	}
++
++
++	if (irqstat & OHS900_INTMASK_SOFINTR) {
++		unsigned index;
++
++		index = ohs900->frame++ % (PERIODIC_SIZE - 1);
++		ohs900->stat_sof++;
++
++		/* be graceful about almost-inevitable periodic schedule
++		 * overruns:  continue the previous frame's transfers iff
++		 * this one has nothing scheduled.
++		 */
++		if (ohs900->next_periodic) {
++			// ERR("overrun to slot %d\n", index);
++			ohs900->stat_overrun++;
++		}
++		if (ohs900->periodic[index])
++			ohs900->next_periodic = ohs900->periodic[index];
++	}
++
++	/* khubd manages debouncing and wakeup */
++	if (irqstat & OHS900_INTMASK_INSRMV) {
++		ohs900->stat_insrmv++;
++
++		/* most stats are reset for each VBUS session */
++		ohs900->stat_wake = 0;
++		ohs900->stat_sof = 0;
++		ohs900->stat_a = 0;
++		ohs900->stat_b = 0;
++		ohs900->stat_lost = 0;
++
++		ohs900->ctrl1 = 0;
++		ohs900_write(ohs900, OHS900_TXLINECTLREG, ohs900->ctrl1);
++
++		ohs900->irq_enable = OHS900_INTMASK_INSRMV;
++		ohs900_write(ohs900, OHS900_IRQ_ENABLE, ohs900->irq_enable);
++
++		/* usbcore nukes other pending transactions on disconnect */
++		if (ohs900->active_a) {
++			ohs900_write(ohs900, OHS900_HOST_TX_CTLREG, 0);
++			finish_request(ohs900, ohs900->active_a,
++				container_of(ohs900->active_a
++					     ->hep->urb_list.next,
++					     struct urb, urb_list),
++				       -ESHUTDOWN);
++			ohs900->active_a = NULL;
++		}
++
++
++		/* port status seems wierd until after reset, so
++		 * force the reset and make khubd clean up later.
++		 */
++		ohs900->port1 |= (1 << USB_PORT_FEAT_C_CONNECTION)
++				| (1 << USB_PORT_FEAT_CONNECTION);
++
++	} else if (irqstat & OHS900_INTMASK_RESUME_DET) {
++		if (ohs900->port1 & (1 << USB_PORT_FEAT_SUSPEND)) {
++			DBG("wakeup\n");
++			ohs900->port1 |= 1 << USB_PORT_FEAT_C_SUSPEND;
++			ohs900->stat_wake++;
++		} else
++			irqstat &= ~OHS900_INTMASK_RESUME_DET;
++	}
++
++	if (irqstat) {
++		if (ohs900->port1 & (1 << USB_PORT_FEAT_ENABLE))
++			start_transfer(ohs900);
++		ret = IRQ_HANDLED;
++		if (retries--)
++			goto retry;
++	}
++
++	if (ohs900->periodic_count == 0 && list_empty(&ohs900->async)) 
++		sofirq_off(ohs900);
++	ohs900_write(ohs900, OHS900_IRQ_ENABLE, ohs900->irq_enable);
++
++	spin_unlock(&ohs900->lock);
++
++	return ret;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* usb 1.1 says max 90% of a frame is available for periodic transfers.
++ * this driver doesn't promise that much since it's got to handle an
++ * IRQ per packet; irq handling latencies also use up that time.
++ */
++#define	MAX_PERIODIC_LOAD	500	/* out of 1000 usec */
++
++static int balance(struct ohs900 *ohs900, u16 period, u16 load)
++{
++	int	i, branch = -ENOSPC;
++
++	/* search for the least loaded schedule branch of that period
++	 * which has enough bandwidth left unreserved.
++	 */
++	for (i = 0; i < period ; i++) {
++		if (branch < 0 || ohs900->load[branch] > ohs900->load[i]) {
++			int	j;
++
++			for (j = i; j < PERIODIC_SIZE; j += period) {
++				if ((ohs900->load[j] + load)
++						> MAX_PERIODIC_LOAD)
++					break;
++			}
++			if (j < PERIODIC_SIZE)
++				continue;
++			branch = i; 
++		}
++	}
++	return branch;
++}
++
++/*-------------------------------------------------------------------------*/
++
++static int ohs900h_urb_enqueue(
++	struct usb_hcd	    *hcd,
++	struct urb	    *urb,
++	gfp_t		    mem_flags
++) {
++	struct ohs900		*ohs900 = hcd_to_ohs900(hcd);
++	struct usb_device	*udev = urb->dev;
++	unsigned int		pipe = urb->pipe;
++	int			is_out = !usb_pipein(pipe);
++	int			type = usb_pipetype(pipe);
++	int			epnum = usb_pipeendpoint(pipe);
++	struct ohs900h_ep	*ep = NULL;
++	unsigned long		flags;
++	int			i;
++	int			retval;
++	struct usb_host_endpoint	*hep = urb->ep;
++
++#ifdef	DISABLE_ISO
++	if (type == PIPE_ISOCHRONOUS)
++		return -ENOSPC;
++#endif
++
++	/* avoid all allocations within spinlocks */
++	if (!hep->hcpriv)
++	  ep = kzalloc(sizeof *ep, mem_flags);
++
++	spin_lock_irqsave(&ohs900->lock, flags);
++
++	/* don't submit to a dead or disabled port */
++	if (!(ohs900->port1 & (1 << USB_PORT_FEAT_ENABLE))
++			|| !HC_IS_RUNNING(hcd->state)) {
++		retval = -ENODEV;
++		kfree(ep);
++		goto fail_not_linked;
++	}
++	retval = usb_hcd_link_urb_to_ep(hcd, urb);
++	if (retval) {
++		kfree(ep);
++		goto fail_not_linked;
++	}
++
++	if (hep->hcpriv) {
++		ep = hep->hcpriv;
++	} else if (!ep) {
++		retval = -ENOMEM;
++		goto fail;
++
++	} else {
++		INIT_LIST_HEAD(&ep->schedule);
++		ep->udev = udev;
++		ep->epnum = epnum;
++		ep->maxpacket = usb_maxpacket(udev, urb->pipe, is_out);
++		ep->defctrl = OHS900_HCTLMASK_TRANS_REQ;
++		usb_settoggle(udev, epnum, is_out, 0);
++
++		if (type == PIPE_CONTROL)
++			ep->nextpid = USB_PID_SETUP;
++		else if (is_out)
++			ep->nextpid = USB_PID_OUT;
++		else
++			ep->nextpid = USB_PID_IN;
++
++		if (ep->maxpacket > H_MAXPACKET) {
++			/* iso packets up to 64 bytes could work... */
++			DBG("dev %d ep%d maxpacket %d\n",
++				udev->devnum, epnum, ep->maxpacket);
++			retval = -EINVAL;
++			goto fail;
++		}
++
++		if (udev->speed == USB_SPEED_LOW) {
++			/* send preamble for external hub? */
++			if (ohs900->ctrl1 & OHS900_TXLCTL_MASK_FS_RATE)
++				ep->defctrl |= OHS900_HCTLMASK_PREAMBLE_EN;
++		}
++		switch (type) {
++		case PIPE_ISOCHRONOUS:
++		case PIPE_INTERRUPT:
++			if (urb->interval > PERIODIC_SIZE)
++				urb->interval = PERIODIC_SIZE;
++			ep->period = urb->interval;
++			ep->branch = PERIODIC_SIZE;
++			if (type == PIPE_ISOCHRONOUS)
++				ep->defctrl |= OHS900_HCTLMASK_ISO_EN;
++			ep->load = usb_calc_bus_time(udev->speed, !is_out,
++				(type == PIPE_ISOCHRONOUS),
++				usb_maxpacket(udev, pipe, is_out))
++					/ 1000;
++			break;
++		}
++
++		hep->hcpriv = ep;
++		ep->hep = hep;
++	}
++
++	/* maybe put endpoint into schedule */
++	switch (type) {
++	case PIPE_CONTROL:
++	case PIPE_BULK:
++		if (list_empty(&ep->schedule))
++			list_add_tail(&ep->schedule, &ohs900->async);
++		break;
++	case PIPE_ISOCHRONOUS:
++	case PIPE_INTERRUPT:
++		urb->interval = ep->period;
++		if (ep->branch < PERIODIC_SIZE)
++			break;
++
++		retval = balance(ohs900, ep->period, ep->load);
++		if (retval < 0)
++			goto fail;
++		ep->branch = retval;
++		retval = 0;
++		urb->start_frame = (ohs900->frame & (PERIODIC_SIZE - 1))
++					+ ep->branch;
++
++		/* sort each schedule branch by period (slow before fast)
++		 * to share the faster parts of the tree without needing
++		 * dummy/placeholder nodes
++		 */
++		DBG("schedule qh%d/%p branch %d\n", ep->period, ep, ep->branch);
++		for (i = ep->branch; i < PERIODIC_SIZE; i += ep->period) {
++			struct ohs900h_ep	**prev = &ohs900->periodic[i];
++			struct ohs900h_ep	*here = *prev;
++
++			while (here && ep != here) {
++				if (ep->period > here->period)
++					break;
++				prev = &here->next;
++				here = *prev;
++			}
++			if (ep != here) {
++				ep->next = here;
++				*prev = ep;
++			}
++			ohs900->load[i] += ep->load;
++		}
++		ohs900->periodic_count++;
++		hcd->self.bandwidth_allocated += ep->load / ep->period;
++		sofirq_on(ohs900);
++	}
++
++	urb->hcpriv = hep;
++
++	start_transfer(ohs900);
++	ohs900_write(ohs900, OHS900_IRQ_ENABLE, ohs900->irq_enable);
++fail:
++	if (retval)
++		usb_hcd_unlink_urb_from_ep(hcd,urb);
++fail_not_linked:
++	spin_unlock_irqrestore(&ohs900->lock, flags);
++	return retval;
++}
++
++static int ohs900h_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
++{
++	struct ohs900		*ohs900 = hcd_to_ohs900(hcd);
++	struct usb_host_endpoint *hep;
++	unsigned long		flags;
++	struct ohs900h_ep	*ep;
++	int			retval;
++
++	spin_lock_irqsave(&ohs900->lock, flags);
++	retval = usb_hcd_check_unlink_urb(hcd, urb, status);
++	if (retval)
++		goto fail;
++
++	hep = hep->hcpriv;
++	if (ep) {
++		/* finish right away if this urb can't be active ...
++		 * note that some drivers wrongly expect delays
++		 */
++		if (ep->hep->urb_list.next != &urb->urb_list) {
++			/* not front of queue?  never active */
++
++		/* for active transfers, we expect an IRQ */
++		} else if (ohs900->active_a == ep) {
++			if (time_before_eq(ohs900->jiffies_a, jiffies)) {
++				/* happens a lot with lowspeed?? */
++				DBG("giveup on DONE_A: ctrl %02x sts %02x\n",
++					ohs900_read(ohs900,OHS900_HOST_TX_CTLREG),
++					ohs900_read(ohs900,OHS900_HRXSTATREG));
++				ohs900_write(ohs900, OHS900_HOST_TX_CTLREG,0);
++				ohs900->active_a = NULL;
++			} else
++				urb = NULL;
++
++		} else {
++			/* front of queue for inactive endpoint */
++		}
++
++		if (urb)
++			finish_request(ohs900, ep, urb, 0);
++		else
++			VDBG("dequeue, urb %p active %s; wait4irq\n", urb,
++				(ohs900->active_a == ep) ? "A" : "B");
++	} else
++	  
++fail:
++	spin_unlock_irqrestore(&ohs900->lock, flags);
++	return retval;
++}
++
++static void
++ohs900h_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
++{
++	struct ohs900h_ep	*ep = hep->hcpriv;
++
++	if (!ep)
++		return;
++
++	/* assume we'd just wait for the irq */
++	if (!list_empty(&hep->urb_list))
++	    msleep(3);
++	if (!list_empty(&hep->urb_list))
++	    WARNING("ep %p not empty?\n", ep);
++
++	kfree(ep);
++	hep->hcpriv = NULL;
++}
++
++static int
++ohs900h_get_frame(struct usb_hcd *hcd)
++{
++	struct ohs900 *ohs900 = hcd_to_ohs900(hcd);
++
++	/* wrong except while periodic transfers are scheduled;
++	 * never matches the on-the-wire frame;
++	 * subject to overruns.
++	 */
++	return ohs900->frame;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/* the virtual root hub timer IRQ checks for hub status */
++static int
++ohs900h_hub_status_data(struct usb_hcd *hcd, char *buf)
++{
++	struct ohs900 *ohs900 = hcd_to_ohs900(hcd);
++#ifdef	QUIRK3
++	unsigned long flags;
++
++	/* non-SMP HACK: use root hub timer as i/o watchdog
++	 * this seems essential when SOF IRQs aren't in use...
++	 */
++	local_irq_save(flags);
++	if (!timer_pending(&ohs900->timer)) {
++		if (ohs900h_irq( /* ~0, */ hcd) != IRQ_NONE)
++			ohs900->stat_lost++;
++	}
++	local_irq_restore(flags);
++#endif
++
++	if (!(ohs900->port1 & (0xffff << 16)))
++		return 0;
++
++	/* tell khubd port 1 changed */
++	*buf = (1 << 1);
++	return 1;
++}
++
++static void
++ohs900h_hub_descriptor (
++	struct ohs900			*ohs900,
++	struct usb_hub_descriptor	*desc
++) {
++	u16		temp = 0;
++
++	desc->bDescriptorType = 0x29;
++	desc->bHubContrCurrent = 0;
++
++	desc->bNbrPorts = 1;
++	desc->bDescLength = 9;
++
++	/* per-port power switching (gang of one!), or none */
++	desc->bPwrOn2PwrGood = 0;
++	if (ohs900->board && ohs900->board->port_power) {
++		desc->bPwrOn2PwrGood = ohs900->board->potpg;
++		if (!desc->bPwrOn2PwrGood)
++			desc->bPwrOn2PwrGood = 10;
++		temp = 0x0001;
++	} else
++		temp = 0x0002;
++
++	/* no overcurrent errors detection/handling */
++	temp |= 0x0010;
++
++	desc->wHubCharacteristics = cpu_to_le16(temp);
++
++	/* two bitmaps:  ports removable, and legacy PortPwrCtrlMask */
++	desc->bitmap[0] = 0 << 1;
++	desc->bitmap[1] = ~0;
++}
++
++static void
++ohs900h_timer(unsigned long _ohs900)
++{
++	struct ohs900 	*ohs900 = (void *) _ohs900;
++	unsigned long	flags;
++	u8		irqstat;
++	u8		signaling = ohs900->ctrl1 & OHS900_TXLCTL_MASK_LINE_CTRL_BITS;
++	const u32	mask = (1 << USB_PORT_FEAT_CONNECTION)
++				| (1 << USB_PORT_FEAT_ENABLE)
++				| (1 << USB_PORT_FEAT_LOWSPEED);
++	u8		sofEnReg = 0;
++
++	spin_lock_irqsave(&ohs900->lock, flags);
++
++	/* stop special signaling */
++	ohs900->ctrl1 &= ~OHS900_TXLCTL_MASK_FORCE;
++	ohs900_write(ohs900, OHS900_TXLINECTLREG, ohs900->ctrl1);
++	udelay(3);
++
++	irqstat = ohs900_read(ohs900, OHS900_IRQ_STATUS);
++
++	switch (signaling) {
++	case OHS900_TXLCTL_MASK_SE0:
++		DBG("end reset\n");
++		ohs900->port1 = (1 << USB_PORT_FEAT_C_RESET)
++				| (1 << USB_PORT_FEAT_POWER);
++		ohs900->ctrl1 = 0;
++		/* don't wrongly ack RD */
++		if (irqstat & OHS900_INTMASK_INSRMV)
++			irqstat &= ~OHS900_INTMASK_RESUME_DET;
++		break;
++	case OHS900_TXLCTL_MASK_FS_K:
++		DBG("end resume\n");
++		ohs900->port1 &= ~(1 << USB_PORT_FEAT_SUSPEND);
++		break;
++	default:
++		DBG("odd timer signaling: %02x\n", signaling);
++		break;
++	}
++	ohs900_write(ohs900, OHS900_IRQ_STATUS, irqstat);
++
++	//if (irqstat & OHS900_INTMASK_RESUME_DET) {...
++	if (ohs900_read(ohs900, OHS900_RXCONNSTATEREG) == OHS900_DISCONNECT_STATE) {
++		/* usbcore nukes all pending transactions on disconnect */
++		if (ohs900->port1 & (1 << USB_PORT_FEAT_CONNECTION))
++			ohs900->port1 |= (1 << USB_PORT_FEAT_C_CONNECTION)
++					| (1 << USB_PORT_FEAT_C_ENABLE);
++		ohs900->port1 &= ~mask;
++		ohs900->irq_enable = OHS900_INTMASK_INSRMV;
++	} else {
++		ohs900->port1 |= mask;
++		if (ohs900_read(ohs900, OHS900_RXCONNSTATEREG) & OHS900_FS_CONN_STATE)
++			ohs900->port1 &= ~(1 << USB_PORT_FEAT_LOWSPEED);
++		ohs900->irq_enable = OHS900_INTMASK_INSRMV | OHS900_INTMASK_RESUME_DET;
++	}
++	//...presumably ?...}
++	if (ohs900->port1 & (1 << USB_PORT_FEAT_CONNECTION)) {
++
++		ohs900->irq_enable |= OHS900_INTMASK_TRANS_DONE;
++		if (ohs900->port1 & (1 << USB_PORT_FEAT_LOWSPEED)) {
++			ohs900->ctrl1 &= ~OHS900_TXLCTL_MASK_FS_POL;
++			ohs900->ctrl1 &= ~OHS900_TXLCTL_MASK_FS_RATE;
++		}
++		else {
++			ohs900->ctrl1 |= OHS900_TXLCTL_MASK_FS_POL;
++			ohs900->ctrl1 |= OHS900_TXLCTL_MASK_FS_RATE;
++		}
++
++		/* start SOFs flowing, kickstarting with A registers */
++		sofEnReg = OHS900_MASK_SOF_ENA;		
++
++		/* Set default device address */
++		ohs900_write(ohs900, OHS900_TXADDRREG, 0); 
++
++		/* khubd provides debounce delay */
++	} else {
++		ohs900->ctrl1 = 0;
++	}
++	ohs900_write(ohs900, OHS900_TXLINECTLREG, ohs900->ctrl1);
++	ohs900_write(ohs900, OHS900_SOFENREG, sofEnReg);
++
++	/* reenable irqs */
++	ohs900_write(ohs900, OHS900_IRQ_ENABLE, ohs900->irq_enable);
++	spin_unlock_irqrestore(&ohs900->lock, flags);
++}
++
++static int
++ohs900h_hub_control(
++	struct usb_hcd	*hcd,
++	u16		typeReq,
++	u16		wValue,
++	u16		wIndex,
++	char		*buf,
++	u16		wLength
++) {
++	struct ohs900	*ohs900 = hcd_to_ohs900(hcd);
++	int		retval = 0;
++	unsigned long	flags;
++
++	spin_lock_irqsave(&ohs900->lock, flags);
++
++	switch (typeReq) {
++	case ClearHubFeature:
++	case SetHubFeature:
++		switch (wValue) {
++		case C_HUB_OVER_CURRENT:
++		case C_HUB_LOCAL_POWER:
++			break;
++		default:
++			goto error;
++		}
++		break;
++	case ClearPortFeature:
++		if (wIndex != 1 || wLength != 0)
++			goto error;
++
++		switch (wValue) {
++		case USB_PORT_FEAT_ENABLE:
++			ohs900->port1 &= (1 << USB_PORT_FEAT_POWER);
++			ohs900->ctrl1 = 0;
++			ohs900_write(ohs900, OHS900_SOFENREG, 0);
++			ohs900_write(ohs900, OHS900_TXLINECTLREG, ohs900->ctrl1);
++			ohs900->irq_enable = OHS900_INTMASK_INSRMV;
++			ohs900_write(ohs900, OHS900_IRQ_ENABLE,
++						ohs900->irq_enable);
++			break;
++		case USB_PORT_FEAT_SUSPEND:
++			if (!(ohs900->port1 & (1 << USB_PORT_FEAT_SUSPEND)))
++				break;
++
++			/* 20 msec of resume/K signaling, other irqs blocked */
++			DBG("start resume...\n");
++			ohs900->irq_enable = 0;
++			ohs900_write(ohs900, OHS900_IRQ_ENABLE,
++						ohs900->irq_enable);
++			ohs900->ctrl1 |= OHS900_TXLCTL_MASK_FS_K;
++			ohs900_write(ohs900, OHS900_TXLINECTLREG, ohs900->ctrl1);
++
++			mod_timer(&ohs900->timer, jiffies
++					+ msecs_to_jiffies(20));
++			break;
++		case USB_PORT_FEAT_POWER:
++			port_power(ohs900, 0);
++			break;
++		case USB_PORT_FEAT_C_ENABLE:
++		case USB_PORT_FEAT_C_SUSPEND:
++		case USB_PORT_FEAT_C_CONNECTION:
++		case USB_PORT_FEAT_C_OVER_CURRENT:
++		case USB_PORT_FEAT_C_RESET:
++			break;
++		default:
++			goto error;
++		}
++		ohs900->port1 &= ~(1 << wValue);
++		break;
++	case GetHubDescriptor:
++		ohs900h_hub_descriptor(ohs900, (struct usb_hub_descriptor *) buf);
++		break;
++	case GetHubStatus:
++		*(__le32 *) buf = cpu_to_le32(0);
++		break;
++	case GetPortStatus:
++		if (wIndex != 1)
++			goto error;
++		*(__le32 *) buf = cpu_to_le32(ohs900->port1);
++
++#ifndef	VERBOSE
++	if (*(u16*)(buf+2))	/* only if wPortChange is interesting */
++#endif
++		DBG("GetPortStatus %08x\n", ohs900->port1);
++		break;
++	case SetPortFeature:
++		if (wIndex != 1 || wLength != 0)
++			goto error;
++		switch (wValue) {
++		case USB_PORT_FEAT_SUSPEND:
++			if (ohs900->port1 & (1 << USB_PORT_FEAT_RESET))
++				goto error;
++			if (!(ohs900->port1 & (1 << USB_PORT_FEAT_ENABLE)))
++				goto error;
++
++			DBG("suspend...\n");
++			ohs900_write(ohs900, OHS900_SOFENREG, 0);
++			break;
++		case USB_PORT_FEAT_POWER:
++			port_power(ohs900, 1);
++			break;
++		case USB_PORT_FEAT_RESET:
++			if (ohs900->port1 & (1 << USB_PORT_FEAT_SUSPEND))
++				goto error;
++			if (!(ohs900->port1 & (1 << USB_PORT_FEAT_POWER)))
++				break;
++
++			/* 50 msec of reset/SE0 signaling, irqs blocked */
++			ohs900->irq_enable = 0;
++			ohs900_write(ohs900, OHS900_IRQ_ENABLE,
++						ohs900->irq_enable);
++			ohs900_write(ohs900, OHS900_SOFENREG, 0);
++			ohs900->ctrl1 = OHS900_TXLCTL_MASK_SE0;
++			ohs900_write(ohs900, OHS900_TXLINECTLREG, ohs900->ctrl1);
++			ohs900->port1 |= (1 << USB_PORT_FEAT_RESET);
++			mod_timer(&ohs900->timer, jiffies
++					+ msecs_to_jiffies(50));
++			break;
++		default:
++			goto error;
++		}
++		ohs900->port1 |= 1 << wValue;
++		break;
++
++	default:
++error:
++		/* "protocol stall" on error */
++		retval = -EPIPE;
++	}
++
++	spin_unlock_irqrestore(&ohs900->lock, flags);
++	return retval;
++}
++
++#ifdef	CONFIG_PM
++
++static int
++ohs900h_bus_suspend(struct usb_hcd *hcd)
++{
++	// SOFs off
++	DBG("%s\n", __func__);
++	return 0;
++}
++
++static int
++ohs900h_bus_resume(struct usb_hcd *hcd)
++{
++	// SOFs on
++	DBG("%s\n", __func__);
++	return 0;
++}
++
++#else
++
++#define	ohs900h_bus_suspend	NULL
++#define	ohs900h_bus_resume	NULL
++
++#endif
++
++
++/*-------------------------------------------------------------------------*/
++
++#ifdef STUB_DEBUG_FILE
++
++static inline void create_debug_file(struct ohs900 *ohs900) { }
++static inline void remove_debug_file(struct ohs900 *ohs900) { }
++
++#else
++
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++
++static void dump_irq(struct seq_file *s, char *label, u8 mask)
++{
++	seq_printf(s, "%s %02x%s%s%s%s\n", label, mask,
++		(mask & OHS900_INTMASK_TRANS_DONE) ? " done" : "",
++		(mask & OHS900_INTMASK_SOFINTR) ? " sof" : "",
++		(mask & OHS900_INTMASK_INSRMV) ? " ins/rmv" : "",
++		(mask & OHS900_INTMASK_RESUME_DET) ? " rd" : "");
++}
++
++static int proc_ohs900h_show(struct seq_file *s, void *unused)
++{
++	struct ohs900		*ohs900 = s->private;
++	struct ohs900h_ep	*ep;
++	unsigned		i;
++	u8	t;
++	
++	seq_printf(s, "%s\n%s version %s\nportstatus[1] = %08x\n",
++		ohs900_to_hcd(ohs900)->product_desc,
++		hcd_name, DRIVER_VERSION,
++		ohs900->port1);
++
++	seq_printf(s, "insert/remove: %ld\n", ohs900->stat_insrmv);
++	seq_printf(s, "current session:  done_a %ld done_b %ld "
++			"wake %ld sof %ld overrun %ld lost %ld\n\n",
++		ohs900->stat_a, ohs900->stat_b,
++		ohs900->stat_wake, ohs900->stat_sof,
++		ohs900->stat_overrun, ohs900->stat_lost);
++
++	spin_lock_irq(&ohs900->lock);
++
++	t = ohs900_read(ohs900, OHS900_TXLINECTLREG);
++
++
++
++
++	seq_printf(s, "ctrl1 %02x%s%s%s%s\n", t,
++		(ohs900_read(ohs900, OHS900_SOFENREG)) ? " sofgen" : "",
++		({char *s; switch (t & OHS900_TXLCTL_MASK_LINE_CTRL_BITS) {
++		case OHS900_TXLCTL_MASK_NORMAL: s = ""; break;
++		case OHS900_TXLCTL_MASK_SE0: s = " se0/reset"; break;
++		case OHS900_TXLCTL_MASK_FS_K: s = " FS k/resume"; break;
++		case OHS900_TXLCTL_MASK_FS_J: s = " FS J/resume"; break;
++		default: s = " not valid ?"; break;
++		}; s; }),
++		(t & OHS900_TXLCTL_MASK_FS_POL) ? " fs pol" : " ls pol ",
++		(t & OHS900_TXLCTL_MASK_FS_RATE) ? " fs rate" : " ls rate ");
++
++	dump_irq(s, "irq_enable",
++			ohs900_read(ohs900, OHS900_IRQ_ENABLE));
++	dump_irq(s, "irq_status",
++			ohs900_read(ohs900, OHS900_IRQ_STATUS));
++	seq_printf(s, "frame clocks remaining:  %d\n",
++			ohs900_read(ohs900, OHS900_SOFTMRREG) << 6);
++
++
++	
++	seq_printf(s, "A: qh%p ctl %02x sts %02x\n", ohs900->active_a,
++		ohs900_read(ohs900, OHS900_HOST_TX_CTLREG),
++		ohs900_read(ohs900, OHS900_HRXSTATREG));
++	seq_printf(s, "\n");
++	list_for_each_entry (ep, &ohs900->async, schedule) {
++		struct urb		*urb;
++
++		seq_printf(s, "%s%sqh%p, ep%d%s, maxpacket %d"
++					" nak %d err %d\n",
++			(ep == ohs900->active_a) ? "(A) " : "",
++			(ep == ohs900->active_b) ? "(B) " : "",
++			ep, ep->epnum,
++			({ char *s; switch (ep->nextpid) {
++			case USB_PID_IN: s = "in"; break;
++			case USB_PID_OUT: s = "out"; break;
++			case USB_PID_SETUP: s = "setup"; break;
++			case USB_PID_ACK: s = "status"; break;
++			default: s = "?"; break;
++			}; s;}),
++			ep->maxpacket,
++			ep->nak_count, ep->error_count);
++		list_for_each_entry (urb, &ep->hep->urb_list, urb_list) {
++			seq_printf(s, "  urb%p, %d/%d\n", urb,
++				urb->actual_length,
++				urb->transfer_buffer_length);
++		}
++	}
++	if (!list_empty(&ohs900->async))
++		seq_printf(s, "\n");
++
++	seq_printf(s, "periodic size= %d\n", PERIODIC_SIZE);
++
++	for (i = 0; i < PERIODIC_SIZE; i++) {
++		ep = ohs900->periodic[i];
++		if (!ep)
++			continue;
++		seq_printf(s, "%2d [%3d]:\n", i, ohs900->load[i]);
++
++		/* DUMB: prints shared entries multiple times */
++		do {
++			seq_printf(s,
++				"   %s%sqh%d/%p (%sdev%d ep%d%s max %d) "
++					"err %d\n",
++				(ep == ohs900->active_a) ? "(A) " : "",
++				(ep == ohs900->active_b) ? "(B) " : "",
++				ep->period, ep,
++				(ep->udev->speed == USB_SPEED_FULL)
++					? "" : "ls ",
++				ep->udev->devnum, ep->epnum,
++				(ep->epnum == 0) ? ""
++					: ((ep->nextpid == USB_PID_IN)
++						? "in"
++						: "out"),
++				ep->maxpacket, ep->error_count);
++			ep = ep->next;
++		} while (ep);
++	}
++
++	spin_unlock_irq(&ohs900->lock);
++	seq_printf(s, "\n");
++
++	return 0;
++}
++
++static int proc_ohs900h_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, proc_ohs900h_show, PDE(inode)->data);
++}
++
++static const file_operations proc_ops = {
++	.open		= proc_ohs900h_open,
++	.read		= seq_read,
++	.llseek		= seq_lseek,
++	.release	= single_release,
++};
++
++/* expect just one ohs900 per system */
++static const char proc_filename[] = "driver/ohs900";
++
++static void create_debug_file(struct ohs900 *ohs900)
++{
++	ohs900->pde = proc_create_data(proc_filename, 0, NULL, &proc_ops, ohs900)
++}
++
++static void remove_debug_file(struct ohs900 *ohs900)
++{
++	if (ohs900->pde)
++		remove_proc_entry(proc_filename, NULL);
++}
++
++#endif
++
++/*-------------------------------------------------------------------------*/
++
++static void
++ohs900h_stop(struct usb_hcd *hcd)
++{
++	struct ohs900	*ohs900 = hcd_to_ohs900(hcd);
++	unsigned long	flags;
++
++	del_timer_sync(&hcd->rh_timer);
++
++	spin_lock_irqsave(&ohs900->lock, flags);
++	port_power(ohs900, 0);
++	spin_unlock_irqrestore(&ohs900->lock, flags);
++}
++
++static int
++ohs900h_start(struct usb_hcd *hcd)
++{
++	struct ohs900		*ohs900 = hcd_to_ohs900(hcd);
++
++	/* chip has been reset, VBUS power is off */
++
++	hcd->state = HC_STATE_RUNNING;
++
++	if (ohs900->board) {
++		if (!device_can_wakeup(hcd->self.controller))
++			device_init_wakeup(hcd->self.controller,
++					   ohs900->board->can_wakeup);
++		hcd->power_budget = ohs900->board->power * 2;
++	}
++
++	/* enable power and interrupts */
++	port_power(ohs900, 1);
++
++	/* This is necessary to make the controller detect devices
++	 * that are already plugged in during initialisation. It
++	 * causes the hub driver to do a reset, which triggers
++	 * checking for an attached device. */
++	ohs900->port1 |= (1 << USB_PORT_FEAT_C_CONNECTION)
++		| (1 << USB_PORT_FEAT_CONNECTION);
++
++	return 0;
++}
++
++/*-------------------------------------------------------------------------*/
++
++static struct hc_driver ohs900h_hc_driver = {
++	.description =		hcd_name,
++	.hcd_priv_size =	sizeof(struct ohs900),
++
++	/*
++	 * generic hardware linkage
++	 */
++	.irq =			ohs900h_irq,
++	.flags =		HCD_USB11,
++
++	.start =		ohs900h_start,
++	.stop =			ohs900h_stop,
++
++	/*
++	 * managing i/o requests and associated device resources
++	 */
++	.urb_enqueue =		ohs900h_urb_enqueue,
++	.urb_dequeue =		ohs900h_urb_dequeue,
++	.endpoint_disable =	ohs900h_endpoint_disable,
++
++	/*
++	 * periodic schedule support
++	 */
++	.get_frame_number =	ohs900h_get_frame,
++
++	/*
++	 * root hub support
++	 */
++	.hub_status_data =	ohs900h_hub_status_data,
++	.hub_control =		ohs900h_hub_control,
++	.bus_suspend =		ohs900h_bus_suspend,
++	.bus_resume =		ohs900h_bus_resume,
++};
++
++/*-------------------------------------------------------------------------*/
++#define resource_len(r) (((r)->end - (r)->start) + 1)
++
++static int __devexit
++ohs900h_remove(struct platform_device *dev)
++{
++	struct usb_hcd		*hcd = platform_get_drvdata(dev);
++	struct ohs900           *ohs900 = hcd_to_ohs900(hcd);
++	struct resource		*res;
++
++	remove_debug_file(ohs900);
++	usb_remove_hcd(hcd);
++
++	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
++	if (res)
++		iounmap(ohs900->addr_reg);
++
++	usb_put_hcd(hcd);
++	return 0;
++}
++
++
++static int __devinit
++ohs900h_probe(struct platform_device *dev)
++{
++  
++  struct usb_hcd		*hcd;
++	struct ohs900		*ohs900;
++	struct resource		*addr, *data, *ires;
++	int			irq;
++	void __iomem		*addr_reg;
++	int			retval;
++	u8			tmp;
++	u8                      ioaddr = 0;
++	unsigned long		irqflags;
++
++	/* basic sanity checks first.  board-specific init logic should
++	 * have initialized these three resources and probably board
++	 * specific platform_data.  we don't probe for IRQs, and do only
++	 * minimal sanity checking.
++	 */
++
++
++	INFO("driver %s, starting ohs900h_probe\n", hcd_name);
++	ires = platform_get_resource(dev, IORESOURCE_IRQ, 0);
++	if (dev->num_resources < 3 || !ires)
++		return -ENODEV;
++
++	irq = ires->start;
++	irqflags = ires->flags & IRQF_TRIGGER_MASK;
++
++	/* refuse to confuse usbcore */
++	if (dev->dev.dma_mask) {
++		DBG("no we won't dma\n");
++		return -EINVAL;
++	}
++
++	addr = platform_get_resource(dev, IORESOURCE_MEM, 0);
++	INFO("driver %s, ioremap addr->start = 0x%lX, resource_len(addr) = 0x%lx\n",
++		       	hcd_name, (unsigned long)(addr->start), (unsigned long)(resource_len(addr)) );
++			
++	retval = -EBUSY;
++	if (!addr) {
++		addr = platform_get_resource(dev, IORESOURCE_IO, 0);
++		if (!addr)
++			return -ENODEV;
++		ioaddr = 1;
++		INFO("driver %s, setting addr_reg to addr->start == 0x%X\n", hcd_name, addr->start) ;
++		addr_reg = (void __iomem *) (unsigned long) addr->start;
++	} else {
++		addr_reg = ioremap(addr->start, 1);
++		INFO("driver %s, setting addr_reg to ioremap(addr->start = 0x%lX) == 0x%lX\n", hcd_name, (unsigned long)(addr->start), (unsigned long)addr_reg) ;
++		if (addr_reg == NULL) {
++			retval = -ENOMEM;
++			goto err2;
++		}
++	}
++
++	/* allocate and initialize hcd */
++	INFO("driver %s, allocating memory\n", hcd_name);
++	hcd = usb_create_hcd(&ohs900h_hc_driver, &dev->dev, dev_name(&dev->dev));
++	if (!hcd) {
++		retval = -ENOMEM;
++		goto err5;
++	}
++	hcd->rsrc_start = addr->start;
++	ohs900 = hcd_to_ohs900(hcd);
++
++	INFO("driver %s, spin_lock_init\n", hcd_name);
++	spin_lock_init(&ohs900->lock);
++	INIT_LIST_HEAD(&ohs900->async);
++	ohs900->board = dev->dev.platform_data;
++	init_timer(&ohs900->timer);
++	ohs900->timer.function = ohs900h_timer;
++	ohs900->timer.data = (unsigned long) ohs900;
++	ohs900->addr_reg = addr_reg;
++	spin_lock_irq(&ohs900->lock);
++
++	port_power(ohs900, 0);
++	INFO("driver %s, returned from port_power\n", hcd_name);
++	spin_unlock_irq(&ohs900->lock);
++	INFO("driver %s, returned from spin_unlock_irqrestore\n", hcd_name);
++	msleep(200);
++
++	INFO("driver %s, getting hw version\n", hcd_name);
++	tmp = ohs900_read(ohs900, OHS900_HWREVREG);
++	switch (tmp) {
++	case 0x7:
++		hcd->product_desc = "OHS900 v0.7";
++		break;
++	case 0x8:
++		hcd->product_desc = "OHS900 v0.8";
++		break;
++	case 0x10:
++		hcd->product_desc = "OHS900 v1.0";
++		break;
++	case 0x11:
++		hcd->product_desc = "OHS900 v1.1";
++		break;
++	case 0x12:
++		hcd->product_desc = "OHS900 v1.2";
++		break;
++	default:
++		/* reject other chip revisions */
++		DBG("chiprev %02x\n", tmp);
++		retval = -ENXIO;
++		goto err6;
++	}
++	INFO("driver %s, hw version = %d\n", hcd_name, tmp);
++
++	irqflags |= IRQF_SHARED;
++	retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | irqflags);
++	if (retval != 0)
++		goto err6;
++
++	INFO("%s, irq %d\n", hcd->product_desc, irq);
++
++	create_debug_file(ohs900);
++	return retval;
++ err6:
++	usb_put_hcd(hcd);
++ err5:
++	if (!ioaddr)
++		iounmap(addr_reg);
++ err2:
++	DBG("init error, %d\n", retval);
++	return retval;
++}
++
++
++#ifdef	CONFIG_PM
++
++/* for this device there's no useful distinction between the controller
++ * and its root hub, except that the root hub only gets direct PM calls 
++ * when CONFIG_USB_SUSPEND is enabled.
++ */
++
++static int
++ohs900h_suspend(struct platform_device *dev)
++{
++	struct ohs900	*ohs900 = dev_get_drvdata(dev);
++	int		retval = 0;
++
++	if (phase != SUSPEND_POWER_DOWN)
++		return retval;
++
++	if (state <= PM_SUSPEND_MEM)
++		retval = ohs900h_bus_suspend(ohs900_to_hcd(ohs900));
++	else
++		port_power(ohs900, 0);
++	if (retval == 0)
++		dev->power.power_state = state;
++	return retval;
++}
++
++static int
++ohs900h_resume(struct platform_device *dev)
++{
++	struct ohs900	*ohs900 = dev_get_drvdata(dev);
++
++	if (phase != RESUME_POWER_ON)
++		return 0;
++
++	/* with no "check to see if VBUS is still powered" board hook,
++	 * let's assume it'd only be powered to enable remote wakeup.
++	 */
++	if (!ohs900->port1 || !ohs900_to_hcd(ohs900)->can_wakeup) {
++		ohs900->port1 = 0;
++		port_power(ohs900, 1);
++		return 0;
++	}
++
++	return ohs900h_bus_resume(ohs900_to_hcd(ohs900));
++}
++
++#else
++
++#define	ohs900h_suspend	NULL
++#define	ohs900h_resume	NULL
++
++#endif
++
++
++struct platform_driver ohs900h_driver = {
++	.probe =	ohs900h_probe,
++	.remove =	__devexit_p(ohs900h_remove),
++
++	.suspend =	ohs900h_suspend,
++	.resume =	ohs900h_resume,
++	.driver = {
++		.name =	(char *) hcd_name,
++		.owner = THIS_MODULE,
++	},
++};
++
++static struct resource ohs900_resources[] = { 
++ [0] = {
++   .start          = (OHS900_BASE),
++   .end            = ((OHS900_BASE) + OHS900_IO_EXTENT - 1),
++   .flags          = IORESOURCE_MEM,
++ },
++ [1] = {
++   .start          = (OHS900SLAVE_BASE),
++   .end            = ((OHS900SLAVE_BASE) + OHS900_IO_EXTENT - 1),
++   .flags          = IORESOURCE_MEM,
++ },
++ [2] = {
++   .start          = (OHS900_IRQ),
++   .end            = (OHS900_IRQ),
++   .flags          = IORESOURCE_IRQ,
++ },
++ [3] = {
++   .start          = (OHS900SLAVE_IRQ),
++   .end            = (OHS900SLAVE_IRQ),
++   .flags          = IORESOURCE_IRQ,
++ },
++};
++
++
++static void sm3k_port_power(struct device *dev, int is_on) {
++	INFO("driver %s, inside stubbed sm3k_port_power\n", hcd_name);
++ // see linux/usb_ohs900.h
++}
++static void sm3k_hc_reset(struct device *dev) {
++ // see linux/usb_ohs900.h
++	struct ohs900	*ohs900 = dev_get_drvdata(dev);
++
++	INFO("Resetting core\n");
++	ohs900_write(ohs900, OHS900_HOSTSLAVECTLREG, OHS900_HSCTLREG_RESET_CORE);
++}
++struct ohs900_platform_data sm3k_ohs900 = {
++ .potpg = 10,
++ .power = 250,
++ .port_power = sm3k_port_power,
++ .reset = sm3k_hc_reset,
++};
++static struct platform_device ohs900_device = {
++ .name           = "ohs900-hcd",
++ .id             = -1,
++ .dev = {
++   .platform_data = &sm3k_ohs900,
++   .release = ohs900_release,
++ },
++ .num_resources  = ARRAY_SIZE(ohs900_resources),
++ .resource       = ohs900_resources,
++};
++
++
++/*-------------------------------------------------------------------------*/
++
++void ohs900_release(struct device *dev) {
++	/*
++	  This function is needed because otherwise the
++	  platform_device_unregister() call fails. Should we be actually
++	  doing something here?
++	 */
++}
++ 
++static int __init ohs900h_init(void) 
++{
++	if (usb_disabled())
++		return -ENODEV;
++	
++	platform_device_register(&ohs900_device); 
++	
++	INFO("driver %s, %s\n", hcd_name, DRIVER_VERSION);
++	return platform_driver_register(&ohs900h_driver);
++}
++module_init(ohs900h_init);
++
++static void __exit ohs900h_cleanup(void) 
++{	
++	platform_driver_unregister(&ohs900h_driver);
++	platform_device_unregister(&ohs900_device);
++}
++module_exit(ohs900h_cleanup);
Index: common/components/usbhostslave/web_uploads/linux_2_6_28_patch_file.zip
===================================================================
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+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/web_uploads/ALDEC_logo.jpg
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/web_uploads/ALDEC_logo.jpg
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/web_uploads/linux_2_6_22_patch_files.zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/web_uploads/linux_2_6_22_patch_files.zip
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ise
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/usbDeviceXilinxTop.ise
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/trunk/usbDevice/verilogCopy.pl
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/verilogCopy.pl	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/verilogCopy.pl	(revision 264)
@@ -0,0 +1,137 @@
+#!/usr/bin/perl -w
+#
+#
+# USAGE: perl verilogCopy.pl [-i <inFile>] [-o <outFile>] 
+#  -i <inFile> : Verilog input file
+#  -0 <outFile> : Verilog output file
+#  example: perl verilogCopy.pl -i inFileName -o outFileName
+#
+# Release notes:
+# 0.1 initial release
+
+use strict;
+use sigtrap;
+use Getopt::Std;
+use constant TIMESTAMP => scalar localtime;
+
+use Socket;
+
+use FileHandle;
+use File::stat;
+
+my %options = ();
+getopts( "o:i:t:",\%options );
+
+my $gRespStr = "";
+my @inFile;
+my $filename;
+my $myFileAsString;
+our $outFile = new FileHandle;		
+our $inFileSt;
+our $outFileSt;
+	
+
+my $version =  "verilogCopy   ";
+
+#print( "$version\n" );
+
+# --- open Verilog input file
+if (defined $options{i} ) {
+  $inFileSt = stat($options{i}) or die "Can't stat $options{i}: $!";
+  #print ("\n in File mtime = ");
+  #print $inFileSt->mtime;
+  #print ("\n");
+}
+else {
+  print ("Input file name missing. Use -i <inputFileName> \n");
+  exit 1;
+}
+
+# --- open verilog output file
+if (defined $options{o} ) {
+  $outFileSt = stat($options{o}) or die "Can't stat $options{o}: $!";
+  #print ("\n out File mtime = ");
+  #print $outFileSt->mtime;
+  #print ("\n");
+}
+else {
+  print ("Output file name missing. Use -o <outputFileName> \n");
+  exit 1;
+}
+
+
+$/ = undef;
+
+  if ($outFileSt->mtime < $inFileSt->mtime) {
+    @inFile = glob( $options{i} );
+    $outFile->open(">$options{o}") or die("Cannot open write file!\n");
+    slurpFile(\$myFileAsString, $inFile[0] );
+    parseInputFile(\$myFileAsString);
+    patchFile(\$myFileAsString, $inFile[0] );
+    $outFile->print("$myFileAsString");
+    $outFile->close();
+    print( "\"$options{i}\" has been processed and copied to \"$options{o}\".\n" );
+  }
+  else {
+    print ("Input file older than output file. No update required\n");
+  }
+
+
+
+#---------------------------------- slurpFile -------------------------------------------#
+sub slurpFile
+{
+	my $fileAsString = shift();
+	my $filename = shift();
+	my $read  = new FileHandle;		# The input file
+	
+	$read->open( $filename ) or print( "Cannot open $filename for reading!\n" ) and return(0);
+     $$fileAsString = $read->getline();     # Read in the entire file as a list
+	$read->close() or die( "Cannot close $_!\n" );
+	return(1);
+}
+
+
+#---------------------------------- parseInputFile -------------------------------------------#
+sub parseInputFile
+{
+  my $fileAsString = shift();
+
+  $$fileAsString =~ s/! =/!=/gs;      #patch ActiveHDL 4.2 FSM2HDL bug
+  $$fileAsString =~ s/ = / <= /gs;    #patch ActiveHDL 4.2 FSM2HDL bug
+  $$fileAsString =~ s/\r//gs;         #delete DOS carriage returns
+  $$fileAsString =~ s/\t/  /gs;       #replace tabs with two spaces
+
+
+}
+
+#---------------------------------- patchFile -------------------------------------------#
+sub patchFile
+{
+  my $fileAsString = shift();
+  my $filename = shift();
+
+  if ($filename =~ /spiCtrl.v/) {
+    unless(
+      $$fileAsString =~ s/\(spiTransCtrl or rxDataRdy/\(spiTransCtrl or rxDataRdy or spiTransType/
+    ) {print "-------- ERROR, patch failed \n"; exit;}
+    print ("--Patched $filename\n");
+  }
+  if ($filename =~ /readWriteSDBlock.v/) {
+    unless(
+      $$fileAsString =~ s/\(blockAddr or sendCmdRdy/\(blockAddr or sendCmdRdy or respTout or respByte/
+    ) {print "-------- ERROR, patch failed \n"; exit;}
+    print ("--Patched $filename\n");
+  }
+  if ($filename =~ /tx_pkt_sched.v/) {
+    unless(
+      $$fileAsString =~ s/\(buffLoadGnt or buffUnLoadGnt/\(buffLoadGnt or buffUnLoadGnt or txBufferLoaded/
+    ) {print "-------- ERROR, patch failed \n"; exit;}
+    print ("--Patched $filename\n");
+  }
+}
+
+
+
+
+
Index: common/components/usbhostslave/web_uploads/dual_Fairchild_USB_PHY_daughter_card_12001-00Rev-01.zip
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/web_uploads/dual_Fairchild_USB_PHY_daughter_card_12001-00Rev-01.zip
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/trunk/doc/usbHostSlave_FSM.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/components/usbhostslave/trunk/doc/usbHostSlave_FSM.pdf
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/usbhostslave/trunk/sim/filelistComboHostSlave.icarus
===================================================================
--- common/components/usbhostslave/trunk/sim/filelistComboHostSlave.icarus	(nonexistent)
+++ common/components/usbhostslave/trunk/sim/filelistComboHostSlave.icarus	(revision 264)
@@ -0,0 +1,56 @@
+../RTL/buffers/dpMem_dc.v
+../RTL/buffers/fifoRTL.v
+../RTL/buffers/RxFifoBI.v
+../RTL/buffers/TxFifoBI.v
+../RTL/buffers/RxFifo.v
+../RTL/buffers/TxFifo.v
+../RTL/busInterface/wishBoneBI.v
+../RTL/hostController/directControl.v
+../RTL/hostController/getPacket.v
+../RTL/hostController/hctxportarbiter.v
+../RTL/hostController/hostcontroller.v
+../RTL/hostController/rxStatusMonitor.v
+../RTL/hostController/sendPacket.v
+../RTL/hostController/sendpacketarbiter.v
+../RTL/hostController/sendpacketcheckpreamble.v
+../RTL/hostController/sofcontroller.v
+../RTL/hostController/softransmit.v
+../RTL/hostController/speedctrlMux.v
+../RTL/hostController/usbHostControl.v
+../RTL/hostController/USBHostControlBI.v
+../RTL/hostSlaveMux/hostSlaveMux.v
+../RTL/hostSlaveMux/hostSlaveMuxBI.v
+../RTL/serialInterfaceEngine/lineControlUpdate.v
+../RTL/serialInterfaceEngine/processRxBit.v
+../RTL/serialInterfaceEngine/processRxByte.v
+../RTL/serialInterfaceEngine/processTxByte.v
+../RTL/serialInterfaceEngine/readUSBWireData.v
+../RTL/serialInterfaceEngine/siereceiver.v
+../RTL/serialInterfaceEngine/SIETransmitter.v
+../RTL/serialInterfaceEngine/updateCRC5.v
+../RTL/serialInterfaceEngine/updateCRC16.v
+../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+../RTL/serialInterfaceEngine/usbTxWireArbiter.v
+../RTL/serialInterfaceEngine/writeUSBWireData.v
+../RTL/slaveController/endpMux.v
+../RTL/slaveController/fifoMux.v
+../RTL/slaveController/sctxportarbiter.v
+../RTL/slaveController/slavecontroller.v
+../RTL/slaveController/slaveDirectcontrol.v
+../RTL/slaveController/slaveGetpacket.v
+../RTL/slaveController/slaveRxStatusMonitor.v
+../RTL/slaveController/slaveSendpacket.v
+../RTL/slaveController/usbSlaveControl.v
+../RTL/slaveController/USBSlaveControlBI.v
+../RTL/wrapper/usbHost.v
+../RTL/wrapper/usbSlave.v
+../RTL/wrapper/usbHostSlave.v
+../model/wb_master_model.v
+../bench/comboHostSlaveTestHarness.v
+../bench/testCase0.v
+
++incdir+../RTL
++incdir+../RTL/include
++incdir+../bench
++define+SIM_COMPILE
+
Index: common/components/usbhostslave/trunk/sim/viewWave.bat
===================================================================
--- common/components/usbhostslave/trunk/sim/viewWave.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/sim/viewWave.bat	(revision 264)
@@ -0,0 +1 @@
+gtkwave wave.vcd
Index: common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbhostslaveavalonwrap/class.ptf
===================================================================
--- common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbhostslaveavalonwrap/class.ptf	(nonexistent)
+++ common/components/usbhostslave/trunk/syn/Altera/sopcCompProj/usbhostslaveavalonwrap/class.ptf	(revision 264)
@@ -0,0 +1,626 @@
+#
+# This class.ptf file built by Component Editor
+# 2006.10.11.20:54:36
+#
+# DO NOT MODIFY THIS FILE
+# If you hand-modify this file you will likely
+# interfere with Component Editor's ability to
+# read and edit it. And then Component Editor
+# will overwrite your changes anyway. So, for
+# the very best results, just relax and
+# DO NOT MODIFY THIS FILE
+#
+CLASS usbhostslaveavalonwrap
+{
+   CB_GENERATOR 
+   {
+      HDL_FILES 
+      {
+         FILE 
+         {
+            use_in_simulation = "1";
+            use_in_synthesis = "1";
+            type = "verilog";
+            filepath = "hdl/usbHostSlaveAvalonWrap.v";
+         }
+      }
+      top_module_name = "usbHostSlaveAvalonWrap.v:usbHostSlaveAvalonWrap";
+      emit_system_h = "0";
+      LIBRARIES 
+      {
+      }
+   }
+   MODULE_DEFAULTS global_signals
+   {
+      class = "usbhostslaveavalonwrap";
+      class_version = "1.0";
+      SYSTEM_BUILDER_INFO 
+      {
+         Instantiate_In_System_Module = "1";
+         Has_Clock = "1";
+         Top_Level_Ports_Are_Enumerated = "1";
+      }
+      COMPONENT_BUILDER 
+      {
+         GLS_SETTINGS 
+         {
+         }
+      }
+      PORT_WIRING 
+      {
+         PORT clk
+         {
+            width = "1";
+            width_expression = "";
+            direction = "input";
+            type = "clk";
+            is_shared = "0";
+            vhdl_record_name = "";
+            vhdl_record_type = "";
+         }
+         PORT reset
+         {
+            width = "1";
+            width_expression = "";
+            direction = "input";
+            type = "reset";
+            is_shared = "0";
+            vhdl_record_name = "";
+            vhdl_record_type = "";
+         }
+         PORT usbClk
+         {
+            width = "1";
+            width_expression = "";
+            direction = "input";
+            type = "export";
+            is_shared = "0";
+            vhdl_record_name = "";
+            vhdl_record_type = "";
+         }
+      }
+      WIZARD_SCRIPT_ARGUMENTS 
+      {
+         hdl_parameters 
+         {
+         }
+      }
+      SIMULATION 
+      {
+         DISPLAY 
+         {
+         }
+      }
+      SLAVE avalon_slave_0
+      {
+         SYSTEM_BUILDER_INFO 
+         {
+            Bus_Type = "avalon";
+            Address_Group = "1";
+            Has_Clock = "0";
+            Address_Width = "8";
+            Address_Alignment = "native";
+            Data_Width = "8";
+            Has_Base_Address = "1";
+            Has_IRQ = "1";
+            Setup_Time = "0";
+            Hold_Time = "0";
+            Read_Wait_States = "peripheral_controlled";
+            Write_Wait_States = "peripheral_controlled";
+            Read_Latency = "0";
+            Maximum_Pending_Read_Transactions = "0";
+            Active_CS_Through_Read_Latency = "0";
+            Is_Printable_Device = "0";
+            Is_Memory_Device = "0";
+            Is_Readable = "1";
+            Is_Writable = "1";
+            Minimum_Uninterrupted_Run_Length = "1";
+         }
+         COMPONENT_BUILDER 
+         {
+            AVS_SETTINGS 
+            {
+               Setup_Value = "0";
+               Read_Wait_Value = "1";
+               Write_Wait_Value = "1";
+               Hold_Value = "0";
+               Timing_Units = "cycles";
+               Read_Latency_Value = "0";
+               Minimum_Arbitration_Shares = "1";
+               Active_CS_Through_Read_Latency = "0";
+               Max_Pending_Read_Transactions_Value = "1";
+               Address_Alignment = "native";
+               Is_Printable_Device = "0";
+               Interleave_Bursts = "0";
+               interface_name = "Avalon Slave";
+               external_wait = "1";
+               Is_Memory_Device = "0";
+            }
+         }
+         PORT_WIRING 
+         {
+            PORT address
+            {
+               width = "8";
+               width_expression = "";
+               direction = "input";
+               type = "address";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT writedata
+            {
+               width = "8";
+               width_expression = "";
+               direction = "input";
+               type = "writedata";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT readdata
+            {
+               width = "8";
+               width_expression = "";
+               direction = "output";
+               type = "readdata";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT write
+            {
+               width = "1";
+               width_expression = "";
+               direction = "input";
+               type = "write";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT read
+            {
+               width = "1";
+               width_expression = "";
+               direction = "input";
+               type = "read";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT waitrequest
+            {
+               width = "1";
+               width_expression = "";
+               direction = "output";
+               type = "waitrequest";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT chipselect
+            {
+               width = "1";
+               width_expression = "";
+               direction = "input";
+               type = "chipselect";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT irq
+            {
+               width = "1";
+               width_expression = "";
+               direction = "output";
+               type = "irq";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT USBWireVPI
+            {
+               width = "1";
+               width_expression = "";
+               direction = "input";
+               type = "export";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT USBWireVMI
+            {
+               width = "1";
+               width_expression = "";
+               direction = "input";
+               type = "export";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT USBWireDataInTick
+            {
+               width = "1";
+               width_expression = "";
+               direction = "output";
+               type = "export";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT USBWireVPO
+            {
+               width = "1";
+               width_expression = "";
+               direction = "output";
+               type = "export";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT USBWireVMO
+            {
+               width = "1";
+               width_expression = "";
+               direction = "output";
+               type = "export";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT USBWireDataOutTick
+            {
+               width = "1";
+               width_expression = "";
+               direction = "output";
+               type = "export";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT USBWireOutEn_n
+            {
+               width = "1";
+               width_expression = "";
+               direction = "output";
+               type = "export";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+            PORT USBFullSpeed
+            {
+               width = "1";
+               width_expression = "";
+               direction = "output";
+               type = "export";
+               is_shared = "0";
+               vhdl_record_name = "";
+               vhdl_record_type = "";
+            }
+         }
+      }
+   }
+   USER_INTERFACE 
+   {
+      USER_LABELS 
+      {
+         name = "usbHostSlaveAvalonWrap";
+         technology = "user logic";
+      }
+      WIZARD_UI the_wizard_ui
+      {
+         title = "usbHostSlaveAvalonWrap - {{ $MOD }}";
+         CONTEXT 
+         {
+            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
+            M = "";
+            SBI_global_signals = "SYSTEM_BUILDER_INFO";
+            SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";
+         }
+         PAGES main
+         {
+            PAGE 1
+            {
+               align = "left";
+               title = "<b>usbHostSlaveAvalonWrap 1.0</b> Settings";
+               layout = "vertical";
+               TEXT 
+               {
+                  title = "Built on: 2006.10.11.20:54:36";
+               }
+               TEXT 
+               {
+                  title = "Class name: usbhostslaveavalonwrap";
+               }
+               TEXT 
+               {
+                  title = "Class version: 1.0";
+               }
+               TEXT 
+               {
+                  title = "Component name: usbHostSlaveAvalonWrap";
+               }
+               TEXT 
+               {
+                  title = "Component Group: user logic";
+               }
+            }
+         }
+      }
+   }
+   SOPC_Builder_Version = "6.00";
+   COMPONENT_BUILDER 
+   {
+      HDL_PARAMETERS 
+      {
+         # generated by CBDocument.getParameterContainer
+         # used only by Component Editor
+      }
+      SW_FILES 
+      {
+      }
+      built_on = "2006.10.11.20:54:36";
+      CACHED_HDL_INFO 
+      {
+         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
+         # used only by Component Builder
+         FILE usbHostSlaveAvalonWrap.v
+         {
+            file_mod = "Fri Oct 06 19:53:44 PDT 2006";
+            quartus_map_start = "Sat Oct 07 21:44:02 PDT 2006";
+            quartus_map_finished = "Sat Oct 07 21:44:11 PDT 2006";
+            #found 1 valid modules
+            WRAPPER usbHostSlaveAvalonWrap
+            {
+               CLASS usbHostSlaveAvalonWrap
+               {
+                  CB_GENERATOR 
+                  {
+                     HDL_FILES 
+                     {
+                        FILE 
+                        {
+                           use_in_simulation = "1";
+                           use_in_synthesis = "1";
+                           type = "";
+                           filepath = "C:/projects/usbhostslaveCVS/usbhostslave/syn/Altera/sopcCompProj/atom_netlists/usbHostSlaveAvalonWrap.v";
+                        }
+                     }
+                     top_module_name = "usbHostSlaveAvalonWrap";
+                     emit_system_h = "0";
+                  }
+                  MODULE_DEFAULTS global_signals
+                  {
+                     class = "usbHostSlaveAvalonWrap";
+                     class_version = "1.0";
+                     SYSTEM_BUILDER_INFO 
+                     {
+                        Instantiate_In_System_Module = "1";
+                     }
+                     SLAVE avalon_slave_0
+                     {
+                        SYSTEM_BUILDER_INFO 
+                        {
+                           Bus_Type = "avalon";
+                        }
+                        PORT_WIRING 
+                        {
+                           PORT address
+                           {
+                              width = "8";
+                              width_expression = "";
+                              direction = "input";
+                              type = "address";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT writedata
+                           {
+                              width = "8";
+                              width_expression = "";
+                              direction = "input";
+                              type = "writedata";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT readdata
+                           {
+                              width = "8";
+                              width_expression = "";
+                              direction = "output";
+                              type = "readdata";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT write
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "input";
+                              type = "write";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT read
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "input";
+                              type = "read";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT waitrequest
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "output";
+                              type = "waitrequest";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT chipselect
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "input";
+                              type = "chipselect";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT irq
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "output";
+                              type = "irq";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT usbClk
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "input";
+                              type = "export";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT USBWireVPI
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "input";
+                              type = "export";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT USBWireVMI
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "input";
+                              type = "export";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT USBWireDataInTick
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "output";
+                              type = "export";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT USBWireVPO
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "output";
+                              type = "export";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT USBWireVMO
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "output";
+                              type = "export";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT USBWireDataOutTick
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "output";
+                              type = "export";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT USBWireOutEn_n
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "output";
+                              type = "export";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                           PORT USBFullSpeed
+                           {
+                              width = "1";
+                              width_expression = "";
+                              direction = "output";
+                              type = "export";
+                              is_shared = "0";
+                              vhdl_record_name = "";
+                              vhdl_record_type = "";
+                           }
+                        }
+                     }
+                     PORT_WIRING 
+                     {
+                        PORT clk
+                        {
+                           width = "1";
+                           width_expression = "";
+                           direction = "input";
+                           type = "clk";
+                           is_shared = "0";
+                           vhdl_record_name = "";
+                           vhdl_record_type = "";
+                        }
+                        PORT reset
+                        {
+                           width = "1";
+                           width_expression = "";
+                           direction = "input";
+                           type = "reset";
+                           is_shared = "0";
+                           vhdl_record_name = "";
+                           vhdl_record_type = "";
+                        }
+                     }
+                  }
+                  USER_INTERFACE 
+                  {
+                     USER_LABELS 
+                     {
+                        name = "usbHostSlaveAvalonWrap";
+                        technology = "imported components";
+                     }
+                  }
+                  SOPC_Builder_Version = "0.0";
+               }
+            }
+         }
+      }
+   }
+   ASSOCIATED_FILES 
+   {
+      Add_Program = "the_wizard_ui";
+      Edit_Program = "the_wizard_ui";
+      Generator_Program = "cb_generator.pl";
+   }
+}
Index: common/components/usbhostslave/trunk/usbDevice/Aldec/design0/design0.adf
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/Aldec/design0/design0.adf	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/Aldec/design0/design0.adf	(revision 264)
@@ -0,0 +1,38 @@
+[Project]
+Current Flow=Generic
+VCS=0
+version=1
+Current Config=compile
+
+[Configurations]
+compile=design0
+
+[Library]
+design0=.\design0.LIB
+
+[$LibMap$]
+design0=.
+
+[Settings]
+FLOW_TYPE=HDL
+LANGUAGE=VHDL
+
+[Files]
+/EP0.asf=-1
+/checkLineState.asf=-1
+/EP1Mouse.asf=-1
+
+[Files.Data]
+.\src\EP0.asf=State Diagram
+.\src\checkLineState.asf=State Diagram
+.\src\EP1Mouse.asf=State Diagram
+
+[file_out:/EP0.asf]
+/\compile\EP0.v=-1
+
+[file_out:/checkLineState.asf]
+/\compile\checkLineState.v=-1
+
+[file_out:/EP1Mouse.asf]
+/\compile\EP1Mouse.v=-1
+
Index: common/components/usbhostslave/trunk/usbDevice/Aldec/design0/src/checkLineState.asf
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/Aldec/design0/src/checkLineState.asf	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/Aldec/design0/src/checkLineState.asf	(revision 264)
@@ -0,0 +1,93 @@
+VERSION=1.15
+HEADER
+FILE="checkLineState.asf"
+FID=4788d213
+LANGUAGE=VERILOG
+ENTITY="checkLineState"
+FRAMES=ON
+FREEOID=1077
+"LIBRARIES=//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// checkLineState.v                                 ////\n////                                                              ////\n//// This file is part of the usbHostSlave opencores effort.\n//// <http://www.opencores.org/cores//>                           ////\n////                                                              ////\n//// Module Description:                                          ////\n//// Checks USB line state. When reset state detected\n//// asserts usbRstDet for one clock tick\n//// usbRstDet is used to reset most of the logic.\n//// \n////                                                              ////\n//// To Do:                                                       ////\n//// \n////                                                              ////\n//// Author(s):                                                   ////\n//// - Steve Fielding, sfielding@base2designs.com                 ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n////                                                              ////\n//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////\n////                                                              ////\n//// This source file may be used and distributed without         ////\n//// restriction provided that this copyright statement is not    ////\n//// removed from the file and that any derivative work contains  ////\n//// the original copyright notice and the associated disclaimer. ////\n////                                                              ////\n//// This source file is free software; you can redistribute it   ////\n//// and/or modify it under the terms of the GNU Lesser General   ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any   ////\n//// later version.                                               ////\n////                                                              ////\n//// This source is distributed in the hope that it will be       ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////\n//// PURPOSE. See the GNU Lesser General Public License for more  ////\n//// details.                                                     ////\n////                                                              ////\n//// You should have received a copy of the GNU Lesser General    ////\n//// Public License along with this source; if not, download it   ////\n//// from <http://www.opencores.org/lgpl.shtml>                   ////\n////                                                              ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"usbSlaveControl_h.v\"\n`include \"usbHostSlaveReg_define.v\"\n`include \"usbSerialInterfaceEngine_h.v\"\n`include \"usbDevice_define.v\""
+END
+BUNDLES
+B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1  "Arial" 0
+B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1  "Arial" 0
+B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1  "Arial" 0
+B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1  "Arial" 0
+B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1  "Arial" 0
+B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1  "Arial" 0
+B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1  "Arial" 0
+B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1  "Arial" 0
+B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1  "Arial" 4
+B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1  "Arial" 0
+B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1  "Arial" 0
+B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1  "Arial" 0
+END
+INSTHEADER 1
+PAGE 25400,25400 215900,279400
+UPPERLEFT 0,0
+GRID=OFF
+GRIDSIZE 5000,5000 10000,10000
+END
+OBJECTS
+G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1  "Arial" 0 | 110650,276400 1 0 0 "Module: checkLineState"
+A 5 0 1 TEXT "Actions" | 30400,266400 1 0 0 "-- diagram ACTION"
+F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,212603
+L 7 6 0 TEXT "Labels" | 31673,209974 1 0 0 "chkLSt"
+L 564 565 0 TEXT "Labels" | 83155,262907 1 0 0 "usbRstDet"
+I 565 0 2 Builtin OutPort | 77155,262907 "" ""
+I 74 0 2 Builtin InPort | 195700,267632 "" ""
+L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst"
+I 72 0 3 Builtin InPort | 195700,272800 "" ""
+L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk"
+S 100 6 0 ELLIPSE "States" | 112176,193512 6500 6500
+L 99 100 0 TEXT "State Labels" | 112176,193512 1 0 0 "START\n/0/"
+C 389 388 0 TEXT "Conditions" | 64133,197548 1 0 0 "rst == 1'b1"
+W 388 6 0 387 100 BEZIER "Transitions" | 49555,202550 64193,201024 91216,196545 105854,195019
+I 387 6 0 Builtin Reset | 49555,202550
+I 471 0 130 Builtin OutPort | 120974,258272 "" ""
+L 472 471 0 TEXT "Labels" | 126974,258272 1 0 0 "wb_addr[7:0]"
+I 473 0 2 Builtin OutPort | 121470,234129 "" ""
+L 474 473 0 TEXT "Labels" | 127470,234129 1 0 0 "wb_we"
+I 475 0 2 Builtin OutPort | 121470,239089 "" ""
+L 476 475 0 TEXT "Labels" | 127470,239089 1 0 0 "wb_stb"
+I 479 0 130 Builtin InPort | 123454,253473 "" ""
+L 480 479 0 TEXT "Labels" | 129454,253473 1 0 0 "wb_data_i[7:0]"
+I 481 0 2 Builtin InPort | 123702,243801 "" ""
+L 482 481 0 TEXT "Labels" | 129702,243801 1 0 0 "wb_ack"
+L 494 495 0 TEXT "Labels" | 83190,258260 1 0 0 "initComplete"
+I 495 0 2 Builtin InPort | 77190,258260 "" ""
+L 496 497 0 TEXT "Labels" | 83190,253838 1 0 0 "wbBusReq"
+I 497 0 2 Builtin OutPort | 77190,253838 "" ""
+L 498 499 0 TEXT "Labels" | 85401,249215 1 0 0 "wbBusGnt"
+I 499 0 2 Builtin InPort | 79401,249215 "" ""
+S 1043 6 4096 ELLIPSE "States" | 74797,116753 6500 6500
+A 1044 1043 4 TEXT "Actions" | 91359,124097 1 0 0 "wb_addr <= `RA_SC_LINE_STATUS_REG;\nwb_stb <= 1'b1;\nwb_we <= 1'b1;"
+S 1045 6 8192 ELLIPSE "States" | 74187,138513 6500 6500
+L 1046 1045 0 TEXT "State Labels" | 74187,138513 1 0 0 "WT_GNT\n/2/"
+A 1047 1045 4 TEXT "Actions" | 91995,140209 1 0 0 "wbBusReq <= 1'b1;"
+W 1051 6 0 1045 1043 BEZIER "Transitions" | 74066,132060 74119,129516 74220,125771 74273,123227
+C 1052 1051 0 TEXT "Conditions" | 76307,130457 1 0 0 "wbBusGnt == 1'b1"
+W 1053 6 0 1043 1063 BEZIER "Transitions" | 74742,110285 74658,108295 74665,87535 74878,72303
+C 1054 1053 0 TEXT "Conditions" | 52376,109915 1 0 0 "wb_ack == 1'b1"
+A 1055 1053 16 TEXT "Actions" | 43552,104880 1 0 0 "wb_stb <= 1'b0;\nif ( (wb_data_i[1:0] == `DISCONNECT) || (wb_data_i[`VBUS_PRES_BIT] == 1'b0) )\n  resetState <= {resetState[0], 1'b1};\nelse\n  resetState <= 2'b00;\nwbBusReq <= 1'b0;"
+C 1071 1061 0 TEXT "Conditions" | 101452,177220 1 0 0 "initComplete == 1'b1"
+L 1056 1043 0 TEXT "State Labels" | 74797,116753 1 0 0 "GET_STAT\n/1/"
+W 1061 6 0 100 1045 BEZIER "Transitions" | 108298,188296 100155,176813 85729,155535 77586,144052
+L 1062 1063 0 TEXT "State Labels" | 75483,66966 1 0 0 "SET_RST_DET\n/3/"
+S 1063 6 12288 ELLIPSE "States" | 75483,66966 6500 6500
+L 1064 1065 0 TEXT "State Labels" | 76581,38853 1 0 0 "DEL_ONE_MSEC\n/4/"
+S 1065 6 16384 ELLIPSE "States" | 76581,38853 6500 6500
+W 1066 6 0 1063 1065 BEZIER "Transitions" | 75394,60480 75571,54410 75922,51155 75989,45315
+A 1067 1066 16 TEXT "Actions" | 66310,59029 1 0 0 "if (resetState == 2'b11) // if reset condition aserted for 2mS\n  usbRstDet <= 1'b1; \ncnt <= 16'h0000;"
+A 1068 1065 4 TEXT "Actions" | 97514,47021 1 0 0 "cnt <= cnt + 1'b1;\nusbRstDet <= 1'b0;"
+W 1069 6 0 1065 1045 BEZIER "Transitions" | 82990,37770 98582,38531 128050,34971 141866,41055\
+                                            155682,47140 179565,74042 183796,90420 188028,106798\
+                                            181074,145412 173411,156071 165748,166731 142049,170757\
+                                            129605,167943 117162,165130 92622,149773 79584,142133
+C 1070 1069 0 TEXT "Conditions" | 97438,36458 1 0 0 "cnt == `ONE_MSEC_DEL"
+I 1076 0 130 Builtin Signal | 43632,229376 "" ""
+L 1075 1076 0 TEXT "Labels" | 46632,229376 1 0 0 "resetState[1:0]"
+I 1074 0 130 Builtin Signal | 42480,236720 "" ""
+L 1073 1074 0 TEXT "Labels" | 45480,236720 1 0 0 "cnt[15:0]"
+A 1072 100 4 TEXT "Actions" | 128684,204360 1 0 0 "usbRstDet <= 1'b0;\nwbBusReq <= 1'b0;\nwb_addr <= 8'h00;\nwb_stb <= 1'b0;\nwb_we <= 1'b0;\ncnt <= 16'h0000;\nresetState <= 2'b00;"
+END
Index: common/components/usbhostslave/trunk/usbDevice/RTL/pll_48MHz.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/pll_48MHz.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/pll_48MHz.v	(revision 264)
@@ -0,0 +1,278 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll_48MHz.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Build 203 02/05/2008 SP 2 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll_48MHz (
+	inclk0,
+	locked);
+
+	input	  inclk0;
+	output	  locked;
+
+	wire  sub_wire0;
+	wire [0:0] sub_wire3 = 1'h0;
+	wire  locked = sub_wire0;
+	wire  sub_wire1 = inclk0;
+	wire [1:0] sub_wire2 = {sub_wire3, sub_wire1};
+
+	altpll	altpll_component (
+				.inclk (sub_wire2),
+				.locked (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clk (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.gate_lock_signal = "NO",
+		altpll_component.inclk0_input_frequency = 20833,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.invalid_lock_multiplier = 5,
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_48MHz",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NO_COMPENSATION",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_UNUSED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_48MHz.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz.bsf FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_inst.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_waveforms.html TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_48MHz_wave*.jpg FALSE FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
Index: common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceXilinxTop.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceXilinxTop.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/usbDeviceXilinxTop.v	(revision 264)
@@ -0,0 +1,92 @@
+
+module usbDeviceXilinxTop (
+
+  //
+  // Global signals
+  //
+  clk,
+
+  //
+  // misc Starter Kit control sigs
+  //
+  E_NRST,
+  SPI_SCK,
+  NF_CE,
+  SD_CS,
+
+  //
+  // USB slave
+  //
+  usbSlaveVP,
+  usbSlaveVM,
+  usbSlaveOE_n,
+  usbDPlusPullup
+
+);
+
+  //
+  // Global signals
+  //
+  input	clk;
+
+  //
+  // misc Starter Kit control sigs
+  //
+  output E_NRST;
+  output SPI_SCK;
+  output NF_CE;
+  output SD_CS;
+
+  //
+  // USB slave
+  //
+  inout usbSlaveVP;
+  inout usbSlaveVM;
+  output usbSlaveOE_n;
+  output usbDPlusPullup;
+
+//local wires and regs
+reg [1:0] rstReg;
+wire rst;
+wire pll_locked;
+wire clk48MHz;
+
+
+assign E_NRST = 1'b0;
+assign SPI_SCK = 1'b0;
+assign NF_CE = 1'b0;
+assign SD_CS = 1'b1;
+
+
+pll_48MHz_xilinx	pll_48MHz_inst (
+	.CLKIN_IN ( clk ),
+   .CLK0_OUT (clk48MHz),
+	.LOCKED_OUT( pll_locked)
+	);
+
+//generate sync reset from pll lock signal
+always @(posedge clk48MHz) begin
+  rstReg[1:0] <= {rstReg[0], ~pll_locked};
+end
+assign rst = rstReg[1];
+
+
+usbDevice u_usbDevice (
+  .clk(clk48MHz),
+  .rst(rst),
+  .usbSlaveVP_in(usbSlaveVP_in),
+  .usbSlaveVM_in(usbSlaveVM_in),
+  .usbSlaveVP_out(usbSlaveVP_out),
+  .usbSlaveVM_out(usbSlaveVM_out),
+  .usbSlaveOE_n(usbSlaveOE_n),
+  .usbDPlusPullup(usbDPlusPullup),
+  .vBusDetect(1'b1)
+);
+
+
+assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
+assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
+
+endmodule
+
+
Index: common/components/usbhostslave/trunk/usbDevice/RTL/usbROM_logitech_mouse.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/RTL/usbROM_logitech_mouse.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/RTL/usbROM_logitech_mouse.v	(revision 264)
@@ -0,0 +1,213 @@
+// ----------------------------- usbROM ---------------------------
+// if you modify this file, be sure to modify usbDevice_define.v
+// Using RAM rather than logic resources might be a more efficient implememtation
+// but this has the advantage of working with FPGAs that do not provide a 
+// mechanism for initialising RAM, eg Actel IGLOO
+// Quartus 7.2 will infer this code as BLOCK RAM, and provide initialisation - nice
+`include "usbDevice_define.v"
+
+
+module usbROM (
+  clk,
+  addr,
+  data
+);
+input clk;
+input [7:0] addr;
+output [7:0] data;
+reg [7:0] data;
+
+always @(posedge clk) begin
+  case (addr)
+// ====================================
+// =====    DEVICE Descriptor     =====
+// ====================================
+
+    8'h00: data <= 8'h12;  //BYTE bLength
+    8'h01: data <= 8'h01;  //BYTE bDescriptorType
+    8'h02: data <= 8'h10;  //WORD (Lo) bcdUSB version supported
+    8'h03: data <= 8'h01;  //WORD (Hi) bcdUSB version supported
+    8'h04: data <= 8'h00;  //BYTE bDeviceClass
+    8'h05: data <= 8'h00;  //BYTE bDeviceSubClass
+    8'h06: data <= 8'h00;  //BYTE bDeviceProtocol
+	 8'h07: data <= `MAX_RESP_SIZE;  //BYTE bMaxPacketSize 
+    8'h08: data <= 8'h6d;  //WORD (Lo) idVendor
+    8'h09: data <= 8'h04;  //WORD (Hi) idVendor
+    8'h0a: data <= 8'h3d;  //WORD (Lo) idProduct; For Logitech mouse
+    8'h0b: data <= 8'hc0;  //WORD (Hi) idProduct; For Logitech Hub mouse
+    8'h0c: data <= 8'h00;  //WORD (Lo) bcdDevice
+    8'h0d: data <= 8'h20;  //WORD (Hi) bcdDevice
+    8'h0e: data <= 8'h01;  //BYTE iManufacturer
+    8'h0f: data <= 8'h02;  //BYTE iProduct
+    8'h10: data <= 8'h00;  //BYTE iSerialNumber
+    8'h11: data <= 8'h01;  //BYTE bNumConfigurations
+
+ 
+// ====================================
+// ===== Configuration Descriptor =====
+// ====================================
+    8'h12: data <= 8'h09;  //BYTE bLength (Configuration descriptor)
+    8'h13: data <= 8'h02;  //BYTE bDescriptorType //Assigned by USB
+	 8'h14: data <= 8'h22;  //WORD (Lo) wTotalLength
+    8'h15: data <= 8'h00;  //WORD (Hi) wTotalLength
+    8'h16: data <= 8'h01;  //BYTE bNumInterfaces
+    8'h17: data <= 8'h01;  //BYTE bConfigurationValue
+    8'h18: data <= 8'h00;  //BYTE iConfiguration
+    8'h19: data <= 8'ha0;  //BYTE bmAttributes, Bus powered and remote wakeup
+    8'h1a: data <= 8'h31;  //BYTE MaxPower, 98mA
+ 
+// ====================================
+// =====   Interface Descriptor   =====
+// ====================================
+    8'h1b: data <= 8'h09;  //BYTE bLength (Interface descriptor)
+    8'h1c: data <= 8'h04;  //BYTE bDescriptionType; assigned by USB
+    8'h1d: data <= 8'h00;  //BYTE bInterfaceNumber
+    8'h1e: data <= 8'h00;  //BYTE bAlternateSetting
+    8'h1f: data <= 8'h01;  //BYTE bNumEndpoints; uses 1 endpoints
+    8'h20: data <= 8'h03;  //BYTE bInterfaceClass; HID Class - 0x03
+    8'h21: data <= 8'h01;  //BYTE bInterfaceSubClass
+    8'h22: data <= 8'h02;  //BYTE bInterfaceProtocol
+    8'h23: data <= 8'h00;  //BYTE iInterface
+ 
+// ====================================
+// =====   HID Descriptor   =====
+// ====================================
+    8'h24: data <= 8'h09;  //BYTE bLength (HID Descriptor)
+    8'h25: data <= 8'h21;  //BYTE bDescriptorType
+    8'h26: data <= 8'h10;  //WORD (Lo) bcdHID
+    8'h27: data <= 8'h01;  //WORD (Hi) bcdHID
+    8'h28: data <= 8'h00;  //BYTE bCountryCode
+    8'h29: data <= 8'h01;  //BYTE bNumDescriptors
+    8'h2a: data <= 8'h22;  //BYTE bReportDescriptorType
+    8'h2b: data <= 8'h32;  //WORD (Lo) wItemLength
+    8'h2c: data <= 8'h00;  //WORD (Hi) wItemLength
+
+// ====================================
+// =====   Endpoint 1 Descriptor  =====
+// ====================================
+    8'h2d: data <= 8'h07;  //BYTE bLength (Endpoint Descriptor)
+    8'h2e: data <= 8'h05;  //BYTE bDescriptorType; assigned by USB
+    8'h2f: data <= 8'h81;  //BYTE bEndpointAddress; IN endpoint; endpoint 1
+    8'h30: data <= 8'h03;  //BYTE bmAttributes; Interrupt endpoint
+    8'h31: data <= 8'h04;  //WORD (Lo) wMaxPacketSize
+    8'h32: data <= 8'h00;  //WORD (Hi) wMaxPacketSize
+    8'h33: data <= 8'h0a;  //BYTE bInterval
+
+ 
+// ====================================
+// =====   Report Descriptor  =====
+// ====================================
+
+    8'h3a: data <= 8'h05;     8'h3b: data <= 8'h01;    // USAGE_PAGE (Generic Desktop)
+    8'h3c: data <= 8'h09;     8'h3d: data <= 8'h02;    // USAGE (Mouse)
+    8'h3e: data <= 8'ha1;     8'h3f: data <= 8'h01;    // COLLECTION (Application)
+    8'h40: data <= 8'h09;     8'h41: data <= 8'h01;    //   USAGE (Pointer)
+    8'h42: data <= 8'ha1;     8'h43: data <= 8'h00;    //   COLLECTION (Physical)
+    8'h44: data <= 8'h05;     8'h45: data <= 8'h09;    //     USAGE_PAGE (Button)
+    8'h46: data <= 8'h19;     8'h47: data <= 8'h01;    //     USAGE_MINIMUM (Button 1)
+    8'h48: data <= 8'h29;     8'h49: data <= 8'h03;    //     USAGE_MAXIMUM (Button 3)
+    8'h4a: data <= 8'h15;     8'h4b: data <= 8'h00;    //     LOGICAL_MINIMUM (0)
+    8'h4c: data <= 8'h25;     8'h4d: data <= 8'h01;    //     LOGICAL_MAXIMUM (1)
+    8'h4e: data <= 8'h95;     8'h4f: data <= 8'h03;    //     REPORT_COUNT (3)
+    8'h50: data <= 8'h75;     8'h51: data <= 8'h01;    //     REPORT_SIZE (1)
+    8'h52: data <= 8'h81;     8'h53: data <= 8'h02;    //     INPUT (Data,Var,Abs)
+    8'h54: data <= 8'h95;     8'h55: data <= 8'h05;    //     REPORT_COUNT (5)
+    8'h56: data <= 8'h81;     8'h57: data <= 8'h03;    //     INPUT (Cnst,Var,Rel)
+    8'h58: data <= 8'h05;     8'h59: data <= 8'h01;    //     USAGE_PAGE (Generic Desktop)
+    8'h5a: data <= 8'h09;     8'h5b: data <= 8'h30;    //     USAGE (X)
+    8'h5c: data <= 8'h09;     8'h5d: data <= 8'h31;    //     USAGE (Y)
+    8'h5e: data <= 8'h09;     8'h5f: data <= 8'h38;    //     USAGE ?
+    8'h60: data <= 8'h15;     8'h61: data <= 8'h81;    //     LOGICAL_MINIMUM (-127)
+    8'h62: data <= 8'h25;     8'h63: data <= 8'h7f;    //     LOGICAL_MAXIMUM (127)
+    8'h64: data <= 8'h75;     8'h65: data <= 8'h08;    //     REPORT_SIZE (8)
+    8'h66: data <= 8'h95;     8'h67: data <= 8'h03;    //     REPORT_COUNT (3)
+    8'h68: data <= 8'h81;     8'h69: data <= 8'h06;    //     INPUT (Data,Var,Rel)
+    8'h6a: data <= 8'hc0;                              //END_COLLECTION
+    8'h6b: data <= 8'hc0;                              // END_COLLECTION
+
+// ZERO_ZERO
+    8'h6c: data <= 8'h00; 
+    8'h6d: data <= 8'h00; 
+// ONE_ZERO
+    8'h6e: data <= 8'h01; 
+    8'h6f: data <= 8'h00; 
+// Vendor data
+    8'h70: data <= 8'h00; 
+    8'h71: data <= 8'h00; 
+
+// =============================================
+// =====   Language ID Descriptor(String0) =====
+// =============================================
+    8'h80: data <= 8'h04;  // bLength
+    8'h81: data <= 8'h03;  // bDescriptorType = String Desc
+    8'h82: data <= 8'h09;  // wLangID (Lo) (Lang ID for English = 0x0409)
+    8'h83: data <= 8'h04;  // wLangID (Hi) (Lang ID for English = 0x0409)
+
+// ====================================
+// =====   string 1 Descriptor  =====
+// ====================================
+    8'h90: data <= 8'd26;  	// bLength
+    8'h91: data <= 8'h03;     // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'h92: data <= "B";  8'h93: data <= 8'h00;
+    8'h94: data <= "a";  8'h95: data <= 8'h00;
+    8'h96: data <= "s";  8'h97: data <= 8'h00;
+    8'h98: data <= "e";  8'h99: data <= 8'h00;
+    8'h9a: data <= "2";  8'h9b: data <= 8'h00;
+    8'h9c: data <= "D";  8'h9d: data <= 8'h00;
+    8'h9e: data <= "e";  8'h9f: data <= 8'h00;
+    8'ha0: data <= "s";  8'ha1: data <= 8'h00;
+    8'ha2: data <= "i";  8'ha3: data <= 8'h00;
+    8'ha4: data <= "g";  8'ha5: data <= 8'h00;
+    8'ha6: data <= "n";  8'ha7: data <= 8'h00;
+    8'ha8: data <= "s";  8'ha9: data <= 8'h00;
+
+
+
+// ====================================
+// =====   string 2 Descriptor  =====
+// ====================================
+	 8'hb0: data <= 8'd20;   // bLength
+    8'hb1: data <= 8'h03;   // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'hb2: data <= "B";  8'hb3: data <= 8'h00;
+    8'hb4: data <= "2";  8'hb5: data <= 8'h00;
+    8'hb6: data <= "D";  8'hb7: data <= 8'h00;
+    8'hb8: data <= " ";  8'hb9: data <= 8'h00;
+    8'hba: data <= "M";  8'hbb: data <= 8'h00;
+    8'hbc: data <= "o";  8'hbd: data <= 8'h00;
+    8'hbe: data <= "u";  8'hbf: data <= 8'h00;
+    8'hc0: data <= "s";  8'hc1: data <= 8'h00;
+    8'hc2: data <= "e";  8'hc3: data <= 8'h00;
+
+// ====================================
+// =====   string 3 Descriptor  =====
+// ====================================
+	 8'hd0: data <= 8'd30;   // bLength
+    8'hd1: data <= 8'h03;   // bDescriptorType = String Desc
+	// Noting that text is always unicode, hence the 'padding'
+    8'hd2: data <= "L";  8'hd3: data <= 8'h00;
+    8'hd4: data <= "i";  8'hd5: data <= 8'h00;
+    8'hd6: data <= "m";  8'hd7: data <= 8'h00;
+    8'hd8: data <= "i";  8'hd9: data <= 8'h00;
+    8'hda: data <= "t";  8'hdb: data <= 8'h00;
+    8'hdc: data <= "e";  8'hdd: data <= 8'h00;
+    8'hde: data <= "d";  8'hdf: data <= 8'h00;
+    8'he0: data <= "E";  8'he1: data <= 8'h00;
+    8'he2: data <= "d";  8'he3: data <= 8'h00;
+    8'he4: data <= "i";  8'he5: data <= 8'h00;
+    8'he6: data <= "t";  8'he7: data <= 8'h00;
+    8'he8: data <= "i";  8'he9: data <= 8'h00;
+    8'hea: data <= "o";  8'heb: data <= 8'h00;
+    8'hec: data <= "n";  8'hed: data <= 8'h00;
+
+
+
+    default: data <= 8'h00;
+  endcase
+end
+
+endmodule
+
+
+ 
Index: common/components/usbhostslave/trunk/usbDevice/bench/usbHostSlaveTB_defines.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/bench/usbHostSlaveTB_defines.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/bench/usbHostSlaveTB_defines.v	(revision 264)
@@ -0,0 +1,2 @@
+`define SIM_HOST_BASE_ADDR 9'h000
+`define SIM_SLAVE_BASE_ADDR 9'h100
Index: common/components/usbhostslave/trunk/usbDevice/sim/build_icarus.bat
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/sim/build_icarus.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/sim/build_icarus.bat	(revision 264)
@@ -0,0 +1,4 @@
+iverilog  -o testHarness -cfilelist.icarus
+
+pause
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/constraint/usbDeviceActelTop.pdc
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/constraint/usbDeviceActelTop.pdc	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/constraint/usbDeviceActelTop.pdc	(revision 264)
@@ -0,0 +1,41 @@
+# Actel Physical design constraints file
+# Version: 8.0 SP2 8.0.3.9
+# Design Name: usbDeviceActelTop 
+# Input Netlist Format: edif 
+# Family: IGLOO , Die: AGL600V2 , Package: 256 FBGA , Speed grade: STD 
+# Date generated: Thu Oct 25 13:06:12 2007 
+
+#
+# IO banks setting
+#
+
+set_iobank Bank3 -vcci 3.30 -fixed no
+set_iobank Bank2 -vcci 3.30 -fixed no
+set_iobank Bank1 -vcci 3.30 -fixed no
+set_iobank Bank0 -vcci 3.30 -fixed no
+
+#
+# I/O constraints
+#
+
+set_io ledOut\[0\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname B7 -fixed yes
+set_io ledOut\[1\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname C7 -fixed yes
+set_io ledOut\[2\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname P5 -fixed yes
+set_io ledOut\[3\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname T2 -fixed yes
+set_io ledOut\[4\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname P4 -fixed yes
+set_io ledOut\[5\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname R3 -fixed yes
+set_io ledOut\[6\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname P2 -fixed yes
+set_io ledOut\[7\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname P1 -fixed yes
+set_io ledOut\[8\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname R1 -fixed yes
+set_io ledOut\[9\] -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname R2 -fixed yes
+
+set_io clk -iostd LVTTL -REGISTER No -RES_PULL None -pinname G13 -fixed yes
+set_io rst_n -iostd LVTTL -REGISTER No -RES_PULL None -pinname N6 -fixed yes
+
+set_io usbSlaveVP -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname A8 -fixed yes
+set_io usbSlaveVM -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname D7 -fixed yes
+set_io usbSlaveOE_n -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname E8 -fixed yes
+set_io usbDPlusPullup -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 5 -pinname C8 -fixed yes
+
+
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.stp
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.stp	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/designer/impl1/usbDeviceActelTop.stp	(revision 264)
@@ -0,0 +1,4349 @@
+NOTE "CREATOR" "Designer Version: 8.3.0.22";
+NOTE "CAPTURE" "8.3.0.22";
+NOTE "DEVICE" "AGL600V5";
+NOTE "PACKAGE" "AGL600V5-fg256";
+NOTE "DATE" "2008/08/22";
+NOTE "STAPL_VERSION" "JESD71";
+NOTE "IDCODE" "03b261cf";
+NOTE "DESIGN" "usbDeviceActelTop";
+NOTE "CHECKSUM" "E537";
+NOTE "SECURITY" "Disable";
+NOTE "ALG_VERSION" "17";
+NOTE "MAP_VERSION" "1";
+NOTE "TOOL_VERSION" "1";
+NOTE "MAX_FREQ" "10000000";
+NOTE "SILSIG" "00000000";
+NOTE "TRACKING_SAR" "72850";
+NOTE "SPEED_GRAD" "STD";
+NOTE "TEMP_GRAD" "COM";
+NOTE "PRG_BSR_SET_IO" "Z";
+
+ACTION PROGRAM = 
+       W_INITIALIZE,
+       DO_ERASE,
+       DO_PROGRAM,
+       DO_VERIFY_BOL,
+       DO_PROGRAM_RLOCK,
+       DO_EXIT;
+ACTION PROGRAM_ARRAY = 
+       AW_INITIALIZE,
+       DO_ERASE_ARRAY,
+       DO_PROGRAM,
+       DO_VERIFY_BOL,
+       DO_PROGRAM_RLOCK,
+       DO_EXIT;
+ACTION ERASE_ARRAY = 
+       AW_INITIALIZE,
+       DO_ERASE_ARRAY_ONLY,
+       DO_EXIT;
+ACTION ERASE = 
+       W_INITIALIZE,
+       DO_ERASE_ONLY,
+       DO_EXIT;
+ACTION ERASE_ALL = 
+       INITIALIZE,
+       DO_ERASE_ALL,
+       DO_EXIT;
+ACTION VERIFY = 
+       R_INITIALIZE,
+       DO_VERIFY_EOL,
+       DO_EXIT;
+ACTION VERIFY_ARRAY = 
+       AR_INITIALIZE,
+       DO_VERIFY_EOL,
+       DO_EXIT;
+ACTION READ_IDCODE = 
+       DO_READ_IDCODE;
+ACTION VERIFY_DEVICE_INFO = 
+       READ_INITIALIZE,
+       READ_IDCODE_ONLY,
+       DO_VERIFY_DEVICE_INFO,
+       DO_EXIT;
+ACTION DEVICE_INFO = 
+       READ_INITIALIZE,
+       READ_IDCODE_ONLY,
+       DO_DEVICE_INFO,
+       DO_QUERY_SECURITY,
+       DO_EXIT;
+
+
+
+DATA CONSTBLOCK;
+    INTEGER IEEE1532=0;
+    INTEGER STAPL=1;
+    INTEGER DIRECTC=2;
+    INTEGER PDB=3;
+    INTEGER SVF=4;
+    INTEGER FP=0;
+    INTEGER FPLITE=1;
+    INTEGER FP3=2;
+    INTEGER SCULPTW=3;
+    INTEGER BPW=4;
+    INTEGER DIRECTCP=5;
+    INTEGER STP=6;
+    INTEGER FP33=0;
+    INTEGER FP34=1;
+    INTEGER FP40=2;
+    INTEGER FP41=3;
+    INTEGER FP42=4;
+    INTEGER FP50=5;
+    INTEGER FP51=6;
+    INTEGER FP60=7;
+    INTEGER FP61=8;
+    INTEGER FP62=9;
+    INTEGER UNKNOWN=127;
+    INTEGER UNSPECIFIED=0;
+    INTEGER QN132=1;
+    INTEGER VQ100=2;
+    INTEGER TQ144=3;
+    INTEGER PQ208=4;
+    INTEGER FG144=5;
+    INTEGER FG256=6;
+    INTEGER FG484=7;
+    INTEGER FG676=8;
+    INTEGER FG896=9;
+    INTEGER QN108=10;
+    INTEGER QN180=11;
+    INTEGER TQ100=12;
+    INTEGER CQ208=13;
+    INTEGER FG1152=14;
+    INTEGER BG456=15;
+    INTEGER UNDEFINED=63;
+    INTEGER GRADE_UNSPEC=0;
+    INTEGER GRADE_1=1;
+    INTEGER GRADE_2=2;
+    INTEGER GRADE_3=3;
+    INTEGER GRADE_F=4;
+    INTEGER GRADE_STD=5;
+    INTEGER GRADE_4=6;
+    INTEGER GRADE_UNDEF=7;
+ENDDATA;
+
+DATA PARAMETERS;
+    INTEGER FREQ =4;
+ENDDATA;
+
+DATA GV;
+    INTEGER ULOPT1_BITLOCATION =11;
+    INTEGER ULOPT0_BITLOCATION =10;
+    INTEGER ULUWE_BITLOCATION =9;
+    INTEGER ULARE_BITLOCATION =8;
+    INTEGER ULUPC_BITLOCATION =7;
+    INTEGER ULUFE_BITLOCATION =6;
+    INTEGER ULUFP_BITLOCATION =5;
+    INTEGER ULUFJ_BITLOCATION =4;
+    INTEGER ULFLR_BITLOCATION =3;
+    INTEGER ULULR_BITLOCATION =2;
+    INTEGER ULAWE_BITLOCATION =1;
+    INTEGER ULARD_BITLOCATION =0;
+    BOOLEAN BUFF128[128];
+    BOOLEAN BUFF32[32];
+    INTEGER I;
+    INTEGER J;
+    INTEGER TEMP;
+    INTEGER SDNUMBER;
+    INTEGER ROWNUMBER;
+    INTEGER DATAINDEX =0;
+    INTEGER FROMROWNUMBER =1;
+    INTEGER AESBLOCK;
+    BOOLEAN ID[32];
+    BOOLEAN PASS = 1;
+    BOOLEAN FADDR[3];
+    INTEGER STATUS =0;
+    BOOLEAN SILSIG[32] = $00000000;
+    BOOLEAN ISC_CONFIG_RESULT[18];
+    BOOLEAN VERIFYEOL[2];
+    BOOLEAN COMBERASESELECT[23];
+    BOOLEAN SECKEY_OK = 1;
+    BOOLEAN SECREG[44];
+    BOOLEAN ULUWE = 0;
+    BOOLEAN ULARE = 0;
+    BOOLEAN ULUPC = 0;
+    BOOLEAN ULUFE = 0;
+    BOOLEAN ULUFP = 0;
+    BOOLEAN ULUFJ = 0;
+    BOOLEAN ULFLR = 0;
+    BOOLEAN ULULR = 0;
+    BOOLEAN ULAWE = 0;
+    BOOLEAN ULARD = 0;
+    BOOLEAN ULOPT[2];
+    BOOLEAN SUROWCHECKSUM[16];
+    INTEGER SUROWCYCLECOUNT =0;
+    INTEGER ACT_UROW_CYCLE_COUNT =0;
+    BOOLEAN ACT_UROW_DESIGN_NAME[70] = $2be746469b7978e9c1;
+    BOOLEAN SUROWDESIGNNAME[70];
+    BOOLEAN SUROWPROGMETHOD[3];
+    BOOLEAN ACT_UROW_ALGO_VERSION[7] = $11;
+    BOOLEAN SUROWALGOVERSION[7];
+    BOOLEAN SUROW_PKG_TYPE[6];
+    BOOLEAN ACT_UROW_SW_VERSION[7];
+    BOOLEAN SUROW_SW_VERSION[7];
+    INTEGER PLAYERVERSIONVARIABLE =0;
+    INTEGER SCULPTORMAJORBASE =4;
+    INTEGER SCULPTORMINORBASE =50;
+    INTEGER PLAYER_VERSION_VARIABLE =0;
+    INTEGER SCULPTOR_MAJOR_BASE =4;
+    INTEGER SCULPTOR_MINOR_BASE =50;
+    BOOLEAN ACT_UROW_PROGRAM_SW[4] = $f;
+    BOOLEAN SUROWPROGRAMSW[4];
+    BOOLEAN SUROW_SPEED_GRADE[3];
+    BOOLEAN SUROW_SRAM_DISTURB[1];
+    BOOLEAN ISERASEONLY = 0;
+    BOOLEAN ISRESTOREDESIGN = 0;
+    BOOLEAN FLAGDISPLAYCYC = 0;
+    BOOLEAN BSRPATTERN[1056] = $924924924924924924924924924924924924924924924924
+        924924924924924924924924924924924924924924924924924924924924924924924924
+        924924924924924924924924924924924924924924924924924924924924924924924924
+        924924924924924924924924924924924924924924924924924924924924924924924924
+        ;
+    BOOLEAN SAMPLEMASK[1056] = $000000000000000000000000000000000000000000000000
+        000000000000000000000000000000000000000000000000000000000000000000000000
+        000000000000000000000000000000000000000000000000000000000000000000000000
+        000000000000000000000000000000000000000000000000000000000000000000000000
+        ;
+    BOOLEAN RLOCK[1248] = $7fffffcffffffbfffffeffffffbfffffefffffffffffffffffff3
+        fffffcffffff3fffffcffffff3fffffcffffff3fffffdffffff3fffffcffffff3fffffcf
+        fffff3fffffcffffff3fffffdffffff3fffffcffffff3fffffcffffff3fffffcffffff3f
+        ffffdffffff3fffffcffffff3fffffcffffff3fffffcffffff3fffffdfffffffffffffff
+        fffffffffffffffffffffffffffffffffffffffffff;
+    BOOLEAN ARRAYRONLY = 1;
+    BOOLEAN CHKARRAY = 0;
+    BOOLEAN FROMRONLY = 1;
+    BOOLEAN CHKFROM = 0;
+    BOOLEAN CHKNVM = 0;
+    BOOLEAN CHKSEC = 1;
+    BOOLEAN PERMLOCK = 0;
+    INTEGER HEX[16] = 70,69,68,67,66,65,57,56,55,54,53,52,51,50,49,48;
+    INTEGER NUMBEROFFROMROWS =8;
+    BOOLEAN INITIALIZE_DATA[5] = $00;
+    INTEGER SDTILE;
+    INTEGER NUMBEROFSDTILES =6;
+    INTEGER NUMBEROFMAPROWS =3444;
+    INTEGER IDREV;
+    INTEGER IDFAB;
+    INTEGER BM7DEVICE =0;
+    INTEGER BM1DEVICE =0;
+    BOOLEAN M1BUFF[128] = $acdd6548ccb488863e291eb18fe95077;
+    BOOLEAN M7BUFF[128] = $e137623a2eeee91126015f3f73664945;
+    BOOLEAN IDCODEVALUE[32] = $03b261cf;
+    BOOLEAN IDMASK[32] = $06ffffff;
+    INTEGER SECKEYCHK =0;
+    INTEGER DESIGNPKGTYPE =6;
+    BOOLEAN ACT_UROW_PROG_METHOD[3] = $1;
+    INTEGER LABEL_SEPARATOR =0;
+ENDDATA;
+
+DATA BITSTREAM;
+    BOOLEAN UROW[128];
+    BOOLEAN UROW_MASK[128] = $fffffffffffffffffffffffffe01ffc0;
+    BOOLEAN DATASTREAM[4298112] = @mA320000110040W0W000020G000400108002200000Ww0
+        rssso0000p@@lF999IjjjQp0000_@x@@IYaatcjD50000y_@V3HIIIORRRR36eXaa49jjDR1
+        0000@x_@HIg11I30000yxxt7Ig69u@@VCDCK3Wm61000_@V1H0vssMj90008@@z@69HIo000
+        049IIICIII2761000Gaaa0Yaa4O3CGaaa4XaaaQu0aaaaWaaag1g0Oaa89Wa4910GDy0IIII
+        10000100602WaaaC16a47q570000GIIIID8dsssMssssS899H9000ejjLRkjDRpIIaa7000u
+        sijjqgjj4HIII00000RRRRORRB1aaayU8e6G0sMMaQW2ossWg1Aejj59DiGDW4sORRssba89
+        7000mskWKWaaa4P0000B99Hoba89dscjTc499RIaaa9IIIiPRRxHIIIMIIIY899HWjjjQ899
+        HZaa89IIYCHRhsMIIaqIIaaa85IMYPRRRGQIQIDW0A98qijjb8D99a6AGIYjTQW0a899IYaa
+        89qsc68e6uX9999kjjjw899HcaaKG8Gssscjaaa8B10999JT4WaaaurPGnYWSb1899f90008
+        GIIY90000GIIa600r02W00000IQYa00000a89110000aC9D100W0G6IMoHpWQ01T2LK3S109
+        9fQ07wTCeOXW103g1EeohWQ02Qo800004100WQW30000M2jmSG1r0408000010HM44f19q85
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+        a8080K3KWssMeqW5ORaaa6aGD07OIIIIvEe6G1QRRRmsssS999Hi@@t@sscjZjDRRIIaam@z
+        @FRN3GWsZa499y@_@7Rrssqgjz6HIIISDm1cjl9h1KWRRBYaaaOV@@Ff15ej999DGXQW2w4G
+        e6O3LIII4@@@zjjjPpQRhWW04@@@_GRRrMRRpsijLRxlDRRtMjjTtijjNrss6pssssssscss
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+        IWa89GIIIaaaW8899GIIIYiaa489992IIYaaaa81IIA5020IIIM3012GIIg1e0aaaar0GGcc
+        4a6m1IGIKg1m08999f1GGD09K701r0KG304K3m154iGQ058B99H2aiKE1FK302Iaaa8999H2
+        GIAd04WWaa8899JIII2489fe1Ae603aaaaaJ03aaaa8889L3m1O199HGGIM3W2f1Km806K30
+        4v4GHWJz6JtNPO4o@GOaWWDT6GHJWe4S2oN3PpU0p4SoFf2mG22aKj341d8JX740IKIAHaBo
+        A1XsF8WWa4K88Ga8I5r0WW4aaaQ0k8DW92EfYQ0A0299PE1Oq9m2bae0199f6JK0981PR1jG
+        GIIAd0JALmWXhNeXXDMqPXQ0S8w36I3u1G2001FAHH9GqAX6L3R08999I1009FG02000Gaaa
+        zbVGOoACxi1LAVGD0KLGW45NKm99D0102O502404GSL24WGW06GuYeCEOEW209004b018080
+        Y8Y0G0G0r0KW8W0Wf1Cu5W2G202008WG800mnBL0100eB02aaWaO00W6GIIYS0012A99I20W
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+        0QZa409000If1G0e0Ipq0AWacaKQ04W6a48D028891e0W0Yaaa8mGG0IIII8O981898L301I
+        IIIC000KGG100G9HII0000miJw4C999G1000ea4481004KI240000I49H2G000049GIGW248
+        GGG00100aN9CG0I020200H2IIr0KGG3504Wai6W22QmWq080W0GWWW0e_c88DW6w48XQ0QeW
+        02aa2000G99wX2KIIIEn01IIIIGII2_KU1aW20wVWWo080GII0C0000G6I45000081H22000
+        0aGg550809Oey2eaa0K301DYNW4WaaQ0AuLZ2G2I2c6m58393h1W0H9H1r0Km904q902P4K0
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+        KImQ08eW03a8a8a603T2aHB@6KWH10A99x4W04999v4Gm00FrMa63QmGdqjC2g8bcovEXKDu
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+        Ju4e5QjBIMIIQhk49B100W0I2wj00aaaQ100g101iaa4f1GWia400000oIIIA8O30I2019G0
+        G20WiBG020aKV040919f4028181K0218090w3eWtI80I20GD05a3Y1b7Kmom5a6G7r0aHerR
+        G206uYv2W3000G99fE02W990qP2120204000CKy1f2OmE980II2uxu48189LVY1H3GGQ0RK3
+        G6XM@HdqAWWIIYi00Gdq50008GabaLT370G0G0999Ria48P991G00Gg3A0G20eE020200KHE
+        7O1000Iaa8910080oYaa002049oII082G28R999qQEQVf09914XMZ0G0Ioqe90240KD05809
+        0evv60800W0Wai6W2IZMYq0A0WW40900102G2W40001011G2G0a04Gd0N4Qz7WC00wak1WGa
+        a09300024K3m2f8S00a449080h9HGD0IaJW1f1G00199II0204Wa89900202WaWaGE14q9W5
+        XMJoM8YS7p9BSbHXEhC0WD4040s3KbqakAVWCsOHdu4EO_NbcO0X6m1yh16_OGYU2oO602wK
+        8Xu0Aegf3IltWkAgOFXMk3WWS2OOkYNgUeYS2s8m9hobQklsfAf2ZIBGYLsg02m0G304SMW5
+        pfGGEMMiBX2d2qGv7c8020OY08o9uWGhVePW2o9mWHAeOxN4o90ZCdTe7x72dGM4400T64X0
+        00WM08eanX0200M3W3r10Hq0dKvR4THMKerxKbG1X@3HerBM3G502002DGXANWew0C0801ag
+        Q61S6pW0808108F02EcgWZ8C0G0WmY2A020Wu56FU8uWXHS0600GA09G040uDY5Qhvaz1A8c
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+        JGI2ITg40IIIYaaWC99R8IGIIaba4G2IIahA1I2I2aaba09891IMIYWaW49989jLx0aaaaGh
+        z199Df0GIIe4aar0KWf9H92I2Gaqai0999WaaaeJ02qaa48999HQIJId04GQIIYaaa0JIIIX
+        aWa4999H0IGYacWirrL2jUcI5A8CCCkOeYKwh89feYXgWQ0K0W000H00WEHge20201004Z11
+        200H6JSH2040nmGNko9rM0Yb1Gmy99iUrGX@h1201Wy9A8b662gXYahqAd0Agjd0899A5UOW
+        WaWa2F8WbaaHm96Waaaena2EEfWsFMmIIIYWa4agGc9qwOGGIIM301IMIo4aaaG919HGMII_
+        A7WabaK8999YIIoPT9eJ03cBWWS288V52Y6uXMM88u4ewXAioBsHaaa41000GIIIa2000099
+        HI6000Ga4993WQ0G0Waa4900WQ08ukO5g1Wg22K0100G117iZVFLqL5400W228GIIIY10008
+        999o1000eaa89008m02QVXWycDerv3g18XFa8e6WeC0000899fW05W999zkq1caaae0000KI
+        IAR12KIIIsM01rDeLD0KKGG2f0Gmxr6KG01X0O0GIIIK000L1G010000999o000w3uWQD88H
+        W4UFuWQ0kgW0A4000a6W10A99J3W04999r00Hd0HK3mL54uGKEwD0m@30ml080WecUO9T5lF
+        YXSCkBOuIwjYpKH_FqwOwNcniWRe605kmhX9QHBLLC_md00081R3OWW04WV28uni2cVrWr0E
+        0810viI5aB23RrJmJ1Ia6TKXM@G898L30a9b7L66P6QjC30yVQDn_qB7bHS18W4Ws2CBdWPI
+        Rcew64CE1bQOEblc7AE1HgLGlSfui0dPJhHbJLrAr1cAvcXU4o2998PdqBGGIKgqK42VrW2g
+        te60d2Vj2f999r0G0f98fQ0CW4a4499fhS28GQIKYaa4qE1O0GIIId0581999QW680915QjN
+        DCi2W08WaaKBH4U28PmGh@Fm9Pp9mo2FoGYa4Kx7PK3G3ab4a2jMhS2meJWC0IIIcJGPfEGJ
+        14K5Qz@XM@Ver@7QDm30y@00O7GR39N_V1eAd3wf30qyrwTbuxFv4yGGTDcVCO9NES1rf6Qz
+        @TM@VerblzoOj5yJE1n5Qznn9yVer@7gJO99nPeEoSRJ6XMpKdqDGMIKALL6AeU31998XMBM
+        tgDGMIKAqw2a5aaajj7r04Ler9baKRn_zVeEWdM3dfSTNerla8IWv4mPu4Sgjjjb1000c@RV
+        VIIIaQQRrc1000y@c@@b499lDRRB0000uz@@FYaaamssss606uXaa49jjTD0Cf100W0000@3
+        00OI000R100a000Wy100O40003WmaBWOIIIX270aaa4WaaqxL78IIIYGIIID07Waaaivv3g1
+        0A0610dxl0I000G20091SGzm4i1W1GIIIQoeXcPK8bO3g1eA400Wr0eGT17awG2iiajvGIIY
+        I000GRRhsSR9scba89F000mjPRRfLRRBIbo6ORRR3RRRhWaaaz08e60dq000m600WB100C00
+        WK78WB00Wa00WD08GIIIYRP29EjjjwijjPtaa89JYaaORhssRRssUIaaa8HIIYPRRRKRRR39
+        999aaaaWsssiqssgbaai60ca000O200WR100CB00W9000o400Gs000i68SY20IQJcwG1@SJ0
+        0GIRa4800000ZpeWjkFOyX4oNGXQ0Q2Wa0m8ZM01000810GUu702081I0WG945q_k2jYVGM4
+        JK30IzROGD08qaU154SWQBGRE999DKS0a6mM1III4200YgZ0rsssrQe0ssss2qDO002g1m9r
+        aaaO200c1d00000OHII49000089H2QRhsmsRiT99IIi@z@@sgjjZLjRRYaaaG@@@FssssWjj
+        jPIIIYm@@lVijDRJRRNMG0Y@@@Q0Uocaa4iaa4LIII4@JIai99How9HIca499_499Xsijjsi
+        @jPpssstMosERRRRTxVRUjjjPijaPxjjLRjjDRZssnAAWjjjDijjDpsssCsssinssM30Jsaa
+        aqsssQRIIYSRRhsD99IcjjQxta89nsgjz08ek@3Vjy10_FqwNQtqW8wX8ek@3jkb25OewwF3
+        Ev@WJ_Fuaw3uy@m_fEua@3Ev@10_FrXI11004SIij4MGZ9@7So@1gZLmm@7e_@1EzVm9mcNZ
+        11dyVm9FJG2Ig60609996So@jI020110040Gv0G040G0004002080022K3GX;
+    INTEGER CHECKSUM =58679;
+ENDDATA;
+
+
+PROCEDURE DO_EXIT USES GV;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $81;
+    WAIT IDLE, 20 USEC;
+    IF ( ! (STATUS!=0) ) THEN GOTO Label_0;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $07;
+    WAIT IDLE, 1 CYCLES;
+    Label_0:
+    WAIT 200 USEC;
+    STATE RESET ;
+    EXIT STATUS;
+ENDPROC;
+
+PROCEDURE DO_READ_SECURITY USES GV;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $a4;
+    WAIT IDLE, 3 CYCLES;
+    DRSCAN 44, $00000000000, CAPTURE SECREG[];
+    ULUWE = SECREG[ULUWE_BITLOCATION];
+    ULARE = SECREG[ULARE_BITLOCATION];
+    ULUPC = SECREG[ULUPC_BITLOCATION];
+    ULUFE = SECREG[ULUFE_BITLOCATION];
+    ULUFP = SECREG[ULUFP_BITLOCATION];
+    ULUFJ = SECREG[ULUFJ_BITLOCATION];
+    ULFLR = SECREG[ULFLR_BITLOCATION];
+    ULULR = SECREG[ULULR_BITLOCATION];
+    ULAWE = SECREG[ULAWE_BITLOCATION];
+    ULARD = SECREG[ULARD_BITLOCATION];
+    ULOPT[1] = SECREG[ULOPT1_BITLOCATION];
+    ULOPT[0] = SECREG[ULOPT0_BITLOCATION];
+ENDPROC;
+
+PROCEDURE DO_OUTPUT_SECURITY USES GV;
+    PRINT "Security Settings :";
+    IF ( ! (ULUFP==1) ) THEN GOTO Label_1;
+    PRINT "FlashROM Write/Erase protected by pass key.";
+    Label_1:
+    IF ( ! (ULUFJ==1) ) THEN GOTO Label_2;
+    PRINT "FlashROM Read protected by pass key.";
+    Label_2:
+    IF ( ! (ULAWE==1) ) THEN GOTO Label_3;
+    PRINT "Array Write/Erase protected by pass key.";
+    Label_3:
+    IF ( ! (ULARD==1) ) THEN GOTO Label_4;
+    PRINT "Array Verify protected by pass key.";
+    Label_4:
+    IF ( ! (ULUFE==1) ) THEN GOTO Label_5;
+    PRINT "Encrypted FlashROM Programming Enabled.";
+    Label_5:
+    IF ( ! (ULARE==1) ) THEN GOTO Label_6;
+    PRINT "Encrypted FPGA Array Programming Enabled.";
+    Label_6:
+    PRINT "=========================================";
+ENDPROC;
+
+PROCEDURE DO_QUERY_SECURITY USES DO_READ_SECURITY,DO_OUTPUT_SECURITY;
+    CALL DO_READ_SECURITY;
+    CALL DO_OUTPUT_SECURITY;
+ENDPROC;
+
+PROCEDURE READ_UROW USES BITSTREAM,GV;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $c0;
+    WAIT IDLE, 1 CYCLES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $a8;
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 132 USEC;
+    DRSCAN 128, $00000000000000000000000000000000, CAPTURE UROW[];
+    SUROWALGOVERSION[6..0] = $00;
+    IF ( ! ( (UROW[5]==0)&&(UROW[0]==1)) ) THEN GOTO Label_7;
+    SUROWALGOVERSION[5..4] = UROW[24..23];
+    Label_7:
+    IF ( ! ( (UROW[5]==1)&&(UROW[0]==0)) ) THEN GOTO Label_8;
+    SUROWALGOVERSION[5..4] = UROW[24..23];
+    SUROWALGOVERSION[6] = 1;
+    Label_8:
+    SUROWCHECKSUM[15..0] = UROW[127..112];
+    SUROWCYCLECOUNT = INT(UROW[111..102]);
+    SUROWDESIGNNAME[69..0] = UROW[101..32];
+    SUROWPROGMETHOD[2..0] = UROW[31..29];
+    SUROWALGOVERSION[3..0] = UROW[28..25];
+    SUROW_PKG_TYPE[5..0] = UROW[22..17];
+    SUROW_SW_VERSION[6..0] = UROW[16..10];
+    SUROWPROGRAMSW[3..0] = UROW[9..6];
+    SUROW_SRAM_DISTURB[0] = UROW[4];
+    SUROW_SPEED_GRADE[2..0] = UROW[3..1];
+    ACT_UROW_CYCLE_COUNT = SUROWCYCLECOUNT;
+ENDPROC;
+
+PROCEDURE FIX_INT_ARRAYS USES GV;
+    IF ( ! (HEX[0]!=48) ) THEN GOTO Label_9;
+    FOR I = 0 TO 7;
+        TEMP = HEX[I];
+        HEX[I] = HEX[(15-I)];
+        HEX[(15-I)] = TEMP;
+    NEXT I;
+    Label_9:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DISP_CHKSUM_DESIGN USES GV,FIX_INT_ARRAYS;
+    CALL FIX_INT_ARRAYS;
+    PRINT "CHECKSUM: ",CHR$(HEX[INT(SUROWCHECKSUM[15..12])]),CHR$(HEX[INT(SUROWCHECKSUM[11..8])])
+        ,CHR$(HEX[INT(SUROWCHECKSUM[7..4])]),CHR$(HEX[INT(SUROWCHECKSUM[3..0])]);
+    PRINT "Design Name: ",CHR$(INT(SUROWDESIGNNAME[63..69])),CHR$(INT(SUROWDESIGNNAME[56..62]))
+        ,CHR$(INT(SUROWDESIGNNAME[49..55])),CHR$(INT(SUROWDESIGNNAME[42..48])),CHR$(INT(SUROWDESIGNNAME[35..41]))
+        ,CHR$(INT(SUROWDESIGNNAME[28..34])),CHR$(INT(SUROWDESIGNNAME[21..27])),CHR$(INT(SUROWDESIGNNAME[14..20]))
+        ,CHR$(INT(SUROWDESIGNNAME[7..13])),CHR$(INT(SUROWDESIGNNAME[0..6]));
+ENDPROC;
+
+PROCEDURE DISPLAY_UROW USES CONSTBLOCK,GV,DISP_CHKSUM_DESIGN;
+    PRINT "User information: ";
+    CALL DISP_CHKSUM_DESIGN;
+    IF ( ! (FLAGDISPLAYCYC==1) ) THEN GOTO Label_10;
+    PRINT "CYCLE COUNT: ",SUROWCYCLECOUNT;
+    Label_10:
+    INTEGER TMPINT =INT(SUROWPROGMETHOD[]);
+    INTEGER TMPINT2 =0;
+    INTEGER TMPINT3 =0;
+    INTEGER TMPINT4 =0;
+    INTEGER TMPINT5 =0;
+    IF ( ! (TMPINT==IEEE1532) ) THEN GOTO Label_11;
+    PRINT "Programming Method: IEEE1532";
+    Label_11:
+    IF ( ! (TMPINT==STAPL) ) THEN GOTO Label_12;
+    PRINT "Programming Method: STAPL";
+    Label_12:
+    IF ( ! (TMPINT==DIRECTC) ) THEN GOTO Label_13;
+    PRINT "Programming Method: DirectC";
+    Label_13:
+    IF ( ! (TMPINT==PDB) ) THEN GOTO Label_14;
+    PRINT "Programming Method: PDB";
+    Label_14:
+    IF ( ! (TMPINT==SVF) ) THEN GOTO Label_15;
+    PRINT "Programming Method: SVF";
+    Label_15:
+    PRINT "Algorithm Version: ",INT(SUROWALGOVERSION[6..0]);
+    TMPINT = INT(SUROW_PKG_TYPE[]);
+    IF ( ! (TMPINT==UNSPECIFIED) ) THEN GOTO Label_16;
+    PRINT "Device Package Type: package information not available from device";
+    Label_16:
+    IF ( ! (TMPINT==QN132) ) THEN GOTO Label_17;
+    PRINT "Device Package Type: QN132/QNG132";
+    Label_17:
+    IF ( ! (TMPINT==VQ100) ) THEN GOTO Label_18;
+    PRINT "Device Package Type: VQ100/VQG100";
+    Label_18:
+    IF ( ! (TMPINT==TQ144) ) THEN GOTO Label_19;
+    PRINT "Device Package Type: TQ144/TQG144";
+    Label_19:
+    IF ( ! (TMPINT==PQ208) ) THEN GOTO Label_20;
+    PRINT "Device Package Type: PQ208/PQG208";
+    Label_20:
+    IF ( ! (TMPINT==FG144) ) THEN GOTO Label_21;
+    PRINT "Device Package Type: FG144/FGG144";
+    Label_21:
+    IF ( ! (TMPINT==FG256) ) THEN GOTO Label_22;
+    PRINT "Device Package Type: FG256/FGG256";
+    Label_22:
+    IF ( ! (TMPINT==FG484) ) THEN GOTO Label_23;
+    PRINT "Device Package Type: FG484/FGG484";
+    Label_23:
+    IF ( ! (TMPINT==FG676) ) THEN GOTO Label_24;
+    PRINT "Device Package Type: FG676/FGG676";
+    Label_24:
+    IF ( ! (TMPINT==FG896) ) THEN GOTO Label_25;
+    PRINT "Device Package Type: FG896/FGG896";
+    Label_25:
+    IF ( ! (TMPINT==QN108) ) THEN GOTO Label_26;
+    PRINT "Device Package Type: QN108/QNG108";
+    Label_26:
+    IF ( ! (TMPINT==QN180) ) THEN GOTO Label_27;
+    PRINT "Device Package Type: QN180/QNG180";
+    Label_27:
+    IF ( ! (TMPINT==TQ100) ) THEN GOTO Label_28;
+    PRINT "Device Package Type: TQ100/TQG100";
+    Label_28:
+    IF ( ! (TMPINT==CQ208) ) THEN GOTO Label_29;
+    PRINT "Device Package Type: CQ208/CQG208";
+    Label_29:
+    IF ( ! (TMPINT==FG1152) ) THEN GOTO Label_30;
+    PRINT "Device Package Type: FG1152/FGG1152";
+    Label_30:
+    IF ( ! (TMPINT==BG456) ) THEN GOTO Label_31;
+    PRINT "Device Package Type: BG456/BGG456";
+    Label_31:
+    IF ( ! (TMPINT==UNDEFINED) ) THEN GOTO Label_32;
+    PRINT "Device Package Type: package information not available from device";
+    Label_32:
+    TMPINT = INT(SUROW_SPEED_GRADE[]);
+    IF ( ! (TMPINT==GRADE_UNSPEC) ) THEN GOTO Label_33;
+    PRINT "Device Speed Grade: speed grade information not available from device";
+    Label_33:
+    IF ( ! (TMPINT==GRADE_1) ) THEN GOTO Label_34;
+    PRINT "Device Speed Grade: -1";
+    Label_34:
+    IF ( ! (TMPINT==GRADE_2) ) THEN GOTO Label_35;
+    PRINT "Device Speed Grade: -2";
+    Label_35:
+    IF ( ! (TMPINT==GRADE_3) ) THEN GOTO Label_36;
+    PRINT "Device Speed Grade: -3";
+    Label_36:
+    IF ( ! (TMPINT==GRADE_F) ) THEN GOTO Label_37;
+    PRINT "Device Speed Grade: -F";
+    Label_37:
+    IF ( ! (TMPINT==GRADE_STD) ) THEN GOTO Label_38;
+    PRINT "Device Speed Grade: STD";
+    Label_38:
+    IF ( ! (TMPINT==GRADE_4) ) THEN GOTO Label_39;
+    PRINT "Device Speed Grade: -4";
+    Label_39:
+    IF ( ! (TMPINT==GRADE_UNDEF) ) THEN GOTO Label_40;
+    PRINT "Device Speed Grade: speed grade information not available from device";
+    Label_40:
+    TMPINT = INT(SUROWPROGRAMSW[]);
+    IF ( ! (TMPINT==FP) ) THEN GOTO Label_41;
+    PRINT "Programmer: FlashPro";
+    Label_41:
+    IF ( ! (TMPINT==FPLITE) ) THEN GOTO Label_42;
+    PRINT "Programmer: FlashPro Lite";
+    Label_42:
+    IF ( ! (TMPINT==FP3) ) THEN GOTO Label_43;
+    PRINT "Programmer: FlashPro3";
+    Label_43:
+    IF ( ! (TMPINT==SCULPTW) ) THEN GOTO Label_44;
+    PRINT "Programmer: SiliconSculptor II";
+    Label_44:
+    IF ( ! (TMPINT==BPW) ) THEN GOTO Label_45;
+    PRINT "Programmer: BP Programmer";
+    Label_45:
+    IF ( ! (TMPINT==DIRECTCP) ) THEN GOTO Label_46;
+    PRINT "Programmer: DirectC";
+    Label_46:
+    IF ( ! (TMPINT==STP) ) THEN GOTO Label_47;
+    PRINT "Programmer: Actel JAM Player";
+    Label_47:
+    IF ( ! ( ( (TMPINT==FP)||(TMPINT==FPLITE))||(TMPINT==FP3)) ) THEN GOTO Label_59;
+    TMPINT2 = INT(SUROW_SW_VERSION[]);
+    IF ( ! (TMPINT2==FP33) ) THEN GOTO Label_48;
+    PRINT "Software: FlashPro v3.3";
+    Label_48:
+    IF ( ! (TMPINT2==FP34) ) THEN GOTO Label_49;
+    PRINT "Software: FlashPro v3.4";
+    Label_49:
+    IF ( ! (TMPINT2==FP40) ) THEN GOTO Label_50;
+    PRINT "Software: FlashPro v4.0";
+    Label_50:
+    IF ( ! (TMPINT2==FP41) ) THEN GOTO Label_51;
+    PRINT "Software: FlashPro v4.1";
+    Label_51:
+    IF ( ! (TMPINT2==FP42) ) THEN GOTO Label_52;
+    PRINT "Software: FlashPro v4.2";
+    Label_52:
+    IF ( ! (TMPINT2==FP50) ) THEN GOTO Label_53;
+    PRINT "Software: FlashPro v5.0";
+    Label_53:
+    IF ( ! (TMPINT2==FP51) ) THEN GOTO Label_54;
+    PRINT "Software: FlashPro v5.1";
+    Label_54:
+    IF ( ! (TMPINT2==FP60) ) THEN GOTO Label_55;
+    PRINT "Software: FlashPro v6.0";
+    Label_55:
+    IF ( ! (TMPINT2==FP61) ) THEN GOTO Label_56;
+    PRINT "Software: FlashPro v6.1";
+    Label_56:
+    IF ( ! (TMPINT2==FP62) ) THEN GOTO Label_57;
+    PRINT "Software: FlashPro v6.2";
+    Label_57:
+    IF ( ! (TMPINT2==UNKNOWN) ) THEN GOTO Label_58;
+    PRINT "Software: FlashPro vX.X";
+    Label_58:
+    LABEL_SEPARATOR = 0;
+    Label_59:
+    IF ( ! ( (TMPINT==SCULPTW)||(TMPINT==BPW)) ) THEN GOTO Label_63;
+    TMPINT3 = (INT(SUROW_SW_VERSION[6..5])+SCULPTORMAJORBASE);
+    TMPINT4 = (INT(SUROW_SW_VERSION[4..1])+SCULPTORMINORBASE);
+    TMPINT5 = 0;
+    IF ( ! (SUROW_SW_VERSION[0]==1) ) THEN GOTO Label_60;
+    TMPINT5 = 1;
+    Label_60:
+    IF ( ! (TMPINT==SCULPTW) ) THEN GOTO Label_61;
+    PRINT "Software: Sculptor Win v",TMPINT3,".",TMPINT4,".",TMPINT5;
+    Label_61:
+    IF ( ! (TMPINT==BPW) ) THEN GOTO Label_62;
+    PRINT "Software: BP Win v",TMPINT3,".",TMPINT4,".",TMPINT5;
+    Label_62:
+    LABEL_SEPARATOR = 0;
+    Label_63:
+    PRINT "=========================================";
+ENDPROC;
+
+PROCEDURE READ_F_ROW USES GV;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $c0;
+    WAIT IDLE, 1 CYCLES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $f9;
+    DRSCAN 3, FADDR[];
+    WAIT IDLE, 1 CYCLES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $bf;
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 132 USEC;
+    DRSCAN 128, $00000000000000000000000000000000, CAPTURE BUFF128[];
+ENDPROC;
+
+PROCEDURE DO_DEVICE_INFO USES GV,READ_UROW,DISPLAY_UROW,READ_F_ROW;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $0e;
+    WAIT IDLE, 1 CYCLES;
+    DRSCAN 32, $00000000, CAPTURE BUFF32[];
+    EXPORT "SILSIG", BUFF32[];
+    CALL READ_UROW;
+    CALL DISPLAY_UROW;
+    FADDR[] = $0;
+    CALL READ_F_ROW;
+    EXPORT "FSN", BUFF128[55..8];
+    PRINT "=========================================";
+ENDPROC;
+
+PROCEDURE INIT_AES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $dd;
+    DRSCAN 128, $00000000000000000000000000000000;
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 120 USEC;
+ENDPROC;
+
+PROCEDURE DO_VERIFY_DEVICE_INFO USES GV,BITSTREAM,DO_EXIT,DO_READ_SECURITY,READ_UROW
+    ,DISP_CHKSUM_DESIGN;
+    CALL READ_UROW;
+    CALL DISP_CHKSUM_DESIGN;
+    CALL DO_READ_SECURITY;
+    BUFF32[31..0] = BOOL(CHECKSUM);
+    UROW[127..112] = BUFF32[15..0];
+    UROW[101..32] = ACT_UROW_DESIGN_NAME[69..0];
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $c0;
+    WAIT IDLE, 1 CYCLES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $a8;
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 264 USEC;
+    DRSCAN 128, $00000000000000000000000000000000,COMPARE UROW[],$ffff003fffffffffffffffff00000000
+        ,PASS;
+    IF ( ! (PASS==0) ) THEN GOTO UROW_CMP_OK;
+    STATUS = -43;
+    PRINT "UROW setting error.";
+    CALL DO_EXIT;
+    UROW_CMP_OK:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE READ_IDCODE_ONLY USES GV;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $0f;
+    WAIT IDLE, 1 CYCLES;
+    DRSCAN 32, $00000000, CAPTURE ID[];
+    EXPORT "IDCODE", ID[];
+ENDPROC;
+
+PROCEDURE VERIFY_ID_DMK USES GV,DO_EXIT,INIT_AES;
+    CALL INIT_AES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $0a;
+    DRSCAN 128, M7BUFF[];
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 128 USEC;
+    DRSCAN 128, $00000000000000000000000000000000, CAPTURE BUFF128[],COMPARE $c0000000000000000000000000000000
+        ,$c0000000000000000000000000000000,PASS;
+    IF ( ! (BUFF128[127]==0) ) THEN GOTO M7VERDONE;
+    STATUS = -31;
+    PRINT "Failed to verify AES Sec.";
+    CALL DO_EXIT;
+    M7VERDONE:
+    IF ( ! ( (BUFF128[126]==0)||(BM7DEVICE==0)) ) THEN GOTO MXIDOK;
+    IF ( ! ( (BUFF128[126]==1)&&(BM7DEVICE==0)) ) THEN GOTO LDETECTM1;
+    STATUS = -32;
+    PRINT "Failed to verify IDCODE.";
+    PRINT "M7 Device detected.";
+    CALL DO_EXIT;
+    LDETECTM1:
+    IF ( ! (BUFF128[126]==0) ) THEN GOTO Label_66;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $0a;
+    DRSCAN 128, M1BUFF[];
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 128 USEC;
+    DRSCAN 128, $00000000000000000000000000000000, CAPTURE BUFF128[],COMPARE $c0000000000000000000000000000000
+        ,$c0000000000000000000000000000000,PASS;
+    IF ( ! (BUFF128[127]==0) ) THEN GOTO M1VERDONE;
+    STATUS = -31;
+    PRINT "Failed to verify AES Sec.";
+    CALL DO_EXIT;
+    M1VERDONE:
+    BOOLEAN BTMPBUFFBIT126 = BUFF128[126];
+    IF ( ! ( (BTMPBUFFBIT126==1)&&(BM1DEVICE==0)) ) THEN GOTO REGDEV;
+    STATUS = -32;
+    PRINT "Failed to verify IDCODE.";
+    PRINT "M1 Device detected.";
+    CALL DO_EXIT;
+    REGDEV:
+    IF ( ! ( (BTMPBUFFBIT126==0)&&(BM7DEVICE==1)) ) THEN GOTO Label_64;
+    STATUS = -32;
+    PRINT "Failed to verify IDCODE.";
+    PRINT "The Target is not an M7 Device.";
+    CALL DO_EXIT;
+    Label_64:
+    IF ( ! ( (BTMPBUFFBIT126==0)&&(BM1DEVICE==1)) ) THEN GOTO Label_65;
+    STATUS = -32;
+    PRINT "Failed to verify IDCODE.";
+    PRINT "The Target is not an M1 Device.";
+    CALL DO_EXIT;
+    Label_65:
+    LABEL_SEPARATOR = 0;
+    Label_66:
+    LABEL_SEPARATOR = 0;
+    MXIDOK:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE VERIFY_IDCODE USES GV,PARAMETERS,DO_EXIT;
+    FREQUENCY (FREQ*1000000);
+    WAIT RESET, 5 CYCLES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $0f;
+    DRSCAN 32, $00000000;
+    WAIT IDLE, 1 CYCLES;
+    DRSCAN 32, $00000000, CAPTURE ID[],COMPARE IDCODEVALUE[],IDMASK[],PASS;
+    IF ( ! (PASS==0) ) THEN GOTO IDOK;
+    STATUS = 6;
+    PRINT "Failed to verify IDCODE";
+    CALL DO_EXIT;
+    IDOK:
+    IDREV = INT(ID[31..28]);
+    IDFAB = INT(ID[24..24]);
+ENDPROC;
+
+PROCEDURE IS_SECOK USES GV,DO_EXIT;
+    IF ( ! (SECKEY_OK==0) ) THEN GOTO SECOK;
+    STATUS = -35;
+    PRINT "Error, pass key match failure";
+    CALL DO_EXIT;
+    SECOK:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DO_CHECK_R USES GV,DO_EXIT,DO_READ_SECURITY;
+    CALL DO_READ_SECURITY;
+    IF ( ! (ULARE==1) ) THEN GOTO ARRAYEPR;
+    STATUS = -33;
+    PRINT "FPGA Array Encryption is enforced. Plain text verification is prohibited.";
+    CALL DO_EXIT;
+    ARRAYEPR:
+    IF ( ! (ULARD==1) ) THEN GOTO SKIPRCHK1;
+    STATUS = -30;
+    PRINT "FPGA Array Verification is protected by pass key.";
+    PRINT "A valid pass key needs to be provided.";
+    CALL DO_EXIT;
+    SKIPRCHK1:
+    IF ( ! (ULARD==0) ) THEN GOTO Label_67;
+    CHKSEC = 0;
+    Label_67:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DO_CHECK_W USES GV,DO_EXIT,DO_READ_SECURITY;
+    CALL DO_READ_SECURITY;
+    IF ( ! (ULAWE==1) ) THEN GOTO ARRAYWP;
+    STATUS = -28;
+    PRINT "FPGA Array Write/Erase is protected by pass key.";
+    PRINT "A valid pass key needs to be provided.";
+    CALL DO_EXIT;
+    ARRAYWP:
+    IF ( ! (ULARD==1) ) THEN GOTO ARRAYRPW;
+    STATUS = -30;
+    PRINT "FPGA Array Verification is protected by pass key.";
+    PRINT "A valid pass key needs to be provided.";
+    CALL DO_EXIT;
+    ARRAYRPW:
+    IF ( ! (ULARE==1) ) THEN GOTO ARRAYEPW;
+    STATUS = -33;
+    PRINT "FPGA Array Encryption is enforced. Plain text programming is prohibited.";
+    CALL DO_EXIT;
+    ARRAYEPW:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE BP_VER USES GV;
+    BOOLEAN PLAYER_VERSION_BOOLEAN[32];
+    PLAYER_VERSION_BOOLEAN[31..0] = BOOL(PLAYERVERSIONVARIABLE);
+    INTEGER PLAYER_MAJOR_VERSION =(INT(PLAYER_VERSION_BOOLEAN[23..16])-SCULPTORMAJORBASE);
+    INTEGER PLAYER_MINOR_VERSION =(INT(PLAYER_VERSION_BOOLEAN[15..8])-SCULPTORMINORBASE);
+    ACT_UROW_SW_VERSION[6..5] = BOOL(PLAYER_MAJOR_VERSION);
+    ACT_UROW_SW_VERSION[4..1] = BOOL(PLAYER_MINOR_VERSION);
+    ACT_UROW_SW_VERSION[0] = PLAYER_VERSION_BOOLEAN[0];
+ENDPROC;
+
+PROCEDURE DO_INITIALIZE USES GV,DO_EXIT,VERIFY_ID_DMK,VERIFY_IDCODE,DO_CHECK_R,DO_CHECK_W
+    ,BP_VER;
+    CALL VERIFY_IDCODE;
+    BOOLEAN BSR[1056];
+    BOOLEAN SAMPLE_DEVICE[1056];
+    BSR[1055..0] = BSRPATTERN[1055..0];
+    BOOLEAN SHIFT_DATA[1056];
+    IRSCAN 8, $01;
+    DRSCAN 1056, BSR[];
+    WAIT IDLE, 1 CYCLES;
+    DRSCAN 1056, SHIFT_DATA[], CAPTURE SAMPLE_DEVICE[];
+    FOR I = 0 TO 1055;
+        IF ( ! (SAMPLEMASK[I]==1) ) THEN GOTO Label_68;
+        BSR[I] = SAMPLE_DEVICE[I];
+        Label_68:
+        LABEL_SEPARATOR = 0;
+    NEXT I;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $01;
+    DRSCAN 1056, BSR[];
+    WAIT IDLE, 1 CYCLES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $c0;
+    WAIT IDLE, 1 CYCLES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $80;
+    DRSCAN 18, $00000;
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 1000 USEC;
+    DRSCAN 18, $00000,COMPARE $30000,$30000,PASS;
+    IF ( ! (PASS==0) ) THEN GOTO CRCOK;
+    STATUS = -26;
+    PRINT "Failed to enter programming mode.";
+    EXPORT "ISC_Config_Result", ISC_CONFIG_RESULT[];
+    CALL DO_EXIT;
+    CRCOK:
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $84;
+    DRSCAN 5, INITIALIZE_DATA[], CAPTURE INITIALIZE_DATA[];
+    WAIT IDLE, 1 CYCLES;
+    IF ( ! (INITIALIZE_DATA[2]==1) ) THEN GOTO JTAGOK;
+    STATUS = -25;
+    PRINT "Failed to enter programming mode";
+    CALL DO_EXIT;
+    JTAGOK:
+    CALL VERIFY_ID_DMK;
+    IF ( ! (CHKARRAY==1) ) THEN GOTO SKIPCHKARRAY;
+    IF ( ! (ARRAYRONLY==0) ) THEN GOTO Label_69;
+    CALL DO_CHECK_W;
+    Label_69:
+    IF ( ! (ARRAYRONLY==1) ) THEN GOTO Label_70;
+    CALL DO_CHECK_R;
+    Label_70:
+    LABEL_SEPARATOR = 0;
+    SKIPCHKARRAY:
+    IF ( ! (PLAYERVERSIONVARIABLE!=0) ) THEN GOTO Label_71;
+    CALL BP_VER;
+    Label_71:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE READ_INITIALIZE USES GV,DO_INITIALIZE;
+    CHKFROM = 0;
+    CHKARRAY = 0;
+    CHKNVM = 0;
+    CHKSEC = 0;
+    CALL DO_INITIALIZE;
+ENDPROC;
+
+PROCEDURE NW_INITIALIZE USES GV,DO_INITIALIZE;
+    CHKFROM = 0;
+    CHKARRAY = 0;
+    CALL DO_INITIALIZE;
+ENDPROC;
+
+PROCEDURE NR_INITIALIZE USES GV,DO_INITIALIZE;
+    CHKFROM = 0;
+    CHKARRAY = 0;
+    CALL DO_INITIALIZE;
+ENDPROC;
+
+PROCEDURE AW_INITIALIZE USES GV,DO_INITIALIZE;
+    ARRAYRONLY = 0;
+    CHKFROM = 0;
+    CHKARRAY = 1;
+    CHKNVM = 0;
+    CALL DO_INITIALIZE;
+ENDPROC;
+
+PROCEDURE AR_INITIALIZE USES GV,DO_INITIALIZE;
+    ARRAYRONLY = 1;
+    CHKFROM = 0;
+    CHKARRAY = 1;
+    CHKNVM = 0;
+    CALL DO_INITIALIZE;
+ENDPROC;
+
+PROCEDURE W_INITIALIZE USES GV,DO_INITIALIZE;
+    ARRAYRONLY = 0;
+    CHKARRAY = 1;
+    CALL DO_INITIALIZE;
+ENDPROC;
+
+PROCEDURE R_INITIALIZE USES GV,DO_INITIALIZE;
+    ARRAYRONLY = 1;
+    CHKARRAY = 1;
+    CALL DO_INITIALIZE;
+ENDPROC;
+
+PROCEDURE INITIALIZE USES GV,DO_INITIALIZE;
+    ARRAYRONLY = 0;
+    FROMRONLY = 0;
+    CHKFROM = 1;
+    CHKARRAY = 1;
+    CALL DO_INITIALIZE;
+ENDPROC;
+
+PROCEDURE POLL_ERASE USES GV;
+    PASS = 0;
+    INTEGER ILOOP_0;
+    FOR ILOOP_0 = 262141 - 1 TO 0 STEP -1;
+        IRSTOP IRPAUSE;
+        DRSTOP DRPAUSE;
+        IRSCAN 8, $84;
+        WAIT IDLE, 1 CYCLES;
+        WAIT IDLE, 1000 USEC;
+        DRSCAN 5, $00,COMPARE $00,$03,PASS;
+        IF PASS THEN ILOOP_0 = 0;
+    NEXT ILOOP_0;
+ENDPROC;
+
+PROCEDURE POLL_PROGRAM USES GV;
+    INTEGER ILOOP_1;
+    FOR ILOOP_1 = 16381 - 1 TO 0 STEP -1;
+        IRSTOP IRPAUSE;
+        DRSTOP DRPAUSE;
+        IRSCAN 8, $84;
+        WAIT IDLE, 1 CYCLES;
+        WAIT IDLE, 100 USEC;
+        DRSCAN 5, $00,COMPARE $00,$0b,PASS;
+        IF PASS THEN ILOOP_1 = 0;
+    NEXT ILOOP_1;
+ENDPROC;
+
+PROCEDURE PROGRAM_UROW USES GV,BITSTREAM,DO_EXIT,POLL_PROGRAM;
+    FOR FROMROWNUMBER = NUMBEROFFROMROWS TO 1 STEP -1;
+        IRSTOP IRPAUSE;
+        DRSTOP DRPAUSE;
+        IRSCAN 8, $9f;
+        DRSCAN 3, BOOL((FROMROWNUMBER-1));
+        WAIT IDLE, 1 CYCLES;
+        IRSTOP IRPAUSE;
+        DRSTOP DRPAUSE;
+        IRSCAN 8, $9b;
+        DRSCAN 128, $ffffffffffffffffffffffffffffffff;
+        WAIT IDLE, 5 CYCLES;
+        WAIT IDLE, 10000 USEC;
+    NEXT FROMROWNUMBER;
+    IF ( ! (ISERASEONLY==0) ) THEN GOTO SKIP_CYC_INCREMENT;
+    IF ( ! (ACT_UROW_CYCLE_COUNT==1023) ) THEN GOTO Label_72;
+    ACT_UROW_CYCLE_COUNT = (ACT_UROW_CYCLE_COUNT+1);
+    Label_72:
+    LABEL_SEPARATOR = 0;
+    SKIP_CYC_INCREMENT:
+    IF ( ! (ISERASEONLY==1) ) THEN GOTO Label_73;
+    UROW[] = $ffffffffffffffffffffffffffffffff;
+    Label_73:
+    IF ( ! ( (PERMLOCK==1)&&(ULAWE==1)) ) THEN GOTO Label_74;
+    ISRESTOREDESIGN = 1;
+    Label_74:
+    IF ( ! ( (ISERASEONLY==0)||(ISRESTOREDESIGN==1)) ) THEN GOTO SKIP_DESIGN_INFO;
+    BUFF32[31..0] = BOOL(CHECKSUM);
+    IF ( ! ( !ISRESTOREDESIGN) ) THEN GOTO Label_75;
+    UROW[127..112] = BUFF32[15..0];
+    Label_75:
+    IF ( ! ISRESTOREDESIGN ) THEN GOTO Label_76;
+    UROW[127..112] = SUROWCHECKSUM[15..0];
+    Label_76:
+    IF ( ! ( !ISRESTOREDESIGN) ) THEN GOTO Label_77;
+    UROW[101..32] = ACT_UROW_DESIGN_NAME[69..0];
+    Label_77:
+    IF ( ! ISRESTOREDESIGN ) THEN GOTO Label_78;
+    UROW[101..32] = SUROWDESIGNNAME[69..0];
+    Label_78:
+    LABEL_SEPARATOR = 0;
+    SKIP_DESIGN_INFO:
+    BUFF32[31..0] = BOOL(ACT_UROW_CYCLE_COUNT);
+    UROW[111..102] = BUFF32[9..0];
+    UROW[31..29] = ACT_UROW_PROG_METHOD[2..0];
+    UROW[28..25] = ACT_UROW_ALGO_VERSION[3..0];
+    UROW[16..10] = ACT_UROW_SW_VERSION[6..0];
+    UROW[9..6] = ACT_UROW_PROGRAM_SW[3..0];
+    UROW[4] = SUROW_SRAM_DISTURB[0];
+    IF ( ! (ACT_UROW_ALGO_VERSION[6]==1) ) THEN GOTO Label_79;
+    UROW[5] = 1;
+    UROW[0] = 0;
+    UROW[24..23] = ACT_UROW_ALGO_VERSION[5..4];
+    Label_79:
+    IF ( ! (ACT_UROW_ALGO_VERSION[6]==0) ) THEN GOTO Label_80;
+    UROW[5] = 0;
+    UROW[0] = 1;
+    UROW[24..23] = ACT_UROW_ALGO_VERSION[5..4];
+    Label_80:
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $a7;
+    DRSCAN 128, UROW[];
+    WAIT IDLE, 15 CYCLES;
+    CALL POLL_PROGRAM;
+    IF ( ! (PASS==0) ) THEN GOTO PROGRAM_OK3;
+    STATUS = -24;
+    PRINT "Failed to program UROW";
+    CALL DO_EXIT;
+    PROGRAM_OK3:
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $c0;
+    WAIT IDLE, 1 CYCLES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $a8;
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 132 USEC;
+    DRSCAN 128, $00000000000000000000000000000000,COMPARE UROW[],UROW_MASK[],PASS;
+    IF ( ! (PASS==0) ) THEN GOTO UROW_OK;
+    STATUS = -24;
+    PRINT "Failed to program UROW";
+    CALL DO_EXIT;
+    UROW_OK:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE FAIL_ERASE USES GV,DO_EXIT;
+    STATUS = 8;
+    PRINT "Failed Erase Operation";
+    CALL DO_EXIT;
+ENDPROC;
+
+PROCEDURE EXE_ERASE USES BITSTREAM,GV,READ_UROW,POLL_ERASE,PROGRAM_UROW,FAIL_ERASE;
+    IF ( ! (COMBERASESELECT[14]==1) ) THEN GOTO SKIPRUROW;
+    CALL READ_UROW;
+    EXPORT "ACTEL_SLOG_UROW", UROW[];
+    SKIPRUROW:
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $85;
+    DRSCAN 23, COMBERASESELECT[];
+    WAIT IDLE, 3 CYCLES;
+    CALL POLL_ERASE;
+    IF ( ! (PASS==0) ) THEN GOTO ERASEOK;
+    CALL FAIL_ERASE;
+    ERASEOK:
+    IF ( ! (COMBERASESELECT[14]==1) ) THEN GOTO Label_81;
+    CALL PROGRAM_UROW;
+    Label_81:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DO_ERASE USES GV,EXE_ERASE;
+    PRINT "Erase ...";
+    COMBERASESELECT[22..0] = $004000;
+    COMBERASESELECT[0] = 1;
+    CALL EXE_ERASE;
+    PRINT "Completed erase";
+ENDPROC;
+
+PROCEDURE DO_ERASE_ARRAY USES GV,EXE_ERASE;
+    PRINT "Erase FPGA Array ...";
+    COMBERASESELECT[22..0] = $004001;
+    CALL EXE_ERASE;
+ENDPROC;
+
+PROCEDURE DO_ERASE_ONLY USES GV,DO_ERASE;
+    ISERASEONLY = 1;
+    CALL DO_ERASE;
+ENDPROC;
+
+PROCEDURE DO_ERASE_ARRAY_ONLY USES GV,DO_ERASE_ARRAY;
+    ISERASEONLY = 1;
+    CALL DO_ERASE_ARRAY;
+ENDPROC;
+
+PROCEDURE DO_ERASE_ALL USES GV,EXE_ERASE;
+    IF ( ! ( (BM7DEVICE==1)||(BM1DEVICE==1)) ) THEN GOTO Label_82;
+    PRINT "Erase FPGA Array and FlashROM ...";
+    Label_82:
+    IF ( ! ( (BM7DEVICE!=1)&&(BM1DEVICE!=1)) ) THEN GOTO Label_83;
+    PRINT "Erase FPGA Array, FlashROM and Security Settings ...";
+    Label_83:
+    COMBERASESELECT[22..0] = $7fc00f;
+    ISERASEONLY = 1;
+    CALL EXE_ERASE;
+ENDPROC;
+
+PROCEDURE LOAD_ROW_DATA USES BITSTREAM,GV;
+    FOR SDTILE = 1 TO NUMBEROFSDTILES;
+        FOR I = 1 TO 8;
+            IRSTOP IRPAUSE;
+            DRSTOP DRPAUSE;
+            IRSCAN 8, $89;
+            DRSCAN 26, DATASTREAM[(DATAINDEX+25)..DATAINDEX];
+            WAIT IDLE, 3 CYCLES;
+            DATAINDEX = (DATAINDEX+26);
+        NEXT I;
+    NEXT SDTILE;
+ENDPROC;
+
+PROCEDURE EXE_PROGRAM USES GV,DO_EXIT,POLL_PROGRAM;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $83;
+    WAIT IDLE, 3 CYCLES;
+    CALL POLL_PROGRAM;
+    IF ( ! (PASS==0) ) THEN GOTO Label_84;
+    STATUS = 10;
+    PRINT "Failed to program FPGA array at row ",ROWNUMBER,".";
+    CALL DO_EXIT;
+    Label_84:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE EXE_VERIFY USES GV,DO_EXIT,POLL_PROGRAM;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $8d;
+    DRSCAN 2, VERIFYEOL[];
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 132 USEC;
+    CALL POLL_PROGRAM;
+    IF ( ! (PASS==0) ) THEN GOTO Label_85;
+    STATUS = 11;
+    PRINT "Verify 0 failed at row ",ROWNUMBER,".";
+    CALL DO_EXIT;
+    Label_85:
+    IRSCAN 8, $8d;
+    DRSCAN 2, VERIFYEOL[],COMPARE $0,$3,PASS;
+    IF ( ! (PASS==0) ) THEN GOTO Label_86;
+    STATUS = 11;
+    PRINT "Verify 0 failed at row ",ROWNUMBER,".";
+    CALL DO_EXIT;
+    Label_86:
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $8e;
+    DRSCAN 2, VERIFYEOL[];
+    WAIT IDLE, 3 CYCLES;
+    WAIT IDLE, 132 USEC;
+    CALL POLL_PROGRAM;
+    IF ( ! (PASS==0) ) THEN GOTO Label_87;
+    STATUS = 11;
+    PRINT "Verify 1 failed at row ",ROWNUMBER,".";
+    CALL DO_EXIT;
+    Label_87:
+    IRSCAN 8, $8e;
+    DRSCAN 2, VERIFYEOL[],COMPARE $0,$3,PASS;
+    IF ( ! (PASS==0) ) THEN GOTO Label_88;
+    STATUS = 11;
+    PRINT "Verify 1 failed at row ",ROWNUMBER,".";
+    CALL DO_EXIT;
+    Label_88:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DO_PROGRAM USES GV,LOAD_ROW_DATA,EXE_PROGRAM;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $87;
+    DRSCAN 2, $2;
+    WAIT IDLE, 3 CYCLES;
+    PRINT "Programming FPGA Array";
+    DATAINDEX = 0;
+    ROWNUMBER = (NUMBEROFMAPROWS-1);
+    INTEGER IREPEAT_0;
+    FOR IREPEAT_0 = NUMBEROFMAPROWS - 1 TO 0 STEP -1;
+        CALL LOAD_ROW_DATA;
+        CALL EXE_PROGRAM;
+        IRSTOP IRPAUSE;
+        DRSTOP DRPAUSE;
+        IRSCAN 8, $87;
+        DRSCAN 2, $3;
+        WAIT IDLE, 3 CYCLES;
+        EXPORT "PERCENT_DONE", ((100*((NUMBEROFMAPROWS-ROWNUMBER)+1))/NUMBEROFMAPROWS);
+        ROWNUMBER = (ROWNUMBER-1);
+    NEXT IREPEAT_0;
+ENDPROC;
+
+PROCEDURE DO_VERIFY USES GV,LOAD_ROW_DATA,EXE_VERIFY;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $87;
+    DRSCAN 2, $2;
+    WAIT IDLE, 3 CYCLES;
+    PRINT "Verifying FPGA Array";
+    DATAINDEX = 0;
+    ROWNUMBER = (NUMBEROFMAPROWS-1);
+    INTEGER IREPEAT_1;
+    FOR IREPEAT_1 = NUMBEROFMAPROWS - 1 TO 0 STEP -1;
+        CALL LOAD_ROW_DATA;
+        CALL EXE_VERIFY;
+        IRSTOP IRPAUSE;
+        DRSTOP DRPAUSE;
+        IRSCAN 8, $87;
+        DRSCAN 2, $3;
+        WAIT IDLE, 3 CYCLES;
+        EXPORT "PERCENT_DONE", ((100*((NUMBEROFMAPROWS-ROWNUMBER)+1))/NUMBEROFMAPROWS);
+        ROWNUMBER = (ROWNUMBER-1);
+    NEXT IREPEAT_1;
+    PRINT "        Verifying FPGA Array -- pass";
+ENDPROC;
+
+PROCEDURE DO_VERIFY_BOL USES GV,DO_VERIFY;
+    VERIFYEOL[0] = 0;
+    CALL DO_VERIFY;
+ENDPROC;
+
+PROCEDURE DO_VERIFY_EOL USES GV,DO_VERIFY;
+    VERIFYEOL[0] = 1;
+    CALL DO_VERIFY;
+ENDPROC;
+
+PROCEDURE DO_PROGRAM_RLOCK USES GV,DO_EXIT,POLL_PROGRAM;
+    DATAINDEX = 0;
+    INTEGER IREPEAT_2;
+    FOR IREPEAT_2 = NUMBEROFSDTILES - 1 TO 0 STEP -1;
+        FOR I = 1 TO 8;
+            IRSTOP IRPAUSE;
+            DRSTOP DRPAUSE;
+            IRSCAN 8, $89;
+            DRSCAN 26, RLOCK[(DATAINDEX+25)..DATAINDEX];
+            WAIT IDLE, 3 CYCLES;
+            DATAINDEX = (DATAINDEX+26);
+        NEXT I;
+    NEXT IREPEAT_2;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $8c;
+    WAIT IDLE, 3 CYCLES;
+    CALL POLL_PROGRAM;
+    IF ( ! (PASS==0) ) THEN GOTO Label_89;
+    STATUS = 10;
+    PRINT "Failed to program Rlock.";
+    CALL DO_EXIT;
+    Label_89:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DO_READ_IDCODE USES READ_IDCODE_ONLY;
+    WAIT RESET, 5 CYCLES;
+    CALL READ_IDCODE_ONLY;
+    EXIT 0;
+ENDPROC;
+
+
+CRC C470;
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP1Mouse.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP1Mouse.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/EP1Mouse.v	(revision 264)
@@ -0,0 +1,295 @@
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// EP1Mouse.v                                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Implements EP1 as a IN endpoint
+//// simulating a mouse (a broken one) by 
+//// responding to IN requests with a constant (x,y) <= (1,1)
+//// which causes the mouse pointer to move from 
+//// top left to bottom right of the screen
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostSlaveReg_define.v"
+
+module EP1Mouse (clk, initComplete, rst, wb_ack, wb_addr, wb_data_i, wb_data_o, wb_stb, wb_we, wbBusGnt, wbBusReq);
+input   clk;
+input   initComplete;
+input   rst;
+input   wb_ack;
+input   [7:0]wb_data_i;
+input   wbBusGnt;
+output  [7:0]wb_addr;
+output  [7:0]wb_data_o;
+output  wb_stb;
+output  wb_we;
+output  wbBusReq;
+
+wire    clk;
+wire    initComplete;
+wire    rst;
+wire    wb_ack;
+reg     [7:0]wb_addr, next_wb_addr;
+wire    [7:0]wb_data_i;
+reg     [7:0]wb_data_o, next_wb_data_o;
+reg     wb_stb, next_wb_stb;
+reg     wb_we, next_wb_we;
+wire    wbBusGnt;
+reg     wbBusReq, next_wbBusReq;
+
+// diagram signals declarations
+reg  [7:0]cnt, next_cnt;
+reg dataSeq, next_dataSeq;
+reg localRst, next_localRst;
+reg transDone, next_transDone;
+
+// BINARY ENCODED state machine: EP1St
+// State codes definitions:
+`define DO_TRANS_WT_GNT 4'b0000
+`define DO_TRANS_TX_EMPTY 4'b0001
+`define DO_TRANS_WR_TX_FIFO1 4'b0010
+`define DO_TRANS_TRANS_GO 4'b0011
+`define DO_TRANS_WT_TRANS_DONE_WT_GNT 4'b0100
+`define DO_TRANS_WT_TRANS_DONE_GET_RDY_STS 4'b0101
+`define DO_TRANS_WT_TRANS_DONE_WT_UNGNT 4'b0110
+`define DO_TRANS_WT_TRANS_DONE_CHK_DONE 4'b0111
+`define START 4'b1000
+`define DO_TRANS_WR_TX_FIFO2 4'b1001
+`define DO_TRANS_WR_TX_FIFO3 4'b1010
+`define DO_TRANS_WT_TRANS_DONE_DEL 4'b1011
+
+reg [3:0]CurrState_EP1St, NextState_EP1St;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+// diagram ACTION
+
+
+// Machine: EP1St
+
+// NextState logic (combinatorial)
+always @ (wbBusGnt or wb_ack or wb_data_i or transDone or initComplete or cnt or wbBusReq or wb_addr or wb_data_o or wb_stb or wb_we or dataSeq or CurrState_EP1St)
+begin
+  NextState_EP1St <= CurrState_EP1St;
+  // Set default values for outputs and signals
+  next_wbBusReq <= wbBusReq;
+  next_wb_addr <= wb_addr;
+  next_wb_data_o <= wb_data_o;
+  next_wb_stb <= wb_stb;
+  next_wb_we <= wb_we;
+  next_dataSeq <= dataSeq;
+  next_transDone <= transDone;
+  next_cnt <= cnt;
+  case (CurrState_EP1St)  // synopsys parallel_case full_case
+    `START:
+    begin
+      next_wbBusReq <= 1'b0;
+      next_wb_addr <= 8'h00;
+      next_wb_data_o <= 8'h00;
+      next_wb_stb <= 1'b0;
+      next_wb_we <= 1'b0;
+      next_cnt <= 8'h00;
+      next_dataSeq <= 1'b0;
+      next_transDone <= 1'b0;
+      if (initComplete == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_GNT;
+      end
+    end
+    `DO_TRANS_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_TX_EMPTY;
+      end
+    end
+    `DO_TRANS_TX_EMPTY:
+    begin
+      next_wb_addr <= `RA_EP1_TX_FIFO_CONTROL_REG;
+      next_wb_data_o <= 8'h01;
+      //force tx fifo empty
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO1;
+        next_wb_stb <= 1'b0;
+        next_wb_addr <= `RA_EP1_TX_FIFO_DATA_REG;
+        next_wb_we <= 1'b1;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO1:
+    begin
+      next_wb_data_o <= 8'h00;
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO2;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_TRANS_GO:
+    begin
+      next_wb_addr <= `RA_EP1_CONTROL_REG;
+      if (dataSeq == 1'b1)
+      next_wb_data_o <= 8'h07;
+      else
+      next_wb_data_o <= 8'h03;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+        next_wb_stb <= 1'b0;
+        if (dataSeq == 1'b1)
+        next_dataSeq <= 1'b0;
+        else
+        next_dataSeq <= 1'b1;
+        next_transDone <= 1'b0;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO2:
+    begin
+      next_wb_data_o <= 8'h01;
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WR_TX_FIFO3;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_WR_TX_FIFO3:
+    begin
+      next_wb_data_o <= 8'h01;
+      next_wb_stb <= 1'b1;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_TRANS_GO;
+        next_wb_stb <= 1'b0;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_GNT:
+    begin
+      next_wbBusReq <= 1'b1;
+      if (wbBusGnt == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_GET_RDY_STS:
+    begin
+      next_wb_addr <= `RA_EP1_CONTROL_REG;
+      next_wb_stb <= 1'b1;
+      next_wb_we <= 1'b0;
+      if (wb_ack == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_UNGNT;
+        next_wb_stb <= 1'b0;
+        next_transDone <= ~wb_data_i[`ENDPOINT_READY_BIT];
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_WT_UNGNT:
+    begin
+      next_wbBusReq <= 1'b0;
+      if (wbBusGnt == 1'b0)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_CHK_DONE;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_CHK_DONE:
+    begin
+      if (transDone == 1'b1)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_GNT;
+      end
+      else
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_DEL;
+        next_cnt <= 8'h00;
+      end
+    end
+    `DO_TRANS_WT_TRANS_DONE_DEL:
+    begin
+      next_cnt <= cnt + 1'b1;
+      if (cnt == `ONE_USEC_DEL)
+      begin
+        NextState_EP1St <= `DO_TRANS_WT_TRANS_DONE_WT_GNT;
+      end
+    end
+  endcase
+end
+
+// Current State Logic (sequential)
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+    CurrState_EP1St <= `START;
+  else
+    CurrState_EP1St <= NextState_EP1St;
+end
+
+// Registered outputs logic
+always @ (posedge clk)
+begin
+  if (rst == 1'b1)
+  begin
+    wbBusReq <= 1'b0;
+    wb_addr <= 8'h00;
+    wb_data_o <= 8'h00;
+    wb_stb <= 1'b0;
+    wb_we <= 1'b0;
+    dataSeq <= 1'b0;
+    transDone <= 1'b0;
+    cnt <= 8'h00;
+  end
+  else 
+  begin
+    wbBusReq <= next_wbBusReq;
+    wb_addr <= next_wb_addr;
+    wb_data_o <= next_wb_data_o;
+    wb_stb <= next_wb_stb;
+    wb_we <= next_wb_we;
+    dataSeq <= next_dataSeq;
+    transDone <= next_transDone;
+    cnt <= next_cnt;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifo.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifo.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/TxFifo.v	(revision 264)
@@ -0,0 +1,132 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// TxFifo.v                                                     ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+////  parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536
+////  fifo write access via bus interface, fifo read access is direct
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module TxFifo(
+  busClk,
+  usbClk,
+  rstSyncToBusClk, 
+  rstSyncToUsbClk, 
+  fifoREn, 
+  fifoEmpty,
+  busAddress, 
+  busWriteEn, 
+  busStrobe_i,
+  busFifoSelect,
+  busDataIn,
+  busDataOut,
+  fifoDataOut ); 
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input busClk; 
+input usbClk; 
+input rstSyncToBusClk; 
+input rstSyncToUsbClk; 
+input fifoREn; 
+output fifoEmpty;
+input [2:0] busAddress; 
+input busWriteEn; 
+input busStrobe_i;
+input busFifoSelect;
+input [7:0] busDataIn; 
+output [7:0] busDataOut; 
+output [7:0] fifoDataOut;
+
+wire busClk; 
+wire usbClk; 
+wire rstSyncToBusClk; 
+wire rstSyncToUsbClk; 
+wire fifoREn; 
+wire fifoEmpty;
+wire [2:0] busAddress; 
+wire busWriteEn; 
+wire busStrobe_i;
+wire busFifoSelect;
+wire [7:0] busDataIn; 
+wire [7:0] busDataOut; 
+wire [7:0] fifoDataOut;
+
+//internal wires and regs
+wire fifoWEn;
+wire forceEmptySyncToUsbClk;
+wire forceEmptySyncToBusClk;
+wire [15:0] numElementsInFifo;
+wire fifoFull;
+
+fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
+  .wrClk(busClk), 
+  .rdClk(usbClk), 
+  .rstSyncToWrClk(rstSyncToBusClk), 
+  .rstSyncToRdClk(rstSyncToUsbClk), 
+  .dataIn(busDataIn), 
+  .dataOut(fifoDataOut), 
+  .fifoWEn(fifoWEn), 
+  .fifoREn(fifoREn), 
+  .fifoFull(fifoFull), 
+  .fifoEmpty(fifoEmpty), 
+  .forceEmptySyncToWrClk(forceEmptySyncToBusClk), 
+  .forceEmptySyncToRdClk(forceEmptySyncToUsbClk), 
+  .numElementsInFifo(numElementsInFifo) );
+  
+TxfifoBI u_TxfifoBI(
+  .address(busAddress), 
+  .writeEn(busWriteEn), 
+  .strobe_i(busStrobe_i),
+  .busClk(busClk), 
+  .usbClk(usbClk), 
+  .rstSyncToBusClk(rstSyncToBusClk), 
+  .fifoSelect(busFifoSelect),
+  .busDataIn(busDataIn), 
+  .busDataOut(busDataOut), 
+  .fifoWEn(fifoWEn),
+  .forceEmptySyncToBusClk(forceEmptySyncToBusClk),
+  .forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
+  .numElementsInFifo(numElementsInFifo)
+  );
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/dpMem_dc.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/dpMem_dc.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/dpMem_dc.v	(revision 264)
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// dpMem_dc.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Synchronous dual port memory with dual clocks
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module dpMem_dc(  addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut);
+  //FIFO_DEPTH = ADDR_WIDTH^2
+  parameter FIFO_WIDTH = 8;
+  parameter FIFO_DEPTH = 64; 
+  parameter ADDR_WIDTH = 6;   
+  
+input wrClk;
+input rdClk;
+input [FIFO_WIDTH-1:0] dataIn;
+output [FIFO_WIDTH-1:0] dataOut;
+input writeEn;
+input readEn;
+input [ADDR_WIDTH-1:0] addrIn;
+input [ADDR_WIDTH-1:0] addrOut;
+
+wire wrClk;
+wire rdClk;
+wire [FIFO_WIDTH-1:0] dataIn;
+reg [FIFO_WIDTH-1:0] dataOut;
+wire writeEn;
+wire readEn;
+wire [ADDR_WIDTH-1:0] addrIn;
+wire [ADDR_WIDTH-1:0] addrOut;
+
+reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1];
+
+// synchronous read. Introduces one clock cycle delay
+always @(posedge rdClk) begin
+  dataOut <= buffer[addrOut];
+end
+
+// synchronous write
+always @(posedge wrClk) begin
+  if (writeEn == 1'b1)
+    buffer[addrIn] <= dataIn;
+end                  
+
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/hostSlaveMuxBI.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/hostSlaveMuxBI.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/hostSlaveMuxBI.v	(revision 264)
@@ -0,0 +1,124 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// hostSlaveMuxBI.v                                             ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbHostSlave_h.v"
+
+module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
+  hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
+
+input [7:0] dataIn;
+input address;
+input writeEn;
+input strobe_i;
+input busClk;
+input usbClk;
+output [7:0] dataOut;
+input hostSlaveMuxSel;
+output hostMode;
+input rstFromWire;
+output rstSyncToBusClkOut;
+output rstSyncToUsbClkOut;
+
+wire [7:0] dataIn;
+wire address;
+wire writeEn;
+wire strobe_i;
+wire busClk;
+wire usbClk;
+reg [7:0] dataOut;
+wire hostSlaveMuxSel;
+reg hostMode;
+wire rstFromWire;
+reg rstSyncToBusClkOut;
+reg rstSyncToUsbClkOut;
+
+//internal wire and regs
+reg [5:0] rstShift;
+reg rstFromBus;
+reg rstSyncToUsbClkFirst;
+
+//sync write demux
+always @(posedge busClk)
+begin
+  if (rstSyncToBusClkOut == 1'b1)
+    hostMode <= 1'b0;
+  else begin
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
+      hostMode <= dataIn[0];
+    end
+    if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
+      rstFromBus <= 1'b1;
+    else
+      rstFromBus <= 1'b0;
+end
+
+// async read mux
+always @(address or hostMode)
+begin
+  case (address)
+    `HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
+    `HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
+  endcase
+end
+
+// reset control
+//generate 'rstSyncToBusClk'
+//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
+always @(posedge busClk) begin
+  if (rstFromWire == 1'b1 || rstFromBus == 1'b1) 
+    rstShift <= 6'b111111;
+  else
+    rstShift <= {1'b0, rstShift[5:1]};
+end
+
+always @(rstShift)
+  rstSyncToBusClkOut <= rstShift[0];
+
+// double sync across clock domains to generate 'forceEmptySyncToWrClk'
+always @(posedge usbClk) begin
+    rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
+    rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
+end
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxByte.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxByte.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/processRxByte.v	(revision 264)
@@ -0,0 +1,493 @@
+
+// File        : ../RTL/serialInterfaceEngine/processRxByte.v
+// Generated   : 11/10/06 05:37:22
+// From        : ../RTL/serialInterfaceEngine/processRxByte.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// processRxByte
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module processRxByte (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, RxByteIn, RxCtrlIn, RxCtrlOut, RxDataOutWEn, RxDataOut, clk, processRxByteRdy, processRxDataInWEn, rst, rstCRC);
+input   [15:0] CRC16Result;
+input   CRC16UpdateRdy;
+input   [4:0] CRC5Result;
+input   CRC5UpdateRdy;
+input   [7:0] RxByteIn;
+input   [7:0] RxCtrlIn;
+input   clk;
+input   processRxDataInWEn;
+input   rst;
+output  CRC16En;
+output  CRC5En;
+output  CRC5_8Bit;
+output  [7:0] CRCData;
+output  [7:0] RxCtrlOut;
+output  RxDataOutWEn;
+output  [7:0] RxDataOut;
+output  processRxByteRdy;
+output  rstCRC;
+
+reg     CRC16En, next_CRC16En;
+wire    [15:0] CRC16Result;
+wire    CRC16UpdateRdy;
+reg     CRC5En, next_CRC5En;
+wire    [4:0] CRC5Result;
+wire    CRC5UpdateRdy;
+reg     CRC5_8Bit, next_CRC5_8Bit;
+reg     [7:0] CRCData, next_CRCData;
+wire    [7:0] RxByteIn;
+wire    [7:0] RxCtrlIn;
+reg     [7:0] RxCtrlOut, next_RxCtrlOut;
+reg     RxDataOutWEn, next_RxDataOutWEn;
+reg     [7:0] RxDataOut, next_RxDataOut;
+wire    clk;
+reg     processRxByteRdy, next_processRxByteRdy;
+wire    processRxDataInWEn;
+wire    rst;
+reg     rstCRC, next_rstCRC;
+
+// diagram signals declarations
+reg  ACKRxed, next_ACKRxed;
+reg  CRCError, next_CRCError;
+reg  NAKRxed, next_NAKRxed;
+reg  [2:0]RXByteStMachCurrState, next_RXByteStMachCurrState;
+reg  [9:0]RXDataByteCnt, next_RXDataByteCnt;
+reg  [7:0]RxByte, next_RxByte;
+reg  [7:0]RxCtrl, next_RxCtrl;
+reg  RxOverflow, next_RxOverflow;
+reg  [7:0]RxStatus;
+reg  RxTimeOut, next_RxTimeOut;
+reg  Signal1, next_Signal1;
+reg  bitStuffError, next_bitStuffError;
+reg  dataSequence, next_dataSequence;
+reg  stallRxed, next_stallRxed;
+
+// BINARY ENCODED state machine: prRxByte
+// State codes definitions:
+`define CHK_ST 4'b0000
+`define START_PRBY 4'b0001
+`define WAIT_BYTE 4'b0010
+`define IDLE_CHK_START 4'b0011
+`define CHK_SYNC_DO 4'b0100
+`define CHK_PID_DO_CHK 4'b0101
+`define CHK_PID_FIRST_BYTE_PROC 4'b0110
+`define HSHAKE_FIN 4'b0111
+`define HSHAKE_CHK 4'b1000
+`define TOKEN_CHK_STRM 4'b1001
+`define TOKEN_FIN 4'b1010
+`define DATA_FIN 4'b1011
+`define DATA_CHK_STRM 4'b1100
+`define TOKEN_WAIT_CRC 4'b1101
+`define DATA_WAIT_CRC 4'b1110
+
+reg [3:0] CurrState_prRxByte;
+reg [3:0] NextState_prRxByte;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+always @
+(next_CRCError or next_bitStuffError or
+  next_RxOverflow or next_NAKRxed or
+  next_stallRxed or next_ACKRxed or
+  next_dataSequence)
+begin
+    RxStatus <=
+    {1'b0, next_dataSequence,
+    next_ACKRxed,
+    next_stallRxed, next_NAKRxed,
+    next_RxOverflow,
+    next_bitStuffError, next_CRCError };
+end
+
+//--------------------------------------------------------------------
+// Machine: prRxByte
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RxByteIn or RxCtrlIn or RxCtrl or RxStatus or RxByte or RXDataByteCnt or CRC16Result or CRC5Result or RXByteStMachCurrState or processRxDataInWEn or CRC16UpdateRdy or CRC5UpdateRdy or CRCError or bitStuffError or RxOverflow or RxTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or RxDataOut or RxCtrlOut or RxDataOutWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or processRxByteRdy or CurrState_prRxByte)
+begin : prRxByte_NextState
+  NextState_prRxByte <= CurrState_prRxByte;
+  // Set default values for outputs and signals
+  next_RxByte <= RxByte;
+  next_RxCtrl <= RxCtrl;
+  next_RXByteStMachCurrState <= RXByteStMachCurrState;
+  next_CRCError <= CRCError;
+  next_bitStuffError <= bitStuffError;
+  next_RxOverflow <= RxOverflow;
+  next_RxTimeOut <= RxTimeOut;
+  next_NAKRxed <= NAKRxed;
+  next_stallRxed <= stallRxed;
+  next_ACKRxed <= ACKRxed;
+  next_dataSequence <= dataSequence;
+  next_RxDataOut <= RxDataOut;
+  next_RxCtrlOut <= RxCtrlOut;
+  next_RxDataOutWEn <= RxDataOutWEn;
+  next_rstCRC <= rstCRC;
+  next_CRCData <= CRCData;
+  next_CRC5En <= CRC5En;
+  next_CRC5_8Bit <= CRC5_8Bit;
+  next_CRC16En <= CRC16En;
+  next_RXDataByteCnt <= RXDataByteCnt;
+  next_processRxByteRdy <= processRxByteRdy;
+  case (CurrState_prRxByte)
+    `CHK_ST:
+      if (RXByteStMachCurrState == `HS_BYTE_ST)	
+        NextState_prRxByte <= `HSHAKE_CHK;
+      else if (RXByteStMachCurrState == `TOKEN_BYTE_ST)	
+        NextState_prRxByte <= `TOKEN_WAIT_CRC;
+      else if (RXByteStMachCurrState == `DATA_BYTE_ST)	
+        NextState_prRxByte <= `DATA_WAIT_CRC;
+      else if (RXByteStMachCurrState == `IDLE_BYTE_ST)	
+        NextState_prRxByte <= `IDLE_CHK_START;
+      else if (RXByteStMachCurrState == `CHECK_SYNC_ST)	
+        NextState_prRxByte <= `CHK_SYNC_DO;
+      else if (RXByteStMachCurrState == `CHECK_PID_ST)	
+        NextState_prRxByte <= `CHK_PID_DO_CHK;
+    `START_PRBY:
+    begin
+      next_RxByte <= 8'h00;
+      next_RxCtrl <= 8'h00;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      next_CRCError <= 1'b0;
+      next_bitStuffError <= 1'b0;
+      next_RxOverflow <= 1'b0;
+      next_RxTimeOut <= 1'b0;
+      next_NAKRxed <= 1'b0;
+      next_stallRxed <= 1'b0;
+      next_ACKRxed <= 1'b0;
+      next_dataSequence <= 1'b0;
+      next_RxDataOut <= 8'h00;
+      next_RxCtrlOut <= 8'h00;
+      next_RxDataOutWEn <= 1'b0;
+      next_rstCRC <= 1'b0;
+      next_CRCData <= 8'h00;
+      next_CRC5En <= 1'b0;
+      next_CRC5_8Bit <= 1'b0;
+      next_CRC16En <= 1'b0;
+      next_RXDataByteCnt <= 10'h00;
+      next_processRxByteRdy <= 1'b1;
+      NextState_prRxByte <= `WAIT_BYTE;
+    end
+    `WAIT_BYTE:
+      if (processRxDataInWEn == 1'b1)	
+      begin
+        NextState_prRxByte <= `CHK_ST;
+        next_RxByte <= RxByteIn;
+        next_RxCtrl <= RxCtrlIn;
+        next_processRxByteRdy <= 1'b0;
+      end
+    `HSHAKE_FIN:
+    begin
+      next_RxDataOutWEn <= 1'b0;
+      next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `HSHAKE_CHK:
+    begin
+      NextState_prRxByte <= `HSHAKE_FIN;
+      if (RxCtrl != `DATA_STOP) //If more than PID rxed, then report error
+        next_RxOverflow <= 1'b1;
+      next_RxDataOut <= RxStatus;
+      next_RxCtrlOut <= `RX_PACKET_STOP;
+      next_RxDataOutWEn <= 1'b1;
+    end
+    `CHK_PID_DO_CHK:
+      if ((RxByte[7:4] ^ RxByte[3:0] ) != 4'hf)	
+      begin
+        NextState_prRxByte <= `WAIT_BYTE;
+        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+        next_processRxByteRdy <= 1'b1;
+      end
+      else
+      begin
+        NextState_prRxByte <= `CHK_PID_FIRST_BYTE_PROC;
+        next_CRCError <= 1'b0;
+        next_bitStuffError <= 1'b0;
+        next_RxOverflow <= 1'b0;
+        next_NAKRxed <= 1'b0;
+        next_stallRxed <= 1'b0;
+        next_ACKRxed <= 1'b0;
+        next_dataSequence <= 1'b0;
+        next_RxTimeOut <= 1'b0;
+        next_RXDataByteCnt <= 10'h000;
+        next_RxDataOut <= RxByte;
+        next_RxCtrlOut <= `RX_PACKET_START;
+        next_RxDataOutWEn <= 1'b1;
+        next_rstCRC <= 1'b1;
+      end
+    `CHK_PID_FIRST_BYTE_PROC:
+    begin
+      next_rstCRC <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      case (RxByte[1:0] )
+          `SPECIAL:                              //Special PID.
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          `TOKEN:                                //Token PID
+          begin
+          next_RXByteStMachCurrState <= `TOKEN_BYTE_ST;
+          next_RXDataByteCnt <= 0;
+          end
+          `HANDSHAKE:                            //Handshake PID
+          begin
+              case (RxByte[3:2] )
+                  2'b00:
+              next_ACKRxed <= 1'b1;
+                  2'b10:
+              next_NAKRxed <= 1'b1;
+                  2'b11:
+              next_stallRxed <= 1'b1;
+                  default:
+                  begin
+                      $display ("Invalid Handshake PID detected in ProcessRXByte\n");
+                  end
+              endcase
+          next_RXByteStMachCurrState <= `HS_BYTE_ST;
+          end
+          `DATA:                                  //Data PID
+          begin
+              case (RxByte[3:2] )
+                  2'b00:
+              next_dataSequence <= 1'b0;
+                  2'b10:
+              next_dataSequence <= 1'b1;
+                  default:
+                      $display ("Invalid DATA PID detected in ProcessRXByte\n");
+              endcase
+          next_RXByteStMachCurrState <= `DATA_BYTE_ST;
+          next_RXDataByteCnt <= 0;
+          end
+      endcase
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_FIN:
+    begin
+      next_CRC16En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `DATA_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+          `DATA_STOP:
+          begin
+              if (CRC16Result != 16'hb001)
+            next_CRCError <= 1'b1;
+          next_RxDataOut <= RxStatus;
+          next_RxCtrlOut <= `RX_PACKET_STOP;
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+          `DATA_BIT_STUFF_ERROR:
+          begin
+          next_bitStuffError <= 1'b1;
+          next_RxDataOut <= RxStatus;
+          next_RxCtrlOut <= `RX_PACKET_STOP;
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+          `DATA_STREAM:
+          begin
+          next_RxDataOut <= RxByte;
+          next_RxCtrlOut <= `RX_PACKET_STREAM;
+          next_CRCData <= RxByte;
+          next_CRC16En <= 1'b1;
+          end
+          default:
+          begin
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `DATA_FIN;
+    end
+    `DATA_WAIT_CRC:
+      if (CRC16UpdateRdy == 1'b1)	
+        NextState_prRxByte <= `DATA_CHK_STRM;
+    `TOKEN_CHK_STRM:
+    begin
+      next_RXDataByteCnt <= RXDataByteCnt + 1'b1;
+      case (RxCtrl)
+          `DATA_STOP:
+          begin
+              if (CRC5Result != 5'h6)
+            next_CRCError <= 1'b1;
+          next_RxDataOut <= RxStatus;
+          next_RxCtrlOut <= `RX_PACKET_STOP;
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+          `DATA_BIT_STUFF_ERROR:
+          begin
+          next_bitStuffError <= 1'b1;
+          next_RxDataOut <= RxStatus;
+          next_RxCtrlOut <= `RX_PACKET_STOP;
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+          `DATA_STREAM:
+          begin
+              if (RXDataByteCnt > 10'h2)
+              begin
+            next_RxOverflow <= 1'b1;
+            next_RxDataOut <= RxStatus;
+            next_RxCtrlOut <= `RX_PACKET_STOP;
+            next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+              end
+              else
+              begin
+            next_RxDataOut <= RxByte;
+            next_RxCtrlOut <= `RX_PACKET_STREAM;
+            next_CRCData <= RxByte;
+            next_CRC5_8Bit <= 1'b1;
+            next_CRC5En <= 1'b1;
+              end
+          end
+          default:
+          begin
+          next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+          end
+      endcase
+      next_RxDataOutWEn <= 1'b1;
+      NextState_prRxByte <= `TOKEN_FIN;
+    end
+    `TOKEN_FIN:
+    begin
+      next_CRC5En <= 1'b0;
+      next_RxDataOutWEn <= 1'b0;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `TOKEN_WAIT_CRC:
+      if (CRC5UpdateRdy == 1'b1)	
+        NextState_prRxByte <= `TOKEN_CHK_STRM;
+    `CHK_SYNC_DO:
+    begin
+      if (RxByte == `SYNC_BYTE)
+        next_RXByteStMachCurrState <= `CHECK_PID_ST;
+      else
+        next_RXByteStMachCurrState <= `IDLE_BYTE_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+    `IDLE_CHK_START:
+    begin
+      if (RxCtrl == `DATA_START)
+        next_RXByteStMachCurrState <= `CHECK_SYNC_ST;
+      NextState_prRxByte <= `WAIT_BYTE;
+      next_processRxByteRdy <= 1'b1;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : prRxByte_CurrentState
+  if (rst)	
+    CurrState_prRxByte <= `START_PRBY;
+  else
+    CurrState_prRxByte <= NextState_prRxByte;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : prRxByte_RegOutput
+  if (rst)	
+  begin
+    RxByte <= 8'h00;
+    RxCtrl <= 8'h00;
+    RXByteStMachCurrState <= `IDLE_BYTE_ST;
+    CRCError <= 1'b0;
+    bitStuffError <= 1'b0;
+    RxOverflow <= 1'b0;
+    RxTimeOut <= 1'b0;
+    NAKRxed <= 1'b0;
+    stallRxed <= 1'b0;
+    ACKRxed <= 1'b0;
+    dataSequence <= 1'b0;
+    RXDataByteCnt <= 10'h00;
+    RxDataOut <= 8'h00;
+    RxCtrlOut <= 8'h00;
+    RxDataOutWEn <= 1'b0;
+    rstCRC <= 1'b0;
+    CRCData <= 8'h00;
+    CRC5En <= 1'b0;
+    CRC5_8Bit <= 1'b0;
+    CRC16En <= 1'b0;
+    processRxByteRdy <= 1'b1;
+  end
+  else 
+  begin
+    RxByte <= next_RxByte;
+    RxCtrl <= next_RxCtrl;
+    RXByteStMachCurrState <= next_RXByteStMachCurrState;
+    CRCError <= next_CRCError;
+    bitStuffError <= next_bitStuffError;
+    RxOverflow <= next_RxOverflow;
+    RxTimeOut <= next_RxTimeOut;
+    NAKRxed <= next_NAKRxed;
+    stallRxed <= next_stallRxed;
+    ACKRxed <= next_ACKRxed;
+    dataSequence <= next_dataSequence;
+    RXDataByteCnt <= next_RXDataByteCnt;
+    RxDataOut <= next_RxDataOut;
+    RxCtrlOut <= next_RxCtrlOut;
+    RxDataOutWEn <= next_RxDataOutWEn;
+    rstCRC <= next_rstCRC;
+    CRCData <= next_CRCData;
+    CRC5En <= next_CRC5En;
+    CRC5_8Bit <= next_CRC5_8Bit;
+    CRC16En <= next_CRC16En;
+    processRxByteRdy <= next_processRxByteRdy;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/siereceiver.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/siereceiver.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/siereceiver.v	(revision 264)
@@ -0,0 +1,283 @@
+
+// File        : ../RTL/serialInterfaceEngine/siereceiver.v
+// Generated   : 11/10/06 05:37:23
+// From        : ../RTL/serialInterfaceEngine/siereceiver.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// SIEReceiver
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+
+
+module SIEReceiver (RxWireDataIn, RxWireDataWEn, clk, connectState, rst);
+input   [1:0] RxWireDataIn;
+input   RxWireDataWEn;
+input   clk;
+input   rst;
+output  [1:0] connectState;
+
+wire    [1:0] RxWireDataIn;
+wire    RxWireDataWEn;
+wire    clk;
+reg     [1:0] connectState, next_connectState;
+wire    rst;
+
+// diagram signals declarations
+reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
+reg  [7:0]RXWaitCount, next_RXWaitCount;
+reg  [1:0]RxBits, next_RxBits;
+
+// BINARY ENCODED state machine: rcvr
+// State codes definitions:
+`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
+`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
+`define LS_CONN_CHK_RX_BITS 4'b0010
+`define DISCNCT_CHK_RXBITS 4'b0011
+`define WAIT_BIT 4'b0100
+`define START_SRX 4'b0101
+`define FS_CONN_CHK_RX_BITS1 4'b0110
+`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
+`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
+
+reg [3:0] CurrState_rcvr;
+reg [3:0] NextState_rcvr;
+
+
+//--------------------------------------------------------------------
+// Machine: rcvr
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or connectState or CurrState_rcvr)
+begin : rcvr_NextState
+  NextState_rcvr <= CurrState_rcvr;
+  // Set default values for outputs and signals
+  next_RxBits <= RxBits;
+  next_RXStMachCurrState <= RXStMachCurrState;
+  next_RXWaitCount <= RXWaitCount;
+  next_connectState <= connectState;
+  case (CurrState_rcvr)
+    `WAIT_BIT:
+      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))	
+      begin
+        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))	
+      begin
+        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))	
+      begin
+        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))	
+      begin
+        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))	
+      begin
+        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))	
+      begin
+        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
+        next_RxBits <= RxWireDataIn;
+      end
+      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))	
+      begin
+        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
+        next_RxBits <= RxWireDataIn;
+      end
+    `START_SRX:
+    begin
+      next_RXStMachCurrState <= `DISCONNECT_ST;
+      next_RXWaitCount <= 8'h00;
+      next_connectState <= `DISCONNECT;
+      next_RxBits <= 2'b00;
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `DISCNCT_CHK_RXBITS:
+      if (RxBits == `ZERO_ONE)	
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else if (RxBits == `ONE_ZERO)	
+      begin
+        NextState_rcvr <= `WAIT_BIT;
+        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
+        next_RXWaitCount <= 8'h00;
+      end
+      else
+        NextState_rcvr <= `WAIT_BIT;
+    `WAIT_FS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ONE_ZERO)
+      begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+          if (RXWaitCount == `CONNECT_WAIT_TIME)
+          begin
+          next_connectState <= `FULL_SPEED_CONNECT;
+          next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+          end
+      end
+      else
+      begin
+        next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `WAIT_LS_CONN_CHK_RX_BITS:
+    begin
+      if (RxBits == `ZERO_ONE)
+      begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+          if (RXWaitCount == `CONNECT_WAIT_TIME)
+          begin
+          next_connectState <= `LOW_SPEED_CONNECT;
+          next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+          end
+      end
+      else
+      begin
+        next_RXStMachCurrState <= `DISCONNECT_ST;
+      end
+      NextState_rcvr <= `WAIT_BIT;
+    end
+    `LS_CONN_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+        next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
+        next_RXWaitCount <= 0;
+      end
+    end
+    `FS_CONN_CHK_RX_BITS1:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+        next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
+        next_RXWaitCount <= 0;
+      end
+    end
+    `WAIT_LS_DIS_CHK_RX_BITS:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+          if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+          begin
+          next_RXStMachCurrState <= `DISCONNECT_ST;
+          next_connectState <= `DISCONNECT;
+          end
+      end
+      else
+      begin
+        next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
+      end
+    end
+    `WAIT_FS_DIS_CHK_RX_BITS2:
+    begin
+      NextState_rcvr <= `WAIT_BIT;
+      if (RxBits == `SE0)
+      begin
+        next_RXWaitCount <= RXWaitCount + 1'b1;
+          if (RXWaitCount == `DISCONNECT_WAIT_TIME)
+          begin
+          next_RXStMachCurrState <= `DISCONNECT_ST;
+          next_connectState <= `DISCONNECT;
+          end
+      end
+      else
+      begin
+        next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
+      end
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : rcvr_CurrentState
+  if (rst)	
+    CurrState_rcvr <= `START_SRX;
+  else
+    CurrState_rcvr <= NextState_rcvr;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : rcvr_RegOutput
+  if (rst)	
+  begin
+    RXStMachCurrState <= `DISCONNECT_ST;
+    RXWaitCount <= 8'h00;
+    RxBits <= 2'b00;
+    connectState <= `DISCONNECT;
+  end
+  else 
+  begin
+    RXStMachCurrState <= next_RXStMachCurrState;
+    RXWaitCount <= next_RXWaitCount;
+    RxBits <= next_RxBits;
+    connectState <= next_connectState;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveSendpacket.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveSendpacket.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/slaveSendpacket.v	(revision 264)
@@ -0,0 +1,252 @@
+
+// File        : ../RTL/slaveController/slaveSendpacket.v
+// Generated   : 11/10/06 05:37:26
+// From        : ../RTL/slaveController/slaveSendpacket.asf
+// By          : FSM2VHDL ver. 5.0.0.9
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// slaveSendPacket
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// http://www.opencores.org/cores/usbhostslave/                 ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//
+`include "timescale.v"
+`include "usbSerialInterfaceEngine_h.v"
+`include "usbConstants_h.v"
+
+module slaveSendPacket (PID, SCTxPortCntl, SCTxPortData, SCTxPortGnt, SCTxPortRdy, SCTxPortReq, SCTxPortWEn, clk, fifoData, fifoEmpty, fifoReadEn, rst, sendPacketRdy, sendPacketWEn);
+input   [3:0] PID;
+input   SCTxPortGnt;
+input   SCTxPortRdy;
+input   clk;
+input   [7:0] fifoData;
+input   fifoEmpty;
+input   rst;
+input   sendPacketWEn;
+output  [7:0] SCTxPortCntl;
+output  [7:0] SCTxPortData;
+output  SCTxPortReq;
+output  SCTxPortWEn;
+output  fifoReadEn;
+output  sendPacketRdy;
+
+wire    [3:0] PID;
+reg     [7:0] SCTxPortCntl, next_SCTxPortCntl;
+reg     [7:0] SCTxPortData, next_SCTxPortData;
+wire    SCTxPortGnt;
+wire    SCTxPortRdy;
+reg     SCTxPortReq, next_SCTxPortReq;
+reg     SCTxPortWEn, next_SCTxPortWEn;
+wire    clk;
+wire    [7:0] fifoData;
+wire    fifoEmpty;
+reg     fifoReadEn, next_fifoReadEn;
+wire    rst;
+reg     sendPacketRdy, next_sendPacketRdy;
+wire    sendPacketWEn;
+
+// diagram signals declarations
+reg  [7:0]PIDNotPID;
+
+// BINARY ENCODED state machine: slvSndPkt
+// State codes definitions:
+`define START_SP1 4'b0000
+`define SP_WAIT_ENABLE 4'b0001
+`define SP1_WAIT_GNT 4'b0010
+`define SP_SEND_PID_WAIT_RDY 4'b0011
+`define SP_SEND_PID_FIN 4'b0100
+`define FIN_SP1 4'b0101
+`define SP_D0_D1_READ_FIFO 4'b0110
+`define SP_D0_D1_WAIT_READ_FIFO 4'b0111
+`define SP_D0_D1_FIFO_EMPTY 4'b1000
+`define SP_D0_D1_FIN 4'b1001
+`define SP_D0_D1_TERM_BYTE 4'b1010
+`define SP_NOT_DATA 4'b1011
+`define SP_D0_D1_CLR_WEN 4'b1100
+`define SP_D0_D1_CLR_REN 4'b1101
+
+reg [3:0] CurrState_slvSndPkt;
+reg [3:0] NextState_slvSndPkt;
+
+// Diagram actions (continuous assignments allowed only: assign ...)
+
+always @(PID)
+begin
+    PIDNotPID <=  { (PID ^ 4'hf), PID };
+end
+
+//--------------------------------------------------------------------
+// Machine: slvSndPkt
+//--------------------------------------------------------------------
+//----------------------------------
+// Next State Logic (combinatorial)
+//----------------------------------
+always @ (PIDNotPID or fifoData or sendPacketWEn or SCTxPortGnt or SCTxPortRdy or PID or fifoEmpty or sendPacketRdy or SCTxPortReq or SCTxPortWEn or SCTxPortData or SCTxPortCntl or fifoReadEn or CurrState_slvSndPkt)
+begin : slvSndPkt_NextState
+  NextState_slvSndPkt <= CurrState_slvSndPkt;
+  // Set default values for outputs and signals
+  next_sendPacketRdy <= sendPacketRdy;
+  next_SCTxPortReq <= SCTxPortReq;
+  next_SCTxPortWEn <= SCTxPortWEn;
+  next_SCTxPortData <= SCTxPortData;
+  next_SCTxPortCntl <= SCTxPortCntl;
+  next_fifoReadEn <= fifoReadEn;
+  case (CurrState_slvSndPkt)
+    `START_SP1:
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+    `SP_WAIT_ENABLE:
+      if (sendPacketWEn == 1'b1)	
+      begin
+        NextState_slvSndPkt <= `SP1_WAIT_GNT;
+        next_sendPacketRdy <= 1'b0;
+        next_SCTxPortReq <= 1'b1;
+      end
+    `SP1_WAIT_GNT:
+      if (SCTxPortGnt == 1'b1)	
+        NextState_slvSndPkt <= `SP_SEND_PID_WAIT_RDY;
+    `FIN_SP1:
+    begin
+      NextState_slvSndPkt <= `SP_WAIT_ENABLE;
+      next_sendPacketRdy <= 1'b1;
+      next_SCTxPortReq <= 1'b0;
+    end
+    `SP_NOT_DATA:
+      NextState_slvSndPkt <= `FIN_SP1;
+    `SP_SEND_PID_WAIT_RDY:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvSndPkt <= `SP_SEND_PID_FIN;
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= PIDNotPID;
+        next_SCTxPortCntl <= `TX_PACKET_START;
+      end
+    `SP_SEND_PID_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      if (PID == `DATA0 || PID == `DATA1)	
+        NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+      else
+        NextState_slvSndPkt <= `SP_NOT_DATA;
+    end
+    `SP_D0_D1_READ_FIFO:
+    begin
+      next_SCTxPortWEn <= 1'b1;
+      next_SCTxPortData <= fifoData;
+      next_SCTxPortCntl <= `TX_PACKET_STREAM;
+      NextState_slvSndPkt <= `SP_D0_D1_CLR_WEN;
+    end
+    `SP_D0_D1_WAIT_READ_FIFO:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_CLR_REN;
+        next_fifoReadEn <= 1'b1;
+      end
+    `SP_D0_D1_FIFO_EMPTY:
+      if (fifoEmpty == 1'b0)	
+        NextState_slvSndPkt <= `SP_D0_D1_WAIT_READ_FIFO;
+      else
+        NextState_slvSndPkt <= `SP_D0_D1_TERM_BYTE;
+    `SP_D0_D1_FIN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `FIN_SP1;
+    end
+    `SP_D0_D1_TERM_BYTE:
+      if (SCTxPortRdy == 1'b1)	
+      begin
+        NextState_slvSndPkt <= `SP_D0_D1_FIN;
+        //Last byte is not valid data,
+        //but the 'TX_PACKET_STOP' flag is required
+        //by the SIE state machine to detect end of data packet
+        next_SCTxPortWEn <= 1'b1;
+        next_SCTxPortData <= 8'h00;
+        next_SCTxPortCntl <= `TX_PACKET_STOP;
+      end
+    `SP_D0_D1_CLR_WEN:
+    begin
+      next_SCTxPortWEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_FIFO_EMPTY;
+    end
+    `SP_D0_D1_CLR_REN:
+    begin
+      next_fifoReadEn <= 1'b0;
+      NextState_slvSndPkt <= `SP_D0_D1_READ_FIFO;
+    end
+  endcase
+end
+
+//----------------------------------
+// Current State Logic (sequential)
+//----------------------------------
+always @ (posedge clk)
+begin : slvSndPkt_CurrentState
+  if (rst)	
+    CurrState_slvSndPkt <= `START_SP1;
+  else
+    CurrState_slvSndPkt <= NextState_slvSndPkt;
+end
+
+//----------------------------------
+// Registered outputs logic
+//----------------------------------
+always @ (posedge clk)
+begin : slvSndPkt_RegOutput
+  if (rst)	
+  begin
+    sendPacketRdy <= 1'b1;
+    SCTxPortReq <= 1'b0;
+    SCTxPortWEn <= 1'b0;
+    SCTxPortData <= 8'h00;
+    SCTxPortCntl <= 8'h00;
+    fifoReadEn <= 1'b0;
+  end
+  else 
+  begin
+    sendPacketRdy <= next_sendPacketRdy;
+    SCTxPortReq <= next_SCTxPortReq;
+    SCTxPortWEn <= next_SCTxPortWEn;
+    SCTxPortData <= next_SCTxPortData;
+    SCTxPortCntl <= next_SCTxPortCntl;
+    fifoReadEn <= next_fifoReadEn;
+  end
+end
+
+endmodule
\ No newline at end of file
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC5.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC5.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/updateCRC5.v	(revision 264)
@@ -0,0 +1,112 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// updateCRC5.v                                                 ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
+input   rstCRC;
+input   CRCEn;
+input   CRC5_8BitIn;
+input   [7:0] dataIn;
+input   clk;
+input   rst;
+output  [4:0] CRCResult;
+output ready;
+
+wire   rstCRC;
+wire   CRCEn;
+wire   CRC5_8BitIn;
+wire   [7:0] dataIn;
+wire   clk;
+wire   rst;
+reg    [4:0] CRCResult;
+reg ready;
+
+reg doUpdateCRC;
+reg [7:0] data;
+reg [3:0] loopEnd;
+reg [3:0] i;
+
+always @(posedge clk)
+begin
+  if (rst == 1'b1 || rstCRC == 1'b1) begin
+    doUpdateCRC <= 1'b0;
+    i <= 4'h0;
+    CRCResult <= 5'h1f;
+    ready <= 1'b1;
+  end
+  else
+  begin
+    if (doUpdateCRC == 1'b0) begin
+      if (CRCEn == 1'b1) begin
+        ready <= 1'b0;
+        doUpdateCRC <= 1'b1;
+        data <= dataIn;
+        if (CRC5_8BitIn == 1'b1) begin
+          loopEnd <= 4'h7; 
+        end
+        else begin
+          loopEnd <= 4'h2;
+        end
+      end
+    end
+    else begin
+      i <= i + 1'b1;
+      if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
+        CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
+      end
+      else begin
+        CRCResult <= {1'b0, CRCResult[4:1]};
+      end
+      data <= {1'b0, data[7:1]};
+      if (i == loopEnd) begin
+        doUpdateCRC <= 1'b0; 
+        i <= 4'h0;
+        ready <= 1'b1;
+      end
+    end
+  end
+end
+    
+
+endmodule
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceAlteraTop.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceAlteraTop.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbDeviceAlteraTop.v	(revision 264)
@@ -0,0 +1,179 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbDeviceAlteraTop.v                                                 ////
+////                                                              ////
+//// This file is part of the spiMaster opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Top level module for Altera FPGA and NXP ISP1105 USB PHY.
+//// Specifically it targets the Base2Designs Altera Development board.
+//// Instantiates a PLL so that the lock signal can be used
+//// to reset the logic, and ties unused control signals
+//// to the off or disabled state
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+
+module usbDeviceAlteraTop (
+
+	//
+	// Global signals
+	//
+		clk,
+
+	//
+	// SDRAM
+	//
+	mc_addr,
+	mc_ba,
+	mc_dqm,
+	mc_we_,
+	mc_cas_,
+	mc_ras_,
+	mc_cke_,
+	sdram_cs,
+	sdram_clk,
+
+  //
+  // SPI bus
+  //
+  spiClk,
+  spiMasterDataOut,
+  spiCS_n,
+
+
+  //
+  // USB host
+  //
+  usbHostOE_n,
+
+  //
+  // USB slave
+  //
+  usbSlaveVP,
+  usbSlaveVM,
+  usbSlaveOE_n,
+  usbDPlusPullup,
+  vBusDetect
+);
+	//
+	// Global signals
+	//
+	input	clk;
+
+	//
+	// SDRAM
+	//
+	output	[11:0]	mc_addr;
+	output	[1:0]	mc_ba;
+	output	[3:0]	mc_dqm;
+	output		mc_we_;
+	output		mc_cas_;
+	output		mc_ras_;
+	output		mc_cke_;
+	output		sdram_cs;
+	output		sdram_clk;
+
+  //
+  // SPI bus
+  //
+  output spiClk;
+  output spiMasterDataOut;
+  output spiCS_n;
+
+  //
+  // USB host
+  //
+  output usbHostOE_n;
+
+  //
+  // USB slave
+  //
+  inout usbSlaveVP;
+  inout usbSlaveVM;
+  output usbSlaveOE_n;
+  output usbDPlusPullup;
+  input vBusDetect;
+
+//local wires and regs
+reg [1:0] rstReg;
+wire rst;
+wire pll_locked;
+
+assign mc_addr = {12{1'b0}};
+assign mc_ba = 2'b00;
+assign mc_dqm = 4'h0;
+assign mc_we_ = 1'b1;
+assign mc_cas_ = 1'b1;
+assign mc_ras_ = 1'b1;
+assign mc_cke_ = 1'b1;
+assign sdram_cs = 1'b1;
+assign sdram_clk = 1'b1;
+assign spiClk = 1'b0;
+assign spiMasterDataOut = 1'b0;
+assign spiCS_n = 1'b1;
+assign usbHostOE_n = 1'b1;
+
+pll_48MHz	pll_48MHz_inst (
+	.inclk0 ( clk ),
+	.locked( pll_locked)
+	);
+
+//generate sync reset from pll lock signal
+always @(posedge clk) begin
+  rstReg[1:0] <= {rstReg[0], ~pll_locked};
+end
+assign rst = rstReg[1];
+
+
+usbDevice u_usbDevice (
+  .clk(clk),
+  .rst(rst),
+  .usbSlaveVP_in(usbSlaveVP_in),
+  .usbSlaveVM_in(usbSlaveVM_in),
+  .usbSlaveVP_out(usbSlaveVP_out),
+  .usbSlaveVM_out(usbSlaveVM_out),
+  .usbSlaveOE_n(usbSlaveOE_n),
+  .usbDPlusPullup(usbDPlusPullup),
+  .vBusDetect(vBusDetect)
+);
+
+
+assign {usbSlaveVP_in, usbSlaveVM_in} = {usbSlaveVP, usbSlaveVM};
+assign {usbSlaveVP, usbSlaveVM} = (usbSlaveOE_n == 1'b0) ? {usbSlaveVP_out, usbSlaveVM_out} : 2'bzz;
+
+endmodule
+
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlaveReg_define.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlaveReg_define.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbHostSlaveReg_define.v	(revision 264)
@@ -0,0 +1,78 @@
+// ------------------------------ usbHostSlaveReg_define.v ----------------------------
+`include "wishBoneBus_h.v"
+`include "usbHostSlave_h.v"
+
+
+
+`define RA_EP0_CONTROL_REG              `SCREG_BASE+`ENDPOINT_CONTROL_REG
+`define RA_EP0_STATUS_REG               `SCREG_BASE+`ENDPOINT_STATUS_REG
+`define RA_EP0_TRANSTYPE_STATUS_REG     `SCREG_BASE+`ENDPOINT_TRANSTYPE_STATUS_REG
+`define RA_EP0_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NAK_TRANSTYPE_STATUS_REG
+`define RA_EP1_CONTROL_REG              `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_CONTROL_REG
+`define RA_EP1_STATUS_REG               `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_STATUS_REG
+`define RA_EP1_TRANSTYPE_STATUS_REG     `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`ENDPOINT_TRANSTYPE_STATUS_REG
+`define RA_EP1_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+`NUM_OF_REGISTERS_PER_ENDPOINT+`NAK_TRANSTYPE_STATUS_REG
+`define RA_EP2_CONTROL_REG              `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_CONTROL_REG
+`define RA_EP2_STATUS_REG               `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`ENDPOINT_STATUS_REG
+`define RA_EP2_TRANSTYPE_STATUS_REG     `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)`+`ENDPOINT_TRANSTYPE_STATUS_REG
+`define RA_EP2_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*2)+`NAK_TRANSTYPE_STATUS_REG
+`define RA_EP3_CONTROL_REG              `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_CONTROL_REG
+`define RA_EP3_STATUS_REG               `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_STATUS_REG
+`define RA_EP3_TRANSTYPE_STATUS_REG     `SCREG_BASE+(NUM_OF_REGISTERS_PER_ENDPOINT*3)+`ENDPOINT_TRANSTYPE_STATUS_REG
+`define RA_EP3_NAK_TRANSTYPE_STATUS_REG `SCREG_BASE+(`NUM_OF_REGISTERS_PER_ENDPOINT*3)+`NAK_TRANSTYPE_STATUS_REG
+`define RA_SC_CONTROL_REG               `SCREG_BASE+`SC_CONTROL_REG
+`define RA_SC_LINE_STATUS_REG           `SCREG_BASE+`SC_LINE_STATUS_REG
+`define RA_SC_INTERRUPT_STATUS_REG      `SCREG_BASE+`SC_INTERRUPT_STATUS_REG
+`define RA_SC_INTERRUPT_MASK_REG        `SCREG_BASE+`SC_INTERRUPT_MASK_REG
+`define RA_SC_ADDRESS                   `SCREG_BASE+`SC_ADDRESS
+`define RA_SC_FRAME_NUM_MSP             `SCREG_BASE+`SC_FRAME_NUM_MSP
+`define RA_SC_FRAME_NUM_LSP             `SCREG_BASE+`SC_FRAME_NUM_LSP
+
+`define RA_EP0_RX_FIFO_DATA_REG         `EP0_RX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP0_RX_FIFO_STATUS_REG       `EP0_RX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP0_RX_FIFO_DATA_COUNT_MSB   `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP0_RX_FIFO_DATA_COUNT_LSB   `EP0_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP0_RX_FIFO_CONTROL_REG      `EP0_RX_FIFO_BASE+`FIFO_CONTROL_REG
+`define RA_EP0_TX_FIFO_DATA_REG         `EP0_TX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP0_TX_FIFO_STATUS_REG       `EP0_TX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP0_TX_FIFO_DATA_COUNT_MSB   `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP0_TX_FIFO_DATA_COUNT_LSB   `EP0_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP0_TX_FIFO_CONTROL_REG      `EP0_TX_FIFO_BASE+`FIFO_CONTROL_REG
+
+`define RA_EP1_RX_FIFO_DATA_REG         `EP1_RX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP1_RX_FIFO_STATUS_REG       `EP1_RX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP1_RX_FIFO_DATA_COUNT_MSB   `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP1_RX_FIFO_DATA_COUNT_LSB   `EP1_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP1_RX_FIFO_CONTROL_REG      `EP1_RX_FIFO_BASE+`FIFO_CONTROL_REG
+`define RA_EP1_TX_FIFO_DATA_REG         `EP1_TX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP1_TX_FIFO_STATUS_REG       `EP1_TX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP1_TX_FIFO_DATA_COUNT_MSB   `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP1_TX_FIFO_DATA_COUNT_LSB   `EP1_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP1_TX_FIFO_CONTROL_REG      `EP1_TX_FIFO_BASE+`FIFO_CONTROL_REG
+
+`define RA_EP2_RX_FIFO_DATA_REG         `EP2_RX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP2_RX_FIFO_STATUS_REG       `EP2_RX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP2_RX_FIFO_DATA_COUNT_MSB   `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP2_RX_FIFO_DATA_COUNT_LSB   `EP2_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP2_RX_FIFO_CONTROL_REG      `EP2_RX_FIFO_BASE+`FIFO_CONTROL_REG
+`define RA_EP2_TX_FIFO_DATA_REG         `EP2_TX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP2_TX_FIFO_STATUS_REG       `EP2_TX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP2_TX_FIFO_DATA_COUNT_MSB   `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP2_TX_FIFO_DATA_COUNT_LSB   `EP2_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP2_TX_FIFO_CONTROL_REG      `EP2_TX_FIFO_BASE+`FIFO_CONTROL_REG
+
+`define RA_EP3_RX_FIFO_DATA_REG         `EP3_RX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP3_RX_FIFO_STATUS_REG       `EP3_RX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP3_RX_FIFO_DATA_COUNT_MSB   `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP3_RX_FIFO_DATA_COUNT_LSB   `EP3_RX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP3_RX_FIFO_CONTROL_REG      `EP3_RX_FIFO_BASE+`FIFO_CONTROL_REG
+`define RA_EP3_TX_FIFO_DATA_REG         `EP3_TX_FIFO_BASE+`FIFO_DATA_REG
+`define RA_EP3_TX_FIFO_STATUS_REG       `EP3_TX_FIFO_BASE+`FIFO_STATUS_REG
+`define RA_EP3_TX_FIFO_DATA_COUNT_MSB   `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_MSB
+`define RA_EP3_TX_FIFO_DATA_COUNT_LSB   `EP3_TX_FIFO_BASE+`FIFO_DATA_COUNT_LSB
+`define RA_EP3_TX_FIFO_CONTROL_REG      `EP3_TX_FIFO_BASE+`FIFO_CONTROL_REG
+
+`define RA_HOST_SLAVE_MODE              `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_CONTROL_REG
+`define RA_HOST_SLAVE_VERSION           `HOST_SLAVE_CONTROL_BASE+`HOST_SLAVE_VERSION_REG
+
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSerialInterfaceEngine.v	(revision 264)
@@ -0,0 +1,394 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// usbSerialInterfaceEngine.v                                   ////
+////                                                              ////
+//// This file is part of the usbhostslave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// 
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+`include "timescale.v"
+
+module usbSerialInterfaceEngine(
+  clk, rst,
+  //readUSBWireData
+  USBWireDataIn,
+  USBWireDataInTick,
+  //writeUSBWireData
+  USBWireDataOut,
+  USBWireCtrlOut,
+  USBWireDataOutTick,
+  //SIEReceiver
+  connectState,
+  //processRxBit
+  resumeDetected,
+  //processRxByte
+  RxCtrlOut, 
+  RxDataOutWEn, 
+  RxDataOut, 
+    //SIETransmitter
+  SIEPortCtrlIn,
+  SIEPortDataIn, 
+  SIEPortTxRdy, 
+  SIEPortWEn, 
+    //lineControlUpdate
+  fullSpeedPolarity,
+  fullSpeedBitRate,
+  noActivityTimeOut,
+  noActivityTimeOutEnable
+);
+
+input clk, rst;
+//readUSBWireData
+input [1:0] USBWireDataIn;
+output USBWireDataInTick;
+output noActivityTimeOut;
+input noActivityTimeOutEnable;
+
+//writeUSBWireData
+output [1:0] USBWireDataOut;
+output USBWireCtrlOut;
+output USBWireDataOutTick;
+
+//SIEReceiver
+output [1:0] connectState;
+//processRxBit
+output resumeDetected;
+//processRxByte
+output [7:0] RxCtrlOut; 
+output RxDataOutWEn; 
+output [7:0] RxDataOut; 
+//SIETransmitter
+input [7:0] SIEPortCtrlIn;
+input [7:0] SIEPortDataIn;
+output SIEPortTxRdy; 
+input SIEPortWEn;
+//lineControlUpdate
+input fullSpeedPolarity;
+input fullSpeedBitRate;
+
+wire clk, rst;
+//readUSBWireData
+wire [1:0] USBWireDataIn;
+wire USBWireDataInTick;
+//writeUSBWireData
+wire [1:0] USBWireDataOut;
+wire USBWireCtrlOut;
+wire noActivityTimeOut;
+wire USBWireDataOutTick;
+//SIEReceiver
+wire [1:0] connectState;
+//processRxBit
+wire resumeDetected;
+//processRxByte
+wire [7:0] RxCtrlOut; 
+wire RxDataOutWEn; 
+wire [7:0] RxDataOut; 
+//SIETransmitter
+wire [7:0] SIEPortCtrlIn;
+wire [7:0] SIEPortDataIn;
+wire SIEPortTxRdy; 
+wire SIEPortWEn;
+//lineControlUpdate
+wire fullSpeedPolarity;
+wire fullSpeedBitRate;
+
+//internal wiring
+wire processRxBitsWEn;
+wire processRxBitRdy;
+wire [1:0] RxWireDataFromWireRx;
+wire RxWireDataWEn;
+wire TxWireActiveDrive;
+wire [1:0] TxBitsFromArbToWire;
+wire TxCtrlFromArbToWire;
+wire USBWireRdy;
+wire USBWireWEn;
+wire USBWireReadyFromTxArb;
+wire prcTxByteCtrl;
+wire [1:0] prcTxByteData;
+wire prcTxByteGnt;
+wire prcTxByteReq;
+wire prcTxByteWEn;
+wire SIETxCtrl;
+wire [1:0] SIETxData;
+wire SIETxGnt;
+wire SIETxReq;
+wire SIETxWEn;
+wire [7:0] TxByteFromSIEToPrcTxByte;
+wire [7:0] TxCtrlFromSIEToPrcTxByte;
+wire [1:0] JBit;
+wire [1:0] KBit;
+wire processRxByteWEn;
+wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
+wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
+wire processRxByteRdy;
+//Rx CRC
+wire RxCRC16En; 
+wire [15:0] RxCRC16Result;
+wire RxCRC16UpdateRdy;
+wire RxCRC5En; 
+wire [4:0] RxCRC5Result; 
+wire RxCRC5_8Bit; 
+wire [7:0] RxCRCData; 
+wire RxRstCRC;
+wire RxCRC5UpdateRdy;
+//Tx CRC
+wire TxCRC16En; 
+wire [15:0] TxCRC16Result;
+wire TxCRC16UpdateRdy;
+wire TxCRC5En; 
+wire [4:0] TxCRC5Result; 
+wire TxCRC5_8Bit; 
+wire [7:0] TxCRCData; 
+wire TxRstCRC; 
+wire TxCRC5UpdateRdy;
+
+wire processTxByteRdy; 
+wire processTxByteWEn; 
+
+wire SIEFsRate;
+wire TxFSRateFromSIETxToPrcTxByte;
+wire prcTxByteFSRate;
+wire FSRateFromArbiterToWire;
+
+wire RxWireActive;
+
+lineControlUpdate u_lineControlUpdate
+  (.fullSpeedPolarity(fullSpeedPolarity),
+  .fullSpeedBitRate(fullSpeedBitRate),
+  .JBit(JBit),
+  .KBit(KBit) );
+
+SIEReceiver u_SIEReceiver
+  (
+  .RxWireDataIn(RxWireDataFromWireRx), 
+  .RxWireDataWEn(RxWireDataWEn), 
+  .clk(clk),
+  .connectState(connectState),
+  .rst(rst) );
+
+  
+processRxBit u_processRxBit
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .RxBitsIn(RxWireDataFromWireRx), 
+  .RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxDataOut(RxDataFromPrcRxBitToPrcRxByte), 
+  .clk(clk), 
+  .processRxBitRdy(processRxBitRdy), 
+  .processRxBitsWEn(RxWireDataWEn), 
+  .processRxByteWEn(processRxByteWEn), 
+  .resumeDetected(resumeDetected), 
+  .rst(rst),
+  .processRxByteRdy(processRxByteRdy),
+  .RxWireActive(RxWireActive)
+  );
+  
+processRxByte u_processRxByte
+  (.CRC16En(RxCRC16En), 
+  .CRC16Result(RxCRC16Result), 
+  .CRC16UpdateRdy(RxCRC16UpdateRdy),
+  .CRC5En(RxCRC5En), 
+  .CRC5Result(RxCRC5Result), 
+  .CRC5_8Bit(RxCRC5_8Bit),
+  .CRC5UpdateRdy(RxCRC5UpdateRdy),
+  .CRCData(RxCRCData), 
+  .RxByteIn(RxDataFromPrcRxBitToPrcRxByte), 
+  .RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte), 
+  .RxCtrlOut(RxCtrlOut), 
+  .RxDataOutWEn(RxDataOutWEn), 
+  .RxDataOut(RxDataOut), 
+  .clk(clk), 
+  .processRxDataInWEn(processRxByteWEn), 
+  .rst(rst), 
+  .rstCRC(RxRstCRC),
+  .processRxByteRdy(processRxByteRdy) ); 
+  
+  
+updateCRC5 RxUpdateCRC5
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC5Result), 
+  .CRCEn(RxCRC5En), 
+  .CRC5_8BitIn(RxCRC5_8Bit), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 RxUpdateCRC16
+  (.rstCRC(RxRstCRC), 
+  .CRCResult(RxCRC16Result), 
+  .CRCEn(RxCRC16En), 
+  .dataIn(RxCRCData), 
+  .ready(RxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+SIETransmitter u_SIETransmitter
+  (.CRC16En(TxCRC16En), 
+  .CRC16Result(TxCRC16Result), 
+  .CRC5En(TxCRC5En), 
+  .CRC5Result(TxCRC5Result), 
+  .CRC5_8Bit(TxCRC5_8Bit), 
+  .CRCData(TxCRCData),
+  .CRC5UpdateRdy(TxCRC5UpdateRdy),
+  .CRC16UpdateRdy(TxCRC16UpdateRdy),
+  .JBit(JBit), 
+  .KBit(KBit), 
+  .SIEPortCtrlIn(SIEPortCtrlIn),
+  .SIEPortDataIn(SIEPortDataIn), 
+  .SIEPortTxRdy(SIEPortTxRdy), 
+  .SIEPortWEn(SIEPortWEn), 
+  .TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteOut(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(SIETxCtrl), 
+  .USBWireData(SIETxData), 
+  .USBWireGnt(SIETxGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(SIETxReq), 
+  .USBWireWEn(SIETxWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst), 
+  .rstCRC(TxRstCRC),
+  .USBWireFullSpeedRate(SIEFsRate),
+  .TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
+  .fullSpeedRateIn(fullSpeedBitRate)
+  );    
+
+updateCRC5 TxUpdateCRC5
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC5Result), 
+  .CRCEn(TxCRC5En), 
+  .CRC5_8BitIn(TxCRC5_8Bit), 
+  .dataIn(TxCRCData),
+  .ready(TxCRC5UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+  
+updateCRC16 TxUpdateCRC16
+  (.rstCRC(TxRstCRC), 
+  .CRCResult(TxCRC16Result), 
+  .CRCEn(TxCRC16En), 
+  .dataIn(TxCRCData), 
+  .ready(TxCRC16UpdateRdy),
+  .clk(clk), 
+  .rst(rst) );  
+
+processTxByte u_processTxByte
+  (.JBit(JBit), 
+  .KBit(KBit), 
+  .TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte), 
+  .TxByteIn(TxByteFromSIEToPrcTxByte), 
+  .USBWireCtrl(prcTxByteCtrl), 
+  .USBWireData(prcTxByteData), 
+  .USBWireGnt(prcTxByteGnt), 
+  .USBWireRdy(USBWireReadyFromTxArb), 
+  .USBWireReq(prcTxByteReq), 
+  .USBWireWEn(prcTxByteWEn), 
+  .clk(clk), 
+  .processTxByteRdy(processTxByteRdy), 
+  .processTxByteWEn(processTxByteWEn), 
+  .rst(rst),
+  .USBWireFullSpeedRate(prcTxByteFSRate),
+  .TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
+  ); 
+  
+USBTxWireArbiter u_USBTxWireArbiter
+  (.SIETxCtrl(SIETxCtrl), 
+  .SIETxData(SIETxData), 
+  .SIETxGnt(SIETxGnt), 
+  .SIETxReq(SIETxReq), 
+  .SIETxWEn(SIETxWEn), 
+  .TxBits(TxBitsFromArbToWire), 
+  .TxCtl(TxCtrlFromArbToWire), 
+  .USBWireRdyIn(USBWireRdy), 
+  .USBWireRdyOut(USBWireReadyFromTxArb), 
+  .USBWireWEn(USBWireWEn),
+  .clk(clk), 
+  .prcTxByteCtrl(prcTxByteCtrl), 
+  .prcTxByteData(prcTxByteData), 
+  .prcTxByteGnt(prcTxByteGnt), 
+  .prcTxByteReq(prcTxByteReq), 
+  .prcTxByteWEn(prcTxByteWEn), 
+  .rst(rst),
+  .SIETxFSRate(SIEFsRate),
+  .prcTxByteFSRate(prcTxByteFSRate),
+  .TxFSRate(FSRateFromArbiterToWire)
+  ); 
+  
+writeUSBWireData u_writeUSBWireData
+  (.TxBitsIn(TxBitsFromArbToWire), 
+  .TxBitsOut(USBWireDataOut), 
+  .TxDataOutTick(USBWireDataOutTick),
+  .TxCtrlIn(TxCtrlFromArbToWire), 
+  .TxCtrlOut(USBWireCtrlOut), 
+  .USBWireRdy(USBWireRdy), 
+  .USBWireWEn(USBWireWEn),
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .fullSpeedRate(FSRateFromArbiterToWire), 
+  .clk(clk),
+  .rst(rst)
+   );  
+
+  
+  
+readUSBWireData u_readUSBWireData
+  (.RxBitsIn(USBWireDataIn), 
+  .RxDataInTick(USBWireDataInTick),
+  .RxBitsOut(RxWireDataFromWireRx), 
+  .SIERxRdyIn(processRxBitRdy), 
+  .SIERxWEn(RxWireDataWEn), 
+  .fullSpeedRate(fullSpeedBitRate), 
+  .TxWireActiveDrive(TxWireActiveDrive),
+  .clk(clk),
+  .rst(rst),
+  .noActivityTimeOut(noActivityTimeOut),
+  .RxWireActive(RxWireActive),
+  .noActivityTimeOutEnable(noActivityTimeOutEnable)
+  );
+
+
+endmodule
+
+  
+  
+
+
+
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl_h.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl_h.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/usbSlaveControl_h.v	(revision 264)
@@ -0,0 +1,86 @@
+//////////////////////////////////////////////////////////////////////
+// usbSlaveControl.v                                           
+//////////////////////////////////////////////////////////////////////
+
+`ifdef usbSlaveControl_h_vdefined
+`else
+`define usbSlaveControl_h_vdefined
+
+//endPointConstants 
+`define NUM_OF_ENDPOINTS 4
+`define NUM_OF_REGISTERS_PER_ENDPOINT 4
+`define BASE_INDEX_FOR_ENDPOINT_REGS 0
+`define ENDPOINT_CONTROL_REG 0
+`define ENDPOINT_STATUS_REG 1
+`define ENDPOINT_TRANSTYPE_STATUS_REG 2
+`define NAK_TRANSTYPE_STATUS_REG 3
+`define EP0_CTRL_REG 5'h0
+`define EP0_STS_REG 5'h1
+`define EP0_TRAN_TYPE_STS_REG 5'h2
+`define EP0_NAK_TRAN_TYPE_STS_REG 5'h3
+`define EP1_CTRL_REG 5'h4
+`define EP1_STS_REG 5'h5
+`define EP1_TRAN_TYPE_STS_REG 5'h6
+`define EP1_NAK_TRAN_TYPE_STS_REG 5'h7
+`define EP2_CTRL_REG 5'h8
+`define EP2_STS_REG 5'h9
+`define EP2_TRAN_TYPE_STS_REG 5'ha
+`define EP2_NAK_TRAN_TYPE_STS_REG 5'hb
+`define EP3_CTRL_REG 5'hc
+`define EP3_STS_REG 5'hd
+`define EP3_TRAN_TYPE_STS_REG 5'he
+`define EP3_NAK_TRAN_TYPE_STS_REG 5'hf
+
+
+//SCRegIndices 
+`define LAST_ENDP_REG = `BASE_INDEX_FOR_ENDPOINT_REGS + (`NUM_OF_REGISTERS_PER_ENDPOINT * `NUM_OF_ENDPOINTS) - 1
+`define SC_CONTROL_REG 5'h10
+`define SC_LINE_STATUS_REG 5'h11
+`define SC_INTERRUPT_STATUS_REG 5'h12
+`define SC_INTERRUPT_MASK_REG 5'h13
+`define SC_ADDRESS 5'h14
+`define SC_FRAME_NUM_MSP 5'h15
+`define SC_FRAME_NUM_LSP 5'h16
+`define SCREG_BUFFER_LEN 5'h17
+//SCRXStatusRegIndices 
+`define NAK_SET_MASK 8'h10
+`define SC_CRC_ERROR_BIT 0
+`define SC_BIT_STUFF_ERROR_BIT 1
+`define SC_RX_OVERFLOW_BIT 2
+`define SC_RX_TIME_OUT_BIT 3
+`define SC_NAK_SENT_BIT 4
+`define SC_STALL_SENT_BIT 5
+`define SC_ACK_RXED_BIT 6
+`define SC_DATA_SEQUENCE_BIT 7
+//SCEndPointControlRegIndices 
+`define ENDPOINT_ENABLE_BIT 0
+`define ENDPOINT_READY_BIT 1
+`define ENDPOINT_OUTDATA_SEQUENCE_BIT 2
+`define ENDPOINT_SEND_STALL_BIT 3
+`define ENDPOINT_ISO_ENABLE_BIT 4
+//SCMasterControlegIndices 
+`define SC_GLOBAL_ENABLE_BIT 0
+`define SC_TX_LINE_STATE_LSBIT 1
+`define SC_TX_LINE_STATE_MSBIT 2
+`define SC_DIRECT_CONTROL_BIT 3
+`define SC_FULL_SPEED_LINE_POLARITY_BIT 4
+`define SC_FULL_SPEED_LINE_RATE_BIT 5
+`define SC_CONNECT_TO_HOST_BIT 6
+//SCinterruptRegIndices 
+`define TRANS_DONE_BIT 0
+`define RESUME_INT_BIT 1
+`define RESET_EVENT_BIT 2  //Line has entered reset state or left reset state
+`define SOF_RECEIVED_BIT 3
+`define NAK_SENT_INT_BIT 4
+`define VBUS_DET_INT_BIT 5
+//TXTransactionTypes 
+`define SC_SETUP_TRANS 0
+`define SC_IN_TRANS 1
+`define SC_OUTDATA_TRANS 2
+//timeOuts 
+`define SC_RX_PACKET_TOUT 18
+
+//line status reg
+`define VBUS_PRES_BIT 2
+
+`endif //usbSlaveControl_h_vdefined  
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishboneArb.v
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishboneArb.v	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/hdl/wishboneArb.v	(revision 264)
@@ -0,0 +1,218 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// wishboneArb.v                                                 ////
+////                                                              ////
+//// This file is part of the usbHostSlave opencores effort.
+//// <http://www.opencores.org/cores//>                           ////
+////                                                              ////
+//// Module Description:                                          ////
+//// Arbitrate between 3 wishbone bus controllers
+//// Uses Round Robin access controller
+//// 
+////
+////                                                              ////
+//// To Do:                                                       ////
+//// 
+////                                                              ////
+//// Author(s):                                                   ////
+//// - Steve Fielding, sfielding@base2designs.com                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from <http://www.opencores.org/lgpl.shtml>                   ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+module wishboneArb (
+  clk,
+  rst,
+
+  addr0_i,
+  data0_i,
+  stb0_i,
+  we0_i,
+  req0,
+  gnt0,
+
+  addr1_i,
+  data1_i,
+  stb1_i,
+  we1_i,
+  req1,
+  gnt1,
+
+  addr2_i,
+  data2_i,
+  stb2_i,
+  we2_i,
+  req2,
+  gnt2,
+
+
+  addr_o,
+  data_o,
+  stb_o,
+  we_o
+);
+
+input clk;
+input rst;
+
+input [7:0] addr0_i;
+input [7:0] data0_i;
+input stb0_i;
+input we0_i;
+input req0;
+output gnt0;
+reg gnt0;
+
+input [7:0] addr1_i;
+input [7:0] data1_i;
+input stb1_i;
+input we1_i;
+input req1;
+output gnt1;
+reg gnt1;
+
+input [7:0] addr2_i;
+input [7:0] data2_i;
+input stb2_i;
+input we2_i;
+input req2;
+output gnt2;
+reg gnt2;
+
+
+output [7:0] addr_o;
+reg [7:0] addr_o;
+output [7:0] data_o;
+reg [7:0] data_o;
+output stb_o;
+reg stb_o;
+output we_o;
+reg we_o;
+
+//local wires and regs
+reg [1:0] muxSel;
+reg [2:0] arbSt;
+
+`define REQ_0 3'b000
+`define REQ_1 3'b001
+`define REQ_2 3'b010
+`define GNT_0 3'b011
+`define GNT_1 3'b100
+`define GNT_2 3'b101
+
+
+//arb
+always @(posedge clk) begin
+  if (rst == 1'b1) begin
+    gnt0 <= 1'b0;
+    gnt1 <= 1'b0;
+    gnt2 <= 1'b0;
+    muxSel <= 2'b00;
+    arbSt <= `REQ_0;
+  end
+  else begin
+    case (arbSt)
+      `REQ_0: begin
+        if (req0 == 1'b1)
+          arbSt <= `GNT_0;
+        else
+          arbSt <= `REQ_1;
+      end
+      `REQ_1: begin
+        if (req1 == 1'b1)
+          arbSt <= `GNT_1;
+        else
+          arbSt <= `REQ_2;
+      end
+      `REQ_2: begin
+        if (req2 == 1'b1)
+          arbSt <= `GNT_2;
+        else
+          arbSt <= `REQ_0;
+      end
+      `GNT_0: begin
+        gnt0 <= 1'b1;
+        muxSel <= 2'b00;
+        if (req0 == 1'b0) begin
+          arbSt <= `REQ_1;
+          gnt0 <= 1'b0;
+        end
+      end
+      `GNT_1: begin
+        gnt1 <= 1'b1;
+        muxSel <= 2'b01;
+        if (req1 == 1'b0) begin
+          arbSt <= `REQ_2;
+          gnt1 <= 1'b0;
+        end
+      end
+      `GNT_2: begin
+        gnt2 <= 1'b1;
+        muxSel <= 2'b10;
+        if (req2 == 1'b0) begin
+          arbSt <= `REQ_0;
+          gnt2 <= 1'b0;
+        end
+      end
+    endcase
+  end
+end
+
+
+//mux
+always @(*) begin
+  case (muxSel)
+    2'b00: begin
+      addr_o <= addr0_i;
+      data_o <= data0_i;
+      stb_o <= stb0_i;
+      we_o <= we0_i;
+    end
+    2'b01: begin
+      addr_o <= addr1_i;
+      data_o <= data1_i;
+      stb_o <= stb1_i;
+      we_o <= we1_i;
+    end
+    2'b10: begin
+      addr_o <= addr2_i;
+      data_o <= data2_i;
+      stb_o <= stb2_i;
+      we_o <= we2_i;
+    end
+    default: begin
+      addr_o <= addr0_i;
+      data_o <= data0_i;
+      stb_o <= stb0_i;
+      we_o <= we0_i;
+    end
+  endcase
+end
+
+
+endmodule
+
Index: common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/usbDeviceActelTop.prj
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/usbDeviceActelTop.prj	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/Actel/usbDeviceActelTop/usbDeviceActelTop.prj	(revision 264)
@@ -0,0 +1,504 @@
+KEY LIBERO "8.3"
+KEY CAPTURE "8.3.0.22"
+KEY DEFAULT_IMPORT_LOC "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\RTL"
+KEY DEFAULT_OPEN_LOC ""
+KEY HDLTechnology "VERILOG"
+KEY VendorTechnology_Family "IGLOO"
+KEY VendorTechnology_Die "IS6X6M2LP"
+KEY VendorTechnology_Package "fg256"
+KEY ProjectLocation "C:\datasheets\Opencores\usbHostSlave_new\usbhostslave\usbDevice\syn\Actel\usbDeviceActelTop"
+KEY SimulationType "VERILOG"
+KEY Vendor "Actel"
+KEY ActiveRoot "usbDeviceActelTop::work"
+LIST REVISIONS
+VALUE="Impl1",NUM=1
+CURREV=1
+ENDLIST
+LIST FileManager
+VALUE "<project>\constraint\usbDeviceActelTop.pdc,pdc"
+STATE="utd"
+TIME="1207237677"
+SIZE="6506"
+ENDFILE
+VALUE "<project>\designer\impl1\usbDevice.adb,adb"
+STATE="ood"
+TIME="1219427579"
+SIZE="1078784"
+ENDFILE
+VALUE "<project>\designer\impl1\usbDeviceActelTop.adb,adb"
+STATE="utd"
+TIME="1219440016"
+SIZE="1136640"
+ENDFILE
+VALUE "<project>\designer\impl1\usbDeviceActelTop.pdb,pdb"
+STATE="utd"
+TIME="1219441261"
+SIZE="16384"
+ENDFILE
+VALUE "<project>\designer\impl1\usbDeviceActelTop.stp,stp"
+STATE="utd"
+TIME="1219441266"
+SIZE="293941"
+ENDFILE
+VALUE "<project>\hdl\checkLineState.v,hdl"
+STATE="utd"
+TIME="1219425593"
+SIZE="6885"
+ENDFILE
+VALUE "<project>\hdl\dpMem_dc.v,hdl"
+STATE="utd"
+TIME="1219427411"
+SIZE="3862"
+ENDFILE
+VALUE "<project>\hdl\endpMux.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="8260"
+ENDFILE
+VALUE "<project>\hdl\EP0.v,hdl"
+STATE="utd"
+TIME="1219425593"
+SIZE="25833"
+ENDFILE
+VALUE "<project>\hdl\EP1Mouse.v,hdl"
+STATE="utd"
+TIME="1219425593"
+SIZE="9454"
+ENDFILE
+VALUE "<project>\hdl\fifoMux.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="6575"
+ENDFILE
+VALUE "<project>\hdl\fifoRTL.v,hdl"
+STATE="utd"
+TIME="1219427411"
+SIZE="6307"
+ENDFILE
+VALUE "<project>\hdl\hostSlaveMuxBI.v,hdl"
+STATE="utd"
+TIME="1219427436"
+SIZE="4931"
+ENDFILE
+VALUE "<project>\hdl\lineControlUpdate.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="3451"
+ENDFILE
+VALUE "<project>\hdl\processRxBit.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="15071"
+ENDFILE
+VALUE "<project>\hdl\processRxByte.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="17214"
+ENDFILE
+VALUE "<project>\hdl\processTxByte.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="15227"
+ENDFILE
+VALUE "<project>\hdl\readUSBWireData.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="10944"
+ENDFILE
+VALUE "<project>\hdl\RxFifo.v,hdl"
+STATE="utd"
+TIME="1219427411"
+SIZE="5079"
+ENDFILE
+VALUE "<project>\hdl\RxFifoBI.v,hdl"
+STATE="utd"
+TIME="1219427411"
+SIZE="5600"
+ENDFILE
+VALUE "<project>\hdl\sctxportarbiter.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="7476"
+ENDFILE
+VALUE "<project>\hdl\siereceiver.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="9992"
+ENDFILE
+VALUE "<project>\hdl\SIETransmitter.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="24223"
+ENDFILE
+VALUE "<project>\hdl\slavecontroller.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="17626"
+ENDFILE
+VALUE "<project>\hdl\slaveDirectcontrol.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="7433"
+ENDFILE
+VALUE "<project>\hdl\slaveGetpacket.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="12832"
+ENDFILE
+VALUE "<project>\hdl\slaveRxStatusMonitor.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="3985"
+ENDFILE
+VALUE "<project>\hdl\slaveSendpacket.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="9072"
+ENDFILE
+VALUE "<project>\hdl\timescale.v,hdl"
+STATE="utd"
+TIME="1219427448"
+SIZE="230"
+ENDFILE
+VALUE "<project>\hdl\TxFifo.v,hdl"
+STATE="utd"
+TIME="1219427411"
+SIZE="5002"
+ENDFILE
+VALUE "<project>\hdl\TxFifoBI.v,hdl"
+STATE="utd"
+TIME="1219427411"
+SIZE="5596"
+ENDFILE
+VALUE "<project>\hdl\updateCRC16.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="4076"
+ENDFILE
+VALUE "<project>\hdl\updateCRC5.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="4274"
+ENDFILE
+VALUE "<project>\hdl\usbConstants_h.v,hdl"
+STATE="utd"
+TIME="1219427448"
+SIZE="706"
+ENDFILE
+VALUE "<project>\hdl\usbDevice.v,hdl"
+STATE="utd"
+TIME="1219425593"
+SIZE="6821"
+ENDFILE
+VALUE "<project>\hdl\usbDeviceActelTop.v,hdl"
+STATE="utd"
+TIME="1219440128"
+SIZE="1329"
+ENDFILE
+VALUE "<project>\hdl\usbDevice_define.v,hdl"
+STATE="utd"
+TIME="1219425593"
+SIZE="1297"
+ENDFILE
+VALUE "<project>\hdl\usbHostControl_h.v,hdl"
+STATE="utd"
+TIME="1219427448"
+SIZE="2187"
+ENDFILE
+VALUE "<project>\hdl\usbHostSlaveReg_define.v,hdl"
+STATE="utd"
+TIME="1219425593"
+SIZE="5597"
+ENDFILE
+VALUE "<project>\hdl\usbHostSlave_h.v,hdl"
+STATE="utd"
+TIME="1219427448"
+SIZE="5297"
+ENDFILE
+VALUE "<project>\hdl\usbROM.v,hdl"
+STATE="utd"
+TIME="1219425593"
+SIZE="12466"
+ENDFILE
+VALUE "<project>\hdl\usbSerialInterfaceEngine.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="11255"
+ENDFILE
+VALUE "<project>\hdl\usbSerialInterfaceEngine_h.v,hdl"
+STATE="utd"
+TIME="1219427448"
+SIZE="3284"
+ENDFILE
+VALUE "<project>\hdl\usbSlave.v,hdl"
+STATE="utd"
+TIME="1219427483"
+SIZE="15345"
+ENDFILE
+VALUE "<project>\hdl\usbSlaveControl.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="15326"
+ENDFILE
+VALUE "<project>\hdl\USBSlaveControlBI.v,hdl"
+STATE="utd"
+TIME="1219427470"
+SIZE="24769"
+ENDFILE
+VALUE "<project>\hdl\usbSlaveControl_h.v,hdl"
+STATE="utd"
+TIME="1219427448"
+SIZE="2718"
+ENDFILE
+VALUE "<project>\hdl\usbTxWireArbiter.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="7513"
+ENDFILE
+VALUE "<project>\hdl\wishboneArb.v,hdl"
+STATE="utd"
+TIME="1219425593"
+SIZE="5708"
+ENDFILE
+VALUE "<project>\hdl\wishBoneBI.v,hdl"
+STATE="utd"
+TIME="1219427420"
+SIZE="8684"
+ENDFILE
+VALUE "<project>\hdl\wishBoneBus_h.v,hdl"
+STATE="utd"
+TIME="1219427448"
+SIZE="1041"
+ENDFILE
+VALUE "<project>\hdl\writeUSBWireData.v,hdl"
+STATE="utd"
+TIME="1219427458"
+SIZE="8542"
+ENDFILE
+VALUE "<project>\synthesis\usbDevice.edn,syn_edn"
+STATE="utd"
+TIME="1219427525"
+SIZE="3585871"
+ENDFILE
+VALUE "<project>\synthesis\usbDeviceActelTop.edn,syn_edn"
+STATE="utd"
+TIME="1219439810"
+SIZE="3661567"
+ENDFILE
+VALUE "<project>\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
+STATE="utd"
+TIME="1219439810"
+SIZE="376"
+ENDFILE
+VALUE "<project>\synthesis\usbDevice_sdc.sdc,syn_sdc"
+STATE="utd"
+TIME="1219427525"
+SIZE="376"
+ENDFILE
+ENDLIST
+LIST UsedFile
+ENDLIST
+LIST NewModulesInfo
+LIST "usbDevice::work"
+FILE "<project>\hdl\usbDevice.v,hdl"
+LIST ProjectState5.1
+LIST Impl1
+LiberoState=Post_Synthesis
+ideSYNTHESIS(<project>\synthesis\usbDevice.edn,syn_edn)=StateSuccess
+LIST FlowOptions
+UsePhySynth=FALSE
+UseSynth=TRUE
+ENDLIST
+Used_File_List
+VALUE "<project>\synthesis\usbDevice.edn,syn_edn"
+VALUE "<project>\synthesis\usbDevice_sdc.sdc,syn_sdc"
+VALUE "<project>\synthesis\usbDevice.v,syn_hdl"
+VALUE "<project>\phy_synthesis\usbDevice_palace.edn,palace_edn"
+VALUE "<project>\phy_synthesis\usbDevice_palace.gcf,palace_gcf"
+VALUE "<project>\phy_synthesis\usbDevice_palace.pdc,palace_pdc"
+VALUE "<project>\phy_synthesis\usbDevice_palace.sdc,palace_sdc"
+VALUE "<project>\phy_synthesis\usbDevice_palace.v,palace_hdl"
+VALUE "<project>\designer\impl1\usbDevice.adb,adb"
+VALUE "<project>\designer\impl1\usbDevice.prb,prb"
+VALUE "<project>\designer\impl1\usbDevice.stp,stp"
+VALUE "<project>\designer\impl1\usbDevice_fp\usbDevice.pro,pro"
+ENDUsed_File_List
+ENDLIST
+ENDLIST
+ENDLIST
+LIST "usbDeviceActelTop::work"
+FILE "<project>\hdl\usbDeviceActelTop.v,hdl"
+LIST ProjectState5.1
+LIST Impl1
+LiberoState=Post_Layout
+ideDESIGNER(<project>\designer\impl1\usbDeviceActelTop.adb,adb)=StateSuccess
+ideSYNTHESIS(<project>\synthesis\usbDeviceActelTop.edn,syn_edn)=StateSuccess
+LIST FlowOptions
+UsePhySynth=FALSE
+UseSynth=TRUE
+ENDLIST
+Used_File_List
+VALUE "<project>\synthesis\usbDeviceActelTop.edn,syn_edn"
+VALUE "<project>\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
+VALUE "<project>\synthesis\usbDeviceActelTop.v,syn_hdl"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.edn,palace_edn"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.gcf,palace_gcf"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.pdc,palace_pdc"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.sdc,palace_sdc"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.v,palace_hdl"
+VALUE "<project>\designer\impl1\usbDeviceActelTop.adb,adb"
+VALUE "<project>\designer\impl1\usbDeviceActelTop.prb,prb"
+VALUE "<project>\designer\impl1\usbDeviceActelTop.stp,stp"
+VALUE "<project>\designer\impl1\usbDeviceActelTop_fp\usbDeviceActelTop.pro,pro"
+ENDUsed_File_List
+ENDLIST
+ENDLIST
+ENDLIST
+ENDLIST
+LIST AssociatedStimulus
+ENDLIST
+LIST Other_Association
+ENDLIST
+LIST SimulationOptions
+UseAutomaticDoFile=true
+IncludeWaveDo=false
+Type=max
+RunTime=1000ns
+Resolution=1ps
+VsimOpt=
+EntityName=testbench
+TopInstanceName=<top>_0
+DoFileName=
+DoFileName2=wave.do
+DoFileParams=
+DisplayDUTWave=false
+LogAllSignals=false
+DumpVCD=false
+VCDFileName=power.vcd
+ENDLIST
+LIST ModelSimLibPath
+UseCustomPath=FALSE
+LibraryPath=
+ENDLIST
+LIST GlobalFlowOptions
+GenerateHDLAfterSynthesis=FALSE
+GenerateHDLAfterPhySynthesis=FALSE
+RunDRCAfterSynthesis=FALSE
+UpdateViewDrawIni=TRUE
+UpdateModelSimIni=TRUE
+NoIOMode=FALSE
+GenerateHDLFromSchematic=TRUE
+FlashProInputFile=pdb
+SmartGenCompileReport=T
+ENDLIST
+LIST PhySynthesisOptions
+ENDLIST
+LIST Profiles
+Type=CoreConfigurator
+Profile=CoreConsole
+Tool=CoreConsole v1.3 or later
+Location=coreconsole
+AdditionalParameter=
+Batch=false
+EndProfile
+Type=Synthesis
+Profile=Synplify
+Tool=Synplify
+Location=C:\Libero\Synplify\Synplify_902A2\bin\Synplify.exe
+AdditionalParameter=
+Batch=false
+EndProfile
+Type=Simulation
+Profile=ModelSim
+Tool=ModelSim
+Location=C:\Libero\Model\win32acoem\modelsim.exe
+AdditionalParameter=
+Batch=false
+EndProfile
+Type=Stimulus
+Profile=WFL
+Tool=WFL
+Location=C:\Libero\WFL\bin\syncad.exe
+AdditionalParameter=-pwflite
+Batch=false
+EndProfile
+Type=PhySynthesis
+Profile=
+Tool=
+Location=
+AdditionalParameter=
+Batch=false
+EndProfile
+Type=Program
+Profile=FlashPro
+Tool=FlashPro
+Location=C:\Libero\FlashPro\bin\FlashPro.exe
+AdditionalParameter=
+Batch=false
+EndProfile
+ENDLIST
+LIST ProjectState5.1
+LIST "usbDevice::work"
+LIST Impl1
+LiberoState=Post_Synthesis
+ideSYNTHESIS(<project>\synthesis\usbDevice.edn,syn_edn)=StateSuccess
+LIST FlowOptions
+UsePhySynth=FALSE
+UseSynth=TRUE
+ENDLIST
+Used_File_List
+VALUE "<project>\synthesis\usbDevice.edn,syn_edn"
+VALUE "<project>\synthesis\usbDevice_sdc.sdc,syn_sdc"
+VALUE "<project>\synthesis\usbDevice.v,syn_hdl"
+VALUE "<project>\phy_synthesis\usbDevice_palace.edn,palace_edn"
+VALUE "<project>\phy_synthesis\usbDevice_palace.gcf,palace_gcf"
+VALUE "<project>\phy_synthesis\usbDevice_palace.pdc,palace_pdc"
+VALUE "<project>\phy_synthesis\usbDevice_palace.sdc,palace_sdc"
+VALUE "<project>\phy_synthesis\usbDevice_palace.v,palace_hdl"
+VALUE "<project>\designer\impl1\usbDevice.adb,adb"
+VALUE "<project>\designer\impl1\usbDevice.prb,prb"
+VALUE "<project>\designer\impl1\usbDevice.stp,stp"
+VALUE "<project>\designer\impl1\usbDevice_fp\usbDevice.pro,pro"
+ENDUsed_File_List
+ENDLIST
+ENDLIST
+LIST "usbDeviceActelTop::work"
+LIST Impl1
+LiberoState=Post_Layout
+ideDESIGNER(<project>\designer\impl1\usbDeviceActelTop.adb,adb)=StateSuccess
+ideSYNTHESIS(<project>\synthesis\usbDeviceActelTop.edn,syn_edn)=StateSuccess
+LIST FlowOptions
+UsePhySynth=FALSE
+UseSynth=TRUE
+ENDLIST
+Used_File_List
+VALUE "<project>\synthesis\usbDeviceActelTop.edn,syn_edn"
+VALUE "<project>\synthesis\usbDeviceActelTop_sdc.sdc,syn_sdc"
+VALUE "<project>\synthesis\usbDeviceActelTop.v,syn_hdl"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.edn,palace_edn"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.gcf,palace_gcf"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.pdc,palace_pdc"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.sdc,palace_sdc"
+VALUE "<project>\phy_synthesis\usbDeviceActelTop_palace.v,palace_hdl"
+VALUE "<project>\designer\impl1\usbDeviceActelTop.adb,adb"
+VALUE "<project>\designer\impl1\usbDeviceActelTop.prb,prb"
+VALUE "<project>\designer\impl1\usbDeviceActelTop.stp,stp"
+VALUE "<project>\designer\impl1\usbDeviceActelTop_fp\usbDeviceActelTop.pro,pro"
+ENDUsed_File_List
+ENDLIST
+ENDLIST
+ENDLIST
+LIST ExcludePackageForSimulation
+ENDLIST
+LIST ExcludePackageForSynthesis
+ENDLIST
+LIST IncludeModuleForSimulation
+ENDLIST
+LIST CDBOrder
+ENDLIST
+LIST UserCustomizedFileList
+ENDLIST
+LIST OpenedFileList
+DESIGNFLOW:
+ACTIVE_VIEW:0
+ENDLIST
Index: common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.qsf
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.qsf	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/altera/usbDeviceAlteraTop.qsf	(revision 264)
@@ -0,0 +1,202 @@
+# Copyright (C) 1991-2006 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		cyc_or12_mini_top_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY usbDeviceAlteraTop
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "06:48:46  JUNE 20, 2007"
+set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
+
+#48MHz local oscillator
+set_global_assignment -name FMAX_REQUIREMENT "20.83 ns" -section_id clk
+set_global_assignment -name DUTY_CYCLE 50 -section_id clk
+
+set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
+
+
+set_location_assignment PIN_30 -to clk
+
+
+set_location_assignment PIN_97 -to mc_addr[0]
+set_location_assignment PIN_96 -to mc_addr[1]
+set_location_assignment PIN_90 -to mc_addr[2]
+set_location_assignment PIN_166 -to mc_addr[3]
+set_location_assignment PIN_165 -to mc_addr[4]
+set_location_assignment PIN_164 -to mc_addr[5]
+set_location_assignment PIN_162 -to mc_addr[6]
+set_location_assignment PIN_161 -to mc_addr[7]
+set_location_assignment PIN_159 -to mc_addr[8]
+set_location_assignment PIN_157 -to mc_addr[9]
+set_location_assignment PIN_100 -to mc_addr[10]
+set_location_assignment PIN_109 -to mc_addr[11]
+
+set_location_assignment PIN_106 -to mc_ba[0]
+set_location_assignment PIN_105 -to mc_ba[1]
+
+set_location_assignment PIN_113 -to mc_cas_
+set_location_assignment PIN_156 -to mc_cke_
+set_location_assignment PIN_155 -to sdram_clk
+set_location_assignment PIN_110 -to sdram_cs
+set_location_assignment PIN_116 -to mc_dqm[0]
+set_location_assignment PIN_150 -to mc_dqm[1]
+set_location_assignment PIN_88 -to mc_dqm[2]
+set_location_assignment PIN_167 -to mc_dqm[3]
+
+set_location_assignment PIN_111 -to mc_ras_
+set_location_assignment PIN_114 -to mc_we_
+
+set_location_assignment PIN_47 -to spiClk
+set_location_assignment PIN_20 -to spiMasterDataOut
+set_location_assignment PIN_44 -to spiCS_n
+
+#set_location_assignment PIN_18 -to usbHostOE_n
+#set_location_assignment PIN_8 -to usbSlaveVP
+#set_location_assignment PIN_7 -to usbSlaveVM
+#set_location_assignment PIN_9 -to usbSlaveOE_n
+#set_location_assignment PIN_13 -to usbDPlusPullup
+#set_location_assignment PIN_4 -to vBusDetect
+
+# Santa Cruz Connector
+set_location_assignment PIN_16 -to SC_P_CLK
+set_location_assignment PIN_15 -to SC_PCS_N
+set_location_assignment PIN_188 -to SC_RST_N
+set_location_assignment PIN_191 -to SC_P0
+set_location_assignment PIN_189 -to SC_P1
+set_location_assignment PIN_194 -to SC_P2
+set_location_assignment PIN_192 -to SC_P3
+set_location_assignment PIN_199 -to SC_P4
+set_location_assignment PIN_197 -to SC_P5
+set_location_assignment PIN_208 -to SC_P6
+set_location_assignment PIN_203 -to SC_P7
+set_location_assignment PIN_218 -to SC_P8
+set_location_assignment PIN_216 -to SC_P9
+set_location_assignment PIN_226 -to SC_P10
+set_location_assignment PIN_223 -to SC_P11
+set_location_assignment PIN_231 -to SC_P12
+set_location_assignment PIN_230 -to SC_P13
+set_location_assignment PIN_234 -to SC_P14
+set_location_assignment PIN_233 -to SC_P15
+set_location_assignment PIN_236 -to SC_P16
+set_location_assignment PIN_237 -to SC_P17
+set_location_assignment PIN_238 -to SC_P18
+set_location_assignment PIN_5 -to SC_P19
+set_location_assignment PIN_4 -to SC_P20
+set_location_assignment PIN_6 -to SC_P21
+set_location_assignment PIN_7 -to SC_P22
+set_location_assignment PIN_8 -to SC_P23
+set_location_assignment PIN_9 -to SC_P24
+set_location_assignment PIN_11 -to SC_P25
+set_location_assignment PIN_13 -to SC_P26
+set_location_assignment PIN_14 -to SC_P27
+set_location_assignment PIN_18 -to SC_P28
+set_location_assignment PIN_184 -to SC_P29
+set_location_assignment PIN_185 -to SC_P30
+set_location_assignment PIN_186 -to SC_P31
+set_location_assignment PIN_187 -to SC_P32
+set_location_assignment PIN_195 -to SC_P33
+set_location_assignment PIN_200 -to SC_P34
+set_location_assignment PIN_214 -to SC_P35
+set_location_assignment PIN_222 -to SC_P36
+set_location_assignment PIN_228 -to SC_P37
+set_location_assignment PIN_232 -to SC_P38
+set_location_assignment PIN_235 -to SC_P39
+
+
+
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+
+
+
+
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 1000
+
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
+
+
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_instance_assignment -name CLOCK_SETTINGS clk -to clk
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
+
+set_global_assignment -name USER_LIBRARIES "..\\..\\..\\rtl\\include;..\\..\\rtl"
+
+set_global_assignment -name VERILOG_FILE ../../../RTL/wrapper/usbSlave.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/USBSlaveControlBI.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/endpMux.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/fifoMux.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/sctxportarbiter.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slavecontroller.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveDirectcontrol.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveGetpacket.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveRxStatusMonitor.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/slaveSendpacket.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/slaveController/usbSlaveControl.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/writeUSBWireData.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/lineControlUpdate.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processRxBit.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processRxByte.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/processTxByte.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/readUSBWireData.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/siereceiver.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/SIETransmitter.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/updateCRC5.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/updateCRC16.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/serialInterfaceEngine/usbTxWireArbiter.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/hostSlaveMux/hostSlaveMuxBI.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/hostSlaveMux/hostSlaveMux.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/busInterface/wishBoneBI.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/TxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/dpMem_dc.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/fifoRTL.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/RxFifo.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/RxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../../../RTL/buffers/TxFifo.v
+set_global_assignment -name VERILOG_FILE ../../RTL/wishboneArb.v
+set_global_assignment -name VERILOG_FILE ../../RTL/checkLineState.v
+set_global_assignment -name VERILOG_FILE ../../RTL/EP0.v
+set_global_assignment -name VERILOG_FILE ../../RTL/EP1Mouse.v
+set_global_assignment -name VERILOG_FILE ../../RTL/pll_48MHz.v
+set_global_assignment -name VERILOG_FILE ../../RTL/usbDevice.v
+set_global_assignment -name VERILOG_FILE ../../RTL/usbDevice_define.v
+set_global_assignment -name VERILOG_FILE ../../RTL/usbDeviceAlteraTop.v
+set_global_assignment -name VERILOG_FILE ../../RTL/usbHostSlaveReg_define.v
+set_global_assignment -name VERILOG_FILE ../../RTL/usbROM.v
+set_global_assignment -name SDC_FILE usbDeviceAlteraTop.sdc
Index: common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx_arwz.ucf
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx_arwz.ucf	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/syn/xilinx/usbDeviceXilinxTop/pll_48MHz_xilinx_arwz.ucf	(revision 264)
@@ -0,0 +1,17 @@
+# Generated by Xilinx Architecture Wizard
+# --- UCF Template Only ---
+# Cut and paste these attributes into the project's UCF file, if desired
+INST DCM_SP_INST CLK_FEEDBACK = 1X;
+INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
+INST DCM_SP_INST CLKFX_DIVIDE = 1;
+INST DCM_SP_INST CLKFX_MULTIPLY = 4;
+INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
+INST DCM_SP_INST CLKIN_PERIOD = 20.833;
+INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
+INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
+INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
+INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
+INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
+INST DCM_SP_INST FACTORY_JF = C080;
+INST DCM_SP_INST PHASE_SHIFT = 0;
+INST DCM_SP_INST STARTUP_WAIT = FALSE;
Index: common/components/usbhostslave/trunk/usbDevice/updateRTL.bat
===================================================================
--- common/components/usbhostslave/trunk/usbDevice/updateRTL.bat	(nonexistent)
+++ common/components/usbhostslave/trunk/usbDevice/updateRTL.bat	(revision 264)
@@ -0,0 +1,5 @@
+perl verilogCopy.pl -i Aldec/design0/compile/EP0.v -o RTL/EP0.v
+perl verilogCopy.pl -i Aldec/design0/compile/checkLineState.v -o RTL/checkLineState.v
+perl verilogCopy.pl -i Aldec/design0/compile/EP1Mouse.v -o RTL/EP1Mouse.v
+pause
+
Index: common/components/usbhostslave/web_uploads/driver/readme.txt
===================================================================
--- common/components/usbhostslave/web_uploads/driver/readme.txt	(nonexistent)
+++ common/components/usbhostslave/web_uploads/driver/readme.txt	(revision 264)
@@ -0,0 +1,4 @@
+Start with a new 2.6.28 kernel, copy the diff file to drivers/usb/ and run "patch -p0 < ohs900_2.6.28.diff"
+The only thing you have to edit after you applyed the patch is the ohs900.h file, 
+and enter the base address where the ip core lays in the addressspace. 
+It can be found at the beginning of this file
Index: common/components/usbhostslave/web_uploads/ohs900.zip
===================================================================
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